text
stringlengths 992
1.04M
|
|---|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: five_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module five_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/five_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/five_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2021 by Krzysztof Bieganski.
// SPDX-License-Identifier: CC0-1.0
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package config_pkg;
typedef struct packed {
int UPPER0;
int UPPER2;
int USE_QUAD0;
int USE_QUAD1;
int USE_QUAD2;
} config_struct;
endpackage : config_pkg
module t;
import config_pkg::*;
struct_submodule #(.MY_CONFIG('{
UPPER0: 10,
UPPER2: 20,
USE_QUAD0: 4,
USE_QUAD1: 5,
USE_QUAD2: 6
})) a_submodule_I ();
endmodule : t
module struct_submodule
import config_pkg::*;
#(parameter config_struct MY_CONFIG = '0);
initial begin
`checkd(MY_CONFIG.UPPER0, 10);
`checkd(MY_CONFIG.USE_QUAD0, 4);
`checkd(MY_CONFIG.USE_QUAD1, 5);
`checkd(MY_CONFIG.USE_QUAD2, 6);
`checkd(MY_CONFIG.UPPER2, 20);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : struct_submodule
|
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 11:41:13 05/10/2011
// Description: log image to ppm file
//-----------------------------------------------
module hdmi_out
(
input hdmi_clk,
input hdmi_vs,
input hdmi_de,
input [31:0] hdmi_data
);
//-----------------------------------------------
integer fm1=0;
reg [7:0]vsc=8'h0;
reg vse=1;
//-----------------------------------------------
initial
begin
//fm1 = $fopen("outA.ppm","wb");
end
//-----------------------------------------------
always @(posedge hdmi_clk)
begin
vse<=hdmi_vs;
if((hdmi_vs==1'b0)&&(vse==1'b1))
begin
$fclose(fm1);
//$stop;
end
if((hdmi_vs==1'b1)&&(vse==1'b0))
begin
fm1 = $fopen({"out/out_",vsc[5:0]/10+8'h30,vsc[5:0]%10+8'h30,".ppm"},"wb");
$display("out%d.ppm saved",vsc);
$fwrite(fm1,"P6%c64 64%c255\n",10,10);
vsc<=vsc+1;
end else
begin
if(hdmi_de)
begin
//just for good debugging
$fwrite(fm1,"%c",{hdmi_data[23:16]});
$fwrite(fm1,"%c",{hdmi_data[15:8]});
$fwrite(fm1,"%c",{hdmi_data[7:0]});
end
end
end
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
//
`define bsg_mem_1rw_sync_macro(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rw_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( {``bits``{1'b0}} ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 ) \
,.TEST ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( {``bits``{1'b0}} ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 )); \
end
module bsg_mem_1rw_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
//, parameter addr_width_lp=$clog2(els_p)
// whether to substitute a 1r1w
, parameter substitute_1r1w_p=1)
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
`bsg_mem_1rw_sync_macro(4096,48,12,8) else
`bsg_mem_1rw_sync_macro(2048,32,11,8) else
`bsg_mem_1rw_sync_macro(1024,32,10,4) else
`bsg_mem_1rw_sync_macro(1024,46,10,4) else
`bsg_mem_1rw_sync_macro(256,128,8,4) else
`bsg_mem_1rf_sync_macro(128,76,7,2) else
`bsg_mem_1rf_sync_macro(128,74,7,2) else
`bsg_mem_1rf_sync_macro(128,73,7,2) else
`bsg_mem_1rf_sync_macro(128,72,7,2) else
`bsg_mem_1rf_sync_macro(128,71,7,2) else
`bsg_mem_1rf_sync_macro(128,70,7,2) else
`bsg_mem_1rf_sync_macro(128,69,7,2) else
`bsg_mem_1rf_sync_macro(128,68,7,2) else
`bsg_mem_1rf_sync_macro(128,67,7,2) else
`bsg_mem_1rf_sync_macro(128,66,7,2) else
`bsg_mem_1rf_sync_macro(128,65,7,2) else
`bsg_mem_1rf_sync_macro(128,64,7,2) else
`bsg_mem_1rf_sync_macro(128,63,7,2) else
`bsg_mem_1rf_sync_macro(128,62,7,2) else
`bsg_mem_1rf_sync_macro(128,61,7,2) else
begin : z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1rw synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(0)
) mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (v_i & w_i)
,.w_addr_i (addr_i)
,.w_data_i (data_i)
,.r_addr_i (addr_i)
,.r_v_i (v_i & ~w_i)
,.r_data_o (data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i)
data_o <= data_lo;
end // block: subst
else
begin: notmacro
bsg_mem_1rw_sync_synth
# (.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
end // block: notmacro
end // block: z
// synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync)
|
// -------------------------------------------------------------------------
//Reed-Solomon decoder
//Copyright (C) Wed Apr 28 11:28:40 2004
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rs_decoder_2(x, error, with_error, enable, valid, k, clk, clrn);
input enable, clk, clrn;
input [8:0] k, x;
output [8:0] error;
wire [8:0] error;
output with_error, valid;
reg valid;
wire with_error;
wire [8:0] s0, s1, s2, s3, s4, s5, s6, s7;
wire [8:0] lambda, omega, alpha;
reg [3:0] count;
reg [8:0] phase;
wire [8:0] D0, D1, DI;
// reg [8:0] D, D2;
wire [8:0] D, D2;
reg [8:0] u, length0, length2;
wire [8:0] length1, length3;
reg syn_enable, syn_init, syn_shift, berl_enable;
reg chien_search, chien_load, shorten;
always @ (chien_search or shorten)
valid = chien_search & ~shorten;
wire bit1;
assign bit1 = syn_shift&phase[0];
rsdec_syn x0 (s0, s1, s2, s3, s4, s5, s6, s7, u, syn_enable, bit1, syn_init, clk, clrn);
rsdec_berl x1 (lambda, omega, s0, s7, s6, s5, s4, s3, s2, s1, D0, D2, count, phase[0], phase[8], berl_enable, clk, clrn);
rsdec_chien x2 (error, alpha, lambda, omega, D1, DI, chien_search, chien_load, shorten, clk, clrn);
inverse x3 (DI, D);
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
syn_enable <= 0;
syn_shift <= 0;
berl_enable <= 0;
chien_search <= 1;
chien_load <= 0;
length0 <= 0;
length2 <= 511 - k;
count <= -1;
phase <= 1;
u <= 0;
shorten <= 1;
syn_init <= 0;
end
else
begin
if (enable & ~syn_enable & ~syn_shift)
begin
syn_enable <= 1;
syn_init <= 1;
end
else if (syn_enable)
begin
length0 <= length1;
syn_init <= 0;
if (length1 == k)
begin
syn_enable <= 0;
syn_shift <= 1;
berl_enable <= 1;
end
end
else if (berl_enable & with_error)
begin
if (phase[0])
begin
count <= count + 1;
if (count == 7)
begin
syn_shift <= 0;
length0 <= 0;
chien_load <= 1;
length2 <= length0;
end
end
phase <= {phase[7:0], phase[8]};
end
else if (berl_enable & ~with_error)
if (&count)
begin
syn_shift <= 0;
length0 <= 0;
berl_enable <= 0;
end
else
phase <= {phase[7:0], phase[8]};
else if (chien_load & phase[8])
begin
berl_enable <= 0;
chien_load <= 0;
chien_search <= 1;
count <= -1;
phase <= 1;
end
else if (chien_search)// | shorten)
begin
length2 <= length3;
if (length3 == 0)
chien_search <= 0;
end
else if (enable) u <= x;
else if (shorten == 1 && length2 == 0)
shorten <= 0;
end
end
// always @ (chien_search or D0 or D1)
// if (chien_search) D = D1;
// else D = D0;
assign D = chien_search ? D1 : D0;
// always @ (DI or alpha or chien_load)
// if (chien_load) D2 = alpha;
// else D2 = DI;
assign D2 = chien_load ? alpha : DI;
assign length1 = length0 + 1;
assign length3 = length2 - 1;
// always @ (syn_shift or s0 or s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8 or s9 or s10 or s11)
// if (syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 | s8 | s9 | s10 | s11)!= 0)
// with_error = 1;
// else with_error = 0;
wire temp;
assign temp = syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 );
assign with_error = temp != 0 ? 1'b1 : 1'b0;
endmodule
// -------------------------------------------------------------------------
//The inverse lookup table for Galois field
//Copyright (C) Wed Apr 28 11:17:28 2004
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module inverse(y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
case (x) // synopsys full_case parallel_case
1: y = 1; // 0 -> 511
2: y = 264; // 1 -> 510
4: y = 132; // 2 -> 509
8: y = 66; // 3 -> 508
16: y = 33; // 4 -> 507
32: y = 280; // 5 -> 506
64: y = 140; // 6 -> 505
128: y = 70; // 7 -> 504
256: y = 35; // 8 -> 503
17: y = 281; // 9 -> 502
34: y = 388; // 10 -> 501
68: y = 194; // 11 -> 500
136: y = 97; // 12 -> 499
272: y = 312; // 13 -> 498
49: y = 156; // 14 -> 497
98: y = 78; // 15 -> 496
196: y = 39; // 16 -> 495
392: y = 283; // 17 -> 494
257: y = 389; // 18 -> 493
19: y = 458; // 19 -> 492
38: y = 229; // 20 -> 491
76: y = 378; // 21 -> 490
152: y = 189; // 22 -> 489
304: y = 342; // 23 -> 488
113: y = 171; // 24 -> 487
226: y = 349; // 25 -> 486
452: y = 422; // 26 -> 485
409: y = 211; // 27 -> 484
291: y = 353; // 28 -> 483
87: y = 440; // 29 -> 482
174: y = 220; // 30 -> 481
348: y = 110; // 31 -> 480
169: y = 55; // 32 -> 479
338: y = 275; // 33 -> 478
181: y = 385; // 34 -> 477
362: y = 456; // 35 -> 476
197: y = 228; // 36 -> 475
394: y = 114; // 37 -> 474
261: y = 57; // 38 -> 473
27: y = 276; // 39 -> 472
54: y = 138; // 40 -> 471
108: y = 69; // 41 -> 470
216: y = 298; // 42 -> 469
432: y = 149; // 43 -> 468
369: y = 322; // 44 -> 467
243: y = 161; // 45 -> 466
486: y = 344; // 46 -> 465
477: y = 172; // 47 -> 464
427: y = 86; // 48 -> 463
327: y = 43; // 49 -> 462
159: y = 285; // 50 -> 461
318: y = 390; // 51 -> 460
109: y = 195; // 52 -> 459
218: y = 361; // 53 -> 458
436: y = 444; // 54 -> 457
377: y = 222; // 55 -> 456
227: y = 111; // 56 -> 455
454: y = 319; // 57 -> 454
413: y = 407; // 58 -> 453
299: y = 451; // 59 -> 452
71: y = 489; // 60 -> 451
142: y = 508; // 61 -> 450
284: y = 254; // 62 -> 449
41: y = 127; // 63 -> 448
82: y = 311; // 64 -> 447
164: y = 403; // 65 -> 446
328: y = 449; // 66 -> 445
129: y = 488; // 67 -> 444
258: y = 244; // 68 -> 443
21: y = 122; // 69 -> 442
42: y = 61; // 70 -> 441
84: y = 278; // 71 -> 440
168: y = 139; // 72 -> 439
336: y = 333; // 73 -> 438
177: y = 430; // 74 -> 437
354: y = 215; // 75 -> 436
213: y = 355; // 76 -> 435
426: y = 441; // 77 -> 434
325: y = 468; // 78 -> 433
155: y = 234; // 79 -> 432
310: y = 117; // 80 -> 431
125: y = 306; // 81 -> 430
250: y = 153; // 82 -> 429
500: y = 324; // 83 -> 428
505: y = 162; // 84 -> 427
483: y = 81; // 85 -> 426
471: y = 288; // 86 -> 425
447: y = 144; // 87 -> 424
367: y = 72; // 88 -> 423
207: y = 36; // 89 -> 422
414: y = 18; // 90 -> 421
301: y = 9; // 91 -> 420
75: y = 268; // 92 -> 419
150: y = 134; // 93 -> 418
300: y = 67; // 94 -> 417
73: y = 297; // 95 -> 416
146: y = 412; // 96 -> 415
292: y = 206; // 97 -> 414
89: y = 103; // 98 -> 413
178: y = 315; // 99 -> 412
356: y = 405; // 100 -> 411
217: y = 450; // 101 -> 410
434: y = 225; // 102 -> 409
373: y = 376; // 103 -> 408
251: y = 188; // 104 -> 407
502: y = 94; // 105 -> 406
509: y = 47; // 106 -> 405
491: y = 287; // 107 -> 404
455: y = 391; // 108 -> 403
415: y = 459; // 109 -> 402
303: y = 493; // 110 -> 401
79: y = 510; // 111 -> 400
158: y = 255; // 112 -> 399
316: y = 375; // 113 -> 398
105: y = 435; // 114 -> 397
210: y = 465; // 115 -> 396
420: y = 480; // 116 -> 395
345: y = 240; // 117 -> 394
163: y = 120; // 118 -> 393
326: y = 60; // 119 -> 392
157: y = 30; // 120 -> 391
314: y = 15; // 121 -> 390
101: y = 271; // 122 -> 389
202: y = 399; // 123 -> 388
404: y = 463; // 124 -> 387
313: y = 495; // 125 -> 386
99: y = 511; // 126 -> 385
198: y = 503; // 127 -> 384
396: y = 499; // 128 -> 383
265: y = 497; // 129 -> 382
3: y = 496; // 130 -> 381
6: y = 248; // 131 -> 380
12: y = 124; // 132 -> 379
24: y = 62; // 133 -> 378
48: y = 31; // 134 -> 377
96: y = 263; // 135 -> 376
192: y = 395; // 136 -> 375
384: y = 461; // 137 -> 374
273: y = 494; // 138 -> 373
51: y = 247; // 139 -> 372
102: y = 371; // 140 -> 371
204: y = 433; // 141 -> 370
408: y = 464; // 142 -> 369
289: y = 232; // 143 -> 368
83: y = 116; // 144 -> 367
166: y = 58; // 145 -> 366
332: y = 29; // 146 -> 365
137: y = 262; // 147 -> 364
274: y = 131; // 148 -> 363
53: y = 329; // 149 -> 362
106: y = 428; // 150 -> 361
212: y = 214; // 151 -> 360
424: y = 107; // 152 -> 359
321: y = 317; // 153 -> 358
147: y = 406; // 154 -> 357
294: y = 203; // 155 -> 356
93: y = 365; // 156 -> 355
186: y = 446; // 157 -> 354
372: y = 223; // 158 -> 353
249: y = 359; // 159 -> 352
498: y = 443; // 160 -> 351
501: y = 469; // 161 -> 350
507: y = 482; // 162 -> 349
487: y = 241; // 163 -> 348
479: y = 368; // 164 -> 347
431: y = 184; // 165 -> 346
335: y = 92; // 166 -> 345
143: y = 46; // 167 -> 344
286: y = 23; // 168 -> 343
45: y = 259; // 169 -> 342
90: y = 393; // 170 -> 341
180: y = 460; // 171 -> 340
360: y = 230; // 172 -> 339
193: y = 115; // 173 -> 338
386: y = 305; // 174 -> 337
277: y = 400; // 175 -> 336
59: y = 200; // 176 -> 335
118: y = 100; // 177 -> 334
236: y = 50; // 178 -> 333
472: y = 25; // 179 -> 332
417: y = 260; // 180 -> 331
339: y = 130; // 181 -> 330
183: y = 65; // 182 -> 329
366: y = 296; // 183 -> 328
205: y = 148; // 184 -> 327
410: y = 74; // 185 -> 326
293: y = 37; // 186 -> 325
91: y = 282; // 187 -> 324
182: y = 141; // 188 -> 323
364: y = 334; // 189 -> 322
201: y = 167; // 190 -> 321
402: y = 347; // 191 -> 320
309: y = 421; // 192 -> 319
123: y = 474; // 193 -> 318
246: y = 237; // 194 -> 317
492: y = 382; // 195 -> 316
457: y = 191; // 196 -> 315
387: y = 343; // 197 -> 314
279: y = 419; // 198 -> 313
63: y = 473; // 199 -> 312
126: y = 484; // 200 -> 311
252: y = 242; // 201 -> 310
504: y = 121; // 202 -> 309
481: y = 308; // 203 -> 308
467: y = 154; // 204 -> 307
439: y = 77; // 205 -> 306
383: y = 302; // 206 -> 305
239: y = 151; // 207 -> 304
478: y = 323; // 208 -> 303
429: y = 425; // 209 -> 302
331: y = 476; // 210 -> 301
135: y = 238; // 211 -> 300
270: y = 119; // 212 -> 299
13: y = 307; // 213 -> 298
26: y = 401; // 214 -> 297
52: y = 448; // 215 -> 296
104: y = 224; // 216 -> 295
208: y = 112; // 217 -> 294
416: y = 56; // 218 -> 293
337: y = 28; // 219 -> 292
179: y = 14; // 220 -> 291
358: y = 7; // 221 -> 290
221: y = 267; // 222 -> 289
442: y = 397; // 223 -> 288
357: y = 462; // 224 -> 287
219: y = 231; // 225 -> 286
438: y = 379; // 226 -> 285
381: y = 437; // 227 -> 284
235: y = 466; // 228 -> 283
470: y = 233; // 229 -> 282
445: y = 380; // 230 -> 281
363: y = 190; // 231 -> 280
199: y = 95; // 232 -> 279
398: y = 295; // 233 -> 278
269: y = 411; // 234 -> 277
11: y = 453; // 235 -> 276
22: y = 490; // 236 -> 275
44: y = 245; // 237 -> 274
88: y = 370; // 238 -> 273
176: y = 185; // 239 -> 272
352: y = 340; // 240 -> 271
209: y = 170; // 241 -> 270
418: y = 85; // 242 -> 269
341: y = 290; // 243 -> 268
187: y = 145; // 244 -> 267
374: y = 320; // 245 -> 266
253: y = 160; // 246 -> 265
506: y = 80; // 247 -> 264
485: y = 40; // 248 -> 263
475: y = 20; // 249 -> 262
423: y = 10; // 250 -> 261
351: y = 5; // 251 -> 260
175: y = 266; // 252 -> 259
350: y = 133; // 253 -> 258
173: y = 330; // 254 -> 257
346: y = 165; // 255 -> 256
165: y = 346; // 256 -> 255
330: y = 173; // 257 -> 254
133: y = 350; // 258 -> 253
266: y = 175; // 259 -> 252
5: y = 351; // 260 -> 251
10: y = 423; // 261 -> 250
20: y = 475; // 262 -> 249
40: y = 485; // 263 -> 248
80: y = 506; // 264 -> 247
160: y = 253; // 265 -> 246
320: y = 374; // 266 -> 245
145: y = 187; // 267 -> 244
290: y = 341; // 268 -> 243
85: y = 418; // 269 -> 242
170: y = 209; // 270 -> 241
340: y = 352; // 271 -> 240
185: y = 176; // 272 -> 239
370: y = 88; // 273 -> 238
245: y = 44; // 274 -> 237
490: y = 22; // 275 -> 236
453: y = 11; // 276 -> 235
411: y = 269; // 277 -> 234
295: y = 398; // 278 -> 233
95: y = 199; // 279 -> 232
190: y = 363; // 280 -> 231
380: y = 445; // 281 -> 230
233: y = 470; // 282 -> 229
466: y = 235; // 283 -> 228
437: y = 381; // 284 -> 227
379: y = 438; // 285 -> 226
231: y = 219; // 286 -> 225
462: y = 357; // 287 -> 224
397: y = 442; // 288 -> 223
267: y = 221; // 289 -> 222
7: y = 358; // 290 -> 221
14: y = 179; // 291 -> 220
28: y = 337; // 292 -> 219
56: y = 416; // 293 -> 218
112: y = 208; // 294 -> 217
224: y = 104; // 295 -> 216
448: y = 52; // 296 -> 215
401: y = 26; // 297 -> 214
307: y = 13; // 298 -> 213
119: y = 270; // 299 -> 212
238: y = 135; // 300 -> 211
476: y = 331; // 301 -> 210
425: y = 429; // 302 -> 209
323: y = 478; // 303 -> 208
151: y = 239; // 304 -> 207
302: y = 383; // 305 -> 206
77: y = 439; // 306 -> 205
154: y = 467; // 307 -> 204
308: y = 481; // 308 -> 203
121: y = 504; // 309 -> 202
242: y = 252; // 310 -> 201
484: y = 126; // 311 -> 200
473: y = 63; // 312 -> 199
419: y = 279; // 313 -> 198
343: y = 387; // 314 -> 197
191: y = 457; // 315 -> 196
382: y = 492; // 316 -> 195
237: y = 246; // 317 -> 194
474: y = 123; // 318 -> 193
421: y = 309; // 319 -> 192
347: y = 402; // 320 -> 191
167: y = 201; // 321 -> 190
334: y = 364; // 322 -> 189
141: y = 182; // 323 -> 188
282: y = 91; // 324 -> 187
37: y = 293; // 325 -> 186
74: y = 410; // 326 -> 185
148: y = 205; // 327 -> 184
296: y = 366; // 328 -> 183
65: y = 183; // 329 -> 182
130: y = 339; // 330 -> 181
260: y = 417; // 331 -> 180
25: y = 472; // 332 -> 179
50: y = 236; // 333 -> 178
100: y = 118; // 334 -> 177
200: y = 59; // 335 -> 176
400: y = 277; // 336 -> 175
305: y = 386; // 337 -> 174
115: y = 193; // 338 -> 173
230: y = 360; // 339 -> 172
460: y = 180; // 340 -> 171
393: y = 90; // 341 -> 170
259: y = 45; // 342 -> 169
23: y = 286; // 343 -> 168
46: y = 143; // 344 -> 167
92: y = 335; // 345 -> 166
184: y = 431; // 346 -> 165
368: y = 479; // 347 -> 164
241: y = 487; // 348 -> 163
482: y = 507; // 349 -> 162
469: y = 501; // 350 -> 161
443: y = 498; // 351 -> 160
359: y = 249; // 352 -> 159
223: y = 372; // 353 -> 158
446: y = 186; // 354 -> 157
365: y = 93; // 355 -> 156
203: y = 294; // 356 -> 155
406: y = 147; // 357 -> 154
317: y = 321; // 358 -> 153
107: y = 424; // 359 -> 152
214: y = 212; // 360 -> 151
428: y = 106; // 361 -> 150
329: y = 53; // 362 -> 149
131: y = 274; // 363 -> 148
262: y = 137; // 364 -> 147
29: y = 332; // 365 -> 146
58: y = 166; // 366 -> 145
116: y = 83; // 367 -> 144
232: y = 289; // 368 -> 143
464: y = 408; // 369 -> 142
433: y = 204; // 370 -> 141
371: y = 102; // 371 -> 140
247: y = 51; // 372 -> 139
494: y = 273; // 373 -> 138
461: y = 384; // 374 -> 137
395: y = 192; // 375 -> 136
263: y = 96; // 376 -> 135
31: y = 48; // 377 -> 134
62: y = 24; // 378 -> 133
124: y = 12; // 379 -> 132
248: y = 6; // 380 -> 131
496: y = 3; // 381 -> 130
497: y = 265; // 382 -> 129
499: y = 396; // 383 -> 128
503: y = 198; // 384 -> 127
511: y = 99; // 385 -> 126
495: y = 313; // 386 -> 125
463: y = 404; // 387 -> 124
399: y = 202; // 388 -> 123
271: y = 101; // 389 -> 122
15: y = 314; // 390 -> 121
30: y = 157; // 391 -> 120
60: y = 326; // 392 -> 119
120: y = 163; // 393 -> 118
240: y = 345; // 394 -> 117
480: y = 420; // 395 -> 116
465: y = 210; // 396 -> 115
435: y = 105; // 397 -> 114
375: y = 316; // 398 -> 113
255: y = 158; // 399 -> 112
510: y = 79; // 400 -> 111
493: y = 303; // 401 -> 110
459: y = 415; // 402 -> 109
391: y = 455; // 403 -> 108
287: y = 491; // 404 -> 107
47: y = 509; // 405 -> 106
94: y = 502; // 406 -> 105
188: y = 251; // 407 -> 104
376: y = 373; // 408 -> 103
225: y = 434; // 409 -> 102
450: y = 217; // 410 -> 101
405: y = 356; // 411 -> 100
315: y = 178; // 412 -> 99
103: y = 89; // 413 -> 98
206: y = 292; // 414 -> 97
412: y = 146; // 415 -> 96
297: y = 73; // 416 -> 95
67: y = 300; // 417 -> 94
134: y = 150; // 418 -> 93
268: y = 75; // 419 -> 92
9: y = 301; // 420 -> 91
18: y = 414; // 421 -> 90
36: y = 207; // 422 -> 89
72: y = 367; // 423 -> 88
144: y = 447; // 424 -> 87
288: y = 471; // 425 -> 86
81: y = 483; // 426 -> 85
162: y = 505; // 427 -> 84
324: y = 500; // 428 -> 83
153: y = 250; // 429 -> 82
306: y = 125; // 430 -> 81
117: y = 310; // 431 -> 80
234: y = 155; // 432 -> 79
468: y = 325; // 433 -> 78
441: y = 426; // 434 -> 77
355: y = 213; // 435 -> 76
215: y = 354; // 436 -> 75
430: y = 177; // 437 -> 74
333: y = 336; // 438 -> 73
139: y = 168; // 439 -> 72
278: y = 84; // 440 -> 71
61: y = 42; // 441 -> 70
122: y = 21; // 442 -> 69
244: y = 258; // 443 -> 68
488: y = 129; // 444 -> 67
449: y = 328; // 445 -> 66
403: y = 164; // 446 -> 65
311: y = 82; // 447 -> 64
127: y = 41; // 448 -> 63
254: y = 284; // 449 -> 62
508: y = 142; // 450 -> 61
489: y = 71; // 451 -> 60
451: y = 299; // 452 -> 59
407: y = 413; // 453 -> 58
319: y = 454; // 454 -> 57
111: y = 227; // 455 -> 56
222: y = 377; // 456 -> 55
444: y = 436; // 457 -> 54
361: y = 218; // 458 -> 53
195: y = 109; // 459 -> 52
390: y = 318; // 460 -> 51
285: y = 159; // 461 -> 50
43: y = 327; // 462 -> 49
86: y = 427; // 463 -> 48
172: y = 477; // 464 -> 47
344: y = 486; // 465 -> 46
161: y = 243; // 466 -> 45
322: y = 369; // 467 -> 44
149: y = 432; // 468 -> 43
298: y = 216; // 469 -> 42
69: y = 108; // 470 -> 41
138: y = 54; // 471 -> 40
276: y = 27; // 472 -> 39
57: y = 261; // 473 -> 38
114: y = 394; // 474 -> 37
228: y = 197; // 475 -> 36
456: y = 362; // 476 -> 35
385: y = 181; // 477 -> 34
275: y = 338; // 478 -> 33
55: y = 169; // 479 -> 32
110: y = 348; // 480 -> 31
220: y = 174; // 481 -> 30
440: y = 87; // 482 -> 29
353: y = 291; // 483 -> 28
211: y = 409; // 484 -> 27
422: y = 452; // 485 -> 26
349: y = 226; // 486 -> 25
171: y = 113; // 487 -> 24
342: y = 304; // 488 -> 23
189: y = 152; // 489 -> 22
378: y = 76; // 490 -> 21
229: y = 38; // 491 -> 20
458: y = 19; // 492 -> 19
389: y = 257; // 493 -> 18
283: y = 392; // 494 -> 17
39: y = 196; // 495 -> 16
78: y = 98; // 496 -> 15
156: y = 49; // 497 -> 14
312: y = 272; // 498 -> 13
97: y = 136; // 499 -> 12
194: y = 68; // 500 -> 11
388: y = 34; // 501 -> 10
281: y = 17; // 502 -> 9
35: y = 256; // 503 -> 8
70: y = 128; // 504 -> 7
140: y = 64; // 505 -> 6
280: y = 32; // 506 -> 5
33: y = 16; // 507 -> 4
66: y = 8; // 508 -> 3
132: y = 4; // 509 -> 2
264: y = 2; // 510 -> 1
endcase
endmodule
// -------------------------------------------------------------------------
//Berlekamp circuit for Reed-Solomon decoder
//Copyright (C) Wed Apr 28 11:17:23 2004
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rsdec_berl (lambda_out, omega_out, syndrome0, syndrome1, syndrome2, syndrome3, syndrome4, syndrome5, syndrome6, syndrome7,
D, DI, count, phase0, phase8, enable, clk, clrn);
input clk, clrn, enable, phase0, phase8;
input [8:0] syndrome0;
input [8:0] syndrome1;
input [8:0] syndrome2;
input [8:0] syndrome3;
input [8:0] syndrome4;
input [8:0] syndrome5;
input [8:0] syndrome6;
input [8:0] syndrome7;
input [8:0] DI;
input [3:0] count;
output [8:0] lambda_out;
output [8:0] omega_out;
reg [8:0] lambda_out;
reg [8:0] omega_out;
output [8:0] D;
reg [8:0] D;
//integer j;
reg init, delta;
reg [1:0] L;
reg [8:0] lambda0;
reg [8:0] lambda1;
reg [8:0] lambda2;
reg [8:0] lambda3;
reg [8:0] lambda4;
reg [8:0] lambda5;
reg [8:0] lambda6;
reg [8:0] lambda7;
reg [8:0] B0;
reg [8:0] B1;
reg [8:0] B2;
reg [8:0] B3;
reg [8:0] B4;
reg [8:0] B5;
reg [8:0] B6;
reg [8:0] omega0;
reg [8:0] omega1;
reg [8:0] omega2;
reg [8:0] omega3;
reg [8:0] omega4;
reg [8:0] omega5;
reg [8:0] omega6;
reg [8:0] omega7;
reg [8:0] A0;
reg [8:0] A1;
reg [8:0] A2;
reg [8:0] A3;
reg [8:0] A4;
reg [8:0] A5;
reg [8:0] A6;
wire [8:0] tmp0;
wire [8:0] tmp1;
wire [8:0] tmp2;
wire [8:0] tmp3;
wire [8:0] tmp4;
wire [8:0] tmp5;
wire [8:0] tmp6;
wire [8:0] tmp7;
always @ (tmp1) lambda_out = tmp1;
always @ (tmp3) omega_out = tmp3;
always @ (L or D or count)
// delta = (D != 0 && 2*L <= i);
if (D != 0 && count >= {L, 1'b0}) delta = 1;
else delta = 0;
rsdec_berl_multiply x0 (tmp0, B6, D, lambda0, syndrome0, phase0);
rsdec_berl_multiply x1 (tmp1, lambda7, DI, lambda1, syndrome1, phase0);
rsdec_berl_multiply x2 (tmp2, A6, D, lambda2, syndrome2, phase0);
rsdec_berl_multiply x3 (tmp3, omega7, DI, lambda3, syndrome3, phase0);
multiply x4 (tmp4, lambda4, syndrome4);
multiply x5 (tmp5, lambda5, syndrome5);
multiply x6 (tmp6, lambda6, syndrome6);
multiply x7 (tmp7, lambda7, syndrome7);
always @ (posedge clk)// or negedge clrn)
begin
// for (j = t-1; j >=0; j--)
// if (j != 0) lambda[j] += D * B[j-1];
/* if (~clrn)
begin
// for (j = 0; j < 8; j = j + 1) lambda[j] <= 0;
// for (j = 0; j < 7; j = j + 1) B[j] <= 0;
// for (j = 0; j < 8; j = j + 1) omega[j] <= 0;
// for (j = 0; j < 7; j = j + 1) A[j] <= 0;
lambda0 <= 0;
lambda1 <= 0;
lambda2 <= 0;
lambda3 <= 0;
lambda4 <= 0;
lambda5 <= 0;
lambda6 <= 0;
lambda7 <= 0;
B0 <= 0;
B1 <= 0;
B2 <= 0;
B3 <= 0;
B4 <= 0;
B5 <= 0;
B6 <= 0;
omega0 <= 0;
omega1 <= 0;
omega2 <= 0;
omega3 <= 0;
omega4 <= 0;
omega5 <= 0;
omega6 <= 0;
omega7 <= 0;
A0 <= 0;
A1 <= 0;
A2 <= 0;
A3 <= 0;
A4 <= 0;
A5 <= 0;
A6 <= 0;
end
else*/ if (~enable)
begin
/*
lambda[0] <= 1;
for (j = 1; j < 8; j = j +1) lambda[j] <= 0;
B[0] <= 1;
for (j = 1; j < 7; j = j +1) B[j] <= 0;
omega[0] <= 1;
for (j = 1; j < 8; j = j +1) omega[j] <= 0;
for (j = 0; j < 7; j = j + 1) A[j] <= 0;
*/
lambda0 <= 1;
lambda1 <= 0;
lambda2 <= 0;
lambda3 <= 0;
lambda4 <= 0;
lambda5 <= 0;
lambda6 <= 0;
lambda7 <= 0;
//for (j = 1; j < 12; j = j +1) lambda[j] <= 0;
B0 <= 1;
B1 <= 0;
B2 <= 0;
B3 <= 0;
B4 <= 0;
B5 <= 0;
B6 <= 0;
//for (j = 1; j < 11; j = j +1) B[j] <= 0;
omega0 <= 1;
omega1 <= 0;
omega2 <= 0;
omega3 <= 0;
omega4 <= 0;
omega5 <= 0;
omega6 <= 0;
omega7 <= 0;
//for (j = 1; j < 12; j = j +1) omega[j] <= 0;
A0 <= 0;
A1 <= 0;
A2 <= 0;
A3 <= 0;
A4 <= 0;
A5 <= 0;
A6 <= 0;
end
else
begin
if (~phase0)
begin
if (~phase8) lambda0 <= lambda7 ^ tmp0;
else lambda0 <= lambda7;
// for (j = 1; j < 8; j = j + 1)
// lambda[j] <= lambda[j-1];
lambda1 <= lambda0;
lambda2 <= lambda1;
lambda3 <= lambda2;
lambda4 <= lambda3;
lambda5 <= lambda4;
lambda6 <= lambda5;
lambda7 <= lambda6;
// end
// for (j = t-1; j >=0; j--)
// if (delta) B[j] = lambda[j] *DI;
// else if (j != 0) B[j] = B[j-1];
// else B[j] = 0;
// if (~phase0)
// begin
if (delta) B0 <= tmp1;
else if (~phase8) B0 <= B6;
else B0 <= 0;
// for (j = 1; j < 7; j = j + 1)
// B[j] <= B[j-1];
B1 <= B0;
B2 <= B1;
B3 <= B2;
B4 <= B3;
B5 <= B4;
B6 <= B5;
// end
// for (j = t-1; j >=0; j--)
// if (j != 0) omega[j] += D * A[j-1];
// if (~phase0)
// begin
if (~phase8) omega0 <= omega7 ^ tmp2;
else omega0 <= omega7;
// for (j = 1; j < 8; j = j + 1)
// omega[j] <= omega[j-1];
omega1 <= omega0;
omega2 <= omega1;
omega3 <= omega2;
omega4 <= omega3;
omega5 <= omega4;
omega6 <= omega5;
omega7 <= omega6;
// end
// for (j = t-1; j >=0; j--)
// if (delta) A[j] = omega[j] *DI;
// else if (j != 0) A[j] = A[j-1];
// else A[j] = 0;
// if (~phase0)
// begin
if (delta) A0 <= tmp3;
else if (~phase8) A0 <= A6;
else A0 <= 0;
// for (j = 1; j < 7; j = j + 1)
// A[j] <= A[j-1];
A1 <= A0;
A2 <= A1;
A3 <= A2;
A4 <= A3;
A5 <= A4;
A6 <= A5;
end
end
end
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
L <= 0;
D <= 0;
end
else
begin
// if (delta) L = i - L + 1;
if ((phase0 & delta) && (count != -1)) L <= count - L + 1;
//for (D = j = 0; j < t; j = j + 1)
// D += lambda[j] * syndrome[t-j-1];
if (phase0)
D <= tmp0 ^ tmp1 ^ tmp2 ^ tmp3 ^ tmp4 ^ tmp5 ^ tmp6 ^ tmp7;
end
end
endmodule
module rsdec_berl_multiply (y, a, b, c, d, e);
input [8:0] a, b, c, d;
input e;
output [8:0] y;
wire [8:0] y;
reg [8:0] p, q;
always @ (a or c or e)
if (e) p = c;
else p = a;
always @ (b or d or e)
if (e) q = d;
else q = b;
multiply x0 (y, p, q);
endmodule
module multiply (y, a, b);
input [8:0] a, b;
output [8:0] y;
wire [8:0] y;
reg [17:0] tempy;
assign y = tempy[8:0];
always @(a or b)
begin
tempy = a * b;
end
/*
always @ (a or b)
begin
y[0] = (a[0] & b[0]) ^ (a[1] & b[8]) ^ (a[2] & b[7]) ^ (a[3] & b[6]) ^ (a[4] & b[5]) ^ (a[5] & b[4]) ^ (a[6] & b[3]) ^ (a[6] & b[8]) ^ (a[7] & b[2]) ^ (a[7] & b[7]) ^ (a[8] & b[1]) ^ (a[8] & b[6]);
y[1] = (a[0] & b[1]) ^ (a[1] & b[0]) ^ (a[2] & b[8]) ^ (a[3] & b[7]) ^ (a[4] & b[6]) ^ (a[5] & b[5]) ^ (a[6] & b[4]) ^ (a[7] & b[3]) ^ (a[7] & b[8]) ^ (a[8] & b[2]) ^ (a[8] & b[7]);
y[2] = (a[0] & b[2]) ^ (a[1] & b[1]) ^ (a[2] & b[0]) ^ (a[3] & b[8]) ^ (a[4] & b[7]) ^ (a[5] & b[6]) ^ (a[6] & b[5]) ^ (a[7] & b[4]) ^ (a[8] & b[3]) ^ (a[8] & b[8]);
y[3] = (a[0] & b[3]) ^ (a[1] & b[2]) ^ (a[2] & b[1]) ^ (a[3] & b[0]) ^ (a[4] & b[8]) ^ (a[5] & b[7]) ^ (a[6] & b[6]) ^ (a[7] & b[5]) ^ (a[8] & b[4]);
y[4] = (a[0] & b[4]) ^ (a[1] & b[3]) ^ (a[1] & b[8]) ^ (a[2] & b[2]) ^ (a[2] & b[7]) ^ (a[3] & b[1]) ^ (a[3] & b[6]) ^ (a[4] & b[0]) ^ (a[4] & b[5]) ^ (a[5] & b[4]) ^ (a[5] & b[8]) ^ (a[6] & b[3]) ^ (a[6] & b[7]) ^ (a[6] & b[8]) ^ (a[7] & b[2]) ^ (a[7] & b[6]) ^ (a[7] & b[7]) ^ (a[8] & b[1]) ^ (a[8] & b[5]) ^ (a[8] & b[6]);
y[5] = (a[0] & b[5]) ^ (a[1] & b[4]) ^ (a[2] & b[3]) ^ (a[2] & b[8]) ^ (a[3] & b[2]) ^ (a[3] & b[7]) ^ (a[4] & b[1]) ^ (a[4] & b[6]) ^ (a[5] & b[0]) ^ (a[5] & b[5]) ^ (a[6] & b[4]) ^ (a[6] & b[8]) ^ (a[7] & b[3]) ^ (a[7] & b[7]) ^ (a[7] & b[8]) ^ (a[8] & b[2]) ^ (a[8] & b[6]) ^ (a[8] & b[7]);
y[6] = (a[0] & b[6]) ^ (a[1] & b[5]) ^ (a[2] & b[4]) ^ (a[3] & b[3]) ^ (a[3] & b[8]) ^ (a[4] & b[2]) ^ (a[4] & b[7]) ^ (a[5] & b[1]) ^ (a[5] & b[6]) ^ (a[6] & b[0]) ^ (a[6] & b[5]) ^ (a[7] & b[4]) ^ (a[7] & b[8]) ^ (a[8] & b[3]) ^ (a[8] & b[7]) ^ (a[8] & b[8]);
y[7] = (a[0] & b[7]) ^ (a[1] & b[6]) ^ (a[2] & b[5]) ^ (a[3] & b[4]) ^ (a[4] & b[3]) ^ (a[4] & b[8]) ^ (a[5] & b[2]) ^ (a[5] & b[7]) ^ (a[6] & b[1]) ^ (a[6] & b[6]) ^ (a[7] & b[0]) ^ (a[7] & b[5]) ^ (a[8] & b[4]) ^ (a[8] & b[8]);
y[8] = (a[0] & b[8]) ^ (a[1] & b[7]) ^ (a[2] & b[6]) ^ (a[3] & b[5]) ^ (a[4] & b[4]) ^ (a[5] & b[3]) ^ (a[5] & b[8]) ^ (a[6] & b[2]) ^ (a[6] & b[7]) ^ (a[7] & b[1]) ^ (a[7] & b[6]) ^ (a[8] & b[0]) ^ (a[8] & b[5]);
end
*/
endmodule
// -------------------------------------------------------------------------
//Syndrome generator circuit in Reed-Solomon Decoder
//Copyright (C) Wed Apr 28 11:28:10 2004
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rsdec_syn_m0 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[8];
y[1] = x[0];
y[2] = x[1];
y[3] = x[2];
y[4] = x[3] ^ x[8];
y[5] = x[4];
y[6] = x[5];
y[7] = x[6];
y[8] = x[7];
end
endmodule
module rsdec_syn_m1 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[7];
y[1] = x[8];
y[2] = x[0];
y[3] = x[1];
y[4] = x[2] ^ x[7];
y[5] = x[3] ^ x[8];
y[6] = x[4];
y[7] = x[5];
y[8] = x[6];
end
endmodule
module rsdec_syn_m2 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[6];
y[1] = x[7];
y[2] = x[8];
y[3] = x[0];
y[4] = x[1] ^ x[6];
y[5] = x[2] ^ x[7];
y[6] = x[3] ^ x[8];
y[7] = x[4];
y[8] = x[5];
end
endmodule
module rsdec_syn_m3 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[5];
y[1] = x[6];
y[2] = x[7];
y[3] = x[8];
y[4] = x[0] ^ x[5];
y[5] = x[1] ^ x[6];
y[6] = x[2] ^ x[7];
y[7] = x[3] ^ x[8];
y[8] = x[4];
end
endmodule
module rsdec_syn_m4 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[4];
y[1] = x[5];
y[2] = x[6];
y[3] = x[7];
y[4] = x[4] ^ x[8];
y[5] = x[0] ^ x[5];
y[6] = x[1] ^ x[6];
y[7] = x[2] ^ x[7];
y[8] = x[3] ^ x[8];
end
endmodule
module rsdec_syn_m5 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[3] ^ x[8];
y[1] = x[4];
y[2] = x[5];
y[3] = x[6];
y[4] = x[3] ^ x[7] ^ x[8];
y[5] = x[4] ^ x[8];
y[6] = x[0] ^ x[5];
y[7] = x[1] ^ x[6];
y[8] = x[2] ^ x[7];
end
endmodule
module rsdec_syn_m6 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[2] ^ x[7];
y[1] = x[3] ^ x[8];
y[2] = x[4];
y[3] = x[5];
y[4] = x[2] ^ x[6] ^ x[7];
y[5] = x[3] ^ x[7] ^ x[8];
y[6] = x[4] ^ x[8];
y[7] = x[0] ^ x[5];
y[8] = x[1] ^ x[6];
end
endmodule
module rsdec_syn_m7 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[6];
y[1] = x[2] ^ x[7];
y[2] = x[3] ^ x[8];
y[3] = x[4];
y[4] = x[1] ^ x[5] ^ x[6];
y[5] = x[2] ^ x[6] ^ x[7];
y[6] = x[3] ^ x[7] ^ x[8];
y[7] = x[4] ^ x[8];
y[8] = x[0] ^ x[5];
end
endmodule
module rsdec_syn (y0, y1, y2, y3, y4, y5, y6, y7, u, enable, shift, init, clk, clrn);
input [8:0] u;
input clk, clrn, shift, init, enable;
output [8:0] y0;
output [8:0] y1;
output [8:0] y2;
output [8:0] y3;
output [8:0] y4;
output [8:0] y5;
output [8:0] y6;
output [8:0] y7;
reg [8:0] y0;
reg [8:0] y1;
reg [8:0] y2;
reg [8:0] y3;
reg [8:0] y4;
reg [8:0] y5;
reg [8:0] y6;
reg [8:0] y7;
wire [8:0] scale0;
wire [8:0] scale1;
wire [8:0] scale2;
wire [8:0] scale3;
wire [8:0] scale4;
wire [8:0] scale5;
wire [8:0] scale6;
wire [8:0] scale7;
rsdec_syn_m0 m0 (scale0, y0);
rsdec_syn_m1 m1 (scale1, y1);
rsdec_syn_m2 m2 (scale2, y2);
rsdec_syn_m3 m3 (scale3, y3);
rsdec_syn_m4 m4 (scale4, y4);
rsdec_syn_m5 m5 (scale5, y5);
rsdec_syn_m6 m6 (scale6, y6);
rsdec_syn_m7 m7 (scale7, y7);
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
y0 <= 0;
y1 <= 0;
y2 <= 0;
y3 <= 0;
y4 <= 0;
y5 <= 0;
y6 <= 0;
y7 <= 0;
end
else if (init)
begin
y0 <= u;
y1 <= u;
y2 <= u;
y3 <= u;
y4 <= u;
y5 <= u;
y6 <= u;
y7 <= u;
end
else if (enable)
begin
y0 <= scale0 ^ u;
y1 <= scale1 ^ u;
y2 <= scale2 ^ u;
y3 <= scale3 ^ u;
y4 <= scale4 ^ u;
y5 <= scale5 ^ u;
y6 <= scale6 ^ u;
y7 <= scale7 ^ u;
end
else if (shift)
begin
y0 <= y1;
y1 <= y2;
y2 <= y3;
y3 <= y4;
y4 <= y5;
y5 <= y6;
y6 <= y7;
y7 <= y0;
end
end
endmodule
// -------------------------------------------------------------------------
//Chien-Forney search circuit for Reed-Solomon decoder
//Copyright (C) Wed Apr 28 11:17:57 2004
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rsdec_chien_scale0 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[0];
y[1] = x[1];
y[2] = x[2];
y[3] = x[3];
y[4] = x[4];
y[5] = x[5];
y[6] = x[6];
y[7] = x[7];
y[8] = x[8];
end
endmodule
module rsdec_chien_scale1 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[8];
y[1] = x[0];
y[2] = x[1];
y[3] = x[2];
y[4] = x[3] ^ x[8];
y[5] = x[4];
y[6] = x[5];
y[7] = x[6];
y[8] = x[7];
end
endmodule
module rsdec_chien_scale2 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[7];
y[1] = x[8];
y[2] = x[0];
y[3] = x[1];
y[4] = x[2] ^ x[7];
y[5] = x[3] ^ x[8];
y[6] = x[4];
y[7] = x[5];
y[8] = x[6];
end
endmodule
module rsdec_chien_scale3 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[6];
y[1] = x[7];
y[2] = x[8];
y[3] = x[0];
y[4] = x[1] ^ x[6];
y[5] = x[2] ^ x[7];
y[6] = x[3] ^ x[8];
y[7] = x[4];
y[8] = x[5];
end
endmodule
module rsdec_chien_scale4 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[5];
y[1] = x[6];
y[2] = x[7];
y[3] = x[8];
y[4] = x[0] ^ x[5];
y[5] = x[1] ^ x[6];
y[6] = x[2] ^ x[7];
y[7] = x[3] ^ x[8];
y[8] = x[4];
end
endmodule
module rsdec_chien_scale5 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[4];
y[1] = x[5];
y[2] = x[6];
y[3] = x[7];
y[4] = x[4] ^ x[8];
y[5] = x[0] ^ x[5];
y[6] = x[1] ^ x[6];
y[7] = x[2] ^ x[7];
y[8] = x[3] ^ x[8];
end
endmodule
module rsdec_chien_scale6 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[3] ^ x[8];
y[1] = x[4];
y[2] = x[5];
y[3] = x[6];
y[4] = x[3] ^ x[7] ^ x[8];
y[5] = x[4] ^ x[8];
y[6] = x[0] ^ x[5];
y[7] = x[1] ^ x[6];
y[8] = x[2] ^ x[7];
end
endmodule
module rsdec_chien_scale7 (y, x);
input [8:0] x;
output [8:0] y;
reg [8:0] y;
always @ (x)
begin
y[0] = x[2] ^ x[7];
y[1] = x[3] ^ x[8];
y[2] = x[4];
y[3] = x[5];
y[4] = x[2] ^ x[6] ^ x[7];
y[5] = x[3] ^ x[7] ^ x[8];
y[6] = x[4] ^ x[8];
y[7] = x[0] ^ x[5];
y[8] = x[1] ^ x[6];
end
endmodule
module rsdec_chien (error, alpha, lambda, omega, even, D, search, load, shorten, clk, clrn);
input clk, clrn, load, search, shorten;
input [8:0] D;
input [8:0] lambda;
input [8:0] omega;
output [8:0] even, error;
output [8:0] alpha;
reg [8:0] even, error;
reg [8:0] alpha;
wire [8:0] scale0;
wire [8:0] scale1;
wire [8:0] scale2;
wire [8:0] scale3;
wire [8:0] scale4;
wire [8:0] scale5;
wire [8:0] scale6;
wire [8:0] scale7;
wire [8:0] scale8;
wire [8:0] scale9;
wire [8:0] scale10;
wire [8:0] scale11;
wire [8:0] scale12;
wire [8:0] scale13;
wire [8:0] scale14;
wire [8:0] scale15;
reg [8:0] data0;
reg [8:0] data1;
reg [8:0] data2;
reg [8:0] data3;
reg [8:0] data4;
reg [8:0] data5;
reg [8:0] data6;
reg [8:0] data7;
reg [8:0] a0;
reg [8:0] a1;
reg [8:0] a2;
reg [8:0] a3;
reg [8:0] a4;
reg [8:0] a5;
reg [8:0] a6;
reg [8:0] a7;
reg [8:0] l0;
reg [8:0] l1;
reg [8:0] l2;
reg [8:0] l3;
reg [8:0] l4;
reg [8:0] l5;
reg [8:0] l6;
reg [8:0] l7;
reg [8:0] o0;
reg [8:0] o1;
reg [8:0] o2;
reg [8:0] o3;
reg [8:0] o4;
reg [8:0] o5;
reg [8:0] o6;
reg [8:0] o7;
reg [8:0] odd, numerator;
wire [8:0] tmp;
//integer j;
rsdec_chien_scale0 x0 (scale0, data0);
rsdec_chien_scale1 x1 (scale1, data1);
rsdec_chien_scale2 x2 (scale2, data2);
rsdec_chien_scale3 x3 (scale3, data3);
rsdec_chien_scale4 x4 (scale4, data4);
rsdec_chien_scale5 x5 (scale5, data5);
rsdec_chien_scale6 x6 (scale6, data6);
rsdec_chien_scale7 x7 (scale7, data7);
rsdec_chien_scale0 x8 (scale8, o0);
rsdec_chien_scale1 x9 (scale9, o1);
rsdec_chien_scale2 x10 (scale10, o2);
rsdec_chien_scale3 x11 (scale11, o3);
rsdec_chien_scale4 x12 (scale12, o4);
rsdec_chien_scale5 x13 (scale13, o5);
rsdec_chien_scale6 x14 (scale14, o6);
rsdec_chien_scale7 x15 (scale15, o7);
always @ (shorten or a0 or l0)
if (shorten) data0 = a0;
else data0 = l0;
always @ (shorten or a1 or l1)
if (shorten) data1 = a1;
else data1 = l1;
always @ (shorten or a2 or l2)
if (shorten) data2 = a2;
else data2 = l2;
always @ (shorten or a3 or l3)
if (shorten) data3 = a3;
else data3 = l3;
always @ (shorten or a4 or l4)
if (shorten) data4 = a4;
else data4 = l4;
always @ (shorten or a5 or l5)
if (shorten) data5 = a5;
else data5 = l5;
always @ (shorten or a6 or l6)
if (shorten) data6 = a6;
else data6 = l6;
always @ (shorten or a7 or l7)
if (shorten) data7 = a7;
else data7 = l7;
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
l0 <= 0;
l1 <= 0;
l2 <= 0;
l3 <= 0;
l4 <= 0;
l5 <= 0;
l6 <= 0;
l7 <= 0;
o0 <= 0;
o1 <= 0;
o2 <= 0;
o3 <= 0;
o4 <= 0;
o5 <= 0;
o6 <= 0;
o7 <= 0;
a0 <= 1;
a1 <= 1;
a2 <= 1;
a3 <= 1;
a4 <= 1;
a5 <= 1;
a6 <= 1;
a7 <= 1;
end
else if (shorten)
begin
a0 <= scale0;
a1 <= scale1;
a2 <= scale2;
a3 <= scale3;
a4 <= scale4;
a5 <= scale5;
a6 <= scale6;
a7 <= scale7;
end
else if (search)
begin
l0 <= scale0;
l1 <= scale1;
l2 <= scale2;
l3 <= scale3;
l4 <= scale4;
l5 <= scale5;
l6 <= scale6;
l7 <= scale7;
o0 <= scale8;
o1 <= scale9;
o2 <= scale10;
o3 <= scale11;
o4 <= scale12;
o5 <= scale13;
o6 <= scale14;
o7 <= scale15;
end
else if (load)
begin
l0 <= lambda;
l1 <= l0;
l2 <= l1;
l3 <= l2;
l4 <= l3;
l5 <= l4;
l6 <= l5;
l7 <= l6;
o0 <= omega;
o1 <= o0;
o2 <= o1;
o3 <= o2;
o4 <= o3;
o5 <= o4;
o6 <= o5;
o7 <= o6;
a0 <= a7;
a1 <= a0;
a2 <= a1;
a3 <= a2;
a4 <= a3;
a5 <= a4;
a6 <= a5;
a7 <= a6;
end
end
always @ (l0 or l2 or l4 or l6)
even = l0 ^ l2 ^ l4 ^ l6;
always @ (l1 or l3 or l5 or l7)
odd = l1 ^ l3 ^ l5 ^ l7;
always @ (o0 or o1 or o2 or o3 or o4 or o5 or o6 or o7)
numerator = o0 ^ o1 ^ o2 ^ o3 ^ o4 ^ o5 ^ o6 ^ o7;
multiply m0 (tmp, numerator, D);
always @ (even or odd or tmp)
if (even == odd) error = tmp;
else error = 0;
always @ (a7) alpha = a7;
endmodule
|
//-----------------------------------------------------------------------------
// Title : MIPS Single-Cycle Processor
// Project : ECE 313 - Computer Organization
//-----------------------------------------------------------------------------
// File : mips_single.v
// Author : John Nestor <[email protected]>
// Organization : Lafayette College
//
// Created : October 2002
// Last modified : 7 January 2005
//-----------------------------------------------------------------------------
// Description :
// "Single Cycle" implementation of the MIPS processor subset described in
// Section 5.4 of "Computer Organization and Design, 3rd ed."
// by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e).
//
// It implements the equivalent of Figure 5.19 on page 309 of COD3e
//
//-----------------------------------------------------------------------------
module mips_single(clk, reset);
input clk, reset;
// instruction bus
wire [31:0] instr;
// break out important fields from instruction
wire [5:0] opcode, funct;
wire [4:0] rs, rt, rd, shamt;
wire [15:0] immed;
wire [31:0] extend_immed, b_offset;
wire [25:0] jumpoffset;
assign opcode = instr[31:26];
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rd = instr[15:11];
assign shamt = instr[10:6];
assign funct = instr[5:0];
assign immed = instr[15:0];
assign jumpoffset = instr[25:0];
// sign-extender
assign extend_immed = { {16{immed[15]}}, immed };
// branch offset shifter
assign b_offset = extend_immed << 2;
// datapath signals
wire [4:0] rfile_wn;
wire [31:0] rfile_rd1, rfile_rd2, rfile_wd, alu_b, alu_out, b_tgt, pc_next,
pc, pc_incr, br_add_out, dmem_rdata, pc_next2;
wire [31:0] jumpTo;
assign jumpTo = (jumpoffset<<2)+pc_incr[31:28];
// control signals
wire RegWrite, Branch, PCSrc, RegDst, MemtoReg, MemRead, MemWrite, ALUSrc, Zero, Jmp, Zero2;
wire [1:0] ALUOp;
wire [2:0] Operation;
// module instantiations
reg32 PC(clk, reset, pc_next, pc);
add32 PCADD(pc, 32'd4, pc_incr);
add32 BRADD(pc_incr, b_offset, b_tgt);
reg_file RFILE(clk, RegWrite, rs, rt, rfile_wn, rfile_rd1, rfile_rd2, rfile_wd);
alu ALU(Operation, rfile_rd1, alu_b, alu_out, Zero);
rom32 IMEM(pc, instr);
mem32 DMEM(clk, MemRead, MemWrite, alu_out, rfile_rd2, dmem_rdata);
xor BR_XOR(Zero2, opcode[0], Zero);
and BR_AND(PCSrc, Branch, Zero2);
mux2 #(5) RFMUX(RegDst, rt, rd, rfile_wn);
mux2 #(32) PCMUX(PCSrc, pc_incr, b_tgt, pc_next2);
mux2 #(32) JMUX(Jmp, pc_next2, jumpTo, pc_next); // control, input, output
mux2 #(32) ALUMUX(ALUSrc, rfile_rd2, extend_immed, alu_b);
mux2 #(32) WRMUX(MemtoReg, alu_out, dmem_rdata, rfile_wd);
control_single CTL(.opcode(opcode), .RegDst(RegDst), .ALUSrc(ALUSrc), .MemtoReg(MemtoReg),
.RegWrite(RegWrite), .MemRead(MemRead), .MemWrite(MemWrite), .Branch(Branch),
.Jmp(Jmp), .ALUOp(ALUOp));
alu_ctl ALUCTL(ALUOp, funct, Operation);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
//`include "control.h"
// ncverilog only
`include "~/ee577b/syn/src/control.h"
// synthesis only
// Behavioral model for the ALU
module alu(reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ppp)
//------------------------------------------------------------------------------------
`aa: // aluwslli SLLI `aa
begin
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}};
result[32:63]<={reg_A[43:63],{11{1'b0}};
result[64:95]<={reg_A[75:95],{11{1'b0}};
result[96:127]<={reg_A[107:127],{11{1'b0}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
end
//------------------------------------------------------------------------------------
`uu: // aluwslli SLLI `uu
begin
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:127]<=64'd0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:127]<=64'd0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:127]<=64'd0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:127]<=64'd0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
5'd9
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}};
result[32:63]<={reg_A[43:63],{11{1'b0}};
result[64:95]<={reg_A[75:95],{11{1'b0}};
result[96:127]<={reg_A[107:127],{11{1'b0}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:127]<=64'd0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:127]<=64'd0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:127]<=64'd0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:127]<=64'd0;
end
5'd19
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:127]<=64'd0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:127]<=64'd0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:127]<=64'd0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:127]<=64'd0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:127]<=64'd0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:127]<=64'd0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:127]<=64'd0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:127]<=64'd0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:127]<=64'd0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:127]<=64'd0;
end
5'd29
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:127]<=64'd0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:127]<=64'd0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
end
//------------------------------------------------------------------------------------
`dd: // aluwslli SLLI `dd
begin
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
3'd1:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
4'd1:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
5'd1:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[75:95],{11{1'b0}};
result[96:127]<={reg_A[107:127],{11{1'b0}};
end
5'd12:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
end
//------------------------------------------------------------------------------------
`ee: // aluwslli SLLI `ee
begin
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:15]<=8'b0;
result[16:23]<=reg_A[16:23];
result[24:31]<=8'b0;
result[32:39]<=reg_A[33:39];
result[40:47]<=8'b0;
result[48:55]<=reg_A[48:55];
result[56:63]<=8'b0;
result[64:71]<=reg_A[64:71];
result[72:79]<=8'b0;
result[80:87]<=reg_A[80:87];
result[88:95]<=8'b0;
result[96:103]<=reg_A[96:103];
result[104:111]<=8'b0;
result[112:119]<=reg_A[112:119];
result[120:127]<=8'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<=8'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<=8'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<=8'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<=8'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<=8'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<=8'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<=8'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<=16'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<=16'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<=16'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<=16'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<=16'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<=16'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<=16'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<=16'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<=16'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<=16'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<=16'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<=16'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<=16'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<=16'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<=16'b0;
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<=32'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<=32'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<=32'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<=32'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<=32'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<=32'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<=32'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<=32'b0;
end
5'd9
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<=32'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<=32'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[75:95],{11{1'b0}};
result[96:127]<=32'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<=32'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<=32'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<=32'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<=32'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<=32'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<=32'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<=32'b0;
end
5'd19
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<=32'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<=32'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<=32'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<=32'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<=32'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<=32'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<=32'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<=32'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<=32'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<=32'b0;
end
5'd29
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<=32'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<=32'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<=32'b0;
end
endcase
end
end
//------------------------------------------------------------------------------------
`oo: // aluwslli SLLI `oo
begin
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[43:63],{11{1'b0}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}};
end
5'd12:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
end
//------------------------------------------------------------------------------------
`mm: // aluwslli SLLI `mm
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:127]<=119'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:127]<=119'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:127]<=119'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:127]<=119'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:127]<=119'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:127]<=119'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:127]<=119'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:127]<=119'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:15]<=reg_A[0:15];
result[16:127]<=112'b0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:127]<=112'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:127]<=112'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:127]<=112'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:127]<=112'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:127]<=112'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:127]<=112'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:127]<=112'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:127]<=112'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:127]<=112'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:127]<=112'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:127]<=112'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:127]<=112'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:127]<=112'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:127]<=112'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:127]<=112'b0;
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:31]<=reg_A[0:31];
result[32:127]<=96'b0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:127]<=96'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:127]<=96'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:127]<=96'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:127]<=96'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:127]<=96'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:127]<=96'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:127]<=96'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:127]<=96'b0;
end
5'd9
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:127]<=96'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:127]<=96'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}};
result[32:127]<=96'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:127]<=96'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:127]<=96'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:127]<=96'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:127]<=96'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:127]<=96'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:127]<=96'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:127]<=96'b0;
end
5'd19
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:127]<=96'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:127]<=96'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:127]<=96'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:127]<=96'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:127]<=96'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:127]<=96'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:127]<=96'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:127]<=96'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:127]<=96'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:127]<=96'b0;
end
5'd29
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:127]<=96'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:127]<=96'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:127]<=96'b0;
end
endcase
end
end
//----------------------------------------------------------------------------------------------
`ll: // aluwslli SLLI `ll
begin
case(crtl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:119]<=120'b0;
result[120:127]<=reg_A[120:127];
end
3'd1:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:111]<=112'b0;
result[112:127]<=reg_A[112:127];
end
4'd1:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
'w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:95]<=96'b0;
result[96:127]<=reg_A[96:127];
end
5'd1:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}};
end
5'd12:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
end
endcase
end
// ================================================
// PRM instruction
`aluwprm:
begin
case(ctrl_ppp)
`aa: // aluwprm PRM `aa
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`uu: // aluwprm PRM `uu
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//bytes8-15
result[64:127]<=64'd0;
end
`dd: // aluwprm PRM `dd
begin
//bytes0-7
result[0:63]<=64'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[0:7];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`ee: // aluwprm PRM `ee
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//byte1
result[8:15]<=8'd0;
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
//byte3
result[24:31]<=8'd0;
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
//byte5
result[40:47]<=8'd0;
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
//byte7
result[56:63]<=8'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
//byte9
result[72:79]<=8'd0;
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
//byte11
result[88:95]<=8'd0;
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
//byte13
result[104:111]<=8'd0;
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
//byte15
result[120:127]<=8'd0;
end
`oo: // aluwprm PRM `oo
begin
//byte0
result[0:7]<=8'd0;
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
//byte2
result[16:23]<=8'd0;
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
//byte4
result[32:39]<=8'd0;
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
//byte6
result[48:55]<=8'd0;
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//byte8
result[64:71]<=8'd0;
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
//byte10
result[80:87]<=8'd0;
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
//byte12
result[96:103]<=8'd0;
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
//byte14
result[112:119]<=8'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`mm: // aluwprm PRM `mm
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//bytes1-14
result[8:127]<=120'd0;
end
`ll: // aluwprm PRM `ll
begin
//bytes0-14
result[0:119]<=120'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
default: // aluwprm PRM Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
/*
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
*/
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
module prometheus_fx3_stream_out(
input rst_n,
input clk_100,
input stream_out_mode_selected,
input i_gpif_in_ch1_rdy_d,
input i_gpif_out_ch1_rdy_d,
input [31:0]stream_out_data_from_fx3,
output o_gpif_re_n_stream_out_,
output o_gpif_oe_n_stream_out_
);
reg [2:0]current_stream_out_state;
reg [2:0]next_stream_out_state;
//parameters for StreamOUT mode state machine
parameter [2:0] stream_out_idle = 3'd0;
parameter [2:0] stream_out_flagc_rcvd = 3'd1;
parameter [2:0] stream_out_wait_flagd = 3'd2;
parameter [2:0] stream_out_read = 3'd3;
parameter [2:0] stream_out_read_rd_and_oe_delay = 3'd4;
parameter [2:0] stream_out_read_oe_delay = 3'd5;
reg [1:0] oe_delay_cnt;
reg rd_oe_delay_cnt;
assign o_gpif_re_n_stream_out_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay)) ? 1'b0 : 1'b1;
assign o_gpif_oe_n_stream_out_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay) | (current_stream_out_state == stream_out_read_oe_delay)) ? 1'b0 : 1'b1;
//counter to delay the read and output enable signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
rd_oe_delay_cnt <= 1'b0;
end else if(current_stream_out_state == stream_out_read) begin
rd_oe_delay_cnt <= 1'b1;
end else if((current_stream_out_state == stream_out_read_rd_and_oe_delay) & (rd_oe_delay_cnt > 1'b0))begin
rd_oe_delay_cnt <= rd_oe_delay_cnt - 1'b1;
end else begin
rd_oe_delay_cnt <= rd_oe_delay_cnt;
end
end
//Counter to delay the OUTPUT Enable(oe) signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
oe_delay_cnt <= 2'd0;
end else if(current_stream_out_state == stream_out_read_rd_and_oe_delay) begin
oe_delay_cnt <= 2'd2;
end else if((current_stream_out_state == stream_out_read_oe_delay) & (oe_delay_cnt > 1'b0))begin
oe_delay_cnt <= oe_delay_cnt - 1'b1;
end else begin
oe_delay_cnt <= oe_delay_cnt;
end
end
//stream_out mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_stream_out_state <= stream_out_idle;
end else begin
current_stream_out_state <= next_stream_out_state;
end
end
//steamOUT mode state machine combo
always @(*)begin
next_stream_out_state = current_stream_out_state;
case(current_stream_out_state)
stream_out_idle:begin
if((stream_out_mode_selected) & (i_gpif_in_ch1_rdy_d == 1'b1))begin
next_stream_out_state = stream_out_flagc_rcvd;
end else begin
next_stream_out_state = stream_out_idle;
end
end
stream_out_flagc_rcvd:begin
next_stream_out_state = stream_out_wait_flagd;
end
stream_out_wait_flagd:begin
if(i_gpif_out_ch1_rdy_d == 1'b1)begin
next_stream_out_state = stream_out_read;
end else begin
next_stream_out_state = stream_out_wait_flagd;
end
end
stream_out_read :begin
if(i_gpif_out_ch1_rdy_d == 1'b0)begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end else begin
next_stream_out_state = stream_out_read;
end
end
stream_out_read_rd_and_oe_delay : begin
if(rd_oe_delay_cnt == 0)begin
next_stream_out_state = stream_out_read_oe_delay;
end else begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end
end
stream_out_read_oe_delay : begin
if(oe_delay_cnt == 0)begin
next_stream_out_state = stream_out_idle;
end else begin
next_stream_out_state = stream_out_read_oe_delay;
end
end
endcase
end
endmodule
|
module TB_fpgatop();
//input REFCLK_N_IN,
//input REFCLK_P_IN,
reg CLK100M_N;
wire CLK100M_P;
//c2c connections
wire [31:0] ring_up_in;
wire [31:0] ring_dn_in;
wire [31:0] ring_up_out;
wire [31:0] ring_dn_out;
wire ring_lock_in;
wire ring_lock_out;
wire ring_ready_in;
wire ring_ready_out;
wire ring_dn_lock_in;
wire ring_dn_lock_out;
wire ring_dn_ready_in;
wire ring_dn_ready_out;
fpga_top uut(
//input REFCLK_N_IN,
//input REFCLK_P_IN,
.CLK100M_N (CLK100M_N),
.CLK100M_P (CLK100M_P),
.ring_up_in (ring_up_in),
.ring_dn_in (ring_dn_in),
.ring_up_out (ring_up_out),
.ring_dn_out (ring_dn_out),
.ring_up_lock_in (ring_lock_in),
.ring_up_lock_out(ring_lock_out),
.ring_up_ready_in(ring_ready_in),
.ring_up_ready_out(ring_ready_out),
.ring_dn_lock_in (ring_dn_lock_in),
.ring_dn_lock_out (ring_dn_lock_out),
.ring_dn_ready_in (ring_dn_ready_in),
.ring_dn_ready_out (ring_dn_ready_out));
fpga_top uut2(
//input REFCLK_N_IN,
//input REFCLK_P_IN,
.CLK100M_N (CLK100M_N),
.CLK100M_P (CLK100M_P),
.ring_up_in (),
.ring_dn_in (ring_up_out),
.ring_up_out (),
.ring_dn_out (ring_up_in),
.ring_up_lock_in (),
.ring_up_lock_out(),
.ring_up_ready_in(),
.ring_up_ready_out(),
.ring_dn_lock_in (ring_lock_out),
.ring_dn_lock_out (ring_lock_in),
.ring_dn_ready_in (ring_ready_out),
.ring_dn_ready_out (ring_ready_in));
initial begin
// Initialize Inputs
// REFCLK_N_IN = 0;
// REFCLK_P_IN = 1;
CLK100M_N = 0;
//ring_up_in = 0;
//ring_dn_in = 0;
//ring_lock_in = 0;
//ring_ready_in = 0;
end
always #5000 CLK100M_N <= !CLK100M_N;
assign CLK100M_P = !CLK100M_N;
endmodule |
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v2_3_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* XGMII 10GBASE-R encoder
*/
module xgmii_baser_enc_64 #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_tx_data,
output wire [HDR_WIDTH-1:0] encoded_tx_hdr
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
reg [DATA_WIDTH*7/8-1:0] encoded_ctrl;
reg [CTRL_WIDTH-1:0] encode_err;
reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {DATA_WIDTH{1'b0}}, encoded_tx_data_next;
reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = {HDR_WIDTH{1'b0}}, encoded_tx_hdr_next;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
integer i;
always @* begin
for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
if (xgmii_txc[i]) begin
// control
case (xgmii_txd[8*i +: 8])
XGMII_IDLE: begin
encoded_ctrl[7*i +: 7] = CTRL_IDLE;
encode_err[i] = 1'b0;
end
XGMII_ERROR: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b0;
end
XGMII_RES_0: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_0;
encode_err[i] = 1'b0;
end
XGMII_RES_1: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_1;
encode_err[i] = 1'b0;
end
XGMII_RES_2: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_2;
encode_err[i] = 1'b0;
end
XGMII_RES_3: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_3;
encode_err[i] = 1'b0;
end
XGMII_RES_4: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_4;
encode_err[i] = 1'b0;
end
XGMII_RES_5: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_5;
encode_err[i] = 1'b0;
end
default: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
endcase
end else begin
// data (always invalid as control)
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
end
if (xgmii_txc == 8'h00) begin
encoded_tx_data_next = xgmii_txd;
encoded_tx_hdr_next = SYNC_DATA;
end else begin
if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_START && !xgmii_txc[7:1]) begin
// start in lane 0
encoded_tx_data_next = {xgmii_txd[63:8], BLOCK_TYPE_START_0};
end else if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_START && !xgmii_txc[7:5]) begin
// start in lane 4
if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_SEQ_OS && !xgmii_txc[3:1]) begin
// ordered set in lane 0
encoded_tx_data_next[35:0] = {O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_START_4};
end else begin
encoded_tx_data_next[35:0] = {encoded_ctrl[27:0], BLOCK_TYPE_START_4};
end
encoded_tx_data_next[63:36] = {xgmii_txd[63:40], 4'd0};
end else if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_SEQ_OS && !xgmii_txc[3:1]) begin
// ordered set in lane 0
encoded_tx_data_next[35:8] = {O_SEQ_OS, xgmii_txd[31:8]};
if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_SEQ_OS && !xgmii_txc[7:5]) begin
// ordered set in lane 4
encoded_tx_data_next[63:36] = {xgmii_txd[63:40], O_SEQ_OS};
encoded_tx_data_next[7:0] = BLOCK_TYPE_OS_04;
end else begin
encoded_tx_data_next[63:36] = encoded_ctrl[55:28];
encoded_tx_data_next[7:0] = BLOCK_TYPE_OS_0;
end
end else if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_SEQ_OS && !xgmii_txc[7:5]) begin
// ordered set in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, 4'd0, encoded_ctrl[27:0], BLOCK_TYPE_OS_4};
end else if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_TERM) begin
// terminate in lane 0
encoded_tx_data_next = {encoded_ctrl[55:7], 7'd0, BLOCK_TYPE_TERM_0};
end else if (xgmii_txc[1] && xgmii_txd[15:8] == XGMII_TERM && !xgmii_txc[0]) begin
// terminate in lane 1
encoded_tx_data_next = {encoded_ctrl[55:14], 6'd0, xgmii_txd[7:0], BLOCK_TYPE_TERM_1};
end else if (xgmii_txc[2] && xgmii_txd[23:16] == XGMII_TERM && !xgmii_txc[1:0]) begin
// terminate in lane 2
encoded_tx_data_next = {encoded_ctrl[55:21], 5'd0, xgmii_txd[15:0], BLOCK_TYPE_TERM_2};
end else if (xgmii_txc[3] && xgmii_txd[31:24] == XGMII_TERM && !xgmii_txc[2:0]) begin
// terminate in lane 3
encoded_tx_data_next = {encoded_ctrl[55:28], 4'd0, xgmii_txd[23:0], BLOCK_TYPE_TERM_3};
end else if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_TERM && !xgmii_txc[3:0]) begin
// terminate in lane 4
encoded_tx_data_next = {encoded_ctrl[55:35], 3'd0, xgmii_txd[31:0], BLOCK_TYPE_TERM_4};
end else if (xgmii_txc[5] && xgmii_txd[47:40] == XGMII_TERM && !xgmii_txc[4:0]) begin
// terminate in lane 5
encoded_tx_data_next = {encoded_ctrl[55:42], 2'd0, xgmii_txd[39:0], BLOCK_TYPE_TERM_5};
end else if (xgmii_txc[6] && xgmii_txd[55:48] == XGMII_TERM && !xgmii_txc[5:0]) begin
// terminate in lane 6
encoded_tx_data_next = {encoded_ctrl[55:49], 1'd0, xgmii_txd[47:0], BLOCK_TYPE_TERM_6};
end else if (xgmii_txc[7] && xgmii_txd[63:56] == XGMII_TERM && !xgmii_txc[6:0]) begin
// terminate in lane 7
encoded_tx_data_next = {xgmii_txd[55:0], BLOCK_TYPE_TERM_7};
end else begin
// all control
encoded_tx_data_next = {encoded_ctrl, BLOCK_TYPE_CTRL};
end
encoded_tx_hdr_next = SYNC_CTRL;
end
end
always @(posedge clk) begin
encoded_tx_data_reg <= encoded_tx_data_next;
encoded_tx_hdr_reg <= encoded_tx_hdr_next;
end
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
`default_nettype none
module comparator_counter(
input wire iCLOCK,
input wire inRESET,
//Main Counter
input wire iMTIMER_WORKING,
input wire [63:0] iMTIMER_COUNT,
//Timmer Settings
input wire iCONF_WRITE,
input wire iCONF_ENA,
input wire iCONF_IRQENA,
input wire iCONF_64MODE,
input wire iCONF_PERIODIC, //Non Periodic mode = 0 | Periodic mode = 1
//Counter
input wire iCOUNT_WRITE,
input wire [1:0] inCOUNT_DQM,
input wire [63:0] iCOUNT_COUNTER,
//Interrupt
output wire oIRQ
);
reg enable;
reg irqena;
reg [63:0] ini_counter;
reg [63:0] counter;
reg bitmode;
reg periodic;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
enable <= 1'b0;
irqena <= 1'b0;
ini_counter <= 64'h0;
counter <= 64'h0;
bitmode <= 1'b0;
periodic <= 1'b0;
end
else begin
///Counter Setting
if(iCONF_WRITE)begin
enable <= iCONF_ENA;
irqena <= iCONF_IRQENA;
bitmode <= iCONF_64MODE;
periodic <= iCONF_PERIODIC;
//Counter Write
if(iCOUNT_WRITE)begin
ini_counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
ini_counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
end
end
else begin
//Counter Write
if(iCOUNT_WRITE)begin
ini_counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
ini_counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
end
else if(enable)begin
if(periodic)begin
if(bitmode)begin
//64bit Mode
if(counter == iMTIMER_COUNT)begin
counter <= counter + ini_counter;
end
end
else begin
//32bit Mode
if(counter[31:0] == iMTIMER_COUNT[31:0])begin
counter <= counter + ini_counter;
end
end
end
end
end
end
end
assign oIRQ = irqena && iMTIMER_WORKING && (bitmode)? (counter == iMTIMER_COUNT && ini_counter != 64'h0) : (counter[31:0] == iMTIMER_COUNT[31:0] && ini_counter[31:0] != 32'h0);
endmodule
`default_nettype wire
|
// DESCRIPTION: Verilator: Simple test of CLkDATA
//
// Trigger the CLKDATA detection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Jie Xu.
localparam ID_MSB = 1;
module t (/*AUTOARG*/
// Inputs
clk,
res,
res8,
res16
);
input clk;
output res;
output [7:0] res8;
output [15:0] res16;
wire [7:0] clkSet;
wire clk_1;
wire [2:0] clk_3;
wire [3:0] clk_4;
wire clk_final;
reg [7:0] count;
assign clkSet = {8{clk}};
assign clk_4 = clkSet[7:4];
assign clk_1 = clk_4[0];;
// arraysel
assign clk_3 = {3{clk_1}};
assign clk_final = clk_3[0];
// the following two assignment triggers the CLKDATA warning
// because on LHS there are a mix of signals both CLOCK and
// DATA
/* verilator lint_off CLKDATA */
assign res8 = {clk_3, 1'b0, clk_4};
assign res16 = {count, clk_3, clk_1, clk_4};
/* verilator lint_on CLKDATA */
initial
count = 0;
always @(posedge clk_final or negedge clk_final) begin
count = count + 1;
// the following assignment should trigger the CLKDATA warning
// because CLOCK signal is used as DATA in sequential block
/* verilator lint_off CLKDATA */
res <= clk_final;
/* verilator lint_on CLKDATA */
if ( count == 8'hf) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under The Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`timescale `time_scale_units / `time_scale_prec
import "DPI-C" function void dpii_check();
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
// verilator lint_off REALCVT
time digits = 5432109876.543210ns; // Will round to time units
realtime rdigits = 5432109876.543210ns; // Will round to time precision
time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double
// verilator lint_on REALCVT
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("- [%0t] tick\n", $time);
`endif
if ($time >= 60) begin
$write(":: In %m\n");
$printtimescale;
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
$timeformat(-9, 6, "ns", 16);
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
$write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n",
$time, $stime, $stime, $stime);
// verilator lint_off REALCVT
$write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n",
$time, $realtime, $realtime, $realtime);
// verilator lint_on REALCVT
dpii_check();
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
`include "lo_read.v"
/*
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125kHz, 0=136kHz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1MHz/1.09MHz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125kHz, max 255
// simulate 4 A/D cycles at 125kHz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 20:21:00 09/20/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: TF_BCD_Binary_Encoder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Binary to BCD Converter Test Bench
//
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_BCD_Binary_Encoder();
//
// Set the Binary Width and BCD Digit parameters
//
localparam BIN_WIDTH = 17;
localparam BDC_DIGITS = 5;
reg [BIN_WIDTH-1:0] BIN_DATA;
//
// System Clock Emulation
//
localparam CLK_RATE_HZ = 500000000; // 500 MHz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
reg CLK;
initial
begin
CLK = 1'b0;
forever #(CLK_HALF_PER) CLK = ~CLK;
end
//
// Unit Under Test: BCD_Binary_Encoder
//
reg RESET;
reg BCD_CONVERT;
wire BCD_DONE;
wire [3:0] bcd_out_0;
wire [3:0] bcd_out_1;
wire [3:0] bcd_out_2;
wire [3:0] bcd_out_3;
wire [3:0] bcd_out_4;
wire bcd_overflow;
BCD_Binary_Encoder
#(
.BIN_WIDTH( BIN_WIDTH ),
.BDC_DIGITS( BDC_DIGITS )
)
uut
(
// Input Signals
.CONVERT( BCD_CONVERT ),
.DONE( BCD_DONE ),
.BIN_IN( BIN_DATA ),
// BCD Data Output Signals
.BCD_OUT( { bcd_out_4, bcd_out_3, bcd_out_2, bcd_out_1, bcd_out_0 } ),
.BCD_OVERFLOW( bcd_overflow ),
// System Signals
.CLK( CLK ),
.RESET( RESET )
);
//
// Testing Procedure
//
integer i;
integer expected_value;
integer result_value;
integer total_errors;
reg error_status;
reg expected_overflow;
reg bcd_out_0_valid;
reg bcd_out_1_valid;
reg bcd_out_2_valid;
reg bcd_out_3_valid;
reg bcd_out_4_valid;
initial
begin
// Initialize Signals
RESET = 1'b1;
BCD_CONVERT = 1'b0;
BIN_DATA = {BIN_WIDTH{1'b0}};
expected_value = 0;
result_value = 0;
total_errors = 0;
error_status = 1'b0;
expected_overflow = 1'b0;
bcd_out_0_valid = 1'b0;
bcd_out_1_valid = 1'b0;
bcd_out_2_valid = 1'b0;
bcd_out_3_valid = 1'b0;
bcd_out_4_valid = 1'b0;
#500;
// Release the Reset
@(posedge CLK);
RESET = 1'b0;
#500;
// Start the Testing
for (i = 0; i < 2**BIN_WIDTH; i=i+1)
begin
// Pulse the Convert signal
@(posedge CLK);
BCD_CONVERT = 1'b1;
@(posedge CLK);
BCD_CONVERT = 1'b0;
// Wait for the Conversion to finish
@(posedge BCD_DONE);
// Wait till next Clock
@(posedge CLK);
//
// Verify the output BCD data
//
// Set Expected Value to Binary Input
if (BIN_DATA < 100000)
begin
expected_value = BIN_DATA; // Normal Value
expected_overflow = 1'b0;
end
else
begin
expected_value = BIN_DATA - 100000; // Overflow Value
expected_overflow = 1'b1;
end
// Compute Result value from BCD output
result_value = bcd_out_4 * 10000 + bcd_out_3 * 1000 + bcd_out_2 * 100 + bcd_out_1 * 10 + bcd_out_0;
// Check each BCD ouptut is valid
bcd_out_0_valid = bcd_out_0 >= 0 && bcd_out_0 < 10;
bcd_out_1_valid = bcd_out_0 >= 0 && bcd_out_0 < 10;
bcd_out_2_valid = bcd_out_0 >= 0 && bcd_out_0 < 10;
bcd_out_3_valid = bcd_out_0 >= 0 && bcd_out_0 < 10;
bcd_out_4_valid = bcd_out_0 >= 0 && bcd_out_0 < 10;
// Set Error Status
error_status = (expected_value != result_value) ||
!bcd_out_4_valid ||
!bcd_out_3_valid ||
!bcd_out_2_valid ||
!bcd_out_1_valid ||
!bcd_out_0_valid ||
expected_overflow != bcd_overflow;
// Report Test Results
$display("Test: [%05X] %01d %01d %01d %01d %01d : %s %s %s %s %s %s %s : %s",
BIN_DATA,
bcd_out_4,
bcd_out_3,
bcd_out_2,
bcd_out_1,
bcd_out_0,
expected_overflow == bcd_overflow ? "." : "X",
bcd_out_4_valid ? "." : "X",
bcd_out_3_valid ? "." : "X",
bcd_out_2_valid ? "." : "X",
bcd_out_1_valid ? "." : "X",
bcd_out_0_valid ? "." : "X",
expected_value == result_value ? "." : "X",
error_status ? "FAILURE!!!" : "Pass "
);
// Increment Error Count if an Error occured
if (error_status)
total_errors = total_errors + 1;
// Increment the Binary Data for the next Test
@(posedge CLK)
BIN_DATA = BIN_DATA + 1'b1;
end
$display("Testing Complete: %d Total Errors", total_errors);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [9:0] I1 = crc[9:0];
wire [9:0] I2 = crc[19:10];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] S; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.S (S[9:0]),
// Inputs
.I1 (I1[9:0]),
.I2 (I2[9:0]));
wire [63:0] result = {32'h0, 22'h0, S};
`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
S,
// Inputs
I1, I2
);
input [9:0] I1/*verilator public*/;
input [9:0] I2/*verilator public*/;
output reg [9:0] S/*verilator public*/;
always @(I1 or I2)
t2(I1,I2,S);
task t1;
input In1,In2;
output Sum;
Sum = In1 ^ In2;
endtask
task t2;
input[9:0] In1,In2;
output [9:0] Sum;
integer I;
begin
for (I=0;I<10;I=I+1)
t1(In1[I],In2[I],Sum[I]);
end
endtask
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
// Three basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
module ibyte_test;
parameter TRIALS = 100;
parameter MAX = 'h7fff;
reg [15:0] ar; // should it be "reg unsigned [7:0] aw"?
reg [15:0] ar_xz; // same as above here?
reg [15:0] ar_expected; // and here
shortint unsigned bu;
shortint unsigned bu_xz;
integer i;
assign bu = ar;
assign bu_xz = ar_xz;
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 16'b0 | bu_xz != 16'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// random numbers
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// with 'x injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect assigment to byte (when 'x): %b", bu);
$finish;
end
end
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead?
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<16; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [15:0] xz_expected (input [15:0] value_xz); // should it be "input unsigned [7:0] instead?
integer i;
begin
for (i=0; i<16; i=i+1)
begin
if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
value_xz[i] = 1'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_nios2_gen2_0_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEV",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEV",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEV",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
module top (
input clk,
input [15:0] wdata,
output [15:0] rdata,
input [7:0] addr
);
SB_RAM40_4K #(
.WRITE_MODE(0),
.READ_MODE(0)
) ram (
.RDATA(rdata),
.RADDR(addr),
.RCLK(clk),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(addr),
.WCLK(clk),
.WCLKE(1'b1),
.WDATA(wdata),
.WE(1'b1),
.MASK(16'b0)
);
defparam ram.INIT_0 = 256'h123456789abcdef00000dddd0000eeee00000012483569ac0111044400000001;
defparam ram.INIT_1 = 256'h56789abcdef123400000dddd0000eeee00000012483569ac0111044401000002;
defparam ram.INIT_2 = 256'habcdef12345678900000dddd0000eeee00000012483569ac0111044402000004;
defparam ram.INIT_3 = 256'h00000000000000000000dddd0000eeee00000012483569ac0111044403000008;
defparam ram.INIT_4 = 256'hffff000022220000444400006666000088880012483569ac0111044404000010;
defparam ram.INIT_5 = 256'hffff000022220000444400006666000088880012483569ac0111044405000020;
defparam ram.INIT_6 = 256'hffff000022220000444400006666000088880012483569ac0111044406000040;
defparam ram.INIT_7 = 256'hffff000022220000444400006666000088880012483569ac0111044407000080;
defparam ram.INIT_8 = 256'h0000111100003333000055550000777700000012483569ac0111044408000100;
defparam ram.INIT_9 = 256'h0000111100003333000055550000777700000012483569ac0111044409000200;
defparam ram.INIT_A = 256'h0000111100003333000055550000777700000012483569ac011104440a000400;
defparam ram.INIT_B = 256'h0000111100003333000055550000777700000012483569ac011104440b000800;
defparam ram.INIT_C = 256'h0123000099990000aaaa0000bbbb0000cccc0012483569ac011104440c001000;
defparam ram.INIT_D = 256'h4567000099990000aaaa0000bbbb0000cccc0012483569ac011104440d002000;
defparam ram.INIT_E = 256'h89ab000099990000aaaa0000bbbb0000cccc0012483569ac011104440e004000;
defparam ram.INIT_F = 256'hcdef000099990000aaaa0000bbbb0000cccc0012483569ac011104440f008000;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board ADV7181 video chip.*
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_adv7181 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter INPUT_CONTROL = 16'h0040;
parameter CHROMA_GAIN_1 = 16'h2df4;
parameter CHROMA_GAIN_2 = 16'h2e00;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Video Config Data
10 : data <= {8'h40, 16'h1500};
11 : data <= {8'h40, 16'h1741};
12 : data <= {8'h40, 16'h3a16};
13 : data <= {8'h40, 16'h5004};
14 : data <= {8'h40, 16'hc305};
15 : data <= {8'h40, 16'hc480};
16 : data <= {8'h40, 16'h0e80};
17 : data <= {8'h40, 16'h5004};
18 : data <= {8'h40, 16'h5218};
19 : data <= {8'h40, 16'h58ed};
20 : data <= {8'h40, 16'h77c5};
21 : data <= {8'h40, 16'h7c93};
22 : data <= {8'h40, 16'h7d00};
23 : data <= {8'h40, 16'hd048};
24 : data <= {8'h40, 16'hd5a0};
25 : data <= {8'h40, 16'hd7ea};
26 : data <= {8'h40, 16'he43e};
27 : data <= {8'h40, 16'hea0f};
28 : data <= {8'h40, 16'h3112};
29 : data <= {8'h40, 16'h3281};
30 : data <= {8'h40, 16'h3384};
31 : data <= {8'h40, 16'h37A0};
32 : data <= {8'h40, 16'he580};
33 : data <= {8'h40, 16'he603};
34 : data <= {8'h40, 16'he785};
35 : data <= {8'h40, 16'h5004};
36 : data <= {8'h40, 16'h5100};
37 : data <= {8'h40, INPUT_CONTROL};
38 : data <= {8'h40, 16'h1000};
39 : data <= {8'h40, 16'h0402};
40 : data <= {8'h40, 16'h0860};
41 : data <= {8'h40, 16'h0a18};
42 : data <= {8'h40, 16'h1100};
43 : data <= {8'h40, 16'h2b00};
44 : data <= {8'h40, 16'h2c8c};
45 : data <= {8'h40, CHROMA_GAIN_1};
46 : data <= {8'h40, CHROMA_GAIN_2};
47 : data <= {8'h40, 16'h2ff4};
48 : data <= {8'h40, 16'h30d2};
49 : data <= {8'h40, 16'h0e05};
default : data <= {8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2017 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NACITVEINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTIACITVE OF CACITVETRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CACITVENECTIACITVE WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* Translate one image size to another image size
* Only downsampling is supported
* TODO:
* Support Up Sampling
*
* Changes:
* 04/06/2017 DFM Initial Commit.
*/
`timescale 1ps / 1ps
module video_resizer #(
parameter DATAS_WIDTH = 24,
parameter PPFIFO_WIDTH = 9
)(
input clk,
input rst,
//Configuration Ports
input i_enable,
input i_reset,
input [31:0] i_video_in_size,
input [31:0] i_video_in_width,
input [31:0] i_video_in_height,
input [31:0] i_video_out_size,
input [31:0] i_video_out_width,
input [31:0] i_video_out_height,
input [31:0] i_video_in_start_x,
input [31:0] i_video_in_start_y,
input [DATAS_WIDTH - 1:0] i_fill_pixel_value,
//FIFO in Signals
output [1:0] o_fifo_in_rdy,
input [1:0] i_fifo_in_act,
input i_fifo_in_stb,
output [23:0] o_fifo_in_size,
input [DATAS_WIDTH - 1:0] i_fifo_in_data,
output o_fifo_out_rdy,
input i_fifo_out_act,
input i_fifo_out_stb,
output [23:0] o_fifo_out_size,
output [DATAS_WIDTH - 1:0] o_fifo_out_data
);
//local parameters
localparam INACTIVE = 0;
localparam ACITVE = 1;
localparam FLUSH = 2;
//registes/wires
reg [3:0] state;
reg [23:0] r_read_count;
reg [23:0] r_write_count;
reg [31:0] r_read_width_pos;
reg [31:0] r_read_height_pos;
reg [31:0] r_pixel_in_count;
reg [31:0] r_pixel_out_count;
reg r_read_stb;
wire w_read_rdy;
reg r_read_act;
wire [23:0] w_read_size;
wire [DATAS_WIDTH - 1: 0] w_read_data;
reg r_write_stb;
wire [1:0] w_write_rdy;
reg [1:0] r_write_act;
wire [23:0] w_write_size;
//reg [DATAS_WIDTH - 1: 0] r_write_data;
//wire [DATAS_WIDTH - 1: 0] w_write_data;
wire w_trans_valid;
//submodules
ppfifo #(
.DATA_WIDTH (DATAS_WIDTH ),
.ADDRESS_WIDTH (PPFIFO_WIDTH )
)fifo_in (
.reset (rst || i_reset ),
//write
.write_clock (clk ),
.write_ready (o_fifo_in_rdy ),
.write_activate (i_fifo_in_act ),
.write_fifo_size (o_fifo_in_size ),
.write_strobe (i_fifo_in_stb ),
.write_data (i_fifo_in_data ),
//read
.read_clock (clk ),
.read_strobe (r_read_stb ),
.read_ready (w_read_rdy ),
.read_activate (r_read_act ),
.read_count (w_read_size ),
.read_data (w_read_data )
);
ppfifo #(
.DATA_WIDTH (DATAS_WIDTH ),
.ADDRESS_WIDTH (PPFIFO_WIDTH )
)fifo_out (
.reset (rst || i_reset ),
//write
.write_clock (clk ),
.write_ready (w_write_rdy ),
.write_activate (r_write_act ),
.write_fifo_size (w_write_size ),
.write_strobe (r_write_stb ),
//.write_data (r_write_data ),
.write_data (w_read_data ),
//read
.read_clock (clk ),
.read_strobe (i_fifo_out_stb ),
.read_ready (o_fifo_out_rdy ),
.read_activate (i_fifo_out_act ),
.read_count (o_fifo_out_size ),
.read_data (o_fifo_out_data )
);
//assign w_write_data = (w_trans_valid) ? w_read_data : i_fill_pixel_value;
//asynchronous logic
assign w_trans_valid = (r_read_width_pos >= i_video_in_start_x) &&
(r_read_width_pos < (i_video_in_start_x + i_video_out_width))&&
(r_read_height_pos >= i_video_in_start_y) &&
(r_read_height_pos < (i_video_in_start_y + i_video_out_height));
//synchronous logic
always @ (posedge clk) begin
r_write_stb <= 0;
r_read_stb <= 0;
if (rst || i_reset) begin
r_read_width_pos <= 0;
r_read_height_pos <= 0;
r_pixel_out_count <= 0;
r_read_act <= 0;
r_write_act <= 0;
// r_write_data <= 0;
state <= INACTIVE;
r_read_count <= 0;
r_write_count <= 0;
r_pixel_in_count <= 0;
end
else begin
case (state)
INACTIVE: begin
r_read_width_pos <= 0;
r_read_height_pos <= 0;
r_pixel_in_count <= 0;
if (i_enable) begin
state <= ACITVE;
end
end
ACITVE: begin
//Both the FIFOs should be open, we can read and transfer between the two
if ((w_write_rdy > 0) && (r_write_act == 0)) begin
r_write_count <= 0;
if (w_write_rdy[0]) begin
r_write_act[0] <= 1;
end
else begin
r_write_act[1] <= 1;
end
end
if (w_read_rdy && !r_read_act) begin
r_read_count <= 0;
r_read_act <= 1;
end
if (r_read_act && (r_write_act > 0)) begin
//Both sides are open
if ((r_write_count < w_write_size) && (r_read_count < w_read_size)) begin
//Get data from the input
r_read_stb <= 1;
r_write_count <= r_write_count + 1;
r_read_count <= r_read_count + 1;
r_pixel_in_count <= r_pixel_in_count + 1;
if ((r_read_width_pos + 1) < i_video_in_width) begin
//Increment the pixel pos on the line
r_read_width_pos <= r_read_width_pos + 1;
end
else begin
//Reached the end of a line, go to the next line
r_read_width_pos <= 0;
r_read_height_pos <= r_read_height_pos + 1;
end
if (w_trans_valid) begin
r_write_stb <= 1;
// r_write_data <= w_read_data;
r_pixel_out_count <= r_pixel_out_count + 1;
end
end
else begin
//Either one or both FIFOs have been drained, drain the other one
if (r_write_count >= w_write_size) begin
r_write_act <= 0;
end
if (r_read_count >= w_read_size) begin
r_read_act <= 0;
end
end
end
if (r_pixel_out_count >= i_video_out_size) begin
state <= FLUSH;
end
end
FLUSH: begin
//Only one of the FIFOs is open, we need to fill it up or drain the rest
if (r_pixel_in_count < i_video_in_size) begin
if (w_read_rdy && !r_read_act) begin
r_read_count <= 0;
r_read_act <= 1;
end
else if (r_read_act) begin
if (r_read_count < w_read_size) begin
r_read_stb <= 1;
r_read_count <= r_read_count + 1;
r_pixel_in_count <= r_pixel_in_count + 1;
end
else begin
r_read_act <= 0;
end
end
end
if (r_pixel_out_count < i_video_out_size) begin
if ((w_write_rdy > 0) && (r_read_act == 0)) begin
r_write_count <= 0;
if (w_write_rdy[0]) begin
r_write_act[0] <= 1;
end
else begin
r_write_act[1] <= 1;
end
end
else if (r_write_act > 0) begin
if (r_write_count < w_write_size) begin
r_write_stb <= 1;
r_write_count <= r_write_count + 1;
r_pixel_out_count <= r_pixel_out_count + 1;
// r_write_data <= i_fill_pixel_value;
end
end
end
if ((r_pixel_in_count >= i_video_in_size) &&
(r_pixel_out_count >= i_video_out_size) ) begin
state <= INACTIVE;
r_write_act <= 0;
r_read_act <= 0;
end
end
default: begin
end
endcase
if (!i_enable) begin
state <= INACTIVE;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_v2
//SINGLE PRECISION PARAMETERS
//# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
RecursiveKOA #(.SW(SW+1), .Opt_FPGA_ASIC(0)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}), //Se le agrega el bit implicito
.Data_B_i({1'b1,Op_MY[SW-1:0]}), //Se le agrega el bit implicito
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_align_double( clock, resetn,
input_a_mantissa, input_a_exponent, input_a_sign,
input_b_mantissa, input_b_exponent, input_b_sign,
left_mantissa, left_exponent, left_sign,
right_mantissa, right_exponent, right_sign,
valid_in, valid_out, stall_in, stall_out,
enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input [55:0] input_a_mantissa;
input [11:0] input_a_exponent;
input input_a_sign;
input [55:0] input_b_mantissa;
input [11:0] input_b_exponent;
input input_b_sign;
output [55:0] left_mantissa;
output [11:0] left_exponent;
output left_sign;
output [55:0] right_mantissa;
output [11:0] right_exponent;
output right_sign;
input enable, valid_in, stall_in;
output valid_out, stall_out;
// This module aligns two floating point input values such that their exponents are equal,
// permitting a proper addition of the two numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_valid;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
wire c5_enable;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c5_stall;
// Cycle 1 - Determine the magnitude of both numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_r_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [13:0] c1_l_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [13:0] c1_r_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_l_sign, c1_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0]c1_matissa_r_greater, c1_matissas_equal;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exp_equal;
assign c1_enable = (HIGH_CAPACITY ? (~c1_stall | ~c1_valid) : enable);
assign stall_out = c1_stall & c1_valid;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_l_mantissa <= 56'dx;
c1_r_mantissa <= 56'dx;
c1_l_exponent <= 12'dx;
c1_r_exponent <= 12'dx;
c1_l_mantissa_nonzero <= 14'dx;
c1_r_mantissa_nonzero <= 14'dx;
c1_l_sign <= 1'bx;
c1_r_sign <= 1'bx;
c1_matissa_r_greater <= 2'bxx;
c1_exp_diff <= 12'dx;
c1_exp_equal <= 1'bx;
c1_matissas_equal <= 2'bxx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if ((FINITE_MATH_ONLY == 0) && (input_a_exponent[11] || input_b_exponent[11]))
begin
c1_exp_diff <= 12'd0;
c1_exp_equal <= 1'b1;
end
else
begin
c1_exp_diff <= {1'b0, input_a_exponent[10:0]} - {1'b0, input_b_exponent[10:0]};
c1_exp_equal <= (input_a_exponent[10:0] == input_b_exponent[10:0]);
end
c1_l_mantissa <= input_a_mantissa;
c1_r_mantissa <= input_b_mantissa;
c1_l_exponent <= input_a_exponent;
c1_r_exponent <= input_b_exponent;
c1_l_mantissa_nonzero <= {input_a_exponent[11] ? (|input_a_mantissa[54:52]) : (|input_a_mantissa[55:52]), |input_a_mantissa[51:48], |input_a_mantissa[47:44], |input_a_mantissa[43:40], |input_a_mantissa[39:36], |input_a_mantissa[35:32], |input_a_mantissa[31:28], |input_a_mantissa[27:24], |input_a_mantissa[23:20], |input_a_mantissa[19:16], |input_a_mantissa[15:12], |input_a_mantissa[11:8], |input_a_mantissa[7:3], |input_a_mantissa[2:0]};
c1_r_mantissa_nonzero <= {input_b_exponent[11] ? (|input_b_mantissa[54:52]) : (|input_b_mantissa[55:52]), |input_b_mantissa[51:48], |input_b_mantissa[47:44], |input_b_mantissa[43:40], |input_b_mantissa[39:36], |input_b_mantissa[35:32], |input_b_mantissa[31:28], |input_b_mantissa[27:24], |input_b_mantissa[23:20], |input_b_mantissa[19:16], |input_b_mantissa[15:12], |input_b_mantissa[11:8], |input_b_mantissa[7:3], |input_b_mantissa[2:0]};
c1_l_sign <= input_a_sign;
c1_r_sign <= input_b_sign;
c1_matissa_r_greater <= {{1'b0, input_b_mantissa[55:28]} > {1'b0, input_a_mantissa[55:28]}, {1'b0, input_b_mantissa[27:0]} > {1'b0, input_a_mantissa[27:0]} };
c1_matissas_equal <= {(input_b_mantissa[55:28] == input_a_mantissa[55:28]),(input_b_mantissa[27:0] == input_a_mantissa[27:0])};
end
end
// Cycle 2 - Swap numbers such that the larger one is the left and the smaller one is the right.
// If the numbers are equal in magnitude, then pick the positive one to be the left one.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c2_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c2_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c2_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_l_sign, c2_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c2_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_r_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_lr_mantissa_info;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_diff_signs;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c2_exponents;
assign c2_enable = (HIGH_CAPACITY ? (~c2_stall | ~c2_valid) : enable);
assign c1_stall = c2_stall & c2_valid;
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_l_mantissa <= 56'dx;
c2_r_mantissa <= 56'dx;
c2_l_exponent <= 12'dx;
c2_l_sign <= 1'bx;
c2_r_sign <= 1'bx;
c2_r_mantissa_nonzero <= 4'dx;
c2_lr_mantissa_info <= 4'dx;
c2_diff_signs <= 1'bx;
c2_exponents <= 2'bxx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_diff_signs <= c1_l_sign ^ c1_r_sign;
c2_exponents <= {c1_l_exponent[11], c1_r_exponent[11]};
// Here we account for denorms
if (c1_exp_diff[11])
begin
c2_exp_diff <= {12{c1_r_mantissa[55] ^ c1_l_mantissa[55]}} - c1_exp_diff;
end
else
begin
if (FINITE_MATH_ONLY == 0)
c2_exp_diff <= (c1_l_exponent[11] || c1_r_exponent[11]) ? c1_exp_diff : c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
else
c2_exp_diff <= c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
end
if ((c1_l_exponent[11] || c1_r_exponent[11]) && (FINITE_MATH_ONLY == 0))
begin
// Here we handle the cases of NaN and Inf values.
// I need to split this into two stages, otherwise the logic is really complicated.
// When testing for non-zero mantissa we need to check that the exponent is maxed out.
// We use c3_lr_mantissa_info to convey this information to the next cycle.
c2_lr_mantissa_info <= {|c1_l_mantissa_nonzero[13:7], |c1_l_mantissa_nonzero[6:0], |c1_r_mantissa_nonzero[13:7], |c1_r_mantissa_nonzero[6:0]};
c2_l_mantissa[55] <= 1'b1; // Inf
c2_l_mantissa[54:0] <= 55'd0; // Inf
c2_r_mantissa <= 56'd0;
c2_l_exponent <= 12'hfff;
c2_l_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
else
if ((&c1_matissas_equal) & c1_exp_equal & ~c1_r_sign |
(c1_exp_equal & (c1_matissa_r_greater[1] | c1_matissas_equal[1] & c1_matissa_r_greater[0])) | (c1_exp_diff[11]))
begin
// Swap left and right inputs
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_r_mantissa;
c2_r_mantissa <= c1_l_mantissa;
c2_l_exponent <= c1_r_exponent;
c2_l_sign <= c1_r_sign;
c2_r_sign <= c1_l_sign;
c2_r_mantissa_nonzero <= {|c1_l_mantissa_nonzero[13:12], |c1_l_mantissa_nonzero[11:8], |c1_l_mantissa_nonzero[7:4], |c1_l_mantissa_nonzero[3:0]};
end
else
begin
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_l_mantissa;
c2_r_mantissa <= c1_r_mantissa;
c2_l_exponent <= c1_l_exponent;
c2_l_sign <= c1_l_sign;
c2_r_sign <= c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
end
end
end
else
begin
// Do not register this stage in low-latency mode.
always @(*)
begin
c2_valid <= c1_valid;
c2_diff_signs <= c1_l_sign ^ c1_r_sign;
c2_exponents <= {c1_l_exponent[11], c1_r_exponent[11]};
// Here we account for denorms
if (c1_exp_diff[11])
begin
c2_exp_diff <= {12{c1_r_mantissa[55] ^ c1_l_mantissa[55]}} - c1_exp_diff;
end
else
begin
if (FINITE_MATH_ONLY == 0)
c2_exp_diff <= (c1_l_exponent[11] || c1_r_exponent[11]) ? c1_exp_diff : c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
else
c2_exp_diff <= c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
end
if ((c1_l_exponent[11] || c1_r_exponent[11]) && (FINITE_MATH_ONLY == 0))
begin
// Here we handle the cases of NaN and Inf values.
// I need to split this into two stages, otherwise the logic is really complicated.
// When testing for non-zero mantissa we need to check that the exponent is maxed out.
// We use c3_lr_mantissa_info to convey this information to the next cycle.
c2_lr_mantissa_info <= {|c1_l_mantissa_nonzero[13:7], |c1_l_mantissa_nonzero[6:0], |c1_r_mantissa_nonzero[13:7], |c1_r_mantissa_nonzero[6:0]};
c2_l_mantissa[55] <= 1'b1; // Inf
c2_l_mantissa[54:0] <= 55'd0; // Inf
c2_r_mantissa <= 56'd0;
c2_l_exponent <= 12'hfff;
c2_l_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
else
if ((&c1_matissas_equal) & c1_exp_equal & ~c1_r_sign |
(c1_exp_equal & (c1_matissa_r_greater[1] | c1_matissas_equal[1] & c1_matissa_r_greater[0])) | (c1_exp_diff[11]))
begin
// Swap left and right inputs
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_r_mantissa;
c2_r_mantissa <= c1_l_mantissa;
c2_l_exponent <= c1_r_exponent;
c2_l_sign <= c1_r_sign;
c2_r_sign <= c1_l_sign;
c2_r_mantissa_nonzero <= {|c1_l_mantissa_nonzero[13:12], |c1_l_mantissa_nonzero[11:8], |c1_l_mantissa_nonzero[7:4], |c1_l_mantissa_nonzero[3:0]};
end
else
begin
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_l_mantissa;
c2_r_mantissa <= c1_r_mantissa;
c2_l_exponent <= c1_l_exponent;
c2_l_sign <= c1_l_sign;
c2_r_sign <= c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
end
end
endgenerate
// Cycle 3 - shift data in the right input as much as needed to match exponents
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c3_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c3_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c3_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_l_sign, c3_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c3_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_clear_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_sticky_right;
assign c3_enable = (HIGH_CAPACITY ? (~c3_stall | ~c3_valid) : enable);
assign c2_stall = c3_stall & c3_valid;
reg [1:0] c3_select;
always@(*)
begin
if (c2_exp_diff >= 9'd48)
c3_select = 2'b11;
else if (c2_exp_diff >= 9'd32)
c3_select = 2'b10;
else if (c2_exp_diff >= 9'd16)
c3_select = 2'b01;
else
c3_select = 2'b00;
end
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_l_mantissa <= 27'dx;
c3_r_mantissa <= 27'dx;
c3_l_exponent <= 9'dx;
c3_l_sign <= 1'bx;
c3_r_sign <= 1'bx;
c3_clear_right <= 1'bx;
c3_sticky_right <= 1'bx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
// A number becomes a NaN when
// 1. it is a sum of positive and negative infinities
// 2. one of the numbers is a NaN
if ((FINITE_MATH_ONLY == 0) && ((c2_exponents[1] & c2_exponents[0] & ~(|c2_lr_mantissa_info) & c2_diff_signs) ||
(c2_exponents[1] & (|c2_lr_mantissa_info[3:2]) | c2_exponents[0] & (|c2_lr_mantissa_info[1:0]))))
c3_l_mantissa[54] <= 1'b1; // Make a number into a NaN if it was infinity before.
else
c3_l_mantissa[54] <= c2_l_mantissa[54];
c3_l_mantissa[55] <= c2_l_mantissa[55];
c3_l_mantissa[53:0] <= c2_l_mantissa[53:0];
c3_l_exponent <= c2_l_exponent;
c3_l_sign <= c2_l_sign;
c3_r_sign <= c2_r_sign;
c3_clear_right <= (c2_exp_diff >= 12'd56);
if (REMOVE_STICKY == 1)
c3_sticky_right <= 1'b0;
else
c3_sticky_right <= |c2_r_mantissa_nonzero;
c3_exp_diff <= c2_exp_diff - {1'b0, c3_select, 4'd0};
case(c3_select)
2'b11:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {48'd0, c2_r_mantissa[55:49], c2_r_mantissa[48]};
else
c3_r_mantissa <= {48'd0, c2_r_mantissa[55:49], c2_r_mantissa[48] | (|c2_r_mantissa_nonzero[2:0])};
end
2'b10:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {32'd0, c2_r_mantissa[55:33], c2_r_mantissa[32]};
else
c3_r_mantissa <= {32'd0, c2_r_mantissa[55:33], c2_r_mantissa[32] | (|c2_r_mantissa_nonzero[1:0])};
end
2'b01:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {16'd0, c2_r_mantissa[55:17], c2_r_mantissa[16]};
else
c3_r_mantissa <= {16'd0, c2_r_mantissa[55:17], c2_r_mantissa[16] | (c2_r_mantissa_nonzero[0])};
end
2'b00:
begin
c3_r_mantissa <= c2_r_mantissa;
end
endcase
end
end
// Cycle 4 - Shift by 12, 8 or 4.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c4_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c4_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c4_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c4_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_l_sign, c4_r_sign;
assign c4_enable = (HIGH_CAPACITY ? (~c4_stall | ~c4_valid) : enable);
assign c3_stall = c4_stall & c4_valid;
reg c4_sticky_bit;
always@(*)
begin
if (REMOVE_STICKY == 1)
c4_sticky_bit = 1'b0;
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_sticky_bit = |c3_r_mantissa[11:0];
2'h2: c4_sticky_bit = |c3_r_mantissa[7:0];
2'h1: c4_sticky_bit = |c3_r_mantissa[3:0];
2'h0: c4_sticky_bit = 1'b0;
endcase
end
end
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_l_mantissa <= 56'dx;
c4_r_mantissa <= 56'dx;
c4_l_exponent <= 12'dx;
c4_l_sign <= 1'bx;
c4_r_sign <= 1'bx;
c4_exp_diff <= 2'bxx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_l_mantissa <= c3_l_mantissa;
c4_l_exponent <= c3_l_exponent;
c4_l_sign <= c3_l_sign;
c4_r_sign <= c3_r_sign;
c4_exp_diff <= c3_exp_diff[1:0];
if (c3_clear_right)
begin
c4_r_mantissa <= c3_sticky_right ? 56'd1 : 56'd0;
end
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_r_mantissa <= {12'd0, c3_r_mantissa[55:13], c3_r_mantissa[12] | c4_sticky_bit};
2'h2: c4_r_mantissa <= {8'd0, c3_r_mantissa[55:9], c3_r_mantissa[8] | c4_sticky_bit};
2'h1: c4_r_mantissa <= {4'd0, c3_r_mantissa[55:5], c3_r_mantissa[4] | c4_sticky_bit};
2'h0: c4_r_mantissa <= c3_r_mantissa;
endcase
end
end
end
end
else
begin
// in low latency mode do not register this stage.
always @(*)
begin
c4_valid <= c3_valid;
c4_l_mantissa <= c3_l_mantissa;
c4_l_exponent <= c3_l_exponent;
c4_l_sign <= c3_l_sign;
c4_r_sign <= c3_r_sign;
c4_exp_diff <= c3_exp_diff[1:0];
if (c3_clear_right)
begin
c4_r_mantissa <= c3_sticky_right ? 56'd1 : 56'd0;
end
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_r_mantissa <= {12'd0, c3_r_mantissa[55:13], c3_r_mantissa[12] | c4_sticky_bit};
2'h2: c4_r_mantissa <= {8'd0, c3_r_mantissa[55:9], c3_r_mantissa[8] | c4_sticky_bit};
2'h1: c4_r_mantissa <= {4'd0, c3_r_mantissa[55:5], c3_r_mantissa[4] | c4_sticky_bit};
2'h0: c4_r_mantissa <= c3_r_mantissa;
endcase
end
end
end
endgenerate
// Cycle 5 - Complete the shifting of data and produce a final result
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c5_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c5_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c5_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_l_sign, c5_r_sign;
assign c5_enable = (HIGH_CAPACITY ? (~c5_stall | ~c5_valid) : enable);
assign c4_stall = c5_stall & c5_valid;
reg c5_sticky_bit;
always@(*)
begin
case(c4_exp_diff)
2'h3: c5_sticky_bit = |c4_r_mantissa[2:0];
2'h2: c5_sticky_bit = |c4_r_mantissa[1:0];
2'h1: c5_sticky_bit = c4_r_mantissa[0];
2'h0: c5_sticky_bit = 1'b0;
endcase
end
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_l_mantissa <= 27'dx;
c5_r_mantissa <= 27'dx;
c5_l_exponent <= 9'dx;
c5_l_sign <= 1'bx;
c5_r_sign <= 1'bx;
c5_valid <= 1'b0;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_l_mantissa <= c4_l_mantissa;
c5_l_exponent <= c4_l_exponent;
c5_l_sign <= c4_l_sign;
c5_r_sign <= c4_r_sign;
c5_r_mantissa <= (c4_r_mantissa >> c4_exp_diff) | c5_sticky_bit;
end
end
assign c5_stall = stall_in;
assign valid_out = c5_valid;
assign left_mantissa = c5_l_mantissa;
assign left_exponent = c5_l_exponent;
assign left_sign = c5_l_sign;
assign right_mantissa = c5_r_mantissa;
assign right_exponent = c5_l_exponent;
assign right_sign = c5_r_sign;
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:00:10 11/17/2012
// Design Name:
// Module Name: CRC8_gen
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CRC8_gen(
input [47:0] D,
output [7:0] NewCRC
);
assign NewCRC[0] = D[46] ^ D[42] ^ D[41] ^ D[37] ^ D[36] ^ D[35] ^ D[34] ^
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[27] ^ D[26] ^ D[24] ^
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
D[8] ^ D[7] ^ D[6] ^ D[3] ^ D[1] ^ D[0];
assign NewCRC[1] = D[47] ^ D[43] ^ D[42] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^
D[34] ^ D[32] ^ D[31] ^ D[30] ^ D[28] ^ D[27] ^ D[25] ^
D[21] ^ D[19] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
D[9] ^ D[8] ^ D[7] ^ D[4] ^ D[2] ^ D[1];
assign NewCRC[2] = D[46] ^ D[44] ^ D[43] ^ D[42] ^ D[41] ^ D[39] ^ D[38] ^
D[34] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[24] ^ D[22] ^
D[19] ^ D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[7] ^ D[6] ^
D[5] ^ D[2] ^ D[1] ^ D[0];
assign NewCRC[3] = D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[39] ^
D[35] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[25] ^ D[23] ^
D[20] ^ D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[8] ^ D[7] ^
D[6] ^ D[3] ^ D[2] ^ D[1];
assign NewCRC[4] = D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[37] ^ D[35] ^
D[33] ^ D[32] ^ D[31] ^ D[27] ^ D[21] ^ D[20] ^ D[18] ^
D[17] ^ D[14] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[6] ^
D[4] ^ D[2] ^ D[1] ^ D[0];
assign NewCRC[5] = D[46] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ D[36] ^
D[34] ^ D[33] ^ D[32] ^ D[28] ^ D[22] ^ D[21] ^ D[19] ^
D[18] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[7] ^
D[5] ^ D[3] ^ D[2] ^ D[1];
assign NewCRC[6] = D[47] ^ D[45] ^ D[44] ^ D[41] ^ D[39] ^ D[36] ^ D[31] ^
D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[23] ^ D[22] ^ D[19] ^
D[18] ^ D[17] ^ D[11] ^ D[7] ^ D[4] ^ D[2] ^ D[1] ^
D[0];
assign NewCRC[7] = D[45] ^ D[41] ^ D[40] ^ D[36] ^ D[35] ^ D[34] ^ D[33] ^
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ D[23] ^
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^
D[7] ^ D[6] ^ D[5] ^ D[2] ^ D[0];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 15326 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w511,
w8176,
w8175,
w7663,
w15326;
assign w1 = i_data0;
assign w15326 = w7663 << 1;
assign w511 = w512 - w1;
assign w512 = w1 << 9;
assign w7663 = w8175 - w512;
assign w8175 = w8176 - w1;
assign w8176 = w511 << 4;
assign o_data0 = w15326;
//multiplier_block area estimate = 5006.23186995147;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAM64X1D.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 01/18/08 - Add support for negative setup/hold timing check (CR457308).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM64X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output DPO,
output SPO,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input D,
input DPRA0,
input DPRA1,
input DPRA2,
input DPRA3,
input DPRA4,
input DPRA5,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM64X1D";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire D_in;
wire WCLK_in;
wire WE_in;
wire [5:0] A_in;
wire [5:0] DPRA_in;
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [5:0] A_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign A_in = A_dly;
assign D_in = D_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign A_in = {A5, A4, A3, A2, A1, A0};
assign D_in = D;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign DPRA_in = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [63:0] mem;
initial
mem = INIT;
assign DPO = mem[DPRA_in];
assign SPO = mem[A_in];
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A0 => SPO) = (0:0:0, 0:0:0);
(A1 => SPO) = (0:0:0, 0:0:0);
(A2 => SPO) = (0:0:0, 0:0:0);
(A3 => SPO) = (0:0:0, 0:0:0);
(A4 => SPO) = (0:0:0, 0:0:0);
(A5 => SPO) = (0:0:0, 0:0:0);
(DPRA0 => DPO) = (0:0:0, 0:0:0);
(DPRA1 => DPO) = (0:0:0, 0:0:0);
(DPRA2 => DPO) = (0:0:0, 0:0:0);
(DPRA3 => DPO) = (0:0:0, 0:0:0);
(DPRA4 => DPO) = (0:0:0, 0:0:0);
(DPRA5 => DPO) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module ad_pnmon (
// adc interface
adc_clk,
adc_valid_in,
adc_data_in,
adc_data_pn,
// pn out of sync and error
adc_pn_oos,
adc_pn_err);
// parameters
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adc interface
input adc_clk;
input adc_valid_in;
input [DW:0] adc_data_in;
input [DW:0] adc_data_pn;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg adc_valid_d = 'd0;
reg adc_pn_match_d = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg adc_pn_oos = 'd0;
reg [ 3:0] adc_pn_oos_count = 'd0;
// internal signals
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// make sure data is not 0, sequence will fail.
assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn oos and counters (16 to clear and set).
always @(posedge adc_clk) begin
adc_valid_d <= adc_valid_in;
adc_pn_match_d <= adc_pn_match_d_s;
adc_pn_match_z <= adc_pn_match_z_s;
if (adc_valid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
adc_pn_oos <= ~adc_pn_oos;
end
if (adc_pn_update_s == 1'b1) begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
end else begin
adc_pn_oos_count <= 'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is paula
//
// 06-03-2005 -started coding
// 19-03-2005 -added interupt controller and uart
// 04-09-2005 -added blitter finished interrupt
// 19-10-2005 -removed cck (color clock enable) input
// -removed intb signal
// -added sof signal
// 23-10-2005 -added dmal signal
// -added paula part of DMACON
// 21-11-2005 -added floppy controller
// -added ADKCON/ADCONR registers
// -added local horbeam counter
// 27-11-2005 -den is now active low (_den)
// -some typo's fixed
// 11-12-2005 -disable syncword interrupt
// 13-12-2005 -enable syncword interrupt
// 27-12-2005 -cleaned up code
// 28-12-2005 -added audio module
// 03-01-2006 -added dmas to avoid interference with copper cycles
// 07-01-2006 -added dmas for disk controller
// 06-02-2006 -added user disk control input
// 03-07-2007 -moved interrupt controller and uart to this file to reduce number of sourcefiles
// JB:
// 2008-09-24 - code clean-up
// - added support for floppy _sel[3:1] signals
// 2008-09-30 - removed user disk control input
// 2008-10-12 - source clean-up
// 2009-01-08 - added audio_dmal, audio_dmas
// 2009-03-08 - removed horbeam counter and sol
// - added strhor
// 2009-04-05 - code clean-up
// 2009-05-24 - clean-up & renaming
// 2009-07-10 - implementation of intreq[14] (Unreal needs it)
// 2009-11-14 - added 28 MHz clock input for sigma-delta modulator
// RK:
// 2013-03-21 - translated & added a new more compatible uart core written by [email protected]
module Paula
(
// system bus interface
input clk, //bus clock
input clk28m, // 28 MHz system clock
input cck, //colour clock enable
input reset, //reset
input [8:1] reg_address_in, //register address inputs
input [15:0] data_in, //bus data in
output [15:0] data_out, //bus data out
//serial (uart)
output txd, //serial port transmitted data
input rxd, //serial port received data
//interrupts and dma
input ntsc, // PAL/NTSC mode
input sof, // start of vertical frame
input strhor, //start of video line (latches audio DMA requests)
input vblint, // vertical blanking interrupt trigger
input int2, //level 2 interrupt
input int3, //level 3 interrupt
input int6, //level 6 interrupt
output [2:0] _ipl, //m68k interrupt request
output [3:0] audio_dmal, //audio dma data transfer request (to Agnus)
output [3:0] audio_dmas, //audio dma location pointer restart (to Agnus)
output disk_dmal, //disk dma data transfer request (to Agnus)
output disk_dmas, //disk dma special request (to Agnus)
//disk control signals from cia and user
input _step, //step heads of disk
input direc, //step heads direction
input [3:0] _sel, //disk select
input side, //upper/lower disk head
input _motor, //disk motor control
output _track0, //track zero detect
output _change, //disk has been removed from drive
output _ready, //disk is ready
output _wprot, //disk is write-protected
output index, // disk index pulse
output disk_led, //disk activity LED
//flash drive host controller interface (SPI)
input _scs, //async. serial data enable
input sdi, //async. serial data input
output sdo, //async. serial data output
input sck, //async. serial data clock
//audio outputs
output left, //audio bitstream left
output right, //audio bitstream right
output [14:0]ldata, //left DAC data
output [14:0]rdata, //right DAC data
// system configuration
input [1:0] floppy_drives, //number of extra floppy drives
// direct sector read from SD card
input direct_scs, //spi select line for direct transfers from SD card
input direct_sdi, //spi data line for direct transfers from SD card
// emulated Hard Disk Drive signals
input hdd_cmd_req, // command request
input hdd_dat_req, // data request
output [2:0] hdd_addr, // task file register address
output [15:0] hdd_data_out, // data bus output
input [15:0] hdd_data_in, // data bus input
output hdd_wr, // task file write enable
output hdd_status_wr, // drive status write enable
output hdd_data_wr, // data port write enable
output hdd_data_rd, // data port read enable
// fifo / track display
output [7:0]trackdisp,
output [13:0]secdisp,
output floppy_fwr,
output floppy_frd
);
//--------------------------------------------------------------------------------------
//register names and addresses
parameter DMACON = 9'h096;
parameter ADKCON = 9'h09e;
parameter ADKCONR = 9'h010;
//local signals
reg [4:0] dmacon; //dmacon paula bits
reg dmaen; //master dma enable
reg [14:0] adkcon; //audio and disk control register
wire [15:0] uartdata_out; //UART data out
wire [15:0] intdata_out; //interrupt controller data out
wire [15:0] diskdata_out; //disk controller data out
wire [15:0] adkconr; //ADKCONR register data out
wire rbfmirror; //rbf mirror (from uart to interrupt controller)
wire rxint; //uart rx interrupt request
wire txint; //uart tx interrupt request
wire blckint; //disk block finished interrupt
wire syncint; //disk syncword match interrupt
wire [3:0] audint; //audio channels 0,1,2,3 interrupt request
wire [3:0] audpen; //audio channels 0,1,2,3 interrupt pending
wire [3:0] auden; //audio channels 0,1,2,3 dma enable
wire dsken; //disk dma enable
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
//data_out multiplexer
assign data_out = uartdata_out | intdata_out | diskdata_out | adkconr;
//--------------------------------------------------------------------------------------
//DMACON register write
//NOTE: this register is also present in the Agnus module,
//there DMACONR (read) is implemented
always @(posedge clk)
if (reset) begin
dmaen <= 0;
dmacon <= 5'd0;
end else if (reg_address_in[8:1]==DMACON[8:1]) begin
if (data_in[15])
{dmaen,dmacon[4:0]} <= {dmaen,dmacon[4:0]} | {data_in[9],data_in[4:0]};
else
{dmaen,dmacon[4:0]} <= {dmaen,dmacon[4:0]} & (~{data_in[9],data_in[4:0]});
end
//assign disk and audio dma enable bits
assign dsken = dmacon[4] & dmaen;
assign auden[3] = dmacon[3] & dmaen;
assign auden[2] = dmacon[2] & dmaen;
assign auden[1] = dmacon[1] & dmaen;
assign auden[0] = dmacon[0] & dmaen;
//--------------------------------------------------------------------------------------
//ADKCON register write
always @(posedge clk)
if (reset)
adkcon <= 15'd0;
else if (reg_address_in[8:1]==ADKCON[8:1])
begin
if (data_in[15])
adkcon[14:0] <= adkcon[14:0] | data_in[14:0];
else
adkcon[14:0] <= adkcon[14:0] & (~data_in[14:0]);
end
//ADKCONR register
assign adkconr[15:0] = (reg_address_in[8:1]==ADKCONR[8:1]) ? {1'b0,adkcon[14:0]} : 16'h0000;
//--------------------------------------------------------------------------------------
//instantiate uart
uart pu1
(
.clk(clk),
.reset(reset),
.rga_i(reg_address_in),
.data_i(data_in),
.data_o(uartdata_out),
.uartbrk(adkcon[11]),
.rbfmirror(rbfmirror),
.rxint(rxint),
.txint(txint),
.rxd(rxd),
.txd(txd)
);
//instantiate interrupt controller
intcontroller pi1
(
.clk(clk),
.reset(reset),
.reg_address_in(reg_address_in),
.data_in(data_in),
.data_out(intdata_out),
.rxint(rxint),
.txint(txint),
.vblint(vblint),
.int2(int2),
.int3(int3),
.int6(int6),
.blckint(blckint),
.syncint(syncint),
.audint(audint),
.audpen(audpen),
.rbfmirror(rbfmirror),
._ipl(_ipl)
);
//instantiate floppy controller / flashdrive host interface
floppy pf1
(
.clk(clk),
.reset(reset),
.ntsc(ntsc),
.sof(sof),
.enable(dsken),
.reg_address_in(reg_address_in),
.data_in(data_in),
.data_out(diskdata_out),
.dmal(disk_dmal),
.dmas(disk_dmas),
._step(_step),
.direc(direc),
._sel(_sel),
.side(side),
._motor(_motor),
._track0(_track0),
._change(_change),
._ready(_ready),
._wprot(_wprot),
.index(index),
.blckint(blckint),
.syncint(syncint),
.wordsync(adkcon[10]),
._scs(_scs),
.sdi(sdi),
.sdo(sdo),
.sck(sck),
.disk_led(disk_led),
.floppy_drives(floppy_drives),
.direct_scs(direct_scs),
.direct_sdi(direct_sdi),
.hdd_cmd_req(hdd_cmd_req),
.hdd_dat_req(hdd_dat_req),
.hdd_addr(hdd_addr),
.hdd_data_out(hdd_data_out),
.hdd_data_in(hdd_data_in),
.hdd_wr(hdd_wr),
.hdd_status_wr(hdd_status_wr),
.hdd_data_wr(hdd_data_wr),
.hdd_data_rd(hdd_data_rd),
// fifo / track display
.trackdisp(trackdisp),
.secdisp(secdisp),
.floppy_fwr (floppy_fwr),
.floppy_frd (floppy_frd)
);
//instantiate audio controller
audio ad1
(
.clk(clk),
.clk28m(clk28m),
.cck(cck),
.reset(reset),
.strhor(strhor),
.reg_address_in(reg_address_in),
.data_in(data_in),
.dmaena(auden[3:0]),
.audint(audint[3:0]),
.audpen(audpen),
.dmal(audio_dmal),
.dmas(audio_dmas),
.left(left),
.right(right),
.ldata(ldata),
.rdata(rdata)
);
//--------------------------------------------------------------------------------------
endmodule
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
// interrupt controller //
module intcontroller
(
input clk, //bus clock
input reset, //reset
input [8:1] reg_address_in, //register address inputs
input [15:0] data_in, //bus data in
output [15:0] data_out, //bus data out
input rxint, //uart receive interrupt
input txint, //uart transmit interrupt
input vblint, // start of video frame
input int2, //level 2 interrupt
input int3, //level 3 interrupt
input int6, //level 6 interrupt
input blckint, //disk block finished interrupt
input syncint, //disk syncword match interrupt
input [3:0] audint, //audio channels 0,1,2,3 interrupts
output [3:0] audpen, //mirror of audio interrupts for audio controller
output rbfmirror, //mirror of serial receive interrupt for uart SERDATR register
output reg [2:0] _ipl //m68k interrupt request
);
//register names and addresses
parameter INTENAR = 9'h01c;
parameter INTREQR = 9'h01e;
parameter INTENA = 9'h09a;
parameter INTREQ = 9'h09c;
//local signals
reg [14:0] intena; //int enable write register
reg [15:0] intenar; //int enable read register
reg [14:0] intreq; //int request register
reg [15:0] intreqr; //int request readback
//rbf mirror out
assign rbfmirror = intreq[11];
//audio mirror out
assign audpen[3:0] = intreq[10:7];
//data_out multiplexer
assign data_out = intenar | intreqr;
//intena register
always @(posedge clk)
if (reset)
intena <= 0;
else if (reg_address_in[8:1]==INTENA[8:1])
begin
if (data_in[15])
intena[14:0] <= intena[14:0] | data_in[14:0];
else
intena[14:0] <= intena[14:0] & (~data_in[14:0]);
end
//intenar register
always @(reg_address_in or intena)
if (reg_address_in[8:1]==INTENAR[8:1])
intenar[15:0] = {1'b0,intena[14:0]};
else
intenar = 16'd0;
//intreqr register
always @(reg_address_in or intreq)
if (reg_address_in[8:1]==INTREQR[8:1])
intreqr[15:0] = {1'b0,intreq[14:0]};
else
intreqr = 16'd0;
// control all interrupts, intterupts are registered at the rising edge of clk
reg [14:0]tmp;
always @(reg_address_in or data_in or intreq)
//check if we are addressed and some bits must change
//(generate mask tmp[13:0])
if (reg_address_in[8:1]==INTREQ[8:1])
begin
if (data_in[15])
tmp[14:0] = intreq[14:0] | data_in[14:0];
else
tmp[14:0] = intreq[14:0] & (~data_in[14:0]);
end
else
tmp[14:0] = intreq[14:0];
always @(posedge clk)
begin
if (reset)//synchronous reset
intreq <= 0;
else
begin
//transmit buffer empty interrupt
intreq[0] <= tmp[0] | txint;
//diskblock finished
intreq[1] <= tmp[1] | blckint;
//software interrupt
intreq[2] <= tmp[2];
//I/O ports and timers
intreq[3] <= tmp[3] | int2;
//Copper
intreq[4] <= tmp[4];
//start of vertical blank
intreq[5] <= tmp[5] | vblint;
//blitter finished
intreq[6] <= tmp[6] | int3;
//audio channel 0
intreq[7] <= tmp[7] | audint[0];
//audio channel 1
intreq[8] <= tmp[8] | audint[1];
//audio channel 2
intreq[9] <= tmp[9] | audint[2];
//audio channel 3
intreq[10] <= tmp[10] | audint[3];
//serial port receive interrupt
intreq[11] <= tmp[11] | rxint;
//disk sync register matches disk data
intreq[12] <= tmp[12] | syncint;
//external interrupt
intreq[13] <= tmp[13] | int6;
//undocumented interrupt
intreq[14] <= tmp[14];
end
end
//create m68k interrupt request signals
reg [14:0]intreqena;
always @(intena or intreq)
begin
//and int enable and request signals together
if (intena[14])
intreqena[14:0] = intreq[14:0] & intena[14:0];
else
intreqena[14:0] = 15'b000_0000_0000_0000;
end
//interrupt priority encoder
always @(posedge clk)
begin
casez (intreqena[14:0])
15'b1?????????????? : _ipl <= 1;
15'b01????????????? : _ipl <= 1;
15'b001???????????? : _ipl <= 2;
15'b0001??????????? : _ipl <= 2;
15'b00001?????????? : _ipl <= 3;
15'b000001????????? : _ipl <= 3;
15'b0000001???????? : _ipl <= 3;
15'b00000001??????? : _ipl <= 3;
15'b000000001?????? : _ipl <= 4;
15'b0000000001????? : _ipl <= 4;
15'b00000000001???? : _ipl <= 4;
15'b000000000001??? : _ipl <= 5;
15'b0000000000001?? : _ipl <= 6;
15'b00000000000001? : _ipl <= 6;
15'b000000000000001 : _ipl <= 6;
15'b000000000000000 : _ipl <= 7;
default: _ipl <= 7;
endcase
end
endmodule
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
module uart (
input wire clk,
input wire reset,
input wire [ 8-1:0] rga_i,
input wire [ 16-1:0] data_i,
output wire [ 16-1:0] data_o,
input wire uartbrk,
input wire rbfmirror,
output wire txint,
output wire rxint,
output wire txd,
input wire rxd
);
//// registers ////
localparam REG_SERDAT = 9'h030;
localparam REG_SERDATR = 9'h018;
localparam REG_SERPER = 9'h032;
//// bits ////
localparam LONG_BIT = 15;
localparam OVRUN_BIT = 15-11;
localparam RBF_BIT = 14-11;
localparam TBE_BIT = 13-11;
localparam TSRE_BIT = 12-11;
localparam RXD_BIT = 11-11;
//// RX input sync ////
reg [ 2-1:0] rxd_sync = 2'b11;
wire rxds;
always @ (posedge clk) begin
rxd_sync <= #1 {rxd_sync[0],rxd};
end
assign rxds = rxd_sync[1];
//// write registers ////
// SERPER
reg [ 16-1:0] serper = 16'h0000;
always @ (posedge clk) begin
if (rga_i == REG_SERPER[8:1])
serper <= #1 data_i;
end
// SERDAT
reg [ 16-1:0] serdat = 16'h0000;
always @ (posedge clk) begin
if (rga_i == REG_SERDAT[8:1])
serdat <= #1 data_i;
end
//// TX ////
localparam [ 2-1:0] TX_IDLE=2'd0, TX_SHIFT=2'd2;
reg [ 2-1:0] tx_state;
reg [ 16-1:0] tx_cnt;
reg [ 16-1:0] tx_shift;
reg tx_txd;
reg tx_irq;
reg tx_tbe;
reg tx_tsre;
always @ (posedge clk) begin
if (reset) begin
tx_state <= #1 TX_IDLE;
tx_txd <= #1 1'b1;
tx_irq <= #1 1'b0;
tx_tbe <= #1 1'b1;
tx_tsre <= #1 1'b1;
end else begin
case (tx_state)
TX_IDLE : begin
// txd pin inactive in idle state
tx_txd <= #1 1'b1;
// check if new data loaded to serdat register
if (!tx_tbe) begin
// set interrupt request
tx_irq <= #1 1'b1;
// data buffer empty again
//tx_tbe <= #1 1'b1;
// generate start bit
tx_txd <= #1 1'b0;
// pass data to a shift register
tx_tsre <= #1 1'b0;
tx_shift <= #1 serdat;
// reload period register
tx_cnt <= #1 {serper[14:0], 1'b1};
// start bitstream generation
tx_state <= #1 TX_SHIFT;
end
end
TX_SHIFT: begin
// clear interrupt request, active by 1 cycle of clk
tx_irq <= #1 1'b0;
// count bit period
if (tx_cnt == 16'd0) begin
// check if any bit left to send out
if (tx_shift == 16'd0) begin
// set TSRE flag when serdat register is empty
if (tx_tbe) tx_tsre <= #1 1'b1;
// data sent, go to idle state
tx_state <= #1 TX_IDLE;
end else begin
// reload period counter
tx_cnt <= #1 {serper[14:0], 1'b1};
// update shift register and txd pin
tx_shift <= #1 {1'b0, tx_shift[15:1]};
tx_txd <= #1 tx_shift[0];
end
end else begin
// decrement period counter
tx_cnt <= #1 tx_cnt - 16'd1;
end
end
default: begin
// force idle state
tx_state <= #1 TX_IDLE;
end
endcase
// force break char when requested
if (uartbrk) tx_txd <= #1 1'b0;
// handle tbe bit
//if (rga_i == REG_SERDAT[8:1]) tx_tbe <= #1 1'b0;
tx_tbe <= #1 (rga_i == REG_SERDAT[8:1]) ? 1'b0 : ((tx_state == TX_IDLE) ? 1'b1 : tx_tbe);
end
end
//// RX ////
localparam [ 2-1:0] RX_IDLE=2'd0, RX_START=2'd1, RX_SHIFT=2'd2;
reg [ 2-1:0] rx_state;
reg [ 16-1:0] rx_cnt;
reg [ 10-1:0] rx_shift;
reg [ 10-1:0] rx_data;
reg rx_rbf;
reg rx_rxd;
reg rx_irq;
reg rx_ovrun;
always @ (posedge clk) begin
if (reset) begin
rx_state <= #1 RX_IDLE;
rx_rbf <= #1 1'b0;
rx_rxd <= #1 1'b1;
rx_irq <= #1 1'b0;
rx_ovrun <= #1 1'b0;
end else begin
case (rx_state)
RX_IDLE : begin
// clear interrupt request
rx_irq <= #1 1'b0;
// wait for start condition
if (rx_rxd && !rxds) begin
// setup received data format
rx_shift <= #1 {serper[LONG_BIT], {9{1'b1}}};
rx_cnt <= #1 {1'b0, serper[14:0]};
// wait for a sampling point of a start bit
rx_state <= #1 RX_START;
end
end
RX_START : begin
// wait for a sampling point
if (rx_cnt == 16'h0) begin
// sample rxd signal
if (!rxds) begin
// start bit valid, start data shifting
rx_shift <= #1 {rxds, rx_shift[9:1]};
// restart period counter
rx_cnt <= #1 {serper[14:0], 1'b1};
// start data bits sampling
rx_state <= #1 RX_SHIFT;
end else begin
// start bit invalid, return into idle state
rx_state <= #1 RX_IDLE;
end
end else begin
rx_cnt <= #1 rx_cnt - 16'd1;
end
// check false start condition
if (!rx_rxd && rxds) begin
rx_state <= #1 RX_IDLE;
end
end
RX_SHIFT : begin
// wait for bit period
if (rx_cnt == 16'h0) begin
// store received bit
rx_shift <= #1 {rxds, rx_shift[9:1]};
// restart period counter
rx_cnt <= #1 {serper[14:0], 1'b1};
// check for all bits received
if (rx_shift[0] == 1'b0) begin
// set interrupt request flag
rx_irq <= #1 1'b1;
// handle OVRUN bit
//rx_ovrun <= #1 rbfmirror;
// update receive buffer
rx_data[9] <= #1 rxds;
if (serper[LONG_BIT]) begin
rx_data[8:0] <= #1 rx_shift[9:1];
end else begin
rx_data[8:0] <= #1 {rxds, rx_shift[9:2]};
end
// go to idle state
rx_state <= #1 RX_IDLE;
end
end else begin
rx_cnt <= #1 rx_cnt - 16'd1;
end
end
default : begin
// force idle state
rx_state <= #1 RX_IDLE;
end
endcase
// register rxds
rx_rxd <= #1 rxds;
// handle ovrun bit
rx_rbf <= #1 rbfmirror;
//if (!rbfmirror && rx_rbf) rx_ovrun <= #1 1'b0;
rx_ovrun <= #1 (!rbfmirror && rx_rbf) ? 1'b0 : (((rx_state == RX_SHIFT) && ~|rx_cnt && !rx_shift[0]) ? rbfmirror : rx_ovrun);
end
end
//// outputs ////
// SERDATR
wire [ 5-1:0] serdatr;
assign serdatr = {rx_ovrun, rx_rbf, tx_tbe, tx_tsre, rx_rxd};
// interrupts
assign txint = tx_irq;
assign rxint = rx_irq;
// uart output
assign txd = tx_txd;
// reg bus output
assign data_o = (rga_i == REG_SERDATR[8:1]) ? {serdatr, 1'b0, rx_data} : 16'h0000;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Line State Machine
// File : dex_smline.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_smline
(
input de_clk,
input de_rstn,
input goline,
input [2:0] dir,
input eol,
input signx,
input eline_actv_2,
input pcbusy,
input nlst_2,
input clip,
input cstop_2,
input eneg,
input eeqz,
output reg l_ldmaj,
output reg l_ldmin,
output reg l_bound,
output reg l_incpat,
output reg inc_err,
output reg rst_err,
output reg l_chgx,
output reg l_chgy,
output reg l_dec_itr,
output reg l_pixreq,
output reg l_set_busy,
output reg l_clr_busy,
output reg l_mul,
output reg l_pc_msk_last,
output reg l_frst_pix,
output reg l_last_pixel,
output reg l_src_upd,
output reg [21:0] l_op,
output l_rht,
output l_dwn
);
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
parameter
LWAIT = 4'h0,
L1 = 4'h1,
L2 = 4'h2,
L3 = 4'h3,
L4 = 4'h4,
L5 = 4'h5,
L6 = 4'h6,
L7 = 4'h7,
L8 = 4'h8,
LIDLE1 = 4'ha,
src = 5'h0,
dst = 5'h1,
delta = 5'h2,
noop = 5'h0,
pline = 5'h10,
einc = 5'h4,
error = 5'h3,
err_inc = 5'hc,
sub = 5'h12,
add = 5'h1,
abs = 5'h0,
mov = 5'hd,
movx = 5'hf,
subx = 5'h13,
cmp_add = 5'h7,
addx = 5'h3,
wrhl = 2'b00,
wrno = 2'b11,
wrhi = 2'b01,
dorgl = 5'hf;
parameter
/* define octants */
/* |YMAJ|sign dy|sign dx| */
/* \ | / */
o0=3'b000, /* \ 7 | 6 / */
o1=3'b001, /* \ | / */
o2=3'b010, /* 3 \ | / 2 */
o3=3'b011, /* --------|------- */
o4=3'b100, /* 1 /| \ 0 */
o5=3'b101, /* / | \ */
o6=3'b110, /* / 5 | 4 \ */
o7=3'b111; /* / | \ */
/* define internal wires and make assignments */
reg [3:0] l_cs;
reg [3:0] l_ns;
/* create the state register */
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn)l_cs <= 4'b0;
else l_cs <= l_ns;
end
assign l_rht = ((dir==o0) || (dir==o2) || (dir==o4) || (dir==o6));
assign l_dwn = ((dir==o0) || (dir==o1) || (dir==o4) || (dir==o5));
always @* begin
l_ldmaj = 1'b0;
l_ldmin = 1'b0;
l_bound = 1'b0;
l_incpat = 1'b0;
inc_err = 1'b0;
rst_err = 1'b0;
l_chgx = 1'b0;
l_chgy = 1'b0;
l_dec_itr = 1'b0;
l_pixreq = 1'b0;
l_set_busy = 1'b0;
l_clr_busy = 1'b0;
l_mul = 1'b0;
l_pc_msk_last = 1'b0;
l_frst_pix = 1'b0;
l_last_pixel = 1'b0;
l_src_upd = 1'b0;
l_op = 22'b00000_00000_00000_00000_11;
case(l_cs) /* synopsys full_case parallel_case */
LWAIT: if(goline)
begin /* calculate deltaX and deltaY */
l_ns=L1;
l_op={dst,src,sub,delta,wrhl};
l_set_busy=1'b1;
end
else l_ns= LWAIT;
L1: begin /* absolute deltaX and deltaY */
l_ns=L2;
l_op={noop,pline,abs,delta,wrhl};
l_mul=1'b1;
end
/* calculate the major axis */
L2: begin /* deltaX minus deltaY and load the resulting sign bit in L4 */
l_ldmin=1'b1;
l_ns=L3;
l_op={pline,pline,subx,noop,wrno};
end
/* wait for the pipeline delay, and add the origin to the destination. */
L3: begin /* add org low nibble to source point */
l_ns=L4;
l_op={dorgl,src,add,src,wrhi};
end
/* If deltaY < deltaX swap deltaX and deltY. */
L4: begin
l_ldmaj=1'b1;
l_ns=L5;
if(signx)l_op={delta,delta,movx,delta,wrhl};
else l_op={delta,delta,mov,noop,wrno};
end
L5: if(!eline_actv_2) /* if not eline calculate the two error increments */
begin /* fx = (ax * 2) - (ay * 2), fy= (ay * 2) */
l_ns=L6;
l_op={pline,pline,err_inc,einc,wrhl};
end
else begin
l_ns=L6;
l_op={einc,einc,subx,einc,wrhi};
end
/* initial error equals (-delta major + 2(delta minor)). */
L6: begin
l_ns=L7;
if(!eline_actv_2)l_op={pline,delta,cmp_add,error,wrhi};
else l_op={error,einc,addx,error,wrhi};
end
L7: begin
if(!pcbusy)
begin
l_op={noop,pline,mov,noop,wrno};
l_ns=4'hb;
end
else l_ns=L7;
l_frst_pix=1'b1;
// l_pipe_adv=1;
end
/* End of line with nolast set */
/* Go to IDLE state. */
L8: begin
if(eol && nlst_2)
begin
l_ns=LIDLE1;
l_pixreq=1'b1;
l_last_pixel = 1'b1;
l_pc_msk_last=1'b1;
l_op={noop,dst,mov,src,wrhl};
l_src_upd=1'b1;
end
/* End of line with nolast not set and stop or not stop. */
/* draw last pixel if pixel cache is not busy. */
/* Go to IDLE state. */
else if(!pcbusy && eol && !nlst_2)
begin
l_ns=LIDLE1;
l_incpat=1'b1;
l_op={noop,dst,mov,src,wrhl};
l_src_upd=1'b1;
end
/* Not end of line. */
/* Hit clipping boundry with stop set. */
/* Draw last pixel if pixel cache is not busy. */
/* Go to IDLE state. */
else if(!pcbusy && !eol && clip && cstop_2)
begin
l_ns=LIDLE1;
l_bound=1'b1;
l_incpat=1'b1;
l_op={noop,dst,mov,src,wrhl};
l_src_upd=1'b1;
end
/* Not end of line draw pixel if pixel cache is no busy. */
else if(!pcbusy && !eol)
begin
l_incpat=1'b1;
l_dec_itr=1'b1;
l_ns=L8;
if(!pcbusy && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
/* error >=0 reset error */ rst_err=1;
else if(!pcbusy && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
/* error > 0 reset error */ rst_err=1;
else if(!pcbusy)
/* increment error. */ inc_err=1;
end
else begin
l_op={noop,pline,mov,noop,wrno};
l_ns=L8;
end
if(!pcbusy) begin
if(eol && !nlst_2) begin
l_pixreq=1'b1;
l_last_pixel = 1'b1;
end
else if(!eol && clip && cstop_2) l_pixreq=1'b1;
else if(!eol)l_pixreq=1'b1;
if(!eol && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
l_chgx=1'b1;
else if(!eol && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
l_chgx=1'b1;
else if(!eol && (dir==o0 || dir==o1 || dir==o2 || dir==o3))
l_chgx=1'b1;
if(!eol && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
l_chgy=1'b1;
else if(!eol && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
l_chgy=1'b1;
else if(!eol && (dir==o4 || dir==o5 || dir==o6 || dir==o7))
l_chgy=1'b1;
end
end
4'hb: begin
l_ns=L8;
l_op={noop,pline,mov,noop,wrno};
end
LIDLE1: begin
l_ns=LWAIT;
l_clr_busy=1'b1;
end
endcase
end
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// All pins listed ok.
module neo_e0(
input [23:1] M68K_ADDR,
input [2:0] BNK,
input nSROMOEU, nSROMOEL,
output nSROMOE,
input nVEC,
output A23Z, A22Z,
output [23:0] CDA
);
assign nSROMOE = nSROMOEU & nSROMOEL;
// Vector table swap:
// A2*Z = 1 if nVEC == 0 and A == 11000000000000000xxxxxxx
assign {A23Z, A22Z} = M68K_ADDR[23:22] ^ {2{~|{M68K_ADDR[21:7], ^M68K_ADDR[23:22], nVEC}}};
// Todo: Check this on real hw (MV4 ?)
// Memcard area is $800000~$BFFFFF
// 10000000 00000000 00000000
// 10111111 11111111 11111111
// xxx 1
//assign CDA = {BNK, M68K_ADDR[21:1]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_TB_V
`define SKY130_FD_SC_MS__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_TB_V
|
// This file extends the original bug test case to explore all the
// forms of a signed right shift that are treated as special cases.
module test;
reg pass;
reg [8*40:1] str;
integer s;
initial begin
pass = 1'b1;
s = 1;
$sformat(str, "%0d", ((0 >> 1) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 1st test, expected \"-1\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((2 >> 1) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 2nd test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((2 >> s) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 3rd test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 1) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 4th test, expected \"-1\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 0) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 5th test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 64) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 6th test, expected \"-1\", got %s", str);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_tx_thrtl_ctl.v
// Version : 1.3
// //
// Description: //
// TX throttle controller. Anticipates back-pressure from PCIe block and //
// preemptively back-pressures user design (packet boundary throttling). //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_thrtl_ctl //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_tx_thrtl_ctl #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter TCQ = 1 // Clock to Q time
) (
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
input [3:0] s_axis_tx_tuser, // TX user signals
input s_axis_tx_tlast, // TX data is last
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
// TRN TX
//-----------
input [5:0] trn_tbuf_av, // TX buffers available
input trn_tdst_rdy, // TX destination ready
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // TX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output reg cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output reg tready_thrtl, // TREADY to pipeline
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Thrtl user when TBUF hits this val
localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
(C_DATA_WIDTH == 64) ? 1 : 0;
// Pause user when TBUF hits this val
localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
// GAP pause time - the latency from the time a packet is accepted on the TRN
// interface to the time trn_tbuf_av from the Block will decrement.
localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
localparam TCFG_LATENCY_TIME = 2'd2;
// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
localparam TCFG_GNT_PIPE_STAGES = 3;
// Throttle condition registers and constants
reg lnk_up_thrtl;
wire lnk_up_trig;
wire lnk_up_exit;
reg tbuf_av_min_thrtl;
wire tbuf_av_min_trig;
reg tbuf_av_gap_thrtl;
reg [2:0] tbuf_gap_cnt;
wire tbuf_av_gap_trig;
wire tbuf_av_gap_exit;
wire gap_trig_tlast;
wire gap_trig_decr;
reg [5:0] tbuf_av_d;
reg tcfg_req_thrtl;
reg [1:0] tcfg_req_cnt;
reg trn_tdst_rdy_d;
wire tcfg_req_trig;
wire tcfg_req_exit;
reg tcfg_gnt_log;
wire pre_throttle;
wire reg_throttle;
wire exit_crit;
reg reg_tcfg_gnt;
reg trn_tcfg_req_d;
reg tcfg_gnt_pending;
wire wire_to_turnoff;
reg reg_turnoff_ok;
reg tready_thrtl_mux;
localparam LINKSTATE_L0 = 3'b000;
localparam LINKSTATE_PPM_L1 = 3'b001;
localparam LINKSTATE_PPM_L1_TRANS = 3'b101;
localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
localparam PM_ENTER_L1 = 8'h20;
localparam POWERSTATE_D0 = 2'b00;
reg ppm_L1_thrtl;
wire ppm_L1_trig;
wire ppm_L1_exit;
reg [2:0] cfg_pcie_link_state_d;
reg trn_rdllp_src_rdy_d;
reg ppm_L23_thrtl;
wire ppm_L23_trig;
reg cfg_turnoff_ok_pending;
reg reg_tlast;
// Throttle control state machine states and registers
localparam IDLE = 0;
localparam THROTTLE = 1;
reg cur_state;
reg next_state;
reg reg_axi_in_pkt;
wire axi_in_pkt;
wire axi_pkt_ending;
wire axi_throttled;
wire axi_thrtl_ok;
wire tx_ecrc_pause;
//----------------------------------------------------------------------------//
// THROTTLE REASON: PCIe link is down //
// - When to throttle: trn_lnk_up deasserted //
// - When to stop: trn_tdst_rdy assesrted //
//----------------------------------------------------------------------------//
assign lnk_up_trig = !trn_lnk_up;
assign lnk_up_exit = trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else begin
if(lnk_up_trig) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else if(lnk_up_exit) begin
lnk_up_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers depleted //
// - When to throttle: trn_tbuf_av falls to 0 //
// - When to stop: trn_tbuf_av rises above 0 again //
//----------------------------------------------------------------------------//
assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
else begin
if(tbuf_av_min_trig) begin
tbuf_av_min_thrtl <= #TCQ 1'b1;
end
// The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
else begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers getting low //
// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP //
// - When to stop: after TBUF_GAP_TIME cycles elapse //
// //
// If we're about to run out of transmit buffers, throttle the user for a //
// few clock cycles to give the PCIe block time to catch up. This is //
// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //
// Block transmit path. //
//----------------------------------------------------------------------------//
// Detect two different scenarios for buffers getting low:
// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
// we need to pause and let that packet "soak in"
assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
// pause and make sure no other packets are about to soak in and cause the
// buffer availability to drop further.
assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&
(tbuf_av_d == (TBUF_AV_GAP+1));
assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);
assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
tbuf_gap_cnt <= #TCQ 3'h0;
tbuf_av_d <= #TCQ 6'h00;
end
else begin
if(tbuf_av_gap_trig) begin
tbuf_av_gap_thrtl <= #TCQ 1'b1;
end
else if(tbuf_av_gap_exit) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
end
// tbuf gap counter:
// This logic controls the length of the throttle condition when tbufs are
// getting low.
if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
if(tbuf_gap_cnt > 0) begin
tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
end
end
else begin
tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
end
tbuf_av_d <= #TCQ trn_tbuf_av;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to send a CFG response //
// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //
// - When to stop: after trn_tdst_rdy transitions to unasserted //
// //
// If the block needs to send a response to a CFG packet, this will cause //
// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //
// grant permission to the block to service request and throttle the user. //
//----------------------------------------------------------------------------//
assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_req_thrtl <= #TCQ 1'b0;
trn_tcfg_req_d <= #TCQ 1'b0;
trn_tdst_rdy_d <= #TCQ 1'b1;
reg_tcfg_gnt <= #TCQ 1'b0;
tcfg_req_cnt <= #TCQ 2'd0;
tcfg_gnt_pending <= #TCQ 1'b0;
end
else begin
if(tcfg_req_trig) begin
tcfg_req_thrtl <= #TCQ 1'b1;
end
else if(tcfg_req_exit) begin
tcfg_req_thrtl <= #TCQ 1'b0;
end
// We need to wait the appropriate amount of time for the tcfg_gnt to
// "sink in" to the PCIe block. After that, we know that the PCIe block will
// not reassert trn_tdst_rdy until the CFG request has been serviced. If a
// new request is being service (tcfg_gnt_log == 1), then reset the timer.
if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
end
else begin
if(tcfg_req_cnt > 0) begin
tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
end
end
// Make sure tcfg_gnt_log pulses once for one clock cycle for every
// cfg packet request.
if(trn_tcfg_req && !trn_tcfg_req_d) begin
tcfg_gnt_pending <= #TCQ 1'b1;
end
else if(tcfg_gnt_log) begin
tcfg_gnt_pending <= #TCQ 1'b0;
end
trn_tcfg_req_d <= #TCQ trn_tcfg_req;
trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
reg_tcfg_gnt <= #TCQ user_tcfg_gnt;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L1 //
// - When to throttle: appropriate low power state signal asserted //
// (architecture dependent) //
// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //
// dependent) //
// //
// If the block needs to transition to PM state PPM L1, we need to finish //
// up what we're doing and throttle immediately. //
//----------------------------------------------------------------------------//
generate
// PPM L1 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for 7 Series in EP mode
else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for V6 in EP mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 detection not supported for S6
else begin : s6_L1_thrtl
assign ppm_L1_trig = 1'b0;
assign ppm_L1_exit = 1'b1;
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L1_thrtl <= #TCQ 1'b0;
cfg_pcie_link_state_d <= #TCQ 3'b0;
trn_rdllp_src_rdy_d <= #TCQ 1'b0;
end
else begin
if(ppm_L1_trig) begin
ppm_L1_thrtl <= #TCQ 1'b1;
end
else if(ppm_L1_exit) begin
ppm_L1_thrtl <= #TCQ 1'b0;
end
cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //
// - When to throttle: appropriate PM signal indicates a transition to //
// L2/3 is pending or in progress (family and role dependent) //
// - When to stop: never (the only path out of L2/3 is a full reset) //
// //
// If the block needs to transition to PM state PPM L2/3, we need to finish //
// up what we're doing and throttle when the user gives permission. //
//----------------------------------------------------------------------------//
generate
// PPM L2/3 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
assign ppm_L23_trig = cfg_pm_send_pme_to;
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals in EP mode
else begin : L23_thrtl_ep
assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
// PPM L2/3 signals for 7 Series in EP mode
// For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
// outstanding, so we need a "sticky" register that grabs the request.
if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
reg reg_to_turnoff;
always @(posedge user_clk) begin
if(user_rst) begin
reg_to_turnoff <= #TCQ 1'b0;
end
else begin
if(cfg_to_turnoff) begin
reg_to_turnoff <= #TCQ 1'b1;
end
end
end
assign wire_to_turnoff = reg_to_turnoff;
end
// PPM L2/3 signals for V6/S6 in EP mode
// In V6 and S6, the to_turnoff signal asserts and remains asserted until
// turnoff_ok is asserted, so a sticky reg is not necessary.
else begin : v6_s6_L23_thrtl_ep
assign wire_to_turnoff = cfg_to_turnoff;
end
always @(posedge user_clk) begin
if(user_rst) begin
reg_turnoff_ok <= #TCQ 1'b0;
end
else begin
reg_turnoff_ok <= #TCQ user_turnoff_ok;
end
end
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L23_thrtl <= #TCQ 1'b0;
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
else begin
if(ppm_L23_trig) begin
ppm_L23_thrtl <= #TCQ 1'b1;
end
// Make sure cfg_turnoff_ok pulses once for one clock cycle for every
// turnoff request.
if(ppm_L23_trig && !ppm_L23_thrtl) begin
cfg_turnoff_ok_pending <= #TCQ 1'b1;
end
else if(cfg_turnoff_ok) begin
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //
// user design on the AXI interface. Since TREADY is registered, this signal //
// needs to assert on the cycle ~before~ we actually intend to throttle. //
// The only time it's OK to throttle when TVALID is asserted is on the first //
// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //
// is true: //
// 1) The user is not in a packet and is not starting one //
// 2) The user is just finishing a packet //
// 3) We're already throttled, so it's OK to continue throttling //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else begin
if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else if(tready_thrtl && s_axis_tx_tvalid) begin
reg_axi_in_pkt <= #TCQ 1'b1;
end
end
end
assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;
assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
assign axi_throttled = !tready_thrtl;
assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;
//----------------------------------------------------------------------------//
// Throttle CTL State Machine: //
// Throttle user design when a throttle trigger (or triggers) occur. //
// Keep user throttled until all exit criteria have been met. //
//----------------------------------------------------------------------------//
// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
// we're seeking one
assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
|| tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
// Registered throttle signals. Used to control throttle state machine
assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
|| tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
&& !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
always @(*) begin
case(cur_state)
// IDLE: in this state we're waiting for a trigger event to occur. As
// soon as an event occurs and the user isn't transmitting a packet, we
// throttle the PCIe block and the user and next state is THROTTLE.
IDLE: begin
if(reg_throttle && axi_thrtl_ok) begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(ppm_L23_thrtl) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
// If there's not throttle event, do nothing
else begin
// Throttle user as soon as possible
tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
end
// THROTTLE: in this state the user is throttle and we're waiting for
// exit criteria, which tells us that the throttle event is over. When
// the exit criteria is satisfied, de-throttle the user and next state
// is IDLE.
THROTTLE: begin
if(exit_crit) begin
// Dethrottle user
tready_thrtl_mux = !pre_throttle;
next_state = IDLE;
end
else begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
end
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl && tcfg_gnt_pending) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(cfg_turnoff_ok_pending) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
default: begin
tready_thrtl_mux = 1'b0;
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
endcase
end
// Synchronous logic
always @(posedge user_clk) begin
if(user_rst) begin
// Throttle user by default until link comes up
cur_state <= #TCQ THROTTLE;
reg_tlast <= #TCQ 1'b0;
tready_thrtl <= #TCQ 1'b0;
end
else begin
cur_state <= #TCQ next_state;
tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
reg_tlast <= #TCQ s_axis_tx_tlast;
end
end
// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
// is asserted at SOF. In this case, the Block needs an extra data beat to
// calculate the ECRC, but only if the following conditions are met:
// 1) there is no empty DWORDS at the end of the packet
// (i.e. packet length % C_DATA_WIDTH == 0)
//
// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
// TLP header
//
// If both conditions are met, the Block will stall the TRN interface for one
// data beat after EOF. We need to predict this stall and preemptively stall the
// User for one beat.
generate
if(C_FAMILY == "X7") begin : ecrc_pause_enabled
wire tx_ecrc_pkt;
reg reg_tx_ecrc_pkt;
wire [1:0] packet_fmt;
wire packet_td;
wire [2:0] header_len;
wire [9:0] payload_len;
wire [13:0] packet_len;
wire pause_needed;
// Grab necessary packet fields
assign packet_fmt = s_axis_tx_tdata[30:29];
assign packet_td = s_axis_tx_tdata[15];
// Calculate total packet length
assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;
assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
assign packet_len = {10'h000, header_len} + {4'h0, payload_len};
// Determine if packet a ECRC pause is needed
if(C_DATA_WIDTH == 128) begin : packet_len_check_128
assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
end
else begin : packet_len_check_64
assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
end
// Create flag to alert TX pipeline to insert a stall
assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
always @(posedge user_clk) begin
if(user_rst) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
else begin
if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b1;
end
else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
end
end
// Insert the stall now
assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
end
else begin : ecrc_pause_disabled
assign tx_ecrc_pause = 1'b0;
end
endgenerate
// Logic for 128-bit single cycle bug fix.
// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
// from AXI Basic causes the packet to be dropped. The packet drop occurs
// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
// prediction just as we do, it ignores the value of trn_tdst_rdy, and
// ultimately drops the packet when transmitting the packet to the block.
generate
if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
genvar stage;
reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
// Create a configurable depth FF delay pipeline
for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
begin : tcfg_gnt_pipeline_stage
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
end
else begin
// For stage 0, insert the actual tcfg_gnt signal from logic
if(stage == 0) begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
end
// For stages 1+, chain together
else begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
end
end
end
// tcfg_gnt output to block assigned the last pipeline stage
assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
end
end
else begin : tcfg_gnt_no_pipeline
// For all other architectures, no pipeline delay needed for tcfg_gnt
assign trn_tcfg_gnt = tcfg_gnt_log;
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= 1'b1;
else
TxCtrlEndFrm <= 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= 1'b1;
else
if(TxDoneIn)
CtrlMux <= 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= 1'b0;
else
TxUsedDataIn_q <= TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= ControlEnd;
TxCtrlStartFrm_q <= TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= DlyCrcCnt + 4'd1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= 6'h0;
else
if(ResetByteCnt)
ByteCnt <= 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= MuxedCtrlData[7:0];
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:58:08 08/25/2014
// Design Name: lab3dpath
// Module Name: C:/ece4743/projects/lab3_solution/tb_lab3dpath.v
// Project Name: lab3_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab3dpath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lab3dpath;
// Inputs
reg [9:0] x1;
reg [9:0] x2;
reg [9:0] x3;
// Outputs
wire [9:0] y;
reg[8*100:1] aline;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
integer errors;
// Instantiate the Unit Under Test (UUT)
lab3dpath uut (
.x1(x1),
.x2(x2),
.x3(x3),
.y(y)
);
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
fd = $fopen("multadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
x1 = i_a;
x2 = i_b;
x3 = i_c;
#40 //delay
if (i_result == y) begin
$display("PASS, x1: %x, x2: %x, x3: %x, y: %x\n",x1,x2,x3,y);
end else begin
$display("FAIL, x1: %x, x2: %x, x3: %x, y (actual): %x, y (expected): %x\n",x1,x2,x3,y,i_result);
errors = errors + 1;
end
end //end while
if (errors == 0) $display("PASS: All vectors pased.\n");
else $display ("FAIL: %d vectors failed\n",errors);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 14:00:36 05/19/2015
// Design Name:
// Module Name: opening3x3
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module opening3x3#(
parameter [9:0] H_SIZE = 83 // domylny rozmiar obrazu to szeroko = 64 piksele
)(
input clk,
input ce,
input rst,
input mask,
input in_de,
input in_vsync,
input in_hsync,
output opened,
output out_de,
output out_vsync,
output out_hsync
);
wire erosion;
wire erosion_de;
wire erosion_vsync;
wire erosion_hsync;
erosion3x3 #
(
.H_SIZE(H_SIZE)
)
erode3
(
.clk(clk),
.ce(1'b1),
.rst(1'b0),
.mask(mask),
.in_de(in_de),
.in_vsync(in_vsync),
.in_hsync(in_hsync),
.eroded(erosion),
.out_de(erosion_de),
.out_vsync(erosion_vsync),
.out_hsync(erosion_hsync)
);
wire dilation;
wire dilation_de;
wire dilation_vsync;
wire dilation_hsync;
dilation3x3 #
(
.H_SIZE(H_SIZE)
)
dilate3
(
.clk(clk),
.ce(1'b1),
.rst(1'b0),
.mask(erosion),
.in_de(erosion_de),
.in_vsync(erosion_vsync),
.in_hsync(erosion_hsync),
.dilated(dilation),
.out_de(dilation_de),
.out_vsync(dilation_vsync),
.out_hsync(dilation_hsync)
);
assign out_de = dilation_de;
assign out_hsync = dilation_hsync;
assign out_vsync = dilation_vsync;
assign opened = dilation;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always assign reg_lvalue = boolean_expression ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4'h1)
$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n");
else
begin
$display("PASSED\n");
$finish;
end
always assign value1 = 1'b1 && 1'b1 ;
endmodule
|
`timescale 1 ps / 1 ps
module s00_couplers_imp_DV8YS4
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[8:0] = auto_pc_to_s00_couplers_ARADDR[8:0];
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = auto_pc_to_s00_couplers_AWADDR[8:0];
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
zynq_1_auto_pc_9 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
(* CORE_GENERATION_INFO = "zynq_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,da_axi4_cnt=1}" *)
module zynq_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [31:0]gpio;
wire GND_1;
wire VCC_1;
wire [31:0]axi_gpio_0_gpio_io_o;
wire [0:0]proc_sys_reset_1_interconnect_aresetn;
wire [0:0]proc_sys_reset_1_peripheral_aresetn;
wire [8:0]processing_system7_1_axi_periph_M00_AXI_ARADDR;
wire processing_system7_1_axi_periph_M00_AXI_ARREADY;
wire processing_system7_1_axi_periph_M00_AXI_ARVALID;
wire [8:0]processing_system7_1_axi_periph_M00_AXI_AWADDR;
wire processing_system7_1_axi_periph_M00_AXI_AWREADY;
wire processing_system7_1_axi_periph_M00_AXI_AWVALID;
wire processing_system7_1_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_1_axi_periph_M00_AXI_BRESP;
wire processing_system7_1_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_1_axi_periph_M00_AXI_RDATA;
wire processing_system7_1_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_1_axi_periph_M00_AXI_RRESP;
wire processing_system7_1_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_1_axi_periph_M00_AXI_WDATA;
wire processing_system7_1_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_1_axi_periph_M00_AXI_WSTRB;
wire processing_system7_1_axi_periph_M00_AXI_WVALID;
wire [14:0]processing_system7_1_ddr_ADDR;
wire [2:0]processing_system7_1_ddr_BA;
wire processing_system7_1_ddr_CAS_N;
wire processing_system7_1_ddr_CKE;
wire processing_system7_1_ddr_CK_N;
wire processing_system7_1_ddr_CK_P;
wire processing_system7_1_ddr_CS_N;
wire [3:0]processing_system7_1_ddr_DM;
wire [31:0]processing_system7_1_ddr_DQ;
wire [3:0]processing_system7_1_ddr_DQS_N;
wire [3:0]processing_system7_1_ddr_DQS_P;
wire processing_system7_1_ddr_ODT;
wire processing_system7_1_ddr_RAS_N;
wire processing_system7_1_ddr_RESET_N;
wire processing_system7_1_ddr_WE_N;
wire processing_system7_1_fclk_clk0;
wire processing_system7_1_fclk_reset0_n;
wire processing_system7_1_fixed_io_DDR_VRN;
wire processing_system7_1_fixed_io_DDR_VRP;
wire [53:0]processing_system7_1_fixed_io_MIO;
wire processing_system7_1_fixed_io_PS_CLK;
wire processing_system7_1_fixed_io_PS_PORB;
wire processing_system7_1_fixed_io_PS_SRSTB;
wire [31:0]processing_system7_1_m_axi_gp0_ARADDR;
wire [1:0]processing_system7_1_m_axi_gp0_ARBURST;
wire [3:0]processing_system7_1_m_axi_gp0_ARCACHE;
wire [11:0]processing_system7_1_m_axi_gp0_ARID;
wire [3:0]processing_system7_1_m_axi_gp0_ARLEN;
wire [1:0]processing_system7_1_m_axi_gp0_ARLOCK;
wire [2:0]processing_system7_1_m_axi_gp0_ARPROT;
wire [3:0]processing_system7_1_m_axi_gp0_ARQOS;
wire processing_system7_1_m_axi_gp0_ARREADY;
wire [2:0]processing_system7_1_m_axi_gp0_ARSIZE;
wire processing_system7_1_m_axi_gp0_ARVALID;
wire [31:0]processing_system7_1_m_axi_gp0_AWADDR;
wire [1:0]processing_system7_1_m_axi_gp0_AWBURST;
wire [3:0]processing_system7_1_m_axi_gp0_AWCACHE;
wire [11:0]processing_system7_1_m_axi_gp0_AWID;
wire [3:0]processing_system7_1_m_axi_gp0_AWLEN;
wire [1:0]processing_system7_1_m_axi_gp0_AWLOCK;
wire [2:0]processing_system7_1_m_axi_gp0_AWPROT;
wire [3:0]processing_system7_1_m_axi_gp0_AWQOS;
wire processing_system7_1_m_axi_gp0_AWREADY;
wire [2:0]processing_system7_1_m_axi_gp0_AWSIZE;
wire processing_system7_1_m_axi_gp0_AWVALID;
wire [11:0]processing_system7_1_m_axi_gp0_BID;
wire processing_system7_1_m_axi_gp0_BREADY;
wire [1:0]processing_system7_1_m_axi_gp0_BRESP;
wire processing_system7_1_m_axi_gp0_BVALID;
wire [31:0]processing_system7_1_m_axi_gp0_RDATA;
wire [11:0]processing_system7_1_m_axi_gp0_RID;
wire processing_system7_1_m_axi_gp0_RLAST;
wire processing_system7_1_m_axi_gp0_RREADY;
wire [1:0]processing_system7_1_m_axi_gp0_RRESP;
wire processing_system7_1_m_axi_gp0_RVALID;
wire [31:0]processing_system7_1_m_axi_gp0_WDATA;
wire [11:0]processing_system7_1_m_axi_gp0_WID;
wire processing_system7_1_m_axi_gp0_WLAST;
wire processing_system7_1_m_axi_gp0_WREADY;
wire [3:0]processing_system7_1_m_axi_gp0_WSTRB;
wire processing_system7_1_m_axi_gp0_WVALID;
assign gpio[31:0] = axi_gpio_0_gpio_io_o;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
zynq_1_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.gpio_io_o(axi_gpio_0_gpio_io_o),
.s_axi_aclk(processing_system7_1_fclk_clk0),
.s_axi_araddr(processing_system7_1_axi_periph_M00_AXI_ARADDR),
.s_axi_aresetn(proc_sys_reset_1_peripheral_aresetn),
.s_axi_arready(processing_system7_1_axi_periph_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_1_axi_periph_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_1_axi_periph_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_1_axi_periph_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_1_axi_periph_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_1_axi_periph_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_1_axi_periph_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_1_axi_periph_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_1_axi_periph_M00_AXI_RDATA),
.s_axi_rready(processing_system7_1_axi_periph_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_1_axi_periph_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_1_axi_periph_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_1_axi_periph_M00_AXI_WDATA),
.s_axi_wready(processing_system7_1_axi_periph_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_1_axi_periph_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_1_axi_periph_M00_AXI_WVALID));
zynq_1_proc_sys_reset_1_0 proc_sys_reset_1
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_1_fclk_reset0_n),
.interconnect_aresetn(proc_sys_reset_1_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(proc_sys_reset_1_peripheral_aresetn),
.slowest_sync_clk(processing_system7_1_fclk_clk0));
zynq_1_processing_system7_1_0 processing_system7_1
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_1_fclk_clk0),
.FCLK_RESET0_N(processing_system7_1_fclk_reset0_n),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_1_fclk_clk0),
.M_AXI_GP0_ARADDR(processing_system7_1_m_axi_gp0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_1_m_axi_gp0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_1_m_axi_gp0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_1_m_axi_gp0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_1_m_axi_gp0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_1_m_axi_gp0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_1_m_axi_gp0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_1_m_axi_gp0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_1_m_axi_gp0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_1_m_axi_gp0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_1_m_axi_gp0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_1_m_axi_gp0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_1_m_axi_gp0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_1_m_axi_gp0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_1_m_axi_gp0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_1_m_axi_gp0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_1_m_axi_gp0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_1_m_axi_gp0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_1_m_axi_gp0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_1_m_axi_gp0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_1_m_axi_gp0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_1_m_axi_gp0_AWVALID),
.M_AXI_GP0_BID(processing_system7_1_m_axi_gp0_BID),
.M_AXI_GP0_BREADY(processing_system7_1_m_axi_gp0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_1_m_axi_gp0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_1_m_axi_gp0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_1_m_axi_gp0_RDATA),
.M_AXI_GP0_RID(processing_system7_1_m_axi_gp0_RID),
.M_AXI_GP0_RLAST(processing_system7_1_m_axi_gp0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_1_m_axi_gp0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_1_m_axi_gp0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_1_m_axi_gp0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_1_m_axi_gp0_WDATA),
.M_AXI_GP0_WID(processing_system7_1_m_axi_gp0_WID),
.M_AXI_GP0_WLAST(processing_system7_1_m_axi_gp0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_1_m_axi_gp0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_1_m_axi_gp0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_1_m_axi_gp0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
zynq_1_processing_system7_1_axi_periph_0 processing_system7_1_axi_periph
(.ACLK(processing_system7_1_fclk_clk0),
.ARESETN(proc_sys_reset_1_interconnect_aresetn),
.M00_ACLK(processing_system7_1_fclk_clk0),
.M00_ARESETN(proc_sys_reset_1_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_1_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_1_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_1_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_1_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_1_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_1_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_1_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_1_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_1_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_1_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_1_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_1_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_1_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_1_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_1_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_1_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_1_axi_periph_M00_AXI_WVALID),
.S00_ACLK(processing_system7_1_fclk_clk0),
.S00_ARESETN(proc_sys_reset_1_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_1_m_axi_gp0_ARADDR),
.S00_AXI_arburst(processing_system7_1_m_axi_gp0_ARBURST),
.S00_AXI_arcache(processing_system7_1_m_axi_gp0_ARCACHE),
.S00_AXI_arid(processing_system7_1_m_axi_gp0_ARID),
.S00_AXI_arlen(processing_system7_1_m_axi_gp0_ARLEN),
.S00_AXI_arlock(processing_system7_1_m_axi_gp0_ARLOCK),
.S00_AXI_arprot(processing_system7_1_m_axi_gp0_ARPROT),
.S00_AXI_arqos(processing_system7_1_m_axi_gp0_ARQOS),
.S00_AXI_arready(processing_system7_1_m_axi_gp0_ARREADY),
.S00_AXI_arsize(processing_system7_1_m_axi_gp0_ARSIZE),
.S00_AXI_arvalid(processing_system7_1_m_axi_gp0_ARVALID),
.S00_AXI_awaddr(processing_system7_1_m_axi_gp0_AWADDR),
.S00_AXI_awburst(processing_system7_1_m_axi_gp0_AWBURST),
.S00_AXI_awcache(processing_system7_1_m_axi_gp0_AWCACHE),
.S00_AXI_awid(processing_system7_1_m_axi_gp0_AWID),
.S00_AXI_awlen(processing_system7_1_m_axi_gp0_AWLEN),
.S00_AXI_awlock(processing_system7_1_m_axi_gp0_AWLOCK),
.S00_AXI_awprot(processing_system7_1_m_axi_gp0_AWPROT),
.S00_AXI_awqos(processing_system7_1_m_axi_gp0_AWQOS),
.S00_AXI_awready(processing_system7_1_m_axi_gp0_AWREADY),
.S00_AXI_awsize(processing_system7_1_m_axi_gp0_AWSIZE),
.S00_AXI_awvalid(processing_system7_1_m_axi_gp0_AWVALID),
.S00_AXI_bid(processing_system7_1_m_axi_gp0_BID),
.S00_AXI_bready(processing_system7_1_m_axi_gp0_BREADY),
.S00_AXI_bresp(processing_system7_1_m_axi_gp0_BRESP),
.S00_AXI_bvalid(processing_system7_1_m_axi_gp0_BVALID),
.S00_AXI_rdata(processing_system7_1_m_axi_gp0_RDATA),
.S00_AXI_rid(processing_system7_1_m_axi_gp0_RID),
.S00_AXI_rlast(processing_system7_1_m_axi_gp0_RLAST),
.S00_AXI_rready(processing_system7_1_m_axi_gp0_RREADY),
.S00_AXI_rresp(processing_system7_1_m_axi_gp0_RRESP),
.S00_AXI_rvalid(processing_system7_1_m_axi_gp0_RVALID),
.S00_AXI_wdata(processing_system7_1_m_axi_gp0_WDATA),
.S00_AXI_wid(processing_system7_1_m_axi_gp0_WID),
.S00_AXI_wlast(processing_system7_1_m_axi_gp0_WLAST),
.S00_AXI_wready(processing_system7_1_m_axi_gp0_WREADY),
.S00_AXI_wstrb(processing_system7_1_m_axi_gp0_WSTRB),
.S00_AXI_wvalid(processing_system7_1_m_axi_gp0_WVALID));
endmodule
module zynq_1_processing_system7_1_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [8:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [8:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire processing_system7_1_axi_periph_ACLK_net;
wire [0:0]processing_system7_1_axi_periph_ARESETN_net;
wire [31:0]processing_system7_1_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_1_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_1_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_1_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_1_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_1_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_1_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_1_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_1_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_1_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_1_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_1_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_1_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_1_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_1_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_1_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_1_axi_periph_to_s00_couplers_BID;
wire processing_system7_1_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_1_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_1_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_1_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_1_axi_periph_to_s00_couplers_RID;
wire processing_system7_1_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_1_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_1_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_1_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_1_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_1_axi_periph_to_s00_couplers_WID;
wire processing_system7_1_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_1_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_1_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_1_axi_periph_to_s00_couplers_WVALID;
wire [8:0]s00_couplers_to_processing_system7_1_axi_periph_ARADDR;
wire s00_couplers_to_processing_system7_1_axi_periph_ARREADY;
wire s00_couplers_to_processing_system7_1_axi_periph_ARVALID;
wire [8:0]s00_couplers_to_processing_system7_1_axi_periph_AWADDR;
wire s00_couplers_to_processing_system7_1_axi_periph_AWREADY;
wire s00_couplers_to_processing_system7_1_axi_periph_AWVALID;
wire s00_couplers_to_processing_system7_1_axi_periph_BREADY;
wire [1:0]s00_couplers_to_processing_system7_1_axi_periph_BRESP;
wire s00_couplers_to_processing_system7_1_axi_periph_BVALID;
wire [31:0]s00_couplers_to_processing_system7_1_axi_periph_RDATA;
wire s00_couplers_to_processing_system7_1_axi_periph_RREADY;
wire [1:0]s00_couplers_to_processing_system7_1_axi_periph_RRESP;
wire s00_couplers_to_processing_system7_1_axi_periph_RVALID;
wire [31:0]s00_couplers_to_processing_system7_1_axi_periph_WDATA;
wire s00_couplers_to_processing_system7_1_axi_periph_WREADY;
wire [3:0]s00_couplers_to_processing_system7_1_axi_periph_WSTRB;
wire s00_couplers_to_processing_system7_1_axi_periph_WVALID;
assign M00_AXI_araddr[8:0] = s00_couplers_to_processing_system7_1_axi_periph_ARADDR;
assign M00_AXI_arvalid = s00_couplers_to_processing_system7_1_axi_periph_ARVALID;
assign M00_AXI_awaddr[8:0] = s00_couplers_to_processing_system7_1_axi_periph_AWADDR;
assign M00_AXI_awvalid = s00_couplers_to_processing_system7_1_axi_periph_AWVALID;
assign M00_AXI_bready = s00_couplers_to_processing_system7_1_axi_periph_BREADY;
assign M00_AXI_rready = s00_couplers_to_processing_system7_1_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_processing_system7_1_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_processing_system7_1_axi_periph_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_processing_system7_1_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_1_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_1_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_1_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_1_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_1_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_1_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_1_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_1_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_1_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_1_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_1_axi_periph_to_s00_couplers_WREADY;
assign processing_system7_1_axi_periph_ACLK_net = M00_ACLK;
assign processing_system7_1_axi_periph_ARESETN_net = M00_ARESETN[0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_1_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_1_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_1_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_1_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_1_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_1_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_1_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_1_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_1_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_1_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_processing_system7_1_axi_periph_ARREADY = M00_AXI_arready;
assign s00_couplers_to_processing_system7_1_axi_periph_AWREADY = M00_AXI_awready;
assign s00_couplers_to_processing_system7_1_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_processing_system7_1_axi_periph_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_processing_system7_1_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_processing_system7_1_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_processing_system7_1_axi_periph_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_processing_system7_1_axi_periph_WREADY = M00_AXI_wready;
s00_couplers_imp_DV8YS4 s00_couplers
(.M_ACLK(processing_system7_1_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_1_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_processing_system7_1_axi_periph_ARADDR),
.M_AXI_arready(s00_couplers_to_processing_system7_1_axi_periph_ARREADY),
.M_AXI_arvalid(s00_couplers_to_processing_system7_1_axi_periph_ARVALID),
.M_AXI_awaddr(s00_couplers_to_processing_system7_1_axi_periph_AWADDR),
.M_AXI_awready(s00_couplers_to_processing_system7_1_axi_periph_AWREADY),
.M_AXI_awvalid(s00_couplers_to_processing_system7_1_axi_periph_AWVALID),
.M_AXI_bready(s00_couplers_to_processing_system7_1_axi_periph_BREADY),
.M_AXI_bresp(s00_couplers_to_processing_system7_1_axi_periph_BRESP),
.M_AXI_bvalid(s00_couplers_to_processing_system7_1_axi_periph_BVALID),
.M_AXI_rdata(s00_couplers_to_processing_system7_1_axi_periph_RDATA),
.M_AXI_rready(s00_couplers_to_processing_system7_1_axi_periph_RREADY),
.M_AXI_rresp(s00_couplers_to_processing_system7_1_axi_periph_RRESP),
.M_AXI_rvalid(s00_couplers_to_processing_system7_1_axi_periph_RVALID),
.M_AXI_wdata(s00_couplers_to_processing_system7_1_axi_periph_WDATA),
.M_AXI_wready(s00_couplers_to_processing_system7_1_axi_periph_WREADY),
.M_AXI_wstrb(s00_couplers_to_processing_system7_1_axi_periph_WSTRB),
.M_AXI_wvalid(s00_couplers_to_processing_system7_1_axi_periph_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_1_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_1_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_1_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_1_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_1_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_1_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_1_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_1_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_1_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_1_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_1_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_1_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_1_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_1_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_1_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_1_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_1_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_1_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_1_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_1_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_1_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_1_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_1_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_1_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_1_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_1_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_1_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_1_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_1_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_1_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_1_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_1_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_1_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_1_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_1_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_1_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_1_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_1_axi_periph_to_s00_couplers_WVALID));
endmodule
|
//name : main_0
//input : input_eth_in:16
//output : output_eth_out:16
//output : output_rs232_out:16
//source_file : /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c
///+============================================================================+
///| |
///| This file was generated by Chips |
///| |
///| Chips |
///| |
///| http://github.com/dawsonjon/Chips-2.0 |
///| |
///| Python powered |
///+============================================================================+
module main_0(input_eth_in,input_eth_in_stb,output_eth_out_ack,output_rs232_out_ack,clk,rst,output_eth_out,output_rs232_out,output_eth_out_stb,output_rs232_out_stb,input_eth_in_ack,exception);
integer file_count;
parameter stop = 3'd0,
instruction_fetch = 3'd1,
operand_fetch = 3'd2,
execute = 3'd3,
load = 3'd4,
wait_state = 3'd5,
read = 3'd6,
write = 3'd7;
input [31:0] input_eth_in;
input input_eth_in_stb;
input output_eth_out_ack;
input output_rs232_out_ack;
input clk;
input rst;
output [31:0] output_eth_out;
output [31:0] output_rs232_out;
output output_eth_out_stb;
output output_rs232_out_stb;
output input_eth_in_ack;
reg [31:0] timer;
reg [63:0] timer_clock;
reg [15:0] program_counter;
reg [15:0] program_counter_1;
reg [15:0] program_counter_2;
reg [44:0] instruction;
reg [4:0] opcode_2;
reg [3:0] a;
reg [3:0] b;
reg [3:0] z;
reg write_enable;
reg [3:0] address_a_2;
reg [3:0] address_b_2;
reg [3:0] address_z_2;
reg [3:0] address_z_3;
reg [31:0] load_data;
reg [31:0] write_output;
reg [31:0] write_value;
reg [31:0] read_input;
reg [15:0] literal_2;
reg [31:0] a_hi;
reg [31:0] b_hi;
reg [31:0] a_lo;
reg [31:0] b_lo;
reg [63:0] long_result;
reg [31:0] result;
reg [15:0] address;
reg [31:0] data_out;
reg [31:0] data_in;
reg [31:0] carry;
reg [31:0] s_output_eth_out_stb;
reg [31:0] s_output_rs232_out_stb;
reg [31:0] s_output_eth_out;
reg [31:0] s_output_rs232_out;
reg [31:0] s_input_eth_in_ack;
reg [7:0] state;
output reg exception;
reg [28:0] instructions [925:0];
reg [31:0] memory [4096:0];
reg [31:0] registers [15:0];
wire [31:0] operand_a;
wire [31:0] operand_b;
wire [31:0] register_a;
wire [31:0] register_b;
wire [15:0] literal;
wire [4:0] opcode;
wire [3:0] address_a;
wire [3:0] address_b;
wire [3:0] address_z;
wire [15:0] load_address;
wire [15:0] store_address;
wire [31:0] store_data;
wire store_enable;
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'literal': True, 'op': 'literal'}
// 1 {'literal': True, 'op': 'addl'}
// 2 {'literal': False, 'op': 'store'}
// 3 {'literal': True, 'op': 'call'}
// 4 {'literal': False, 'op': 'stop'}
// 5 {'literal': False, 'op': 'load'}
// 6 {'literal': False, 'op': 'add'}
// 7 {'literal': False, 'op': 'greater'}
// 8 {'literal': True, 'op': 'jmp_if_false'}
// 9 {'literal': False, 'op': 'shift_left'}
// 10 {'literal': False, 'op': 'subtract'}
// 11 {'literal': True, 'op': 'goto'}
// 12 {'literal': False, 'op': 'return'}
// 13 {'literal': False, 'op': 'write'}
// 14 {'literal': False, 'op': 'read'}
// 15 {'literal': False, 'op': 'unsigned_shift_right'}
// 16 {'literal': False, 'op': 'equal'}
// Intructions
// ===========
initial
begin
instructions[0] = {5'd0, 4'd3, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'literal'}
instructions[1] = {5'd0, 4'd4, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'literal'}
instructions[2] = {5'd1, 4'd3, 4'd3, 16'd43};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'a': 3, 'literal': 43, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'addl'}
instructions[3] = {5'd0, 4'd8, 4'd0, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 7 {'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 7, 'op': 'literal'}
instructions[4] = {5'd0, 4'd2, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 7 {'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 7, 'op': 'literal'}
instructions[5] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 7 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 7, 'op': 'store'}
instructions[6] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 6 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 6, 'op': 'literal'}
instructions[7] = {5'd0, 4'd2, 4'd0, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 6 {'literal': 2, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 6, 'op': 'literal'}
instructions[8] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 6 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 6, 'op': 'store'}
instructions[9] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[10] = {5'd0, 4'd2, 4'd0, 16'd3};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[11] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'store'}
instructions[12] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 1 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 1, 'op': 'literal'}
instructions[13] = {5'd0, 4'd2, 4'd0, 16'd5};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 1 {'literal': 5, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 1, 'op': 'literal'}
instructions[14] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 1 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 1, 'op': 'store'}
instructions[15] = {5'd0, 4'd8, 4'd0, 16'd67};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 67, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[16] = {5'd0, 4'd2, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 8, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[17] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[18] = {5'd0, 4'd8, 4'd0, 16'd104};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 104, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[19] = {5'd0, 4'd2, 4'd0, 16'd9};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 9, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[20] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[21] = {5'd0, 4'd8, 4'd0, 16'd105};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 105, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[22] = {5'd0, 4'd2, 4'd0, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 10, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[23] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[24] = {5'd0, 4'd8, 4'd0, 16'd112};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 112, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[25] = {5'd0, 4'd2, 4'd0, 16'd11};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 11, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[26] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[27] = {5'd0, 4'd8, 4'd0, 16'd115};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 115, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[28] = {5'd0, 4'd2, 4'd0, 16'd12};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 12, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[29] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[30] = {5'd0, 4'd8, 4'd0, 16'd32};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 32, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[31] = {5'd0, 4'd2, 4'd0, 16'd13};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 13, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[32] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[33] = {5'd0, 4'd8, 4'd0, 16'd105};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 105, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[34] = {5'd0, 4'd2, 4'd0, 16'd14};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 14, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[35] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[36] = {5'd0, 4'd8, 4'd0, 16'd109};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 109, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[37] = {5'd0, 4'd2, 4'd0, 16'd15};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 15, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[38] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[39] = {5'd0, 4'd8, 4'd0, 16'd97};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 97, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[40] = {5'd0, 4'd2, 4'd0, 16'd16};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 16, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[41] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[42] = {5'd0, 4'd8, 4'd0, 16'd103};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 103, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[43] = {5'd0, 4'd2, 4'd0, 16'd17};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 17, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[44] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[45] = {5'd0, 4'd8, 4'd0, 16'd101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 101, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[46] = {5'd0, 4'd2, 4'd0, 16'd18};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 18, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[47] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[48] = {5'd0, 4'd8, 4'd0, 16'd32};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 32, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[49] = {5'd0, 4'd2, 4'd0, 16'd19};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 19, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[50] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[51] = {5'd0, 4'd8, 4'd0, 16'd112};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 112, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[52] = {5'd0, 4'd2, 4'd0, 16'd20};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 20, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[53] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[54] = {5'd0, 4'd8, 4'd0, 16'd114};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 114, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[55] = {5'd0, 4'd2, 4'd0, 16'd21};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 21, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[56] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[57] = {5'd0, 4'd8, 4'd0, 16'd111};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 111, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[58] = {5'd0, 4'd2, 4'd0, 16'd22};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 22, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[59] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[60] = {5'd0, 4'd8, 4'd0, 16'd99};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 99, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[61] = {5'd0, 4'd2, 4'd0, 16'd23};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 23, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[62] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[63] = {5'd0, 4'd8, 4'd0, 16'd101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 101, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[64] = {5'd0, 4'd2, 4'd0, 16'd24};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 24, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[65] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[66] = {5'd0, 4'd8, 4'd0, 16'd115};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 115, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[67] = {5'd0, 4'd2, 4'd0, 16'd25};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 25, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[68] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[69] = {5'd0, 4'd8, 4'd0, 16'd115};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 115, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[70] = {5'd0, 4'd2, 4'd0, 16'd26};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 26, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[71] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[72] = {5'd0, 4'd8, 4'd0, 16'd105};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 105, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[73] = {5'd0, 4'd2, 4'd0, 16'd27};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 27, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[74] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[75] = {5'd0, 4'd8, 4'd0, 16'd110};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 110, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[76] = {5'd0, 4'd2, 4'd0, 16'd28};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 28, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[77] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[78] = {5'd0, 4'd8, 4'd0, 16'd103};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 103, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[79] = {5'd0, 4'd2, 4'd0, 16'd29};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 29, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[80] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[81] = {5'd0, 4'd8, 4'd0, 16'd32};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 32, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[82] = {5'd0, 4'd2, 4'd0, 16'd30};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 30, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[83] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[84] = {5'd0, 4'd8, 4'd0, 16'd101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 101, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[85] = {5'd0, 4'd2, 4'd0, 16'd31};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 31, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[86] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[87] = {5'd0, 4'd8, 4'd0, 16'd120};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 120, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[88] = {5'd0, 4'd2, 4'd0, 16'd32};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 32, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[89] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[90] = {5'd0, 4'd8, 4'd0, 16'd97};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 97, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[91] = {5'd0, 4'd2, 4'd0, 16'd33};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 33, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[92] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[93] = {5'd0, 4'd8, 4'd0, 16'd109};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 109, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[94] = {5'd0, 4'd2, 4'd0, 16'd34};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 34, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[95] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[96] = {5'd0, 4'd8, 4'd0, 16'd112};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 112, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[97] = {5'd0, 4'd2, 4'd0, 16'd35};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 35, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[98] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[99] = {5'd0, 4'd8, 4'd0, 16'd108};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 108, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[100] = {5'd0, 4'd2, 4'd0, 16'd36};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 36, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[101] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[102] = {5'd0, 4'd8, 4'd0, 16'd101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 101, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[103] = {5'd0, 4'd2, 4'd0, 16'd37};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 37, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[104] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[105] = {5'd0, 4'd8, 4'd0, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 10, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[106] = {5'd0, 4'd2, 4'd0, 16'd38};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 38, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[107] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[108] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[109] = {5'd0, 4'd2, 4'd0, 16'd39};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 39, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[110] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[111] = {5'd0, 4'd8, 4'd0, 16'd1029};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 3 {'literal': 1029, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 3, 'op': 'literal'}
instructions[112] = {5'd0, 4'd2, 4'd0, 16'd40};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 3 {'literal': 40, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 3, 'op': 'literal'}
instructions[113] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 3 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 3, 'op': 'store'}
instructions[114] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 5 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 5, 'op': 'literal'}
instructions[115] = {5'd0, 4'd2, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 5 {'literal': 41, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 5, 'op': 'literal'}
instructions[116] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 5 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 5, 'op': 'store'}
instructions[117] = {5'd0, 4'd8, 4'd0, 16'd515};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 2 {'literal': 515, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 2, 'op': 'literal'}
instructions[118] = {5'd0, 4'd2, 4'd0, 16'd42};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 2 {'literal': 42, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 2, 'op': 'literal'}
instructions[119] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 2 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 2, 'op': 'store'}
instructions[120] = {5'd1, 4'd7, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'addl'}
instructions[121] = {5'd1, 4'd4, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'addl'}
instructions[122] = {5'd3, 4'd6, 4'd0, 16'd124};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'z': 6, 'label': 124, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'call'}
instructions[123] = {5'd4, 4'd0, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72 {'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 72, 'op': 'stop'}
instructions[124] = {5'd1, 4'd3, 4'd3, 16'd132135};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25 {'a': 3, 'literal': 132135, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25, 'op': 'addl'}
instructions[125] = {5'd0, 4'd8, 4'd0, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39 {'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39, 'op': 'literal'}
instructions[126] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39, 'op': 'addl'}
instructions[127] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39, 'op': 'load'}
instructions[128] = {5'd0, 4'd2, 4'd0, 16'd3};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39 {'literal': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39, 'op': 'literal'}
instructions[129] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 39, 'op': 'store'}
instructions[130] = {5'd2, 4'd0, 4'd3, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[131] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[132] = {5'd2, 4'd0, 4'd3, 16'd7};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[133] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[134] = {5'd0, 4'd8, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'literal': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'literal'}
instructions[135] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'store'}
instructions[136] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[137] = {5'd1, 4'd7, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[138] = {5'd1, 4'd4, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[139] = {5'd3, 4'd6, 4'd0, 16'd438};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'z': 6, 'label': 438, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'call'}
instructions[140] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[141] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[142] = {5'd5, 4'd7, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'load'}
instructions[143] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[144] = {5'd5, 4'd6, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'z': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'load'}
instructions[145] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 41, 'op': 'addl'}
instructions[146] = {5'd1, 4'd8, 4'd4, 16'd131075};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 4, 'literal': 131075, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'addl'}
instructions[147] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'store'}
instructions[148] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'addl'}
instructions[149] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'literal'}
instructions[150] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[151] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'load'}
instructions[152] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'add'}
instructions[153] = {5'd1, 4'd2, 4'd4, 16'd132099};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 4, 'literal': 132099, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'addl'}
instructions[154] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 43, 'op': 'store'}
instructions[155] = {5'd1, 4'd8, 4'd4, 16'd131331};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 4, 'literal': 131331, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'addl'}
instructions[156] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'store'}
instructions[157] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'addl'}
instructions[158] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'literal'}
instructions[159] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[160] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'load'}
instructions[161] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'add'}
instructions[162] = {5'd1, 4'd2, 4'd4, 16'd132100};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 4, 'literal': 132100, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'addl'}
instructions[163] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 44, 'op': 'store'}
instructions[164] = {5'd1, 4'd8, 4'd4, 16'd131587};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 4, 'literal': 131587, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'addl'}
instructions[165] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'store'}
instructions[166] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'addl'}
instructions[167] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'literal'}
instructions[168] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[169] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'load'}
instructions[170] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'add'}
instructions[171] = {5'd1, 4'd2, 4'd4, 16'd132101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 4, 'literal': 132101, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'addl'}
instructions[172] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 45, 'op': 'store'}
instructions[173] = {5'd1, 4'd8, 4'd4, 16'd132100};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50 {'a': 4, 'literal': 132100, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50, 'op': 'addl'}
instructions[174] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50, 'op': 'addl'}
instructions[175] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50, 'op': 'load'}
instructions[176] = {5'd1, 4'd2, 4'd4, 16'd132101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50 {'a': 4, 'literal': 132101, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50, 'op': 'addl'}
instructions[177] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 50, 'op': 'store'}
instructions[178] = {5'd1, 4'd8, 4'd4, 16'd132099};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51 {'a': 4, 'literal': 132099, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51, 'op': 'addl'}
instructions[179] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51, 'op': 'addl'}
instructions[180] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51, 'op': 'load'}
instructions[181] = {5'd1, 4'd2, 4'd4, 16'd132100};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51 {'a': 4, 'literal': 132100, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51, 'op': 'addl'}
instructions[182] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 51, 'op': 'store'}
instructions[183] = {5'd2, 4'd0, 4'd3, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'store'}
instructions[184] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[185] = {5'd2, 4'd0, 4'd3, 16'd7};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'store'}
instructions[186] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[187] = {5'd1, 4'd8, 4'd4, 16'd132099};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 4, 'literal': 132099, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[188] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[189] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'load'}
instructions[190] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'store'}
instructions[191] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[192] = {5'd1, 4'd7, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[193] = {5'd1, 4'd4, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[194] = {5'd3, 4'd6, 4'd0, 16'd529};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'z': 6, 'label': 529, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'call'}
instructions[195] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[196] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[197] = {5'd5, 4'd7, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'load'}
instructions[198] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[199] = {5'd5, 4'd6, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 3, 'z': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'load'}
instructions[200] = {5'd0, 4'd2, 4'd0, 16'd4};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'literal': 4, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'literal'}
instructions[201] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'load'}
instructions[202] = {5'd1, 4'd2, 4'd4, 16'd132102};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 4, 'literal': 132102, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'addl'}
instructions[203] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 52, 'op': 'store'}
instructions[204] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'literal'}
instructions[205] = {5'd1, 4'd2, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 4, 'literal': 131072, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[206] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'store'}
instructions[207] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[208] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[209] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'load'}
instructions[210] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'store'}
instructions[211] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[212] = {5'd0, 4'd8, 4'd0, 16'd256};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'literal': 256, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'literal'}
instructions[213] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[214] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'load'}
instructions[215] = {5'd7, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'greater'}
instructions[216] = {5'd8, 4'd0, 4'd8, 16'd413};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 8, 'label': 413, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'jmp_if_false'}
instructions[217] = {5'd0, 4'd8, 4'd0, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'literal'}
instructions[218] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'store'}
instructions[219] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[220] = {5'd1, 4'd8, 4'd4, 16'd132100};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 4, 'literal': 132100, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[221] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[222] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'load'}
instructions[223] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'store'}
instructions[224] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[225] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[226] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[227] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'load'}
instructions[228] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[229] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'load'}
instructions[230] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'add'}
instructions[231] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[232] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'load'}
instructions[233] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[234] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'load'}
instructions[235] = {5'd9, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'shift_left'}
instructions[236] = {5'd1, 4'd2, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 4, 'literal': 131074, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'addl'}
instructions[237] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 55, 'op': 'store'}
instructions[238] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'literal'}
instructions[239] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'store'}
instructions[240] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'addl'}
instructions[241] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'addl'}
instructions[242] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'addl'}
instructions[243] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'load'}
instructions[244] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[245] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'load'}
instructions[246] = {5'd7, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'greater'}
instructions[247] = {5'd8, 4'd0, 4'd8, 16'd307};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'a': 8, 'label': 307, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'jmp_if_false'}
instructions[248] = {5'd1, 4'd8, 4'd4, 16'd132099};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 4, 'literal': 132099, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[249] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[250] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[251] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'store'}
instructions[252] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[253] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'literal'}
instructions[254] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'store'}
instructions[255] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[256] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[257] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[258] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[259] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[260] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[261] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'subtract'}
instructions[262] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[263] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[264] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'add'}
instructions[265] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[266] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[267] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'store'}
instructions[268] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[269] = {5'd1, 4'd8, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 4, 'literal': 131074, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[270] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[271] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[272] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[273] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'load'}
instructions[274] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'subtract'}
instructions[275] = {5'd1, 4'd2, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 4, 'literal': 131074, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'addl'}
instructions[276] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 57, 'op': 'store'}
instructions[277] = {5'd1, 4'd8, 4'd4, 16'd132101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 4, 'literal': 132101, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[278] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[279] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[280] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'store'}
instructions[281] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[282] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'literal'}
instructions[283] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'store'}
instructions[284] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[285] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[286] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[287] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[288] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[289] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[290] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'subtract'}
instructions[291] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[292] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[293] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'add'}
instructions[294] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[295] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[296] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'store'}
instructions[297] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[298] = {5'd1, 4'd8, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 4, 'literal': 131074, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[299] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[300] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[301] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[302] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'load'}
instructions[303] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'subtract'}
instructions[304] = {5'd1, 4'd2, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 4, 'literal': 131074, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'addl'}
instructions[305] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 58, 'op': 'store'}
instructions[306] = {5'd11, 4'd0, 4'd0, 16'd307};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56 {'label': 307, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 56, 'op': 'goto'}
instructions[307] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'addl'}
instructions[308] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'addl'}
instructions[309] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'load'}
instructions[310] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'store'}
instructions[311] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'addl'}
instructions[312] = {5'd0, 4'd8, 4'd0, 16'd255};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'literal': 255, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'literal'}
instructions[313] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[314] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'load'}
instructions[315] = {5'd7, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'greater'}
instructions[316] = {5'd8, 4'd0, 4'd8, 16'd376};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'a': 8, 'label': 376, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'jmp_if_false'}
instructions[317] = {5'd1, 4'd8, 4'd4, 16'd132101};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 4, 'literal': 132101, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[318] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[319] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[320] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'store'}
instructions[321] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[322] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'literal'}
instructions[323] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'store'}
instructions[324] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[325] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[326] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[327] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[328] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[329] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[330] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'add'}
instructions[331] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[332] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[333] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'add'}
instructions[334] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[335] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[336] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'store'}
instructions[337] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[338] = {5'd1, 4'd8, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 4, 'literal': 131074, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[339] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[340] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[341] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[342] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'load'}
instructions[343] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'subtract'}
instructions[344] = {5'd1, 4'd2, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 4, 'literal': 131074, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'addl'}
instructions[345] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 61, 'op': 'store'}
instructions[346] = {5'd1, 4'd8, 4'd4, 16'd132099};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 4, 'literal': 132099, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[347] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[348] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[349] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'store'}
instructions[350] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[351] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'literal'}
instructions[352] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'store'}
instructions[353] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[354] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[355] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[356] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[357] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[358] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[359] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'add'}
instructions[360] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[361] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[362] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'add'}
instructions[363] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[364] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[365] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'store'}
instructions[366] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[367] = {5'd1, 4'd8, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 4, 'literal': 131074, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[368] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[369] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[370] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[371] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'load'}
instructions[372] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'subtract'}
instructions[373] = {5'd1, 4'd2, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 4, 'literal': 131074, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'addl'}
instructions[374] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 62, 'op': 'store'}
instructions[375] = {5'd11, 4'd0, 4'd0, 16'd376};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60 {'label': 376, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 60, 'op': 'goto'}
instructions[376] = {5'd1, 4'd8, 4'd4, 16'd131074};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 4, 'literal': 131074, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[377] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[378] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'load'}
instructions[379] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'store'}
instructions[380] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[381] = {5'd1, 4'd8, 4'd4, 16'd131843};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 4, 'literal': 131843, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[382] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'store'}
instructions[383] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[384] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[385] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[386] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'load'}
instructions[387] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[388] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'load'}
instructions[389] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'add'}
instructions[390] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'addl'}
instructions[391] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[392] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'load'}
instructions[393] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 64, 'op': 'store'}
instructions[394] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[395] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[396] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'load'}
instructions[397] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'store'}
instructions[398] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[399] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'literal'}
instructions[400] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'store'}
instructions[401] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[402] = {5'd1, 4'd8, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 4, 'literal': 131072, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[403] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[404] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'load'}
instructions[405] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[406] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'load'}
instructions[407] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'add'}
instructions[408] = {5'd1, 4'd2, 4'd4, 16'd131072};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 4, 'literal': 131072, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'addl'}
instructions[409] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'store'}
instructions[410] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[411] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'load'}
instructions[412] = {5'd11, 4'd0, 4'd0, 16'd207};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54 {'label': 207, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 54, 'op': 'goto'}
instructions[413] = {5'd2, 4'd0, 4'd3, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'store'}
instructions[414] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[415] = {5'd2, 4'd0, 4'd3, 16'd7};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'store'}
instructions[416] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[417] = {5'd1, 4'd8, 4'd4, 16'd131843};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 4, 'literal': 131843, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[418] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'store'}
instructions[419] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[420] = {5'd1, 4'd8, 4'd4, 16'd132102};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 4, 'literal': 132102, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[421] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[422] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'load'}
instructions[423] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'store'}
instructions[424] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[425] = {5'd1, 4'd7, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[426] = {5'd1, 4'd4, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[427] = {5'd3, 4'd6, 4'd0, 16'd739};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'z': 6, 'label': 739, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'call'}
instructions[428] = {5'd1, 4'd3, 4'd3, -16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': -2, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[429] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[430] = {5'd5, 4'd7, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'z': 7, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'load'}
instructions[431] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[432] = {5'd5, 4'd6, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'z': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'load'}
instructions[433] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 67, 'op': 'addl'}
instructions[434] = {5'd11, 4'd0, 4'd0, 16'd173};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 46 {'label': 173, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 46, 'op': 'goto'}
instructions[435] = {5'd1, 4'd3, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25, 'op': 'addl'}
instructions[436] = {5'd1, 4'd4, 4'd7, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25, 'op': 'addl'}
instructions[437] = {5'd12, 4'd0, 4'd6, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25 {'a': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/application.c : 25, 'op': 'return'}
instructions[438] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[439] = {5'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[440] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[441] = {5'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[442] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[443] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[444] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[445] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[446] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[447] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[448] = {5'd0, 4'd8, 4'd0, 16'd3};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'literal': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'literal'}
instructions[449] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[450] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[451] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[452] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[453] = {5'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[454] = {5'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[455] = {5'd3, 4'd6, 4'd0, 16'd465};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'z': 6, 'label': 465, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'call'}
instructions[456] = {5'd1, 4'd3, 4'd3, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': -2, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[457] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[458] = {5'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[459] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[460] = {5'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[461] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[462] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[463] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[464] = {5'd12, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'return'}
instructions[465] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[466] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'literal'}
instructions[467] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'addl'}
instructions[468] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'store'}
instructions[469] = {5'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[470] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[471] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[472] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'store'}
instructions[473] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[474] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[475] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[476] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[477] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[478] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[479] = {5'd6, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'add'}
instructions[480] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[481] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[482] = {5'd8, 4'd0, 4'd8, 16'd524};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'a': 8, 'label': 524, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'jmp_if_false'}
instructions[483] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[484] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[485] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[486] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[487] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[488] = {5'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[489] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[490] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[491] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[492] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[493] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[494] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[495] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[496] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[497] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[498] = {5'd6, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'add'}
instructions[499] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[500] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[501] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[502] = {5'd5, 4'd0, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 0, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[503] = {5'd13, 4'd0, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 0, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'write'}
instructions[504] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[505] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[506] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[507] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[508] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[509] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[510] = {5'd0, 4'd8, 4'd0, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'literal'}
instructions[511] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[512] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[513] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[514] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[515] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[516] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[517] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[518] = {5'd6, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'add'}
instructions[519] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[520] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[521] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[522] = {5'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[523] = {5'd11, 4'd0, 4'd0, 16'd525};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 525, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[524] = {5'd11, 4'd0, 4'd0, 16'd526};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 526, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[525] = {5'd11, 4'd0, 4'd0, 16'd469};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'label': 469, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'goto'}
instructions[526] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[527] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[528] = {5'd12, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'return'}
instructions[529] = {5'd1, 4'd3, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 7 {'a': 3, 'literal': 8, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 7, 'op': 'addl'}
instructions[530] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13, 'op': 'literal'}
instructions[531] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13, 'op': 'addl'}
instructions[532] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13, 'op': 'load'}
instructions[533] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13, 'op': 'read'}
instructions[534] = {5'd1, 4'd2, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13 {'a': 4, 'literal': 2, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13, 'op': 'addl'}
instructions[535] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 13, 'op': 'store'}
instructions[536] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14, 'op': 'literal'}
instructions[537] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14, 'op': 'addl'}
instructions[538] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14, 'op': 'load'}
instructions[539] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14, 'op': 'read'}
instructions[540] = {5'd1, 4'd2, 4'd4, 16'd4};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14 {'a': 4, 'literal': 4, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14, 'op': 'addl'}
instructions[541] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 14, 'op': 'store'}
instructions[542] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15, 'op': 'literal'}
instructions[543] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15, 'op': 'addl'}
instructions[544] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15, 'op': 'load'}
instructions[545] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15, 'op': 'read'}
instructions[546] = {5'd1, 4'd2, 4'd4, 16'd5};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15 {'a': 4, 'literal': 5, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15, 'op': 'addl'}
instructions[547] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 15, 'op': 'store'}
instructions[548] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16, 'op': 'literal'}
instructions[549] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16, 'op': 'addl'}
instructions[550] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16, 'op': 'load'}
instructions[551] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16, 'op': 'read'}
instructions[552] = {5'd1, 4'd2, 4'd4, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16 {'a': 4, 'literal': 6, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16, 'op': 'addl'}
instructions[553] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 16, 'op': 'store'}
instructions[554] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17, 'op': 'literal'}
instructions[555] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17, 'op': 'addl'}
instructions[556] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17, 'op': 'load'}
instructions[557] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17, 'op': 'read'}
instructions[558] = {5'd0, 4'd2, 4'd0, 16'd7};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17 {'literal': 7, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17, 'op': 'literal'}
instructions[559] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 17, 'op': 'store'}
instructions[560] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18, 'op': 'literal'}
instructions[561] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18, 'op': 'addl'}
instructions[562] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18, 'op': 'load'}
instructions[563] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18, 'op': 'read'}
instructions[564] = {5'd0, 4'd2, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18 {'literal': 1, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18, 'op': 'literal'}
instructions[565] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 18, 'op': 'store'}
instructions[566] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19, 'op': 'literal'}
instructions[567] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19, 'op': 'addl'}
instructions[568] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19, 'op': 'load'}
instructions[569] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19, 'op': 'read'}
instructions[570] = {5'd0, 4'd2, 4'd0, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19 {'literal': 6, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19, 'op': 'literal'}
instructions[571] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 19, 'op': 'store'}
instructions[572] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20, 'op': 'literal'}
instructions[573] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20, 'op': 'addl'}
instructions[574] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20, 'op': 'load'}
instructions[575] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20, 'op': 'read'}
instructions[576] = {5'd1, 4'd2, 4'd4, 16'd7};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20 {'a': 4, 'literal': 7, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20, 'op': 'addl'}
instructions[577] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 20, 'op': 'store'}
instructions[578] = {5'd0, 4'd8, 4'd0, 16'd14};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'literal': 14, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'literal'}
instructions[579] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'store'}
instructions[580] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'addl'}
instructions[581] = {5'd1, 4'd8, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 4, 'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'addl'}
instructions[582] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'addl'}
instructions[583] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'load'}
instructions[584] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[585] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'load'}
instructions[586] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'subtract'}
instructions[587] = {5'd1, 4'd2, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 4, 'literal': 1, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'addl'}
instructions[588] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 21, 'op': 'store'}
instructions[589] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'literal'}
instructions[590] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'store'}
instructions[591] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'addl'}
instructions[592] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'literal'}
instructions[593] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'store'}
instructions[594] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'addl'}
instructions[595] = {5'd1, 4'd8, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'addl'}
instructions[596] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'addl'}
instructions[597] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'load'}
instructions[598] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[599] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'load'}
instructions[600] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'add'}
instructions[601] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[602] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'load'}
instructions[603] = {5'd15, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'unsigned_shift_right'}
instructions[604] = {5'd1, 4'd2, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'addl'}
instructions[605] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 22, 'op': 'store'}
instructions[606] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'literal'}
instructions[607] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'store'}
instructions[608] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[609] = {5'd1, 4'd8, 4'd4, 16'd4};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 4, 'literal': 4, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[610] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[611] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'load'}
instructions[612] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[613] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'load'}
instructions[614] = {5'd16, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'equal'}
instructions[615] = {5'd8, 4'd0, 4'd8, 16'd625};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'label': 625, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'jmp_if_false'}
instructions[616] = {5'd0, 4'd8, 4'd0, 16'd515};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'literal': 515, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'literal'}
instructions[617] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'store'}
instructions[618] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[619] = {5'd1, 4'd8, 4'd4, 16'd5};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 4, 'literal': 5, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[620] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[621] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'load'}
instructions[622] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[623] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'load'}
instructions[624] = {5'd16, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'equal'}
instructions[625] = {5'd8, 4'd0, 4'd8, 16'd635};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'label': 635, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'jmp_if_false'}
instructions[626] = {5'd0, 4'd8, 4'd0, 16'd1029};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'literal': 1029, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'literal'}
instructions[627] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'store'}
instructions[628] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[629] = {5'd1, 4'd8, 4'd4, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 4, 'literal': 6, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[630] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'addl'}
instructions[631] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'load'}
instructions[632] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[633] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'load'}
instructions[634] = {5'd16, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'equal'}
instructions[635] = {5'd8, 4'd0, 4'd8, 16'd709};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'a': 8, 'label': 709, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'jmp_if_false'}
instructions[636] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 26 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 26, 'op': 'literal'}
instructions[637] = {5'd1, 4'd2, 4'd4, 16'd3};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 26 {'a': 4, 'literal': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 26, 'op': 'addl'}
instructions[638] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 26 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 26, 'op': 'store'}
instructions[639] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27, 'op': 'addl'}
instructions[640] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27, 'op': 'addl'}
instructions[641] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27, 'op': 'load'}
instructions[642] = {5'd8, 4'd0, 4'd8, 16'd698};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 8, 'label': 698, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'jmp_if_false'}
instructions[643] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'literal'}
instructions[644] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[645] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[646] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'read'}
instructions[647] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'store'}
instructions[648] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[649] = {5'd1, 4'd8, 4'd4, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[650] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[651] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[652] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'store'}
instructions[653] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[654] = {5'd1, 4'd8, 4'd4, 16'd3};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 4, 'literal': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[655] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[656] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[657] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'store'}
instructions[658] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[659] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'literal'}
instructions[660] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'store'}
instructions[661] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[662] = {5'd1, 4'd8, 4'd4, 16'd3};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 4, 'literal': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[663] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[664] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[665] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[666] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[667] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'add'}
instructions[668] = {5'd1, 4'd2, 4'd4, 16'd3};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 4, 'literal': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[669] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'store'}
instructions[670] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[671] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[672] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[673] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[674] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'add'}
instructions[675] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'addl'}
instructions[676] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[677] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'load'}
instructions[678] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 28, 'op': 'store'}
instructions[679] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[680] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[681] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'load'}
instructions[682] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'store'}
instructions[683] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[684] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'literal'}
instructions[685] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'store'}
instructions[686] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[687] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[688] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[689] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'load'}
instructions[690] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[691] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'load'}
instructions[692] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'subtract'}
instructions[693] = {5'd1, 4'd2, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'addl'}
instructions[694] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'store'}
instructions[695] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[696] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 29, 'op': 'load'}
instructions[697] = {5'd11, 4'd0, 4'd0, 16'd699};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'label': 699, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'goto'}
instructions[698] = {5'd11, 4'd0, 4'd0, 16'd700};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'label': 700, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'goto'}
instructions[699] = {5'd11, 4'd0, 4'd0, 16'd639};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27 {'label': 639, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 27, 'op': 'goto'}
instructions[700] = {5'd1, 4'd8, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'addl'}
instructions[701] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'addl'}
instructions[702] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'load'}
instructions[703] = {5'd0, 4'd2, 4'd0, 16'd4};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'literal': 4, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'literal'}
instructions[704] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'store'}
instructions[705] = {5'd1, 4'd3, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'addl'}
instructions[706] = {5'd1, 4'd4, 4'd7, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'addl'}
instructions[707] = {5'd12, 4'd0, 4'd6, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31 {'a': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 31, 'op': 'return'}
instructions[708] = {5'd11, 4'd0, 4'd0, 16'd738};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24 {'label': 738, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 24, 'op': 'goto'}
instructions[709] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35, 'op': 'addl'}
instructions[710] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35, 'op': 'addl'}
instructions[711] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35, 'op': 'load'}
instructions[712] = {5'd8, 4'd0, 4'd8, 16'd736};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 40 {'a': 8, 'label': 736, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 40, 'op': 'jmp_if_false'}
instructions[713] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36, 'op': 'literal'}
instructions[714] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36, 'op': 'addl'}
instructions[715] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36, 'op': 'load'}
instructions[716] = {5'd14, 4'd8, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36 {'a': 8, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 36, 'op': 'read'}
instructions[717] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[718] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[719] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'load'}
instructions[720] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'store'}
instructions[721] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[722] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'literal'}
instructions[723] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'store'}
instructions[724] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[725] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[726] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[727] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'load'}
instructions[728] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[729] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'load'}
instructions[730] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'subtract'}
instructions[731] = {5'd1, 4'd2, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'addl'}
instructions[732] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'store'}
instructions[733] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[734] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 37, 'op': 'load'}
instructions[735] = {5'd11, 4'd0, 4'd0, 16'd737};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 40 {'label': 737, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 40, 'op': 'goto'}
instructions[736] = {5'd11, 4'd0, 4'd0, 16'd738};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 40 {'label': 738, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 40, 'op': 'goto'}
instructions[737] = {5'd11, 4'd0, 4'd0, 16'd709};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35 {'label': 709, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 35, 'op': 'goto'}
instructions[738] = {5'd11, 4'd0, 4'd0, 16'd530};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 12 {'label': 530, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 12, 'op': 'goto'}
instructions[739] = {5'd1, 4'd3, 4'd3, 16'd3};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45 {'a': 3, 'literal': 3, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45, 'op': 'addl'}
instructions[740] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'literal'}
instructions[741] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'store'}
instructions[742] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'addl'}
instructions[743] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'literal'}
instructions[744] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'store'}
instructions[745] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'addl'}
instructions[746] = {5'd1, 4'd8, 4'd4, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'addl'}
instructions[747] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'addl'}
instructions[748] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'load'}
instructions[749] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[750] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'load'}
instructions[751] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'add'}
instructions[752] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[753] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'load'}
instructions[754] = {5'd15, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'unsigned_shift_right'}
instructions[755] = {5'd1, 4'd2, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 4, 'literal': 2, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'addl'}
instructions[756] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 49, 'op': 'store'}
instructions[757] = {5'd0, 4'd8, 4'd0, 16'd14};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'literal': 14, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'literal'}
instructions[758] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'store'}
instructions[759] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'addl'}
instructions[760] = {5'd1, 4'd8, 4'd4, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'addl'}
instructions[761] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'addl'}
instructions[762] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'load'}
instructions[763] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[764] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'load'}
instructions[765] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'add'}
instructions[766] = {5'd1, 4'd2, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'addl'}
instructions[767] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 50, 'op': 'store'}
instructions[768] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'literal'}
instructions[769] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'addl'}
instructions[770] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'load'}
instructions[771] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'store'}
instructions[772] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'addl'}
instructions[773] = {5'd1, 4'd8, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'addl'}
instructions[774] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'addl'}
instructions[775] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'load'}
instructions[776] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[777] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'load'}
instructions[778] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'write'}
instructions[779] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 52, 'op': 'addl'}
instructions[780] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'literal'}
instructions[781] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'addl'}
instructions[782] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'load'}
instructions[783] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'store'}
instructions[784] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'addl'}
instructions[785] = {5'd0, 4'd8, 4'd0, 16'd7};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'literal': 7, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'literal'}
instructions[786] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'addl'}
instructions[787] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'load'}
instructions[788] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[789] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'load'}
instructions[790] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'write'}
instructions[791] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 53, 'op': 'addl'}
instructions[792] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'literal'}
instructions[793] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'addl'}
instructions[794] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'load'}
instructions[795] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'store'}
instructions[796] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'addl'}
instructions[797] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'literal'}
instructions[798] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'addl'}
instructions[799] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'load'}
instructions[800] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[801] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'load'}
instructions[802] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'write'}
instructions[803] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 54, 'op': 'addl'}
instructions[804] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'literal'}
instructions[805] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'addl'}
instructions[806] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'load'}
instructions[807] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'store'}
instructions[808] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'addl'}
instructions[809] = {5'd0, 4'd8, 4'd0, 16'd6};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'literal': 6, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'literal'}
instructions[810] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'addl'}
instructions[811] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'load'}
instructions[812] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[813] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'load'}
instructions[814] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'write'}
instructions[815] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 55, 'op': 'addl'}
instructions[816] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'literal'}
instructions[817] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'addl'}
instructions[818] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'load'}
instructions[819] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'store'}
instructions[820] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'addl'}
instructions[821] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'literal'}
instructions[822] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[823] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'load'}
instructions[824] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'write'}
instructions[825] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 56, 'op': 'addl'}
instructions[826] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'literal'}
instructions[827] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'addl'}
instructions[828] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'load'}
instructions[829] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'store'}
instructions[830] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'addl'}
instructions[831] = {5'd0, 4'd8, 4'd0, 16'd515};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'literal': 515, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'literal'}
instructions[832] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[833] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'load'}
instructions[834] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'write'}
instructions[835] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 57, 'op': 'addl'}
instructions[836] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'literal'}
instructions[837] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'addl'}
instructions[838] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'load'}
instructions[839] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'store'}
instructions[840] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'addl'}
instructions[841] = {5'd0, 4'd8, 4'd0, 16'd1029};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'literal': 1029, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'literal'}
instructions[842] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[843] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'load'}
instructions[844] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'write'}
instructions[845] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 58, 'op': 'addl'}
instructions[846] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'literal'}
instructions[847] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'addl'}
instructions[848] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'load'}
instructions[849] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'store'}
instructions[850] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'addl'}
instructions[851] = {5'd1, 4'd8, 4'd4, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'addl'}
instructions[852] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'addl'}
instructions[853] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'load'}
instructions[854] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[855] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'load'}
instructions[856] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'write'}
instructions[857] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 59, 'op': 'addl'}
instructions[858] = {5'd0, 4'd8, 4'd0, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 61 {'literal': 0, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 61, 'op': 'literal'}
instructions[859] = {5'd1, 4'd2, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 61 {'a': 4, 'literal': 1, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 61, 'op': 'addl'}
instructions[860] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 61 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 61, 'op': 'store'}
instructions[861] = {5'd1, 4'd8, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62 {'a': 4, 'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62, 'op': 'addl'}
instructions[862] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62, 'op': 'addl'}
instructions[863] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62, 'op': 'load'}
instructions[864] = {5'd8, 4'd0, 4'd8, 16'd921};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 67 {'a': 8, 'label': 921, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 67, 'op': 'jmp_if_false'}
instructions[865] = {5'd0, 4'd8, 4'd0, 16'd41};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'literal': 41, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'literal'}
instructions[866] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[867] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[868] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'store'}
instructions[869] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[870] = {5'd1, 4'd8, 4'd4, -16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 4, 'literal': -2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[871] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[872] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[873] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'store'}
instructions[874] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[875] = {5'd1, 4'd8, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[876] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[877] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[878] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'store'}
instructions[879] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[880] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'literal'}
instructions[881] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'store'}
instructions[882] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[883] = {5'd1, 4'd8, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[884] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[885] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[886] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[887] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[888] = {5'd6, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'add'}
instructions[889] = {5'd1, 4'd2, 4'd4, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 4, 'literal': 1, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[890] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'store'}
instructions[891] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[892] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[893] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[894] = {5'd5, 4'd2, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[895] = {5'd6, 4'd8, 4'd8, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'z': 8, 'b': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'add'}
instructions[896] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[897] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[898] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[899] = {5'd5, 4'd0, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'z': 0, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'load'}
instructions[900] = {5'd13, 4'd0, 4'd0, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 0, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'write'}
instructions[901] = {5'd1, 4'd3, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 63, 'op': 'addl'}
instructions[902] = {5'd1, 4'd8, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 4, 'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[903] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[904] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'load'}
instructions[905] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'store'}
instructions[906] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[907] = {5'd0, 4'd8, 4'd0, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'literal': 1, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'literal'}
instructions[908] = {5'd2, 4'd0, 4'd3, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'store'}
instructions[909] = {5'd1, 4'd3, 4'd3, 16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[910] = {5'd1, 4'd8, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 4, 'literal': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[911] = {5'd1, 4'd2, 4'd8, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[912] = {5'd5, 4'd8, 4'd2, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 2, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'load'}
instructions[913] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[914] = {5'd5, 4'd10, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'z': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'load'}
instructions[915] = {5'd10, 4'd8, 4'd8, 16'd10};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'subtract'}
instructions[916] = {5'd1, 4'd2, 4'd4, 16'd2};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 4, 'literal': 2, 'z': 2, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'addl'}
instructions[917] = {5'd2, 4'd0, 4'd2, 16'd8};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 2, 'b': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'store'}
instructions[918] = {5'd1, 4'd3, 4'd3, -16'd1};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'comment': 'pop', 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[919] = {5'd5, 4'd8, 4'd3, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64 {'a': 3, 'z': 8, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 64, 'op': 'load'}
instructions[920] = {5'd11, 4'd0, 4'd0, 16'd922};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 67 {'label': 922, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 67, 'op': 'goto'}
instructions[921] = {5'd11, 4'd0, 4'd0, 16'd923};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 67 {'label': 923, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 67, 'op': 'goto'}
instructions[922] = {5'd11, 4'd0, 4'd0, 16'd861};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62 {'label': 861, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 62, 'op': 'goto'}
instructions[923] = {5'd1, 4'd3, 4'd4, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45, 'op': 'addl'}
instructions[924] = {5'd1, 4'd4, 4'd7, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45, 'op': 'addl'}
instructions[925] = {5'd12, 4'd0, 4'd6, 16'd0};///home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45 {'a': 6, 'trace': /home/jon/Projects/Chips-Demo/demo/examples/image_processor/ethernet.h : 45, 'op': 'return'}
end
always @(posedge clk)
begin
load_data <= memory[load_address];
if(store_enable && state == execute) begin
memory[store_address] <= store_data;
end
end
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 1 -- FETCH INSTRUCTION
//
always @(posedge clk)
begin
//implement memory for instructions
if (state == instruction_fetch || state == operand_fetch || state == execute) begin
instruction <= instructions[program_counter];
program_counter_1 <= program_counter;
end
end
assign opcode = instruction[28:24];
assign address_z = instruction[23:20];
assign address_a = instruction[19:16];
assign address_b = instruction[3:0];
assign literal = instruction[15:0];
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 2 -- FETCH OPERANDS
//
always @(posedge clk)
begin
if (write_enable) begin
registers[address_z_3] <= result;
end
if (state == operand_fetch || state == execute) begin
opcode_2 <= opcode;
literal_2 <= literal;
address_a_2 <= address_a;
address_b_2 <= address_b;
address_z_2 <= address_z;
program_counter_2 <= program_counter_1;
end
end
assign register_a = registers[address_a_2];
assign register_b = registers[address_b_2];
assign operand_a = (address_a_2 == address_z_3 && write_enable)?result:register_a;
assign operand_b = (address_b_2 == address_z_3 && write_enable)?result:register_b;
assign store_address = operand_a;
assign load_address = operand_a;
assign store_data = operand_b;
assign store_enable = (opcode_2==2);
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 3 -- EXECUTE
//
always @(posedge clk)
begin
write_enable <= 0;
timer_clock <= timer_clock + 1;
case(state)
//instruction_fetch
instruction_fetch: begin
program_counter <= program_counter + 1;
state <= operand_fetch;
end
//operand_fetch
operand_fetch: begin
program_counter <= program_counter + 1;
state <= execute;
end
//execute
execute: begin
program_counter <= program_counter + 1;
address_z_3 <= address_z_2;
case(opcode_2)
//literal
16'd0:
begin
result<=$signed(literal_2);
write_enable <= 1;
end
//addl
16'd1:
begin
result<=operand_a + literal_2;
write_enable <= 1;
end
//store
16'd2:
begin
end
//call
16'd3:
begin
result <= program_counter_2 + 1;
write_enable <= 1;
program_counter <= literal_2;
state <= instruction_fetch;
end
//stop
16'd4:
begin
state <= stop;
end
//load
16'd5:
begin
state <= load;
end
//add
16'd6:
begin
long_result = operand_a + operand_b;
result <= long_result[31:0];
carry[0] <= long_result[32];
write_enable <= 1;
end
//greater
16'd7:
begin
result <= $signed(operand_a) > $signed(operand_b);
write_enable <= 1;
end
//jmp_if_false
16'd8:
begin
if (operand_a == 0) begin
program_counter <= literal_2;
state <= instruction_fetch;
end
end
//shift_left
16'd9:
begin
if(operand_b < 32) begin
result <= operand_a << operand_b;
carry <= operand_a >> (32-operand_b);
end else begin
result <= 0;
carry <= operand_a;
end
write_enable <= 1;
end
//subtract
16'd10:
begin
long_result = operand_a + (~operand_b) + 1;
result <= long_result[31:0];
carry[0] <= ~long_result[32];
write_enable <= 1;
end
//goto
16'd11:
begin
program_counter <= literal_2;
state <= instruction_fetch;
end
//return
16'd12:
begin
program_counter <= operand_a;
state <= instruction_fetch;
end
//write
16'd13:
begin
state <= write;
write_output <= operand_a;
write_value <= operand_b;
end
//read
16'd14:
begin
state <= read;
read_input <= operand_a;
end
//unsigned_shift_right
16'd15:
begin
if(operand_b < 32) begin
result <= operand_a >> operand_b;
carry <= operand_a << (32-operand_b);
end else begin
result <= 0;
carry <= operand_a;
end
write_enable <= 1;
end
//equal
16'd16:
begin
result <= operand_a == operand_b;
write_enable <= 1;
end
endcase
end
read:
begin
case(read_input)
2:
begin
s_input_eth_in_ack <= 1;
if (s_input_eth_in_ack && input_eth_in_stb) begin
result <= input_eth_in;
write_enable <= 1;
s_input_eth_in_ack <= 0;
state <= execute;
end
end
endcase
end
write:
begin
case(write_output)
0:
begin
s_output_eth_out_stb <= 1;
s_output_eth_out <= write_value;
if (output_eth_out_ack && s_output_eth_out_stb) begin
s_output_eth_out_stb <= 0;
state <= execute;
end
end
1:
begin
s_output_rs232_out_stb <= 1;
s_output_rs232_out <= write_value;
if (output_rs232_out_ack && s_output_rs232_out_stb) begin
s_output_rs232_out_stb <= 0;
state <= execute;
end
end
endcase
end
load:
begin
result <= load_data;
write_enable <= 1;
state <= execute;
end
wait_state:
begin
if (timer) begin
timer <= timer - 1;
end else begin
state <= execute;
end
end
stop:
begin
end
endcase
if (rst == 1'b1) begin
timer <= 0;
timer_clock <= 0;
program_counter <= 0;
address_z_3 <= 0;
result <= 0;
a = 0;
b = 0;
z = 0;
state <= instruction_fetch;
s_input_eth_in_ack <= 0;
s_output_eth_out_stb <= 0;
s_output_rs232_out_stb <= 0;
end
end
assign input_eth_in_ack = s_input_eth_in_ack;
assign output_eth_out_stb = s_output_eth_out_stb;
assign output_eth_out = s_output_eth_out;
assign output_rs232_out_stb = s_output_rs232_out_stb;
assign output_rs232_out = s_output_rs232_out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function int mon_check();
`endif
module t #(
parameter int WIDTH /* verilator public_flat_rd */ = 32
) (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
localparam int DEPTH /* verilator public_flat_rd */ = 16;
localparam longint PARAM_LONG /* verilator public_flat_rd */ = 64'hFEDCBA9876543210;
localparam string PARAM_STR /* verilator public_flat_rd */ = "'some string value'";
reg [WIDTH-1:0] mem0 [DEPTH:1] /*verilator public_flat_rw @(posedge clk) */;
integer i, status;
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef IVERILOG
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_param.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
|
`timescale 1ns/1ns
module lspc_regs(
input RESET,
input RESETP,
input [3:1] M68K_ADDR,
input [15:0] M68K_DATA,
input LSPOE,
input LSPWE,
input VMODE,
input [8:0] RASTERC,
input [2:0] AA_COUNT,
input [15:0] VRAM_LOW_READ,
input [15:0] VRAM_HIGH_READ,
output WR_VRAM_ADDR,
output WR_VRAM_RW,
output WR_TIMER_HIGH,
output WR_TIMER_LOW,
output WR_IRQ_ACK,
output [15:0] REG_VRAMADDR,
output [15:0] REG_VRAMMOD,
output [15:0] REG_VRAMRW,
output [15:0] REG_LSPCMODE,
output [15:0] CPU_DATA_OUT,
output [7:0] AA_SPEED, // Auto-animation speed
output [2:0] TIMER_MODE, // Timer mode
output TIMER_IRQ_EN, // Timer interrupt enable
output AA_DISABLE, // Auto-animation disable
output TIMER_STOP,
output nVRAM_WRITE_REQ,
input D112B_OUT
);
reg [7:0] WR_DECODED; // CPU address decoder output
wire [15:0] CPU_DATA_MUX;
// CPU address decode
// C27
always @(*)
begin
if (~LSPWE)
begin
case (M68K_ADDR)
3'h0 : WR_DECODED <= 8'b11111110;
3'h1 : WR_DECODED <= 8'b11111101;
3'h2 : WR_DECODED <= 8'b11111011;
3'h3 : WR_DECODED <= 8'b11110111;
3'h4 : WR_DECODED <= 8'b11101111;
3'h5 : WR_DECODED <= 8'b11011111;
3'h6 : WR_DECODED <= 8'b10111111;
3'h7 : WR_DECODED <= 8'b01111111;
endcase
end
else
WR_DECODED <= 8'b11111111;
end
always @(negedge LSPWE)
begin
case (M68K_ADDR)
//3'h0 : Address set
//3'h1 : Data write
3'h2 : $display("VRAM set modulo to 0x%H", M68K_DATA);
3'h3 : $display("LSPC set timer mode to %b, timer irq to %b, AA disable to %b, AA speed to 0x%H", M68K_DATA[7:5], M68K_DATA[4], M68K_DATA[3], M68K_DATA[15:8]);
3'h4 : $display("LSPC set timer reload MSB to 0x%H", M68K_DATA);
3'h5 : $display("LSPC set timer reload LSB to 0x%H", M68K_DATA);
3'h6 : $display("LSPC ack interrupt %d", M68K_DATA[2:0]);
3'h7 : $display("LSPC set timer stop for PAL mode to %B", M68K_DATA[0]);
endcase
end
assign WR_VRAM_ADDR = WR_DECODED[0];
assign WR_VRAM_RW = WR_DECODED[1];
assign WR_VRAM_MOD = WR_DECODED[2];
assign WR_LSPC_MODE = WR_DECODED[3];
assign WR_TIMER_HIGH = WR_DECODED[4];
assign WR_TIMER_LOW = WR_DECODED[5];
assign WR_IRQ_ACK = WR_DECODED[6];
assign WR_TIMER_STOP = WR_DECODED[7];
// CPU reads
assign REG_LSPCMODE = {RASTERC, 3'b0, VMODE, AA_COUNT};
// Read: CPU_READ_SW:
// $3C0000 REG_VRAMRW REG_VRAMADDR_MSB
// $3C0002 REG_VRAMRW REG_VRAMADDR_MSB
// $3C0004 REG_VRAMMOD 0
// $3C0006 REG_LSPCMODE 1
// C20A C22B C20B
assign CPU_READ_SW = ~|{~|{M68K_ADDR[1], ~M68K_ADDR[2]}, ~|{REG_VRAMADDR[15], M68K_ADDR[2]}};
// CPU read data select
// F218A F221A F230 G252A
// K172 F235 F232 G250
// G274 G276A G267A H266A
// I250A I253 I255A H264
assign CPU_DATA_MUX = M68K_ADDR[2] ?
CPU_READ_SW ? REG_LSPCMODE : REG_VRAMMOD
:
CPU_READ_SW ? VRAM_HIGH_READ : VRAM_LOW_READ;
// CPU read data latch
// B138 A123 A68 A28
FDS16bit B138(~LSPOE, CPU_DATA_MUX, CPU_DATA_OUT);
// CPU write to REG_VRAMRW
// F155 D131 D121 E154
FDS16bit F155(~WR_VRAM_RW, M68K_DATA, REG_VRAMRW);
// CPU VRAM write request flag handling
// Set by write to REG_VRAMRW, reset when write is done or write to REG_VRAMADDR
assign D32A_OUT = D28_nQ & 1'b1; // Used for test mode
FDPCell D38(~WR_VRAM_RW, 1'b1, 1'b1, D32A_OUT, D38_Q, nVRAM_WRITE_REQ);
FDPCell D28(D112B_OUT, 1'b1, 1'b1, D38_Q, , D28_nQ);
// CPU write to REG_VRAMMOD
// H105 G105 F81 G123
FDS16bit H105(~WR_VRAM_MOD, M68K_DATA, REG_VRAMMOD);
// CPU write to REG_VRAMADDR
// F47 D87 A79 C123
FDS16bit F47(~WR_VRAM_ADDR, M68K_DATA, REG_VRAMADDR);
// CPU write to REG_LSPCMODE
FDSCell E105(WR_LSPC_MODE, M68K_DATA[15:12], AA_SPEED[7:4]);
FDSCell C87(WR_LSPC_MODE, M68K_DATA[11:8], AA_SPEED[3:0]);
FDPCell E74(WR_LSPC_MODE, M68K_DATA[7], 1'b1, RESET, TIMER_MODE[2], );
FDRCell E61(WR_LSPC_MODE, M68K_DATA[6:3], RESET, {TIMER_MODE[1:0], TIMER_IRQ_EN, AA_DISABLE});
// CPU write to REG_TIMERSTOP
FDPCell D34(WR_TIMER_STOP, M68K_DATA[0], RESETP, 1'b1, , TIMER_STOP);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : ddr_phy_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_phy_top #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// This parameter must be set based on memory clock frequency
// It must be set to 4 for frequencies above 533 MHz?? (undecided)
// and set to 2 for 533 MHz and below
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter OUTPUT_DRV = "HIGH", // to calib_top
parameter REG_CTRL = "OFF", // to calib_top
parameter RTT_NOM = "60", // to calib_top
parameter RTT_WR = "120", // to calib_top
parameter tCK = 2500, // pS
parameter tRFC = 110000, // pS
parameter tREFI = 7800000, // pS
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter WRLVL = "OFF", // to calib_top
parameter DEBUG_PORT = "OFF", // to calib_top
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// Simulation /debug options
parameter SIM_BYPASS_INIT_CAL = "OFF",
// Parameter used to force skipping
// or abbreviation of initialization
// and calibration. Overrides
// SIM_INIT_OPTION, SIM_CAL_OPTION,
// and disables various other blocks
//parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps
//parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps
parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz)
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter RD_PATH_REG = 0, // optional registers in the read path
// to MC for timing improvement.
// =1 enabled, = 0 disabled
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter TAPSPERKCLK = 56,
parameter POC_USE_METASTABLE_SAMP = "FALSE"
)
(
input clk, // Fabric logic clock
// To MC, calib_top, hard PHY
input clk_ref, // Idelay_ctrl reference clock
// To hard PHY (external source)
input freq_refclk, // To hard PHY for Phasers
input mem_refclk, // Memory clock to hard PHY
input pll_lock, // System PLL lock signal
input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS
input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering
input poc_sample_pd, // Tell POC how to avoid metastability.
input error, // Support for TG error detect
output rst_tg_mc, // Support for TG error detect
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input rst,
input iddr_rst,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// From MC
input [nCK_PER_CLK-1:0] mc_ras_n,
input [nCK_PER_CLK-1:0] mc_cas_n,
input [nCK_PER_CLK-1:0] mc_we_n,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
input mc_reset_n,
input [1:0] mc_odt,
input [nCK_PER_CLK-1:0] mc_cke,
// AUX - For ODT and CKE assertion during reads and writes
input [3:0] mc_aux_out0,
input [3:0] mc_aux_out1,
input mc_cmd_wren,
input mc_ctl_wren,
input [2:0] mc_cmd,
input [1:0] mc_cas_slot,
input [5:0] mc_data_offset,
input [5:0] mc_data_offset_1,
input [5:0] mc_data_offset_2,
input [1:0] mc_rank_cnt,
// Write
input mc_wrdata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask,
input idle,
// DDR bus signals
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// Debug Port Outputs
output [255:0] dbg_calib_top,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output dbg_rddata_valid,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
// FIFO status flags
output phy_mc_ctl_full,
output phy_mc_cmd_full,
output phy_mc_data_full,
// Calibration status and resultant outputs
output init_calib_complete,
output init_wrcal_complete,
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps
);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Parameter used to force skipping or abbreviation of initialization
// and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
// disables various other blocks depending on the option selected
// This option should only be used during simulation. In the case of
// the "SKIP" option, the testbench used should also not be modeling
// propagation delays.
// Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
// "NONE" = options determined by the individual parameter settings
// "SIM_FULL" = skip power-up delay. FULL calibration performed without
// averaging algorithm turned ON during window detection.
// "SKIP" = skip power-up delay. Skip calibration not yet supported.
// "FAST" = skip power-up delay, and calibrate (read leveling, write
// leveling, and phase detector) only using one DQS group, and
// apply the results to all other DQS groups.
localparam SIM_INIT_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" :
((SIM_BYPASS_INIT_CAL == "FAST") ||
(SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" :
"NONE");
localparam SIM_CAL_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" :
(SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" :
((SIM_BYPASS_INIT_CAL == "SIM_FULL") ||
(SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" :
"NONE");
localparam WRLVL_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL;
localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 :
(BYTE_LANES_B2 != 0 ? 3 :
(BYTE_LANES_B1 != 0 ? 2 : 1))));
localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 :
BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 :
0;
localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 :
BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 :
0;
localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 :
BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 :
0;
localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 :
BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 :
0;
localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 :
BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 :
0;
localparam HIGHEST_LANE =
(HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) :
((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) :
((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) :
((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) :
HIGHEST_LANE_B0)));
localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) +
(0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) +
(0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) +
(0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) +
((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) +
(0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) +
(0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) +
(0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) +
((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) +
(0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) +
(0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) +
(0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) +
((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) +
(0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) +
(0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) +
(0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) +
((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) +
(0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) +
(0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) +
(0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]));
// Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
// This should be the case since the PLL should be placed adjacent
// to the same IO Bank as Ck/Addr/Cmd and Control
localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) |
((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ?
3'b000 :
(((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ?
3'b001 :
(((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ?
3'b010 :
(((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ?
3'b011 :
(((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) |
((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ?
3'b100 : 3'b000;
localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ?
8'b00_00_01_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_10 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_00 : 8'b11_10_01_00;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data;
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out;
wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk;
wire phy_mc_go;
wire phy_ctl_full;
wire phy_cmd_full;
wire phy_data_full;
wire phy_pre_data_a_full;
wire if_empty /* synthesis syn_maxfan = 3 */;
wire phy_write_calib;
wire phy_read_calib;
wire [HIGHEST_BANK-1:0] rst_stg1_cal;
wire [5:0] calib_sel;
wire calib_in_common /* synthesis syn_maxfan = 10 */;
wire [HIGHEST_BANK-1:0] calib_zero_inputs;
wire [HIGHEST_BANK-1:0] calib_zero_ctrl;
wire pi_phase_locked;
wire pi_phase_locked_all;
wire pi_found_dqs;
wire pi_dqs_found_all;
wire pi_dqs_out_of_range;
wire pi_enstg2_f;
wire pi_stg2_fincdec;
wire pi_stg2_load;
wire [5:0] pi_stg2_reg_l;
wire idelay_ce;
wire idelay_inc;
wire idelay_ld;
wire [2:0] po_sel_stg2stg3;
wire [2:0] po_stg2_cincdec;
wire [2:0] po_enstg2_c;
wire [2:0] po_stg2_fincdec;
wire [2:0] po_enstg2_f;
wire [8:0] po_counter_read_val;
wire [5:0] pi_counter_read_val;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata;
reg [nCK_PER_CLK-1:0] parity;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n;
wire [nCK_PER_CLK-1:0] phy_ras_n;
wire [nCK_PER_CLK-1:0] phy_cas_n;
wire [nCK_PER_CLK-1:0] phy_we_n;
wire phy_reset_n;
wire [3:0] calib_aux_out;
wire [nCK_PER_CLK-1:0] calib_cke;
wire [1:0] calib_odt;
wire calib_ctl_wren;
wire calib_cmd_wren;
wire calib_wrdata_en;
wire [2:0] calib_cmd;
wire [1:0] calib_seq;
wire [5:0] calib_data_offset_0;
wire [5:0] calib_data_offset_1;
wire [5:0] calib_data_offset_2;
wire [1:0] calib_rank_cnt;
wire [1:0] calib_cas_slot;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address;
wire [3:0] mux_aux_out;
wire [3:0] aux_out_map;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank;
wire [2:0] mux_cmd;
wire mux_cmd_wren;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n;
wire mux_ctl_wren;
wire [1:0] mux_cas_slot;
wire [5:0] mux_data_offset;
wire [5:0] mux_data_offset_1;
wire [5:0] mux_data_offset_2;
wire [nCK_PER_CLK-1:0] mux_ras_n;
wire [nCK_PER_CLK-1:0] mux_cas_n;
wire [1:0] mux_rank_cnt;
wire mux_reset_n;
wire [nCK_PER_CLK-1:0] mux_we_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata;
wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask;
wire mux_wrdata_en;
wire [nCK_PER_CLK-1:0] mux_cke ;
wire [1:0] mux_odt ;
wire phy_if_empty_def;
wire phy_if_reset;
wire phy_init_data_sel;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map;
wire phy_rddata_valid_w;
reg rddata_valid_reg;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg;
wire [4:0] idelaye2_init_val;
wire [5:0] oclkdelay_init_val;
wire po_counter_load_en;
wire [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb;
wire fine_delay_sel;
wire pd_out;
//***************************************************************************
assign dbg_rddata_valid = rddata_valid_reg;
assign dbg_rddata = rd_data_reg;
assign dbg_rd_data_offset = calib_rd_data_offset_0;
assign dbg_pi_phaselocked_done = pi_phase_locked_all;
assign dbg_po_counter_read_val = po_counter_read_val;
assign dbg_pi_counter_read_val = pi_counter_read_val;
//***************************************************************************
genvar i;
generate
for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen
assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i];
assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1];
end
endgenerate
//***************************************************************************
// During memory initialization and calibration the calibration logic drives
// the memory signals. After calibration is complete the memory controller
// drives the memory signals.
// Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
//***************************************************************************
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ;
genvar v ;
generate
if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm
for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin
if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin
assign mc_cs_n_temp[v] = mc_cs_n[v] ;
end else begin
assign mc_cs_n_temp[v] = 'b1 ;
end
end
end else begin
assign mc_cs_n_temp = mc_cs_n ;
end
endgenerate
assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata;
assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0;
assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address;
assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank;
assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n;
assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n;
assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n;
assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n;
assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n;
assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out;
assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ;
assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ;
assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren :
calib_cmd_wren;
assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren :
calib_ctl_wren;
assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en :
calib_wrdata_en;
assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd;
assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot;
assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset :
calib_data_offset_0;
assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 :
calib_data_offset_1;
assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 :
calib_data_offset_2;
// Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
assign mux_rank_cnt = 2'b00;
// Assigning cke & odt for DDR2 & DDR3
// No changes for DDR3 & DDR2 dual rank
// DDR2 single rank systems might potentially need 3 odt signals.
// Aux_out[2] will have the odt toggled by phy and controller
// wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
// all of the three odt bits or some of them might be used.
// mapping done in mc_phy_wrapper module
generate
if(CKE_ODT_AUX == "TRUE") begin
assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ?
{mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} :
mux_aux_out;
end else begin
assign aux_out_map = 4'b0000 ;
end
endgenerate
assign init_calib_complete = phy_init_data_sel;
assign phy_mc_ctl_full = phy_ctl_full;
assign phy_mc_cmd_full = phy_cmd_full;
assign phy_mc_data_full = phy_pre_data_a_full;
//***************************************************************************
// Generate parity for DDR3 RDIMM.
//***************************************************************************
generate
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3],
mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3],
mux_cas_n[3], mux_ras_n[3], mux_we_n[3]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0],mux_ras_n[0], mux_we_n[0]});
parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2],
mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2],
mux_cas_n[2],mux_ras_n[2], mux_we_n[2]});
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0],
mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0], mux_ras_n[0], mux_we_n[0]});
end
end
end else begin: gen_ddr3_noparity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
parity[2] <= #TCQ 1'b0;
parity[3] <= #TCQ 1'b0;
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
end
end
end
endgenerate
//***************************************************************************
// Code for optional register stage in read path to MC for timing
//***************************************************************************
generate
if(RD_PATH_REG == 1)begin:RD_REG_TIMING
always @(posedge clk)begin
rddata_valid_reg <= #TCQ phy_rddata_valid_w;
rd_data_reg <= #TCQ rd_data_map;
end // always @ (posedge clk)
end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING
always @(phy_rddata_valid_w or rd_data_map)begin
rddata_valid_reg = phy_rddata_valid_w;
rd_data_reg = rd_data_map;
end
end
endgenerate
assign phy_rddata_valid = rddata_valid_reg;
assign phy_rd_data = rd_data_reg;
//***************************************************************************
// Hard PHY and accompanying bit mapping logic
//***************************************************************************
mig_7series_v2_3_ddr_mc_phy_wrapper #
(
.TCQ (TCQ),
.tCK (tCK),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CK_WIDTH (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.CWL (CWL),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.HIGHEST_BANK (HIGHEST_BANK),
.HIGHEST_LANE (HIGHEST_LANE),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DRAM_WIDTH (DRAM_WIDTH),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_ddr_mc_phy_wrapper
(
.rst (rst),
.iddr_rst (iddr_rst),
.clk (clk),
// For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
// For memory frequencies below 400 MHz mem_refclk = mem_refclk and
// freq_refclk = 2x or 4x mem_refclk such that it remains in the
// 400~1066 MHz range
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.mmcm_ps_clk (mmcm_ps_clk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.idelayctrl_refclk (clk_ref),
.phy_cmd_wr_en (mux_cmd_wren),
.phy_data_wr_en (mux_wrdata_en),
// phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
// DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
// AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
// The fields ACTPRE, and BankCount are only used
// when the hard PHY counters are used by the MC.
.phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset,
mux_rank_cnt, 3'd0, aux_out_map,
5'd0, mux_cmd}),
.phy_ctl_wr (mux_ctl_wren),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
.data_offset_1 (mux_data_offset_1),
.data_offset_2 (mux_data_offset_2),
.aux_in_1 (aux_out_map),
.aux_in_2 (aux_out_map),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
.if_empty (if_empty),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.phy_pre_data_a_full (phy_pre_data_a_full),
.ddr_clk (ddr_clk),
.phy_mc_go (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.po_fine_enable (po_enstg2_f),
.po_coarse_enable (po_enstg2_c),
.po_fine_inc (po_stg2_fincdec),
.po_coarse_inc (po_stg2_cincdec),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_en (1'b1),
.po_sel_fine_oclk_delay (po_sel_stg2stg3),
.po_counter_load_val (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (rst_stg1_cal),
.pi_fine_enable (pi_enstg2_f),
.pi_fine_inc (pi_stg2_fincdec),
.pi_counter_load_en (pi_stg2_load),
.pi_counter_load_val (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
// Currently not being used. May be used in future if periodic reads
// become a requirement. This output could also be used to signal a
// catastrophic failure in read capture and the need for re-cal
.pi_dqs_out_of_range (pi_dqs_out_of_range),
.phy_init_data_sel (phy_init_data_sel),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.mux_address (mux_address),
.mux_bank (mux_bank),
.mux_cs_n (mux_cs_n),
.mux_ras_n (mux_ras_n),
.mux_cas_n (mux_cas_n),
.mux_we_n (mux_we_n),
.mux_reset_n (mux_reset_n),
.parity_in (parity),
.mux_wrdata (mux_wrdata),
.mux_wrdata_mask (mux_wrdata_mask),
.mux_odt (mux_odt),
.mux_cke (mux_cke),
.idle (idle),
.rd_data (rd_data_map),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_parity (ddr_parity),
.ddr_ras_n (ddr_ras_n),
.ddr_we_n (ddr_we_n),
.ddr_dq (ddr_dq),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_reset_n (ddr_reset_n),
.dbg_pi_counter_read_en (1'b1),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.byte_sel_cnt (byte_sel_cnt),
.pd_out (pd_out),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
//***************************************************************************
// Soft memory initialization and calibration logic
//***************************************************************************
mig_7series_v2_3_ddr_calib_top #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.nCK_PER_CLK (nCK_PER_CLK),
.PRE_REV3ES (PRE_REV3ES),
.tCK (tCK),
.CLK_PERIOD (CLK_PERIOD),
.N_CTL_LANES (N_CTL_LANES),
.CTL_BYTE_LANE (CTL_BYTE_LANE),
.CTL_BANK (CTL_BANK),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (8),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.HIGHEST_BANK (HIGHEST_BANK),
.BANK_TYPE (BANK_TYPE),
.HIGHEST_LANE (HIGHEST_LANE),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.CS_WIDTH (CS_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.PER_BIT_DESKEW ("OFF"),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (CL),
.nCWL (CWL),
.tRFC (tRFC),
.tREFI (tREFI),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL_W),
.USE_ODT_PORT (USE_ODT_PORT),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_ddr_calib_top
(
.clk (clk),
.rst (rst),
.tg_err (error),
.rst_tg_mc (rst_tg_mc),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
// PHY Control Block and IN_FIFO status
.phy_ctl_ready (phy_mc_go),
.phy_ctl_full (1'b0),
.phy_cmd_full (1'b0),
.phy_data_full (1'b0),
.phy_if_empty (if_empty),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
// From calib logic To data IN_FIFO
// DQ IDELAY tap value from Calib logic
// port to be added to mc_phy by Gary
.dlyval_dq (),
// hard PHY calibration modes
.write_calib (phy_write_calib),
.read_calib (phy_read_calib),
// DQS count and ck/addr/cmd to be mapped to calib_sel
// based on parameter that defines placement of ctl lanes
// and DQS byte groups in each bank. When phy_write_calib
// is de-asserted calib_sel should select CK/addr/cmd/ctl.
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
// Signals from calib logic to be MUXED with MC
// signals before sending to hard PHY
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_odt (calib_odt),
.calib_cke (calib_cke),
.calib_cmd (calib_cmd),
.calib_wrdata_en (calib_wrdata_en),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.phy_reset_n (phy_reset_n),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_cas_n (phy_cas_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
// DQS Phaser_IN calibration/status signals
.pi_phaselocked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_found_dqs (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.pi_rst_stg1_cal (rst_stg1_cal),
.pi_en_stg2_f (pi_enstg2_f),
.pi_stg2_f_incdec (pi_stg2_fincdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en),
// IDELAY tap enable and inc signals
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
// DQS Phaser_OUT calibration/status signals
.po_sel_stg2stg3 (po_sel_stg2stg3),
.po_stg2_c_incdec (po_stg2_cincdec),
.po_en_stg2_c (po_enstg2_c),
.po_stg2_f_incdec (po_stg2_fincdec),
.po_en_stg2_f (po_enstg2_f),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_val (po_counter_read_val),
// From data IN_FIFO To Calib logic and MC/UI
.phy_rddata (rd_data_map),
// From calib logic To MC
.phy_rddata_valid (phy_rddata_valid_w),
.calib_rd_data_offset_0 (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.calib_writes (),
// Mem Init and Calibration status To MC
.init_calib_complete (phy_init_data_sel),
.init_wrcal_complete (init_wrcal_complete),
// Debug Error signals
.pi_phase_locked_err (dbg_pi_phaselock_err),
.pi_dqsfound_err (dbg_pi_dqsfound_err),
.wrcal_err (dbg_wrcal_err),
//used for oclk stg3 centering
.pd_out (pd_out),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.poc_sample_pd (poc_sample_pd),
// Debug Signals
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_calib_top (dbg_calib_top),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.byte_sel_cnt (byte_sel_cnt),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem2x
#(
parameter DEPTH_WORDS=1,
parameter WIDTH=32,
parameter RDW_MODE="DONT_CARE",
parameter RAM_OPERATION_MODE = "BIDIR_DUAL_PORT", // altsyncram's OPERATION_MODE parameter
parameter RAM_BLOCK_TYPE = "AUTO" // altsyncram's RAM_BLOCK_TYPE parameter
)
(
input clk,
input clk2x,
input resetn,
input [WIDTH-1:0] avs_port1_writedata,
input [WIDTH-1:0] avs_port2_writedata,
input [WIDTH-1:0] avs_port3_writedata,
input [WIDTH-1:0] avs_port4_writedata,
input [WIDTH/8-1:0] avs_port1_byteenable,
input [WIDTH/8-1:0] avs_port2_byteenable,
input [WIDTH/8-1:0] avs_port3_byteenable,
input [WIDTH/8-1:0] avs_port4_byteenable,
input [$clog2(DEPTH_WORDS)-1:0] avs_port1_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port2_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port3_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port4_address,
input avs_port1_read,
input avs_port2_read,
input avs_port3_read,
input avs_port4_read,
input avs_port1_write,
input avs_port2_write,
input avs_port3_write,
input avs_port4_write,
output reg [WIDTH-1:0] avs_port1_readdata,
output reg [WIDTH-1:0] avs_port2_readdata,
output reg [WIDTH-1:0] avs_port3_readdata,
output reg [WIDTH-1:0] avs_port4_readdata,
output avs_port1_readdatavalid,
output avs_port2_readdatavalid,
output avs_port3_readdatavalid,
output avs_port4_readdatavalid,
output avs_port1_waitrequest,
output avs_port2_waitrequest,
output avs_port3_waitrequest,
output avs_port4_waitrequest
);
localparam LOG2DEPTH = $clog2( DEPTH_WORDS );
assign avs_port1_waitrequest=1'b0;
assign avs_port2_waitrequest=1'b0;
assign avs_port3_waitrequest=1'b0;
assign avs_port4_waitrequest=1'b0;
wire [WIDTH-1:0] data_out_a_unreg;
wire [WIDTH-1:0] data_out_b_unreg;
reg [WIDTH-1:0] data_out_a_reg;
reg [WIDTH-1:0] data_out_b_reg;
reg [WIDTH-1:0] data_out_a_reg2;
reg [WIDTH-1:0] data_out_b_reg2;
_acl_mem2x_shiftreg readatavalid_1(.D(avs_port1_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port1_readdatavalid));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_2(.D(avs_port2_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port2_readdatavalid));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_3(.D(avs_port3_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port3_readdatavalid));
defparam readatavalid_3.WIDTH = 1;
defparam readatavalid_3.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_4(.D(avs_port4_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port4_readdatavalid));
defparam readatavalid_4.WIDTH = 1;
defparam readatavalid_4.DEPTH = 4;
localparam PREFERRED_WIDTH=128;
localparam NUM_RAMS=((WIDTH+PREFERRED_WIDTH-1)/PREFERRED_WIDTH);
genvar n;
generate
for(n=0; n<NUM_RAMS; n++)
begin : block_n
localparam MY_WIDTH=( (n==NUM_RAMS-1) ? (WIDTH-(NUM_RAMS-1)*PREFERRED_WIDTH) : PREFERRED_WIDTH );
reg [LOG2DEPTH-1:0] addr_1_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg2x /* synthesis dont_merge */;
reg write_1_reg2x /* synthesis dont_merge */;
reg write_2_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_1_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_3_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_4_reg /* synthesis dont_merge */;
reg write_1_reg, write_2_reg /* synthesis dont_merge */;
reg write_3_reg, write_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_4_reg /* synthesis dont_merge */;
reg clk_90deg, sel2x /* synthesis dont_merge */;
//Convert clock to data signal
always@(negedge clk2x)
clk_90deg<=clk;
always@(posedge clk2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clk
always@(posedge clk2x)
begin
addr_1_reg2x <= (!sel2x) ? addr_2_reg : addr_1_reg;
addr_2_reg2x <= (!sel2x) ? addr_4_reg : addr_3_reg;
write_1_reg2x <= (!sel2x) ? write_2_reg : write_1_reg;
write_2_reg2x <= (!sel2x) ? write_4_reg : write_3_reg;
end
always@(posedge clk)
begin
addr_1_reg <= avs_port1_address;
addr_2_reg <= avs_port2_address;
addr_3_reg <= avs_port3_address;
addr_4_reg <= avs_port4_address;
write_1_reg <= avs_port1_write;
write_2_reg <= avs_port2_write;
write_3_reg <= avs_port3_write;
write_4_reg <= avs_port4_write;
end
//Register before double pumping
always@(posedge clk)
begin
data_1_reg <= avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_2_reg <= avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_3_reg <= avs_port3_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_4_reg <= avs_port4_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_1_reg <= avs_port1_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_2_reg <= avs_port2_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_3_reg <= avs_port3_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_4_reg <= avs_port4_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
// Consider making only one port r/w and the rest read only
always@(posedge clk2x)
begin
data_1_reg2x <= (!sel2x) ? data_2_reg : data_1_reg;
data_2_reg2x <= (!sel2x) ? data_4_reg : data_3_reg;
byteen_1_reg2x <= (!sel2x) ? byteen_2_reg : byteen_1_reg;
byteen_2_reg2x <= (!sel2x) ? byteen_4_reg : byteen_3_reg;
end
altsyncram altsyncram_component (
.clock0 (clk2x),
.wren_a (write_1_reg2x),
.wren_b (write_2_reg2x),
.address_a (addr_1_reg2x),
.address_b (addr_2_reg2x),
.data_a (data_1_reg2x),
.data_b (data_2_reg2x),
.q_a (data_out_a_unreg[n*PREFERRED_WIDTH +: MY_WIDTH]),
.q_b (data_out_b_unreg[n*PREFERRED_WIDTH +: MY_WIDTH]),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (byteen_1_reg2x),
.byteena_b (byteen_2_reg2x),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH_WORDS,
altsyncram_component.numwords_b = DEPTH_WORDS,
altsyncram_component.operation_mode = RAM_OPERATION_MODE,
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = RDW_MODE,
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = MY_WIDTH,
altsyncram_component.width_b = MY_WIDTH,
altsyncram_component.width_byteena_a = MY_WIDTH/8,
altsyncram_component.width_byteena_b = MY_WIDTH/8,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.ram_block_type = RAM_BLOCK_TYPE;
end
endgenerate
always@(posedge clk2x)
begin
data_out_a_reg<=data_out_a_unreg;
data_out_b_reg<=data_out_b_unreg;
data_out_a_reg2<=data_out_a_reg;
data_out_b_reg2<=data_out_b_reg;
end
always@(posedge clk)
begin
avs_port1_readdata <= data_out_a_reg;
avs_port2_readdata <= data_out_a_reg2;
avs_port3_readdata <= data_out_b_reg;
avs_port4_readdata <= data_out_b_reg2;
end
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module _acl_mem2x_shiftreg(D, clock, resetn, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, resetn, enable;
output [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn)
local_ffs <= '0;
else if (enable)
local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probec_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V |
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
MatchTemplateBin
:Function
Match a binary from template for binary images.
It will give the first output after 1 cycle while in_enable enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module MatchTemplateBin(
clk,
rst_n,
template,
in_enable,
in_data,
out_ready,
out_data);
/*
::description
This module's working mode.
::range
0 for Pipeline, 1 for Req-ack
*/
parameter[0 : 0] work_mode = 0;
/*
::description
The width(and height) of window.
::range
2 - 15
*/
parameter[3 : 0] window_width = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Reset, active low.
*/
input[window_width * window_width - 1 : 0] template;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [window_width * window_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output out_data;
reg reg_out_data;
reg reg_out_ready;
generate
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
reg_out_ready <= 0;
end else begin
reg_out_ready <= 1;
end
end
assign out_ready = reg_out_ready;
if(work_mode == 0) begin
always @(posedge clk)
reg_out_data <= in_data == template ? 1 : 0;
end else begin
always @(posedge in_enable)
reg_out_data <= in_data == template ? 1 : 0;
end
assign out_data = out_ready ? reg_out_data : 0;
endgenerate
endmodule |
module crc_datapath
(
//OUTPUTS
output [31:0] crc_out,
output [ 1:0] size_out,
output [ 7:0] crc_idr_out,
output [31:0] crc_poly_out,
output [31:0] crc_init_out,
//INPUTS
input [31:0] bus_wr, //Write data Bus
input [ 1:0] rev_in_type, //select type of reversion of bus
input rev_out_type,
input buffer_en,
input byte_en,
input crc_init_en,
input crc_out_en,
input crc_idr_en,
input crc_poly_en,
input buffer_rst,
input bypass_byte0,
input bypass_size,
input [1:0] byte_sel,
input [1:0] size_in,
input clear_crc_init_sel,
input set_crc_init_sel,
input [1:0] crc_poly_size,
input clk,
input rst_n
);
//Reset definitions
localparam RESET_BUFFER = 32'hffffffff;
localparam RESET_BYTE = 32'hffffffff;
localparam RESET_BF_SIZE = 2'b10;
localparam RESET_SIZE = 2'b10;
localparam RESET_CRC_INIT_SEL = 1'b0;
localparam RESET_CRC_INIT = 32'hffffffff;
localparam RESET_CRC_OUT = 32'h0;
localparam RESET_CRC_IDR = 8'h0;
localparam RESET_CRC_POLY = 32'h04c11db7;
//Parameters definitions
localparam BYTE_0 = 2'b00;
localparam BYTE_1 = 2'b01;
localparam BYTE_2 = 2'b10;
localparam BYTE_3 = 2'b11;
localparam POLY_SIZE_32 = 2'b00;
localparam POLY_SIZE_16 = 2'b01;
localparam POLY_SIZE_8 = 2'b10;
localparam POLY_SIZE_7 = 2'b11;
//Flops Definition
reg [31:0] buffer_ff;
reg [31:0] byte_ff;
reg [31:0] crc_init_ff;
reg [31:0] crc_out_ff;
reg [31:0] crc_poly_ff;
reg [ 7:0] crc_idr_ff;
reg [ 1:0] bf_size_ff;
reg [ 1:0] size_ff;
reg crc_init_sel_ff;
//internal signals definition
reg [7:0] crc_data_in;
reg crc_poly_size_7;
reg crc_poly_size_8;
reg crc_poly_size_16;
reg crc_poly_size_32;
wire [31:0] bus_reversed;
wire [31:0] crc_init_mux;
wire [31:0] crc_unit_out;
wire [31:0] crc_poly_size_in;
wire [31:0] crc_out_rev;
wire [ 7:0] byte0_in;
wire [ 7:0] byte1_in;
wire [ 7:0] byte2_in;
wire [ 7:0] byte3_in;
wire [ 7:0] byte0_mux_out;
//Instantiatin of bit_reversed module
//to perform reversion fuctionality according with rev_type bits
bit_reversal
#(
.DATA_SIZE ( 32 )
)REV_IN
(
.data_out ( bus_reversed ),
.data_in ( bus_wr ),
.rev_type ( rev_in_type )
);
//Definition of Registers buffer_ff and byte_ff
always @(posedge clk)
begin
if(!rst_n)
begin
buffer_ff <= RESET_BUFFER;
byte_ff <= RESET_BYTE;
end
else
begin
if(buffer_en)
buffer_ff <= bus_reversed;
//else
// if(buffer_rst)
// buffer_ff <= RESET_BUFFER;
if(byte_en)
byte_ff <= buffer_ff;
end
end
//Definition of Registers bf_size_ff and size_ff
always @(posedge clk)
begin
if(!rst_n)
begin
bf_size_ff <= RESET_BF_SIZE;
size_ff <= RESET_SIZE;
end
else
begin
if(buffer_en)
bf_size_ff <= size_in;
else
if(buffer_rst)
bf_size_ff <= RESET_BF_SIZE;
if(byte_en)
size_ff <= bf_size_ff;
end
end
//Mux to bypass size_ff
//This informatin is used by FSM to decide the size of the current operatin
assign size_out = (bypass_size) ? bf_size_ff : size_ff;
assign byte0_in = byte_ff[ 7: 0];
assign byte1_in = byte_ff[15: 8];
assign byte2_in = byte_ff[23:16];
assign byte3_in = byte_ff[31:24];
//Mux to bypass byte0_ff
assign byte0_mux_out = (bypass_byte0) ? buffer_ff[7:0] : byte0_in;
//Mux to select input of CRC Unit
//TODO:AVALIAR A INFLUENCIA DA CODIFICACAO DA FSM NO SINAL BYTE_SEL
always @(*)
begin
crc_data_in = 32'h0;
case(byte_sel)
BYTE_0: crc_data_in = byte0_mux_out;
BYTE_1: crc_data_in = byte1_in;
BYTE_2: crc_data_in = byte2_in;
BYTE_3: crc_data_in = byte3_in;
default:crc_data_in = 32'h0;
endcase
end
//Definition of Register crc_init_sel_ff
//This is a set/clear flop where the clear wins set
//This flop controls when the CRC operation is chained (crc_init_sel_ff = 1) or not
//In the chained operatin the current crc calculation depends of the previous crc calculated
//in the unchained operatin the current crc calculation depends of value of crc_init register
always @(posedge clk)
begin
if(!rst_n)
crc_init_sel_ff <= RESET_CRC_INIT_SEL;
else
begin
if(clear_crc_init_sel)
crc_init_sel_ff <= 1'b0;
else
if(set_crc_init_sel)
crc_init_sel_ff <= 1'b1;
end
end
//This register contains the init value used in non chained operatin of crc
assign crc_init_out = crc_init_ff;
always @(posedge clk)
begin
if(!rst_n)
crc_init_ff <= RESET_CRC_INIT;
else
if(crc_init_en)
crc_init_ff <= bus_wr;
else
if(buffer_rst)
crc_init_ff <= RESET_CRC_INIT;
end
//This register contains the final value of crc
always @(posedge clk)
begin
if(!rst_n)
crc_out_ff <= RESET_CRC_OUT;
else
if(crc_out_en)
crc_out_ff <= crc_unit_out;
end
//this is a general purpouse register
//see the spec for more details
assign crc_idr_out = crc_idr_ff;
always @(posedge clk)
begin
if(!rst_n)
crc_idr_ff <= RESET_CRC_IDR;
else
if(crc_idr_en)
crc_idr_ff <= bus_wr[7:0];
end
//This register contains the polynomial coefficients to crc calculation
assign crc_poly_out = crc_poly_ff;
always @(posedge clk)
begin
if(!rst_n)
crc_poly_ff <= RESET_CRC_POLY;
else
if(crc_poly_en)
crc_poly_ff <= bus_wr;
end
//Mux that define the type of operation (chained or not)
assign crc_init_mux = (crc_init_sel_ff) ? crc_out_ff : crc_init_ff;
//Decoding of crc_poly_sizesignal
always @(*)
begin
crc_poly_size_7 = 1'b0;
crc_poly_size_8 = 1'b0;
crc_poly_size_16 = 1'b0;
crc_poly_size_32 = 1'b0;
case(crc_poly_size)
POLY_SIZE_7 : crc_poly_size_7 = 1'b1;
POLY_SIZE_8 : crc_poly_size_8 = 1'b1;
POLY_SIZE_16: crc_poly_size_16 = 1'b1;
POLY_SIZE_32: crc_poly_size_32 = 1'b1;
endcase
end
//This signal define the configurability of the CRC Unit
//In this case, the size of the polynomial can be: 7, 8, 16 or 32
assign crc_poly_size_in = {crc_poly_size_32, 15'h0, crc_poly_size_16, 7'h0, crc_poly_size_8, crc_poly_size_7, 6'h0};
//Instanciation of CRC Unit
//The module is configured to calculate CRC of 32 bits for 8 bits of data in parallel
crc_parallel
#(
.CRC_SIZE ( 32 ),
.FRAME_SIZE ( 8 )
)CRC_UNIT
(
.crc_out ( crc_unit_out ),
.data_in ( crc_data_in ),
.crc_init ( crc_init_mux ),
.crc_poly ( crc_poly_ff ),
.crc_poly_size ( crc_poly_size_in )
);
//crc_out_rev[31:0] = crc_out_ff[0:31]
generate
genvar i;
for(i = 0; i < 32; i = i + 1)
assign crc_out_rev[i] = crc_out_ff[31 - i];
endgenerate
assign crc_out = (rev_out_type) ? crc_out_rev : crc_out_ff;
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`include "pcie_defines.v"
`include "nysa_pcie_defines.v"
module pcie_control (
input clk,
input rst,
//Configuration Values
input [7:0] i_pcie_bus_num,
input [4:0] i_pcie_dev_num,
input [2:0] i_pcie_fun_num,
//Ingress Machine Interface
input [31:0] i_write_a_addr,
input [31:0] i_write_b_addr,
input [31:0] i_read_a_addr,
input [31:0] i_read_b_addr,
input [31:0] i_status_addr,
input [31:0] i_buffer_size,
input [31:0] i_dev_addr,
input [31:0] i_ping_value,
input [1:0] i_update_buf,
input i_update_buf_stb,
input i_reg_write_stb,
//Nysa Interface
input [31:0] i_interrupt_value,
input i_interrupt_stb,
output reg o_interrupt_send_en,
input i_interrupt_send_rdy,
//In band reset
input i_cmd_rst_stb,
//Command Strobes
input i_cmd_wr_stb,
input i_cmd_rd_stb,
input i_cmd_flg_fifo,
input i_cmd_flg_sel_periph,
input i_cmd_flg_sel_memory,
input i_cmd_flg_sel_dma,
input i_cmd_ping_stb,
input i_cmd_rd_cfg_stb,
input i_cmd_unknown,
input [31:0] i_cmd_data_count,
input [31:0] i_cmd_data_address,
//User Control Interface
output reg o_per_sel,
output reg o_mem_sel,
output reg o_dma_sel,
output o_data_fifo_sel,
input i_write_fin,
input i_read_fin,
output reg [31:0] o_data_size,
output reg [31:0] o_data_address,
output reg o_data_fifo_flg,
output reg o_data_read_flg,
output reg o_data_write_flg,
//Flow Controller
//Peripheral/Memory/DMA Egress FIFO Interface
input i_e_fifo_rdy,
input [23:0] i_e_fifo_size,
//Egress State Machine
output o_egress_enable,
input i_egress_finished,
output [7:0] o_egress_tlp_command,
output [13:0] o_egress_tlp_flags,
output [31:0] o_egress_tlp_address,
output [15:0] o_egress_tlp_requester_id,
output [7:0] o_egress_tag,
//Egress FIFO for control data
output reg o_ctr_sel,
output reg [7:0] o_interrupt_msi_value,
//output reg o_interrupt_stb,
output o_egress_fifo_rdy,
input i_egress_fifo_act,
output [23:0] o_egress_fifo_size,
input i_egress_fifo_stb,
output [31:0] o_egress_fifo_data,
//Flow Control Interface
input i_fc_ready,
output reg o_fc_cmt_stb,
//Ingress Buffer Interface
input i_ibm_buf_fin_stb, // ingress buffer manager (Buffer Finished Strobe)
input [1:0] i_ibm_buf_fin, // ingress buffer manager (Buffer Finished)
output reg o_ibm_en, // ingress buffer manager (Enable Buffer Manager)
output reg o_ibm_req_stb, // ingress buffer manager (Request Buffer Strobe)
output reg o_ibm_dat_fin,
input [7:0] i_ibm_tag, // ingress buffer manager (Tag to use)
input i_ibm_tag_rdy, // ingress buffer manager (Tag is ready)
input [9:0] i_ibm_dword_cnt, // ingress buffer manager (Dword Count)
input [11:0] i_ibm_start_addr,
input i_ibm_buf_sel,
input i_ibm_idle,
//Buffer Builder
input [23:0] i_buf_max_size,
output reg [23:0] o_buf_data_count,
output reg [9:0] o_dword_req_cnt,
output o_sys_rst,
output reg [7:0] o_cfg_read_exec,
output [3:0] o_cfg_sm_state,
output [3:0] o_sm_state
);
//local parameters
localparam IDLE = 4'h0;
localparam EGRESS_DATA_FLOW = 4'h1;
localparam WAIT_FOR_HOST_EGRESS_BUFFER = 4'h2;
localparam WAIT_FOR_FPGA_EGRESS_FIFO = 4'h3;
localparam SEND_EGRESS_DATA = 4'h4;
localparam SEND_EGRESS_STATUS = 4'h5;
localparam INGRESS_PREPARE = 4'h6;
localparam INGRESS_DATA_FLOW = 4'h7;
localparam WAIT_FOR_HOST_INGRESS_TAG = 4'h8;
localparam WAIT_FOR_FLOW_CONTROL = 4'h9;
localparam REQUEST_INGRESS_DATA = 4'hA;
localparam SEND_INGRESS_STATUS = 4'hB;
localparam SEND_CONFIG = 4'hC;
localparam PREPARE = 4'h1;
localparam LOAD_FIFO = 4'h2;
localparam CFG_SEND_CONFIG = 4'h3;
localparam SEND_INT = 4'h4;
localparam FINISH = 4'h5;
//registes/wires
reg [3:0] state;
wire [1:0] w_fifo_rdy;
reg [1:0] r_fifo_act;
wire [23:0] w_fifo_size;
reg r_fifo_stb;
reg [31:0] r_fifo_data;
reg [4:0] r_fifo_count;
wire [31:0] register_map [`CONFIG_REGISTER_COUNT:0];
wire [31:0] w_comm_status;
wire w_sts_ready;
reg r_sts_ping;
reg r_sts_read_cfg;
reg r_sts_unknown_cmd;
reg r_sts_interrupt;
wire w_sts_flg_fifo_stall;
wire w_sts_hst_buf_stall;
reg r_sts_cmd_err;
reg r_sts_reset;
reg r_sts_done;
reg [31:0] r_index_valuea;
reg [31:0] r_index_valueb;
reg [31:0] r_data_count;
reg [31:0] r_data_pos;
reg [23:0] r_block_count;
reg [23:0] r_fifo_size;
reg r_buf_sel;
//reg r_buf_next_sel;
reg [1:0] r_buf_rdy;
reg [1:0] r_buf_done;
reg [1:0] r_tmp_done;
reg r_send_data_en;
reg r_delay_stb;
reg [7:0] r_tlp_command; //XXX: When send to host MWR, when get from host MRD
reg [13:0] r_tlp_flags;
reg [31:0] r_tlp_address; //XXX: Need to figure out this!
reg [15:0] r_tlp_requester_id; //XXX: Need to figure out this!
reg [7:0] r_tlp_tag; //XXX: Need to figure out this!
reg r_send_cfg_en;
reg r_send_cfg_fin;
//Configuration State Machine
reg [3:0] cfg_state;
wire r_cfg_ready;
reg r_cfg_chan_en;
//Convenience Signals
wire w_valid_bus_select;
wire w_cfg_req;
wire [23:0] w_ingress_count_left;
assign w_ingress_count_left = (o_data_size - r_data_count);
wire [31:0] write_buf_map [0:1];
assign write_buf_map[0] = i_write_a_addr;
assign write_buf_map[1] = i_write_b_addr;
wire [31:0] read_buf_map [0:1];
assign read_buf_map[0] = i_read_a_addr;
assign read_buf_map[1] = i_read_b_addr;
//submodules
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (4 ) //16 32-bit values for the control
) egress_fifo (
.reset (rst || i_cmd_rst_stb),
//Write Side
.write_clock (clk ),
.write_ready (w_fifo_rdy ),
.write_activate (r_fifo_act ),
.write_fifo_size (w_fifo_size ),
.write_strobe (r_fifo_stb ),
.write_data (r_fifo_data ),
//Read Side
.read_clock (clk ),
.read_ready (o_egress_fifo_rdy ),
.read_activate (i_egress_fifo_act ),
.read_count (o_egress_fifo_size ),
.read_strobe (i_egress_fifo_stb ),
.read_data (o_egress_fifo_data )
);
//asynchronous logic
assign register_map [`HDR_STATUS_BUF_ADDR ] = i_status_addr;
assign register_map [`HDR_BUFFER_READY ] = {29'h00, r_buf_rdy};
assign register_map [`HDR_WRITE_BUF_A_ADDR ] = i_write_a_addr;
assign register_map [`HDR_WRITE_BUF_B_ADDR ] = i_write_b_addr;
assign register_map [`HDR_READ_BUF_A_ADDR ] = i_read_a_addr;
assign register_map [`HDR_READ_BUF_B_ADDR ] = i_read_b_addr;
assign register_map [`HDR_BUFFER_SIZE ] = i_buffer_size;
//assign register_map [`HDR_PING_VALUE ] = i_ping_value;
assign register_map [`HDR_INDEX_VALUEA ] = r_index_valuea;
assign register_map [`HDR_INDEX_VALUEB ] = r_index_valueb;
assign register_map [`HDR_DEV_ADDR ] = i_dev_addr;
assign register_map [`STS_DEV_STATUS ] = w_comm_status;
//assign register_map [`STS_BUF_RDY ] = {29'h00, r_buf_done[1] , r_buf_done[0] };
assign register_map [`STS_BUF_RDY ] = {29'h00, r_buf_done};
assign register_map [`STS_BUF_POS ] = r_data_pos;
assign register_map [`STS_INTERRUPT ] = i_interrupt_value;
//Status Register
assign w_comm_status[`STATUS_UNUSED ] = 0;
assign w_comm_status[`STATUS_BIT_CMD_ERR ] = r_sts_cmd_err;
assign w_comm_status[`STATUS_BIT_RESET ] = r_sts_reset;
assign w_comm_status[`STATUS_BIT_DONE ] = r_sts_done;
assign w_comm_status[`STATUS_BIT_READY ] = w_sts_ready;
assign w_comm_status[`STATUS_BIT_WRITE ] = o_data_write_flg;
assign w_comm_status[`STATUS_BIT_READ ] = o_data_read_flg;
assign w_comm_status[`STATUS_BIT_FIFO ] = o_data_fifo_flg;
assign w_comm_status[`STATUS_BIT_PING ] = r_sts_ping;
assign w_comm_status[`STATUS_BIT_READ_CFG ] = r_sts_read_cfg;
assign w_comm_status[`STATUS_BIT_UNKNOWN_CMD ] = r_sts_unknown_cmd;
assign w_comm_status[`STATUS_BIT_PPFIFO_STALL ] = w_sts_flg_fifo_stall;
assign w_comm_status[`STATUS_BIT_HOST_BUF_STALL] = w_sts_hst_buf_stall;
assign w_comm_status[`STATUS_BIT_PERIPH ] = o_per_sel;
assign w_comm_status[`STATUS_BIT_MEM ] = o_mem_sel;
assign w_comm_status[`STATUS_BIT_DMA ] = o_dma_sel;
assign w_comm_status[`STATUS_BIT_INTERRUPT ] = r_sts_interrupt;
assign o_sys_rst = i_cmd_rst_stb;
assign o_data_fifo_sel = (!r_cfg_chan_en) ? (o_per_sel || o_mem_sel || o_dma_sel): 1'b0;
assign o_egress_enable = r_cfg_chan_en || r_send_data_en;
assign o_egress_tlp_command = (r_cfg_chan_en) ? `PCIE_MWR_32B:
r_tlp_command;
assign o_egress_tlp_flags = (r_cfg_chan_en) ? (`FLAG_NORMAL):
r_tlp_flags;
assign o_egress_tlp_address = (r_cfg_chan_en) ? i_status_addr:
r_tlp_address;
//assign o_egress_tlp_requester_id = (r_cfg_chan_en) ? 16'h0:
// r_tlp_requester_id;
assign o_egress_tlp_requester_id = {i_pcie_bus_num, i_pcie_dev_num, i_pcie_fun_num};
assign o_egress_tag = (r_cfg_chan_en) ? 8'h0:
r_tlp_tag;
assign r_cfg_ready = (cfg_state != IDLE);
assign o_cfg_sm_state = cfg_state;
assign o_sm_state = state;
assign w_sts_ready = (state == IDLE);
assign w_sts_hst_buf_stall = (state == WAIT_FOR_HOST_EGRESS_BUFFER) ||
(state == WAIT_FOR_HOST_INGRESS_TAG) ||
(state == INGRESS_PREPARE) ||
(state == INGRESS_DATA_FLOW);
assign w_sts_flg_fifo_stall = (state == WAIT_FOR_FPGA_EGRESS_FIFO);
assign w_valid_bus_select = (i_cmd_flg_sel_periph || i_cmd_flg_sel_memory || i_cmd_flg_sel_dma);
assign w_cfg_req = (r_sts_unknown_cmd || r_sts_ping || r_sts_interrupt || r_sts_read_cfg);
//synchronous logic
always @ (posedge clk) begin
o_fc_cmt_stb <= 0;
o_ibm_req_stb <= 0;
r_delay_stb <= 0;
if (rst || i_cmd_rst_stb) begin
state <= IDLE;
r_buf_rdy <= 0;
r_tlp_command <= 0;
r_tlp_flags <= 0;
r_tlp_address <= 0;
r_tlp_requester_id <= 0;
r_tlp_tag <= 0;
r_index_valuea <= 0;
r_index_valueb <= 0;
r_buf_done <= 2'b00;
r_tmp_done <= 2'b00;
o_data_write_flg <= 0;
o_data_read_flg <= 0;
o_data_fifo_flg <= 0;
o_per_sel <= 0;
o_mem_sel <= 0;
o_dma_sel <= 0;
r_sts_reset <= 0;
r_sts_done <= 0;
r_sts_cmd_err <= 0;
r_data_count <= 0;
r_block_count <= 0;
o_data_size <= 0;
o_data_address <= 0;
r_buf_sel <= 0;
//r_buf_next_sel <= 0;
r_fifo_size <= 0;
o_dword_req_cnt <= 0;
o_ibm_en <= 0;
o_ibm_dat_fin <= 0;
r_send_cfg_en <= 0;
r_send_data_en <= 0;
if (i_cmd_rst_stb) begin
r_sts_reset <= 1;
end
r_sts_ping <= 0;
r_sts_read_cfg <= 0;
r_sts_interrupt <= 0;
r_sts_unknown_cmd <= 0;
o_buf_data_count <= 0;
end
else begin
if (i_cmd_unknown) begin
r_sts_unknown_cmd <= 1;
end
if (i_cmd_ping_stb) begin
r_sts_ping <= 1;
end
if (i_interrupt_stb) begin
r_sts_interrupt <= 1;
end
if (i_cmd_rd_cfg_stb) begin
r_sts_read_cfg <= 1;
end
case (state)
IDLE: begin
o_buf_data_count <= i_buf_max_size;
o_ibm_en <= 0;
o_data_write_flg <= 0;
o_data_read_flg <= 0;
o_data_fifo_flg <= 0;
o_per_sel <= 0;
o_mem_sel <= 0;
o_dma_sel <= 0;
r_sts_done <= 0;
r_sts_cmd_err <= 0;
r_tlp_tag <= 0;
r_buf_rdy <= 0;
r_buf_done <= 2'b00;
r_tmp_done <= 2'b00;
r_data_count <= 0;
r_data_pos <= 0;
r_block_count <= 0;
r_buf_sel <= 0;
//r_buf_next_sel <= 0;
r_send_cfg_en <= 0;
r_send_data_en <= 0;
r_index_valuea <= 0;
r_index_valueb <= 0;
//o_data_address <= i_cmd_data_address;
o_data_address <= i_dev_addr;
o_data_size <= i_cmd_data_count;
if (i_cmd_wr_stb) begin
if (w_valid_bus_select) begin
o_data_write_flg<= 1;
state <= INGRESS_PREPARE;
end
else begin
//XXX: SEND AN ERROR TELLING THE USER THEY NEED TO SELET A BUS
r_sts_cmd_err <= 1;
state <= SEND_CONFIG;
end
end
else if (i_cmd_rd_stb) begin
if (w_valid_bus_select) begin
o_data_read_flg <= 1;
state <= EGRESS_DATA_FLOW;
end
else begin
//XXX: SEND AN ERROR TELLING THE USER THEY NEED TO SELET A BUS
r_sts_cmd_err <= 1;
state <= SEND_CONFIG;
end
end
else if (w_cfg_req) begin
state <= SEND_CONFIG;
end
//Flags
if (i_cmd_flg_fifo) begin
o_data_fifo_flg <= 1;
end
if (i_cmd_flg_sel_periph) begin
o_per_sel <= 1;
end
if (i_cmd_flg_sel_memory) begin
o_mem_sel <= 1;
end
if (i_cmd_flg_sel_dma) begin
o_dma_sel <= 1;
end
end
//Egress Flow
EGRESS_DATA_FLOW: begin
r_tlp_command <= `PCIE_MWR_32B;
r_tlp_flags <= (`FLAG_NORMAL);
//if (r_data_count < o_data_size) begin
if (!i_read_fin) begin
//More data to send
state <= WAIT_FOR_HOST_EGRESS_BUFFER;
end
else begin
r_sts_done <= 1;
state <= IDLE;
end
end
WAIT_FOR_HOST_EGRESS_BUFFER: begin
if (!i_update_buf_stb) begin
r_block_count <= 0;
//Select a buffer
if (r_buf_rdy != 0) begin
if (r_buf_rdy == 2'b01) begin
//Select the first buffer
r_buf_sel <= 0;
r_buf_rdy[0] <= 0;
end
else if( r_buf_rdy == 2'b10) begin
//Select the second buffer
r_buf_sel <= 1;
r_buf_rdy[1] <= 0;
end
else begin //both enabled
//Select buffer 0
r_buf_sel <= 0;
r_buf_rdy <= 2'b10;
end
state <= WAIT_FOR_FPGA_EGRESS_FIFO;
end
end
end
WAIT_FOR_FPGA_EGRESS_FIFO: begin
//Send data to the host
//if ((r_data_count < o_data_size) && (r_block_count < i_buffer_size)) begin
if (!i_read_fin && (r_block_count < i_buffer_size)) begin
if (i_e_fifo_rdy) begin
r_fifo_size <= i_e_fifo_size;
r_tlp_address <= read_buf_map[r_buf_sel] + r_block_count;
state <= SEND_EGRESS_DATA;
end
end
else begin
r_buf_done[r_buf_sel] <= 1;
//if (r_data_count >= o_data_size) begin
if (i_read_fin) begin
r_sts_done <= 1;
end
state <= SEND_EGRESS_STATUS;
end
end
SEND_EGRESS_DATA: begin
//After a block of data is sent to the host send a configuration packet to update the buffer
//Go back ot the 'egress data flow to start on the next block or see if we are done
r_send_data_en <= 1;
if (i_egress_finished) begin
r_send_data_en <= 0;
//Add the amount we sent through the egress FIFO to our data count
r_block_count <= r_block_count + (r_fifo_size << 2);
r_data_count <= r_data_count + (r_fifo_size << 2);
state <= WAIT_FOR_FPGA_EGRESS_FIFO;
end
end
SEND_EGRESS_STATUS: begin
r_send_cfg_en <= 1;
if (r_send_cfg_fin) begin
r_send_cfg_en <= 0;
r_buf_done <= 0;
r_data_pos <= r_data_count;
state <= EGRESS_DATA_FLOW;
r_index_valuea <= r_index_valuea + 1;
end
end
//Ingress Flow
INGRESS_PREPARE: begin
if (w_ingress_count_left < i_buf_max_size) begin
o_buf_data_count <= w_ingress_count_left;
end
else begin
o_buf_data_count <= i_buf_max_size;
end
state <= INGRESS_DATA_FLOW;
end
INGRESS_DATA_FLOW: begin
o_ibm_en <= 1;
r_tlp_command <= `PCIE_MRD_32B;
r_tlp_flags <= `FLAG_NORMAL;
if (r_data_count < o_data_size) begin
//More data to send
state <= WAIT_FOR_HOST_INGRESS_TAG;
end
else begin
o_ibm_dat_fin <= 1;
//if (i_ibm_idle) begin
if (i_write_fin && i_ibm_idle) begin
o_ibm_dat_fin <= 0;
r_sts_done <= 1;
state <= SEND_CONFIG;
end
end
end
WAIT_FOR_HOST_INGRESS_TAG: begin
//This means both the host is ready and all the data in the incomming FIFO has been read out
//Buffer Controller Is good
//Host has populated a buffer
if (i_ibm_tag_rdy) begin
r_tlp_tag <= i_ibm_tag;
r_tlp_address <= write_buf_map[i_ibm_buf_sel] + i_ibm_start_addr[11:0];
o_dword_req_cnt <= i_ibm_dword_cnt;
o_ibm_req_stb <= 1;
state <= WAIT_FOR_FLOW_CONTROL;
end
else if ((r_tmp_done > 0) && !i_ibm_buf_fin_stb && !r_delay_stb) begin
r_buf_done <= r_tmp_done;
if (r_tmp_done[0]) begin
r_index_valuea <= r_index_valuea + 1;
end
if (r_tmp_done[1]) begin
r_index_valueb <= r_index_valueb + 1;
end
r_tmp_done <= 0;
if (w_ingress_count_left < i_buf_max_size) begin
o_buf_data_count <= w_ingress_count_left;
end
state <= SEND_INGRESS_STATUS;
end
end
WAIT_FOR_FLOW_CONTROL: begin
//Config State Machine Idle
if (i_fc_ready) begin
o_fc_cmt_stb <= 1;
state <= REQUEST_INGRESS_DATA;
end
end
REQUEST_INGRESS_DATA: begin
//At the end of a block send, send the updated buffer status to the host
// go back to the 'Ingress data flow' to figure out if we need to read mroe data
r_send_data_en <= 1;
if (i_egress_finished) begin
r_send_data_en <= 0;
r_data_count <= r_data_count + o_dword_req_cnt;
state <= INGRESS_DATA_FLOW;
end
end
SEND_INGRESS_STATUS: begin
r_send_cfg_en <= 1;
if (r_send_cfg_fin)begin
r_send_cfg_en <= 0;
r_buf_done <= 0;
state <= INGRESS_DATA_FLOW;
end
end
//At the end of a transaction send the final status
SEND_CONFIG: begin
r_send_cfg_en <= 1;
if (r_send_cfg_fin) begin
r_send_cfg_en <= 0;
r_sts_cmd_err <= 0;
r_sts_reset <= 0;
r_sts_ping <= 0;
r_sts_read_cfg <= 0;
r_sts_interrupt <= 0;
r_sts_unknown_cmd <= 0;
state <= IDLE;
end
end
default: begin
end
endcase
if (i_update_buf_stb) begin
r_buf_rdy <= r_buf_rdy | i_update_buf;
end
if (i_ibm_buf_fin_stb) begin
r_tmp_done <= r_tmp_done | i_ibm_buf_fin;
r_delay_stb <= 1;
end
end
end
//This state machine has one purpose, to write the configuration data and send an interrupt
always @ (posedge clk) begin
//Strobes
r_fifo_stb <= 0;
//o_interrupt_stb <= 0;
if (rst || i_cmd_rst_stb) begin
cfg_state <= IDLE;
r_fifo_act <= 0;
r_fifo_data <= 0;
o_ctr_sel <= 0;
r_fifo_count <= 0;
r_cfg_chan_en <= 0;
o_interrupt_msi_value <= `NYSA_INTERRUPT_CONFIG;
o_cfg_read_exec <= 0;
o_interrupt_send_en <= 0;
r_send_cfg_fin <= 0;
end
else begin
case (cfg_state)
IDLE: begin
r_send_cfg_fin <= 0;
r_fifo_count <= 0;
o_ctr_sel <= 0;
if (r_send_cfg_en) begin
cfg_state <= PREPARE;
end
end
PREPARE: begin
o_ctr_sel <= 1;
if ((w_fifo_rdy > 0) && (r_fifo_act == 0)) begin
r_fifo_count <= 0;
if (w_fifo_rdy[0]) begin
r_fifo_act[0] <= 1;
end
else begin
r_fifo_act[1] <= 1;
end
cfg_state <= LOAD_FIFO;
end
end
LOAD_FIFO: begin
if (r_fifo_count < `CONFIG_REGISTER_COUNT) begin
r_fifo_data <= register_map[r_fifo_count];
r_fifo_count <= r_fifo_count + 1;
r_fifo_stb <= 1;
end
else begin
cfg_state <= CFG_SEND_CONFIG;
r_fifo_act <= 0;
o_cfg_read_exec <= o_cfg_read_exec + 1;
end
end
CFG_SEND_CONFIG: begin
r_cfg_chan_en <= 1;
if (i_egress_finished) begin
r_cfg_chan_en <= 0;
cfg_state <= SEND_INT;
end
end
SEND_INT: begin
o_interrupt_send_en <= 1;
if (i_interrupt_send_rdy) begin
o_interrupt_send_en <= 0;
cfg_state <= FINISH;
end
//o_interrupt_stb <= 1;
end
FINISH: begin
r_send_cfg_fin <= 1;
if (!r_send_cfg_en) begin
r_send_cfg_fin <= 0;
cfg_state <= IDLE;
end
end
default: begin
end
endcase
end
end
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Mon Mar 24 13:58:19 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_3/part_1/ip/clk_193MHz/clk_193MHz_funcsim.v
// Design : clk_193MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_193MHz,clk_wiz_v5_1,{component_name=clk_193MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_193MHz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
wire clk_100MHz;
wire clk_193MHz;
wire locked;
clk_193MHzclk_193MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_193MHz(clk_193MHz),
.locked(locked));
endmodule
module clk_193MHzclk_193MHz_clk_wiz
(locked,
clk_193MHz,
clk_100MHz);
output locked;
output clk_193MHz;
input clk_100MHz;
wire \<const0> ;
wire \<const1> ;
wire clk_100MHz;
wire clk_100MHz_clk_193MHz;
wire clk_193MHz;
wire clk_193MHz_clk_193MHz;
wire clkfbout_buf_clk_193MHz;
wire clkfbout_clk_193MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_193MHz),
.O(clkfbout_buf_clk_193MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_193MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_193MHz_clk_193MHz),
.O(clk_193MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(45.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.750000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_193MHz),
.CLKFBOUT(clkfbout_clk_193MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_193MHz),
.CLKIN2(\<const0> ),
.CLKINSEL(\<const1> ),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_193MHz_clk_193MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DCLK(\<const0> ),
.DEN(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(\<const0> ),
.LOCKED(locked),
.PSCLK(\<const0> ),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(\<const0> ),
.PSINCDEC(\<const0> ),
.PWRDWN(\<const0> ),
.RST(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Jie Xu.
// SPDX-License-Identifier: CC0-1.0
//
// The test was added together with the concat optimization.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] in_c;
reg [31:0] in_d;
reg [31:0] in_e;
reg [15:0] in_f;
wire [31:0] in_g;
assign in_g = in_a << 4;
reg [31:0] out_x;
reg [31:0] out_y;
reg [31:0] out_z;
reg [31:0] out_o;
reg [31:0] out_p;
reg [31:0] out_q;
assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f};
assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]};
assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]};
assign out_o = out_z | out_y;
assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]};
assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
in_a <= cyc;
in_b <= cyc + 1;
in_c <= cyc + 3;
in_d <= cyc + 8;
in_e <= cyc;
in_f <= cyc[15:0];
if (out_x != (in_a & {2{in_f}}))
$stop;
if (out_y != (in_a&in_b))
$stop;
if (out_z != (in_e&in_d&in_c))
$stop;
if (out_o != (((in_a&in_b)|(in_c&in_e&in_d))))
$stop;
if (out_p != (in_a & {2{in_f}} | in_e))
$stop;
if (out_q != (in_a ^ in_g))
$stop;
if (cyc==100) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//
// Ticket Machine
// Jenner Hanni
//
// Implements a Moore finite state machine in Verilog
//
// This file handles encoding and behavior of a finite state machine to control
// a mass transit ticketing machine. A One Week Travel ticket costs $40. The
// machine accepts only $20 and $10 bills and will return all bills if more than
// $40 is placed in the machine. The machine does not make change.
//
// The four states:
// READY (LED on to indicate bills will be accepted)
// DISPENSE (dispenses a ticket once $40 received)
// RETURN (return all bills if more than $40 received)
// BILL (turns on LED to indicate an incomplete transaction)
//
// In the original project description, there is no RESET or CLEAR input.
//
module TicketMachine(Clock, Clear, Ten, Twenty, Ready, Dispense, Return, Bill);
input Clock, Clear, Ten, Twenty;
output Ready, Dispense, Return, Bill;
reg Ready, Dispense, Return, Bill;
parameter ON = 1'b1;
parameter OFF = 1'b0;
// define states using same names and state assignments as state diagram and table
// Using one-hot method, we have one bit per state
parameter // states
RDY = 6'b000001,
DISP = 6'b000010,
RTN = 6'b000100,
BILL10 = 6'b001000,
BILL20 = 6'b010000,
BILL30 = 6'b100000;
reg [5:0] State, NextState;
//
// Update state or reset on every + clock edge
// We have no clear
//
always @(posedge Clock)
begin
if (Clear)
State <= RDY;
else
State <= NextState;
end
//
// Outputs depend only upon state (Moore machine)
//
always @(State)
begin
case (State)
RDY: begin
Ready = ON;
Bill = OFF;
Dispense = OFF;
Return = OFF;
end
DISP: begin
Ready = OFF;
Bill = OFF;
Dispense = ON;
Return = OFF;
end
RTN: begin
Ready = OFF;
Bill = OFF;
Dispense = OFF;
Return = ON;
end
BILL10: begin
Ready = OFF;
Bill = ON;
Dispense = OFF;
Return = OFF;
end
BILL20: begin
Ready = OFF;
Bill = ON;
Dispense = OFF;
Return = OFF;
end
BILL30: begin
Ready = OFF;
Bill = ON;
Dispense = OFF;
Return = OFF;
end
endcase
end
//
// Next state generation logic
//
always @(State or Ten or Twenty)
begin
case (State)
RDY: begin
if (Ten)
NextState = BILL10;
else if (Twenty)
NextState = BILL20;
else
NextState = RDY;
end
BILL10: begin
if (Ten)
NextState = BILL20;
else if (Twenty)
NextState = BILL30;
else
NextState = BILL10;
end
BILL20: begin
if (Ten)
NextState = BILL30;
else if (Twenty)
NextState = DISP;
else
NextState = BILL20;
end
BILL30: begin
if (Ten)
NextState = DISP;
else if (Twenty)
NextState = RTN;
else
NextState = BILL30;
end
DISP: begin
NextState = RDY;
end
RTN: begin
NextState = RDY;
end
endcase
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../top/config.vh"
module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [13:0] tx_i_i;
input [13:0] tx_q_i;
output [13:0] tx_data_o;
output tx_sync_o;
`ifdef TX_RATE_MAX
wire clk128;
reg clk64_d;
reg [13:0] tx_data_o;
// Create a 128 MHz clock
dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
// Register the clk64 clock in the clk128 domain
always @(posedge clk128)
clk64_d <= clk_i;
// Register the tx data in the clk128 domain
always @(posedge clk128)
tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
assign tx_sync_o = clk64_d;
`else // !`ifdef TX_RATE_MAX
assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;
assign tx_sync_o = strobe_i;
`endif // !`ifdef TX_RATE_MAX
endmodule // dac_interface
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ted Campbell.
//With MULTI_CLK defined shows bug, without it is hidden
`define MULTI_CLK
//bug634
module t (
input i_clk_wr,
input i_clk_rd
);
wire wr$wen;
wire [7:0] wr$addr;
wire [7:0] wr$wdata;
wire [7:0] wr$rdata;
wire rd$wen;
wire [7:0] rd$addr;
wire [7:0] rd$wdata;
wire [7:0] rd$rdata;
wire clk_wr;
wire clk_rd;
`ifdef MULTI_CLK
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_rd;
`else
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_wr;
`endif
FooWr u_wr (
.i_clk ( clk_wr ),
.o_wen ( wr$wen ),
.o_addr ( wr$addr ),
.o_wdata ( wr$wdata ),
.i_rdata ( wr$rdata )
);
FooRd u_rd (
.i_clk ( clk_rd ),
.o_wen ( rd$wen ),
.o_addr ( rd$addr ),
.o_wdata ( rd$wdata ),
.i_rdata ( rd$rdata )
);
FooMem u_mem (
.iv_clk ( {clk_wr, clk_rd } ),
.iv_wen ( {wr$wen, rd$wen } ),
.iv_addr ( {wr$addr, rd$addr } ),
.iv_wdata ( {wr$wdata,rd$wdata} ),
.ov_rdata ( {wr$rdata,rd$rdata} )
);
endmodule
// Memory Writer
module FooWr(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd50 )
cnt <= cnt + 8'd1;
// Write addr in (10,30) if even
assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
assign o_addr = cnt;
assign o_wdata = cnt;
endmodule
// Memory Reader
module FooRd(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
reg [7:0] addr_r;
reg en_r;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd200 )
cnt <= cnt + 8'd1;
// Read data
assign o_wen = 0;
assign o_addr = cnt - 8'd100;
// Track issued read
always @( posedge i_clk )
begin
addr_r <= o_addr;
en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
end
// Display to console 100 cycles after writer
always @( negedge i_clk )
if ( en_r ) begin
`ifdef TEST_VERBOSE
$display( "MEM[%x] == %x", addr_r, i_rdata );
`endif
if (addr_r != i_rdata) $stop;
end
endmodule
// Multi-port memory abstraction
module FooMem(
input [2 -1:0] iv_clk,
input [2 -1:0] iv_wen,
input [2*8-1:0] iv_addr,
input [2*8-1:0] iv_wdata,
output [2*8-1:0] ov_rdata
);
FooMemImpl u_impl (
.a_clk ( iv_clk [0*1+:1] ),
.a_wen ( iv_wen [0*1+:1] ),
.a_addr ( iv_addr [0*8+:8] ),
.a_wdata ( iv_wdata[0*8+:8] ),
.a_rdata ( ov_rdata[0*8+:8] ),
.b_clk ( iv_clk [1*1+:1] ),
.b_wen ( iv_wen [1*1+:1] ),
.b_addr ( iv_addr [1*8+:8] ),
.b_wdata ( iv_wdata[1*8+:8] ),
.b_rdata ( ov_rdata[1*8+:8] )
);
endmodule
// Dual-Port L1 Memory Implementation
module FooMemImpl(
input a_clk,
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
reg [7:0] mem[0:255];
/* verilator lint_on MULTIDRIVEN */
always @( posedge a_clk )
if ( a_wen )
mem[a_addr] <= a_wdata;
always @( posedge b_clk )
if ( b_wen )
mem[b_addr] <= b_wdata;
always @( posedge a_clk )
a_rdata <= mem[a_addr];
always @( posedge b_clk )
b_rdata <= mem[b_addr];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_V |
module brainfuck_top
(
input clk, rst_n,
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [7:0] key_in,
input key_d_en,
output txd,
input rxd,
output of_err
);
wire [31:0] op;
reg op_en;
wire [11:0] dp;
wire [15:0] d_o;
wire w_en, w_sel, w_wait;
wire [15:0] d_i;
wire r_en, d_en, r_sel;
wire ram_w_en, ram_r_en;
reg ram_d_en;
wire [15:0] ram_d_i;
wire s_rst;
wire rst;
reg lcd_wen;
reg [8:0] lcd_wdt;
wire lcd_status;
wire [11:0] pc;
wire pc_r;
assign rst = !rst_n;
brainfuck bf( .clk(clk), .rst(rst), .s_rst(s_rst),
.pc(pc), .op_r_req(pc_r), .op(op), .op_den(op_en),
.dp_adr(dp), .data_out(d_o), .data_w_req(w_en), .data_w_sel(w_sel), .data_w_wait(w_wait),
.data_in(d_i), .data_r_req(r_en), .data_r_sel(r_sel), .data_den(d_en)
);
LCDCONTROL lcd(.CLK(clk), .RST(rst), .WRITE(lcd_wen), .WRDATA(lcd_wdt), .STATUS(lcd_status),
.LCD_BLON(LCD_BLON), .LCD_RW(LCD_RW), .LCD_EN(LCD_EN), .LCD_RS(LCD_RS), .LCD_DATA(LCD_DATA)
);
wire [8:0] cmd_in;
reg [8:0] cmd [31:0];
reg [5:0] cmd_len;
wire cmd_st, cmd_busy, cmd_en;
integer ci;
wire [7:0] udout;
wire udout_en;
uart uart_1( .clk(clk), .rst(rst), .txd(txd), .rxd(rxd), .din(cmd_in), .din_en(cmd_en),
.dout(udout), .dout_en(udout_en), .of_err(of_err)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
cmd[0] <= 9'h38;
cmd[1] <= 9'h0c;
cmd[2] <= 9'h01;
cmd[3] <= 9'h06;
cmd[4] <= 9'h80;
for(ci=5; ci<32; ci=ci+1) begin
cmd[ci] <= 0;
end
cmd_len <= 6'd5;
end // if (rst)
else begin
if (cmd_st) begin
for(ci=0; ci<31; ci=ci+1) begin
cmd[ci] <= cmd[ci+1];
end
if (cmd_en) begin
cmd[cmd_len-6'h1] <= cmd_in;
end
else begin
cmd_len <= cmd_len - 6'h1;
end
end
else if (cmd_len < 6'd32 & cmd_en==1) begin
cmd[cmd_len] <= cmd_in;
cmd_len <= cmd_len + 6'h1;
end
end // else: !if(rst)
end // always @ (posedge clk or posedge rst)
assign cmd_st = (cmd_len>0 & cmd_busy==0);
assign cmd_busy = lcd_status | lcd_wen;
assign cmd_in = {1'b1, d_o[7:0]};
assign cmd_en = (w_en & w_sel) ? 1'b1 : 1'b0;
assign w_wait = (w_sel & cmd_len >= 6'h32) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst) begin
lcd_wen <= 0;
lcd_wdt <= 0;
end
else begin
if (cmd_st) begin
lcd_wen <= 1;
lcd_wdt <= cmd[0];
end
else begin
lcd_wen <= 0;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
// program memory
drom32 drom_inst ( .address ( pc ), .clock ( clk ), .q ( op ) );
// data memory
dmem16 dmem_inst (.address ( dp ), .clock ( clk ), .data ( d_o ), .wren ( ram_w_en ), .q ( ram_d_i ));
assign ram_w_en = (w_sel==0) ? w_en : 1'b0;
assign ram_r_en = (r_sel==0) ? r_en : 1'b0;
assign d_en = (r_sel==0) ? ram_d_en : key_d_en;
assign d_i = (r_sel==0) ? ram_d_i : {8'h0, key_in};
assign s_rst = 0;
always @(posedge clk or posedge rst) begin
if (rst)
op_en <= 0;
else
op_en <= pc_r;
end
always @(posedge clk or posedge rst) begin
if (rst)
ram_d_en <= 0;
else
ram_d_en <= ram_r_en;
end
endmodule // brainfuck_top
|
// Test the various string.Xtoa() methods
module testbench;
string str;
int val;
real valr;
task test_string_value(string str, string reference);
if (str != reference) begin
$display("FAILED -- str=%0s, should be %s", str, reference);
$finish;
end
endtask // test_string_value
initial begin
val = 11;
valr = 11.1;
str.itoa(val);
test_string_value(str, "11");
str.hextoa(val);
test_string_value(str, "b");
str.octtoa(val);
test_string_value(str, "13");
str.bintoa(val);
test_string_value(str, "1011");
str.realtoa(valr);
test_string_value(str, "11.1");
val = -11;
valr = -11.1;
str.itoa(val);
test_string_value(str, "-11");
str.hextoa(val);
test_string_value(str, "-b");
str.octtoa(val);
test_string_value(str, "-13");
str.bintoa(val);
test_string_value(str, "-1011");
str.realtoa(valr);
test_string_value(str, "-11.1");
$display("PASSED");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {48'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module callee (input [7:0] port [7:0], output [7:0] o);
assign o = ^{port[0], port[1], port[2], port[3],
port[4], port[5], port[6], port[7]};
endmodule // callee
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output reg [15:0] out;
wire [7:0] port [15:0];
wire [7:0] goodport [7:0];
always_comb begin
port[0][7:0] = in[7:0];
port[1][7:0] = in[16:8];
port[2] = '0;
port[3] = '0;
port[4] = '0;
port[5] = '0;
port[6] = '0;
port[7] = '0;
end
always_comb begin
goodport[0][7:0] = in[7:0];
goodport[1][7:0] = in[16:8];
goodport[2] = '0;
goodport[3] = '0;
goodport[4] = '0;
goodport[5] = '0;
goodport[6] = '0;
goodport[7] = '0;
end
callee good (.port(goodport), .o(out[7:0]));
// This is a slice, unsupported by other tools, bug711
callee bad (.port(port[7:0]), .o(out[15:8]));
endmodule
|
//Logarithm function evaluation
module log(u0, e, clk);
input [47:0]u0;
input clk;
output [30:0]e;
reg [30:0]e;
reg [7:0]exp_e;
reg [47:0]x_e;
reg [113:0]y_e1, y_e_2, y_e_3, y_e;
reg [65:0]y_e2;
reg [15:0]ln2;
reg [18:0]e_e;
reg [33:0]e_e_, y_e_;
reg [34:0]e0;
reg [16:0]c_e_1;
reg [16:0]c_e_2, c_e_3;
reg [48:0]x_e_;
integer i;
always@(posedge clk)
begin
i = 47; //Leading zero calculation for u0
while(i>=0)
begin
if(u0[i] == 1'b1)
begin
exp_e = 48 - i; //exp_e has the LZD value
i = 0;
end
i = i-1;
end
x_e = x_e&(48'h000000000000);
x_e = u0 << exp_e; //Left shift of u0 based on exp_e
y_e = 0;
//Logarithm function Approximation
c_e_1 = 17'b00011011000001110;
c_e_2 = 17'b10101000111110001;
c_e_3 = 17'b10001101010001101;
x_e_[47:0] = x_e[47:0];
x_e_[48] = 1;
y_e1 = c_e_1*x_e_*x_e_ ;
y_e2 = c_e_2*x_e_ ;
y_e_3[113] = 0;
y_e_2[113:48] = y_e2[65:0];
y_e_2[47:0] = 0;
y_e_3[112:96] = c_e_3[16:0];
y_e_3[95:0] = 0;
y_e = -y_e1 + y_e_2 - y_e_3; // Evalulating the polynomial
ln2 = 16'b1011000101110010;
e_e = exp_e*ln2;
y_e_[33:31] = 0;
y_e_[30:0] = y_e[111:81];
e_e_[33:15] = e_e[18:0];
e_e_[14:0] = 0;
e0 = e_e_ + y_e_;
e[27:0] = e0[34:7];
e[30:28] = 0;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_axi_basic_rx_null_gen.v
// Version : 3.0
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digest: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1
2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2
2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2
2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3
endcase
end
assign new_pkt_len =
{{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len};
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
//assign new_pkt_len =
// {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`include "verilated.v"
module t_case_write1_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
inout [STRLEN*8:1] foobar;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : foobar = {foobar, " 0"};
7'h01 : foobar = {foobar, " 1"};
7'h02 : foobar = {foobar, " 2"};
7'h03 : foobar = {foobar, " 3"};
7'h04 : foobar = {foobar, " 4"};
7'h05 : foobar = {foobar, " 5"};
7'h06 : foobar = {foobar, " 6"};
7'h07 : foobar = {foobar, " 7"};
7'h08 : foobar = {foobar, " 8"};
7'h09 : foobar = {foobar, " 9"};
7'h0a : foobar = {foobar, " 10"};
7'h0b : foobar = {foobar, " 11"};
7'h0c : foobar = {foobar, " 12"};
7'h0d : foobar = {foobar, " 13"};
7'h0e : foobar = {foobar, " 14"};
7'h0f : foobar = {foobar, " 15"};
7'h10 : foobar = {foobar, " 16"};
7'h11 : foobar = {foobar, " 17"};
7'h12 : foobar = {foobar, " 18"};
7'h13 : foobar = {foobar, " 19"};
7'h14 : foobar = {foobar, " 20"};
7'h15 : foobar = {foobar, " 21"};
7'h16 : foobar = {foobar, " 22"};
7'h17 : foobar = {foobar, " 23"};
7'h18 : foobar = {foobar, " 24"};
7'h19 : foobar = {foobar, " 25"};
7'h1a : foobar = {foobar, " 26"};
7'h1b : foobar = {foobar, " 27"};
7'h1c : foobar = {foobar, " 28"};
7'h1d : foobar = {foobar, " 29"};
7'h1e : foobar = {foobar, " 30"};
7'h1f : foobar = {foobar, " 31"};
7'h20 : foobar = {foobar, " 32"};
7'h21 : foobar = {foobar, " 33"};
7'h22 : foobar = {foobar, " 34"};
7'h23 : foobar = {foobar, " 35"};
7'h24 : foobar = {foobar, " 36"};
7'h25 : foobar = {foobar, " 37"};
7'h26 : foobar = {foobar, " 38"};
7'h27 : foobar = {foobar, " 39"};
7'h28 : foobar = {foobar, " 40"};
7'h29 : foobar = {foobar, " 41"};
7'h2a : foobar = {foobar, " 42"};
7'h2b : foobar = {foobar, " 43"};
7'h2c : foobar = {foobar, " 44"};
7'h2d : foobar = {foobar, " 45"};
7'h2e : foobar = {foobar, " 46"};
7'h2f : foobar = {foobar, " 47"};
7'h30 : foobar = {foobar, " 48"};
7'h31 : foobar = {foobar, " 49"};
7'h32 : foobar = {foobar, " 50"};
7'h33 : foobar = {foobar, " 51"};
7'h34 : foobar = {foobar, " 52"};
7'h35 : foobar = {foobar, " 53"};
7'h36 : foobar = {foobar, " 54"};
7'h37 : foobar = {foobar, " 55"};
7'h38 : foobar = {foobar, " 56"};
7'h39 : foobar = {foobar, " 57"};
7'h3a : foobar = {foobar, " 58"};
7'h3b : foobar = {foobar, " 59"};
7'h3c : foobar = {foobar, " 60"};
7'h3d : foobar = {foobar, " 61"};
7'h3e : foobar = {foobar, " 62"};
7'h3f : foobar = {foobar, " 63"};
7'h40 : foobar = {foobar, " 64"};
7'h41 : foobar = {foobar, " 65"};
7'h42 : foobar = {foobar, " 66"};
7'h43 : foobar = {foobar, " 67"};
7'h44 : foobar = {foobar, " 68"};
7'h45 : foobar = {foobar, " 69"};
7'h46 : foobar = {foobar, " 70"};
7'h47 : foobar = {foobar, " 71"};
7'h48 : foobar = {foobar, " 72"};
7'h49 : foobar = {foobar, " 73"};
7'h4a : foobar = {foobar, " 74"};
7'h4b : foobar = {foobar, " 75"};
7'h4c : foobar = {foobar, " 76"};
7'h4d : foobar = {foobar, " 77"};
7'h4e : foobar = {foobar, " 78"};
7'h4f : foobar = {foobar, " 79"};
7'h50 : foobar = {foobar, " 80"};
7'h51 : foobar = {foobar, " 81"};
7'h52 : foobar = {foobar, " 82"};
7'h53 : foobar = {foobar, " 83"};
7'h54 : foobar = {foobar, " 84"};
7'h55 : foobar = {foobar, " 85"};
7'h56 : foobar = {foobar, " 86"};
7'h57 : foobar = {foobar, " 87"};
7'h58 : foobar = {foobar, " 88"};
7'h59 : foobar = {foobar, " 89"};
7'h5a : foobar = {foobar, " 90"};
7'h5b : foobar = {foobar, " 91"};
7'h5c : foobar = {foobar, " 92"};
7'h5d : foobar = {foobar, " 93"};
7'h5e : foobar = {foobar, " 94"};
7'h5f : foobar = {foobar, " 95"};
7'h60 : foobar = {foobar, " 96"};
7'h61 : foobar = {foobar, " 97"};
7'h62 : foobar = {foobar, " 98"};
7'h63 : foobar = {foobar, " 99"};
7'h64 : foobar = {foobar, " 100"};
7'h65 : foobar = {foobar, " 101"};
7'h66 : foobar = {foobar, " 102"};
7'h67 : foobar = {foobar, " 103"};
7'h68 : foobar = {foobar, " 104"};
7'h69 : foobar = {foobar, " 105"};
7'h6a : foobar = {foobar, " 106"};
7'h6b : foobar = {foobar, " 107"};
7'h6c : foobar = {foobar, " 108"};
7'h6d : foobar = {foobar, " 109"};
7'h6e : foobar = {foobar, " 110"};
7'h6f : foobar = {foobar, " 111"};
7'h70 : foobar = {foobar, " 112"};
7'h71 : foobar = {foobar, " 113"};
7'h72 : foobar = {foobar, " 114"};
7'h73 : foobar = {foobar, " 115"};
7'h74 : foobar = {foobar, " 116"};
7'h75 : foobar = {foobar, " 117"};
7'h76 : foobar = {foobar, " 118"};
7'h77 : foobar = {foobar, " 119"};
7'h78 : foobar = {foobar, " 120"};
7'h79 : foobar = {foobar, " 121"};
7'h7a : foobar = {foobar, " 122"};
7'h7b : foobar = {foobar, " 123"};
7'h7c : foobar = {foobar, " 124"};
7'h7d : foobar = {foobar, " 125"};
7'h7e : foobar = {foobar, " 126"};
7'h7f : foobar = {foobar, " 127"};
default:foobar = {foobar, " 128"};
endcase
end
endtask
task ozonerb;
input [5:0] rb;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: foobar = {foobar, " 129"};
default: ozonerab({1'b1, rb}, foobar);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 130"};
end
2'h1 :
begin
foobar = {foobar, " 131"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
2'h2 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 132"};
end
2'h3 :
begin
foobar = {foobar, " 133"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (hex)
4'h0 : foobar = {foobar, " 134"};
4'h1 : foobar = {foobar, " 135"};
4'h2 : foobar = {foobar, " 136"};
4'h3 : foobar = {foobar, " 137"};
4'h4 : foobar = {foobar, " 138"};
4'h5 : foobar = {foobar, " 139"};
4'h6 : foobar = {foobar, " 140"};
4'h7 : foobar = {foobar, " 141"};
4'h8 : foobar = {foobar, " 142"};
4'h9 : foobar = {foobar, " 143"};
4'ha : foobar = {foobar, " 144"};
4'hb : foobar = {foobar, " 145"};
4'hc : foobar = {foobar, " 146"};
4'hd : foobar = {foobar, " 147"};
4'he : foobar = {foobar, " 148"};
4'hf : foobar = {foobar, " 149"};
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : foobar = {foobar, " 158"};
3'h1 : foobar = {foobar, " 159"};
3'h2 : foobar = {foobar, " 160"};
3'h3 : foobar = {foobar, " 161"};
3'h4 : foobar = {foobar, " 162"};
3'h5 : foobar = {foobar, " 163"};
3'h6 : foobar = {foobar, " 164"};
3'h7 : foobar = {foobar, " 165"};
endcase
end
endtask
task ozonejk;
input k;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (k)
foobar = {foobar, " 166"};
else
foobar = {foobar, " 167"};
end
endtask
task ozoneae;
input [ 2:0] ae;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ae)
3'b000 : foobar = {foobar, " 168"};
3'b001 : foobar = {foobar, " 169"};
3'b010 : foobar = {foobar, " 170"};
3'b011 : foobar = {foobar, " 171"};
3'b100 : foobar = {foobar, " 172"};
3'b101 : foobar = {foobar, " 173"};
3'b110 : foobar = {foobar, " 174"};
3'b111 : foobar = {foobar, " 175"};
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 176"};
3'b000 : foobar = {foobar, " 177"};
3'b010 : foobar = {foobar, " 178"};
3'b100 : foobar = {foobar, " 179"};
3'b110 : foobar = {foobar, " 180"};
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 181"};
3'b000 : foobar = {foobar, " 182"};
3'b010 : foobar = {foobar, " 183"};
3'b100 : foobar = {foobar, " 184"};
3'b110 : foobar = {foobar, " 185"};
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
foobar = {foobar, " 186"};
else
foobar = {foobar, " 187"};
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 188"};
2'b01 : foobar = {foobar, " 189"};
2'b10 : foobar = {foobar, " 190"};
2'b11 : foobar = {foobar, " 191"};
endcase
4'h2 : foobar = {foobar, " 192"};
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 193"};
2'b01 : foobar = {foobar, " 194"};
2'b10 : foobar = {foobar, " 195"};
2'b11 : foobar = {foobar, " 196"};
endcase
4'h4 :
if (foo[26])
foobar = {foobar, " 197"};
else
foobar = {foobar, " 198"};
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 199"};
2'b01 : foobar = {foobar, " 200"};
2'b10 : foobar = {foobar, " 201"};
2'b11 : foobar = {foobar, " 202"};
endcase
4'h6 : foobar = {foobar, " 203"};
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 204"};
2'b01 : foobar = {foobar, " 205"};
2'b10 : foobar = {foobar, " 206"};
2'b11 : foobar = {foobar, " 207"};
endcase
4'h8 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 208"};
2'b01 : foobar = {foobar, " 209"};
2'b10 : foobar = {foobar, " 210"};
2'b11 : foobar = {foobar, " 211"};
endcase
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 212"};
2'b01 : foobar = {foobar, " 213"};
2'b10 : foobar = {foobar, " 214"};
2'b11 : foobar = {foobar, " 215"};
endcase
4'ha :
if (foo[25])
foobar = {foobar, " 216"};
else
foobar = {foobar, " 217"};
4'hb :
if (foo[25])
foobar = {foobar, " 218"};
else
foobar = {foobar, " 219"};
4'hc :
if (foo[26])
foobar = {foobar, " 220"};
else
foobar = {foobar, " 221"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar, " 222"};
2'b01 : foobar = {foobar, " 223"};
2'b10 : foobar = {foobar, " 224"};
2'b11 : foobar = {foobar, " 225"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar, " 226"};
2'b01 : foobar = {foobar, " 227"};
2'b10 : foobar = {foobar, " 228"};
2'b11 : foobar = {foobar, " 229"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 230"};
2'b01 : foobar = {foobar, " 231"};
2'b10 : foobar = {foobar, " 232"};
2'b11 : foobar = {foobar, " 233"};
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 234"};
foobar = {foobar, " 235"};
end
7'h01:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 236"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 237"};
foobar = {foobar, " 238"};
end
7'h02:
foobar = {foobar, " 239"};
7'h03:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 240"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 241"};
foobar = {foobar, " 242"};
end
7'h04:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 243"};
foobar = {foobar," 244"};
end
7'h05:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 245"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 246"};
end
7'h06:
foobar = {foobar, " 247"};
7'h07:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 248"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 249"};
end
7'h08:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 250"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 251"};
end
7'h09:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 252"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 253"};
end
7'h0a:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 254"};
end
7'h0b:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 255"};
end
7'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 256"};
end
7'h0d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 257"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 258"};
end
7'h0e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 259"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 260"};
end
7'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 261"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 262"};
end
7'h10:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 263"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 264"};
foobar = {foobar, " 265"};
foobar = {foobar, " 266"};
end
7'h11:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 267"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 268"};
foobar = {foobar, " 269"};
foobar = {foobar, " 270"};
end
7'h12:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 271"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 272"};
foobar = {foobar, " 273"};
foobar = {foobar, " 274"};
end
7'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 275"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 276"};
foobar = {foobar, " 277"};
foobar = {foobar, " 278"};
end
7'h14:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 279"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 280"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 281"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 282"};
foobar = {foobar, " 283"};
foobar = {foobar, " 284"};
end
7'h15:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 285"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 286"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 287"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 288"};
foobar = {foobar, " 289"};
foobar = {foobar, " 290"};
end
7'h16:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 291"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 292"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 293"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 294"};
foobar = {foobar, " 295"};
foobar = {foobar, " 296"};
end
7'h17:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 297"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 298"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 299"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 300"};
foobar = {foobar, " 301"};
foobar = {foobar, " 302"};
end
7'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 303"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 304"};
foobar = {foobar, " 305"};
foobar = {foobar, " 306"};
end
7'h19:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 307"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 308"};
foobar = {foobar, " 309"};
foobar = {foobar, " 310"};
end
7'h1a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 311"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 312"};
foobar = {foobar, " 313"};
foobar = {foobar, " 314"};
end
7'h1b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 315"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 316"};
foobar = {foobar, " 317"};
foobar = {foobar, " 318"};
end
7'h1c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 319"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 320"};
foobar = {foobar, " 321"};
foobar = {foobar, " 322"};
end
7'h1d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 323"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 324"};
foobar = {foobar, " 325"};
foobar = {foobar, " 326"};
end
7'h1e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 327"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 328"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 329"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 330"};
foobar = {foobar, " 331"};
foobar = {foobar, " 332"};
end
7'h1f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 333"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 334"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 335"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 336"};
foobar = {foobar, " 337"};
foobar = {foobar, " 338"};
end
7'h20:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 339"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 340"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 341"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 342"};
foobar = {foobar, " 343"};
foobar = {foobar, " 344"};
end
7'h21:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 345"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 346"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 347"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 348"};
foobar = {foobar, " 349"};
foobar = {foobar, " 350"};
end
7'h22:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 351"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 352"};
foobar = {foobar, " 353"};
foobar = {foobar, " 354"};
end
7'h23:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 355"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 356"};
foobar = {foobar, " 357"};
foobar = {foobar, " 358"};
end
7'h24:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 359"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 360"};
foobar = {foobar, " 361"};
foobar = {foobar, " 362"};
end
7'h25:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 363"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 364"};
foobar = {foobar, " 365"};
foobar = {foobar, " 366"};
end
7'h26:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 367"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 368"};
foobar = {foobar, " 369"};
foobar = {foobar, " 370"};
end
7'h27:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 371"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 372"};
foobar = {foobar, " 373"};
foobar = {foobar, " 374"};
end
7'h28:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 375"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 376"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 377"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 378"};
foobar = {foobar, " 379"};
foobar = {foobar, " 380"};
end
7'h29:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 381"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 382"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 383"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 384"};
foobar = {foobar, " 385"};
foobar = {foobar, " 386"};
end
7'h2a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 387"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 388"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 389"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 390"};
foobar = {foobar, " 391"};
foobar = {foobar, " 392"};
end
7'h2b:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 393"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 394"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 395"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 396"};
foobar = {foobar, " 397"};
foobar = {foobar, " 398"};
end
7'h2c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 399"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 400"};
foobar = {foobar, " 401"};
foobar = {foobar, " 402"};
end
7'h2d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 403"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 404"};
foobar = {foobar, " 405"};
foobar = {foobar, " 406"};
end
7'h2e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 407"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 408"};
foobar = {foobar, " 409"};
foobar = {foobar, " 410"};
end
7'h2f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 411"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 412"};
foobar = {foobar, " 413"};
foobar = {foobar, " 414"};
end
7'h30:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 415"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 416"};
foobar = {foobar, " 417"};
foobar = {foobar, " 418"};
end
7'h31:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 419"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 420"};
foobar = {foobar, " 421"};
foobar = {foobar, " 422"};
end
7'h32:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 423"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 424"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 425"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 426"};
foobar = {foobar, " 427"};
foobar = {foobar, " 428"};
end
7'h33:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 429"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 430"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 431"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 432"};
foobar = {foobar, " 433"};
foobar = {foobar, " 434"};
end
7'h34:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 435"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 436"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 437"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 438"};
foobar = {foobar, " 439"};
foobar = {foobar, " 440"};
end
7'h35:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 441"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 442"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 443"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 444"};
foobar = {foobar, " 445"};
foobar = {foobar, " 446"};
end
7'h36:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 447"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 448"};
foobar = {foobar, " 449"};
foobar = {foobar, " 450"};
end
7'h37:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 451"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 452"};
foobar = {foobar, " 453"};
foobar = {foobar, " 454"};
end
7'h38:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 455"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 456"};
foobar = {foobar, " 457"};
end
7'h39:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 458"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 459"};
foobar = {foobar, " 460"};
end
7'h3a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 461"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 462"};
foobar = {foobar, " 463"};
end
7'h3b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 464"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 465"};
foobar = {foobar, " 466"};
end
7'h3c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 467"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 468"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 469"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 470"};
foobar = {foobar, " 471"};
end
7'h3d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 472"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 473"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 474"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 475"};
foobar = {foobar, " 476"};
end
7'h3e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 477"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 478"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 479"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 480"};
foobar = {foobar, " 481"};
end
7'h3f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 482"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 483"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 484"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 485"};
foobar = {foobar, " 486"};
end
7'h40:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 487"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 488"};
foobar = {foobar, " 489"};
foobar = {foobar, " 490"};
end
7'h41:
begin
foobar = {foobar, " 491"};
foobar = {foobar, " 492"};
end
7'h42:
begin
foobar = {foobar, " 493"};
foobar = {foobar, " 494"};
end
7'h43:
begin
foobar = {foobar, " 495"};
foobar = {foobar, " 496"};
end
7'h44:
begin
foobar = {foobar, " 497"};
foobar = {foobar, " 498"};
end
7'h45:
foobar = {foobar, " 499"};
7'h46:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 500"};
foobar = {foobar, " 501"};
foobar = {foobar, " 502"};
end
7'h47:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 503"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 504"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 505"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 506"};
foobar = {foobar, " 507"};
foobar = {foobar, " 508"};
end
7'h48:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 509"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 510"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 511"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 512"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 513"};
end
7'h49:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 514"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 515"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 516"};
end
7'h4a:
foobar = {foobar," 517"};
7'h4b:
foobar = {foobar, " 518"};
7'h4c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 519"};
foobar = {foobar, " 520"};
foobar = {foobar, " 521"};
end
7'h4d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 522"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 523"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 524"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 525"};
foobar = {foobar, " 526"};
foobar = {foobar, " 527"};
end
7'h4e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 528"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 529"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 530"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 531"};
end
7'h4f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 532"};
end
7'h50:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 533"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 534"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 535"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 536"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 537"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 538"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 539"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 540"};
end
7'h51:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 541"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 542"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 543"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 544"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 545"};
end
7'h52:
foobar = {foobar, " 546"};
7'h53:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 547"};
end
7'h54:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 548"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 549"};
end
7'h55:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 550"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 551"};
end
7'h56:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 552"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 553"};
foobar = {foobar, " 554"};
end
7'h57:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 555"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 556"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 557"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 558"};
end
7'h58:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 559"};
end
7'h59:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 560"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 561"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 562"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 563"};
end
7'h5a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 564"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 565"};
end
7'h5b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 566"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 567"};
end
7'h5c:
begin
foobar = {foobar," 568"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 569"};
foobar = {foobar," 570"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 571"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 572"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 573"};
end
7'h5d:
begin
foobar = {foobar," 574"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 575"};
foobar = {foobar," 576"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 577"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 578"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 579"};
end
7'h5e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 580"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 581"};
end
7'h5f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 582"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 583"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 584"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 585"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 586"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 587"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 588"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 589"};
end
7'h60:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 590"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 591"};
end
7'h61:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 592"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 593"};
end
7'h62:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 594"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 595"};
end
7'h63:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 596"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 597"};
end
7'h64:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 598"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 599"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 600"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 601"};
end
7'h65:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 602"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 603"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 604"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 605"};
end
7'h66:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 606"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 607"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 608"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 609"};
end
7'h67:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 610"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 611"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 612"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 613"};
end
7'h68:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 614"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 615"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 616"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 617"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 618"};
ozoneape(foo[17:15], foobar);
end
7'h69:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 619"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 620"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 621"};
end
7'h6a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 622"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 623"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 624"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 625"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 626"};
ozoneae(foo[17:15], foobar);
end
7'h6b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 627"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 628"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 629"};
end
7'h6c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 630"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 631"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 632"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 633"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 634"};
ozoneae(foo[17:15], foobar);
end
7'h6d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 635"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 636"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 637"};
end
7'h6e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 638"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 639"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 640"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 641"};
end
7'h6f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 642"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 643"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 644"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 645"};
end
7'h70:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 646"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 647"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 648"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 649"};
end
7'h71:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 650"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 651"};
end
7'h72:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 652"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 653"};
end
7'h73:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 654"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 655"};
ozoneae(foo[17:15], foobar);
end
7'h74:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 656"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 657"};
ozoneae(foo[17:15], foobar);
end
7'h75:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 658"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 659"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 660"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 661"};
foobar = {foobar, " 662"};
foobar = {foobar, " 663"};
end
7'h76:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 664"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 665"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 666"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 667"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 668"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 669"};
end
7'h77:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 670"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 671"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 672"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 673"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 674"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 675"};
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
foobar = {foobar," 676"};
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : foobar = {foobar," 677"};
2'b01 : foobar = {foobar," 678"};
2'b10 : foobar = {foobar," 679"};
2'b11 : foobar = {foobar," 680"};
endcase
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar," 681"};
2'b01 : foobar = {foobar," 682"};
2'b10 : foobar = {foobar," 683"};
2'b11 : foobar = {foobar," 684"};
endcase
4'h2 :
case (foo[26:25])
2'b00 : foobar = {foobar," 685"};
2'b01 : foobar = {foobar," 686"};
2'b10 : foobar = {foobar," 687"};
2'b11 : foobar = {foobar," 688"};
endcase
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar," 689"};
2'b01 : foobar = {foobar," 690"};
2'b10 : foobar = {foobar," 691"};
2'b11 : foobar = {foobar," 692"};
endcase
4'h4 :
case (foo[26:25])
2'b00 : foobar = {foobar," 693"};
2'b01 : foobar = {foobar," 694"};
2'b10 : foobar = {foobar," 695"};
2'b11 : foobar = {foobar," 696"};
endcase
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar," 697"};
2'b01 : foobar = {foobar," 698"};
2'b10 : foobar = {foobar," 699"};
2'b11 : foobar = {foobar," 700"};
endcase
4'h6 :
case (foo[26:25])
2'b00 : foobar = {foobar," 701"};
2'b01 : foobar = {foobar," 702"};
2'b10 : foobar = {foobar," 703"};
2'b11 : foobar = {foobar," 704"};
endcase
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar," 705"};
2'b01 : foobar = {foobar," 706"};
2'b10 : foobar = {foobar," 707"};
2'b11 : foobar = {foobar," 708"};
endcase
4'h8 :
if (foo[26])
foobar = {foobar," 709"};
else
foobar = {foobar," 710"};
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar," 711"};
2'b01 : foobar = {foobar," 712"};
2'b10 : foobar = {foobar," 713"};
2'b11 : foobar = {foobar," 714"};
endcase
4'ha :
case (foo[26:25])
2'b00 : foobar = {foobar," 715"};
2'b01 : foobar = {foobar," 716"};
2'b10 : foobar = {foobar," 717"};
2'b11 : foobar = {foobar," 718"};
endcase
4'hb :
case (foo[26:25])
2'b00 : foobar = {foobar," 719"};
2'b01 : foobar = {foobar," 720"};
2'b10 : foobar = {foobar," 721"};
2'b11 : foobar = {foobar," 722"};
endcase
4'hc :
if (foo[26])
foobar = {foobar," 723"};
else
foobar = {foobar," 724"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar," 725"};
2'b01 : foobar = {foobar," 726"};
2'b10 : foobar = {foobar," 727"};
2'b11 : foobar = {foobar," 728"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar," 729"};
2'b01 : foobar = {foobar," 730"};
2'b10 : foobar = {foobar," 731"};
2'b11 : foobar = {foobar," 732"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar," 733"};
2'b01 : foobar = {foobar," 734"};
2'b10 : foobar = {foobar," 735"};
2'b11 : foobar = {foobar," 736"};
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 737"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 738"};
end
5'h01 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 739"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 740"};
end
5'h02 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 741"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 742"};
end
5'h03 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 743"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 744"};
end
5'h04 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 745"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 746"};
end
5'h05 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 747"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 748"};
end
5'h06 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 749"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 750"};
end
5'h07 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 751"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 752"};
end
5'h08 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 753"};
if (foo[ 6])
foobar = {foobar," 754"};
else
foobar = {foobar," 755"};
end
5'h09 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 756"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 757"};
end
5'h0a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 758"};
ozoneae(foo[17:15], foobar);
end
5'h0b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 759"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 760"};
end
5'h0c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 761"};
end
5'h0d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 762"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 763"};
end
5'h0e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 764"};
ozoneae(foo[17:15], foobar);
end
5'h0f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 765"};
ozoneae(foo[17:15], foobar);
end
5'h10 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 766"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 767"};
end
5'h11 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 768"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 769"};
end
5'h18 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 770"};
if (foo[ 6])
foobar = {foobar," 771"};
else
foobar = {foobar," 772"};
end
5'h1a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 773"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 774"};
end
5'h1b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 775"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 776"};
if (foo[ 6])
foobar = {foobar," 777"};
else
foobar = {foobar," 778"};
foobar = {foobar," 779"};
end
5'h1c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 780"};
end
5'h1d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 781"};
if (foo[ 6])
foobar = {foobar," 782"};
else
foobar = {foobar," 783"};
foobar = {foobar," 784"};
end
5'h1e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 785"};
if (foo[ 6])
foobar = {foobar," 786"};
else
foobar = {foobar," 787"};
foobar = {foobar," 788"};
end
5'h1f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 789"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 790"};
if (foo[ 6])
foobar = {foobar," 791"};
else
foobar = {foobar," 792"};
foobar = {foobar," 793"};
end
default :
foobar = {foobar," 794"};
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], foobar);
case (foo[22:21])
2'h0: foobar = {foobar," 795"};
2'h1: foobar = {foobar," 796"};
2'h2: foobar = {foobar," 797"};
endcase
ozoneae(foo[17:15], foobar);
foobar = {foobar," 798"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 799"};
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 800"};
ozoneae(foo[17:15], foobar);
case (foo[23:21])
3'h0: foobar = {foobar," 801"};
3'h1: foobar = {foobar," 802"};
3'h5: foobar = {foobar," 803"};
3'h6: foobar = {foobar," 804"};
3'h7: foobar = {foobar," 805"};
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], foobar);
if (foo[21])
foobar = {foobar," 806"};
else
foobar = {foobar," 807"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 808"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 809"};
ozoneae(foo[17:15], foobar);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 810"};
ozoneae(foo[17:15], foobar);
case (foo[22:21])
2'h0,
2'h2:
foobar = {foobar," 811"};
2'h1,
2'h3:
foobar = {foobar," 812"};
endcase
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 813"};
ozoneae((foo[20:18]+1), foobar);
foobar = {foobar," 814"};
ozoneae((foo[17:15]+1), foobar);
case (foo[22:21])
2'h0,
2'h3:
foobar = {foobar," 815"};
2'h1,
2'h2:
foobar = {foobar," 816"};
endcase
ozoneae((foo[ 8: 6]+1), foobar);
end
5'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 817"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 818"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 819"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 820"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 821"};
ozoneae(foo[ 8: 6], foobar);
end
default :
foobar = {foobar," 822"};
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (te)
3'b100 : foobar = {foobar, " 823"};
3'b101 : foobar = {foobar, " 824"};
3'b110 : foobar = {foobar, " 825"};
default: foobar = {foobar, " 826"};
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ate)
3'b000 : foobar = {foobar, " 827"};
3'b001 : foobar = {foobar, " 828"};
3'b010 : foobar = {foobar, " 829"};
3'b011 : foobar = {foobar, " 830"};
3'b100 : foobar = {foobar, " 831"};
3'b101 : foobar = {foobar, " 832"};
3'b110 : foobar = {foobar, " 833"};
3'b111 : foobar = {foobar, " 834"};
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
foobar = {foobar, " 835"};
5'h01,
5'h05 :
foobar = {foobar, " 836"};
5'h02,
5'h06 :
foobar = {foobar, " 837"};
5'h03,
5'h07 :
foobar = {foobar, " 838"};
5'h08,
5'h18 :
foobar = {foobar, " 839"};
5'h09,
5'h19 :
foobar = {foobar, " 840"};
5'h0a,
5'h1a :
foobar = {foobar, " 841"};
5'h0b :
foobar = {foobar, " 842"};
5'h1b :
foobar = {foobar, " 843"};
5'h0c,
5'h1c :
foobar = {foobar, " 844"};
5'h0d,
5'h1d :
foobar = {foobar, " 845"};
5'h1e :
foobar = {foobar, " 846"};
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : foobar = {foobar, " 847"};
2'b01 : foobar = {foobar, " 848"};
2'b10 : foobar = {foobar, " 849"};
2'b11 : foobar = {foobar, " 850"};
endcase
4'h1:
case (foo[26:25])
2'b00 : foobar = {foobar, " 851"};
2'b01 : foobar = {foobar, " 852"};
2'b10 : foobar = {foobar, " 853"};
2'b11 : foobar = {foobar, " 854"};
endcase
4'h2:
case (foo[26:25])
2'b00 : foobar = {foobar, " 855"};
2'b01 : foobar = {foobar, " 856"};
2'b10 : foobar = {foobar, " 857"};
2'b11 : foobar = {foobar, " 858"};
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 859"};
2'b01 : foobar = {foobar, " 860"};
2'b10 : foobar = {foobar, " 861"};
2'b11 : foobar = {foobar, " 862"};
endcase
4'ha,
4'hb :
if (foo[25])
foobar = {foobar, " 863"};
else
foobar = {foobar, " 864"};
4'hc :
if (foo[26])
foobar = {foobar, " 865"};
else
foobar = {foobar, " 866"};
default :
begin
foobar = {foobar, " 867"};
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
foobar = {foobar, " 868"};
4'h9 :
foobar = {foobar, " 869"};
4'ha,
4'he :
foobar = {foobar, " 870"};
4'hb,
4'hf :
foobar = {foobar, " 871"};
4'hd :
foobar = {foobar, " 872"};
endcase
if (foo[20])
case (foo[18:16])
3'b000 : foobar = {foobar, " 873"};
3'b100 : foobar = {foobar, " 874"};
default: foobar = {foobar, " 875"};
endcase
else
ozoneae(foo[18:16], foobar);
if (foo[24:21] === 4'hc)
if (foo[25])
foobar = {foobar, " 876"};
else
foobar = {foobar, " 877"};
case (foo[24:21])
4'h0,
4'h1,
4'h2:
foobar = {foobar, " 878"};
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : foobar = {foobar, " 879"};
2'h1 : foobar = {foobar, " 880"};
2'h2 : foobar = {foobar, " 881"};
2'h3 : foobar = {foobar, " 882"};
endcase
case (foo[17:16])
2'h1 : foobar = {foobar, " 883"};
2'h2 : foobar = {foobar, " 884"};
2'h3 : foobar = {foobar, " 885"};
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rme)
3'h0 : foobar = {foobar, " 886"};
3'h1 : foobar = {foobar, " 887"};
3'h2 : foobar = {foobar, " 888"};
3'h3 : foobar = {foobar, " 889"};
3'h4 : foobar = {foobar, " 890"};
3'h5 : foobar = {foobar, " 891"};
3'h6 : foobar = {foobar, " 892"};
3'h7 : foobar = {foobar, " 893"};
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 894"};
ozonerme(ye[5:3],foobar);
case ({ye[ 2:0], l})
4'h2,
4'ha: foobar = {foobar, " 895"};
4'h4,
4'hb: foobar = {foobar, " 896"};
4'h6,
4'he: foobar = {foobar, " 897"};
4'h8,
4'hc: foobar = {foobar, " 898"};
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 899"};
ozonerme(ye[5:3],foobar);
ozonef1e_inc_dec(ye[5:0], l ,foobar);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
foobar = {foobar, " 900"};
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: foobar = {foobar, " 901"};
4'h4,
4'h5,
4'hb: foobar = {foobar, " 902"};
4'h6,
4'h7,
4'he: foobar = {foobar, " 903"};
4'h8,
4'h9,
4'hc: foobar = {foobar, " 904"};
4'hf: foobar = {foobar, " 905"};
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: foobar = {foobar, " 906"};
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: foobar = {foobar, " 907"};
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : foobar = {foobar, " 908"};
1'b1 : foobar = {foobar, " 909"};
endcase
case (xe[ 2:0])
3'h1,
3'h5: foobar = {foobar, " 910"};
3'h2,
3'h6: foobar = {foobar, " 911"};
3'h3,
3'h7: foobar = {foobar, " 912"};
3'h4: foobar = {foobar, " 913"};
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rp)
3'h0 : foobar = {foobar, " 914"};
3'h1 : foobar = {foobar, " 915"};
3'h2 : foobar = {foobar, " 916"};
3'h3 : foobar = {foobar, " 917"};
3'h4 : foobar = {foobar, " 918"};
3'h5 : foobar = {foobar, " 919"};
3'h6 : foobar = {foobar, " 920"};
3'h7 : foobar = {foobar, " 921"};
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ry)
4'h0 : foobar = {foobar, " 922"};
4'h1 : foobar = {foobar, " 923"};
4'h2 : foobar = {foobar, " 924"};
4'h3 : foobar = {foobar, " 925"};
4'h4 : foobar = {foobar, " 926"};
4'h5 : foobar = {foobar, " 927"};
4'h6 : foobar = {foobar, " 928"};
4'h7 : foobar = {foobar, " 929"};
4'h8 : foobar = {foobar, " 930"};
4'h9 : foobar = {foobar, " 931"};
4'ha : foobar = {foobar, " 932"};
4'hb : foobar = {foobar, " 933"};
4'hc : foobar = {foobar, " 934"};
4'hd : foobar = {foobar, " 935"};
4'he : foobar = {foobar, " 936"};
4'hf : foobar = {foobar, " 937"};
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : foobar = {foobar, " 938"};
2'h1 : foobar = {foobar, " 939"};
2'h2 : foobar = {foobar, " 940"};
2'h3 : foobar = {foobar, " 941"};
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: foobar = {foobar, " 942"};
5'b001??: foobar = {foobar, " 943"};
5'b?10??: foobar = {foobar, " 944"};
5'b0110?: foobar = {foobar, " 945"};
5'b01110: foobar = {foobar, " 946"};
5'b01111: foobar = {foobar, " 947"};
5'b10???: foobar = {foobar, " 948"};
5'b11100: foobar = {foobar, " 949"};
5'b11101: foobar = {foobar, " 950"};
5'b11110: foobar = {foobar, " 951"};
5'b11111: foobar = {foobar, " 952"};
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (con)
5'h00 : foobar = {foobar, " 953"};
5'h01 : foobar = {foobar, " 954"};
5'h02 : foobar = {foobar, " 955"};
5'h03 : foobar = {foobar, " 956"};
5'h04 : foobar = {foobar, " 957"};
5'h05 : foobar = {foobar, " 958"};
5'h06 : foobar = {foobar, " 959"};
5'h07 : foobar = {foobar, " 960"};
5'h08 : foobar = {foobar, " 961"};
5'h09 : foobar = {foobar, " 962"};
5'h0a : foobar = {foobar, " 963"};
5'h0b : foobar = {foobar, " 964"};
5'h0c : foobar = {foobar, " 965"};
5'h0d : foobar = {foobar, " 966"};
5'h0e : foobar = {foobar, " 967"};
5'h0f : foobar = {foobar, " 968"};
5'h10 : foobar = {foobar, " 969"};
5'h11 : foobar = {foobar, " 970"};
5'h12 : foobar = {foobar, " 971"};
5'h13 : foobar = {foobar, " 972"};
5'h14 : foobar = {foobar, " 973"};
5'h15 : foobar = {foobar, " 974"};
5'h16 : foobar = {foobar, " 975"};
5'h17 : foobar = {foobar, " 976"};
5'h18 : foobar = {foobar, " 977"};
5'h19 : foobar = {foobar, " 978"};
5'h1a : foobar = {foobar, " 979"};
5'h1b : foobar = {foobar, " 980"};
5'h1c : foobar = {foobar, " 981"};
5'h1d : foobar = {foobar, " 982"};
5'h1e : foobar = {foobar, " 983"};
5'h1f : foobar = {foobar, " 984"};
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : foobar = {foobar, " 985"};
4'h1 : foobar = {foobar, " 986"};
4'h2 : foobar = {foobar, " 987"};
4'h3 : foobar = {foobar, " 988"};
4'h4 : foobar = {foobar, " 989"};
4'h5 : foobar = {foobar, " 990"};
4'h6 : foobar = {foobar, " 991"};
4'h7 : foobar = {foobar, " 992"};
4'h8 : foobar = {foobar, " 993"};
4'h9 : foobar = {foobar, " 994"};
4'ha : foobar = {foobar, " 995"};
4'hb : foobar = {foobar, " 996"};
4'hc : foobar = {foobar, " 997"};
4'hd : foobar = {foobar, " 998"};
4'he : foobar = {foobar, " 999"};
4'hf : foobar = {foobar, " 1000"};
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : foobar = {foobar, " 1001"};
2'h1 : foobar = {foobar, " 1002"};
2'h2 : foobar = {foobar, " 1003"};
2'h3 : foobar = {foobar, " 1004"};
endcase
end
endtask
task ozoneacc;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1005"};
2'h1 : foobar = {foobar, " 1006"};
endcase
end
endtask
task ozonehl;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1007"};
2'h1 : foobar = {foobar, " 1008"};
endcase
end
endtask
task dude;
inout [STRLEN*8: 1] foobar;
reg [ 7:0] temp;
integer i;
reg nacho;
// verilator no_inline_task
begin : justify_block
nacho = 1'b0;
for (i=STRLEN-1; i>1; i=i-1)
begin
temp = foobar>>((STRLEN-1)*8);
if (temp || nacho)
nacho = 1'b1;
else
begin
foobar = foobar<<8;
foobar[8:1] = 32;
end
end
end
endtask
task big_case;
input [ 31:0] fd;
input [ 31:0] foo;
reg [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = " 1009";
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1011"};
ozoneacc(~foo[26], foobar);
ozonehl(foo[20], foobar);
foobar = {foobar, " 1012"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1013:%s", foobar);
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1014"};
ozonerx(foo, foobar);
foobar = {foobar, " 1015"};
foobar = {foobar, " 1016"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1017:%s", foobar);
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1018"};
ozonerx(foo, foobar);
foobar = {foobar, " 1019"};
foobar = {foobar, " 1020"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1021:%s", foobar);
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1022"};
if (foo[20])
begin
foobar = {foobar, " 1023"};
ozoneacc(foo[18], foobar);
foobar = {foobar, " 1024"};
foobar = {foobar, " 1025"};
if (foo[19])
foobar = {foobar, " 1026"};
else
foobar = {foobar, " 1027"};
end
else
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1028:%s", foobar);
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1029"};
foobar = {foobar, " 1030"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1031"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1032:%s", foobar);
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1033"};
foobar = {foobar, " 1034"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1035"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1036:%s", foobar);
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1037"};
ozonerx(foo, foobar);
foobar = {foobar, " 1038"};
foobar = {foobar, " 1039"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1040:%s", foobar);
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1041"};
foobar = {foobar, " 1042"};
ozonerx(foo, foobar);
foobar = {foobar, " 1043"};
if (foo[20])
foobar = {foobar, " 1044"};
else
foobar = {foobar, " 1045"};
dude(foobar);
$fwrite (fd, " 1046:%s", foobar);
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
foobar = " 1047";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1048"};
ozonef1e(foo, foobar);
dude(foobar);
$fwrite (fd, " 1049:%s", foobar);
end
7'b00_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1050"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
foobar = {foobar, " 1051"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b01:
begin
foobar = {foobar, " 1052"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b10:
begin
foobar = {foobar, " 1053"};
ozoneae(foo[14:12], foobar);
end
2'b11: foobar = {foobar, " 1054"};
endcase
dude(foobar);
$fwrite (fd, " 1055:%s", foobar);
end
7'b01_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1056"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1057"};
end
2'b01:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1058"};
end
2'b10:
begin
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1059"};
end
2'b11: foobar = {foobar, " 1060"};
endcase
dude(foobar);
$fwrite (fd, " 1061:%s", foobar);
end
7'b10_0_110_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1062"};
foobar = {foobar, " 1063"};
if (foo[12])
foobar = {foobar, " 1064"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
dude(foobar);
$fwrite (fd, " 1065:%s", foobar);
end
7'b10_0_110_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1066"};
if (foo[12])
foobar = {foobar, " 1067"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1068"};
dude(foobar);
$fwrite (fd, " 1069:%s", foobar);
end
7'b??_?_000_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1070"};
foobar = {foobar, " 1071"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1072"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1073:%s", foobar);
end
7'b??_?_100_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1074"};
foobar = {foobar, " 1075"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1076"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1077:%s", foobar);
end
7'b??_?_001_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1078"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1079"};
foobar = {foobar, " 1080"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1081:%s", foobar);
end
7'b??_?_011_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1082"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1083"};
foobar = {foobar, " 1084"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1085:%s", foobar);
end
7'b??_?_101_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1086"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1087:%s", foobar);
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1088"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1089"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1090:%s", foobar);
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1091"};
if (foo[ 6])
foobar = {foobar, " 1092"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
foobar = {foobar, " 1093"};
foobar = {foobar, " 1094"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1095"};
endcase
dude(foobar);
$fwrite (fd, " 1096:%s", foobar);
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1097"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1098"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1099:%s", foobar);
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1100"};
foobar = {foobar, " 1101"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1102"};
endcase
foobar = {foobar, " 1103"};
if (foo[ 6])
foobar = {foobar, " 1104"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
dude(foobar);
$fwrite (fd, " 1105:%s", foobar);
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1106"};
case (foo[11:9])
3'h2:
begin
foobar = {foobar, " 1107"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1108"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1109"};
end
3'h6:
begin
foobar = {foobar, " 1110"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1111"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1112"};
end
3'h0:
begin
foobar = {foobar, " 1113"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1114"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1115"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1116"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h1:
begin
foobar = {foobar, " 1117"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1118"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1119"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1120"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h4:
begin
foobar = {foobar, " 1121"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1122"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1123"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1124"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h5:
begin
foobar = {foobar, " 1125"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1126"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1127"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1128"};
else
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1129:%s", foobar);
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1130"};
foobar = {foobar, " 1131"};
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1132"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1133:%s", foobar);
end
6'b???_11_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1134"};
ozoneae(foo[14:12], foobar);
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1135"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1136:%s", foobar);
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1137"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1138"};
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
foobar = {foobar, " 1139"};
else
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1140:%s", foobar);
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1141"};
foobar = {foobar, " 1142"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1143"};
foobar = {foobar, " 1144"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1145"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1146:%s", foobar);
end
6'b???_00_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1147"};
if (foo[ 9])
begin
foobar = {foobar, " 1148"};
ozoneae(foo[14:12], foobar);
end
else
begin
foobar = {foobar, " 1149"};
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1150"};
end
foobar = {foobar, " 1151"};
foobar = {foobar, " 1152"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1153"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1154:%s", foobar);
end
6'b???_01_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1155"};
ozoneae(foo[14:12], foobar);
if (foo[ 9])
foobar = {foobar, " 1156"};
else
foobar = {foobar, " 1157"};
foobar = {foobar, " 1158"};
foobar = {foobar, " 1159"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1160"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1161:%s", foobar);
end
6'b011_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1162"};
case (foo[ 8: 5])
4'h0: foobar = {foobar, " 1163"};
4'h1: foobar = {foobar, " 1164"};
4'h2: foobar = {foobar, " 1165"};
4'h3: foobar = {foobar, " 1166"};
4'h4: foobar = {foobar, " 1167"};
4'h5: foobar = {foobar, " 1168"};
4'h8: foobar = {foobar, " 1169"};
4'h9: foobar = {foobar, " 1170"};
4'ha: foobar = {foobar, " 1171"};
4'hb: foobar = {foobar, " 1172"};
4'hc: foobar = {foobar, " 1173"};
4'hd: foobar = {foobar, " 1174"};
default: foobar = {foobar, " 1175"};
endcase
dude(foobar);
$fwrite (fd, " 1176:%s", foobar);
end
default: foobar = {foobar, " 1177"};
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1178"};
foobar = {foobar, " 1179"};
ozonef1e_hl(foo[11:9], foo[0], foobar);
foobar = {foobar, " 1180"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1181"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1182"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1183:%s", foobar);
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1184"};
foobar = {foobar, " 1185"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1186"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1187"};
foobar = {foobar, " 1188"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1189"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1190:%s", foobar);
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1191"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1192"};
foobar = {foobar, " 1193"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1194"};
foobar = {foobar, " 1195"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1196"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1197:%s", foobar);
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1198"};
foobar = {foobar, " 1199"};
ozonef1e_h(foo[11:9],foobar);
foobar = {foobar, " 1200"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1201"};
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
foobar = {foobar, " 1202"};
default:
begin
foobar = {foobar, " 1203"};
foobar = {foobar, " 1204"};
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1205:%s", foobar);
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1206"};
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1207"};
default:
begin
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1208"};
foobar = {foobar, " 1209"};
end
endcase
foobar = {foobar, " 1210"};
foobar = {foobar, " 1211"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1212"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1213:%s", foobar);
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1214"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1215"};
foobar = {foobar, " 1216"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1217"};
foobar = {foobar, " 1218"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1219"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1220:%s", foobar);
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1221"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1222"};
foobar = {foobar, " 1223"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1224"};
foobar = {foobar, " 1225"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1226"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1227:%s", foobar);
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
foobar = " 1228";
else
foobar = " 1229";
ozonecon(foo[20:16], foobar);
foobar = {foobar, " 1230"};
ozonef2(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1231:%s", foobar);
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
foobar = " 1232";
else
foobar = " 1233";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1234"};
ozonef2e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1235:%s", foobar);
end
else
begin
foobar = " 1236";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1237"};
ozonef3e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1238:%s", foobar);
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], foobar);
dude(foobar);
$fwrite(fd, " 1239:%s", foobar);
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1241"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1242"};
dude(foobar);
$fwrite(fd, " 1243:%s", foobar);
end
5'b0_01??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1244"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozonearm(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1245:%s", foobar);
end
5'b0_1011:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1246"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1247"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1248"};
dude(foobar);
$fwrite(fd, " 1249:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1250"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1251"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1252"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1253"};
dude(foobar);
$fwrite(fd, " 1254:%s", foobar);
end
5'b0_1111 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1255"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1256"};
ozoneae(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1257:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1258"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1259"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1260"};
ozonearm(foo[18:16], foobar);
foobar = {foobar, " 1261"};
dude(foobar);
$fwrite(fd, " 1262:%s", foobar);
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1263"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1264"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1265"};
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3:0], foobar);
foobar = {foobar, " 1266"};
dude(foobar);
$fwrite(fd, " 1267:%s", foobar);
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1268"};
if (foo[23:21] == 3'b100)
foobar = {foobar, " 1269"};
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1270"};
else
foobar = {foobar, " 1271"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1272"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1273:%s", foobar);
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1274"};
else
foobar = {foobar, " 1275"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1276"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1277:%s", foobar);
end
endcase
17'b00_1000_?_????_11_0011 :
begin
foobar = " 1278";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1279"};
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1281"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1282"};
dude(foobar);
$fwrite(fd, " 1283:%s", foobar);
end
5'b0_01??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1284"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozonearm(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1285:%s", foobar);
end
5'b0_1011:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1286"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1287"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1288"};
dude(foobar);
$fwrite(fd, " 1289:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1290"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1291"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1292"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1293"};
dude(foobar);
$fwrite(fd, " 1294:%s", foobar);
end
5'b0_1111 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1295"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1296"};
ozoneae(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1297:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1298"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1299"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1300"};
ozonearm(foo[ 8: 6], foobar);
foobar = {foobar, " 1301"};
dude(foobar);
$fwrite(fd, " 1302:%s", foobar);
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
$fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]);
ozonerab({1'b0, foo[25:20]}, foobar);
$fwrite(fd, " 1304b:%x", foobar);
foobar = {foobar, " 1303"};
$fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]);
skyway(foo[19:16], foobar);
$fwrite(fd, " 1304d:%x", foobar);
dude(foobar);
$fwrite(fd, " 1304e:%x", foobar);
$fwrite(fd, " 1304:%s", foobar);
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
foobar = {foobar, " 1305"};
if (foo[26])
foobar = {foobar, " 1306"};
else
foobar = {foobar, " 1307"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1308"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
else
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1309"};
if (foo[26])
foobar = {foobar, " 1310"};
else
foobar = {foobar, " 1311"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1312"};
end
dude(foobar);
$fwrite(fd, " 1313:%s", foobar);
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], foobar);
foobar = {foobar, " 1314"};
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
end
else
begin
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
foobar = {foobar, " 1315"};
ozonerb(foo[25:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1316:%s", foobar);
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1317"};
ozonerx(foo, foobar);
end
else
begin
ozonerx(foo, foobar);
foobar = {foobar, " 1318"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
dude(foobar);
$fwrite(fd, " 1319:%s", foobar);
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], foobar);
foobar = {foobar, " 1320"};
skyway(foo[19:16], foobar);
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3: 0], foobar);
dude(foobar);
$fwrite(fd, " 1321:%s", foobar);
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1322"};
end
3'b01?:
begin
foobar = {foobar, " 1323"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1324"};
else
ozonerab(foo[22:16], foobar);
end
3'b110:
foobar = {foobar, " 1325"};
3'b10?:
begin
foobar = {foobar, " 1326"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1327"};
else
ozonerab(foo[22:16], foobar);
end
3'b111:
begin
foobar = {foobar, " 1328"};
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1329"};
end
endcase
dude(foobar);
$fwrite(fd, " 1330:%s", foobar);
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
foobar = {foobar, " 1331"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1332"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1333"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1334"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1335"};
foobar = {foobar, " 1336"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1337"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1338"};
end
dude(foobar);
$fwrite(fd, " 1339:%s", foobar);
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
foobar = {foobar, " 1340"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1341"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1342"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1343"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1344"};
foobar = {foobar, " 1345"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1346"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1347"};
end
dude(foobar);
$fwrite(fd, " 1348:%s", foobar);
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1350"};
ozoneye(foo[14: 9],foo[ 5], foobar);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], foobar);
foobar = {foobar, " 1351"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1352"};
else
ozonerab(foo[26:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1353:%s", foobar);
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, foobar);
foobar = {foobar, " 1355"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1356"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1357"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1358:%s", foobar);
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
foobar = {foobar, " 1360"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1361"};
else
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1362"};
foobar = {foobar, " 1363"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1364:%s", foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1365"};
foobar = {foobar, " 1366"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1367:%s", foobar);
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar);
foobar = {foobar, " 1369"};
ozonerab({1'b0,foo[25:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1370:%s", foobar);
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
foobar = " 1371";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1372"};
ozonerab({foo[ 9: 7],foo[19:16]}, foobar);
foobar = {foobar, " 1373"};
ozonerab({foo[26:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1374:%s", foobar);
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1376"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1377"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1378:%s", foobar);
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1379"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1380"};
ozonejk(foo[ 5], foobar);
dude(foobar);
$fwrite(fd, " 1381:%s", foobar);
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%s", foo[27:16]);
else
$fwrite(fd, " 1384:%s", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%s", foo[27: 8]);
else
$fwrite(fd, " 1386:%s", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
foobar = " 1388";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1389"};
if (foo[15])
foobar = {foobar, " 1390"};
else
foobar = {foobar, " 1391"};
skyway(foo[27:24], foobar);
skyway(foo[23:20], foobar);
skyway(foo[19:16], foobar);
skyway(foo[ 9: 6], foobar);
dude(foobar);
$fwrite(fd, " 1392:%s", foobar);
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
foobar = " 1393";
ozonecon(foo[20:16], foobar);
case (foo[23:21])
3'h0 : foobar = {foobar, " 1394"};
3'h1 : foobar = {foobar, " 1395"};
3'h2 : foobar = {foobar, " 1396"};
3'h3 : foobar = {foobar, " 1397"};
3'h4 : foobar = {foobar, " 1398"};
3'h5 : foobar = {foobar, " 1399"};
3'h6 : foobar = {foobar, " 1400"};
3'h7 : foobar = {foobar, " 1401"};
endcase
dude(foobar);
$fwrite(fd, " 1402:%s", foobar);
end
4'b0000 :
$fwrite(fd, " 1403:%s", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%s", foo[22:16]);
else
$fwrite(fd, " 1409:%s", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Export Coq.Classes.CRelationClasses.
Generalizable Variables A eqA B C D R RA RB RC m f x y.
Local Obligation Tactic := try solve [ simpl_crelation ].
Set Universe Polymorphism.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Section Proper.
Context {A : Type}.
Class Proper (R : crelation A) (m : A) :=
proper_prf : R m m.
(** Every element in the carrier of a reflexive relation is a morphism
for this relation. We use a proxy class for this case which is used
internally to discharge reflexivity constraints. The [Reflexive]
instance will almost always be used, but it won't apply in general to
any kind of [Proper (A -> B) _ _] goal, making proof-search much
slower. A cleaner solution would be to be able to set different
priorities in different hint bases and select a particular hint
database for resolution of a type class constraint. *)
Class ProperProxy (R : crelation A) (m : A) :=
proper_proxy : R m m.
Lemma eq_proper_proxy (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy x `(Proper R x) : ProperProxy R x.
Proof. firstorder. Qed.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Type)
(R' : forall (x : A) (y : B), C x -> D y -> Type) :
(forall x : A, C x) -> (forall x : B, D x) -> Type :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful {B} (R : crelation A) (R' : crelation B) : crelation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
End Proper.
(** We favor the use of Leibniz equality or a declared reflexive crelation
when resolving [ProperProxy], otherwise, if the crelation is given (not an evar),
we fall back to [Proper]. *)
#[global]
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
#[global]
Hint Extern 2 (ProperProxy ?R _) =>
not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Declare Scope signatureT_scope.
Delimit Scope signatureT_scope with signatureT.
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signatureT) (R'%signatureT))
(right associativity, at level 55) : signatureT_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signatureT) (R'%signatureT))
(right associativity, at level 55) : signatureT_scope.
Notation " R --> R' " := (@respectful _ _ (flip (R%signatureT)) (R'%signatureT))
(right associativity, at level 55) : signatureT_scope.
End ProperNotations.
Arguments Proper {A}%type R%signatureT m.
Arguments respectful {A B}%type (R R')%signatureT _ _.
Export ProperNotations.
Local Open Scope signatureT_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : crelation T);
let H := fresh in
assert (H : (Rx==>R)%signatureT f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
solve [change (Proper R f); eauto with typeclass_instances | reflexivity ]
| _ => idtac
end.
Section Relations.
Context {A : Type}.
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def (P : A -> Type) : Type := forall x : A, P x.
(** Dependent pointwise lifting of a crelation on the range. *)
Definition forall_relation (P : A -> Type)
(sig : forall a, crelation (P a)) : crelation (forall x, P x) :=
fun f g => forall a, sig a (f a) (g a).
(** Non-dependent pointwise lifting *)
Definition pointwise_relation {B} (R : crelation B) : crelation (A -> B) :=
fun f g => forall a, R (f a) (g a).
Lemma pointwise_pointwise {B} (R : crelation B) :
relation_equivalence (pointwise_relation R) (@eq A ==> R).
Proof.
intros. split.
- simpl_crelation.
- firstorder.
Qed.
(** Subcrelations induce a morphism on the identity. *)
Global Instance subrelation_id_proper `(subrelation A RA RA') : Proper (RA ==> RA') id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A RA' RA, subr : subrelation B RB RB') :
subrelation (RA ==> RB) (RA' ==> RB').
Proof. simpl_crelation. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl R : @subrelation A R R.
Proof. simpl_crelation. Qed.
(** [Proper] is itself a covariant morphism for [subrelation].
We use an unconvertible premise to avoid looping.
*)
Lemma subrelation_proper `(mor : Proper A R' m)
`(unc : Unconvertible (crelation A) R R')
`(sub : subrelation A R' R) : Proper R m.
Proof.
intros. apply sub. apply mor.
Qed.
Global Instance proper_subrelation_proper_arrow :
Proper (subrelation ++> eq ==> arrow) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
Global Instance pointwise_subrelation `(sub : subrelation B R R') :
subrelation (pointwise_relation R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. auto. Qed.
(** For dependent function types. *)
Lemma forall_subrelation (P : A -> Type) (R S : forall x : A, crelation (P x)) :
(forall a, subrelation (R a) (S a)) ->
subrelation (forall_relation P R) (forall_relation P S).
Proof. reduce. firstorder. Qed.
End Relations.
Global Typeclasses Opaque respectful pointwise_relation forall_relation.
Arguments forall_relation {A P}%type sig%signatureT _ _.
Arguments pointwise_relation A%type {B}%type R%signatureT _ _.
#[global]
Hint Unfold Reflexive : core.
#[global]
Hint Unfold Symmetric : core.
#[global]
Hint Unfold Transitive : core.
(** Resolution with subrelation: favor decomposing products over applying reflexivity
for unconstrained goals. *)
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
#[global]
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
#[global]
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
#[global]
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
#[global]
Instance iff_flip_impl_subrelation : subrelation iff (flip impl) | 2.
Proof. firstorder. Qed.
(** Essential subrelation instances for [iffT] and [arrow]. *)
#[global]
Instance iffT_arrow_subrelation : subrelation iffT arrow | 2.
Proof. firstorder. Qed.
#[global]
Instance iffT_flip_arrow_subrelation : subrelation iffT (flip arrow) | 2.
Proof. firstorder. Qed.
(** We use an extern hint to help unification. *)
#[global]
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
Section GenericInstances.
(* Share universes *)
Implicit Types A B C : Type.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
intros A R H B R' H0 x y z X X0 x0 y0 X1.
assert(R x0 x0).
- transitivity y0... symmetry...
- transitivity (y x0)...
Qed.
Unset Strict Universe Declaration.
(** The complement of a crelation conserves its proper elements. *)
(** The [flip] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
intros A B C RA RB RC f mor x y X x0 y0 X0.
apply mor ; auto.
Qed.
(** Every Transitive crelation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Global Program
Instance trans_contra_co_type_morphism
`(Transitive A R) : Proper (R --> R ++> arrow) R.
Next Obligation.
Proof with auto.
intros A R H x y X x0 y0 X0 X1.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Global Program
Instance trans_contra_inv_impl_type_morphism
`(Transitive A R) {x} : Proper (R --> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
intros A R H x x0 y X X0.
transitivity y...
Qed.
Global Program
Instance trans_co_impl_type_morphism
`(Transitive A R) {x} : Proper (R ++> arrow) (R x) | 3.
Next Obligation.
Proof with auto.
intros A R H x x0 y X X0.
transitivity x0...
Qed.
Global Program
Instance trans_sym_co_inv_impl_type_morphism
`(PER A R) {x} : Proper (R ++> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
intros A R H x x0 y X X0.
transitivity y... symmetry...
Qed.
Global Program Instance trans_sym_contra_arrow_morphism
`(PER A R) {x} : Proper (R --> arrow) (R x) | 3.
Next Obligation.
Proof with auto.
intros A R H x x0 y X X0.
transitivity x0... symmetry...
Qed.
Global Program Instance per_partial_app_type_morphism
`(PER A R) {x} : Proper (R ==> iffT) (R x) | 2.
Next Obligation.
Proof with auto.
intros A R H x x0 y X.
split.
- intros ; transitivity x0...
- intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive crelation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof to get an [R y z] goal. *)
Global Program
Instance trans_co_eq_inv_arrow_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> flip arrow) R | 2.
Next Obligation.
Proof with auto.
intros A R H x y X y0 y1 e X0; destruct e.
transitivity y...
Qed.
(** Every Symmetric and Transitive crelation gives rise to an equivariant morphism. *)
Global Program
Instance PER_type_morphism `(PER A R) : Proper (R ==> R ==> iffT) R | 1.
Next Obligation.
Proof with auto.
intros A R H x y X x0 y0 X0.
split ; intros.
- transitivity x0... transitivity x... symmetry...
- transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_flip `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Global Program Instance compose_proper A B C RA RB RC :
Proper ((RB ==> RC) ==> (RA ==> RB) ==> (RA ==> RC)) (@compose A B C).
Next Obligation.
Proof.
simpl_crelation.
unfold compose. firstorder.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Global Instance reflexive_eq_dom_reflexive `(Reflexive B R') {A} :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_crelation. Qed.
(** [respectful] is a morphism for crelation equivalence . *)
Global Instance respectful_morphism {A B} :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence)
(@respectful A B).
Proof.
intros R R' HRR' S S' HSS' f g.
unfold respectful , relation_equivalence in *; simpl in *.
split ; intros H x y Hxy.
- apply (fst (HSS' _ _)). apply H. now apply (snd (HRR' _ _)).
- apply (snd (HSS' _ _)). apply H. now apply (fst (HRR' _ _)).
Qed.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_crelation. Qed.
Class Params {A} (of : A) (arity : nat).
Lemma flip_respectful {A B} (R : crelation A) (R' : crelation B) :
relation_equivalence (flip (R ==> R')) (flip R ==> flip R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Treating flip: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma flip1 `(subrelation A R' R) : subrelation (flip (flip R')) R.
Proof. firstorder. Qed.
Lemma flip2 `(subrelation A R R') : subrelation R (flip (flip R')).
Proof. firstorder. Qed.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_crelation. Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_flip_proper `(mor : Proper A R m) : Proper (flip R) m := mor.
(** Every reflexive crelation gives rise to a morphism,
only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A) : Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq {A} (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
End GenericInstances.
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Ltac partial_application_tactic :=
let rec do_partial_apps H m cont :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ;
[(do_partial_apps H m' ltac:(idtac))|clear H]
| _ => cont
end
in
let rec do_partial H ar m :=
match ar with
| 0%nat => do_partial_apps H m ltac:(fail 1)
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let params m sk fk :=
(let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by typeclasses eauto ;
let v' := eval compute in v in subst m';
(sk H v' || fail 1))
|| fk
in
let on_morphism m cont :=
params m ltac:(fun H n => do_partial H n m)
ltac:(cont)
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ H : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism; [|clear H]
| _ => on_morphism (m x)
ltac:(class_apply @Reflexive_partial_app_morphism)
end
end.
(** Bootstrap !!! *)
#[global]
Instance proper_proper {A} : Proper (relation_equivalence ==> eq ==> iffT) (@Proper A).
Proof.
intros R R' HRR' x y <-. red in HRR'.
split ; red ; intros.
- now apply (fst (HRR' _ _)).
- now apply (snd (HRR' _ _)).
Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
#[global]
Hint Extern 1 (subrelation (flip _) _) => class_apply @flip1 : typeclass_instances.
#[global]
Hint Extern 1 (subrelation _ (flip _)) => class_apply @flip2 : typeclass_instances.
(* Hint Extern 1 (Proper _ (complement _)) => apply @complement_proper *)
(* : typeclass_instances. *)
#[global]
Hint Extern 1 (Proper _ (flip _)) => apply @flip_proper
: typeclass_instances.
#[global]
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_flip_proper
: typeclass_instances.
#[global]
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic
: typeclass_instances.
#[global]
Hint Extern 7 (@Proper _ _ _) => proper_reflexive
: typeclass_instances.
(** Special-purpose class to do normalization of signatures w.r.t. flip. *)
Section Normalize.
Context (A : Type).
Class Normalizes (m : crelation A) (m' : crelation A) :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [flip] everywhere and reduce using [subrelation]
afterwards. *)
Lemma proper_normalizes_proper `(Normalizes R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
apply (_ : Normalizes R0 R1). assumption.
Qed.
Lemma flip_atom R : Normalizes R (flip (flip R)).
Proof.
firstorder.
Qed.
End Normalize.
Lemma flip_arrow `(NA : Normalizes A R (flip R'''), NB : Normalizes B R' (flip R'')) :
Normalizes (A -> B) (R ==> R') (flip (R''' ==> R'')%signatureT).
Proof.
unfold Normalizes in *. intros.
rewrite NA, NB. firstorder.
Qed.
Ltac normalizes :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @flip_arrow
| _ => class_apply @flip_atom
end.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] =>
let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
#[global]
Hint Extern 1 (Normalizes _ _ _) => normalizes : typeclass_instances.
#[global]
Hint Extern 6 (@Proper _ _ _) => proper_normalization
: typeclass_instances.
(** When the crelation on the domain is symmetric, we can
flip the crelation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>flip R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>flip R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the crelation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary crelation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_arrow_iffT : forall `(Symmetric A R)`(Proper _ (R==>arrow) f),
Proper (R==>iffT) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_arrow_iffT_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>arrow) f),
Proper (R==>R'==>iffT) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Require Import Relation_Definitions.
#[global]
Instance PartialOrder_proper_type `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iffT) R.
Proof.
intros.
apply proper_sym_arrow_iffT_2. 1-2: auto with crelations.
intros x x' Hx y y' Hy Hr.
transitivity x.
- generalize (partial_order_equivalence x x'); compute; intuition.
- transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
- intros x (_,Hx). apply Hx, Equivalence_Reflexive.
- intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
+ apply PreOrder_Transitive with y; assumption.
+ intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz. auto.
Qed.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iffT) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
- intros x. right. reflexivity.
- intros x y z [Hxy|Hxy] [Hyz|Hyz].
+ left. transitivity y; auto.
+ left. rewrite <- Hyz; auto.
+ left. rewrite Hxy; auto.
+ right. transitivity y; auto.
Qed.
#[global]
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iffT) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
#[global]
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
#[global]
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_performance_counter_0 (
// inputs:
address,
begintransfer,
clk,
reset_n,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 2: 0] address;
input begintransfer;
input clk;
input reset_n;
input write;
input [ 31: 0] writedata;
wire clk_en;
reg [ 63: 0] event_counter_0;
reg [ 63: 0] event_counter_1;
wire global_enable;
wire global_reset;
wire go_strobe_0;
wire go_strobe_1;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
wire stop_strobe_0;
wire stop_strobe_1;
reg [ 63: 0] time_counter_0;
reg [ 63: 0] time_counter_1;
reg time_counter_enable_0;
reg time_counter_enable_1;
wire write_strobe;
//control_slave, which is an e_avalon_slave
assign clk_en = -1;
assign write_strobe = write & begintransfer;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_0 <= 0;
else if ((time_counter_enable_0 & global_enable) | global_reset)
if (global_reset)
time_counter_0 <= 0;
else
time_counter_0 <= time_counter_0 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_0 <= 0;
else if ((go_strobe_0 & global_enable) | global_reset)
if (global_reset)
event_counter_0 <= 0;
else
event_counter_0 <= event_counter_0 + 1;
end
assign stop_strobe_0 = (address == 0) && write_strobe;
assign go_strobe_0 = (address == 1) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_0 <= 0;
else if (clk_en)
if (stop_strobe_0 | global_reset)
time_counter_enable_0 <= 0;
else if (go_strobe_0)
time_counter_enable_0 <= -1;
end
assign global_enable = time_counter_enable_0 | go_strobe_0;
assign global_reset = stop_strobe_0 && writedata[0];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_1 <= 0;
else if ((time_counter_enable_1 & global_enable) | global_reset)
if (global_reset)
time_counter_1 <= 0;
else
time_counter_1 <= time_counter_1 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_1 <= 0;
else if ((go_strobe_1 & global_enable) | global_reset)
if (global_reset)
event_counter_1 <= 0;
else
event_counter_1 <= event_counter_1 + 1;
end
assign stop_strobe_1 = (address == 4) && write_strobe;
assign go_strobe_1 = (address == 5) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_1 <= 0;
else if (clk_en)
if (stop_strobe_1 | global_reset)
time_counter_enable_1 <= 0;
else if (go_strobe_1)
time_counter_enable_1 <= -1;
end
assign read_mux_out = ({32 {(address == 0)}} & time_counter_0[31 : 0]) |
({32 {(address == 1)}} & time_counter_0[63 : 32]) |
({32 {(address == 2)}} & event_counter_0) |
({32 {(address == 4)}} & time_counter_1[31 : 0]) |
({32 {(address == 5)}} & time_counter_1[63 : 32]) |
({32 {(address == 6)}} & event_counter_1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
endmodule
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always force reg_lvalue = constant ;
// D: No dependancy
module main ;
reg [3:0] value1 ;
initial
begin
#15;
if(value1 != 4'h5)
$display("FAILED - 3.1.3D always force reg_lvalue = constant;\n");
else
begin
$display("PASSED\n");
$finish;
end
end
always force value1 = 4'h5;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_csr_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The following registers are maintained here.
// A8, B8 - L2 BIST control register.
// A9, B9 - L2 control register
// AA, BA - L2 Error Enable Register
// AB, BB - L2 Error Status register.
// AC, BC - L2 Error Address register.
// AD, BD - L2 Error Injection Register.
// AE,AF, BE, BF - L2 Tag SelF time MArgin Register
// The L2 diagnostic addresses are as follows
// A0-A3, B0-B3 - L2 data
// A4,A5, B0,B5 - L2 Address
// A6,A7,B6,B7 - L2 VUAD
`include "iop.h"
`include "sctag.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module sctag_csr_ctl( /*AUTOARG*/
// Outputs
fbctl_decc_scrd_corr_err_c8, fbctl_decc_scrd_uncorr_err_c8,
mbctl_decc_spcfb_corr_err_c8, mbctl_decc_spcd_corr_err_c8,
fbctl_decc_bscd_corr_err_c8, fbctl_decc_bscd_uncorr_err_c8,
arbctl_data_ecc_active_c3, decc_data_ecc_active_c3,
tagdp_l2_dir_map_on, mbctl_l2_dir_map_on, fbctl_l2_dir_map_on,
arbctl_dbginit_l, mbctl_dbginit_l, fbctl_dbginit_l,
tagctl_dbginit_l, tagdp_ctl_dbginit_l, csr_dbginit_l,
wbctl_dbginit_l, so, csr_ctl_wr_en_c8, csr_erren_wr_en_c8,
csr_errstate_wr_en_c8, csr_errinj_wr_en_c8, err_state_in_rw,
err_state_in_mec, err_state_in_meu, err_state_in, csr_synd_wr_en,
mux1_synd_sel, mux2_synd_sel, wr_enable_tid_c9, csr_tid_wr_en,
csr_async_wr_en, set_async_c9, error_rw_en, diag_wr_en,
mux1_addr_sel, mux2_addr_sel, csr_addr_wr_en, csr_rd_mux1_sel_c7,
csr_rd_mux2_sel_c7, csr_rd_mux3_sel_c7, sctag_por_req,
csr_bist_wr_en_c8,
// Inputs
arbctl_csr_wr_en_c7, arbdp_word_addr_c6, rclk, si, se, rst_tri_en,
vuad_error_c8, dir_error_c8, decc_spcd_corr_err_c8,
decc_spcd_uncorr_err_c8, decc_scrd_corr_err_c8,
decc_scrd_uncorr_err_c8, decc_spcfb_corr_err_c8,
decc_spcfb_uncorr_err_c8, decc_bscd_corr_err_c8,
decc_bscd_uncorr_err_c8, tag_error_c8, data_ecc_active_c3,
l2_dir_map_on, dbginit_l, dram_scb_secc_err_d1,
dram_scb_mecc_err_d1, fbctl_uncorr_err_c8, fbctl_corr_err_c8,
fbctl_bsc_corr_err_c12, fbctl_ld64_fb_hit_c12, ev_uerr_r6,
ev_cerr_r6, rdmard_uerr_c12, rdmard_cerr_c12, error_status_vec,
error_status_veu, store_err_c8, arbdp_async_bit_c8, str_ld_hit_c7
);
input arbctl_csr_wr_en_c7;
input [2:0] arbdp_word_addr_c6;
input rclk;
input si, se;
input rst_tri_en;
// from vuaddp
input vuad_error_c8; // from vuad dp.
// from arbctl.
input dir_error_c8 ; // from the directory
// from decc_ctl.v
input decc_spcd_corr_err_c8 ; // error in 156 bit data
input decc_spcd_uncorr_err_c8 ; // error in 156 bit data
input decc_scrd_corr_err_c8 ;// error in 156 bit data
input decc_scrd_uncorr_err_c8 ;// error in 156 bit data
input decc_spcfb_corr_err_c8 ; // error in 156 bit data or error
input decc_spcfb_uncorr_err_c8 ; // error in 156 bit data or error
input decc_bscd_corr_err_c8; // error in 156 bit data ( for WR8s)
input decc_bscd_uncorr_err_c8; // error in 156 bit data ( for WR8s)
// from tagdp.v
input tag_error_c8;
input data_ecc_active_c3 ; // POST_4.2 ( Right)
output fbctl_decc_scrd_corr_err_c8; // POST_4.2 ( Top)
output fbctl_decc_scrd_uncorr_err_c8; // POST_4.2 ( Top)
output mbctl_decc_spcfb_corr_err_c8; // POST_4.2 (Top)
output mbctl_decc_spcd_corr_err_c8 ; // POST_4.2 (Top)
output fbctl_decc_bscd_corr_err_c8; // POST_4.2 ( Top)
output fbctl_decc_bscd_uncorr_err_c8; // POST_4.2 ( Top)
output arbctl_data_ecc_active_c3; // POST_4.2 ( Top)
output decc_data_ecc_active_c3; // POST_4.2 ( Top)
input l2_dir_map_on; // POST_4.2 ( Left)
output tagdp_l2_dir_map_on; // POST_4.2 ( Left/Bottom)
output mbctl_l2_dir_map_on; // POST_4.2 ( Top)
output fbctl_l2_dir_map_on; // POST_4.2 ( Top)
input dbginit_l ; // POST_4.2 Bottom
output arbctl_dbginit_l ; // POST_4.2 TOp
output mbctl_dbginit_l ; // POST_4.2 Top
output fbctl_dbginit_l ; // POST_4.2 Top
output tagctl_dbginit_l ; // POST_4.2 Top
output tagdp_ctl_dbginit_l ; // POST_4.2 Left
output csr_dbginit_l ; // POST_4.2 Left
output wbctl_dbginit_l ; // POST_4.2 Top
// from fbctl.v
input dram_scb_secc_err_d1; // scrub error from DRAM
input dram_scb_mecc_err_d1; // scrub error from DRAM
input fbctl_uncorr_err_c8 ; // Errors from DRAM in response to a read
input fbctl_corr_err_c8 ; // Errors from DRAM in response to a read
input fbctl_bsc_corr_err_c12; // Errors from DRAM in response to a rd64 miss.
input fbctl_ld64_fb_hit_c12; // qualification for errors found in
// rdma rd stream out data path.
// from rdmatctl.v
input ev_uerr_r6;// wb errors from the evict dp.
input ev_cerr_r6;// wb errors from the evict dp.
input rdmard_uerr_c12;
input rdmard_cerr_c12;
// from csr
input error_status_vec;
input error_status_veu;
// from arbdec
input store_err_c8;
input arbdp_async_bit_c8; // ADDED POST_4.0
input str_ld_hit_c7; // from oqctl.
// csr_ctl
output so;
output csr_ctl_wr_en_c8 ;
output csr_erren_wr_en_c8;
output csr_errstate_wr_en_c8;
output csr_errinj_wr_en_c8;
//output csr_stm_wr_en_c8; // REMOVED POST_4.0
// 21 control bits in Status register.
output err_state_in_rw ;
output err_state_in_mec ;
output err_state_in_meu ;
output [`ERR_LDAC:`ERR_VEU] err_state_in ;
output csr_synd_wr_en;
output [1:0] mux1_synd_sel;
output [1:0] mux2_synd_sel;
output wr_enable_tid_c9;
output csr_tid_wr_en;
output csr_async_wr_en;
// output wr_enable_async_c9; REMOVED POST_4.0
output set_async_c9 ; // ADDED POST_4.0
output error_rw_en ; // ADDED POST_4.0
output diag_wr_en; // ADDED POST_4.0
output [3:0] mux1_addr_sel;
output [2:0] mux2_addr_sel;
output csr_addr_wr_en;
// output csr_erraddr_wr_en_c8; // REMOVED POST_4.0
// read enables.
output [3:0] csr_rd_mux1_sel_c7;
output csr_rd_mux2_sel_c7;
output [1:0] csr_rd_mux3_sel_c7;
// these outputs need to be removed.
output sctag_por_req; // POST_4.2
output csr_bist_wr_en_c8; // POST_2.0
wire control_reg_write_en, control_reg_write_en_d1;
wire erren_reg_write_en, erren_reg_write_en_d1;
wire errst_reg_write_en, errst_reg_write_en_d1;
wire erraddr_reg_write_en, erraddr_reg_write_en_d1;
wire errinj_reg_write_en, errinj_reg_write_en_d1;
//wire stm_reg_write_en, stm_reg_write_en_d1;
wire [2:0] word_addr_c7;
wire [2:0] mux1_sel_c6, mux1_sel_c7;
wire [63:0] err_status_in;
wire [63:0] err_state_new_c9;
wire [63:0] err_state_new_c8;
wire [7:0] new_uerr_vec_c9 ;
wire [7:0] wr_uerr_vec_c9 ;
wire [6:0] new_cerr_vec_c9 ;
wire [6:0] wr_cerr_vec_c9 ;
wire rdma_pst_err_c9;
wire store_error_c9 ;
wire rdmard_uerr_c13, rdmard_cerr_c13 ;
wire str_ld_hit_c8, str_ld_hit_c9 ;
wire err_sel, new_err_sel;
wire rdmard_addr_sel_c13;
wire bsc_corr_err_c13;
wire en_por_c7, en_por_c7_d1;
wire bist_reg_write_en, bist_reg_write_en_d1;
wire [3:0] mux1_addr_sel_tmp;
wire [2:0] mux2_addr_sel_tmp ;
wire pipe_addr_sel;
wire bscd_uncorr_err_c9, bscd_corr_err_c9 ;
wire csr_erraddr_wr_en_c8;
wire async_bit_c9, wr_enable_async_c9;
wire error_spc, error_bsc ;
// --------------\/------- Added repeaters post_4.2 ---\/ --------
assign arbctl_dbginit_l = dbginit_l ;
assign mbctl_dbginit_l = dbginit_l ;
assign fbctl_dbginit_l = dbginit_l ;
assign wbctl_dbginit_l = dbginit_l ;
assign csr_dbginit_l = dbginit_l ;
assign tagctl_dbginit_l = dbginit_l ;
assign tagdp_ctl_dbginit_l = dbginit_l ;
//decc_spcd_uncorr_err_c8 repeater not needed.
//decc_spcfb_corr_err_c8 repeater not needed.
assign fbctl_decc_scrd_corr_err_c8 = decc_scrd_corr_err_c8;
assign fbctl_decc_scrd_uncorr_err_c8 = decc_scrd_uncorr_err_c8 ;
assign fbctl_decc_bscd_corr_err_c8 = decc_bscd_corr_err_c8 ;
assign fbctl_decc_bscd_uncorr_err_c8 = decc_bscd_uncorr_err_c8 ;
assign mbctl_decc_spcd_corr_err_c8 = decc_spcd_corr_err_c8 ;
assign mbctl_decc_spcfb_corr_err_c8 = decc_spcfb_corr_err_c8 ;
assign arbctl_data_ecc_active_c3 = data_ecc_active_c3 ;
assign decc_data_ecc_active_c3 = data_ecc_active_c3 ;
assign tagdp_l2_dir_map_on = l2_dir_map_on ;
assign mbctl_l2_dir_map_on = l2_dir_map_on ;
assign fbctl_l2_dir_map_on = l2_dir_map_on ;
// --------------\/------- Added repeaters post_4.2 ---\/ --------
/////////////////////////////////////////////////////
// Exception cases:
//
// - Wr8s will cause DAU to be set in OFF mode. ( if an uncorr err
// is signalled by DRAM).
// - Wr8 will cause DAC to be set. in OFF/ON mode.
/////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// CSR pipeline.
//
//============================================================
// C7 C8 C9
//============================================================
// generate mux out xmit
// mux selects rd data to
// ccx
//
// enable
// a write
//
//============================================================
//
// Eventhough the Write and Read operations do not happen in the
// same cycle, no data forwarding is required because the write
// is followed by ATLEAST one bubble
//
// Errors update the ESR and EAR in the C10 cycle.
// Hence a CSR load may actually miss the error that occurred
// just before it.
////////////////////////////////////////////////////////////////////////////////
//////////////////////////
// I) WR ENABLE GENERATION
//
// Write pipeline.
// A CSR store is performed
// in the C8 cycle.
//////////////////////////
dff_s #(3) ff_word_addr_c7 (.din(arbdp_word_addr_c6[2:0]),
.clk(rclk),
.q(word_addr_c7[2:0]),
.se(se), .si(), .so());
//////////////////////////
// BIST REG A8
// This register can be written by software or
// by JTAG via the CTU
//////////////////////////
assign bist_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h0 ) ; // A8
dff_s #(1) ff_bist_reg_write_en_d1 (.din(bist_reg_write_en),
.clk(rclk),
.q(bist_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_bist_wr_en_c8 = bist_reg_write_en_d1 ;
//////////////////////////
// CONTROL REG A9
//////////////////////////
assign control_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h1 ) ; // A9
dff_s #(1) ff_control_reg_write_en_d1 (.din(control_reg_write_en),
.clk(rclk),
.q(control_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_ctl_wr_en_c8 = control_reg_write_en_d1 ;
//////////////////////////
// ERR ENABLE REG AA
//////////////////////////
assign erren_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h2) ; // AA
dff_s #(1) ff_erren_reg_write_en_d1 (.din(erren_reg_write_en),
.clk(rclk),
.q(erren_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_erren_wr_en_c8 = erren_reg_write_en_d1 ;
//////////////////////////
// ERR STATE REG AB
//////////////////////////
assign errst_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h3) ; // AB
dff_s #(1) ff_errst_reg_write_en_d1 (.din(errst_reg_write_en), .clk(rclk),
.q(errst_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_errstate_wr_en_c8 = errst_reg_write_en_d1 ;
//////////////////////////
// ERR ADDR REG AC
//////////////////////////
assign erraddr_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h4) ; // AC
dff_s #(1) ff_erraddr_reg_write_en_d1 (.din(erraddr_reg_write_en), .clk(rclk),
.q(erraddr_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_erraddr_wr_en_c8 = erraddr_reg_write_en_d1 ;
//////////////////////////
// ERR INJ REG AD
//////////////////////////
assign errinj_reg_write_en = arbctl_csr_wr_en_c7 &
(word_addr_c7==3'h5) ; // AD
dff_s #(1) ff_errinj_reg_write_en_d1 (.din(errinj_reg_write_en), .clk(rclk),
.q(errinj_reg_write_en_d1),
.se(se), .si(), .so());
assign csr_errinj_wr_en_c8 = errinj_reg_write_en_d1 ;
//////////////////////////
// THIS REGISTER HAS BEEN REMOVED FROM THE SPEC
// STM REG AE or AF
//////////////////////////
//assign stm_reg_write_en = arbctl_csr_wr_en_c7 &
//( (word_addr_c7==3'h6) |
//(word_addr_c7==3'h7)
//) ;
//dff #(1) ff_stm_reg_write_en_d1 (.din(stm_reg_write_en), .clk(rclk),
//.q(stm_reg_write_en_d1),
//.se(se), .si(), .so());
//
//
//assign csr_stm_wr_en_c8 = stm_reg_write_en_d1 ;
//////////////////////////
// RD enable generation.
//////////////////////////
assign mux1_sel_c6[0] = ( arbdp_word_addr_c6[1:0] == 2'd0 ) ; // A8 or Ac
assign mux1_sel_c6[1] = ( arbdp_word_addr_c6[1:0] == 2'd1 ) ; // A9 or Ad
assign mux1_sel_c6[2] = ( arbdp_word_addr_c6[1:0] == 2'd2 ) ; //Aa or Ae
dff_s #(3) ff_mux1_sel_c7 (.din(mux1_sel_c6[2:0]), .clk(rclk),
.q(mux1_sel_c7[2:0]),
.se(se), .si(), .so());
assign csr_rd_mux1_sel_c7[0] = mux1_sel_c7[0] & ~rst_tri_en ;
assign csr_rd_mux1_sel_c7[1] = mux1_sel_c7[1] & ~rst_tri_en ;
assign csr_rd_mux1_sel_c7[2] = mux1_sel_c7[2] & ~rst_tri_en ;
assign csr_rd_mux1_sel_c7[3] = ~(|(mux1_sel_c7[2:0])) | rst_tri_en;
assign csr_rd_mux2_sel_c7 = ~( mux1_sel_c7[0] |
mux1_sel_c7[1] ) | rst_tri_en ;
assign csr_rd_mux3_sel_c7[0] = ~word_addr_c7[2] ;
assign csr_rd_mux3_sel_c7[1] = word_addr_c7[2] ;
//////////////////////////
// ERROR LOGGING LOGIC.
// UNCORR ERRORS.
//////////////////////////
/////////////////////////////////////////////////////
// LVU bit
// vuad parity. Addr=C9, syndrome = parity_c9<3:0>
// set this bit, if there is no pending uncorr err.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LVU] = vuad_error_c8 ;
dff_s #(1) ff_err_state_new_c9_lvu
(.din(err_state_new_c8[`ERR_LVU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LVU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LVU] = ~error_status_veu &
err_state_new_c9[`ERR_LVU] ;
/////////////////////////////////////////////////////
// LRU bit
// dir parity. Addr=index syndrome = X
// set this bit if no lvu occurs and no pending uncorr err.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LRU] = dir_error_c8 ; // directory error
dff_s #(1) ff_err_state_new_c9_lru
(.din(err_state_new_c8[`ERR_LRU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LRU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LRU] = ~( err_state_new_c9[`ERR_LVU] |
error_status_veu ) &
err_state_new_c9[`ERR_LRU] ;
/////////////////////////////////////////////////////
// LDSU bit
// set for a scrub
// Address=C7. Syndrome = data_syndrome from decc
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDSU] = decc_scrd_uncorr_err_c8 ; // scrub uncorr err
dff_s #(1) ff_err_state_new_c9_ldsu
(.din(err_state_new_c8[`ERR_LDSU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDSU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDSU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDSU] ;
/////////////////////////////////////////////////////
// LDAU bit
// set for any kind of access LD/ST/ATOMIC/PST
// Address=C9. Syndrome = data_syndrome from decc
// Only set for accesses that hit the $
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDAU] = decc_spcd_uncorr_err_c8 ; // data uncorr err
dff_s #(1) ff_err_state_new_c9_ldau
(.din(err_state_new_c8[`ERR_LDAU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDAU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDAU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDAU] ;
/////////////////////////////////////////////////////
// LDWU bit
// eviction error logging done in cycles r7 through r14
// of an evict. Address logging is also done in the
// same 8 cycle window
// ??? may need to change leave_state2 counter to 13
// in wbctl.v
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDWU] = ev_uerr_r6 ; // eviction uncorr err
dff_s #(1) ff_err_state_new_c9_ldwu
(.din(err_state_new_c8[`ERR_LDWU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDWU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDWU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDSU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDWU] ;
/////////////////////////////////////////////////////
// LDRU bit
// Set for an RDMA Read or an RDMA Write ( Partial )
// or RDMA Write which
// returns with an error from the DRAM.
// Only set for accesses that hit the $
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDRU] = decc_bscd_uncorr_err_c8 |
( rdmard_uerr_c12 &
~fbctl_ld64_fb_hit_c12 ) ;
dff_s #(1) ff_err_state_new_c9_ldru
(.din(err_state_new_c8[`ERR_LDRU]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDRU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDRU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDSU] |
err_state_new_c9[`ERR_LDWU] |
error_status_veu ) &
err_state_new_c9[`ERR_LDRU] ;
/////////////////////////////////////////////////////
// DRU bit
// FB hit only for LD64/
// Wr8s will cause DAU to be set in OFF mode.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DRU] =
( rdmard_uerr_c12 &
fbctl_ld64_fb_hit_c12) ;
dff_s #(1) ff_err_state_new_c9_dru
(.din(err_state_new_c8[`ERR_DRU]), .clk(rclk),
.q(err_state_new_c9[`ERR_DRU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DRU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDSU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDWU] |
error_status_veu) &
err_state_new_c9[`ERR_DRU] ;
/////////////////////////////////////////////////////
// DAU bit
// only set for a FB hit or a FILL
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DAU] =
( decc_spcfb_uncorr_err_c8 | // from a spc instruction
fbctl_uncorr_err_c8 ) ; // from a fill.
dff_s #(1) ff_err_state_new_c9_dau
(.din(err_state_new_c8[`ERR_DAU]), .clk(rclk),
.q(err_state_new_c9[`ERR_DAU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DAU] = ~( err_state_new_c9[`ERR_LVU] |
err_state_new_c9[`ERR_LRU] |
err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDSU] |
err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDWU] |
err_state_new_c9[`ERR_DRU] |
error_status_veu ) &
err_state_new_c9[`ERR_DAU] ;
/////////////////////////////////////////////////////
// DSU bit
// This bit does not influence MEU
// and does not need to go through the
// priority logic
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DSU] = dram_scb_mecc_err_d1 ;
// scrub in DRAM causing an error.
dff_s #(1) ff_err_state_new_c9_dsu
(.din(err_state_new_c8[`ERR_DSU]), .clk(rclk),
.q(err_state_new_c9[`ERR_DSU]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DSU] = err_state_new_c9[`ERR_DSU] ;
/////////////////////////////////////////////////////
// MEU bit
// Multiple error uncorrectable bit is set if multiple
// uncorrectable errors happen in the same cycle or
// are separated in time.
// This bit is set if the vector being written in
// is different from the vector that is detected
/////////////////////////////////////////////////////
assign new_uerr_vec_c9 = { err_state_new_c9[`ERR_LDAU],
err_state_new_c9[`ERR_LDWU],
err_state_new_c9[`ERR_LDRU],
err_state_new_c9[`ERR_LDSU],
err_state_new_c9[`ERR_LRU],
err_state_new_c9[`ERR_LVU],
err_state_new_c9[`ERR_DAU],
err_state_new_c9[`ERR_DRU] } ;
// atleast 10 gates to do the priority.
assign wr_uerr_vec_c9 = { err_status_in[`ERR_LDAU],
err_status_in[`ERR_LDWU],
err_status_in[`ERR_LDRU],
err_status_in[`ERR_LDSU],
err_status_in[`ERR_LRU],
err_status_in[`ERR_LVU],
err_status_in[`ERR_DAU],
err_status_in[`ERR_DRU] } ;
assign err_status_in[`ERR_MEU] = |( ~wr_uerr_vec_c9 & new_uerr_vec_c9 ) ;
/////////////////////////////////////////////////////
// VEU bit
/////////////////////////////////////////////////////
assign err_status_in[`ERR_VEU] = |(new_uerr_vec_c9) ;
/////////////////////////////////////////////////////
// ERROR LOGGING LOGIC.
// CORR ERRORS.
// correctible errors are logged if
// * there is no uncorr err in the same cycle.
// * there is no pending corr or uncorr err.
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// LTC bit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LTC] = tag_error_c8 ;
dff_s #(1) ff_err_state_new_c9_ltc
(.din(err_state_new_c8[`ERR_LTC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LTC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LTC] = ~( err_status_in[`ERR_VEU] |
& error_status_veu |
error_status_vec ) &
err_state_new_c9[`ERR_LTC] ;
/////////////////////////////////////////////////////
// LDSC bit
// addr=C9 and syndrome = data synd.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDSC] = decc_scrd_corr_err_c8 ;
dff_s #(1) ff_err_state_new_c9_ldsc
(.din(err_state_new_c8[`ERR_LDSC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDSC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDSC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] ) &
err_state_new_c9[`ERR_LDSC] ; // LDAC and LDSC are mutex
/////////////////////////////////////////////////////
// LDAC bit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDAC] = decc_spcd_corr_err_c8 ;
dff_s #(1) ff_err_state_new_c9_ldac
(.din(err_state_new_c8[`ERR_LDAC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDAC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDAC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] ) &
err_state_new_c9[`ERR_LDAC] ;
/////////////////////////////////////////////////////
// LDWC bit
// comes from a Wback
// addr = evicted address and syndrome = datasyndrome.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDWC] = ev_cerr_r6 ;
dff_s #(1) ff_err_state_new_c9_ldwc
(.din(err_state_new_c8[`ERR_LDWC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDWC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDWC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDAC] ) &
err_state_new_c9[`ERR_LDWC] ; // LDAC and LDSC are mutex
/////////////////////////////////////////////////////
// LDRC bit
// comes from an RDMA Read access and
// only for a $ hit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_LDRC] = decc_bscd_corr_err_c8 |
( rdmard_cerr_c12 &
~fbctl_ld64_fb_hit_c12 ) ;
dff_s #(1) ff_err_state_new_c9_ldrc
(.din(err_state_new_c8[`ERR_LDRC]), .clk(rclk),
.q(err_state_new_c9[`ERR_LDRC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_LDRC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDWC] |
err_state_new_c9[`ERR_LDAC] ) &
err_state_new_c9[`ERR_LDRC] ;
/////////////////////////////////////////////////////
// DRC bit
// ld 64 will cause DRC to be set.
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DRC] = fbctl_bsc_corr_err_c12 ;
dff_s #(1) ff_err_state_new_c9_drc
(.din(err_state_new_c8[`ERR_DRC]), .clk(rclk),
.q(err_state_new_c9[`ERR_DRC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DRC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDAC] |
err_state_new_c9[`ERR_LDWC] |
err_state_new_c9[`ERR_LDRC]
) &
err_state_new_c9[`ERR_DRC];
/////////////////////////////////////////////////////
// DAC bit
// Only an fb hit or a fill
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DAC] = ( decc_spcfb_corr_err_c8 |
fbctl_corr_err_c8 ) ;
dff_s #(1) ff_err_state_new_c9_dac
(.din(err_state_new_c8[`ERR_DAC]), .clk(rclk),
.q(err_state_new_c9[`ERR_DAC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DAC] = ~( err_status_in[`ERR_VEU] |
error_status_veu |
error_status_vec |
err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDSC] |
err_state_new_c9[`ERR_LDAC] |
err_state_new_c9[`ERR_LDWC] |
err_state_new_c9[`ERR_LDRC] |
err_state_new_c9[`ERR_DRC]
) &
err_state_new_c9[`ERR_DAC];
/////////////////////////////////////////////////////
// DSC bit
/////////////////////////////////////////////////////
assign err_state_new_c8[`ERR_DSC] = dram_scb_secc_err_d1 ;
dff_s #(1) ff_err_state_new_c9_dsc
(.din(err_state_new_c8[`ERR_DSC]), .clk(rclk),
.q(err_state_new_c9[`ERR_DSC]),
.se(se), .si(), .so());
assign err_status_in[`ERR_DSC] = err_state_new_c9[`ERR_DSC] ;
/////////////////////////////////////////////////////
// MEC bit
// set if the corr err detected is unable to record in the L2 esr
// OR if an uncorrectable err happens when a corr err has already occurred.
/////////////////////////////////////////////////////
assign wr_cerr_vec_c9 = { err_status_in[`ERR_LTC],
err_status_in[`ERR_LDAC],
err_status_in[`ERR_LDRC],
err_status_in[`ERR_LDWC],
err_status_in[`ERR_LDSC],
err_status_in[`ERR_DAC],
err_status_in[`ERR_DRC] } ;
assign new_cerr_vec_c9 = { err_state_new_c9[`ERR_LTC],
err_state_new_c9[`ERR_LDAC],
err_state_new_c9[`ERR_LDRC],
err_state_new_c9[`ERR_LDWC],
err_state_new_c9[`ERR_LDSC],
err_state_new_c9[`ERR_DAC],
err_state_new_c9[`ERR_DRC] } ;
assign err_status_in[`ERR_MEC] = (|( ~wr_cerr_vec_c9 & new_cerr_vec_c9 )) |
( err_status_in[`ERR_VEU] & error_status_vec ) ;
/////////////////////////////////////////////////////
// VEC bit
/////////////////////////////////////////////////////
assign err_status_in[`ERR_VEC] = |( new_cerr_vec_c9 ) ;
/////////////////////////////////////////////////////
// RW bit
// 1 for a write access
// Set to 1 for Stores, strm stores, CAs, SWAP, LDSTUB
// or rdma psts that encounter an error.
/////////////////////////////////////////////////////
assign rdma_pst_err_c9 = bscd_uncorr_err_c9 | bscd_corr_err_c9 ;
dff_s #(1) ff_store_error_c9
(.din(store_err_c8), .clk(rclk),
.q(store_error_c9),
.se(se), .si(), .so());
assign error_spc = ( err_status_in[`ERR_LDAU] | err_status_in[`ERR_LDAC] |
err_status_in[`ERR_DAU] | err_status_in[`ERR_DAC]) ;
assign error_bsc = ( err_status_in[`ERR_LDRU] | err_status_in[`ERR_LDRC] |
err_status_in[`ERR_DRU] | err_status_in[`ERR_DRC] );
assign err_status_in[`ERR_RW] = ( store_error_c9 & error_spc) |
( rdma_pst_err_c9 & error_bsc &
~( rdmard_uerr_c13 | rdmard_cerr_c13 ) ) ;
assign error_rw_en = ( error_spc | error_bsc ) |
( diag_wr_en ) ;
/////////////////////////////////////////////////////
// ERROR STATUS BITS to CSR from csr_ctl.
/////////////////////////////////////////////////////
assign err_state_in_mec = err_status_in[`ERR_MEC];
assign err_state_in_meu = err_status_in[`ERR_MEU];
assign err_state_in_rw = err_status_in[`ERR_RW];
assign err_state_in[`ERR_LDAC:`ERR_VEU] = err_status_in[`ERR_LDAC:`ERR_VEU] ;
/////////////////////////////////////////////////////
// SYNDROME
// recorded for
// * vuad errors
// * ldac/ldau
// * ldrc/ldru for rdma writes only.
/////////////////////////////////////////////////////
dff_s #(1) ff_rdmard_uerr_c13
(.din(rdmard_uerr_c12), .clk(rclk),
.q(rdmard_uerr_c13),
.se(1'b0), .si(), .so());
dff_s #(1) ff_rdmard_cerr_c13
(.din(rdmard_cerr_c12), .clk(rclk),
.q(rdmard_cerr_c13),
.se(1'b0), .si(), .so());
assign mux1_synd_sel[0] = err_status_in[`ERR_LVU];
assign mux1_synd_sel[1] = ~err_status_in[`ERR_LVU];
assign mux2_synd_sel[0] = ((err_state_new_c9[`ERR_LDAU] |
err_state_new_c9[`ERR_LDAC]) |
(( err_state_new_c9[`ERR_LDRU] |
err_state_new_c9[`ERR_LDRC] ) &
~( rdmard_uerr_c13 | rdmard_cerr_c13 ))
) ;
assign mux2_synd_sel[1] = ~mux2_synd_sel[0] ;
assign csr_synd_wr_en = diag_wr_en |
( new_err_sel & ( mux1_synd_sel[0] | mux2_synd_sel[0] )) ;
/////////////////////////////////////////////////////
// TID
// reported for
// * ldac/ldau errors
// * dac/dau errors when they are
// detected/reported by an instruction other than a FILL
/////////////////////////////////////////////////////
assign wr_enable_tid_c9 = ( err_status_in[`ERR_LDAC] |
err_status_in[`ERR_LDAU] |
err_status_in[`ERR_DAC] |
err_status_in[`ERR_DAU] ) ;
assign csr_tid_wr_en = ( wr_enable_tid_c9 | diag_wr_en ) ;
/////////////////////////////////////////////////////
// ASYNC
// reported for only ldac/ldau errors.
/////////////////////////////////////////////////////
dff_s #(1) ff_str_ld_hit_c8 (.din(str_ld_hit_c7), .clk(rclk),
.q(str_ld_hit_c8),
.se(1'b0), .si(), .so());
dff_s #(1) ff_str_ld_hit_c9 (.din(str_ld_hit_c8), .clk(rclk),
.q(str_ld_hit_c9),
.se(1'b0), .si(), .so());
dff_s #(1) ff_async_bit_c9 (.q(async_bit_c9), .clk(rclk),
.din(arbdp_async_bit_c8),
.se(se), .si(), .so());
assign wr_enable_async_c9 = (err_status_in[`ERR_LDAC] |
err_status_in[`ERR_DAC] |
err_status_in[`ERR_DAU] |
err_status_in[`ERR_LDAU] ) ;
assign set_async_c9 = str_ld_hit_c9 & async_bit_c9 ;
assign csr_async_wr_en = ( wr_enable_async_c9 |
diag_wr_en ) ;
/////////////////////////////////////////////////////
// ADDRESS PRIORITIES
/////////////////////////////////////////////////////
//
// 1. LVU pipe-addr
// 2. LRU dir_addr
// 3a. LDSU scrub addr
// 3b. LDAU pipe_addr.
// 4. LDWU evict_addr
// 5a. LDRU rdma rd addr.
// 5b. LDRU pipe_addr.
// 6a. DRU rdma rd addr.
// 6b. DRU pipe addr
// 6c. DAU pipe_addr
// 7. LTC pipe_addr
// 8a. LDSC scrub addr.
// 8b. LDAC pipe_addr
// 9. LDWC evict_addr
// 10a. LDRC rdma rd addr.
// 10b. LDRC pipe_addr.
// 11a DRC rdma rd addr.
// 11b DRC pipe addr
// 11c DAC pipe_addr.
/////////////////////////////////////////////////////
dff_s #(1) ff_bscd_uncorr_err_c9
(.din(decc_bscd_uncorr_err_c8), .clk(rclk),
.q(bscd_uncorr_err_c9),
.se(se), .si(), .so());
dff_s #(1) ff_bscd_corr_err_c9
(.din(decc_bscd_corr_err_c8), .clk(rclk),
.q(bscd_corr_err_c9),
.se(se), .si(), .so());
dff_s #(1) ff_bsc_corr_err_c13
(.din(fbctl_bsc_corr_err_c12), .clk(rclk),
.q(bsc_corr_err_c13),
.se(1'b0), .si(), .so());
assign mux1_addr_sel_tmp[0] = err_state_new_c9[`ERR_LRU] ; // sel dir addr.
assign mux1_addr_sel_tmp[1] =
(( err_state_new_c9[`ERR_LDSU] & ~err_state_new_c9[`ERR_LRU] ) |
( err_state_new_c9[`ERR_LDSC] & ~err_status_in[`ERR_VEU]) ) ; // scrub addr.
assign mux1_addr_sel_tmp[2] = (( err_state_new_c9[`ERR_LDWU] & ~err_state_new_c9[`ERR_LDSU]
& ~err_state_new_c9[`ERR_LRU] ) |
( err_state_new_c9[`ERR_LDWC] &
~err_status_in[`ERR_VEU] &
~err_state_new_c9[`ERR_LDSC]) ) ; // evict addr.
assign mux1_addr_sel_tmp[3] = ~|(mux1_addr_sel_tmp[2:0]);
assign mux1_addr_sel[0] = mux1_addr_sel_tmp[0] & ~rst_tri_en ;
assign mux1_addr_sel[1] = mux1_addr_sel_tmp[1] & ~rst_tri_en ;
assign mux1_addr_sel[2] = mux1_addr_sel_tmp[2] & ~rst_tri_en ;
assign mux1_addr_sel[3] = ( mux1_addr_sel_tmp[3] | rst_tri_en ) ;
assign err_sel = ( err_status_in[`ERR_VEC] |
err_status_in[`ERR_VEU] ) ;
assign diag_wr_en = csr_errstate_wr_en_c8 & ~err_sel ;
assign rdmard_addr_sel_c13 = ( (err_state_new_c9[`ERR_LDRU] | err_state_new_c9[`ERR_DRU] ) |
(( err_state_new_c9[`ERR_LDRC] | err_state_new_c9[`ERR_DRC])
& ~err_status_in[`ERR_VEU])) &
(rdmard_uerr_c13 |
rdmard_cerr_c13 |
bsc_corr_err_c13 ); // rdma rd addr only
// Fix for bug#4375
// when an error is detected in a rdma rd and a wr8 in the same cycle,
// the wr8 address is discarded and the rdma rd address is selected.
// the pipe_addr_sel expression needed appropriate qualifications with
// rdmard_uerr_c13 & ( rdmard_cerr_c13 | bsc_corr_err_c13 )
assign pipe_addr_sel = ( err_state_new_c9[`ERR_LVU] |
(~err_state_new_c9[`ERR_LRU] & err_state_new_c9[`ERR_LDAU] ) |
(~err_state_new_c9[`ERR_LRU] & ~err_state_new_c9[`ERR_LDWU] & bscd_uncorr_err_c9 & ~rdmard_uerr_c13)) |
(~err_status_in[`ERR_VEU] &
(err_state_new_c9[`ERR_LTC] |
err_state_new_c9[`ERR_LDAC] |
( bscd_corr_err_c9 & ~err_state_new_c9[`ERR_LDWC] & ~rdmard_cerr_c13 & ~bsc_corr_err_c13 ))
); // pipe addr only
assign mux2_addr_sel_tmp[0] = ( rdmard_addr_sel_c13 |
(|(mux1_addr_sel_tmp[2:0])) ) &
~pipe_addr_sel ; // sel mux1
// if err
// or rdma rd
assign mux2_addr_sel_tmp[1] = err_sel & ~mux2_addr_sel_tmp[0] ; // sel pipe addr
// a9
assign mux2_addr_sel_tmp[2] = ~(mux2_addr_sel_tmp[1] | mux2_addr_sel_tmp[0] ) ;
// sel wr data.
assign mux2_addr_sel[0] = mux2_addr_sel_tmp[0] & ~rst_tri_en ;
assign mux2_addr_sel[1] = mux2_addr_sel_tmp[1] & ~rst_tri_en ;
assign mux2_addr_sel[2] = ( mux2_addr_sel_tmp[2] | rst_tri_en ) ;
assign new_err_sel = |(wr_uerr_vec_c9) | (|(wr_cerr_vec_c9) ) ;
// An error gets priority to write into the EAR if an error
// and a diagnostic write try to update the EAR in the same cycle.
// Bug #3986.
// err_addr_sel indicates that an error occurred. In this case,
// any diagnostic write is disabled.
assign csr_addr_wr_en = ( csr_erraddr_wr_en_c8 & ~err_sel ) | new_err_sel ;
/////////////////////////////////////////////////////
// POR signalled for LVU/LRU
// PMB requires reset assertion for 6 cycles.
// The following signal is not a C8 signal but
// that is the name it has been given.
//
// This request is conditioned in JBI with an enable bit
// before actually causing a POR.
/////////////////////////////////////////////////////
assign en_por_c7 = ( err_state_new_c9[`ERR_LVU] | err_state_new_c9[`ERR_LRU] ) ;
dff_s #(1) ff_en_por_c7_d1 (.din(en_por_c7), .clk(rclk),
.q(en_por_c7_d1),
.se(1'b0), .si(), .so());
assign sctag_por_req = en_por_c7_d1 ;
endmodule
|
/*
-- ============================================================================
-- FILE NAME : decoder.v
-- DESCRIPTION : ½ßfR[_
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module decoder (
/********** IF/IDpCvCWX^ **********/
input wire [`WordAddrBus] if_pc, // vOJE^
input wire [`WordDataBus] if_insn, // ½ß
input wire if_en, // pCvCf[^ÌLø
/********** GPRC^tF[X **********/
input wire [`WordDataBus] gpr_rd_data_0, // ÇÝoµf[^ 0
input wire [`WordDataBus] gpr_rd_data_1, // ÇÝoµf[^ 1
output wire [`RegAddrBus] gpr_rd_addr_0, // ÇÝoµAhX 0
output wire [`RegAddrBus] gpr_rd_addr_1, // ÇÝoµAhX 1
/********** tH[fBO **********/
// IDXe[W©çÌtH[fBO
input wire id_en, // pCvCf[^ÌLø
input wire [`RegAddrBus] id_dst_addr, // «ÝAhX
input wire id_gpr_we_, // «ÝLø
input wire [`MemOpBus] id_mem_op, // Iy[V
// EXXe[W©çÌtH[fBO
input wire ex_en, // pCvCf[^ÌLø
input wire [`RegAddrBus] ex_dst_addr, // «ÝAhX
input wire ex_gpr_we_, // «ÝLø
input wire [`WordDataBus] ex_fwd_data, // tH[fBOf[^
// MEMXe[W©çÌtH[fBO
input wire [`WordDataBus] mem_fwd_data, // tH[fBOf[^
/********** §äWX^C^tF[X **********/
input wire [`CpuExeModeBus] exe_mode, // Às[h
input wire [`WordDataBus] creg_rd_data, // ÇÝoµf[^
output wire [`RegAddrBus] creg_rd_addr, // ÇÝoµAhX
/********** fR[hÊ **********/
output reg [`AluOpBus] alu_op, // ALUIy[V
output reg [`WordDataBus] alu_in_0, // ALUüÍ 0
output reg [`WordDataBus] alu_in_1, // ALUüÍ 1
output reg [`WordAddrBus] br_addr, // ªòAhX
output reg br_taken, // ªò̬§
output reg br_flag, // ªòtO
output reg [`MemOpBus] mem_op, // Iy[V
output wire [`WordDataBus] mem_wr_data, // «Ýf[^
output reg [`CtrlOpBus] ctrl_op, // §äIy[V
output reg [`RegAddrBus] dst_addr, // ÄpWX^«ÝAhX
output reg gpr_we_, // ÄpWX^«ÝLø
output reg [`IsaExpBus] exp_code, // áOR[h
output reg ld_hazard // [hnU[h
);
/********** ½ßtB[h **********/
wire [`IsaOpBus] op = if_insn[`IsaOpLoc]; // IyR[h
wire [`RegAddrBus] ra_addr = if_insn[`IsaRaAddrLoc]; // RaAhX
wire [`RegAddrBus] rb_addr = if_insn[`IsaRbAddrLoc]; // RbAhX
wire [`RegAddrBus] rc_addr = if_insn[`IsaRcAddrLoc]; // RcAhX
wire [`IsaImmBus] imm = if_insn[`IsaImmLoc]; // ¦l
/********** ¦l **********/
// g£
wire [`WordDataBus] imm_s = {{`ISA_EXT_W{imm[`ISA_IMM_MSB]}}, imm};
// [g£
wire [`WordDataBus] imm_u = {{`ISA_EXT_W{1'b0}}, imm};
/********** WX^ÌÇÝoµAhX **********/
assign gpr_rd_addr_0 = ra_addr; // ÄpWX^ÇÝoµAhX 0
assign gpr_rd_addr_1 = rb_addr; // ÄpWX^ÇÝoµAhX 1
assign creg_rd_addr = ra_addr; // §äWX^ÇÝoµAhX
/********** ÄpWX^ÌÇÝoµf[^ **********/
reg [`WordDataBus] ra_data; // ȵRa
wire signed [`WordDataBus] s_ra_data = $signed(ra_data); // t«Ra
reg [`WordDataBus] rb_data; // ȵRb
wire signed [`WordDataBus] s_rb_data = $signed(rb_data); // t«Rb
assign mem_wr_data = rb_data; // «Ýf[^
/********** AhX **********/
wire [`WordAddrBus] ret_addr = if_pc + 1'b1; // ßèÔn
wire [`WordAddrBus] br_target = if_pc + imm_s[`WORD_ADDR_MSB:0]; // ªòæ
wire [`WordAddrBus] jr_target = ra_data[`WordAddrLoc]; // Wvæ
/********** tH[fBO **********/
always @(*) begin
/* RaWX^ */
if ((id_en == `ENABLE) && (id_gpr_we_ == `ENABLE_) &&
(id_dst_addr == ra_addr)) begin
ra_data = ex_fwd_data; // EXXe[W©çÌtH[fBO
end else if ((ex_en == `ENABLE) && (ex_gpr_we_ == `ENABLE_) &&
(ex_dst_addr == ra_addr)) begin
ra_data = mem_fwd_data; // MEMXe[W©çÌtH[fBO
end else begin
ra_data = gpr_rd_data_0; // WX^t@C©çÌÇÝoµ
end
/* RbWX^ */
if ((id_en == `ENABLE) && (id_gpr_we_ == `ENABLE_) &&
(id_dst_addr == rb_addr)) begin
rb_data = ex_fwd_data; // EXXe[W©çÌtH[fBO
end else if ((ex_en == `ENABLE) && (ex_gpr_we_ == `ENABLE_) &&
(ex_dst_addr == rb_addr)) begin
rb_data = mem_fwd_data; // MEMXe[W©çÌtH[fBO
end else begin
rb_data = gpr_rd_data_1; // WX^t@C©çÌÇÝoµ
end
end
/********** [hnU[hÌo **********/
always @(*) begin
if ((id_en == `ENABLE) && (id_mem_op == `MEM_OP_LDW) &&
((id_dst_addr == ra_addr) || (id_dst_addr == rb_addr))) begin
ld_hazard = `ENABLE; // [hnU[h
end else begin
ld_hazard = `DISABLE; // nU[hȵ
end
end
/********** ½ßÌfR[h **********/
always @(*) begin
/* ftHgl */
alu_op = `ALU_OP_NOP;
alu_in_0 = ra_data;
alu_in_1 = rb_data;
br_taken = `DISABLE;
br_flag = `DISABLE;
br_addr = {`WORD_ADDR_W{1'b0}};
mem_op = `MEM_OP_NOP;
ctrl_op = `CTRL_OP_NOP;
dst_addr = rb_addr;
gpr_we_ = `DISABLE_;
exp_code = `ISA_EXP_NO_EXP;
/* IyR[hÌ»è */
if (if_en == `ENABLE) begin
case (op)
/* _Z½ß */
`ISA_OP_ANDR : begin // WX^¯mÌ_Ï
alu_op = `ALU_OP_AND;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ANDI : begin // WX^ƦlÌ_Ï
alu_op = `ALU_OP_AND;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ORR : begin // WX^¯mÌ_a
alu_op = `ALU_OP_OR;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ORI : begin // WX^ƦlÌ_a
alu_op = `ALU_OP_OR;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_XORR : begin // WX^¯mÌr¼I_a
alu_op = `ALU_OP_XOR;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_XORI : begin // WX^ƦlÌr¼I_a
alu_op = `ALU_OP_XOR;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
/* ZpZ½ß */
`ISA_OP_ADDSR : begin // WX^¯mÌt«ÁZ
alu_op = `ALU_OP_ADDS;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDSI : begin // WX^ƦlÌt«ÁZ
alu_op = `ALU_OP_ADDS;
alu_in_1 = imm_s;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDUR : begin // WX^¯mÌȵÁZ
alu_op = `ALU_OP_ADDU;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDUI : begin // WX^ƦlÌȵÁZ
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SUBSR : begin // WX^¯mÌt«¸Z
alu_op = `ALU_OP_SUBS;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SUBUR : begin // WX^¯mÌȵ¸Z
alu_op = `ALU_OP_SUBU;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
/* Vtg½ß */
`ISA_OP_SHRLR : begin // WX^¯mÌ_EVtg
alu_op = `ALU_OP_SHRL;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHRLI : begin // WX^ƦlÌ_EVtg
alu_op = `ALU_OP_SHRL;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHLLR : begin // WX^¯mÌ_¶Vtg
alu_op = `ALU_OP_SHLL;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHLLI : begin // WX^ƦlÌ_¶Vtg
alu_op = `ALU_OP_SHLL;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
/* ªò½ß */
`ISA_OP_BE : begin // WX^¯mÌt«äriRa == Rbj
br_addr = br_target;
br_taken = (ra_data == rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BNE : begin // WX^¯mÌt«äriRa != Rbj
br_addr = br_target;
br_taken = (ra_data != rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BSGT : begin // WX^¯mÌt«äriRa < Rbj
br_addr = br_target;
br_taken = (s_ra_data < s_rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BUGT : begin // WX^¯mÌȵäriRa < Rbj
br_addr = br_target;
br_taken = (ra_data < rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_JMP : begin // ³ðªò
br_addr = jr_target;
br_taken = `ENABLE;
br_flag = `ENABLE;
end
`ISA_OP_CALL : begin // R[
alu_in_0 = {ret_addr, {`BYTE_OFFSET_W{1'b0}}};
br_addr = jr_target;
br_taken = `ENABLE;
br_flag = `ENABLE;
dst_addr = `REG_ADDR_W'd31;
gpr_we_ = `ENABLE_;
end
/* ANZX½ß */
`ISA_OP_LDW : begin // [hÇÝoµ
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
mem_op = `MEM_OP_LDW;
gpr_we_ = `ENABLE_;
end
`ISA_OP_STW : begin // [h«Ý
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
mem_op = `MEM_OP_STW;
end
/* VXeR[½ß */
`ISA_OP_TRAP : begin // gbv
exp_code = `ISA_EXP_TRAP;
end
/* Á ½ß */
`ISA_OP_RDCR : begin // §äWX^ÌÇÝoµ
if (exe_mode == `CPU_KERNEL_MODE) begin
alu_in_0 = creg_rd_data;
gpr_we_ = `ENABLE_;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
`ISA_OP_WRCR : begin // §äWX^ÖÌ«Ý
if (exe_mode == `CPU_KERNEL_MODE) begin
ctrl_op = `CTRL_OP_WRCR;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
`ISA_OP_EXRT : begin // áO©çÌA
if (exe_mode == `CPU_KERNEL_MODE) begin
ctrl_op = `CTRL_OP_EXRT;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
/* »Ì¼Ì½ß */
default : begin // ¢è`½ß
exp_code = `ISA_EXP_UNDEF_INSN;
end
endcase
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_if/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_ARUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
// write request
wire write_ready;
wire write_valid;
wire [31:0] write_address;
wire [31:0] write_length;
wire [C_USER_DATA_WIDTH-1:0] write_data;
// read request
wire read_ready;
wire read_valid;
wire [31:0] read_address;
wire [31:0] read_length;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_stride_request_preprocessor
nfa_accept_samples_generic_hw_indices_stride_request_preprocessor #(
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) request_preprocessor (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.USER_dataout ( USER_dataout ),
.USER_address ( USER_address ),
.USER_size ( USER_size ),
.USER_req_din ( USER_req_din ),
.USER_req_full_n ( USER_req_full_n ),
.USER_req_write ( USER_req_write ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length )
);
// nfa_accept_samples_generic_hw_indices_stride_write
nfa_accept_samples_generic_hw_indices_stride_write #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_AWUSER_WIDTH ( C_AWUSER_WIDTH ),
.C_WUSER_WIDTH ( C_WUSER_WIDTH ),
.C_BUSER_WIDTH ( C_BUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_write (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.AWID ( AWID ),
.AWADDR ( AWADDR ),
.AWLEN ( AWLEN ),
.AWSIZE ( AWSIZE ),
.AWBURST ( AWBURST ),
.AWLOCK ( AWLOCK ),
.AWCACHE ( AWCACHE ),
.AWPROT ( AWPROT ),
.AWQOS ( AWQOS ),
.AWUSER ( AWUSER ),
.AWVALID ( AWVALID ),
.AWREADY ( AWREADY ),
.WDATA ( WDATA ),
.WSTRB ( WSTRB ),
.WLAST ( WLAST ),
.WUSER ( WUSER ),
.WVALID ( WVALID ),
.WREADY ( WREADY ),
.BID ( BID ),
.BRESP ( BRESP ),
.BUSER ( BUSER ),
.BVALID ( BVALID ),
.BREADY ( BREADY ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data )
);
// nfa_accept_samples_generic_hw_indices_stride_read
nfa_accept_samples_generic_hw_indices_stride_read #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_ARUSER_WIDTH ( C_ARUSER_WIDTH ),
.C_RUSER_WIDTH ( C_RUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_read (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.ARID ( ARID ),
.ARADDR ( ARADDR ),
.ARLEN ( ARLEN ),
.ARSIZE ( ARSIZE ),
.ARBURST ( ARBURST ),
.ARLOCK ( ARLOCK ),
.ARCACHE ( ARCACHE ),
.ARPROT ( ARPROT ),
.ARQOS ( ARQOS ),
.ARUSER ( ARUSER ),
.ARVALID ( ARVALID ),
.ARREADY ( ARREADY ),
.RID ( RID ),
.RDATA ( RDATA ),
.RRESP ( RRESP ),
.RLAST ( RLAST ),
.RUSER ( RUSER ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length ),
.USER_datain ( USER_datain ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.USER_rsp_read ( USER_rsp_read )
);
//------------------------Body---------------------------
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_request_preprocessor/*{{{*/
#(parameter
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// user ports
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
// write request
input wire write_ready,
output wire write_valid,
output wire [31:0] write_address,
output wire [31:0] write_length,
output wire [C_USER_DATA_WIDTH-1:0] write_data,
// read request
input wire read_ready,
output wire read_valid,
output wire [31:0] read_address,
output wire [31:0] read_length
);
//------------------------Parameter----------------------
localparam
REQUEST_WIDTH = 1 + 32 + 32 + C_USER_DATA_WIDTH,
MAX_REQUEST = 32;
//------------------------Local signal-------------------
// request fifo
wire req_empty_n;
wire req_full_n;
wire req_rdreq;
wire req_wrreq;
wire [REQUEST_WIDTH-1:0] req_data;
wire [REQUEST_WIDTH-1:0] req_q;
wire [31:0] tmp_size;
wire tmp_type; // 0 - read, 1 - write
wire [31:0] tmp_address; // start address of read/write request
wire [31:0] tmp_length; // length of read/write request
wire [C_USER_DATA_WIDTH-1:0] tmp_data; // data of write request
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_stride_fifo
nfa_accept_samples_generic_hw_indices_stride_fifo #(
.DATA_BITS ( REQUEST_WIDTH ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) req_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( req_empty_n ),
.full_n ( req_full_n ),
.rdreq ( req_rdreq ),
.wrreq ( req_wrreq ),
.q ( req_q ),
.data ( req_data )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++user ports+++++++++++++++++++++
assign USER_req_full_n = req_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
assign write_valid = req_empty_n & tmp_type;
assign write_address = tmp_address;
assign write_length = tmp_length;
assign write_data = tmp_data;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_valid = req_empty_n & ~tmp_type;
assign read_address = tmp_address;
assign read_length = tmp_length;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++request fifo+++++++++++++++++++
assign req_rdreq = (read_valid & read_ready) | (write_valid & write_ready);
assign req_wrreq = USER_req_write;
assign req_data = {USER_req_din, USER_address, tmp_size, USER_dataout};
assign tmp_size = (USER_size==1'b0)? 1'b1 : USER_size;
assign tmp_type = req_q[REQUEST_WIDTH-1];
assign tmp_address = req_q[C_USER_DATA_WIDTH+63:C_USER_DATA_WIDTH+32];
assign tmp_length = req_q[C_USER_DATA_WIDTH+31:C_USER_DATA_WIDTH];
assign tmp_data = req_q[C_USER_DATA_WIDTH-1:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_write/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// write request
output wire write_ready,
input wire write_valid,
input wire [31:0] write_address,
input wire [31:0] write_length,
input wire [C_USER_DATA_WIDTH-1:0] write_data
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_BYTES = USER_DATA_BYTES > BUS_DATA_BYTES?
USER_DATA_BYTES : BUS_DATA_BYTES,
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
DATA = 4'd3,
LOOP = 4'd4;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg enough_data;
reg [DATA_BUF_BYTES*8-1:0] data_buf;
reg [DATA_BUF_BYTES-1:0] data_valid;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
reg [BUS_ADDR_ALIGN-1:0] tmp_bytes;
reg [BUS_ADDR_ALIGN-1:0] head_bytes;
reg [BUS_ADDR_ALIGN-1:0] tail_bytes;
reg add_head;
reg add_tail;
reg first_beat;
reg last_beat;
// axi4 bus
wire [BUS_DATA_BYTES-1:0] wstrb0;
wire [BUS_DATA_BYTES-1:0] wstrb1;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (write_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (AWREADY)
next = DATA;
else
next = ADDR;
DATA:
if (WVALID && WREADY && loop_beats==1'b1)
next = LOOP;
else
next = DATA;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (write_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && AWREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
len_buf <= write_length - 1'b1;
else if (write_ready && write_valid)
len_buf <= len_buf - 1'b1;
end
// enough_data
always @(posedge ACLK) begin
if (state==IDLE && write_valid) begin
if (write_length == 1'b1)
enough_data <= 1'b1;
else
enough_data <= 1'b0;
end
else if (write_ready && write_valid && len_buf==1'b1)
enough_data <= 1'b1;
end
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : wide_to_narrow
assign wstrb0 = {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= write_data;
else if (WREADY & WVALID)
data_buf <= data_buf >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (write_ready & write_valid)
data_valid <= {DATA_BUF_BYTES{1'b1}};
else if (WREADY & WVALID)
data_valid <= data_valid >> BUS_DATA_BYTES;
end
// tmp_bytes, head_bytes, tail_bytes, add_head, add_tail
// first_beat, last_beat
always @(*) begin
// these signals are useless if user data width is
// greater than bus data width
tmp_bytes = 1'b0;
head_bytes = 1'b0;
tail_bytes = 1'b0;
add_head = 1'b0;
add_tail = 1'b0;
first_beat = 1'b0;
last_beat = 1'b0;
end
end
else begin : narrow_to_wide
assign wstrb0 = first_beat? {BUS_DATA_BYTES{1'b1}} << head_bytes : {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = last_beat? {BUS_DATA_BYTES{1'b1}} >> tail_bytes : {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= {write_data, data_buf} >> USER_DATA_WIDTH;
else if (state==DATA && add_tail)
data_buf <= data_buf >> (tail_bytes * 8);
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (WREADY & WVALID)
data_valid <= {USER_DATA_BYTES{write_ready & write_valid}} << (DATA_BUF_BYTES-USER_DATA_BYTES);
else if (write_ready & write_valid)
data_valid <= {{USER_DATA_BYTES{1'b1}}, data_valid} >> USER_DATA_BYTES;
else if (add_head)
data_valid <= (data_valid >> head_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> head_bytes);
else if (state==DATA && add_tail)
data_valid <= (data_valid >> tail_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> tail_bytes);
end
// tmp_bytes
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
tmp_bytes <= write_length[BUS_ADDR_ALIGN-1:0] << USER_ADDR_ALIGN;
end
// head_bytes
always @(posedge ACLK) begin
if (state==PREP)
head_bytes <= addr_buf[BUS_ADDR_ALIGN-1:0];
end
// tail_bytes
always @(posedge ACLK) begin
if (state==PREP)
tail_bytes <= BUS_DATA_BYTES - addr_buf[BUS_ADDR_ALIGN-1:0] - tmp_bytes;
end
// add_head
always @(posedge ACLK) begin
if (state==PREP)
add_head <= 1'b1;
else
add_head <= 1'b0;
end
// add_tail
always @(posedge ACLK) begin
if (write_ready && write_valid && (write_length== 1'b1 || len_buf==1'b1))
add_tail <= 1'b1;
else if (state==DATA)
add_tail <= 1'b0;
end
// first_beat
always @(posedge ACLK) begin
if (state==PREP)
first_beat <= 1'b1;
else if (WREADY & WVALID)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if ((state==PREP || state==LOOP) && total_beats==1'b1)
last_beat <= 1'b1;
else if (WREADY & WVALID) begin
if (total_beats==1'b0 && loop_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end
endgenerate
// total_beats
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
total_beats <= ((write_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && AWREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
else if (WVALID & WREADY)
loop_beats <= loop_beats - 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi4 bus+++++++++++++++++++++++
// write address channel
assign AWID = 1'b0;
assign AWADDR = addr_buf;
assign AWLEN = loop_beats - 1'b1;
assign AWSIZE = BUS_ADDR_ALIGN[2:0];
assign AWBURST = 2'b01;
assign AWLOCK = 2'b00;
assign AWCACHE = C_CACHE_VALUE;
assign AWPROT = C_PROT_VALUE;
assign AWQOS = 4'b0000;
assign AWUSER = C_USER_VALUE;
assign AWVALID = (state==ADDR);
// write data channel
assign WDATA = data_buf[BUS_DATA_WIDTH-1:0];
assign WSTRB = wstrb0 & wstrb1;
assign WLAST = WVALID & (loop_beats==1'b1);
assign WUSER = C_USER_VALUE;
assign WVALID = (state==DATA) & data_valid[0];
// write response channel
assign BREADY = 1'b1; // we don't handle write response
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
generate
if (USER_DATA_BYTES <= BUS_DATA_BYTES) begin : gen_write_ready_0
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(~data_valid[0] | WREADY));
end
else begin : gen_write_ready_1
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(data_valid[DATA_BUF_BYTES-1:BUS_DATA_BYTES]==1'b0) &
(~data_valid[0] | WREADY));
end
endgenerate
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_read/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_ARUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// read request
output wire read_ready,
input wire read_valid,
input wire [31:0] read_address,
input wire [31:0] read_length,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
LOOP = 4'd3;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
// data align
wire align_ready;
wire align_valid;
wire [31:0] align_beats;
wire [31:0] align_address;
wire [31:0] align_length;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_stride_read_data_align
nfa_accept_samples_generic_hw_indices_stride_read_data_align #(
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) data_align (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.RDATA ( RDATA ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.USER_datain ( USER_datain ),
.USER_rsp_read ( USER_rsp_read ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.align_ready ( align_ready ),
.align_valid ( align_valid ),
.align_beats ( align_beats ),
.align_address ( align_address ),
.align_length ( align_length )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (align_ready & read_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (ARREADY)
next = LOOP;
else
next = ADDR;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (read_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && ARREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
len_buf <= read_length;
end
// total_beats
always @(posedge ACLK) begin
if (read_ready & read_valid)
total_beats <= ((read_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && ARREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read address channel+++++++++++
assign ARID = 1'b0;
assign ARADDR = addr_buf;
assign ARLEN = loop_beats - 1'b1;
assign ARSIZE = BUS_ADDR_ALIGN[2:0];
assign ARBURST = 2'b01;
assign ARLOCK = 2'b00;
assign ARCACHE = C_CACHE_VALUE;
assign ARPROT = C_PROT_VALUE;
assign ARQOS = 4'b0000;
assign ARUSER = C_USER_VALUE;
assign ARVALID = (state==ADDR);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++data align+++++++++++++++++++++
assign align_valid = (state==PREP);
assign align_beats = total_beats;
assign align_address = addr_buf;
assign align_length = len_buf;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_ready = (state==IDLE) & align_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_read_data_align/*{{{*/
#(parameter
C_DATA_WIDTH = 32,
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read data channel
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read,
// data align
output wire align_ready,
input wire align_valid,
input wire [31:0] align_beats,
input wire [31:0] align_address,
input wire [31:0] align_length
);
//------------------------Parameter----------------------
localparam
DATA_FIFO_DEPTH = 32,
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_WIDTH = USER_DATA_WIDTH > BUS_DATA_WIDTH?
USER_DATA_WIDTH : BUS_DATA_WIDTH,
DATA_VALID_BITS = USER_DATA_BYTES > BUS_DATA_BYTES ?
USER_DATA_BYTES / BUS_DATA_BYTES :
BUS_DATA_BYTES / USER_DATA_BYTES;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Local signal-------------------
reg [DATA_BUF_WIDTH-1:0] data_buf;
reg [DATA_VALID_BITS-1:0] data_valid;
reg [31:0] total_beats;
reg ready_buf;
wire [BUS_DATA_WIDTH-1:0] rs0_data;
wire rs0_valid;
wire rs0_ready;
wire fifo_empty_n;
wire fifo_full_n;
wire fifo_rdreq;
wire fifo_wrreq;
wire [C_USER_DATA_WIDTH-1:0] fifo_q;
wire [C_USER_DATA_WIDTH-1:0] fifo_data;
wire fifo_push;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_stride_reg_slice
nfa_accept_samples_generic_hw_indices_stride_reg_slice #(
.N ( BUS_DATA_WIDTH )
) rs0 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( RDATA ),
.s_valid ( RVALID ),
.s_ready ( RREADY ),
.m_data ( rs0_data ),
.m_valid ( rs0_valid ),
.m_ready ( rs0_ready )
);
// nfa_accept_samples_generic_hw_indices_stride_fifo
nfa_accept_samples_generic_hw_indices_stride_fifo #(
.DATA_BITS ( C_USER_DATA_WIDTH ),
.DEPTH ( DATA_FIFO_DEPTH ),
.DEPTH_BITS ( log2(DATA_FIFO_DEPTH) )
) data_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( fifo_empty_n ),
.full_n ( fifo_full_n ),
.rdreq ( fifo_rdreq ),
.wrreq ( fifo_wrreq ),
.q ( fifo_q ),
.data ( fifo_data )
);
// nfa_accept_samples_generic_hw_indices_stride_reg_slice
nfa_accept_samples_generic_hw_indices_stride_reg_slice #(
.N ( C_USER_DATA_WIDTH )
) rs1 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( fifo_q ),
.s_valid ( fifo_empty_n ),
.s_ready ( fifo_rdreq ),
.m_data ( USER_datain ),
.m_valid ( USER_rsp_empty_n ),
.m_ready ( USER_rsp_read )
);
//------------------------Body---------------------------
assign fifo_data = data_buf[C_USER_DATA_WIDTH-1:0];
assign fifo_wrreq = data_valid[0];
assign fifo_push = fifo_full_n & fifo_wrreq;
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : narrow_to_wide
/*
* user data width is greater than or equal to bus data width
* so all bytes of bus data are valid
*/
assign align_ready = 1'b1;
assign rs0_ready = ~align_valid & ready_buf & (~data_valid[0] | fifo_push);
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= {rs0_data, data_buf} >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (fifo_push)
data_valid <= (rs0_ready & rs0_valid) << (DATA_VALID_BITS-1);
else if (rs0_ready & rs0_valid)
data_valid <= {1'b1, data_valid} >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (~ARESETN)
total_beats <= 1'b0;
else if (align_valid)
total_beats <= total_beats + align_beats; // may overflow
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (align_valid)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
end // end of narrow_to_wide
else begin : wide_to_narrow
/*
* user data width is less than bus data width
* so we have to remove the padding bytes
*/
localparam
PADDING_BITS = log2(DATA_VALID_BITS),
MAX_REQUEST = 32,
DATA_BITS = PADDING_BITS * 2 + 32;
wire [31:0] end_address;
wire [PADDING_BITS-1:0] head_tmp;
wire [PADDING_BITS-1:0] tail_tmp;
reg [PADDING_BITS-1:0] head_padding;
reg [PADDING_BITS-1:0] tail_padding;
reg first_beat;
reg last_beat;
wire request_fifo_empty_n;
wire request_fifo_full_n;
wire request_fifo_rdreq;
wire request_fifo_wrreq;
wire [DATA_BITS-1:0] request_fifo_q;
wire [DATA_BITS-1:0] request_fifo_data;
// nfa_accept_samples_generic_hw_indices_stride_fifo
nfa_accept_samples_generic_hw_indices_stride_fifo #(
.DATA_BITS ( DATA_BITS ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) request_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( request_fifo_empty_n ),
.full_n ( request_fifo_full_n ),
.rdreq ( request_fifo_rdreq ),
.wrreq ( request_fifo_wrreq ),
.q ( request_fifo_q ),
.data ( request_fifo_data )
);
assign align_ready = request_fifo_full_n;
assign rs0_ready = ready_buf & (data_valid==1'b0 || (data_valid==1'b1 && fifo_push));
assign end_address = align_address + align_length * USER_DATA_BYTES;
assign head_tmp = align_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN];
assign tail_tmp = ~end_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN] + 1'b1;
assign request_fifo_rdreq = request_fifo_empty_n & ~ready_buf;
assign request_fifo_wrreq = align_valid;
assign request_fifo_data = {head_tmp, tail_tmp, align_beats};
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= rs0_data >> (first_beat? head_padding * USER_DATA_WIDTH : 0);
else if (fifo_push)
data_buf <= data_buf >> USER_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (rs0_ready & rs0_valid)
data_valid <= ({DATA_VALID_BITS{1'b1}} >> (last_beat? tail_padding : 0))
>> (first_beat? head_padding : 0);
else if (fifo_push)
data_valid <= data_valid >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (request_fifo_rdreq)
total_beats <= request_fifo_q[31:0];
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (request_fifo_rdreq)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
// head_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
head_padding <= request_fifo_q[31+PADDING_BITS*2:32+PADDING_BITS];
end
// tail_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
tail_padding <= request_fifo_q[31+PADDING_BITS:32];
end
// first_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq)
first_beat <= 1'b1;
else if (rs0_ready & rs0_valid)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq && request_fifo_q[31:0]==1'b1)
last_beat <= 1'b1;
else if (rs0_ready & rs0_valid) begin
if (total_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end // end of wide_to_narrow
endgenerate
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_fifo/*{{{*/
#(parameter
DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
)(
input wire sclk,
input wire reset_n,
output reg empty_n,
output reg full_n,
input wire rdreq,
input wire wrreq,
output wire [DATA_BITS-1:0] q,
input wire [DATA_BITS-1:0] data
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
wire push;
wire pop;
reg [DEPTH_BITS-1:0] pout;
reg [DATA_BITS-1:0] mem[0:DEPTH-1];
//------------------------Body---------------------------
assign push = full_n & wrreq;
assign pop = empty_n & rdreq;
assign q = mem[pout];
// empty_n
always @(posedge sclk) begin
if (~reset_n)
empty_n <= 1'b0;
else if (push)
empty_n <= 1'b1;
else if (~push && pop && pout == 1'b0)
empty_n <= 1'b0;
end
// full_n
always @(posedge sclk) begin
if (~reset_n)
full_n <= 1'b1;
else if (rdreq)
full_n <= 1'b1;
else if (push && ~pop && pout == DEPTH - 2)
full_n <= 1'b0;
end
// pout
always @(posedge sclk) begin
if (~reset_n)
pout <= 1'b0;
else if (push & ~pop & empty_n)
pout <= pout + 1'b1;
else if (~push && pop && pout != 1'b0)
pout <= pout - 1'b1;
end
integer i;
always @(posedge sclk) begin
if (push) begin
for (i = 0; i < DEPTH - 1; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= data;
end
end
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_stride_reg_slice/*{{{*/
#(parameter
N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset_n,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [1:0] state;
reg [1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge sclk) begin
if (load_p1) begin
if (load_p1_from_p2)
data_p1 <= data_p2;
else
data_p1 <= s_data;
end
end
// data_p2
always @(posedge sclk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge sclk) begin
if (~reset_n)
s_ready_t <= 1'b0;
else if (state == ZERO)
s_ready_t <= 1'b1;
else if (state == ONE && next == TWO)
s_ready_t <= 1'b0;
else if (state == TWO && next == ONE)
s_ready_t <= 1'b1;
end
// state
always @(posedge sclk) begin
if (~reset_n)
state <= ZERO;
else
state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready)
next = ONE;
else
next = ZERO;
ONE:
if (~s_valid & m_ready)
next = ZERO;
else if (s_valid & ~m_ready)
next = TWO;
else
next = ONE;
TWO:
if (m_ready)
next = ONE;
else
next = TWO;
default:
next = ZERO;
endcase
end
endmodule/*}}}*/
// vim:ts=4 sw=4 et fdm=marker:
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_BLACKBOX_V
`define SKY130_FD_SC_MS__SEDFXTP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_BLACKBOX_V
|
// vga_0.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module vga_0 (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) vga_0 (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_div CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_div 2012:05:31:20:08:02:SJ cbx_altsyncram 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_abs 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_decode 2012:05:31:20:08:02:SJ cbx_lpm_divide 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_stratixiii 2012:05:31:20:08:02:SJ cbx_stratixv 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altfp_div_pst CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" FILE_NAME="acl_fp_div_s5.v:a" PIPELINE=14 WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_div 2012:05:31:20:08:02:SJ cbx_altsyncram 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_abs 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_decode 2012:05:31:20:08:02:SJ cbx_lpm_divide 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_stratixiii 2012:05:31:20:08:02:SJ cbx_stratixv 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = altsyncram 1 lpm_add_sub 4 lpm_compare 1 lpm_mult 5 mux21 74 reg 847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_s5_altfp_div_pst_e6f
(
aclr,
clk_en,
clock,
dataa,
datab,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] wire_altsyncram3_q_a;
reg a_is_infinity_dffe_0;
reg a_is_infinity_dffe_1;
reg a_is_infinity_dffe_10;
reg a_is_infinity_dffe_11;
reg a_is_infinity_dffe_12;
reg a_is_infinity_dffe_2;
reg a_is_infinity_dffe_3;
reg a_is_infinity_dffe_4;
reg a_is_infinity_dffe_5;
reg a_is_infinity_dffe_6;
reg a_is_infinity_dffe_7;
reg a_is_infinity_dffe_8;
reg a_is_infinity_dffe_9;
reg a_zero_b_not_dffe_0;
reg a_zero_b_not_dffe_1;
reg a_zero_b_not_dffe_10;
reg a_zero_b_not_dffe_11;
reg a_zero_b_not_dffe_12;
reg a_zero_b_not_dffe_2;
reg a_zero_b_not_dffe_3;
reg a_zero_b_not_dffe_4;
reg a_zero_b_not_dffe_5;
reg a_zero_b_not_dffe_6;
reg a_zero_b_not_dffe_7;
reg a_zero_b_not_dffe_8;
reg a_zero_b_not_dffe_9;
reg [33:0] b1_dffe_0;
reg [33:0] b1_dffe_1;
reg b_is_infinity_dffe_0;
reg b_is_infinity_dffe_1;
reg b_is_infinity_dffe_10;
reg b_is_infinity_dffe_11;
reg b_is_infinity_dffe_12;
reg b_is_infinity_dffe_2;
reg b_is_infinity_dffe_3;
reg b_is_infinity_dffe_4;
reg b_is_infinity_dffe_5;
reg b_is_infinity_dffe_6;
reg b_is_infinity_dffe_7;
reg b_is_infinity_dffe_8;
reg b_is_infinity_dffe_9;
reg both_exp_zeros_dffe;
reg divbyzero_pipe_dffe_0;
reg divbyzero_pipe_dffe_1;
reg divbyzero_pipe_dffe_10;
reg divbyzero_pipe_dffe_11;
reg divbyzero_pipe_dffe_12;
reg divbyzero_pipe_dffe_2;
reg divbyzero_pipe_dffe_3;
reg divbyzero_pipe_dffe_4;
reg divbyzero_pipe_dffe_5;
reg divbyzero_pipe_dffe_6;
reg divbyzero_pipe_dffe_7;
reg divbyzero_pipe_dffe_8;
reg divbyzero_pipe_dffe_9;
reg [16:0] e1_dffe_0;
reg [16:0] e1_dffe_1;
reg [16:0] e1_dffe_perf_0;
reg [16:0] e1_dffe_perf_1;
reg [16:0] e1_dffe_perf_2;
reg [16:0] e1_dffe_perf_3;
reg [7:0] exp_result_dffe_0;
reg [7:0] exp_result_dffe_1;
reg [7:0] exp_result_dffe_10;
reg [7:0] exp_result_dffe_11;
reg [7:0] exp_result_dffe_2;
reg [7:0] exp_result_dffe_3;
reg [7:0] exp_result_dffe_4;
reg [7:0] exp_result_dffe_5;
reg [7:0] exp_result_dffe_6;
reg [7:0] exp_result_dffe_7;
reg [7:0] exp_result_dffe_8;
reg [7:0] exp_result_dffe_9;
reg frac_a_smaller_dffe1;
reg [22:0] man_a_dffe1_dffe1;
reg [22:0] man_b_dffe1_dffe1;
reg [22:0] man_result_dffe;
reg nan_pipe_dffe_0;
reg nan_pipe_dffe_1;
reg nan_pipe_dffe_10;
reg nan_pipe_dffe_11;
reg nan_pipe_dffe_12;
reg nan_pipe_dffe_2;
reg nan_pipe_dffe_3;
reg nan_pipe_dffe_4;
reg nan_pipe_dffe_5;
reg nan_pipe_dffe_6;
reg nan_pipe_dffe_7;
reg nan_pipe_dffe_8;
reg nan_pipe_dffe_9;
reg over_under_dffe_0;
reg over_under_dffe_1;
reg over_under_dffe_10;
reg over_under_dffe_2;
reg over_under_dffe_3;
reg over_under_dffe_4;
reg over_under_dffe_5;
reg over_under_dffe_6;
reg over_under_dffe_7;
reg over_under_dffe_8;
reg over_under_dffe_9;
reg [33:0] q_partial_perf_dffe_0;
reg [33:0] q_partial_perf_dffe_1;
reg [16:0] quotient_j_dffe;
reg [16:0] quotient_k_dffe_0;
reg [16:0] quotient_k_dffe_perf_0;
reg [16:0] quotient_k_dffe_perf_1;
reg [16:0] quotient_k_dffe_perf_2;
reg [16:0] quotient_k_dffe_perf_3;
reg [49:0] remainder_j_dffe_0;
reg [49:0] remainder_j_dffe_1;
reg [49:0] remainder_j_dffe_perf_0;
reg [49:0] remainder_j_dffe_perf_1;
reg [49:0] remainder_j_dffe_perf_2;
reg sign_pipe_dffe_0;
reg sign_pipe_dffe_1;
reg sign_pipe_dffe_10;
reg sign_pipe_dffe_11;
reg sign_pipe_dffe_12;
reg sign_pipe_dffe_13;
reg sign_pipe_dffe_2;
reg sign_pipe_dffe_3;
reg sign_pipe_dffe_4;
reg sign_pipe_dffe_5;
reg sign_pipe_dffe_6;
reg sign_pipe_dffe_7;
reg sign_pipe_dffe_8;
reg sign_pipe_dffe_9;
wire wire_bias_addition_overflow;
wire [8:0] wire_bias_addition_result;
wire [8:0] wire_exp_sub_result;
wire [30:0] wire_quotient_process_result;
wire [49:0] wire_remainder_sub_0_result;
wire wire_cmpr2_alb;
wire [34:0] wire_a1_prod_result;
wire [33:0] wire_b1_prod_result;
wire [33:0] wire_q_partial_0_result;
wire [33:0] wire_q_partial_1_result;
wire [50:0] wire_remainder_mult_0_result;
wire [7:0]wire_exp_result_muxa_dataout;
wire [24:0]wire_man_a_adjusteda_dataout;
wire [22:0]wire_man_result_muxa_dataout;
wire [8:0]wire_select_bias_2a_dataout;
wire [8:0]wire_select_biasa_dataout;
wire a_is_infinity_w;
wire a_is_nan_w;
wire a_zero_b_not;
wire [33:0] b1_dffe_w;
wire b_is_infinity_w;
wire b_is_nan_w;
wire bias_addition_overf_w;
wire [7:0] bias_addition_w;
wire both_exp_zeros;
wire [8:0] e0_dffe1_wo;
wire [8:0] e0_w;
wire [50:0] e1_w;
wire [7:0] exp_a_all_one_w;
wire [7:0] exp_a_not_zero_w;
wire [7:0] exp_add_output_all_one;
wire [7:0] exp_add_output_not_zero;
wire [7:0] exp_b_all_one_w;
wire [7:0] exp_b_not_zero_w;
wire [7:0] exp_result_mux_out;
wire exp_result_mux_sel_w;
wire [7:0] exp_result_w;
wire exp_sign_w;
wire [8:0] exp_sub_a_w;
wire [8:0] exp_sub_b_w;
wire [8:0] exp_sub_w;
wire frac_a_smaller_dffe1_wi;
wire frac_a_smaller_dffe1_wo;
wire frac_a_smaller_w;
wire guard_bit;
wire [24:0] man_a_adjusted_w;
wire [22:0] man_a_dffe1_wi;
wire [22:0] man_a_dffe1_wo;
wire [22:0] man_a_not_zero_w;
wire [23:0] man_b_adjusted_w;
wire [22:0] man_b_dffe1_wi;
wire [22:0] man_b_dffe1_wo;
wire [22:0] man_b_not_zero_w;
wire [22:0] man_result_dffe_wi;
wire [22:0] man_result_dffe_wo;
wire man_result_mux_select;
wire [22:0] man_result_w;
wire [22:0] man_zeros_w;
wire [7:0] overflow_ones_w;
wire overflow_underflow;
wire overflow_w;
wire [61:0] quotient_accumulate_w;
wire quotient_process_cin_w;
wire [99:0] remainder_j_w;
wire round_bit;
wire [8:0] select_bias_out_2_w;
wire [8:0] select_bias_out_w;
wire [4:0] sticky_bits;
wire underflow_w;
wire [7:0] underflow_zeros_w;
wire [8:0] value_add_one_w;
wire [8:0] value_normal_w;
wire [8:0] value_zero_w;
altsyncram altsyncram3
(
.address_a(datab[22:14]),
.clock0(clock),
.clocken0(clk_en),
.eccstatus(),
.q_a(wire_altsyncram3_q_a),
.q_b()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({9{1'b1}}),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram3.init_file = "acl_fp_div_s5.hex",
altsyncram3.operation_mode = "ROM",
altsyncram3.width_a = 9,
altsyncram3.widthad_a = 9,
altsyncram3.intended_device_family = "Stratix V",
altsyncram3.lpm_type = "altsyncram";
// synopsys translate_off
initial
a_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_0 <= a_is_infinity_w;
// synopsys translate_off
initial
a_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
// synopsys translate_off
initial
a_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_10 <= a_is_infinity_dffe_9;
// synopsys translate_off
initial
a_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_11 <= a_is_infinity_dffe_10;
// synopsys translate_off
initial
a_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_12 <= a_is_infinity_dffe_11;
// synopsys translate_off
initial
a_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
// synopsys translate_off
initial
a_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
// synopsys translate_off
initial
a_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
// synopsys translate_off
initial
a_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_5 <= a_is_infinity_dffe_4;
// synopsys translate_off
initial
a_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_6 <= a_is_infinity_dffe_5;
// synopsys translate_off
initial
a_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_7 <= a_is_infinity_dffe_6;
// synopsys translate_off
initial
a_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_8 <= a_is_infinity_dffe_7;
// synopsys translate_off
initial
a_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_9 <= a_is_infinity_dffe_8;
// synopsys translate_off
initial
a_zero_b_not_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_0 <= a_zero_b_not;
// synopsys translate_off
initial
a_zero_b_not_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
// synopsys translate_off
initial
a_zero_b_not_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_10 <= a_zero_b_not_dffe_9;
// synopsys translate_off
initial
a_zero_b_not_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_11 <= a_zero_b_not_dffe_10;
// synopsys translate_off
initial
a_zero_b_not_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_12 <= a_zero_b_not_dffe_11;
// synopsys translate_off
initial
a_zero_b_not_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
// synopsys translate_off
initial
a_zero_b_not_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
// synopsys translate_off
initial
a_zero_b_not_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
// synopsys translate_off
initial
a_zero_b_not_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_5 <= a_zero_b_not_dffe_4;
// synopsys translate_off
initial
a_zero_b_not_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_6 <= a_zero_b_not_dffe_5;
// synopsys translate_off
initial
a_zero_b_not_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_7 <= a_zero_b_not_dffe_6;
// synopsys translate_off
initial
a_zero_b_not_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_8 <= a_zero_b_not_dffe_7;
// synopsys translate_off
initial
a_zero_b_not_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_9 <= a_zero_b_not_dffe_8;
// synopsys translate_off
initial
b1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) b1_dffe_0 <= wire_b1_prod_result;
// synopsys translate_off
initial
b1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) b1_dffe_1 <= b1_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_0 <= b_is_infinity_w;
// synopsys translate_off
initial
b_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_10 <= b_is_infinity_dffe_9;
// synopsys translate_off
initial
b_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_11 <= b_is_infinity_dffe_10;
// synopsys translate_off
initial
b_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_12 <= b_is_infinity_dffe_11;
// synopsys translate_off
initial
b_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
// synopsys translate_off
initial
b_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
// synopsys translate_off
initial
b_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
// synopsys translate_off
initial
b_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_5 <= b_is_infinity_dffe_4;
// synopsys translate_off
initial
b_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_6 <= b_is_infinity_dffe_5;
// synopsys translate_off
initial
b_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_7 <= b_is_infinity_dffe_6;
// synopsys translate_off
initial
b_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_8 <= b_is_infinity_dffe_7;
// synopsys translate_off
initial
b_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_9 <= b_is_infinity_dffe_8;
// synopsys translate_off
initial
both_exp_zeros_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_exp_zeros_dffe <= 1'b0;
else if (clk_en == 1'b1) both_exp_zeros_dffe <= ((~ exp_b_not_zero_w[7]) & (~ exp_a_not_zero_w[7]));
// synopsys translate_off
initial
divbyzero_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_0 <= ((((~ exp_b_not_zero_w[7]) & (~ a_is_nan_w)) & exp_a_not_zero_w[7]) & (~ a_is_infinity_w));
// synopsys translate_off
initial
divbyzero_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
// synopsys translate_off
initial
divbyzero_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_10 <= divbyzero_pipe_dffe_9;
// synopsys translate_off
initial
divbyzero_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_11 <= divbyzero_pipe_dffe_10;
// synopsys translate_off
initial
divbyzero_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_12 <= divbyzero_pipe_dffe_11;
// synopsys translate_off
initial
divbyzero_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
// synopsys translate_off
initial
divbyzero_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
// synopsys translate_off
initial
divbyzero_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
// synopsys translate_off
initial
divbyzero_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_5 <= divbyzero_pipe_dffe_4;
// synopsys translate_off
initial
divbyzero_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_6 <= divbyzero_pipe_dffe_5;
// synopsys translate_off
initial
divbyzero_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_7 <= divbyzero_pipe_dffe_6;
// synopsys translate_off
initial
divbyzero_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_8 <= divbyzero_pipe_dffe_7;
// synopsys translate_off
initial
divbyzero_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_9 <= divbyzero_pipe_dffe_8;
// synopsys translate_off
initial
e1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_0 <= e1_w[16:0];
// synopsys translate_off
initial
e1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_1 <= e1_w[33:17];
// synopsys translate_off
initial
e1_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_0 <= e1_dffe_0;
// synopsys translate_off
initial
e1_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_1 <= e1_dffe_perf_0;
// synopsys translate_off
initial
e1_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_2 <= e1_dffe_perf_1;
// synopsys translate_off
initial
e1_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_3 <= e1_dffe_perf_2;
// synopsys translate_off
initial
exp_result_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_0 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_0 <= exp_result_mux_out;
// synopsys translate_off
initial
exp_result_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_1 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_1 <= exp_result_dffe_0;
// synopsys translate_off
initial
exp_result_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_10 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_10 <= exp_result_dffe_9;
// synopsys translate_off
initial
exp_result_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_11 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_11 <= exp_result_dffe_10;
// synopsys translate_off
initial
exp_result_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_2 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_2 <= exp_result_dffe_1;
// synopsys translate_off
initial
exp_result_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_3 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_3 <= exp_result_dffe_2;
// synopsys translate_off
initial
exp_result_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_4 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_4 <= exp_result_dffe_3;
// synopsys translate_off
initial
exp_result_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_5 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_5 <= exp_result_dffe_4;
// synopsys translate_off
initial
exp_result_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_6 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_6 <= exp_result_dffe_5;
// synopsys translate_off
initial
exp_result_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_7 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_7 <= exp_result_dffe_6;
// synopsys translate_off
initial
exp_result_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_8 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_8 <= exp_result_dffe_7;
// synopsys translate_off
initial
exp_result_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_9 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_9 <= exp_result_dffe_8;
// synopsys translate_off
initial
frac_a_smaller_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) frac_a_smaller_dffe1 <= 1'b0;
else if (clk_en == 1'b1) frac_a_smaller_dffe1 <= frac_a_smaller_dffe1_wi;
// synopsys translate_off
initial
man_a_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_dffe1_dffe1 <= 23'b0;
else if (clk_en == 1'b1) man_a_dffe1_dffe1 <= man_a_dffe1_wi;
// synopsys translate_off
initial
man_b_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_dffe1_dffe1 <= 23'b0;
else if (clk_en == 1'b1) man_b_dffe1_dffe1 <= man_b_dffe1_wi;
// synopsys translate_off
initial
man_result_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_dffe <= 23'b0;
else if (clk_en == 1'b1) man_result_dffe <= man_result_dffe_wi;
// synopsys translate_off
initial
nan_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_0 <= (((a_is_nan_w | b_is_nan_w) | (a_is_infinity_w & b_is_infinity_w)) | ((~ exp_a_not_zero_w[7]) & (~ exp_b_not_zero_w[7])));
// synopsys translate_off
initial
nan_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_1 <= nan_pipe_dffe_0;
// synopsys translate_off
initial
nan_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_10 <= nan_pipe_dffe_9;
// synopsys translate_off
initial
nan_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_11 <= nan_pipe_dffe_10;
// synopsys translate_off
initial
nan_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_12 <= nan_pipe_dffe_11;
// synopsys translate_off
initial
nan_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_2 <= nan_pipe_dffe_1;
// synopsys translate_off
initial
nan_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_3 <= nan_pipe_dffe_2;
// synopsys translate_off
initial
nan_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_4 <= nan_pipe_dffe_3;
// synopsys translate_off
initial
nan_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_5 <= nan_pipe_dffe_4;
// synopsys translate_off
initial
nan_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_6 <= nan_pipe_dffe_5;
// synopsys translate_off
initial
nan_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_7 <= nan_pipe_dffe_6;
// synopsys translate_off
initial
nan_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_8 <= nan_pipe_dffe_7;
// synopsys translate_off
initial
nan_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_9 <= nan_pipe_dffe_8;
// synopsys translate_off
initial
over_under_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_0 <= overflow_underflow;
// synopsys translate_off
initial
over_under_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_1 <= over_under_dffe_0;
// synopsys translate_off
initial
over_under_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_10 <= over_under_dffe_9;
// synopsys translate_off
initial
over_under_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_2 <= over_under_dffe_1;
// synopsys translate_off
initial
over_under_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_3 <= over_under_dffe_2;
// synopsys translate_off
initial
over_under_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_4 <= over_under_dffe_3;
// synopsys translate_off
initial
over_under_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_5 <= over_under_dffe_4;
// synopsys translate_off
initial
over_under_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_6 <= over_under_dffe_5;
// synopsys translate_off
initial
over_under_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_7 <= over_under_dffe_6;
// synopsys translate_off
initial
over_under_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_8 <= over_under_dffe_7;
// synopsys translate_off
initial
over_under_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_9 <= over_under_dffe_8;
// synopsys translate_off
initial
q_partial_perf_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_0 <= wire_q_partial_0_result;
// synopsys translate_off
initial
q_partial_perf_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_1 <= wire_q_partial_1_result;
// synopsys translate_off
initial
quotient_j_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_j_dffe <= 17'b0;
else if (clk_en == 1'b1) quotient_j_dffe <= q_partial_perf_dffe_0[32:16];
// synopsys translate_off
initial
quotient_k_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_0 <= quotient_k_dffe_perf_3;
// synopsys translate_off
initial
quotient_k_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_0 <= quotient_accumulate_w[30:14];
// synopsys translate_off
initial
quotient_k_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_1 <= quotient_k_dffe_perf_0;
// synopsys translate_off
initial
quotient_k_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_2 <= quotient_k_dffe_perf_1;
// synopsys translate_off
initial
quotient_k_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_3 <= quotient_k_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_0 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_0 <= remainder_j_w[49:0];
// synopsys translate_off
initial
remainder_j_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_1 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_1 <= remainder_j_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_0 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_0 <= remainder_j_dffe_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_1 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_1 <= remainder_j_dffe_perf_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_2 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_2 <= remainder_j_dffe_perf_1;
// synopsys translate_off
initial
sign_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_0 <= (dataa[31] ^ datab[31]);
// synopsys translate_off
initial
sign_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_1 <= sign_pipe_dffe_0;
// synopsys translate_off
initial
sign_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_10 <= sign_pipe_dffe_9;
// synopsys translate_off
initial
sign_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_11 <= sign_pipe_dffe_10;
// synopsys translate_off
initial
sign_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_12 <= sign_pipe_dffe_11;
// synopsys translate_off
initial
sign_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_13 <= sign_pipe_dffe_12;
// synopsys translate_off
initial
sign_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_2 <= sign_pipe_dffe_1;
// synopsys translate_off
initial
sign_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_3 <= sign_pipe_dffe_2;
// synopsys translate_off
initial
sign_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_4 <= sign_pipe_dffe_3;
// synopsys translate_off
initial
sign_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_5 <= sign_pipe_dffe_4;
// synopsys translate_off
initial
sign_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_6 <= sign_pipe_dffe_5;
// synopsys translate_off
initial
sign_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_7 <= sign_pipe_dffe_6;
// synopsys translate_off
initial
sign_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_8 <= sign_pipe_dffe_7;
// synopsys translate_off
initial
sign_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_9 <= sign_pipe_dffe_8;
lpm_add_sub bias_addition
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_w),
.datab(select_bias_out_2_w),
.overflow(wire_bias_addition_overflow),
.result(wire_bias_addition_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
bias_addition.lpm_direction = "ADD",
bias_addition.lpm_pipeline = 1,
bias_addition.lpm_representation = "SIGNED",
bias_addition.lpm_width = 9,
bias_addition.lpm_type = "lpm_add_sub";
lpm_add_sub exp_sub
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_a_w),
.datab(exp_sub_b_w),
.overflow(),
.result(wire_exp_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_sub.lpm_direction = "SUB",
exp_sub.lpm_pipeline = 1,
exp_sub.lpm_representation = "SIGNED",
exp_sub.lpm_width = 9,
exp_sub.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_process
(
.aclr(aclr),
.cin(quotient_process_cin_w),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[61:45], {14{1'b0}}}),
.datab({{14{1'b0}}, q_partial_perf_dffe_1[32:22], {6{1'b1}}}),
.overflow(),
.result(wire_quotient_process_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_process.lpm_direction = "ADD",
quotient_process.lpm_pipeline = 1,
quotient_process.lpm_representation = "UNSIGNED",
quotient_process.lpm_width = 31,
quotient_process.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_1[49:15], {15{1'b0}}}),
.datab(wire_remainder_mult_0_result[49:0]),
.overflow(),
.result(wire_remainder_sub_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_0.lpm_direction = "SUB",
remainder_sub_0.lpm_pipeline = 1,
remainder_sub_0.lpm_representation = "UNSIGNED",
remainder_sub_0.lpm_width = 50,
remainder_sub_0.lpm_type = "lpm_add_sub";
lpm_compare cmpr2
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr2_alb),
.aleb(),
.aneb(),
.dataa(dataa[22:0]),
.datab(datab[22:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 23,
cmpr2.lpm_type = "lpm_compare";
lpm_mult a1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_a_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_a1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
a1_prod.lpm_pipeline = 3,
a1_prod.lpm_representation = "UNSIGNED",
a1_prod.lpm_widtha = 25,
a1_prod.lpm_widthb = 10,
a1_prod.lpm_widthp = 35,
a1_prod.lpm_type = "lpm_mult",
a1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult b1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_b_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_b1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
b1_prod.lpm_pipeline = 3,
b1_prod.lpm_representation = "UNSIGNED",
b1_prod.lpm_widtha = 24,
b1_prod.lpm_widthb = 10,
b1_prod.lpm_widthp = 34,
b1_prod.lpm_type = "lpm_mult",
b1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[49:33]),
.datab(e1_w[16:0]),
.result(wire_q_partial_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_0.lpm_pipeline = 1,
q_partial_0.lpm_representation = "UNSIGNED",
q_partial_0.lpm_widtha = 17,
q_partial_0.lpm_widthb = 17,
q_partial_0.lpm_widthp = 34,
q_partial_0.lpm_type = "lpm_mult",
q_partial_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[99:83]),
.datab(e1_w[50:34]),
.result(wire_q_partial_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_1.lpm_pipeline = 1,
q_partial_1.lpm_representation = "UNSIGNED",
q_partial_1.lpm_widtha = 17,
q_partial_1.lpm_widthb = 17,
q_partial_1.lpm_widthp = 34,
q_partial_1.lpm_type = "lpm_mult",
q_partial_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[33:0]),
.datab(q_partial_perf_dffe_0[32:16]),
.result(wire_remainder_mult_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_0.lpm_pipeline = 3,
remainder_mult_0.lpm_representation = "UNSIGNED",
remainder_mult_0.lpm_widtha = 34,
remainder_mult_0.lpm_widthb = 17,
remainder_mult_0.lpm_widthp = 51,
remainder_mult_0.lpm_type = "lpm_mult",
remainder_mult_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign wire_exp_result_muxa_dataout = (exp_result_mux_sel_w === 1'b1) ? underflow_zeros_w : exp_result_w;
assign wire_man_a_adjusteda_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? {1'b1, man_a_dffe1_wo, 1'b0} : {1'b0, 1'b1, man_a_dffe1_wo};
assign wire_man_result_muxa_dataout = (man_result_mux_select === 1'b1) ? {nan_pipe_dffe_12, man_zeros_w[21:0]} : wire_quotient_process_result[28:6];
assign wire_select_bias_2a_dataout = (both_exp_zeros === 1'b1) ? value_zero_w : select_bias_out_w;
assign wire_select_biasa_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? value_normal_w : value_add_one_w;
assign
a_is_infinity_w = (exp_a_all_one_w[7] & (~ man_a_not_zero_w[22])),
a_is_nan_w = (exp_a_all_one_w[7] & man_a_not_zero_w[22]),
a_zero_b_not = (exp_b_not_zero_w[7] & (~ exp_a_not_zero_w[7])),
b1_dffe_w = {b1_dffe_1},
b_is_infinity_w = (exp_b_all_one_w[7] & (~ man_b_not_zero_w[22])),
b_is_nan_w = (exp_b_all_one_w[7] & man_b_not_zero_w[22]),
bias_addition_overf_w = wire_bias_addition_overflow,
bias_addition_w = wire_bias_addition_result[7:0],
both_exp_zeros = both_exp_zeros_dffe,
e0_dffe1_wo = e0_w,
e0_w = wire_altsyncram3_q_a,
e1_w = {e1_dffe_1, e1_dffe_perf_3, (~ wire_b1_prod_result[33:17])},
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_add_output_all_one = {(bias_addition_w[7] & exp_add_output_all_one[6]), (bias_addition_w[6] & exp_add_output_all_one[5]), (bias_addition_w[5] & exp_add_output_all_one[4]), (bias_addition_w[4] & exp_add_output_all_one[3]), (bias_addition_w[3] & exp_add_output_all_one[2]), (bias_addition_w[2] & exp_add_output_all_one[1]), (bias_addition_w[1] & exp_add_output_all_one[0]), bias_addition_w[0]},
exp_add_output_not_zero = {(bias_addition_w[7] | exp_add_output_not_zero[6]), (bias_addition_w[6] | exp_add_output_not_zero[5]), (bias_addition_w[5] | exp_add_output_not_zero[4]), (bias_addition_w[4] | exp_add_output_not_zero[3]), (bias_addition_w[3] | exp_add_output_not_zero[2]), (bias_addition_w[2] | exp_add_output_not_zero[1]), (bias_addition_w[1] | exp_add_output_not_zero[0]), bias_addition_w[0]},
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_result_mux_out = wire_exp_result_muxa_dataout,
exp_result_mux_sel_w = ((((a_zero_b_not_dffe_1 | b_is_infinity_dffe_1) | ((~ bias_addition_overf_w) & exp_sign_w)) | (((~ exp_add_output_not_zero[7]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)),
exp_result_w = (({8{((~ bias_addition_overf_w) & (~ exp_sign_w))}} & bias_addition_w) | ({8{(((bias_addition_overf_w | divbyzero_pipe_dffe_1) | nan_pipe_dffe_1) | a_is_infinity_dffe_1)}} & overflow_ones_w)),
exp_sign_w = wire_bias_addition_result[8],
exp_sub_a_w = {1'b0, dataa[30:23]},
exp_sub_b_w = {1'b0, datab[30:23]},
exp_sub_w = wire_exp_sub_result,
frac_a_smaller_dffe1_wi = frac_a_smaller_w,
frac_a_smaller_dffe1_wo = frac_a_smaller_dffe1,
frac_a_smaller_w = wire_cmpr2_alb,
guard_bit = q_partial_perf_dffe_1[22],
man_a_adjusted_w = wire_man_a_adjusteda_dataout,
man_a_dffe1_wi = dataa[22:0],
man_a_dffe1_wo = man_a_dffe1_dffe1,
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_adjusted_w = {1'b1, man_b_dffe1_wo},
man_b_dffe1_wi = datab[22:0],
man_b_dffe1_wo = man_b_dffe1_dffe1,
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_result_dffe_wi = man_result_w,
man_result_dffe_wo = man_result_dffe,
man_result_mux_select = (((((over_under_dffe_10 | a_zero_b_not_dffe_12) | nan_pipe_dffe_12) | b_is_infinity_dffe_12) | a_is_infinity_dffe_12) | divbyzero_pipe_dffe_12),
man_result_w = wire_man_result_muxa_dataout,
man_zeros_w = {23{1'b0}},
overflow_ones_w = {8{1'b1}},
overflow_underflow = (overflow_w | underflow_w),
overflow_w = ((bias_addition_overf_w | ((exp_add_output_all_one[7] & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (((~ nan_pipe_dffe_1) & (~ a_is_infinity_dffe_1)) & (~ divbyzero_pipe_dffe_1))),
quotient_accumulate_w = {quotient_k_dffe_0, {14{1'b0}}, quotient_j_dffe, {14{1'b0}}},
quotient_process_cin_w = (round_bit & (guard_bit | sticky_bits[4])),
remainder_j_w = {wire_remainder_sub_0_result[35:0], {14{1'b0}}, wire_a1_prod_result[34:0], {15{1'b0}}},
result = {sign_pipe_dffe_13, exp_result_dffe_11, man_result_dffe_wo},
round_bit = q_partial_perf_dffe_1[21],
select_bias_out_2_w = wire_select_bias_2a_dataout,
select_bias_out_w = wire_select_biasa_dataout,
sticky_bits = {(q_partial_perf_dffe_1[20] | sticky_bits[3]), (q_partial_perf_dffe_1[19] | sticky_bits[2]), (q_partial_perf_dffe_1[18] | sticky_bits[1]), (q_partial_perf_dffe_1[17] | sticky_bits[0]), q_partial_perf_dffe_1[16]},
underflow_w = ((((((~ bias_addition_overf_w) & exp_sign_w) | (((~ exp_add_output_not_zero[7]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)) & (~ a_zero_b_not_dffe_1)) & (~ b_is_infinity_dffe_1)),
underflow_zeros_w = {8{1'b0}},
value_add_one_w = 9'b001111111,
value_normal_w = 9'b001111110,
value_zero_w = {9{1'b0}};
endmodule //acl_fp_div_s5_altfp_div_pst_e6f
//synthesis_resources = altsyncram 1 lpm_add_sub 4 lpm_compare 1 lpm_mult 5 mux21 74 reg 847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_s5_altfp_div_prh
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altfp_div_pst1_result;
wire aclr;
acl_fp_div_s5_altfp_div_pst_e6f altfp_div_pst1
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(wire_altfp_div_pst1_result));
assign
aclr = 1'b0,
result = wire_altfp_div_pst1_result;
endmodule //acl_fp_div_s5_altfp_div_prh
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_div_s5 (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_div_s5_altfp_div_prh acl_fp_div_s5_altfp_div_prh_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_bb.v TRUE
|
module axi_etrace (/*AUTOARG*/
// Outputs
wr_wait, txwr_packet, txwr_access, txrd_packet, txrd_access,
rxwr_wait, rxrr_wait, rd_wait, emesh_packet, emesh_access,
data_packet_out, data_access_out, cfg_packet_out, cfg_access_out,
m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
s_axi_wready,
// Inputs
wr_packet, wr_access, txwr_wait, txrd_wait, trace_vector,
trace_trigger, trace_clk, rxwr_packet, rxwr_access, rxrr_packet,
rxrr_access, rd_packet, rd_access, emesh_wait, cfg_packet_in,
cfg_access_in, m_axi_aclk, m_axi_aresetn, m_axi_awready,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready,
m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
s_axi_aclk, s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
s_axi_wstrb, s_axi_wvalid
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
//########################
//AXI MASTER INTERFACE
//########################
//clk+reset
input m_axi_aclk;
input m_axi_aresetn; // global reset singal.
//Write address channel
output [M_IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [M_IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // slave is ready for data
//Write response channel
input [M_IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [M_IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output m_axi_arlock; // lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; // --
output m_axi_arvalid; // read address and control is valid
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [M_IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
//########################
//AXI SLAVE INTERFACE
//########################
//clk+reset
input s_axi_aclk;
input s_axi_aresetn;
//Read address channel
input [S_IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [S_IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [S_IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [S_IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [S_IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input cfg_access_in; // To etrace of etrace.v
input [PW-1:0] cfg_packet_in; // To etrace of etrace.v
input emesh_wait; // To emesh_mux of emesh_mux.v
input rd_access; // To emesh_mux of emesh_mux.v
input [PW-1:0] rd_packet; // To emesh_mux of emesh_mux.v
input rxrr_access; // To esaxi of esaxi.v
input [PW-1:0] rxrr_packet; // To esaxi of esaxi.v
input rxwr_access; // To emaxi of emaxi.v
input [PW-1:0] rxwr_packet; // To emaxi of emaxi.v
input trace_clk; // To etrace of etrace.v
input trace_trigger; // To etrace of etrace.v
input [VW-1:0] trace_vector; // To etrace of etrace.v
input txrd_wait; // To esaxi of esaxi.v
input txwr_wait; // To esaxi of esaxi.v
input wr_access; // To emesh_mux of emesh_mux.v
input [PW-1:0] wr_packet; // To emesh_mux of emesh_mux.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cfg_access_out; // From etrace of etrace.v
output [PW-1:0] cfg_packet_out; // From etrace of etrace.v
output data_access_out; // From etrace of etrace.v
output [PW-1:0] data_packet_out; // From etrace of etrace.v
output emesh_access; // From emesh_mux of emesh_mux.v
output [PW-1:0] emesh_packet; // From emesh_mux of emesh_mux.v
output rd_wait; // From emesh_mux of emesh_mux.v
output rxrr_wait; // From esaxi of esaxi.v
output rxwr_wait; // From emaxi of emaxi.v
output txrd_access; // From esaxi of esaxi.v
output [PW-1:0] txrd_packet; // From esaxi of esaxi.v
output txwr_access; // From esaxi of esaxi.v
output [PW-1:0] txwr_packet; // From esaxi of esaxi.v
output wr_wait; // From emesh_mux of emesh_mux.v
// End of automatics
emaxi emaxi (.rxrd_access (1'b0),//no reads generated, just push
.rxrd_packet ({(PW){1'b0}}),
.rxrd_wait (),
.txrr_access (),//no reads, so no responses
.txrr_packet (),
.txrr_wait (1'b0),
/*AUTOINST*/
// Outputs
.rxwr_wait (rxwr_wait),
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
// Inputs
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid));
esaxi esaxi (/*AUTOINST*/
// Outputs
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.rxrr_wait (rxrr_wait),
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
//mux the read/write together
emesh_mux emesh_mux (/*AUTOINST*/
// Outputs
.rd_wait (rd_wait),
.wr_wait (wr_wait),
.emesh_access (emesh_access),
.emesh_packet (emesh_packet[PW-1:0]),
// Inputs
.rd_access (rd_access),
.rd_packet (rd_packet[PW-1:0]),
.wr_access (wr_access),
.wr_packet (wr_packet[PW-1:0]),
.emesh_wait (emesh_wait));
//tracing unit
etrace etrace (/*AUTOINST*/
// Outputs
.data_access_out (data_access_out),
.data_packet_out (data_packet_out[PW-1:0]),
.cfg_access_out (cfg_access_out),
.cfg_packet_out (cfg_packet_out[PW-1:0]),
// Inputs
.trace_clk (trace_clk),
.trace_trigger (trace_trigger),
.trace_vector (trace_vector[VW-1:0]),
.cfg_access_in (cfg_access_in),
.cfg_packet_in (cfg_packet_in[PW-1:0]));
endmodule // axi_etrace
// Local Variables:
// verilog-library-directories:("." "../../axi/hdl" "../../emesh/hdl")
// End:
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sdlclkp (
VPWR,
VGND,
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
input VPWR;
input VGND;
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire SCE_GATE ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (m0 , SCE_GATE, clkn, VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_V |
/*
Name: ClockRecoverSetCounter
Attempts to recover a clock from a serial signal whose frequency is known, set,
and equal to system clock frequency divided by some integer. Reclocked serial
data is then output along with a clock strobe.
Faster is pretty much always better for this type of function, so the clock
recovery system runs at system clock.
Target frequency is set by setting the TARGET_PERIOD value such that
f_target = f_clk / TARGET_PERIOD
*/
module ClkRecoverSetCounter #(
parameter TARGET_PERIOD = 10 ///< Expected # clks for recovered clock
)
(
// Inputs
input clk, ///< System clock
input rst, ///< Reset, synchronous and active high
input rx, ///< Input serial signal
// Outputs
output reg clkStrobe, ///< Recovered clock strobe
output reg rxClocked ///< Synchronized rx data
);
parameter PHASE_HIGH = $clog2(TARGET_PERIOD-1) - 1;
wire intClk; ///< Internal clock
reg [PHASE_HIGH:0] phaseAccum; ///< Phase accumulator for internal clock
reg intClkD1; ///< intClk delayed 1 clk
reg rxD1; ///< rx delayed 1 clk
reg started; ///< Goes high once first edge found
// Debug
wire refClk;
reg isZero;
assign refClk = (phaseAccum == 'd0) && ~isZero;
always @(posedge clk) begin
isZero <= phaseAccum == 'd0;
end
assign intClk = (phaseAccum == (TARGET_PERIOD>>1));
always @(posedge clk) begin
rxD1 <= rx;
intClkD1 <= intClk;
clkStrobe <= intClk & ~intClkD1;
rxClocked <= (intClk & ~intClkD1) ? rx : rxClocked;
end
// Phase accumulator and tracking loop
always @(posedge clk) begin
if (rst) begin
phaseAccum <= 'd0;
started <= 1'b0;
end
else begin
if (started) begin
// Phase lag - increase phase to catch up
if ((rxD1 ^ rx) && (phaseAccum >= (TARGET_PERIOD>>1))) begin
if (phaseAccum == TARGET_PERIOD-1) begin
phaseAccum <= 'd1;
end
else if (phaseAccum == TARGET_PERIOD-2) begin
phaseAccum <= 'd0;
end
else begin
phaseAccum <= phaseAccum + 2'd2;
end
end
// Phase lead - don't increment phase to slow down
else if ((rxD1 ^ rx) && (phaseAccum != 'd0)) begin
phaseAccum <= phaseAccum;
end
// In phase but lagging
else if (phaseAccum == TARGET_PERIOD-1) begin
phaseAccum <= 'd0;
end
else begin
phaseAccum <= phaseAccum + 2'd1;
end
end
else begin
started <= rxD1 ^ rx;
phaseAccum <= 'd0;
end
end
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_M_V
`define SKY130_FD_SC_LP__A2111OI_M_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_m (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_m (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_M_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_cmp35.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_cmp37
// Description:
// 37 bit comparator for MIL hit detection
*/
////////////////////////////////////////////////////////////////////////
module sparc_ifu_cmp35(/*AUTOARG*/
// Outputs
hit,
// Inputs
a, b, valid
);
input [34:0] a, b;
input valid;
output hit;
reg hit;
wire valid;
wire [34:0] a, b;
always @ (a or b or valid)
begin
if ((a==b) & valid)
hit = 1'b1;
else
hit = 1'b0;
end // always @ (a or b or valid)
endmodule // sparc_ifu_cmp35
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:03:37 10/29/2015
// Design Name:
// Module Name: ControllerReadTempI2C
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ControllerReadTempI2C(Clock,ClockI2C,Reset,SDA,Start,BaudEnable,Done,ReadOrWrite,Select,ShiftOrHold,StartStopAck,WriteLoad);
input Clock;
input ClockI2C;
input Reset;
input SDA;
input Start;
output BaudEnable;
output Done;
output ReadOrWrite;
output Select;
output ShiftOrHold;
output StartStopAck;
output WriteLoad;
reg [3:0] DataCounter;
reg [2:0] State;
reg [2:0] NextState;
parameter InitialState = 3'd0;
parameter LoadState = 3'd1;
parameter WriteState = 3'd2;
parameter ReadState = 3'd3;
wire OneShotNegative, OneShotPositive;
ClockedNegativeOneShot OneShotNegativeUnit(ClockI2C, OneShotNegative, Reset, clock);
ClockedPositiveOneShot OneShotPositiveUnit(ClockI2C, OneShotPositive, Reset, clock);
reg ACKbit;
always@(posedge clock)
if(Reset==1) begin State<=InitialState; ACKbit<=1; end
else begin
State<=NextState;
if(OneShotPositive==1) ACKbit<=SDA; else ACKbit<=ACKbit;
end
//count update
always@(posedge clock)
if(Reset==1) begin DataCounter<=4'd9; end
else case (State)
LoadState:
if(OneShotNegative==0) DataCounter<=DataCounter-1'b1;
else DataCounter<=DataCounter;
WriteState:
if(OneShotNegative==0) DataCounter<=DataCounter-1'b1;
else DataCounter<=DataCounter;
ReadState:
if(OneShotPositive==1) DataCounter<=DataCounter-1'b1;
else DataCounter<=DataCounter;
default: DataCounter<=4'd9;
endcase
endmodule |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : cabac_residual.v
// Author : guo yong
// Created : 2013-12
// Description : H.265 encode residual
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module cabac_residual(
//input
clk ,
rst_n ,
residual_en_i ,
mb_x_i ,
mb_y_i ,
slice_type_i ,
intra_luma_mode_i ,
intra_chroma_mode_i ,
cu_idx_i ,
cu_depth_i ,
cu_idx_minus1_i ,
cu_idx_minus5_i ,
cu_idx_minus21_i ,
cu_qp_i ,
luma_cbf_i ,
cr_cbf_i ,
cb_cbf_i ,
data_coeff_i ,
//output
addr_coeff_o ,
rd_en_coeff_o ,
residual_done_o ,
ctx_pair_residual0_o ,
ctx_pair_residual1_o ,
ctx_pair_residual2_o ,
ctx_pair_residual3_o ,
ctx_pair_residual4_o ,
ctx_pair_residual5_o ,
ctx_pair_residual6_o ,
ctx_pair_residual7_o ,
ctx_pair_residual8_o ,
ctx_pair_residual9_o ,
ctx_pair_residual10_o ,
ctx_pair_residual11_o ,
ctx_pair_residual12_o ,
ctx_pair_residual13_o ,
ctx_pair_residual14_o ,
ctx_pair_residual15_o ,
valid_num_residual_o
);
// **************************************************
//
// INPUT DECLARATION
//
// **************************************************
input clk ; //clock
input rst_n ; //reset, low active
input residual_en_i ; //residual enable
input [`PIC_X_WIDTH-1:0] mb_x_i ; //mb_x
input [`PIC_Y_WIDTH-1:0] mb_y_i ; //mb_y
input slice_type_i ; //slice_type_i
input [5:0] intra_luma_mode_i ; //intra_luma_mode_i
input [5:0] intra_chroma_mode_i ; //intra chroma mode
//have reversed in the upper story, 0: split, 1: unsplit
input [6:0] cu_idx_i ; //cu index
input [6:0] cu_idx_minus1_i ; //cu index minus 1
input [6:0] cu_idx_minus5_i ; //cu index minus 5
input [6:0] cu_idx_minus21_i ; //cu index minus 21
input [1:0] cu_depth_i ; //cu depth: 0~3
input [5:0] cu_qp_i ; //cu qp
input [`LCU_SIZE*`LCU_SIZE/16-1:0] luma_cbf_i ; //z-scan, reverse order
input [`LCU_SIZE*`LCU_SIZE/64-1:0] cr_cbf_i ; //z-scan, reverse order
input [`LCU_SIZE*`LCU_SIZE/64-1:0] cb_cbf_i ; //z-scan, reverse order
input [255:0] data_coeff_i ; //residual data of current block
// **************************************************
//
// OUTPUT DECLARATION
//
// **************************************************
output [8:0] addr_coeff_o ; //residual address of next block
output rd_en_coeff_o ; //read residual enable signal
output residual_done_o ; //residual encode done flag
output [4:0] valid_num_residual_o ; //valid number of residual
output [10:0] ctx_pair_residual0_o ; //ctx pair of residual bin 0
output [10:0] ctx_pair_residual1_o ; //ctx pair of residual bin 1
output [10:0] ctx_pair_residual2_o ; //ctx pair of residual bin 2
output [10:0] ctx_pair_residual3_o ; //ctx pair of residual bin 3
output [10:0] ctx_pair_residual4_o ; //ctx pair of residual bin 4
output [10:0] ctx_pair_residual5_o ; //ctx pair of residual bin 5
output [10:0] ctx_pair_residual6_o ; //ctx pair of residual bin 6
output [10:0] ctx_pair_residual7_o ; //ctx pair of residual bin 7
output [10:0] ctx_pair_residual8_o ; //ctx pair of residual bin 8
output [10:0] ctx_pair_residual9_o ; //ctx pair of residual bin 9
output [10:0] ctx_pair_residual10_o ; //ctx pair of residual bin 10
output [10:0] ctx_pair_residual11_o ; //ctx pair of residual bin 11
output [10:0] ctx_pair_residual12_o ; //ctx pair of residual bin 12
output [10:0] ctx_pair_residual13_o ; //ctx pair of residual bin 13
output [10:0] ctx_pair_residual14_o ; //ctx pair of residual bin 14
output [10:0] ctx_pair_residual15_o ; //ctx pair of residual bin 15
// **************************************************
//
// PARAMETER DECLARATION
//
// **************************************************
parameter RESIDUAL_IDLE = 4'd0,
RESIDUAL_ROOT_CBF = 4'd1,
RESIDUAL_CHROMA_CBF_ROOT = 4'd2,
RESIDUAL_SUB_DIV = 4'd3,
RESIDUAL_CHROMA_CBF = 4'd4,
RESIDUAL_LUMA_CBF = 4'd5,
RESIDUAL_DQP = 4'd6,
RESIDUAL_LUMA_COEFF = 4'd7,
RESIDUAL_CR_COEFF = 4'd8,
RESIDUAL_CB_COEFF = 4'd9,
RESIDUAL_END = 4'd10;
parameter TU_IDLE = 4'd0,
TU_SKIP_LAST_SIG = 4'd1,
TU_LAST_SIG_05 = 4'd2,
TU_LAST_SIG_0 = 4'd3,
TU_LAST_SIG = 4'd4,
TU_BLK_IDLE = 4'd5,
TU_BLK_CBF = 4'd6,
TU_SIG_FLAG = 4'd7,
TU_GE12 = 4'd8,
TU_RES_SIGN = 4'd9,
TU_RES_REMAIN = 4'd10,
TU_END = 4'd11;
// **************************************************
//
// REG DECLARATION
//
// **************************************************
reg [8:0] addr_coeff_o ; //residual address of next block
reg rd_en_coeff_o ; //read residual enable signal
reg residual_done_o ; //residual encode done flag
reg [4:0] valid_num_residual_o ; //valid number of residual
reg [10:0] ctx_pair_residual0_o ; //ctx pair of residual bin 0
reg [10:0] ctx_pair_residual1_o ; //ctx pair of residual bin 1
reg [10:0] ctx_pair_residual2_o ; //ctx pair of residual bin 2
reg [10:0] ctx_pair_residual3_o ; //ctx pair of residual bin 3
reg [10:0] ctx_pair_residual4_o ; //ctx pair of residual bin 4
reg [10:0] ctx_pair_residual5_o ; //ctx pair of residual bin 5
reg [10:0] ctx_pair_residual6_o ; //ctx pair of residual bin 6
reg [10:0] ctx_pair_residual7_o ; //ctx pair of residual bin 7
reg [10:0] ctx_pair_residual8_o ; //ctx pair of residual bin 8
reg [10:0] ctx_pair_residual9_o ; //ctx pair of residual bin 9
reg [10:0] ctx_pair_residual10_o ; //ctx pair of residual bin 10
reg [10:0] ctx_pair_residual11_o ; //ctx pair of residual bin 11
reg [10:0] ctx_pair_residual12_o ; //ctx pair of residual bin 12
reg [10:0] ctx_pair_residual13_o ; //ctx pair of residual bin 13
reg [10:0] ctx_pair_residual14_o ; //ctx pair of residual bin 14
reg [10:0] ctx_pair_residual15_o ; //ctx pair of residual bin 15
reg [3:0] res_curr_state_r ; //residual encode current state
reg [3:0] res_next_state_r ; //residual encode next state
reg [3:0] tu_curr_state_r ; //tu encode current state
reg [3:0] tu_next_state_r ; //tu encode next state
reg [1:0] tu_cnt_r ; //tu count reg
reg [1:0] tu_tot_r ; //tu total reg
reg qp_done_r ; //qp encode done flag
reg tu_done_r ; //tu encode done flag
reg residual_done_r ; //residual encode done flag
reg rd_e_done_r ; //read done of 4x4 block
reg scan_e_done_r ; //scan done of 4x4 block
reg enc_e_done_r ; //encoding done of 4x4 block
reg blk_e_done_r ; //block encoding done
wire rd_done_w ; //read one tu block
wire enc_done_w ; //encode one tu block
wire rd_bin_cbf_w ; //cbf of read blk coefficient
reg enc_bin_cbf_r ; //cbf of coding blk coefficient
reg [2:0] rd_cyc_cnt_r ; //read cycle count
reg [2:0] scan_cyc_cnt_r ; //scan cycle count
reg [1:0] enc_sig_cyc_cnt_r ; //sig cycle count
reg [1:0] enc_sig_cyc_tot_r ; //sig cycle total
reg [3:0] enc_sign_cyc_cnt_r ; //sign cycle count
reg [3:0] enc_sign_cyc_tot_r ; //sign cycle total
reg [3:0] enc_ge12_cyc_cnt_r ; //ge12 cycle count
reg [3:0] enc_ge12_cyc_tot_r ; //ge12 cycle total
reg [4:0] enc_remain_cnt_r ; //remain count
reg [4:0] enc_remain_tot_r ; //remain total
reg [3:0] enc_remain_cyc_cnt_r ; //remain cycle count
reg [3:0] enc_remain_cyc_tot_r ; //remain cycle total
wire enc_sign_done_w ; //sign encode done flag
wire enc_remain_done_w ; //remain encode done flag
reg [1:0] c1_r ; //c1_r
reg [5:0] blk_tot_r ; //block total number
reg [5:0] blk_cbf_idx_r ; //(4/16/64)-blk_tot_r, increase by on block
reg [5:0] rd_blk_cnt_r ; //read block count
reg [5:0] rd_blk_cnt_level_r ; //read block count level signal
reg [5:0] scan_blk_cnt_r ; //scan block count
reg [5:0] enc_blk_cnt_r ; //coding block count
reg [5:0] rd_blk_map_r ; //
reg [3:0] cu_luma_cbf_r ; //0: the first tu cbf, 1: the second tu cbf
//2: the third tu cbf, 3: the fourth tu cbf
reg [3:0] cu_cr_cbf_r ; //ditto
reg [3:0] cu_cb_cbf_r ; //ditto
reg [63:0] tu_luma_cbf_r ; //tu luma cbf
reg [15:0] tu_cr_cbf_r ; //tu cr cbf
reg [15:0] tu_cb_cbf_r ; //tu cb cbf
reg [63:0] tu_32x32_luma_cbf_r ; //tu 32x32 luma cbf
reg [15:0] tu_16x16_cr_cbf_r ; //tu 16x16 cr cbf
reg [15:0] tu_16x16_cb_cbf_r ; //tu 16x16 cb cbf
reg [15:0] tu_16x16_luma_cbf_r ; //tu 16x16 luma cbf
reg [3:0] tu_8x8_cr_cbf_r ; //tu 8x8 cr cbf
reg [3:0] tu_8x8_cb_cbf_r ; //tu 8x8 cb cbf
reg [3:0] tu_8x8_luma_cbf_r ; //tu 8x8 luma cbf
reg tu_4x4_cr_cbf_r ; //tu 4x4 cr cbf
reg tu_4x4_cb_cbf_r ; //tu 4x4 cb cbf
// **************************************************
//
// WIRE DECLARATION
//
// **************************************************
wire cbf_ne_zero_flag_w ; //cbf not equal zero
wire cbf_chroma_ne_zero_flag_w ; //cu_cr_cbf_r!=0 || cu_cb_cbf_r!=0
wire tu_en_w ; //tu enable flag
//res_curr_state_r==RESIDUAL_LUMA_COEFF ||
//res_curr_state_r==RESIDUAL_CR_COEFF ||
//res_curr_state_r==RESIDUAL_CB_COEFF ||
wire [7:0] cu_idx_minus1_shift6_minus1_w ;
// *********************************************************
// root_cbf
wire [10:0] ctx_pair_root_cbf_w ; //context pair of root cbf
reg valid_num_bin_root_cbf_r ; //valid number of root cbf
wire bin_string_root_cbf_w ; //bin_string of root cbf
wire [7:0] ctx_idx_root_cbf_w ; //context index of root cbf
// *********************************************************
// luma_cbf
wire [10:0] ctx_pair_luma_cbf_w ; //context pair of luma cbf
reg valid_num_bin_luma_cbf_r ; //valid number bin of luma cbf
reg bin_string_luma_cbf_r ; //bin string of luma cbf
reg [7:0] ctx_idx_luma_cbf_r ; //context index of luma cbf
// *********************************************************
// chroma_cbf
wire [10:0] ctx_pair_chroma_cbf_0_w ; //context pair of chroma_root_cbf
wire [10:0] ctx_pair_chroma_cbf_1_w ; //context pair of chroma_root_cbf
reg [1:0] valid_num_bin_chroma_cbf_r ; //valid number of chroma root cbf
wire [1:0] bin_string_chroma_cbf_w ; //bin string of chroma root cbf
wire [7:0] ctx_idx_chroma_cbf_0_w ; //context index of chroma root cbf
wire [7:0] ctx_idx_chroma_cbf_1_w ; //context index of chroma root cbf
// *********************************************************
// sub_div
wire [10:0] ctx_pair_sub_div_w ; //context pair of sub div
reg valid_num_bin_sub_div_r ; //valid number bin of sub div
reg bin_string_sub_div_r ; //bin string of sub div
reg [7:0] ctx_idx_sub_div_r ; //context index of sub div
// *********************************************************
// chroma_root_cbf
wire [10:0] ctx_pair_chroma_root_cbf_0_w ; //context pair of chroma_root_cbf
wire [10:0] ctx_pair_chroma_root_cbf_1_w ; //context pair of chroma_root_cbf
wire [1:0] valid_num_bin_chroma_root_cbf_w ; //valid number of chroma root cbf
wire [1:0] bin_string_chroma_root_cbf_w ; //bin string of chroma root cbf
wire [7:0] ctx_idx_chroma_root_cbf_0_w ; //context index of chroma root cbf
wire [7:0] ctx_idx_chroma_root_cbf_1_w ; //context index of chroma root cbf
// *********************************************************
// qp_delta
reg [10:0] ctx_pair_qp_delta_0_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_1_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_2_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_3_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_4_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_5_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_6_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_7_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_8_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_9_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_10_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_11_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_12_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_13_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_14_w ; //context pair of qp_delta
reg [10:0] ctx_pair_qp_delta_15_w ; //context pair of qp_delta
reg [3:0] valid_num_bin_qp_delta_r ; //valid number bin of qp_delta
reg [2:0] valid_num_bin_qp_delta_pre_r ; //valid number bin of qp_delta prefix
reg [3:0] valid_num_bin_qp_delta_suf_r ; //valid number bin of qp_delta suffix
reg [1:0] qp_delta_pre_cyc_tot_r ; //prefix cycle total
reg [2:0] qp_delta_suf_cyc_tot_r ; //suffix cycle total
reg [2:0] qp_delta_cyc_tot_r ; //total cycle
reg [2:0] qp_delta_cyc_cnt_r ; //total cycle count
reg [15:0] bin_string_qp_delta_r ; //bin string of qp_delta
reg [5:0] cu_qp_r ; //current cu qp
reg [5:0] cu_qp_left_r ; //left cu qp
reg [5:0] cu_qp_top_r ; //top cu qp
reg [5:0] cu_qp_last_r ; //last cu qp
reg [5:0] ref_qp_r ; //reference cu qp
reg signed [5:0] qp_delta_r ; //qp delta
reg [5:0] qp_delta_abs_r ; //qp delta abs
wire [5:0] qp_delta_abs_m5_w ; //qp delta abs minus 5
reg [2:0] tu_value_r ; //min(qp_delta_abs_r, 5)
reg qp_suffix_r ; //suffix flag
wire qp_delta_sign_w ; //qp delta sign
wire [5:0] qp_delta_abs_m5m1_w ;
wire [5:0] qp_delta_abs_m5m3_w ;
wire [5:0] qp_delta_abs_m5m7_w ;
wire [5:0] qp_delta_abs_m5m15_w ;
// ******************************************************
// transform_skip
wire [10:0] ctx_pair_transform_skip_w ; //context pair of transform_skip
wire [7:0] ctx_idx_transform_skip_w ; //context index of transform_skip
// *******************************************************
// last_significant_xy
wire [10:0] ctx_pair_last_x_prefix_0_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_1_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_2_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_3_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_4_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_5_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_6_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_7_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_8_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_prefix_9_w ; //context pair of last x prefix
wire [10:0] ctx_pair_last_x_suffix_0_w ; //context pair of last x suffix
wire [10:0] ctx_pair_last_x_suffix_1_w ; //context pair of last x suffix
wire [10:0] ctx_pair_last_x_suffix_2_w ; //context pair of last x suffix
wire [10:0] ctx_pair_last_y_prefix_0_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_1_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_2_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_3_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_4_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_5_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_6_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_7_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_8_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_prefix_9_w ; //context pair of last y prefix
wire [10:0] ctx_pair_last_y_suffix_0_w ; //context pair of last y suffix
wire [10:0] ctx_pair_last_y_suffix_1_w ; //context pair of last y suffix
wire [10:0] ctx_pair_last_y_suffix_2_w ; //context pair of last y suffix
reg [9:0] bin_string_last_x_prefix_r ; //bin string of last x prefix
reg [9:0] bin_string_last_y_prefix_r ; //bin string of last y prefix
reg [2:0] bin_string_last_x_suffix_r ; //bin string of last x suffix
reg [2:0] bin_string_last_y_suffix_r ; //bin string of last y prefix
wire [3:0] valid_num_bin_last_x_prefix_w ; //valid number of bin of last x prefix
wire [3:0] valid_num_bin_last_y_prefix_w ; //valid number of bin of last y prefix
reg [1:0] valid_num_bin_last_x_suffix_r ; //valid number of bin of last x suffix
reg [1:0] valid_num_bin_last_y_suffix_r ; //valid number of bin of last y suffix
reg [7:0] ctx_idx_last_x_prefix_0_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_1_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_2_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_3_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_4_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_5_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_6_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_7_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_8_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_x_prefix_9_r ; //context index of last x prefix
reg [7:0] ctx_idx_last_y_prefix_0_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_1_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_2_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_3_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_4_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_5_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_6_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_7_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_8_r ; //context index of last y prefix
reg [7:0] ctx_idx_last_y_prefix_9_r ; //context index of last y prefix
reg last_sig_enc_done_r ; //last sig encode done flag, next cycle is TU_BLK_IDLE
reg [3:0] last_x_prefix_cyc_tot_r ;
reg [3:0] last_y_prefix_cyc_tot_r ;
reg last_x_suffix_cyc_tot_r ;
reg last_y_suffix_cyc_tot_r ;
wire [3:0] last_xy_cyc_tot_w ;
reg [2:0] last_xy_cyc_cnt_r ;
reg [2:0] last_xy_r ; //00: last_x_prefix, 01: last_y_prefix
//10: last_x_suffix, 11: last_y_suffix
reg [4:0] pos_x_base_r ; //group index base of x
reg [4:0] pos_y_base_r ; //group index base of y
reg [3:0] pos_x_inc_r ; //group index increament of x
reg [3:0] pos_y_inc_r ; //group index increament of y
wire [4:0] pos_x_w ; //last coefficient x position
wire [4:0] pos_y_w ; //last coefficient y position
reg [2:0] pos_x_mar_r ; //pos_x_w-min_in_group[group_idx_x]
reg [2:0] pos_y_mar_r ; //pos_y_w-min_in_group[group_idx_y]
reg [3:0] group_idx_x_r ; //group index of x
reg [3:0] group_idx_y_r ; //group index of y
reg group_idx_x_1_r ; //group_idx_x_r < group_idx[width]?
reg group_idx_y_1_r ; //group_idx_y_r < group_idx[height]?
wire [255:0] last_blk_res_r ; //last blk residual flow the scan index,
//to find the last coeff position
// *********************************************************
// sub_blk_sig_flag
wire [10:0] ctx_pair_sub_blk_sig_w ; //context pair of sub block sig flag
wire bin_string_sub_blk_sig_r ; //bin of sub block sig flag
reg [7:0] ctx_idx_sub_blk_sig_r ; //context index of sub block sig flag
reg valid_num_bin_sub_blk_sig_r ; //valid number of bin of sub block sig flag
reg [1:0] ctx_sub_blk_sig_r ; //cbf_right | cbf_lower
// **********************************************************
// sig_flag
reg [10:0] ctx_pair_sig_flag_0_r ; //context pair of sig flag 0, final data
reg [10:0] ctx_pair_sig_flag_1_r ; //context pair of sig flag 1
reg [10:0] ctx_pair_sig_flag_2_r ; //context pair of sig flag 2
reg [10:0] ctx_pair_sig_flag_3_r ; //context pair of sig flag 3
reg [10:0] ctx_pair_sig_flag_4_r ; //context pair of sig flag 4
reg [10:0] ctx_pair_sig_flag_5_r ; //context pair of sig flag 5
reg [10:0] ctx_pair_sig_flag_6_r ; //context pair of sig flag 6
reg [10:0] ctx_pair_sig_flag_7_r ; //context pair of sig flag 7
reg [10:0] ctx_pair_sig_flag_8_r ; //context pair of sig flag 8
reg [10:0] ctx_pair_sig_flag_9_r ; //context pair of sig flag 9
reg [10:0] ctx_pair_sig_flag_10_r ; //context pair of sig flag 10
reg [10:0] ctx_pair_sig_flag_11_r ; //context pair of sig flag 11
reg [10:0] ctx_pair_sig_flag_12_r ; //context pair of sig flag 12
reg [10:0] ctx_pair_sig_flag_13_r ; //context pair of sig flag 13
reg [10:0] ctx_pair_sig_flag_14_r ; //context pair of sig flag 14
reg [10:0] ctx_pair_sig_flag_15_r ; //context pair of sig flag 15
wire [10:0] ctx_pair_sig_flag_0_w ; //context pair of sig flag 0
wire [10:0] ctx_pair_sig_flag_1_w ; //context pair of sig flag 1
wire [10:0] ctx_pair_sig_flag_2_w ; //context pair of sig flag 2
wire [10:0] ctx_pair_sig_flag_3_w ; //context pair of sig flag 3
wire [10:0] ctx_pair_sig_flag_4_w ; //context pair of sig flag 4
wire [10:0] ctx_pair_sig_flag_5_w ; //context pair of sig flag 5
wire [10:0] ctx_pair_sig_flag_6_w ; //context pair of sig flag 6
wire [10:0] ctx_pair_sig_flag_7_w ; //context pair of sig flag 7
wire [10:0] ctx_pair_sig_flag_8_w ; //context pair of sig flag 8
wire [10:0] ctx_pair_sig_flag_9_w ; //context pair of sig flag 9
wire [10:0] ctx_pair_sig_flag_10_w ; //context pair of sig flag 10
wire [10:0] ctx_pair_sig_flag_11_w ; //context pair of sig flag 11
wire [10:0] ctx_pair_sig_flag_12_w ; //context pair of sig flag 12
wire [10:0] ctx_pair_sig_flag_13_w ; //context pair of sig flag 13
wire [10:0] ctx_pair_sig_flag_14_w ; //context pair of sig flag 14
wire [10:0] ctx_pair_sig_flag_15_w ; //context pair of sig flag 15
reg [15:0] bin_string_sig_flag_r ; //bin string of sig flag
reg [4:0] valid_num_bin_sig_flag_r ; //valid number bin of sig flag
reg [7:0] ctx_idx_sig_flag_0_r ; //context index of sig flag 0
reg [7:0] ctx_idx_sig_flag_1_r ; //context index of sig flag 1
reg [7:0] ctx_idx_sig_flag_2_r ; //context index of sig flag 2
reg [7:0] ctx_idx_sig_flag_3_r ; //context index of sig flag 3
reg [7:0] ctx_idx_sig_flag_4_r ; //context index of sig flag 4
reg [7:0] ctx_idx_sig_flag_5_r ; //context index of sig flag 5
reg [7:0] ctx_idx_sig_flag_6_r ; //context index of sig flag 6
reg [7:0] ctx_idx_sig_flag_7_r ; //context index of sig flag 7
reg [7:0] ctx_idx_sig_flag_8_r ; //context index of sig flag 8
reg [7:0] ctx_idx_sig_flag_9_r ; //context index of sig flag 9
reg [7:0] ctx_idx_sig_flag_10_r ; //context index of sig flag 10
reg [7:0] ctx_idx_sig_flag_11_r ; //context index of sig flag 11
reg [7:0] ctx_idx_sig_flag_12_r ; //context index of sig flag 12
reg [7:0] ctx_idx_sig_flag_13_r ; //context index of sig flag 13
reg [7:0] ctx_idx_sig_flag_14_r ; //context index of sig flag 14
reg [7:0] ctx_idx_sig_flag_15_r ; //context index of sig flag 15
// **********************************************************
// ge12
wire [10:0] ctx_pair_ge12_0_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_1_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_2_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_3_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_4_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_5_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_6_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_7_w ; //context pair of coefficient ge12
wire [10:0] ctx_pair_ge12_8_w ; //context pair of coefficient ge12
reg [8:0] bin_string_ge12_r ; //bin string of coefficients ge12
wire [3:0] valid_num_bin_ge12_r ; //valid number of coefficients ge12
reg [7:0] ctx_idx_ge12_0_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_1_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_2_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_3_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_4_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_5_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_6_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_7_r ; //context index of coefficient ge12
reg [7:0] ctx_idx_ge12_8_r ; //context index of coefficient ge12
reg coeff_ge1_r ; //some coefficients greater 1
reg coeff_ge2_r ; //some coefficients greater 2
reg [1:0] i_ctx_set_r ; //i_ctx_set_r
// *********************************************************
// coefficient signs
wire [10:0] ctx_pair_sign_0_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_1_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_2_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_3_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_4_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_5_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_6_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_7_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_8_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_9_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_10_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_11_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_12_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_13_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_14_w ; //context pair of coefficient sign
wire [10:0] ctx_pair_sign_15_w ; //context pair of coefficient sign
wire [4:0] valid_num_bin_sign_r ; //valid number of sign bin
wire [15:0] bin_string_sign_flag_r ; //bin string of sign
// **********************************************************
// coefficient remains
wire [10:0] ctx_pair_remain_0_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_1_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_2_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_3_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_4_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_5_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_6_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_7_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_8_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_9_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_10_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_11_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_12_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_13_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_14_w ; //ctx_pair_remain_0_w
wire [10:0] ctx_pair_remain_15_w ; //ctx_pair_remain_0_w
reg [4:0] valid_num_remain_r ; //valid_num_remain_r
reg [15:0] bin_string_remain_r ; //bin string of remains
reg [31:0] bin_string_remain_all_r ; //bin string of remain all bins
reg [4:0] valid_num_remain_all_r ; //valid num of remain all bins
reg [3:0] first_non_one_coeff_idx_r ; //first greater-one coeff_abs
reg [1:0] base_level_r ; //base_level_r
reg [2:0] i_go_rice_param_r ; //i_go_rice_param_r
reg [15:0] encoding_coeff_abs_r ; //coefficient abs
reg [15:0] encoding_coeff_abs_remain_r ; //coefficient abs remain
reg [1:0] scan_idx_r ; //scan mode, 0: SCAN_DIAG, 1: SCAN_HOR, 2: SCAN_VER;
wire [63:0] tu_cbf_z2s_luma32x32_w ; //zcan-to-scan mode cbf, scan mode based on intra mode
wire [15:0] tu_cbf_z2s_luma16x16_w ;
reg [3:0] tu_cbf_z2s_luma8x8_r ;
wire [63:0] tu_cbf_z2s_luma32x32_rer_w ; //righter
wire [15:0] tu_cbf_z2s_luma16x16_rer_w ; //righter
reg [3:0] tu_cbf_z2s_luma8x8_rer_r ; //righter
wire [63:0] tu_cbf_z2s_luma32x32_ler_w ; //lower
wire [15:0] tu_cbf_z2s_luma16x16_ler_w ; //lower
reg [3:0] tu_cbf_z2s_luma8x8_ler_r ; //lower
wire [15:0] tu_cbf_z2s_cr16x16_w ; //zcan-to-scan mode cbf, scan mode based on intra mode
wire [3:0] tu_cbf_z2s_cr8x8_w ;
wire tu_cbf_z2s_cr4x4_w ;
wire [15:0] tu_cbf_z2s_cr16x16_rer_w ; //righter
wire [3:0] tu_cbf_z2s_cr8x8_rer_w ; //righter
wire tu_cbf_z2s_cr4x4_rer_w ; //righter
wire [15:0] tu_cbf_z2s_cr16x16_ler_w ; //lower
wire [3:0] tu_cbf_z2s_cr8x8_ler_w ; //lower
wire tu_cbf_z2s_cr4x4_ler_w ; //lower
wire [15:0] tu_cbf_z2s_cb16x16_w ; //zcan-to-scan mode cbf, scan mode based on intra mode
wire [3:0] tu_cbf_z2s_cb8x8_w ;
wire tu_cbf_z2s_cb4x4_w ;
wire [15:0] tu_cbf_z2s_cb16x16_rer_w ; //righter
wire [3:0] tu_cbf_z2s_cb8x8_rer_w ; //righter
wire tu_cbf_z2s_cb4x4_rer_w ; //righter
wire [15:0] tu_cbf_z2s_cb16x16_ler_w ; //lower
wire [3:0] tu_cbf_z2s_cb8x8_ler_w ; //lower
wire tu_cbf_z2s_cb4x4_ler_w ; //lower
reg [5:0] last_cbf_idx_r ; //last non_zero cbf idx
reg [7:0] last_cbf_0_r ; //cbf split into sub
reg [7:0] last_cbf_1_r ; //cbf split into sub
reg [7:0] last_cbf_2_r ; //cbf split into sub
reg [7:0] last_cbf_3_r ; //cbf split into sub
reg [7:0] last_cbf_4_r ; //cbf split into sub
reg [7:0] last_cbf_5_r ; //cbf split into sub
reg [7:0] last_cbf_6_r ; //cbf split into sub
reg [7:0] last_cbf_7_r ; //cbf split into sub
reg [5:0] last_blk_idx_0_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_1_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_2_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_3_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_4_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_5_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_6_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_7_r ; //last non zero block idx in sub
reg [5:0] last_blk_idx_r ; //last non zero block idx
reg [1:0] tu_width_flag_r ; //0: 32, 1: 16, 2: 8, 3: 4
//read & encode
reg [4:0] rd_non_zero_num_r ; //read non_zero number
reg [4:0] enc_coeff_tot_r ; //encode non_zero_number
reg [3:0] rd_res_idx_r [15:0] ; //non-zero residual data index when Scanning
reg [3:0] enc_res_idx_r [15:0] ; //non-zero residual data index when encoding
reg [255:0] scan_res_data_r ; //residual data when scaning
reg [15:0] enc_res_data_r [15:0] ; //residual data when encoding
wire [15:0] enc_non_zero_0_w ; //non_zero_coefficient 0
wire [15:0] enc_non_zero_1_w ; //non_zero_coefficient 1
wire [15:0] enc_non_zero_2_w ; //non_zero_coefficient 2
wire [15:0] enc_non_zero_3_w ; //non_zero_coefficient 3
wire [15:0] enc_non_zero_4_w ; //non_zero_coefficient 4
wire [15:0] enc_non_zero_5_w ; //non_zero_coefficient 5
wire [15:0] enc_non_zero_6_w ; //non_zero_coefficient 6
wire [15:0] enc_non_zero_7_w ; //non_zero_coefficient 7
wire [15:0] enc_non_zero_8_w ; //non_zero_coefficient 8
wire [15:0] enc_non_zero_9_w ; //non_zero_coefficient 9
wire [15:0] enc_non_zero_10_w ; //non_zero_coefficient 10
wire [15:0] enc_non_zero_11_w ; //non_zero_coefficient 11
wire [15:0] enc_non_zero_12_w ; //non_zero_coefficient 12
wire [15:0] enc_non_zero_13_w ; //non_zero_coefficient 13
wire [15:0] enc_non_zero_14_w ; //non_zero_coefficient 14
wire [15:0] enc_non_zero_15_w ; //non_zero_coefficient 15
wire [15:0] enc_non_zero_abs_0_r ; //non_zero_coefficient 0
wire [15:0] enc_non_zero_abs_1_r ; //non_zero_coefficient 1
wire [15:0] enc_non_zero_abs_2_r ; //non_zero_coefficient 2
wire [15:0] enc_non_zero_abs_3_r ; //non_zero_coefficient 3
wire [15:0] enc_non_zero_abs_4_r ; //non_zero_coefficient 4
wire [15:0] enc_non_zero_abs_5_r ; //non_zero_coefficient 5
wire [15:0] enc_non_zero_abs_6_r ; //non_zero_coefficient 6
wire [15:0] enc_non_zero_abs_7_r ; //non_zero_coefficient 7
wire [15:0] enc_non_zero_abs_8_r ; //non_zero_coefficient 8
wire [15:0] enc_non_zero_abs_9_r ; //non_zero_coefficient 9
wire [15:0] enc_non_zero_abs_10_r ; //non_zero_coefficient 10
wire [15:0] enc_non_zero_abs_11_r ; //non_zero_coefficient 11
wire [15:0] enc_non_zero_abs_12_r ; //non_zero_coefficient 12
wire [15:0] enc_non_zero_abs_13_r ; //non_zero_coefficient 13
wire [15:0] enc_non_zero_abs_14_r ; //non_zero_coefficient 14
wire [15:0] enc_non_zero_abs_15_r ; //non_zero_coefficient 15
wire enc_non_zero_abs_0_ge1_r ; //non_zero_coefficient 0 > 1
wire enc_non_zero_abs_1_ge1_r ; //non_zero_coefficient 1 > 1
wire enc_non_zero_abs_2_ge1_r ; //non_zero_coefficient 2 > 1
wire enc_non_zero_abs_3_ge1_r ; //non_zero_coefficient 3 > 1
wire enc_non_zero_abs_4_ge1_r ; //non_zero_coefficient 4 > 1
wire enc_non_zero_abs_5_ge1_r ; //non_zero_coefficient 5 > 1
wire enc_non_zero_abs_6_ge1_r ; //non_zero_coefficient 6 > 1
wire enc_non_zero_abs_7_ge1_r ; //non_zero_coefficient 7 > 1
wire enc_non_zero_abs_0_ge2_r ; //non_zero_coefficient 0 > 2
wire enc_non_zero_abs_1_ge2_r ; //non_zero_coefficient 1 > 2
wire enc_non_zero_abs_2_ge2_r ; //non_zero_coefficient 2 > 2
wire enc_non_zero_abs_3_ge2_r ; //non_zero_coefficient 3 > 2
wire enc_non_zero_abs_4_ge2_r ; //non_zero_coefficient 4 > 2
wire enc_non_zero_abs_5_ge2_r ; //non_zero_coefficient 5 > 2
wire enc_non_zero_abs_6_ge2_r ; //non_zero_coefficient 6 > 2
wire enc_non_zero_abs_7_ge2_r ; //non_zero_coefficient 7 > 2
reg [15:0] coeff_a_r ; //coeff_a_r
reg [15:0] coeff_b_r ; //coeff_b_r
reg [1:0] coeff_a_b_r ; //00: coeff_a_r==0, coeff_b_r==0;
//01: coeff_a_r==0, coeff_b_r!=0; //10: coeff_a_r!=0, coeff_b_r==0;
//11: coeff_a_r!=0, coeff_b_r!=0; //10: coeff_a_r!=0, coeff_b_r==0;
reg rd_last_find_flag_r ; //find the last non_zero coefficient //11: coeff_a_r!=0, coeff_b_r!=0;
reg [3:0] rd_last_coeff_idx_r ; //last non-zero coefficient index
reg [3:0] enc_last_coeff_idx_r ; //last non-zero coefficient index
wire [15:0] rd_coeff_sig_w ; //rd 16 sig of coefficients
reg [15:0] enc_coeff_sig_r ; //enc 16 sig of coefficients
reg [1:0] enc_pattern_sig_ctx_r ; //sig_right + (sig_lower<<1)
reg sig_right_blk_r ; //sig_right
reg sig_lower_blk_r ; //sig_lower
//cbf!=0 flag
assign cbf_ne_zero_flag_w = (cu_luma_cbf_r!='d0 || cu_cr_cbf_r!='d0 || cu_cb_cbf_r!='d0);
assign cbf_chroma_ne_zero_flag_w = (cu_cr_cbf_r!='d0 || cu_cb_cbf_r!='d0);
//tu_en_w
assign tu_en_w = (res_curr_state_r==RESIDUAL_LUMA_COEFF
|| res_curr_state_r==RESIDUAL_CR_COEFF
|| res_curr_state_r==RESIDUAL_CB_COEFF);
wire [8:0] base_01_w ;
wire [8:0] base_02_w ;
wire [8:0] base_03_w ;
wire [8:0] base_04_w ;
wire [8:0] base_11_w ;
wire [8:0] base_12_w ;
wire [8:0] base_13_w ;
wire [8:0] base_14_w ;
wire [8:0] base_chroma_w ;
wire [8:0] base_cr_w ;
wire [8:0] base_cb_w ;
wire [8:0] base_21_w ;
wire [8:0] base_22_w ;
wire [8:0] base_23_w ;
wire [8:0] base_24_w ;
assign base_01_w = tu_cnt_r;
assign base_02_w = cu_idx_minus1_i;
assign base_03_w = cu_idx_minus5_i;
assign base_04_w = cu_idx_minus21_i;
assign base_11_w = base_01_w << 6;
assign base_12_w = base_02_w << 6;
assign base_13_w = base_03_w << 4;
assign base_14_w = base_04_w << 2;
assign base_chroma_w = rd_blk_map_r;
assign base_cr_w = base_chroma_w + 'd256;
assign base_cb_w = base_chroma_w + 'd320;
assign base_21_w = base_01_w << 4;
assign base_22_w = base_02_w << 4;
assign base_23_w = base_03_w << 2;
assign base_24_w = base_04_w ;
//addr_coeff_o
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
addr_coeff_o <= 'd0;
else if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0: addr_coeff_o <= rd_blk_map_r + base_11_w;
'd1: addr_coeff_o <= rd_blk_map_r + base_12_w;
'd2: addr_coeff_o <= rd_blk_map_r + base_13_w;
'd3: addr_coeff_o <= rd_blk_map_r + base_14_w;
default:addr_coeff_o <= 'd0;
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF) begin
case(cu_depth_i)
'd0: addr_coeff_o <= base_cr_w + base_21_w;
'd1: addr_coeff_o <= base_cr_w + base_22_w;
'd2: addr_coeff_o <= base_cr_w + base_23_w;
'd3: addr_coeff_o <= base_cr_w + base_24_w;
default:addr_coeff_o <= 'd0;
endcase
end
else if(res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0: addr_coeff_o <= base_cb_w + base_21_w;
'd1: addr_coeff_o <= base_cb_w + base_22_w;
'd2: addr_coeff_o <= base_cb_w + base_23_w;
'd3: addr_coeff_o <= base_cb_w + base_24_w;
default:addr_coeff_o <= 'd0;
endcase
end
else begin
addr_coeff_o <= 'd0;
end
end
//rd_en_coeff_o
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rd_en_coeff_o <= 'd0;
else if(blk_e_done_r || tu_curr_state_r==TU_LAST_SIG_05)
rd_en_coeff_o <= 'd1;
else
rd_en_coeff_o <= 'd0;
end
//state machine
//res_curr_state_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
res_curr_state_r <= RESIDUAL_IDLE;
else
res_curr_state_r <= res_next_state_r;
end
//res_next_state_r
always @* begin
if(~residual_en_i)
res_next_state_r = RESIDUAL_IDLE;
else begin
case(res_curr_state_r)
RESIDUAL_IDLE: begin
if(slice_type_i==(`SLICE_TYPE_P))
res_next_state_r = RESIDUAL_ROOT_CBF;
else if(cu_depth_i!='d0)
res_next_state_r = RESIDUAL_SUB_DIV;
else if(cbf_chroma_ne_zero_flag_w)
res_next_state_r = RESIDUAL_CHROMA_CBF_ROOT;
else
res_next_state_r = RESIDUAL_SUB_DIV;
end
RESIDUAL_ROOT_CBF: begin
if(~cbf_ne_zero_flag_w)
res_next_state_r = RESIDUAL_END;
else if(cu_depth_i!='d0)
res_next_state_r = RESIDUAL_SUB_DIV;
else if(cbf_chroma_ne_zero_flag_w)
res_next_state_r = RESIDUAL_CHROMA_CBF_ROOT;
else
res_next_state_r = RESIDUAL_SUB_DIV;
end
RESIDUAL_CHROMA_CBF_ROOT: begin
if(cu_depth_i=='d0)
res_next_state_r = RESIDUAL_SUB_DIV;
else if(slice_type_i==(`SLICE_TYPE_P) && cu_depth_i!='d0 &&
cu_cr_cbf_r=='d0 && cu_cb_cbf_r=='d0 && tu_cnt_r=='d0)
res_next_state_r = RESIDUAL_DQP;
else
res_next_state_r = RESIDUAL_LUMA_CBF;
end
RESIDUAL_SUB_DIV: begin
if((cu_depth_i!='d0))
res_next_state_r = RESIDUAL_CHROMA_CBF_ROOT;
else if(cu_depth_i=='d0 &&
(cu_cr_cbf_r!='d0 || cu_cb_cbf_r!='d0))
res_next_state_r = RESIDUAL_CHROMA_CBF;
else if((slice_type_i==(`SLICE_TYPE_I)) ||
(cu_depth_i=='d0) ||
(cbf_chroma_ne_zero_flag_w))
res_next_state_r = RESIDUAL_LUMA_CBF;
else if(cbf_ne_zero_flag_w && tu_cnt_r=='d0)
res_next_state_r = RESIDUAL_DQP;
else if(cu_luma_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_LUMA_COEFF;
else if(cu_cr_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CR_COEFF;
else if(cu_cb_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CB_COEFF;
else
res_next_state_r = RESIDUAL_END;
end
RESIDUAL_CHROMA_CBF: begin
if((slice_type_i==(`SLICE_TYPE_I)) ||
(cu_depth_i=='d0) ||
(cbf_chroma_ne_zero_flag_w))
res_next_state_r = RESIDUAL_LUMA_CBF;
else if(cbf_ne_zero_flag_w && tu_cnt_r=='d0)
res_next_state_r = RESIDUAL_DQP;
else if(cu_luma_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_LUMA_COEFF;
else if(cu_cr_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CR_COEFF;
else if(cu_cb_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CB_COEFF;
else
res_next_state_r = RESIDUAL_END;
end
RESIDUAL_LUMA_CBF: begin
if(cbf_ne_zero_flag_w && tu_cnt_r=='d0)
res_next_state_r = RESIDUAL_DQP;
else if(cu_luma_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_LUMA_COEFF;
else if(cu_cr_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CR_COEFF;
else if(cu_cb_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CB_COEFF;
else
res_next_state_r = RESIDUAL_END;
end
RESIDUAL_DQP: begin
if(qp_done_r) begin
if(cu_luma_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_LUMA_COEFF;
else if(cu_cr_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CR_COEFF;
else if(cu_cb_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CB_COEFF;
else
res_next_state_r = RESIDUAL_END;
end
else
res_next_state_r = res_curr_state_r;
end
RESIDUAL_LUMA_COEFF: begin
if(tu_done_r) begin
if(cu_cr_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CR_COEFF;
else if(cu_cb_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CB_COEFF;
else
res_next_state_r = RESIDUAL_END;
end
else
res_next_state_r = res_curr_state_r;
end
RESIDUAL_CR_COEFF: begin
if(tu_done_r) begin
if(cu_cb_cbf_r[tu_cnt_r])
res_next_state_r = RESIDUAL_CB_COEFF;
else
res_next_state_r = RESIDUAL_END;
end
else
res_next_state_r = res_curr_state_r;
end
RESIDUAL_CB_COEFF: begin
if(tu_done_r)
res_next_state_r = RESIDUAL_END;
else
res_next_state_r = res_curr_state_r;
end
RESIDUAL_END: begin
if(tu_cnt_r==tu_tot_r)
res_next_state_r = RESIDUAL_IDLE;
else
res_next_state_r = RESIDUAL_SUB_DIV;
end
default: begin
res_next_state_r = RESIDUAL_IDLE;
end
endcase
end
end
//tu_curr_state_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
tu_curr_state_r <= TU_IDLE;
else
tu_curr_state_r <= tu_next_state_r;
end
//tu_next_state_r
always @* begin
if(~tu_en_w)
tu_next_state_r = TU_IDLE;
else begin
case(tu_curr_state_r)
TU_IDLE: begin
if(tu_en_w) begin
if((res_curr_state_r==RESIDUAL_CR_COEFF || res_curr_state_r==RESIDUAL_CB_COEFF)
&& cu_depth_i==3)
tu_next_state_r = TU_SKIP_LAST_SIG;
else
tu_next_state_r = TU_LAST_SIG_05;
end
else
tu_next_state_r = tu_curr_state_r;
end
TU_SKIP_LAST_SIG: begin
tu_next_state_r = TU_LAST_SIG_05;
end
TU_LAST_SIG_05: begin
tu_next_state_r = TU_LAST_SIG_0;
end
TU_LAST_SIG_0: begin
if(rd_cyc_cnt_r=='d7)
tu_next_state_r = TU_LAST_SIG;
else
tu_next_state_r = tu_curr_state_r;
end
TU_LAST_SIG: begin
if(blk_e_done_r)
tu_next_state_r = TU_BLK_IDLE;
else
tu_next_state_r = tu_curr_state_r;
end
TU_BLK_IDLE: begin
if(enc_e_done_r)
tu_next_state_r = tu_curr_state_r;
else
tu_next_state_r = TU_BLK_CBF;
end
TU_BLK_CBF: begin
if(enc_bin_cbf_r || enc_blk_cnt_r==blk_tot_r)
tu_next_state_r = TU_SIG_FLAG;
else if(enc_done_w)
tu_next_state_r = TU_END;
else
tu_next_state_r = TU_BLK_IDLE;
end
TU_SIG_FLAG: begin
if(enc_sig_cyc_cnt_r==enc_sig_cyc_tot_r)
tu_next_state_r = TU_GE12;
else
tu_next_state_r = tu_curr_state_r;
end
TU_GE12: begin
if(enc_ge12_cyc_cnt_r==enc_ge12_cyc_tot_r) begin
tu_next_state_r = TU_RES_SIGN;
end
else
tu_next_state_r = tu_curr_state_r;
end
TU_RES_SIGN: begin
if(enc_sign_done_w) begin
if(coeff_ge1_r=='d1 || enc_coeff_tot_r>'d8)
tu_next_state_r = TU_RES_REMAIN;
else if(enc_done_w)
tu_next_state_r = TU_END;
else
tu_next_state_r = TU_BLK_IDLE;
end
else
tu_next_state_r = tu_curr_state_r;
end
TU_RES_REMAIN: begin
if(enc_remain_done_w) begin
if(enc_done_w)
tu_next_state_r = TU_END;
else
tu_next_state_r = TU_BLK_IDLE;
end
else
tu_next_state_r = tu_curr_state_r;
end
TU_END: begin
tu_next_state_r = TU_IDLE;
end
default: begin
tu_next_state_r = TU_IDLE;
end
endcase
end
end
//tu_tot_r
always @* begin
if(cu_depth_i=='d0)
tu_tot_r = 'd3;
else
tu_tot_r = 'd0;
end
//tu_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
tu_cnt_r <= 'd0;
else if(res_curr_state_r==RESIDUAL_END) begin
if(tu_cnt_r==tu_tot_r)
tu_cnt_r <= 'd0;
else
tu_cnt_r <= tu_cnt_r + 'd1;
end
else
tu_cnt_r <= tu_cnt_r;
end
//tu_done_r
always @* begin
if(tu_curr_state_r==TU_END)
tu_done_r = 'd1;
else
tu_done_r = 'd0;
end
//rd_done_w
assign rd_done_w = (rd_blk_cnt_r==blk_tot_r && blk_e_done_r=='d1) ? 1 : 0;
//enc_done_w
assign enc_done_w = (enc_blk_cnt_r==blk_tot_r && enc_e_done_r=='d1) ? 1 : 0;
//rd_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rd_cyc_cnt_r <= 'd0;
else if(~tu_en_w)
rd_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_05 || tu_done_r || blk_e_done_r)
rd_cyc_cnt_r <= 'd0;
else if(rd_cyc_cnt_r=='d7)
rd_cyc_cnt_r <= rd_cyc_cnt_r;
else
rd_cyc_cnt_r <= rd_cyc_cnt_r + 'd1;
end
//scan_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
scan_cyc_cnt_r <= 'd0;
else if(~tu_en_w)
scan_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0 || tu_done_r)
scan_cyc_cnt_r <= 'd0;
else if(~rd_bin_cbf_w)
scan_cyc_cnt_r <= 'd0;
else if(blk_e_done_r)
scan_cyc_cnt_r <= 'd0;
else if(scan_cyc_cnt_r=='d7 && (~blk_e_done_r))
scan_cyc_cnt_r <= scan_cyc_cnt_r;
else
scan_cyc_cnt_r <= scan_cyc_cnt_r + 'd1;
end
//rd_e_done_r
always @* begin
if(~tu_en_w)
rd_e_done_r = 'd0;
else if(tu_curr_state_r==TU_IDLE ||
tu_curr_state_r==TU_SKIP_LAST_SIG ||
tu_curr_state_r==TU_LAST_SIG_05 ||
tu_curr_state_r==TU_END)
rd_e_done_r = 'd0;
else if(rd_cyc_cnt_r=='d7)
rd_e_done_r = 'd1;
else if(scan_blk_cnt_r==blk_tot_r &&
rd_blk_cnt_r=='d0 &&
tu_curr_state_r!=TU_LAST_SIG_0)
rd_e_done_r = 'd1;
else
rd_e_done_r = 'd0;
end
//scan_e_done_r
always @* begin
if(~tu_en_w)
scan_e_done_r = 'd0;
else if(tu_curr_state_r==TU_IDLE ||
tu_curr_state_r==TU_SKIP_LAST_SIG ||
tu_curr_state_r==TU_LAST_SIG_05 ||
// tu_curr_state_r==TU_LAST_SIG_0 ||
tu_curr_state_r==TU_END)
scan_e_done_r = 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0 && rd_cyc_cnt_r=='d7)
scan_e_done_r = 'd1;
else if(~rd_bin_cbf_w || scan_cyc_cnt_r=='d7)
scan_e_done_r = 'd1;
else if(enc_blk_cnt_r==blk_tot_r &&
scan_blk_cnt_r=='d0 &&
tu_curr_state_r!=TU_LAST_SIG_0 &&
tu_curr_state_r!=TU_LAST_SIG)
scan_e_done_r = 'd1;
else
scan_e_done_r = 'd0;
end
reg enc_e_done_0_r ;
reg enc_e_done_1_r ;
//enc_e_done_0_r
always @* begin
if(~tu_en_w)
enc_e_done_0_r = 0;
else if(tu_curr_state_r==TU_IDLE
|| tu_curr_state_r==TU_SKIP_LAST_SIG
|| tu_curr_state_r==TU_LAST_SIG_05
// || tu_curr_state_r==TU_LAST_SIG_0
|| tu_curr_state_r==TU_END
|| tu_curr_state_r==TU_BLK_IDLE)
enc_e_done_0_r = 0;
else if(tu_curr_state_r==TU_LAST_SIG_0 && rd_cyc_cnt_r=='d7)
enc_e_done_0_r = 'd1;
else if(~enc_bin_cbf_r && enc_blk_cnt_r!=blk_tot_r)
enc_e_done_0_r = 1;
else if((tu_curr_state_r==TU_LAST_SIG && last_sig_enc_done_r)
|| (tu_curr_state_r==TU_RES_SIGN && enc_sign_done_w && (~(coeff_ge1_r=='d1 || enc_coeff_tot_r>'d8)))
|| (tu_curr_state_r==TU_RES_REMAIN && enc_remain_done_w))
enc_e_done_0_r = 1;
else
enc_e_done_0_r = 0;
end
//enc_e_done_1_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_e_done_1_r <= 'd0;
else if(enc_e_done_r && ((~rd_e_done_r) || (~scan_e_done_r)))
enc_e_done_1_r <= 'd1;
else
enc_e_done_1_r <= 'd0;
end
//enc_e_done_r
always @* begin
if(tu_en_w)
enc_e_done_r = enc_e_done_0_r | enc_e_done_1_r;
else
enc_e_done_r = 'd0;
end
//blk_e_done_r
always @* begin
if(rd_e_done_r && enc_e_done_r && scan_e_done_r)
blk_e_done_r = 'd1;
else
blk_e_done_r = 'd0;
end
//rd_bin_cbf_w
assign rd_bin_cbf_w = (scan_res_data_r=='d0) ? 'd0 : 'd1;
//enc_bin_cbf_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_bin_cbf_r <= 'd0;
else if(blk_e_done_r)
enc_bin_cbf_r <= rd_bin_cbf_w;
else
enc_bin_cbf_r <= enc_bin_cbf_r;
end
//residual_done_o
always @* begin
if(residual_en_i)
residual_done_o = residual_done_r;
else
residual_done_o = 'd0;
end
//residual_done_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
residual_done_r <= 'd0;
else if(res_curr_state_r==RESIDUAL_END
&& tu_cnt_r==tu_tot_r)
residual_done_r <= 'd1;
else
residual_done_r <= 'd0;
end
//rd_blk_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rd_blk_cnt_r <= 'd0;
else if(tu_curr_state_r==TU_IDLE)
rd_blk_cnt_r <= 'd0;
else if(blk_e_done_r) begin
if(rd_blk_cnt_r==blk_tot_r || scan_blk_cnt_r==blk_tot_r)
rd_blk_cnt_r <= 'd0;
else
rd_blk_cnt_r <= rd_blk_cnt_r + 'd1;
end
else
rd_blk_cnt_r <= rd_blk_cnt_r;
end
//scan_blk_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
scan_blk_cnt_r <= 'd0;
else if(tu_curr_state_r==TU_IDLE)
scan_blk_cnt_r <= 'd0;
else if(blk_e_done_r) begin
if(scan_blk_cnt_r==blk_tot_r)
scan_blk_cnt_r <= 'd0;
else
scan_blk_cnt_r <= rd_blk_cnt_r;
end
else
scan_blk_cnt_r <= scan_blk_cnt_r;
end
//enc_blk_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_blk_cnt_r <= 'd0;
else if(tu_curr_state_r==TU_IDLE)
enc_blk_cnt_r <= 'd0;
else if(blk_e_done_r)
enc_blk_cnt_r <= scan_blk_cnt_r;
else
enc_blk_cnt_r <= enc_blk_cnt_r;
end
//rd_blk_cnt_level_r
always @* begin
if(~tu_en_w)
rd_blk_cnt_level_r = 'd0;
else if(tu_curr_state_r==TU_END)
rd_blk_cnt_level_r = 'd0;
else if(blk_e_done_r)
rd_blk_cnt_level_r = rd_blk_cnt_r + 'd1;
else
rd_blk_cnt_level_r = rd_blk_cnt_r;
end
wire [5:0] rd_blk_cnt_rev_w ;
assign rd_blk_cnt_rev_w = blk_tot_r - (blk_e_done_r ? rd_blk_cnt_level_r : rd_blk_cnt_r);
//rd_blk_map_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1:begin
case(rd_blk_cnt_rev_w)
'd0: rd_blk_map_r = 'd0 ;
'd1: rd_blk_map_r = 'd2 ;
'd2: rd_blk_map_r = 'd1 ;
'd3: rd_blk_map_r = 'd8 ;
'd4: rd_blk_map_r = 'd3 ;
'd5: rd_blk_map_r = 'd4 ;
'd6: rd_blk_map_r = 'd10;
'd7: rd_blk_map_r = 'd9 ;
'd8: rd_blk_map_r = 'd6 ;
'd9: rd_blk_map_r = 'd5 ;
'd10: rd_blk_map_r = 'd32;
'd11: rd_blk_map_r = 'd11;
'd12: rd_blk_map_r = 'd12;
'd13: rd_blk_map_r = 'd7 ;
'd14: rd_blk_map_r = 'd16;
'd15: rd_blk_map_r = 'd34;
'd16: rd_blk_map_r = 'd33;
'd17: rd_blk_map_r = 'd14;
'd18: rd_blk_map_r = 'd13;
'd19: rd_blk_map_r = 'd18;
'd20: rd_blk_map_r = 'd17;
'd21: rd_blk_map_r = 'd40;
'd22: rd_blk_map_r = 'd35;
'd23: rd_blk_map_r = 'd36;
'd24: rd_blk_map_r = 'd15;
'd25: rd_blk_map_r = 'd24;
'd26: rd_blk_map_r = 'd19;
'd27: rd_blk_map_r = 'd20;
'd28: rd_blk_map_r = 'd42;
'd29: rd_blk_map_r = 'd41;
'd30: rd_blk_map_r = 'd38;
'd31: rd_blk_map_r = 'd37;
'd32: rd_blk_map_r = 'd26;
'd33: rd_blk_map_r = 'd25;
'd34: rd_blk_map_r = 'd22;
'd35: rd_blk_map_r = 'd21;
'd36: rd_blk_map_r = 'd43;
'd37: rd_blk_map_r = 'd44;
'd38: rd_blk_map_r = 'd39;
'd39: rd_blk_map_r = 'd48;
'd40: rd_blk_map_r = 'd27;
'd41: rd_blk_map_r = 'd28;
'd42: rd_blk_map_r = 'd23;
'd43: rd_blk_map_r = 'd46;
'd44: rd_blk_map_r = 'd45;
'd45: rd_blk_map_r = 'd50;
'd46: rd_blk_map_r = 'd49;
'd47: rd_blk_map_r = 'd30;
'd48: rd_blk_map_r = 'd29;
'd49: rd_blk_map_r = 'd47;
'd50: rd_blk_map_r = 'd56;
'd51: rd_blk_map_r = 'd51;
'd52: rd_blk_map_r = 'd52;
'd53: rd_blk_map_r = 'd31;
'd54: rd_blk_map_r = 'd58;
'd55: rd_blk_map_r = 'd57;
'd56: rd_blk_map_r = 'd54;
'd57: rd_blk_map_r = 'd53;
'd58: rd_blk_map_r = 'd59;
'd59: rd_blk_map_r = 'd60;
'd60: rd_blk_map_r = 'd55;
'd61: rd_blk_map_r = 'd62;
'd62: rd_blk_map_r = 'd61;
'd63: rd_blk_map_r = 'd63;
default:rd_blk_map_r = 'd0 ;
endcase
end
'd2: begin
case(rd_blk_cnt_rev_w)
'd0: rd_blk_map_r = 'd0 ;
'd1: rd_blk_map_r = 'd2 ;
'd2: rd_blk_map_r = 'd1 ;
'd3: rd_blk_map_r = 'd8 ;
'd4: rd_blk_map_r = 'd3 ;
'd5: rd_blk_map_r = 'd4 ;
'd6: rd_blk_map_r = 'd10;
'd7: rd_blk_map_r = 'd9 ;
'd8: rd_blk_map_r = 'd6 ;
'd9: rd_blk_map_r = 'd5 ;
'd10: rd_blk_map_r = 'd11;
'd11: rd_blk_map_r = 'd12;
'd12: rd_blk_map_r = 'd7 ;
'd13: rd_blk_map_r = 'd14;
'd14: rd_blk_map_r = 'd13;
'd15: rd_blk_map_r = 'd15;
default:rd_blk_map_r = 'd0 ;
endcase
end
'd3: begin
case(rd_blk_cnt_rev_w)
'd0: rd_blk_map_r = 'd0 ;
'd1: rd_blk_map_r = scan_idx_r!=(`SCAN_HOR) ? 2 : 1;
'd2: rd_blk_map_r = scan_idx_r!=(`SCAN_HOR) ? 1 : 2;
'd3: rd_blk_map_r = 'd3 ;
default:rd_blk_map_r = 'd0 ;
endcase
end
default:begin
rd_blk_map_r = 'd0;
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF || res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
case(rd_blk_cnt_rev_w)
'd0: rd_blk_map_r = 'd0 ;
'd1: rd_blk_map_r = 'd2 ;
'd2: rd_blk_map_r = 'd1 ;
'd3: rd_blk_map_r = 'd8 ;
'd4: rd_blk_map_r = 'd3 ;
'd5: rd_blk_map_r = 'd4 ;
'd6: rd_blk_map_r = 'd10;
'd7: rd_blk_map_r = 'd9 ;
'd8: rd_blk_map_r = 'd6 ;
'd9: rd_blk_map_r = 'd5 ;
'd10: rd_blk_map_r = 'd11;
'd11: rd_blk_map_r = 'd12;
'd12: rd_blk_map_r = 'd7 ;
'd13: rd_blk_map_r = 'd14;
'd14: rd_blk_map_r = 'd13;
'd15: rd_blk_map_r = 'd15;
default:rd_blk_map_r = 'd0 ;
endcase
end
'd2: begin
case(rd_blk_cnt_rev_w)
'd0: rd_blk_map_r = 'd0;
'd1: rd_blk_map_r = 'd2;
'd2: rd_blk_map_r = 'd1;
'd3: rd_blk_map_r = 'd3;
default:rd_blk_map_r = 'd0;
endcase
end
'd3: begin
rd_blk_map_r = 'd0;
end
default:begin
rd_blk_map_r = 'd0;
end
endcase
end
else begin
rd_blk_map_r = 'd0;
end
end
//cu_luma_cbf_r, cu_cr_cbf_r, cu_cb_cbf_r
always @* begin
case(cu_depth_i)
'd0: begin
cu_luma_cbf_r = {luma_cbf_i[255:192]!='d0, luma_cbf_i[191:128]!='d0, luma_cbf_i[127:64]!='d0, luma_cbf_i[63:0]!='d0};
cu_cr_cbf_r = {cr_cbf_i[63:48]!='d0, cr_cbf_i[47:32]!='d0, cr_cbf_i[31:16]!='d0, cr_cbf_i[15:0]!='d0};
cu_cb_cbf_r = {cb_cbf_i[63:48]!='d0, cb_cbf_i[47:32]!='d0, cb_cbf_i[31:16]!='d0, cb_cbf_i[15:0]!='d0};
end
'd1: begin
cu_luma_cbf_r = tu_32x32_luma_cbf_r!='d0;
cu_cr_cbf_r = tu_16x16_cr_cbf_r!='d0;
cu_cb_cbf_r = tu_16x16_cb_cbf_r!='d0;
end
'd2: begin
cu_luma_cbf_r = tu_16x16_luma_cbf_r!='d0;
cu_cr_cbf_r = tu_8x8_cr_cbf_r!='d0;
cu_cb_cbf_r = tu_8x8_cb_cbf_r!='d0;
end
'd3: begin
cu_luma_cbf_r = tu_8x8_luma_cbf_r!='d0;
cu_cr_cbf_r = tu_4x4_cr_cbf_r!='d0;
cu_cb_cbf_r = tu_4x4_cb_cbf_r!='d0;
end
default:begin
cu_luma_cbf_r = 'd0;
cu_cr_cbf_r = 'd0;
cu_cb_cbf_r = 'd0;
end
endcase
end
// tu_32x32_luma_cbf_r, tu_16x16_cr_cbf_r, tu_16x16_cb_cbf_r
always @* begin
if(cu_depth_i=='d0) begin
case(tu_cnt_r)
'd0: begin
tu_32x32_luma_cbf_r = luma_cbf_i[63:0];
tu_16x16_cr_cbf_r = cr_cbf_i[15:0];
tu_16x16_cb_cbf_r = cb_cbf_i[15:0];
end
'd1: begin
tu_32x32_luma_cbf_r = luma_cbf_i[127:64];
tu_16x16_cr_cbf_r = cr_cbf_i[31:16];
tu_16x16_cb_cbf_r = cb_cbf_i[31:16];
end
'd2: begin
tu_32x32_luma_cbf_r = luma_cbf_i[191:128];
tu_16x16_cr_cbf_r = cr_cbf_i[47:32];
tu_16x16_cb_cbf_r = cb_cbf_i[47:32];
end
'd3: begin
tu_32x32_luma_cbf_r = luma_cbf_i[255:192];
tu_16x16_cr_cbf_r = cr_cbf_i[63:48];
tu_16x16_cb_cbf_r = cb_cbf_i[63:48];
end
default:begin
tu_32x32_luma_cbf_r = luma_cbf_i[63:0];
tu_16x16_cr_cbf_r = cr_cbf_i[15:0];
tu_16x16_cb_cbf_r = cb_cbf_i[15:0];
end
endcase
end
else begin
case(cu_idx_i)
'd1: begin
tu_32x32_luma_cbf_r = luma_cbf_i[63:0];
tu_16x16_cr_cbf_r = cr_cbf_i[15:0];
tu_16x16_cb_cbf_r = cb_cbf_i[15:0];
end
'd2: begin
tu_32x32_luma_cbf_r = luma_cbf_i[127:64];
tu_16x16_cr_cbf_r = cr_cbf_i[31:16];
tu_16x16_cb_cbf_r = cb_cbf_i[31:16];
end
'd3: begin
tu_32x32_luma_cbf_r = luma_cbf_i[191:128];
tu_16x16_cr_cbf_r = cr_cbf_i[47:32];
tu_16x16_cb_cbf_r = cb_cbf_i[47:32];
end
'd4: begin
tu_32x32_luma_cbf_r = luma_cbf_i[255:192];
tu_16x16_cr_cbf_r = cr_cbf_i[63:48];
tu_16x16_cb_cbf_r = cb_cbf_i[63:48];
end
default:begin
tu_32x32_luma_cbf_r = 'd0;
tu_16x16_cr_cbf_r = 'd0;
tu_16x16_cb_cbf_r = 'd0;
end
endcase
end
end
//tu_16x16_luma_cbf_r, tu_8x8_cr_cbf_r, tu_8x8_cb_cbf_r
always @* begin
case(cu_idx_i)
'd5: begin
tu_16x16_luma_cbf_r = luma_cbf_i[15:0];
tu_8x8_cr_cbf_r = cr_cbf_i[3:0];
tu_8x8_cb_cbf_r = cb_cbf_i[3:0];
end
'd6: begin
tu_16x16_luma_cbf_r = luma_cbf_i[31:16];
tu_8x8_cr_cbf_r = cr_cbf_i[7:4];
tu_8x8_cb_cbf_r = cb_cbf_i[7:4];
end
'd7: begin
tu_16x16_luma_cbf_r = luma_cbf_i[47:32];
tu_8x8_cr_cbf_r = cr_cbf_i[11:8];
tu_8x8_cb_cbf_r = cb_cbf_i[11:8];
end
'd8: begin
tu_16x16_luma_cbf_r = luma_cbf_i[63:48];
tu_8x8_cr_cbf_r = cr_cbf_i[15:12];
tu_8x8_cb_cbf_r = cb_cbf_i[15:12];
end
'd9: begin
tu_16x16_luma_cbf_r = luma_cbf_i[79:64];
tu_8x8_cr_cbf_r = cr_cbf_i[19:16];
tu_8x8_cb_cbf_r = cb_cbf_i[19:16];
end
'd10: begin
tu_16x16_luma_cbf_r = luma_cbf_i[95:80];
tu_8x8_cr_cbf_r = cr_cbf_i[23:20];
tu_8x8_cb_cbf_r = cb_cbf_i[23:20];
end
'd11: begin
tu_16x16_luma_cbf_r = luma_cbf_i[111:96];
tu_8x8_cr_cbf_r = cr_cbf_i[27:24];
tu_8x8_cb_cbf_r = cb_cbf_i[27:24];
end
'd12: begin
tu_16x16_luma_cbf_r = luma_cbf_i[127:112];
tu_8x8_cr_cbf_r = cr_cbf_i[31:28];
tu_8x8_cb_cbf_r = cb_cbf_i[31:28];
end
'd13: begin
tu_16x16_luma_cbf_r = luma_cbf_i[143:128];
tu_8x8_cr_cbf_r = cr_cbf_i[35:32];
tu_8x8_cb_cbf_r = cb_cbf_i[35:32];
end
'd14: begin
tu_16x16_luma_cbf_r = luma_cbf_i[159:144];
tu_8x8_cr_cbf_r = cr_cbf_i[39:36];
tu_8x8_cb_cbf_r = cb_cbf_i[39:36];
end
'd15: begin
tu_16x16_luma_cbf_r = luma_cbf_i[175:160];
tu_8x8_cr_cbf_r = cr_cbf_i[43:40];
tu_8x8_cb_cbf_r = cb_cbf_i[43:40];
end
'd16: begin
tu_16x16_luma_cbf_r = luma_cbf_i[191:176];
tu_8x8_cr_cbf_r = cr_cbf_i[47:44];
tu_8x8_cb_cbf_r = cb_cbf_i[47:44];
end
'd17: begin
tu_16x16_luma_cbf_r = luma_cbf_i[207:192];
tu_8x8_cr_cbf_r = cr_cbf_i[51:48];
tu_8x8_cb_cbf_r = cb_cbf_i[51:48];
end
'd18: begin
tu_16x16_luma_cbf_r = luma_cbf_i[223:208];
tu_8x8_cr_cbf_r = cr_cbf_i[55:52];
tu_8x8_cb_cbf_r = cb_cbf_i[55:52];
end
'd19: begin
tu_16x16_luma_cbf_r = luma_cbf_i[239:224];
tu_8x8_cr_cbf_r = cr_cbf_i[59:56];
tu_8x8_cb_cbf_r = cb_cbf_i[59:56];
end
'd20: begin
tu_16x16_luma_cbf_r = luma_cbf_i[255:240];
tu_8x8_cr_cbf_r = cr_cbf_i[63:60];
tu_8x8_cb_cbf_r = cb_cbf_i[63:60];
end
default:begin
tu_16x16_luma_cbf_r = 'd0;
tu_8x8_cr_cbf_r = 'd0;
tu_8x8_cb_cbf_r = 'd0;
end
endcase
end
// tu_8x8_luma_cbf_r, tu_4x4_cr_cbf_r, tu_4x4_cb_cbf_r
always @* begin
if(cu_depth_i=='d3) begin
// tu_8x8_luma_cbf_r = luma_cbf_i[((cu_idx_minus21_i<<2)+3) : (cu_idx_minus21_i<<2)];
tu_4x4_cr_cbf_r = cr_cbf_i[cu_idx_minus21_i];
tu_4x4_cb_cbf_r = cb_cbf_i[cu_idx_minus21_i];
end
else begin
// tu_8x8_luma_cbf_r = 'd0;
tu_4x4_cr_cbf_r = 'd0;
tu_4x4_cb_cbf_r = 'd0;
end
end
always @* begin
if(cu_depth_i=='d3) begin
case(cu_idx_i)
'd21: tu_8x8_luma_cbf_r = luma_cbf_i[ 3: 0];
'd22: tu_8x8_luma_cbf_r = luma_cbf_i[ 7: 4];
'd23: tu_8x8_luma_cbf_r = luma_cbf_i[ 11: 8];
'd24: tu_8x8_luma_cbf_r = luma_cbf_i[ 15: 12];
'd25: tu_8x8_luma_cbf_r = luma_cbf_i[ 19: 16];
'd26: tu_8x8_luma_cbf_r = luma_cbf_i[ 23: 20];
'd27: tu_8x8_luma_cbf_r = luma_cbf_i[ 27: 24];
'd28: tu_8x8_luma_cbf_r = luma_cbf_i[ 31: 28];
'd29: tu_8x8_luma_cbf_r = luma_cbf_i[ 35: 32];
'd30: tu_8x8_luma_cbf_r = luma_cbf_i[ 39: 36];
'd31: tu_8x8_luma_cbf_r = luma_cbf_i[ 43: 40];
'd32: tu_8x8_luma_cbf_r = luma_cbf_i[ 47: 44];
'd33: tu_8x8_luma_cbf_r = luma_cbf_i[ 51: 48];
'd34: tu_8x8_luma_cbf_r = luma_cbf_i[ 55: 52];
'd35: tu_8x8_luma_cbf_r = luma_cbf_i[ 59: 56];
'd36: tu_8x8_luma_cbf_r = luma_cbf_i[ 63: 60];
'd37: tu_8x8_luma_cbf_r = luma_cbf_i[ 67: 64];
'd38: tu_8x8_luma_cbf_r = luma_cbf_i[ 71: 68];
'd39: tu_8x8_luma_cbf_r = luma_cbf_i[ 75: 72];
'd40: tu_8x8_luma_cbf_r = luma_cbf_i[ 79: 76];
'd41: tu_8x8_luma_cbf_r = luma_cbf_i[ 83: 80];
'd42: tu_8x8_luma_cbf_r = luma_cbf_i[ 87: 84];
'd43: tu_8x8_luma_cbf_r = luma_cbf_i[ 91: 88];
'd44: tu_8x8_luma_cbf_r = luma_cbf_i[ 95: 92];
'd45: tu_8x8_luma_cbf_r = luma_cbf_i[ 99: 96];
'd46: tu_8x8_luma_cbf_r = luma_cbf_i[103:100];
'd47: tu_8x8_luma_cbf_r = luma_cbf_i[107:104];
'd48: tu_8x8_luma_cbf_r = luma_cbf_i[111:108];
'd49: tu_8x8_luma_cbf_r = luma_cbf_i[115:112];
'd50: tu_8x8_luma_cbf_r = luma_cbf_i[119:116];
'd51: tu_8x8_luma_cbf_r = luma_cbf_i[123:120];
'd52: tu_8x8_luma_cbf_r = luma_cbf_i[127:124];
'd53: tu_8x8_luma_cbf_r = luma_cbf_i[131:128];
'd54: tu_8x8_luma_cbf_r = luma_cbf_i[135:132];
'd55: tu_8x8_luma_cbf_r = luma_cbf_i[139:136];
'd56: tu_8x8_luma_cbf_r = luma_cbf_i[143:140];
'd57: tu_8x8_luma_cbf_r = luma_cbf_i[147:144];
'd58: tu_8x8_luma_cbf_r = luma_cbf_i[151:148];
'd59: tu_8x8_luma_cbf_r = luma_cbf_i[155:152];
'd60: tu_8x8_luma_cbf_r = luma_cbf_i[159:156];
'd61: tu_8x8_luma_cbf_r = luma_cbf_i[163:160];
'd62: tu_8x8_luma_cbf_r = luma_cbf_i[167:164];
'd63: tu_8x8_luma_cbf_r = luma_cbf_i[171:168];
'd64: tu_8x8_luma_cbf_r = luma_cbf_i[175:172];
'd65: tu_8x8_luma_cbf_r = luma_cbf_i[179:176];
'd66: tu_8x8_luma_cbf_r = luma_cbf_i[183:180];
'd67: tu_8x8_luma_cbf_r = luma_cbf_i[187:184];
'd68: tu_8x8_luma_cbf_r = luma_cbf_i[191:188];
'd69: tu_8x8_luma_cbf_r = luma_cbf_i[195:192];
'd70: tu_8x8_luma_cbf_r = luma_cbf_i[199:196];
'd71: tu_8x8_luma_cbf_r = luma_cbf_i[203:200];
'd72: tu_8x8_luma_cbf_r = luma_cbf_i[207:204];
'd73: tu_8x8_luma_cbf_r = luma_cbf_i[211:208];
'd74: tu_8x8_luma_cbf_r = luma_cbf_i[215:212];
'd75: tu_8x8_luma_cbf_r = luma_cbf_i[219:216];
'd76: tu_8x8_luma_cbf_r = luma_cbf_i[223:220];
'd77: tu_8x8_luma_cbf_r = luma_cbf_i[227:224];
'd78: tu_8x8_luma_cbf_r = luma_cbf_i[231:228];
'd79: tu_8x8_luma_cbf_r = luma_cbf_i[235:232];
'd80: tu_8x8_luma_cbf_r = luma_cbf_i[239:236];
'd81: tu_8x8_luma_cbf_r = luma_cbf_i[243:240];
'd82: tu_8x8_luma_cbf_r = luma_cbf_i[247:244];
'd83: tu_8x8_luma_cbf_r = luma_cbf_i[251:248];
'd84: tu_8x8_luma_cbf_r = luma_cbf_i[255:252];
default:tu_8x8_luma_cbf_r = 'd0;
endcase
end
else begin
tu_8x8_luma_cbf_r = 'd0;
end
end
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0: tu_width_flag_r = 'd0; //32x32
'd1: tu_width_flag_r = 'd0; //32x32
'd2: tu_width_flag_r = 'd1; //16x16
'd3: tu_width_flag_r = 'd2; //8x8
default:tu_width_flag_r = 'd2; //8x8
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF || res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0: tu_width_flag_r = 'd1; //16x16
'd1: tu_width_flag_r = 'd1; //16x16
'd2: tu_width_flag_r = 'd2; //8x8
'd3: tu_width_flag_r = 'd3; //4x4
default:tu_width_flag_r = 'd3; //4x4
endcase
end
else begin
tu_width_flag_r = 'd3;
end
end
wire [7:0] a0_w;
wire [7:0] a1_w;
wire [7:0] a2_w;
wire [7:0] a3_w;
wire [7:0] a4_w;
wire [7:0] a5_w;
wire [7:0] a6_w;
wire [7:0] a7_w;
wire [7:0] b0_w;
wire [7:0] b1_w;
wire [7:0] c0_w;
wire [7:0] cr0_w;
wire [7:0] cr1_w;
wire [7:0] cb0_w;
wire [7:0] cb1_w;
assign a0_w = {tu_cbf_z2s_luma32x32_w[56], tu_cbf_z2s_luma32x32_w[57], tu_cbf_z2s_luma32x32_w[58], tu_cbf_z2s_luma32x32_w[59],
tu_cbf_z2s_luma32x32_w[60], tu_cbf_z2s_luma32x32_w[61], tu_cbf_z2s_luma32x32_w[62], tu_cbf_z2s_luma32x32_w[63]}; // tu_cbf_z2s_luma32x32_w[56:63];
assign a1_w = {tu_cbf_z2s_luma32x32_w[48], tu_cbf_z2s_luma32x32_w[49], tu_cbf_z2s_luma32x32_w[50], tu_cbf_z2s_luma32x32_w[51],
tu_cbf_z2s_luma32x32_w[52], tu_cbf_z2s_luma32x32_w[53], tu_cbf_z2s_luma32x32_w[54], tu_cbf_z2s_luma32x32_w[55]}; // tu_cbf_z2s_luma32x32_w[48:55];
assign a2_w = {tu_cbf_z2s_luma32x32_w[40], tu_cbf_z2s_luma32x32_w[41], tu_cbf_z2s_luma32x32_w[42], tu_cbf_z2s_luma32x32_w[43],
tu_cbf_z2s_luma32x32_w[44], tu_cbf_z2s_luma32x32_w[45], tu_cbf_z2s_luma32x32_w[46], tu_cbf_z2s_luma32x32_w[47]};// tu_cbf_z2s_luma32x32_w[40:47];
assign a3_w = {tu_cbf_z2s_luma32x32_w[32], tu_cbf_z2s_luma32x32_w[33], tu_cbf_z2s_luma32x32_w[34], tu_cbf_z2s_luma32x32_w[35],
tu_cbf_z2s_luma32x32_w[36], tu_cbf_z2s_luma32x32_w[37], tu_cbf_z2s_luma32x32_w[38], tu_cbf_z2s_luma32x32_w[39]};// tu_cbf_z2s_luma32x32_w[32:39];
assign a4_w = {tu_cbf_z2s_luma32x32_w[24], tu_cbf_z2s_luma32x32_w[25], tu_cbf_z2s_luma32x32_w[26], tu_cbf_z2s_luma32x32_w[27],
tu_cbf_z2s_luma32x32_w[28], tu_cbf_z2s_luma32x32_w[29], tu_cbf_z2s_luma32x32_w[30], tu_cbf_z2s_luma32x32_w[31]};// tu_cbf_z2s_luma32x32_w[24:31];
assign a5_w = {tu_cbf_z2s_luma32x32_w[16], tu_cbf_z2s_luma32x32_w[17], tu_cbf_z2s_luma32x32_w[18], tu_cbf_z2s_luma32x32_w[19],
tu_cbf_z2s_luma32x32_w[20], tu_cbf_z2s_luma32x32_w[21], tu_cbf_z2s_luma32x32_w[22], tu_cbf_z2s_luma32x32_w[23]};// tu_cbf_z2s_luma32x32_w[16:23];
assign a6_w = {tu_cbf_z2s_luma32x32_w[ 8], tu_cbf_z2s_luma32x32_w[ 9], tu_cbf_z2s_luma32x32_w[10], tu_cbf_z2s_luma32x32_w[11],
tu_cbf_z2s_luma32x32_w[12], tu_cbf_z2s_luma32x32_w[13], tu_cbf_z2s_luma32x32_w[14], tu_cbf_z2s_luma32x32_w[15]};// tu_cbf_z2s_luma32x32_w[ 8:15];
assign a7_w = {tu_cbf_z2s_luma32x32_w[ 0], tu_cbf_z2s_luma32x32_w[ 1], tu_cbf_z2s_luma32x32_w[ 2], tu_cbf_z2s_luma32x32_w[ 3],
tu_cbf_z2s_luma32x32_w[ 4], tu_cbf_z2s_luma32x32_w[ 5], tu_cbf_z2s_luma32x32_w[ 6], tu_cbf_z2s_luma32x32_w[ 7]};// tu_cbf_z2s_luma32x32_w[ 0: 7];
assign b0_w = {tu_cbf_z2s_luma16x16_w[ 8], tu_cbf_z2s_luma16x16_w[ 9], tu_cbf_z2s_luma16x16_w[10], tu_cbf_z2s_luma16x16_w[11],
tu_cbf_z2s_luma16x16_w[12], tu_cbf_z2s_luma16x16_w[13], tu_cbf_z2s_luma16x16_w[14], tu_cbf_z2s_luma16x16_w[15]};//tu_cbf_z2s_luma16x16_w[ 8:15];
assign b1_w = {tu_cbf_z2s_luma16x16_w[ 0], tu_cbf_z2s_luma16x16_w[ 1], tu_cbf_z2s_luma16x16_w[ 2], tu_cbf_z2s_luma16x16_w[ 3],
tu_cbf_z2s_luma16x16_w[ 4], tu_cbf_z2s_luma16x16_w[ 5], tu_cbf_z2s_luma16x16_w[ 6], tu_cbf_z2s_luma16x16_w[ 7]};//tu_cbf_z2s_luma16x16_w[ 0: 7];
assign c0_w = {4'd0,
tu_cbf_z2s_luma8x8_r[ 0], tu_cbf_z2s_luma8x8_r[ 1], tu_cbf_z2s_luma8x8_r[ 2], tu_cbf_z2s_luma8x8_r[ 3]};//{4'd0, tu_cbf_z2s_luma8x8_r[0:3]};
assign cr0_w = {tu_cbf_z2s_cr16x16_w[ 8], tu_cbf_z2s_cr16x16_w[ 9], tu_cbf_z2s_cr16x16_w[10], tu_cbf_z2s_cr16x16_w[11],
tu_cbf_z2s_cr16x16_w[12], tu_cbf_z2s_cr16x16_w[13], tu_cbf_z2s_cr16x16_w[14], tu_cbf_z2s_cr16x16_w[15]};//tu_cbf_z2s_cr16x16_w[ 8:15];
assign cr1_w = {tu_cbf_z2s_cr16x16_w[ 0], tu_cbf_z2s_cr16x16_w[ 1], tu_cbf_z2s_cr16x16_w[ 2], tu_cbf_z2s_cr16x16_w[ 3],
tu_cbf_z2s_cr16x16_w[ 4], tu_cbf_z2s_cr16x16_w[ 5], tu_cbf_z2s_cr16x16_w[ 6], tu_cbf_z2s_cr16x16_w[ 7]};//tu_cbf_z2s_cr16x16_w[ 0: 7];
assign cb0_w = {tu_cbf_z2s_cb16x16_w[ 8], tu_cbf_z2s_cb16x16_w[ 9], tu_cbf_z2s_cb16x16_w[10], tu_cbf_z2s_cb16x16_w[11],
tu_cbf_z2s_cb16x16_w[12], tu_cbf_z2s_cb16x16_w[13], tu_cbf_z2s_cb16x16_w[14], tu_cbf_z2s_cb16x16_w[15]};//tu_cbf_z2s_cb16x16_w[ 8:15];
assign cb1_w = {tu_cbf_z2s_cb16x16_w[ 0], tu_cbf_z2s_cb16x16_w[ 1], tu_cbf_z2s_cb16x16_w[ 2], tu_cbf_z2s_cb16x16_w[ 3],
tu_cbf_z2s_cb16x16_w[ 4], tu_cbf_z2s_cb16x16_w[ 5], tu_cbf_z2s_cb16x16_w[ 6], tu_cbf_z2s_cb16x16_w[ 7]};//tu_cbf_z2s_cb16x16_w[ 0: 7];
//last_cbf_0_r~last_cbf_7_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
last_cbf_0_r = a0_w;//tu_cbf_z2s_luma32x32_w[56:63]; //right-down
last_cbf_1_r = a1_w;//tu_cbf_z2s_luma32x32_w[48:55];
last_cbf_2_r = a2_w;//tu_cbf_z2s_luma32x32_w[40:47];
last_cbf_3_r = a3_w;//tu_cbf_z2s_luma32x32_w[32:39];
last_cbf_4_r = a4_w;//tu_cbf_z2s_luma32x32_w[24:31];
last_cbf_5_r = a5_w;//tu_cbf_z2s_luma32x32_w[16:23];
last_cbf_6_r = a6_w;//tu_cbf_z2s_luma32x32_w[ 8:15];
last_cbf_7_r = a7_w;//tu_cbf_z2s_luma32x32_w[ 0: 7]; //left-top
end
'd2: begin
last_cbf_0_r = b0_w;//tu_cbf_z2s_luma16x16_w[ 8:15];
last_cbf_1_r = b1_w;//tu_cbf_z2s_luma16x16_w[ 0: 7];
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
'd3: begin
last_cbf_0_r = c0_w;
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
default:begin
last_cbf_0_r = 'd0;
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
last_cbf_0_r = cr0_w;//tu_cbf_z2s_cr16x16_w[ 8:15];
last_cbf_1_r = cr1_w;//tu_cbf_z2s_cr16x16_w[ 0: 7];
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
'd2: begin
last_cbf_0_r = {4'd0, tu_cbf_z2s_cr8x8_w[0], tu_cbf_z2s_cr8x8_w[1],
tu_cbf_z2s_cr8x8_w[2], tu_cbf_z2s_cr8x8_w[3]};//{4'd0, tu_cbf_z2s_cr8x8_w};
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
'd3: begin
last_cbf_0_r = {7'd0, tu_cbf_z2s_cr4x4_w};
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
default:begin
last_cbf_0_r = 'd0;
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
last_cbf_0_r = cb0_w;// tu_cbf_z2s_cb16x16_w[ 8:15];
last_cbf_1_r = cb1_w;// tu_cbf_z2s_cb16x16_w[ 0: 7];
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
'd2: begin
last_cbf_0_r = {4'd0, tu_cbf_z2s_cb8x8_w[0], tu_cbf_z2s_cb8x8_w[1],
tu_cbf_z2s_cb8x8_w[2], tu_cbf_z2s_cb8x8_w[3]};
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
'd3: begin
last_cbf_0_r = {7'd0, tu_cbf_z2s_cb4x4_w};
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
default:begin
last_cbf_0_r = 'd0;
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
endcase
end
else begin
last_cbf_0_r = 'd0;
last_cbf_1_r = 'd0;
last_cbf_2_r = 'd0;
last_cbf_3_r = 'd0;
last_cbf_4_r = 'd0;
last_cbf_5_r = 'd0;
last_cbf_6_r = 'd0;
last_cbf_7_r = 'd0;
end
end
always @* begin
if(last_cbf_0_r[7:0]!='d0) begin //right_down
if(last_cbf_0_r[3:0]!='d0) begin
if(last_cbf_0_r[1:0]!='d0) begin
if(last_cbf_0_r[0]!='d0) begin
last_blk_idx_0_r = 'd0;
end
else begin
last_blk_idx_0_r = 'd1;
end
end
else begin
if(last_cbf_0_r[2]!='d0) begin
last_blk_idx_0_r = 'd2;
end
else begin
last_blk_idx_0_r = 'd3;
end
end
end
else begin
if(last_cbf_0_r[5:4]!='d0) begin
if(last_cbf_0_r[4]!='d0)
last_blk_idx_0_r = 'd4;
else
last_blk_idx_0_r = 'd5;
end
else begin
if(last_cbf_0_r[6]!='d0)
last_blk_idx_0_r = 'd6;
else
last_blk_idx_0_r = 'd7;
end
end
end
else
last_blk_idx_0_r = 'hff;
end
always @* begin
if(last_cbf_1_r[7:0]!='d0) begin
if(last_cbf_1_r[3:0]!='d0) begin
if(last_cbf_1_r[1:0]!='d0) begin
if(last_cbf_1_r[0]!='d0) begin
last_blk_idx_1_r = 'd0;
end
else begin
last_blk_idx_1_r = 'd1;
end
end
else begin
if(last_cbf_1_r[2]!='d0) begin
last_blk_idx_1_r = 'd2;
end
else begin
last_blk_idx_1_r = 'd3;
end
end
end
else begin
if(last_cbf_1_r[5:4]!='d0) begin
if(last_cbf_1_r[4]!='d0)
last_blk_idx_1_r = 'd4;
else
last_blk_idx_1_r = 'd5;
end
else begin
if(last_cbf_1_r[6]!='d0)
last_blk_idx_1_r = 'd6;
else
last_blk_idx_1_r = 'd7;
end
end
end
else
last_blk_idx_1_r = 'hff;
end
always @* begin
if(last_cbf_2_r[7:0]!='d0) begin
if(last_cbf_2_r[3:0]!='d0) begin
if(last_cbf_2_r[1:0]!='d0) begin
if(last_cbf_2_r[0]!='d0) begin
last_blk_idx_2_r = 'd0;
end
else begin
last_blk_idx_2_r = 'd1;
end
end
else begin
if(last_cbf_2_r[2]!='d0) begin
last_blk_idx_2_r = 'd2;
end
else begin
last_blk_idx_2_r = 'd3;
end
end
end
else begin
if(last_cbf_2_r[5:4]!='d0) begin
if(last_cbf_2_r[4]!='d0)
last_blk_idx_2_r = 'd4;
else
last_blk_idx_2_r = 'd5;
end
else begin
if(last_cbf_2_r[6]!='d0)
last_blk_idx_2_r = 'd6;
else
last_blk_idx_2_r = 'd7;
end
end
end
else
last_blk_idx_2_r = 'hff;
end
always @* begin
if(last_cbf_3_r[7:0]!='d0) begin
if(last_cbf_3_r[3:0]!='d0) begin
if(last_cbf_3_r[1:0]!='d0) begin
if(last_cbf_3_r[0]!='d0) begin
last_blk_idx_3_r = 'd0;
end
else begin
last_blk_idx_3_r = 'd1;
end
end
else begin
if(last_cbf_3_r[2]!='d0) begin
last_blk_idx_3_r = 'd2;
end
else begin
last_blk_idx_3_r = 'd3;
end
end
end
else begin
if(last_cbf_3_r[5:4]!='d0) begin
if(last_cbf_3_r[4]!='d0)
last_blk_idx_3_r = 'd4;
else
last_blk_idx_3_r = 'd5;
end
else begin
if(last_cbf_3_r[6]!='d0)
last_blk_idx_3_r = 'd6;
else
last_blk_idx_3_r = 'd7;
end
end
end
else
last_blk_idx_3_r = 'hff;
end
always @* begin
if(last_cbf_4_r[7:0]!='d0) begin
if(last_cbf_4_r[3:0]!='d0) begin
if(last_cbf_4_r[1:0]!='d0) begin
if(last_cbf_4_r[0]!='d0) begin
last_blk_idx_4_r = 'd0;
end
else begin
last_blk_idx_4_r = 'd1;
end
end
else begin
if(last_cbf_4_r[2]!='d0) begin
last_blk_idx_4_r = 'd2;
end
else begin
last_blk_idx_4_r = 'd3;
end
end
end
else begin
if(last_cbf_4_r[5:4]!='d0) begin
if(last_cbf_4_r[4]!='d0)
last_blk_idx_4_r = 'd4;
else
last_blk_idx_4_r = 'd5;
end
else begin
if(last_cbf_4_r[6]!='d0)
last_blk_idx_4_r = 'd6;
else
last_blk_idx_4_r = 'd7;
end
end
end
else
last_blk_idx_4_r = 'hff;
end
always @* begin
if(last_cbf_5_r[7:0]!='d0) begin
if(last_cbf_5_r[3:0]!='d0) begin
if(last_cbf_5_r[1:0]!='d0) begin
if(last_cbf_5_r[0]!='d0) begin
last_blk_idx_5_r = 'd0;
end
else begin
last_blk_idx_5_r = 'd1;
end
end
else begin
if(last_cbf_5_r[2]!='d0) begin
last_blk_idx_5_r = 'd2;
end
else begin
last_blk_idx_5_r = 'd3;
end
end
end
else begin
if(last_cbf_5_r[5:4]!='d0) begin
if(last_cbf_5_r[4]!='d0)
last_blk_idx_5_r = 'd4;
else
last_blk_idx_5_r = 'd5;
end
else begin
if(last_cbf_5_r[6]!='d0)
last_blk_idx_5_r = 'd6;
else
last_blk_idx_5_r = 'd7;
end
end
end
else
last_blk_idx_5_r = 'hff;
end
always @* begin
if(last_cbf_6_r[7:0]!='d0) begin
if(last_cbf_6_r[3:0]!='d0) begin
if(last_cbf_6_r[1:0]!='d0) begin
if(last_cbf_6_r[0]!='d0) begin
last_blk_idx_6_r = 'd0;
end
else begin
last_blk_idx_6_r = 'd1;
end
end
else begin
if(last_cbf_6_r[2]!='d0) begin
last_blk_idx_6_r = 'd2;
end
else begin
last_blk_idx_6_r = 'd3;
end
end
end
else begin
if(last_cbf_6_r[5:4]!='d0) begin
if(last_cbf_6_r[4]!='d0)
last_blk_idx_6_r = 'd4;
else
last_blk_idx_6_r = 'd5;
end
else begin
if(last_cbf_6_r[6]!='d0)
last_blk_idx_6_r = 'd6;
else
last_blk_idx_6_r = 'd7;
end
end
end
else
last_blk_idx_6_r = 'hff;
end
always @* begin
if(last_cbf_7_r[7:0]!='d0) begin //left_top
if(last_cbf_7_r[3:0]!='d0) begin
if(last_cbf_7_r[1:0]!='d0) begin
if(last_cbf_7_r[0]!='d0) begin
last_blk_idx_7_r = 'd0;
end
else begin
last_blk_idx_7_r = 'd1;
end
end
else begin
if(last_cbf_7_r[2]!='d0) begin
last_blk_idx_7_r = 'd2;
end
else begin
last_blk_idx_7_r = 'd3;
end
end
end
else begin
if(last_cbf_7_r[5:4]!='d0) begin
if(last_cbf_7_r[4]!='d0)
last_blk_idx_7_r = 'd4;
else
last_blk_idx_7_r = 'd5;
end
else begin
if(last_cbf_7_r[6]!='d0)
last_blk_idx_7_r = 'd6;
else
last_blk_idx_7_r = 'd7;
end
end
end
else
last_blk_idx_7_r = 'hff;
end
//last_blk_idx_r, 0-->left_top, 64-->right_down
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
last_blk_idx_r <= 'd0;
else if(tu_curr_state_r==TU_IDLE) begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin //32x32
if(last_blk_idx_0_r!='h3f)
last_blk_idx_r <= 'd63 - last_blk_idx_0_r;
else if(last_blk_idx_1_r!='h3f)
last_blk_idx_r <= 'd55 - last_blk_idx_1_r;
else if(last_blk_idx_2_r!='h3f)
last_blk_idx_r <= 'd47 - last_blk_idx_2_r;
else if(last_blk_idx_3_r!='h3f)
last_blk_idx_r <= 'd39 - last_blk_idx_3_r;
else if(last_blk_idx_4_r!='h3f)
last_blk_idx_r <= 'd31 - last_blk_idx_4_r;
else if(last_blk_idx_5_r!='h3f)
last_blk_idx_r <= 'd23 - last_blk_idx_5_r;
else if(last_blk_idx_6_r!='h3f)
last_blk_idx_r <= 'd15 - last_blk_idx_6_r;
else if(last_blk_idx_7_r!='h3f)
last_blk_idx_r <= 'd7 - last_blk_idx_7_r;
else
last_blk_idx_r <= 'd0;
end
'd2: begin //16x16
if(last_blk_idx_0_r!='h3f)
last_blk_idx_r <= 'd15 - last_blk_idx_0_r;
else if(last_blk_idx_1_r!='h3f)
last_blk_idx_r <= 'd7 - last_blk_idx_1_r;
else
last_blk_idx_r <= 'd0;
end
'd3: begin //8x8
if(last_blk_idx_0_r!='h3f)
last_blk_idx_r <= 'd3 - last_blk_idx_0_r;
else
last_blk_idx_r <= 'd0;
end
default:begin
last_blk_idx_r <= 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin //16x16
if(last_blk_idx_0_r!='h3f)
last_blk_idx_r <= 'd15 - last_blk_idx_0_r;
else if(last_blk_idx_1_r!='h3f)
last_blk_idx_r <= 'd7 - last_blk_idx_1_r;
else
last_blk_idx_r <= 'd0;
end
'd2: begin //8x8
if(last_blk_idx_0_r!='h3f)
last_blk_idx_r <= 'd3 - last_blk_idx_0_r;
else
last_blk_idx_r <= 'd0;
end
'd3: begin //4x4
last_blk_idx_r <= 'd0;
end
default:begin
last_blk_idx_r <= 'd0;
end
endcase
end
end
else
last_blk_idx_r <= last_blk_idx_r;
end
//blk_tot_r
always @* begin
if(~tu_en_w)
blk_tot_r = 'd0;
else
blk_tot_r = last_blk_idx_r;
end
//blk_cbf_idx_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
blk_cbf_idx_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0) begin
blk_cbf_idx_r <= last_blk_idx_r + 'd1;
end
else if(blk_e_done_r) begin
blk_cbf_idx_r <= blk_cbf_idx_r - 'd1;
end
else
blk_cbf_idx_r <= blk_cbf_idx_r;
end
always @* begin
if(slice_type_i==(`SLICE_TYPE_P))
scan_idx_r = `SCAN_DIAG;
else begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
if(cu_depth_i=='d3)
scan_idx_r = (intra_luma_mode_i>='d22 && intra_luma_mode_i<='d30) ? (`SCAN_HOR) :
((intra_luma_mode_i>='d6 && intra_luma_mode_i<='d14) ? (`SCAN_VER) : (`SCAN_DIAG));
else
scan_idx_r = `SCAN_DIAG;
end
else begin
if(cu_depth_i=='d3) begin
if(intra_chroma_mode_i=='d36)
scan_idx_r = (intra_luma_mode_i>='d22 && intra_luma_mode_i<='d30) ? (`SCAN_HOR) :
((intra_luma_mode_i>='d6 && intra_luma_mode_i<='d14) ? (`SCAN_VER) : (`SCAN_DIAG));
else
scan_idx_r = (intra_chroma_mode_i>='d22 && intra_chroma_mode_i<='d30) ? (`SCAN_HOR) :
((intra_chroma_mode_i>='d6 && intra_chroma_mode_i<='d14) ? (`SCAN_VER) : (`SCAN_DIAG));
end
else
scan_idx_r = `SCAN_DIAG;
end
end
end
//luma cbf 32x32, zcan to diag scan
assign tu_cbf_z2s_luma32x32_w[ 0] = tu_32x32_luma_cbf_r[ 0];
assign tu_cbf_z2s_luma32x32_w[ 1] = tu_32x32_luma_cbf_r[ 2];
assign tu_cbf_z2s_luma32x32_w[ 2] = tu_32x32_luma_cbf_r[ 1];
assign tu_cbf_z2s_luma32x32_w[ 3] = tu_32x32_luma_cbf_r[ 8];
assign tu_cbf_z2s_luma32x32_w[ 4] = tu_32x32_luma_cbf_r[ 3];
assign tu_cbf_z2s_luma32x32_w[ 5] = tu_32x32_luma_cbf_r[ 4];
assign tu_cbf_z2s_luma32x32_w[ 6] = tu_32x32_luma_cbf_r[10];
assign tu_cbf_z2s_luma32x32_w[ 7] = tu_32x32_luma_cbf_r[ 9];
assign tu_cbf_z2s_luma32x32_w[ 8] = tu_32x32_luma_cbf_r[ 6];
assign tu_cbf_z2s_luma32x32_w[ 9] = tu_32x32_luma_cbf_r[ 5];
assign tu_cbf_z2s_luma32x32_w[10] = tu_32x32_luma_cbf_r[32];
assign tu_cbf_z2s_luma32x32_w[11] = tu_32x32_luma_cbf_r[11];
assign tu_cbf_z2s_luma32x32_w[12] = tu_32x32_luma_cbf_r[12];
assign tu_cbf_z2s_luma32x32_w[13] = tu_32x32_luma_cbf_r[ 7];
assign tu_cbf_z2s_luma32x32_w[14] = tu_32x32_luma_cbf_r[16];
assign tu_cbf_z2s_luma32x32_w[15] = tu_32x32_luma_cbf_r[34];
assign tu_cbf_z2s_luma32x32_w[16] = tu_32x32_luma_cbf_r[33];
assign tu_cbf_z2s_luma32x32_w[17] = tu_32x32_luma_cbf_r[14];
assign tu_cbf_z2s_luma32x32_w[18] = tu_32x32_luma_cbf_r[13];
assign tu_cbf_z2s_luma32x32_w[19] = tu_32x32_luma_cbf_r[18];
assign tu_cbf_z2s_luma32x32_w[20] = tu_32x32_luma_cbf_r[17];
assign tu_cbf_z2s_luma32x32_w[21] = tu_32x32_luma_cbf_r[40];
assign tu_cbf_z2s_luma32x32_w[22] = tu_32x32_luma_cbf_r[35];
assign tu_cbf_z2s_luma32x32_w[23] = tu_32x32_luma_cbf_r[36];
assign tu_cbf_z2s_luma32x32_w[24] = tu_32x32_luma_cbf_r[15];
assign tu_cbf_z2s_luma32x32_w[25] = tu_32x32_luma_cbf_r[24];
assign tu_cbf_z2s_luma32x32_w[26] = tu_32x32_luma_cbf_r[19];
assign tu_cbf_z2s_luma32x32_w[27] = tu_32x32_luma_cbf_r[20];
assign tu_cbf_z2s_luma32x32_w[28] = tu_32x32_luma_cbf_r[42];
assign tu_cbf_z2s_luma32x32_w[29] = tu_32x32_luma_cbf_r[41];
assign tu_cbf_z2s_luma32x32_w[30] = tu_32x32_luma_cbf_r[38];
assign tu_cbf_z2s_luma32x32_w[31] = tu_32x32_luma_cbf_r[37];
assign tu_cbf_z2s_luma32x32_w[32] = tu_32x32_luma_cbf_r[26];
assign tu_cbf_z2s_luma32x32_w[33] = tu_32x32_luma_cbf_r[25];
assign tu_cbf_z2s_luma32x32_w[34] = tu_32x32_luma_cbf_r[22];
assign tu_cbf_z2s_luma32x32_w[35] = tu_32x32_luma_cbf_r[21];
assign tu_cbf_z2s_luma32x32_w[36] = tu_32x32_luma_cbf_r[43];
assign tu_cbf_z2s_luma32x32_w[37] = tu_32x32_luma_cbf_r[44];
assign tu_cbf_z2s_luma32x32_w[38] = tu_32x32_luma_cbf_r[39];
assign tu_cbf_z2s_luma32x32_w[39] = tu_32x32_luma_cbf_r[48];
assign tu_cbf_z2s_luma32x32_w[40] = tu_32x32_luma_cbf_r[27];
assign tu_cbf_z2s_luma32x32_w[41] = tu_32x32_luma_cbf_r[28];
assign tu_cbf_z2s_luma32x32_w[42] = tu_32x32_luma_cbf_r[23];
assign tu_cbf_z2s_luma32x32_w[43] = tu_32x32_luma_cbf_r[46];
assign tu_cbf_z2s_luma32x32_w[44] = tu_32x32_luma_cbf_r[45];
assign tu_cbf_z2s_luma32x32_w[45] = tu_32x32_luma_cbf_r[50];
assign tu_cbf_z2s_luma32x32_w[46] = tu_32x32_luma_cbf_r[49];
assign tu_cbf_z2s_luma32x32_w[47] = tu_32x32_luma_cbf_r[30];
assign tu_cbf_z2s_luma32x32_w[48] = tu_32x32_luma_cbf_r[29];
assign tu_cbf_z2s_luma32x32_w[49] = tu_32x32_luma_cbf_r[47];
assign tu_cbf_z2s_luma32x32_w[50] = tu_32x32_luma_cbf_r[56];
assign tu_cbf_z2s_luma32x32_w[51] = tu_32x32_luma_cbf_r[51];
assign tu_cbf_z2s_luma32x32_w[52] = tu_32x32_luma_cbf_r[52];
assign tu_cbf_z2s_luma32x32_w[53] = tu_32x32_luma_cbf_r[31];
assign tu_cbf_z2s_luma32x32_w[54] = tu_32x32_luma_cbf_r[58];
assign tu_cbf_z2s_luma32x32_w[55] = tu_32x32_luma_cbf_r[57];
assign tu_cbf_z2s_luma32x32_w[56] = tu_32x32_luma_cbf_r[54];
assign tu_cbf_z2s_luma32x32_w[57] = tu_32x32_luma_cbf_r[53];
assign tu_cbf_z2s_luma32x32_w[58] = tu_32x32_luma_cbf_r[59];
assign tu_cbf_z2s_luma32x32_w[59] = tu_32x32_luma_cbf_r[60];
assign tu_cbf_z2s_luma32x32_w[60] = tu_32x32_luma_cbf_r[55];
assign tu_cbf_z2s_luma32x32_w[61] = tu_32x32_luma_cbf_r[62];
assign tu_cbf_z2s_luma32x32_w[62] = tu_32x32_luma_cbf_r[61];
assign tu_cbf_z2s_luma32x32_w[63] = tu_32x32_luma_cbf_r[63];
//luma cbf 16x16, zcan to diag scan
assign tu_cbf_z2s_luma16x16_w[ 0] = tu_16x16_luma_cbf_r[ 0];
assign tu_cbf_z2s_luma16x16_w[ 1] = tu_16x16_luma_cbf_r[ 2];
assign tu_cbf_z2s_luma16x16_w[ 2] = tu_16x16_luma_cbf_r[ 1];
assign tu_cbf_z2s_luma16x16_w[ 3] = tu_16x16_luma_cbf_r[ 8];
assign tu_cbf_z2s_luma16x16_w[ 4] = tu_16x16_luma_cbf_r[ 3];
assign tu_cbf_z2s_luma16x16_w[ 5] = tu_16x16_luma_cbf_r[ 4];
assign tu_cbf_z2s_luma16x16_w[ 6] = tu_16x16_luma_cbf_r[10];
assign tu_cbf_z2s_luma16x16_w[ 7] = tu_16x16_luma_cbf_r[ 9];
assign tu_cbf_z2s_luma16x16_w[ 8] = tu_16x16_luma_cbf_r[ 6];
assign tu_cbf_z2s_luma16x16_w[ 9] = tu_16x16_luma_cbf_r[ 5];
assign tu_cbf_z2s_luma16x16_w[10] = tu_16x16_luma_cbf_r[11];
assign tu_cbf_z2s_luma16x16_w[11] = tu_16x16_luma_cbf_r[12];
assign tu_cbf_z2s_luma16x16_w[12] = tu_16x16_luma_cbf_r[ 7];
assign tu_cbf_z2s_luma16x16_w[13] = tu_16x16_luma_cbf_r[14];
assign tu_cbf_z2s_luma16x16_w[14] = tu_16x16_luma_cbf_r[13];
assign tu_cbf_z2s_luma16x16_w[15] = tu_16x16_luma_cbf_r[15];
//luma cbf 8x8, zcan to scan_idx scan
always @* begin
case(scan_idx_r)
(`SCAN_HOR): begin
tu_cbf_z2s_luma8x8_r[0] = tu_8x8_luma_cbf_r[0];
tu_cbf_z2s_luma8x8_r[1] = tu_8x8_luma_cbf_r[1];
tu_cbf_z2s_luma8x8_r[2] = tu_8x8_luma_cbf_r[2];
tu_cbf_z2s_luma8x8_r[3] = tu_8x8_luma_cbf_r[3];
end
(`SCAN_VER): begin
tu_cbf_z2s_luma8x8_r[0] = tu_8x8_luma_cbf_r[0];
tu_cbf_z2s_luma8x8_r[1] = tu_8x8_luma_cbf_r[2];
tu_cbf_z2s_luma8x8_r[2] = tu_8x8_luma_cbf_r[1];
tu_cbf_z2s_luma8x8_r[3] = tu_8x8_luma_cbf_r[3];
end
default: begin
tu_cbf_z2s_luma8x8_r[0] = tu_8x8_luma_cbf_r[0];
tu_cbf_z2s_luma8x8_r[1] = tu_8x8_luma_cbf_r[2];
tu_cbf_z2s_luma8x8_r[2] = tu_8x8_luma_cbf_r[1];
tu_cbf_z2s_luma8x8_r[3] = tu_8x8_luma_cbf_r[3];
end
endcase
end
//tu_cbf_luma righter
assign tu_cbf_z2s_luma32x32_rer_w[ 0] = tu_32x32_luma_cbf_r[ 1];
assign tu_cbf_z2s_luma32x32_rer_w[ 1] = tu_32x32_luma_cbf_r[ 3];
assign tu_cbf_z2s_luma32x32_rer_w[ 2] = tu_32x32_luma_cbf_r[ 4];
assign tu_cbf_z2s_luma32x32_rer_w[ 3] = tu_32x32_luma_cbf_r[ 9];
assign tu_cbf_z2s_luma32x32_rer_w[ 4] = tu_32x32_luma_cbf_r[ 6];
assign tu_cbf_z2s_luma32x32_rer_w[ 5] = tu_32x32_luma_cbf_r[ 5];
assign tu_cbf_z2s_luma32x32_rer_w[ 6] = tu_32x32_luma_cbf_r[11];
assign tu_cbf_z2s_luma32x32_rer_w[ 7] = tu_32x32_luma_cbf_r[12];
assign tu_cbf_z2s_luma32x32_rer_w[ 8] = tu_32x32_luma_cbf_r[ 7];
assign tu_cbf_z2s_luma32x32_rer_w[ 9] = tu_32x32_luma_cbf_r[16];
assign tu_cbf_z2s_luma32x32_rer_w[10] = tu_32x32_luma_cbf_r[33];
assign tu_cbf_z2s_luma32x32_rer_w[11] = tu_32x32_luma_cbf_r[14];
assign tu_cbf_z2s_luma32x32_rer_w[12] = tu_32x32_luma_cbf_r[13];
assign tu_cbf_z2s_luma32x32_rer_w[13] = tu_32x32_luma_cbf_r[18];
assign tu_cbf_z2s_luma32x32_rer_w[14] = tu_32x32_luma_cbf_r[17];
assign tu_cbf_z2s_luma32x32_rer_w[15] = tu_32x32_luma_cbf_r[35];
assign tu_cbf_z2s_luma32x32_rer_w[16] = tu_32x32_luma_cbf_r[36];
assign tu_cbf_z2s_luma32x32_rer_w[17] = tu_32x32_luma_cbf_r[15];
assign tu_cbf_z2s_luma32x32_rer_w[18] = tu_32x32_luma_cbf_r[24];
assign tu_cbf_z2s_luma32x32_rer_w[19] = tu_32x32_luma_cbf_r[19];
assign tu_cbf_z2s_luma32x32_rer_w[20] = tu_32x32_luma_cbf_r[20];
assign tu_cbf_z2s_luma32x32_rer_w[21] = tu_32x32_luma_cbf_r[41];
assign tu_cbf_z2s_luma32x32_rer_w[22] = tu_32x32_luma_cbf_r[38];
assign tu_cbf_z2s_luma32x32_rer_w[23] = tu_32x32_luma_cbf_r[37];
assign tu_cbf_z2s_luma32x32_rer_w[24] = tu_32x32_luma_cbf_r[26];
assign tu_cbf_z2s_luma32x32_rer_w[25] = tu_32x32_luma_cbf_r[25];
assign tu_cbf_z2s_luma32x32_rer_w[26] = tu_32x32_luma_cbf_r[22];
assign tu_cbf_z2s_luma32x32_rer_w[27] = tu_32x32_luma_cbf_r[21];
assign tu_cbf_z2s_luma32x32_rer_w[28] = tu_32x32_luma_cbf_r[43];
assign tu_cbf_z2s_luma32x32_rer_w[29] = tu_32x32_luma_cbf_r[44];
assign tu_cbf_z2s_luma32x32_rer_w[30] = tu_32x32_luma_cbf_r[39];
assign tu_cbf_z2s_luma32x32_rer_w[31] = tu_32x32_luma_cbf_r[48];
assign tu_cbf_z2s_luma32x32_rer_w[32] = tu_32x32_luma_cbf_r[27];
assign tu_cbf_z2s_luma32x32_rer_w[33] = tu_32x32_luma_cbf_r[28];
assign tu_cbf_z2s_luma32x32_rer_w[34] = tu_32x32_luma_cbf_r[23];
assign tu_cbf_z2s_luma32x32_rer_w[35] = 'd0;//tu_32x32_luma_cbf_r[];
assign tu_cbf_z2s_luma32x32_rer_w[36] = tu_32x32_luma_cbf_r[46];
assign tu_cbf_z2s_luma32x32_rer_w[37] = tu_32x32_luma_cbf_r[45];
assign tu_cbf_z2s_luma32x32_rer_w[38] = tu_32x32_luma_cbf_r[50];
assign tu_cbf_z2s_luma32x32_rer_w[39] = tu_32x32_luma_cbf_r[49];
assign tu_cbf_z2s_luma32x32_rer_w[40] = tu_32x32_luma_cbf_r[30];
assign tu_cbf_z2s_luma32x32_rer_w[41] = tu_32x32_luma_cbf_r[29];
assign tu_cbf_z2s_luma32x32_rer_w[42] = 'd0;//tu_32x32_luma_cbf_r[50];
assign tu_cbf_z2s_luma32x32_rer_w[43] = tu_32x32_luma_cbf_r[47];
assign tu_cbf_z2s_luma32x32_rer_w[44] = tu_32x32_luma_cbf_r[56];
assign tu_cbf_z2s_luma32x32_rer_w[45] = tu_32x32_luma_cbf_r[51];
assign tu_cbf_z2s_luma32x32_rer_w[46] = tu_32x32_luma_cbf_r[52];
assign tu_cbf_z2s_luma32x32_rer_w[47] = tu_32x32_luma_cbf_r[31];
assign tu_cbf_z2s_luma32x32_rer_w[48] = 'd0;//tu_32x32_luma_cbf_r[];
assign tu_cbf_z2s_luma32x32_rer_w[49] = tu_32x32_luma_cbf_r[58];
assign tu_cbf_z2s_luma32x32_rer_w[50] = tu_32x32_luma_cbf_r[57];
assign tu_cbf_z2s_luma32x32_rer_w[51] = tu_32x32_luma_cbf_r[54];
assign tu_cbf_z2s_luma32x32_rer_w[52] = tu_32x32_luma_cbf_r[53];
assign tu_cbf_z2s_luma32x32_rer_w[53] = 'd0;//tu_32x32_luma_cbf_r[];
assign tu_cbf_z2s_luma32x32_rer_w[54] = tu_32x32_luma_cbf_r[59];
assign tu_cbf_z2s_luma32x32_rer_w[55] = tu_32x32_luma_cbf_r[60];
assign tu_cbf_z2s_luma32x32_rer_w[56] = tu_32x32_luma_cbf_r[55];
assign tu_cbf_z2s_luma32x32_rer_w[57] = 'd0;//tu_32x32_luma_cbf_r[59];
assign tu_cbf_z2s_luma32x32_rer_w[58] = tu_32x32_luma_cbf_r[62];
assign tu_cbf_z2s_luma32x32_rer_w[59] = tu_32x32_luma_cbf_r[61];
assign tu_cbf_z2s_luma32x32_rer_w[60] = 'd0;//tu_32x32_luma_cbf_r[62];
assign tu_cbf_z2s_luma32x32_rer_w[61] = tu_32x32_luma_cbf_r[63];
assign tu_cbf_z2s_luma32x32_rer_w[62] = 'd0;//tu_32x32_luma_cbf_r[63];
assign tu_cbf_z2s_luma32x32_rer_w[63] = 'd0;
assign tu_cbf_z2s_luma16x16_rer_w[ 0] = tu_16x16_luma_cbf_r[ 1];
assign tu_cbf_z2s_luma16x16_rer_w[ 1] = tu_16x16_luma_cbf_r[ 3];
assign tu_cbf_z2s_luma16x16_rer_w[ 2] = tu_16x16_luma_cbf_r[ 4];
assign tu_cbf_z2s_luma16x16_rer_w[ 3] = tu_16x16_luma_cbf_r[ 9];
assign tu_cbf_z2s_luma16x16_rer_w[ 4] = tu_16x16_luma_cbf_r[ 6];
assign tu_cbf_z2s_luma16x16_rer_w[ 5] = tu_16x16_luma_cbf_r[ 5];
assign tu_cbf_z2s_luma16x16_rer_w[ 6] = tu_16x16_luma_cbf_r[11];
assign tu_cbf_z2s_luma16x16_rer_w[ 7] = tu_16x16_luma_cbf_r[12];
assign tu_cbf_z2s_luma16x16_rer_w[ 8] = tu_16x16_luma_cbf_r[ 7];
assign tu_cbf_z2s_luma16x16_rer_w[ 9] = 'd0;//tu_16x16_luma_cbf_r[];
assign tu_cbf_z2s_luma16x16_rer_w[10] = tu_16x16_luma_cbf_r[14];
assign tu_cbf_z2s_luma16x16_rer_w[11] = tu_16x16_luma_cbf_r[13];
assign tu_cbf_z2s_luma16x16_rer_w[12] = 'd0;//tu_16x16_luma_cbf_r[];
assign tu_cbf_z2s_luma16x16_rer_w[13] = tu_16x16_luma_cbf_r[15];
assign tu_cbf_z2s_luma16x16_rer_w[14] = 'd0;//tu_16x16_luma_cbf_r[];
assign tu_cbf_z2s_luma16x16_rer_w[15] = 'd0;//tu_16x16_luma_cbf_r[15];
always @* begin
case(scan_idx_r)
(`SCAN_HOR): begin
tu_cbf_z2s_luma8x8_rer_r[ 0] = tu_8x8_luma_cbf_r[ 1];
tu_cbf_z2s_luma8x8_rer_r[ 1] = 'd0;//tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_rer_r[ 2] = tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_rer_r[ 3] = 'd0;//tu_8x8_luma_cbf_r[ ];
end
default: begin
tu_cbf_z2s_luma8x8_rer_r[ 0] = tu_8x8_luma_cbf_r[ 1];
tu_cbf_z2s_luma8x8_rer_r[ 1] = tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_rer_r[ 2] = 'd0;//tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_rer_r[ 3] = 'd0;//tu_8x8_luma_cbf_r[ ];
end
endcase
end
//tu_cbf_luma lower
assign tu_cbf_z2s_luma32x32_ler_w[ 0] = tu_32x32_luma_cbf_r[ 2];
assign tu_cbf_z2s_luma32x32_ler_w[ 1] = tu_32x32_luma_cbf_r[ 8];
assign tu_cbf_z2s_luma32x32_ler_w[ 2] = tu_32x32_luma_cbf_r[ 3];
assign tu_cbf_z2s_luma32x32_ler_w[ 3] = tu_32x32_luma_cbf_r[10];
assign tu_cbf_z2s_luma32x32_ler_w[ 4] = tu_32x32_luma_cbf_r[ 9];
assign tu_cbf_z2s_luma32x32_ler_w[ 5] = tu_32x32_luma_cbf_r[ 6];
assign tu_cbf_z2s_luma32x32_ler_w[ 6] = tu_32x32_luma_cbf_r[32];
assign tu_cbf_z2s_luma32x32_ler_w[ 7] = tu_32x32_luma_cbf_r[11];
assign tu_cbf_z2s_luma32x32_ler_w[ 8] = tu_32x32_luma_cbf_r[12];
assign tu_cbf_z2s_luma32x32_ler_w[ 9] = tu_32x32_luma_cbf_r[ 7];
assign tu_cbf_z2s_luma32x32_ler_w[10] = tu_32x32_luma_cbf_r[34];
assign tu_cbf_z2s_luma32x32_ler_w[11] = tu_32x32_luma_cbf_r[33];
assign tu_cbf_z2s_luma32x32_ler_w[12] = tu_32x32_luma_cbf_r[14];
assign tu_cbf_z2s_luma32x32_ler_w[13] = tu_32x32_luma_cbf_r[13];
assign tu_cbf_z2s_luma32x32_ler_w[14] = tu_32x32_luma_cbf_r[18];
assign tu_cbf_z2s_luma32x32_ler_w[15] = tu_32x32_luma_cbf_r[40];
assign tu_cbf_z2s_luma32x32_ler_w[16] = tu_32x32_luma_cbf_r[35];
assign tu_cbf_z2s_luma32x32_ler_w[17] = tu_32x32_luma_cbf_r[36];
assign tu_cbf_z2s_luma32x32_ler_w[18] = tu_32x32_luma_cbf_r[15];
assign tu_cbf_z2s_luma32x32_ler_w[19] = tu_32x32_luma_cbf_r[24];
assign tu_cbf_z2s_luma32x32_ler_w[20] = tu_32x32_luma_cbf_r[19];
assign tu_cbf_z2s_luma32x32_ler_w[21] = tu_32x32_luma_cbf_r[42];
assign tu_cbf_z2s_luma32x32_ler_w[22] = tu_32x32_luma_cbf_r[41];
assign tu_cbf_z2s_luma32x32_ler_w[23] = tu_32x32_luma_cbf_r[38];
assign tu_cbf_z2s_luma32x32_ler_w[24] = tu_32x32_luma_cbf_r[37];
assign tu_cbf_z2s_luma32x32_ler_w[25] = tu_32x32_luma_cbf_r[26];
assign tu_cbf_z2s_luma32x32_ler_w[26] = tu_32x32_luma_cbf_r[25];
assign tu_cbf_z2s_luma32x32_ler_w[27] = tu_32x32_luma_cbf_r[22];
assign tu_cbf_z2s_luma32x32_ler_w[28] = 'd0;//tu_32x32_luma_cbf_r[];
assign tu_cbf_z2s_luma32x32_ler_w[29] = tu_32x32_luma_cbf_r[43];
assign tu_cbf_z2s_luma32x32_ler_w[30] = tu_32x32_luma_cbf_r[44];
assign tu_cbf_z2s_luma32x32_ler_w[31] = tu_32x32_luma_cbf_r[39];
assign tu_cbf_z2s_luma32x32_ler_w[32] = tu_32x32_luma_cbf_r[48];
assign tu_cbf_z2s_luma32x32_ler_w[33] = tu_32x32_luma_cbf_r[27];
assign tu_cbf_z2s_luma32x32_ler_w[34] = tu_32x32_luma_cbf_r[28];
assign tu_cbf_z2s_luma32x32_ler_w[35] = tu_32x32_luma_cbf_r[23];
assign tu_cbf_z2s_luma32x32_ler_w[36] = 'd0;//tu_32x32_luma_cbf_r[];
assign tu_cbf_z2s_luma32x32_ler_w[37] = tu_32x32_luma_cbf_r[46];
assign tu_cbf_z2s_luma32x32_ler_w[38] = tu_32x32_luma_cbf_r[45];
assign tu_cbf_z2s_luma32x32_ler_w[39] = tu_32x32_luma_cbf_r[50];
assign tu_cbf_z2s_luma32x32_ler_w[40] = tu_32x32_luma_cbf_r[49];
assign tu_cbf_z2s_luma32x32_ler_w[41] = tu_32x32_luma_cbf_r[30];
assign tu_cbf_z2s_luma32x32_ler_w[42] = tu_32x32_luma_cbf_r[29];
assign tu_cbf_z2s_luma32x32_ler_w[43] = 'd0;//tu_32x32_luma_cbf_r[];
assign tu_cbf_z2s_luma32x32_ler_w[44] = tu_32x32_luma_cbf_r[47];
assign tu_cbf_z2s_luma32x32_ler_w[45] = tu_32x32_luma_cbf_r[56];
assign tu_cbf_z2s_luma32x32_ler_w[46] = tu_32x32_luma_cbf_r[51];
assign tu_cbf_z2s_luma32x32_ler_w[47] = tu_32x32_luma_cbf_r[52];
assign tu_cbf_z2s_luma32x32_ler_w[48] = tu_32x32_luma_cbf_r[31];
assign tu_cbf_z2s_luma32x32_ler_w[49] = 'd0;//tu_32x32_luma_cbf_r[58];
assign tu_cbf_z2s_luma32x32_ler_w[50] = tu_32x32_luma_cbf_r[58];
assign tu_cbf_z2s_luma32x32_ler_w[51] = tu_32x32_luma_cbf_r[57];
assign tu_cbf_z2s_luma32x32_ler_w[52] = tu_32x32_luma_cbf_r[54];
assign tu_cbf_z2s_luma32x32_ler_w[53] = tu_32x32_luma_cbf_r[53];
assign tu_cbf_z2s_luma32x32_ler_w[54] = 'd0;//tu_32x32_luma_cbf_r[59];
assign tu_cbf_z2s_luma32x32_ler_w[55] = tu_32x32_luma_cbf_r[59];
assign tu_cbf_z2s_luma32x32_ler_w[56] = tu_32x32_luma_cbf_r[60];
assign tu_cbf_z2s_luma32x32_ler_w[57] = tu_32x32_luma_cbf_r[55];
assign tu_cbf_z2s_luma32x32_ler_w[58] = 'd0;//tu_32x32_luma_cbf_r[62];
assign tu_cbf_z2s_luma32x32_ler_w[59] = tu_32x32_luma_cbf_r[62];
assign tu_cbf_z2s_luma32x32_ler_w[60] = tu_32x32_luma_cbf_r[61];
assign tu_cbf_z2s_luma32x32_ler_w[61] = 'd0;//tu_32x32_luma_cbf_r[63];
assign tu_cbf_z2s_luma32x32_ler_w[62] = tu_32x32_luma_cbf_r[63];
assign tu_cbf_z2s_luma32x32_ler_w[63] = 'd0;
assign tu_cbf_z2s_luma16x16_ler_w[ 0] = tu_16x16_luma_cbf_r[ 2];
assign tu_cbf_z2s_luma16x16_ler_w[ 1] = tu_16x16_luma_cbf_r[ 8];
assign tu_cbf_z2s_luma16x16_ler_w[ 2] = tu_16x16_luma_cbf_r[ 3];
assign tu_cbf_z2s_luma16x16_ler_w[ 3] = tu_16x16_luma_cbf_r[10];
assign tu_cbf_z2s_luma16x16_ler_w[ 4] = tu_16x16_luma_cbf_r[ 9];
assign tu_cbf_z2s_luma16x16_ler_w[ 5] = tu_16x16_luma_cbf_r[ 6];
assign tu_cbf_z2s_luma16x16_ler_w[ 6] = 'd0;//tu_16x16_luma_cbf_r[11];
assign tu_cbf_z2s_luma16x16_ler_w[ 7] = tu_16x16_luma_cbf_r[11];
assign tu_cbf_z2s_luma16x16_ler_w[ 8] = tu_16x16_luma_cbf_r[12];
assign tu_cbf_z2s_luma16x16_ler_w[ 9] = tu_16x16_luma_cbf_r[ 7];
assign tu_cbf_z2s_luma16x16_ler_w[10] = 'd0;//tu_16x16_luma_cbf_r[14];
assign tu_cbf_z2s_luma16x16_ler_w[11] = tu_16x16_luma_cbf_r[14];
assign tu_cbf_z2s_luma16x16_ler_w[12] = tu_16x16_luma_cbf_r[13];
assign tu_cbf_z2s_luma16x16_ler_w[13] = 'd0;//tu_16x16_luma_cbf_r[15];
assign tu_cbf_z2s_luma16x16_ler_w[14] = tu_16x16_luma_cbf_r[15];
assign tu_cbf_z2s_luma16x16_ler_w[15] = 'd0;//tu_16x16_luma_cbf_r[15];
always @* begin
case(scan_idx_r)
(`SCAN_HOR): begin
tu_cbf_z2s_luma8x8_ler_r[ 0] = tu_8x8_luma_cbf_r[ 2];
tu_cbf_z2s_luma8x8_ler_r[ 1] = tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_ler_r[ 2] = 'd0;//tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_ler_r[ 3] = 'd0;//tu_8x8_luma_cbf_r[ ];
end
default: begin
tu_cbf_z2s_luma8x8_ler_r[ 0] = tu_8x8_luma_cbf_r[ 2];
tu_cbf_z2s_luma8x8_ler_r[ 1] = 'd0;//tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_ler_r[ 2] = tu_8x8_luma_cbf_r[ 3];
tu_cbf_z2s_luma8x8_ler_r[ 3] = 'd0;//tu_8x8_luma_cbf_r[ ];
end
endcase
end
//cr cbf 16x16, zscan to scan_idx scan
assign tu_cbf_z2s_cr16x16_w[ 0] = tu_16x16_cr_cbf_r[ 0];
assign tu_cbf_z2s_cr16x16_w[ 1] = tu_16x16_cr_cbf_r[ 2];
assign tu_cbf_z2s_cr16x16_w[ 2] = tu_16x16_cr_cbf_r[ 1];
assign tu_cbf_z2s_cr16x16_w[ 3] = tu_16x16_cr_cbf_r[ 8];
assign tu_cbf_z2s_cr16x16_w[ 4] = tu_16x16_cr_cbf_r[ 3];
assign tu_cbf_z2s_cr16x16_w[ 5] = tu_16x16_cr_cbf_r[ 4];
assign tu_cbf_z2s_cr16x16_w[ 6] = tu_16x16_cr_cbf_r[10];
assign tu_cbf_z2s_cr16x16_w[ 7] = tu_16x16_cr_cbf_r[ 9];
assign tu_cbf_z2s_cr16x16_w[ 8] = tu_16x16_cr_cbf_r[ 6];
assign tu_cbf_z2s_cr16x16_w[ 9] = tu_16x16_cr_cbf_r[ 5];
assign tu_cbf_z2s_cr16x16_w[10] = tu_16x16_cr_cbf_r[11];
assign tu_cbf_z2s_cr16x16_w[11] = tu_16x16_cr_cbf_r[12];
assign tu_cbf_z2s_cr16x16_w[12] = tu_16x16_cr_cbf_r[ 7];
assign tu_cbf_z2s_cr16x16_w[13] = tu_16x16_cr_cbf_r[14];
assign tu_cbf_z2s_cr16x16_w[14] = tu_16x16_cr_cbf_r[13];
assign tu_cbf_z2s_cr16x16_w[15] = tu_16x16_cr_cbf_r[15];
//cr cbf 8x8, zscan to scan_idx scan
assign tu_cbf_z2s_cr8x8_w[0] = tu_8x8_cr_cbf_r[0];
assign tu_cbf_z2s_cr8x8_w[1] = tu_8x8_cr_cbf_r[2];
assign tu_cbf_z2s_cr8x8_w[2] = tu_8x8_cr_cbf_r[1];
assign tu_cbf_z2s_cr8x8_w[3] = tu_8x8_cr_cbf_r[3];
//cr cbf 4x4
assign tu_cbf_z2s_cr4x4_w = tu_4x4_cr_cbf_r;
//cr cbf righter
assign tu_cbf_z2s_cr16x16_rer_w[ 0] = tu_16x16_cr_cbf_r[ 1];
assign tu_cbf_z2s_cr16x16_rer_w[ 1] = tu_16x16_cr_cbf_r[ 3];
assign tu_cbf_z2s_cr16x16_rer_w[ 2] = tu_16x16_cr_cbf_r[ 4];
assign tu_cbf_z2s_cr16x16_rer_w[ 3] = tu_16x16_cr_cbf_r[ 9];
assign tu_cbf_z2s_cr16x16_rer_w[ 4] = tu_16x16_cr_cbf_r[ 6];
assign tu_cbf_z2s_cr16x16_rer_w[ 5] = tu_16x16_cr_cbf_r[ 5];
assign tu_cbf_z2s_cr16x16_rer_w[ 6] = tu_16x16_cr_cbf_r[11];
assign tu_cbf_z2s_cr16x16_rer_w[ 7] = tu_16x16_cr_cbf_r[12];
assign tu_cbf_z2s_cr16x16_rer_w[ 8] = tu_16x16_cr_cbf_r[ 7];
assign tu_cbf_z2s_cr16x16_rer_w[ 9] = 'd0;//tu_16x16_cr_cbf_r[];
assign tu_cbf_z2s_cr16x16_rer_w[10] = tu_16x16_cr_cbf_r[14];
assign tu_cbf_z2s_cr16x16_rer_w[11] = tu_16x16_cr_cbf_r[13];
assign tu_cbf_z2s_cr16x16_rer_w[12] = 'd0;//tu_16x16_cr_cbf_r[];
assign tu_cbf_z2s_cr16x16_rer_w[13] = tu_16x16_cr_cbf_r[15];
assign tu_cbf_z2s_cr16x16_rer_w[14] = 'd0;//tu_16x16_cr_cbf_r[];
assign tu_cbf_z2s_cr16x16_rer_w[15] = 'd0;//tu_16x16_cr_cbf_r[15];
assign tu_cbf_z2s_cr8x8_rer_w[ 0] = tu_8x8_cr_cbf_r[ 1];
assign tu_cbf_z2s_cr8x8_rer_w[ 1] = tu_8x8_cr_cbf_r[ 3];
assign tu_cbf_z2s_cr8x8_rer_w[ 2] = 'd0;//tu_8x8_cr_cbf_r[ ];
assign tu_cbf_z2s_cr8x8_rer_w[ 3] = 'd0;//tu_8x8_cr_cbf_r[ ];
assign tu_cbf_z2s_cr4x4_rer_w = 'd0;
//cr cbf lower
assign tu_cbf_z2s_cr16x16_ler_w[ 0] = tu_16x16_cr_cbf_r[ 2];
assign tu_cbf_z2s_cr16x16_ler_w[ 1] = tu_16x16_cr_cbf_r[ 8];
assign tu_cbf_z2s_cr16x16_ler_w[ 2] = tu_16x16_cr_cbf_r[ 3];
assign tu_cbf_z2s_cr16x16_ler_w[ 3] = tu_16x16_cr_cbf_r[10];
assign tu_cbf_z2s_cr16x16_ler_w[ 4] = tu_16x16_cr_cbf_r[ 9];
assign tu_cbf_z2s_cr16x16_ler_w[ 5] = tu_16x16_cr_cbf_r[ 6];
assign tu_cbf_z2s_cr16x16_ler_w[ 6] = 'd0;//tu_16x16_cr_cbf_r[ ];
assign tu_cbf_z2s_cr16x16_ler_w[ 7] = tu_16x16_cr_cbf_r[11];
assign tu_cbf_z2s_cr16x16_ler_w[ 8] = tu_16x16_cr_cbf_r[12];
assign tu_cbf_z2s_cr16x16_ler_w[ 9] = tu_16x16_cr_cbf_r[ 7];
assign tu_cbf_z2s_cr16x16_ler_w[10] = 'd0;//tu_16x16_cr_cbf_r[14];
assign tu_cbf_z2s_cr16x16_ler_w[11] = tu_16x16_cr_cbf_r[14];
assign tu_cbf_z2s_cr16x16_ler_w[12] = tu_16x16_cr_cbf_r[13];
assign tu_cbf_z2s_cr16x16_ler_w[13] = 'd0;//tu_16x16_cr_cbf_r[15];
assign tu_cbf_z2s_cr16x16_ler_w[14] = tu_16x16_cr_cbf_r[15];
assign tu_cbf_z2s_cr16x16_ler_w[15] = 'd0;//tu_16x16_cr_cbf_r[15];
assign tu_cbf_z2s_cr8x8_ler_w[ 0] = tu_8x8_cr_cbf_r[ 2];
assign tu_cbf_z2s_cr8x8_ler_w[ 1] = 'd0;//tu_8x8_cr_cbf_r[ ];
assign tu_cbf_z2s_cr8x8_ler_w[ 2] = tu_8x8_cr_cbf_r[ 3];
assign tu_cbf_z2s_cr8x8_ler_w[ 3] = 'd0;//tu_8x8_cr_cbf_r[ ];
assign tu_cbf_z2s_cr4x4_ler_w = 'd0;
//cb cbf 16x16, zscan to scan_idx scan
assign tu_cbf_z2s_cb16x16_w[ 0] = tu_16x16_cb_cbf_r[ 0];
assign tu_cbf_z2s_cb16x16_w[ 1] = tu_16x16_cb_cbf_r[ 2];
assign tu_cbf_z2s_cb16x16_w[ 2] = tu_16x16_cb_cbf_r[ 1];
assign tu_cbf_z2s_cb16x16_w[ 3] = tu_16x16_cb_cbf_r[ 8];
assign tu_cbf_z2s_cb16x16_w[ 4] = tu_16x16_cb_cbf_r[ 3];
assign tu_cbf_z2s_cb16x16_w[ 5] = tu_16x16_cb_cbf_r[ 4];
assign tu_cbf_z2s_cb16x16_w[ 6] = tu_16x16_cb_cbf_r[10];
assign tu_cbf_z2s_cb16x16_w[ 7] = tu_16x16_cb_cbf_r[ 9];
assign tu_cbf_z2s_cb16x16_w[ 8] = tu_16x16_cb_cbf_r[ 6];
assign tu_cbf_z2s_cb16x16_w[ 9] = tu_16x16_cb_cbf_r[ 5];
assign tu_cbf_z2s_cb16x16_w[10] = tu_16x16_cb_cbf_r[11];
assign tu_cbf_z2s_cb16x16_w[11] = tu_16x16_cb_cbf_r[12];
assign tu_cbf_z2s_cb16x16_w[12] = tu_16x16_cb_cbf_r[ 7];
assign tu_cbf_z2s_cb16x16_w[13] = tu_16x16_cb_cbf_r[14];
assign tu_cbf_z2s_cb16x16_w[14] = tu_16x16_cb_cbf_r[13];
assign tu_cbf_z2s_cb16x16_w[15] = tu_16x16_cb_cbf_r[15];
//cb cbf 8x8, zscan to scan_idx scan
assign tu_cbf_z2s_cb8x8_w[0] = tu_8x8_cb_cbf_r[0];
assign tu_cbf_z2s_cb8x8_w[1] = tu_8x8_cb_cbf_r[2];
assign tu_cbf_z2s_cb8x8_w[2] = tu_8x8_cb_cbf_r[1];
assign tu_cbf_z2s_cb8x8_w[3] = tu_8x8_cb_cbf_r[3];
//cb cbf 4x4
assign tu_cbf_z2s_cb4x4_w = tu_4x4_cb_cbf_r;
//cr cbf righter
assign tu_cbf_z2s_cb16x16_rer_w[ 0] = tu_16x16_cb_cbf_r[ 1];
assign tu_cbf_z2s_cb16x16_rer_w[ 1] = tu_16x16_cb_cbf_r[ 3];
assign tu_cbf_z2s_cb16x16_rer_w[ 2] = tu_16x16_cb_cbf_r[ 4];
assign tu_cbf_z2s_cb16x16_rer_w[ 3] = tu_16x16_cb_cbf_r[ 9];
assign tu_cbf_z2s_cb16x16_rer_w[ 4] = tu_16x16_cb_cbf_r[ 6];
assign tu_cbf_z2s_cb16x16_rer_w[ 5] = tu_16x16_cb_cbf_r[ 5];
assign tu_cbf_z2s_cb16x16_rer_w[ 6] = tu_16x16_cb_cbf_r[11];
assign tu_cbf_z2s_cb16x16_rer_w[ 7] = tu_16x16_cb_cbf_r[12];
assign tu_cbf_z2s_cb16x16_rer_w[ 8] = tu_16x16_cb_cbf_r[ 7];
assign tu_cbf_z2s_cb16x16_rer_w[ 9] = 'd0;//tu_16x16_cb_cbf_r[];
assign tu_cbf_z2s_cb16x16_rer_w[10] = tu_16x16_cb_cbf_r[14];
assign tu_cbf_z2s_cb16x16_rer_w[11] = tu_16x16_cb_cbf_r[13];
assign tu_cbf_z2s_cb16x16_rer_w[12] = 'd0;//tu_16x16_cb_cbf_r[];
assign tu_cbf_z2s_cb16x16_rer_w[13] = tu_16x16_cb_cbf_r[15];
assign tu_cbf_z2s_cb16x16_rer_w[14] = 'd0;//tu_16x16_cb_cbf_r[];
assign tu_cbf_z2s_cb16x16_rer_w[15] = 'd0;//tu_16x16_cb_cbf_r[15];
assign tu_cbf_z2s_cb8x8_rer_w[ 0] = tu_8x8_cb_cbf_r[ 1];
assign tu_cbf_z2s_cb8x8_rer_w[ 1] = tu_8x8_cb_cbf_r[ 3];
assign tu_cbf_z2s_cb8x8_rer_w[ 2] = 'd0;//tu_8x8_cb_cbf_r[ ];
assign tu_cbf_z2s_cb8x8_rer_w[ 3] = 'd0;//tu_8x8_cb_cbf_r[ ];
assign tu_cbf_z2s_cb4x4_rer_w = 'd0;
//cr cbf lower
assign tu_cbf_z2s_cb16x16_ler_w[ 0] = tu_16x16_cb_cbf_r[ 2];
assign tu_cbf_z2s_cb16x16_ler_w[ 1] = tu_16x16_cb_cbf_r[ 8];
assign tu_cbf_z2s_cb16x16_ler_w[ 2] = tu_16x16_cb_cbf_r[ 3];
assign tu_cbf_z2s_cb16x16_ler_w[ 3] = tu_16x16_cb_cbf_r[10];
assign tu_cbf_z2s_cb16x16_ler_w[ 4] = tu_16x16_cb_cbf_r[ 9];
assign tu_cbf_z2s_cb16x16_ler_w[ 5] = tu_16x16_cb_cbf_r[ 6];
assign tu_cbf_z2s_cb16x16_ler_w[ 6] = 'd0;//tu_16x16_cb_cbf_r[ ];
assign tu_cbf_z2s_cb16x16_ler_w[ 7] = tu_16x16_cb_cbf_r[11];
assign tu_cbf_z2s_cb16x16_ler_w[ 8] = tu_16x16_cb_cbf_r[12];
assign tu_cbf_z2s_cb16x16_ler_w[ 9] = tu_16x16_cb_cbf_r[ 7];
assign tu_cbf_z2s_cb16x16_ler_w[10] = 'd0;//tu_16x16_cb_cbf_r[14];
assign tu_cbf_z2s_cb16x16_ler_w[11] = tu_16x16_cb_cbf_r[14];
assign tu_cbf_z2s_cb16x16_ler_w[12] = tu_16x16_cb_cbf_r[13];
assign tu_cbf_z2s_cb16x16_ler_w[13] = 'd0;//tu_16x16_cb_cbf_r[15];
assign tu_cbf_z2s_cb16x16_ler_w[14] = tu_16x16_cb_cbf_r[15];
assign tu_cbf_z2s_cb16x16_ler_w[15] = 'd0;//tu_16x16_cb_cbf_r[15];
assign tu_cbf_z2s_cb8x8_ler_w[ 0] = tu_8x8_cb_cbf_r[ 2];
assign tu_cbf_z2s_cb8x8_ler_w[ 1] = 'd0;//tu_8x8_cb_cbf_r[ ];
assign tu_cbf_z2s_cb8x8_ler_w[ 2] = tu_8x8_cb_cbf_r[ 3];
assign tu_cbf_z2s_cb8x8_ler_w[ 3] = 'd0;//tu_8x8_cb_cbf_r[ ];
assign tu_cbf_z2s_cb4x4_ler_w = 'd0;
reg [255:0] last_blk_data_w ;
//last_blk_data_w
always @* begin
case(scan_idx_r)
(`SCAN_DIAG): begin
last_blk_data_w = {data_coeff_i[255:240], data_coeff_i[223:208], data_coeff_i[239:224], data_coeff_i[127:112],
data_coeff_i[207:192], data_coeff_i[191:176], data_coeff_i[ 95: 80], data_coeff_i[111: 96],
data_coeff_i[159:144], data_coeff_i[175:160], data_coeff_i[ 79: 64], data_coeff_i[ 63: 48],
data_coeff_i[143:128], data_coeff_i[ 31: 16], data_coeff_i[ 47: 32], data_coeff_i[ 15: 0]};
end
(`SCAN_HOR): begin
last_blk_data_w = {data_coeff_i[255:240], data_coeff_i[239:224], data_coeff_i[191:176], data_coeff_i[175:160],
data_coeff_i[223:208], data_coeff_i[207:192], data_coeff_i[159:144], data_coeff_i[143:128],
data_coeff_i[127:112], data_coeff_i[111: 96], data_coeff_i[ 63: 48], data_coeff_i[ 47: 32],
data_coeff_i[ 95: 80], data_coeff_i[ 79: 64], data_coeff_i[ 31: 16], data_coeff_i[ 15: 0]};
end
(`SCAN_VER): begin
last_blk_data_w = {data_coeff_i[255:240], data_coeff_i[223:208], data_coeff_i[127:112], data_coeff_i[ 95: 80],
data_coeff_i[239:224], data_coeff_i[207:192], data_coeff_i[111: 96], data_coeff_i[ 79: 64],
data_coeff_i[191:176], data_coeff_i[159:144], data_coeff_i[ 63: 48], data_coeff_i[ 31: 16],
data_coeff_i[175:160], data_coeff_i[143:128], data_coeff_i[ 47: 32], data_coeff_i[ 15: 0]};
end
default: begin
last_blk_data_w = 'd0;
end
endcase
end
//scan_res_data_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
scan_res_data_r <= 'd0;
else if(blk_e_done_r)
scan_res_data_r <= last_blk_data_w;
else
scan_res_data_r <= scan_res_data_r;
end
//always @(posedge clk or negedge rst_n) begin
// if(~rst_n)
// scan_res_data_r <= 'd0;
// else if(blk_e_done_r) begin
// case(scan_idx_r)
// (`SCAN_DIAG): begin
// scan_res_data_r <= {data_coeff_i[255:240], data_coeff_i[223:208], data_coeff_i[239:224], data_coeff_i[127:112],
// data_coeff_i[207:192], data_coeff_i[191:176], data_coeff_i[ 95: 80], data_coeff_i[111: 96],
// data_coeff_i[159:144], data_coeff_i[175:160], data_coeff_i[ 79: 64], data_coeff_i[ 63: 48],
// data_coeff_i[143:128], data_coeff_i[ 31: 16], data_coeff_i[ 47: 32], data_coeff_i[ 15: 0]};
// end
//
// (`SCAN_HOR): begin
// scan_res_data_r <= {data_coeff_i[255:240], data_coeff_i[239:224], data_coeff_i[191:176], data_coeff_i[175:160],
// data_coeff_i[223:208], data_coeff_i[207:192], data_coeff_i[159:144], data_coeff_i[143:128],
// data_coeff_i[127:112], data_coeff_i[111: 96], data_coeff_i[ 63: 48], data_coeff_i[ 47: 32],
// data_coeff_i[ 95: 80], data_coeff_i[ 79: 64], data_coeff_i[ 31: 16], data_coeff_i[ 15: 0]};
// end
//
// (`SCAN_VER): begin
// scan_res_data_r <= {data_coeff_i[255:240], data_coeff_i[223:208], data_coeff_i[127:112], data_coeff_i[ 95: 80],
// data_coeff_i[239:224], data_coeff_i[207:192], data_coeff_i[111: 96], data_coeff_i[ 79: 64],
// data_coeff_i[191:176], data_coeff_i[159:144], data_coeff_i[ 63: 48], data_coeff_i[ 31: 16],
// data_coeff_i[175:160], data_coeff_i[143:128], data_coeff_i[ 47: 32], data_coeff_i[ 15: 0]};
// end
//
// default: begin
// scan_res_data_r <= 'd0;
// end
// endcase
// end
//end
//rd_coeff_sig_w
assign rd_coeff_sig_w[15] = (scan_res_data_r[ 15: 0]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[14] = (scan_res_data_r[ 31: 16]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[13] = (scan_res_data_r[ 47: 32]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[12] = (scan_res_data_r[ 63: 48]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[11] = (scan_res_data_r[ 79: 64]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[10] = (scan_res_data_r[ 95: 80]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 9] = (scan_res_data_r[111: 96]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 8] = (scan_res_data_r[127:112]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 7] = (scan_res_data_r[143:128]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 6] = (scan_res_data_r[159:144]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 5] = (scan_res_data_r[175:160]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 4] = (scan_res_data_r[191:176]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 3] = (scan_res_data_r[207:192]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 2] = (scan_res_data_r[223:208]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 1] = (scan_res_data_r[239:224]=='d0) ? 'd0 : 'd1;
assign rd_coeff_sig_w[ 0] = (scan_res_data_r[255:240]=='d0) ? 'd0 : 'd1;
//enc_coeff_sig_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_coeff_sig_r <= 'd0;
else if(blk_e_done_r)
enc_coeff_sig_r <= rd_coeff_sig_w;
else
enc_coeff_sig_r <= enc_coeff_sig_r;
end
//rd_last_find_flag_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rd_last_find_flag_r <= 0;
else if(tu_curr_state_r==TU_LAST_SIG_0)
rd_last_find_flag_r <= 0;
else if(tu_done_r)
rd_last_find_flag_r <= 0;
else if(scan_cyc_cnt_r==7)
rd_last_find_flag_r <= rd_last_find_flag_r;
else if(scan_cyc_cnt_r=='d0) begin
if(coeff_a_b_r=='d0)
rd_last_find_flag_r <= 'd0;
else
rd_last_find_flag_r <= 'd1;
end
else if(coeff_a_b_r!=2'b00)
rd_last_find_flag_r <= 1;
else
rd_last_find_flag_r <= rd_last_find_flag_r;
end
//rd_last_coeff_idx_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rd_last_coeff_idx_r <= 'd0;
else if(~tu_en_w)
rd_last_coeff_idx_r <= 'd0;
else if(~rd_bin_cbf_w)
rd_last_coeff_idx_r <= 'd15;
else if(tu_curr_state_r==TU_LAST_SIG_0)
rd_last_coeff_idx_r <= 'd15;
else if(blk_e_done_r)
rd_last_coeff_idx_r <= 'd15;
else if(rd_last_find_flag_r && (scan_cyc_cnt_r!='d0))
rd_last_coeff_idx_r <= rd_last_coeff_idx_r;
else begin
case(coeff_a_b_r)
2'b00: rd_last_coeff_idx_r <= rd_last_coeff_idx_r - 2;
2'b01: rd_last_coeff_idx_r <= rd_last_coeff_idx_r - 1;
2'b10,
2'b11: rd_last_coeff_idx_r <= rd_last_coeff_idx_r;
default:rd_last_coeff_idx_r <= rd_last_coeff_idx_r;
endcase
end
end
//enc_last_coeff_idx_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_last_coeff_idx_r <= 'd0;
else if(blk_e_done_r) begin
if(rd_last_find_flag_r)
enc_last_coeff_idx_r <= rd_last_coeff_idx_r;
else begin
case(coeff_a_b_r[1])
1'b0: enc_last_coeff_idx_r <= 'd0;
1'b1: enc_last_coeff_idx_r <= 'd1;
default:enc_last_coeff_idx_r <= enc_last_coeff_idx_r;
endcase
end
end
else
enc_last_coeff_idx_r <= enc_last_coeff_idx_r;
end
//rd_non_zero_num_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rd_non_zero_num_r <= 'd0;
else if((~residual_en_i) || tu_done_r
|| blk_e_done_r || (tu_curr_state_r==TU_LAST_SIG_0))
rd_non_zero_num_r <= 'd0;
else if(scan_e_done_r)
rd_non_zero_num_r <= rd_non_zero_num_r;
else begin
case(coeff_a_b_r)
2'b00: rd_non_zero_num_r <= rd_non_zero_num_r;
2'b10,
2'b01: rd_non_zero_num_r <= rd_non_zero_num_r + 'd1;
2'b11: rd_non_zero_num_r <= rd_non_zero_num_r + 'd2;
default:rd_non_zero_num_r <= rd_non_zero_num_r;
endcase
end
end
//enc_coeff_tot_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_coeff_tot_r <= 0;
else if(~tu_en_w)
enc_coeff_tot_r <= 0;
else if(blk_e_done_r) begin
case(coeff_a_b_r)
2'b00: enc_coeff_tot_r <= rd_non_zero_num_r;
2'b01,
2'b10: enc_coeff_tot_r <= rd_non_zero_num_r + 'd1;
2'b11: enc_coeff_tot_r <= rd_non_zero_num_r + 'd2;
default:enc_coeff_tot_r <= rd_non_zero_num_r;
endcase
end
else
enc_coeff_tot_r <= enc_coeff_tot_r;
end
//rd_res_idx_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
rd_res_idx_r[0 ] <= 'd0;
rd_res_idx_r[1 ] <= 'd0;
rd_res_idx_r[2 ] <= 'd0;
rd_res_idx_r[3 ] <= 'd0;
rd_res_idx_r[4 ] <= 'd0;
rd_res_idx_r[5 ] <= 'd0;
rd_res_idx_r[6 ] <= 'd0;
rd_res_idx_r[7 ] <= 'd0;
rd_res_idx_r[8 ] <= 'd0;
rd_res_idx_r[9 ] <= 'd0;
rd_res_idx_r[10] <= 'd0;
rd_res_idx_r[11] <= 'd0;
rd_res_idx_r[12] <= 'd0;
rd_res_idx_r[13] <= 'd0;
rd_res_idx_r[14] <= 'd0;
rd_res_idx_r[15] <= 'd0;
end
else begin
case(coeff_a_b_r)
2'b01: rd_res_idx_r[rd_non_zero_num_r] <= (scan_cyc_cnt_r << 1) + 1;
2'b10: rd_res_idx_r[rd_non_zero_num_r] <= (scan_cyc_cnt_r << 1);
2'b11: begin
rd_res_idx_r[rd_non_zero_num_r] <= (scan_cyc_cnt_r << 1);
rd_res_idx_r[rd_non_zero_num_r+1] <= (scan_cyc_cnt_r << 1) + 1;
end
endcase
end
end
//-->test
wire [3:0] rd_res_idx_0_w ;
wire [3:0] rd_res_idx_1_w ;
wire [3:0] rd_res_idx_2_w ;
wire [3:0] rd_res_idx_3_w ;
wire [3:0] rd_res_idx_4_w ;
wire [3:0] rd_res_idx_5_w ;
wire [3:0] rd_res_idx_6_w ;
wire [3:0] rd_res_idx_7_w ;
wire [3:0] rd_res_idx_8_w ;
wire [3:0] rd_res_idx_9_w ;
wire [3:0] rd_res_idx_10_w ;
wire [3:0] rd_res_idx_11_w ;
wire [3:0] rd_res_idx_12_w ;
wire [3:0] rd_res_idx_13_w ;
wire [3:0] rd_res_idx_14_w ;
wire [3:0] rd_res_idx_15_w ;
wire [3:0] enc_res_idx_0_w ;
wire [3:0] enc_res_idx_1_w ;
wire [3:0] enc_res_idx_2_w ;
wire [3:0] enc_res_idx_3_w ;
wire [3:0] enc_res_idx_4_w ;
wire [3:0] enc_res_idx_5_w ;
wire [3:0] enc_res_idx_6_w ;
wire [3:0] enc_res_idx_7_w ;
wire [3:0] enc_res_idx_8_w ;
wire [3:0] enc_res_idx_9_w ;
wire [3:0] enc_res_idx_10_w ;
wire [3:0] enc_res_idx_11_w ;
wire [3:0] enc_res_idx_12_w ;
wire [3:0] enc_res_idx_13_w ;
wire [3:0] enc_res_idx_14_w ;
wire [3:0] enc_res_idx_15_w ;
assign rd_res_idx_0_w = rd_res_idx_r[0 ];
assign rd_res_idx_1_w = rd_res_idx_r[1 ];
assign rd_res_idx_2_w = rd_res_idx_r[2 ];
assign rd_res_idx_3_w = rd_res_idx_r[3 ];
assign rd_res_idx_4_w = rd_res_idx_r[4 ];
assign rd_res_idx_5_w = rd_res_idx_r[5 ];
assign rd_res_idx_6_w = rd_res_idx_r[6 ];
assign rd_res_idx_7_w = rd_res_idx_r[7 ];
assign rd_res_idx_8_w = rd_res_idx_r[8 ];
assign rd_res_idx_9_w = rd_res_idx_r[9 ];
assign rd_res_idx_10_w = rd_res_idx_r[10];
assign rd_res_idx_11_w = rd_res_idx_r[11];
assign rd_res_idx_12_w = rd_res_idx_r[12];
assign rd_res_idx_13_w = rd_res_idx_r[13];
assign rd_res_idx_14_w = rd_res_idx_r[14];
assign rd_res_idx_15_w = rd_res_idx_r[15];
assign enc_res_idx_0_w = enc_res_idx_r[0 ];
assign enc_res_idx_1_w = enc_res_idx_r[1 ];
assign enc_res_idx_2_w = enc_res_idx_r[2 ];
assign enc_res_idx_3_w = enc_res_idx_r[3 ];
assign enc_res_idx_4_w = enc_res_idx_r[4 ];
assign enc_res_idx_5_w = enc_res_idx_r[5 ];
assign enc_res_idx_6_w = enc_res_idx_r[6 ];
assign enc_res_idx_7_w = enc_res_idx_r[7 ];
assign enc_res_idx_8_w = enc_res_idx_r[8 ];
assign enc_res_idx_9_w = enc_res_idx_r[9 ];
assign enc_res_idx_10_w = enc_res_idx_r[10];
assign enc_res_idx_11_w = enc_res_idx_r[11];
assign enc_res_idx_12_w = enc_res_idx_r[12];
assign enc_res_idx_13_w = enc_res_idx_r[13];
assign enc_res_idx_14_w = enc_res_idx_r[14];
assign enc_res_idx_15_w = enc_res_idx_r[15];
//<--test
//enc_res_idx_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
enc_res_idx_r[0 ] <= 0;
enc_res_idx_r[1 ] <= 0;
enc_res_idx_r[2 ] <= 0;
enc_res_idx_r[3 ] <= 0;
enc_res_idx_r[4 ] <= 0;
enc_res_idx_r[5 ] <= 0;
enc_res_idx_r[6 ] <= 0;
enc_res_idx_r[7 ] <= 0;
enc_res_idx_r[8 ] <= 0;
enc_res_idx_r[9 ] <= 0;
enc_res_idx_r[10] <= 0;
enc_res_idx_r[11] <= 0;
enc_res_idx_r[12] <= 0;
enc_res_idx_r[13] <= 0;
enc_res_idx_r[14] <= 0;
enc_res_idx_r[15] <= 0;
end
else if(scan_cyc_cnt_r=='d0) begin
enc_res_idx_r[0 ] <= rd_res_idx_r[0 ];
enc_res_idx_r[1 ] <= rd_res_idx_r[1 ];
enc_res_idx_r[2 ] <= rd_res_idx_r[2 ];
enc_res_idx_r[3 ] <= rd_res_idx_r[3 ];
enc_res_idx_r[4 ] <= rd_res_idx_r[4 ];
enc_res_idx_r[5 ] <= rd_res_idx_r[5 ];
enc_res_idx_r[6 ] <= rd_res_idx_r[6 ];
enc_res_idx_r[7 ] <= rd_res_idx_r[7 ];
enc_res_idx_r[8 ] <= rd_res_idx_r[8 ];
enc_res_idx_r[9 ] <= rd_res_idx_r[9 ];
enc_res_idx_r[10] <= rd_res_idx_r[10];
enc_res_idx_r[11] <= rd_res_idx_r[11];
enc_res_idx_r[12] <= rd_res_idx_r[12];
enc_res_idx_r[13] <= rd_res_idx_r[13];
enc_res_idx_r[14] <= rd_res_idx_r[14];
enc_res_idx_r[15] <= rd_res_idx_r[15];
end
else begin
enc_res_idx_r[0 ] <= enc_res_idx_r[0 ];
enc_res_idx_r[1 ] <= enc_res_idx_r[1 ];
enc_res_idx_r[2 ] <= enc_res_idx_r[2 ];
enc_res_idx_r[3 ] <= enc_res_idx_r[3 ];
enc_res_idx_r[4 ] <= enc_res_idx_r[4 ];
enc_res_idx_r[5 ] <= enc_res_idx_r[5 ];
enc_res_idx_r[6 ] <= enc_res_idx_r[6 ];
enc_res_idx_r[7 ] <= enc_res_idx_r[7 ];
enc_res_idx_r[8 ] <= enc_res_idx_r[8 ];
enc_res_idx_r[9 ] <= enc_res_idx_r[9 ];
enc_res_idx_r[10] <= enc_res_idx_r[10];
enc_res_idx_r[11] <= enc_res_idx_r[11];
enc_res_idx_r[12] <= enc_res_idx_r[12];
enc_res_idx_r[13] <= enc_res_idx_r[13];
enc_res_idx_r[14] <= enc_res_idx_r[14];
enc_res_idx_r[15] <= enc_res_idx_r[15];
end
end
//enc_res_data_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
enc_res_data_r[0 ] <= 'd0;
enc_res_data_r[1 ] <= 'd0;
enc_res_data_r[2 ] <= 'd0;
enc_res_data_r[3 ] <= 'd0;
enc_res_data_r[4 ] <= 'd0;
enc_res_data_r[5 ] <= 'd0;
enc_res_data_r[6 ] <= 'd0;
enc_res_data_r[7 ] <= 'd0;
enc_res_data_r[8 ] <= 'd0;
enc_res_data_r[9 ] <= 'd0;
enc_res_data_r[10] <= 'd0;
enc_res_data_r[11] <= 'd0;
enc_res_data_r[12] <= 'd0;
enc_res_data_r[13] <= 'd0;
enc_res_data_r[14] <= 'd0;
enc_res_data_r[15] <= 'd0;
end
else if(blk_e_done_r) begin
enc_res_data_r[0 ] <= scan_res_data_r[15:0];
enc_res_data_r[1 ] <= scan_res_data_r[31:16];
enc_res_data_r[2 ] <= scan_res_data_r[47:32];
enc_res_data_r[3 ] <= scan_res_data_r[63:48];
enc_res_data_r[4 ] <= scan_res_data_r[79:64];
enc_res_data_r[5 ] <= scan_res_data_r[95:80];
enc_res_data_r[6 ] <= scan_res_data_r[111:96];
enc_res_data_r[7 ] <= scan_res_data_r[127:112];
enc_res_data_r[8 ] <= scan_res_data_r[143:128];
enc_res_data_r[9 ] <= scan_res_data_r[159:144];
enc_res_data_r[10] <= scan_res_data_r[175:160];
enc_res_data_r[11] <= scan_res_data_r[191:176];
enc_res_data_r[12] <= scan_res_data_r[207:192];
enc_res_data_r[13] <= scan_res_data_r[223:208];
enc_res_data_r[14] <= scan_res_data_r[239:224];
enc_res_data_r[15] <= scan_res_data_r[255:240];
end
else begin
enc_res_data_r[0 ] <= enc_res_data_r[0 ];
enc_res_data_r[1 ] <= enc_res_data_r[1 ];
enc_res_data_r[2 ] <= enc_res_data_r[2 ];
enc_res_data_r[3 ] <= enc_res_data_r[3 ];
enc_res_data_r[4 ] <= enc_res_data_r[4 ];
enc_res_data_r[5 ] <= enc_res_data_r[5 ];
enc_res_data_r[6 ] <= enc_res_data_r[6 ];
enc_res_data_r[7 ] <= enc_res_data_r[7 ];
enc_res_data_r[8 ] <= enc_res_data_r[8 ];
enc_res_data_r[9 ] <= enc_res_data_r[9 ];
enc_res_data_r[10] <= enc_res_data_r[10];
enc_res_data_r[11] <= enc_res_data_r[11];
enc_res_data_r[12] <= enc_res_data_r[12];
enc_res_data_r[13] <= enc_res_data_r[13];
enc_res_data_r[14] <= enc_res_data_r[14];
enc_res_data_r[15] <= enc_res_data_r[15];
end
end
assign enc_non_zero_0_w = enc_res_data_r[enc_res_idx_r[0 ]];
assign enc_non_zero_1_w = enc_res_data_r[enc_res_idx_r[1 ]];
assign enc_non_zero_2_w = enc_res_data_r[enc_res_idx_r[2 ]];
assign enc_non_zero_3_w = enc_res_data_r[enc_res_idx_r[3 ]];
assign enc_non_zero_4_w = enc_res_data_r[enc_res_idx_r[4 ]];
assign enc_non_zero_5_w = enc_res_data_r[enc_res_idx_r[5 ]];
assign enc_non_zero_6_w = enc_res_data_r[enc_res_idx_r[6 ]];
assign enc_non_zero_7_w = enc_res_data_r[enc_res_idx_r[7 ]];
assign enc_non_zero_8_w = enc_res_data_r[enc_res_idx_r[8 ]];
assign enc_non_zero_9_w = enc_res_data_r[enc_res_idx_r[9 ]];
assign enc_non_zero_10_w = enc_res_data_r[enc_res_idx_r[10]];
assign enc_non_zero_11_w = enc_res_data_r[enc_res_idx_r[11]];
assign enc_non_zero_12_w = enc_res_data_r[enc_res_idx_r[12]];
assign enc_non_zero_13_w = enc_res_data_r[enc_res_idx_r[13]];
assign enc_non_zero_14_w = enc_res_data_r[enc_res_idx_r[14]];
assign enc_non_zero_15_w = enc_res_data_r[enc_res_idx_r[15]];
//always @* begin
// if(tu_en_w) begin
assign enc_non_zero_abs_0_r = enc_non_zero_0_w[15] ? ((~enc_non_zero_0_w )+'d1) : enc_non_zero_0_w ;
assign enc_non_zero_abs_1_r = enc_non_zero_1_w[15] ? ((~enc_non_zero_1_w )+'d1) : enc_non_zero_1_w ;
assign enc_non_zero_abs_2_r = enc_non_zero_2_w[15] ? ((~enc_non_zero_2_w )+'d1) : enc_non_zero_2_w ;
assign enc_non_zero_abs_3_r = enc_non_zero_3_w[15] ? ((~enc_non_zero_3_w )+'d1) : enc_non_zero_3_w ;
assign enc_non_zero_abs_4_r = enc_non_zero_4_w[15] ? ((~enc_non_zero_4_w )+'d1) : enc_non_zero_4_w ;
assign enc_non_zero_abs_5_r = enc_non_zero_5_w[15] ? ((~enc_non_zero_5_w )+'d1) : enc_non_zero_5_w ;
assign enc_non_zero_abs_6_r = enc_non_zero_6_w[15] ? ((~enc_non_zero_6_w )+'d1) : enc_non_zero_6_w ;
assign enc_non_zero_abs_7_r = enc_non_zero_7_w[15] ? ((~enc_non_zero_7_w )+'d1) : enc_non_zero_7_w ;
assign enc_non_zero_abs_8_r = enc_non_zero_8_w[15] ? ((~enc_non_zero_8_w )+'d1) : enc_non_zero_8_w ;
assign enc_non_zero_abs_9_r = enc_non_zero_9_w[15] ? ((~enc_non_zero_9_w )+'d1) : enc_non_zero_9_w ;
assign enc_non_zero_abs_10_r = enc_non_zero_10_w[15] ? ((~enc_non_zero_10_w)+'d1) : enc_non_zero_10_w;
assign enc_non_zero_abs_11_r = enc_non_zero_11_w[15] ? ((~enc_non_zero_11_w)+'d1) : enc_non_zero_11_w;
assign enc_non_zero_abs_12_r = enc_non_zero_12_w[15] ? ((~enc_non_zero_12_w)+'d1) : enc_non_zero_12_w;
assign enc_non_zero_abs_13_r = enc_non_zero_13_w[15] ? ((~enc_non_zero_13_w)+'d1) : enc_non_zero_13_w;
assign enc_non_zero_abs_14_r = enc_non_zero_14_w[15] ? ((~enc_non_zero_14_w)+'d1) : enc_non_zero_14_w;
assign enc_non_zero_abs_15_r = enc_non_zero_15_w[15] ? ((~enc_non_zero_15_w)+'d1) : enc_non_zero_15_w;
// end
// else begin
// enc_non_zero_abs_0_r = 'd0;
// enc_non_zero_abs_1_r = 'd0;
// enc_non_zero_abs_2_r = 'd0;
// enc_non_zero_abs_3_r = 'd0;
// enc_non_zero_abs_4_r = 'd0;
// enc_non_zero_abs_5_r = 'd0;
// enc_non_zero_abs_6_r = 'd0;
// enc_non_zero_abs_7_r = 'd0;
// enc_non_zero_abs_8_r = 'd0;
// enc_non_zero_abs_9_r = 'd0;
// enc_non_zero_abs_10_r = 'd0;
// enc_non_zero_abs_11_r = 'd0;
// enc_non_zero_abs_12_r = 'd0;
// enc_non_zero_abs_13_r = 'd0;
// enc_non_zero_abs_14_r = 'd0;
// enc_non_zero_abs_15_r = 'd0;
// end
//end
//always @* begin
// if(tu_en_w) begin
assign enc_non_zero_abs_0_ge1_r = enc_non_zero_abs_0_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_1_ge1_r = enc_non_zero_abs_1_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_2_ge1_r = enc_non_zero_abs_2_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_3_ge1_r = enc_non_zero_abs_3_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_4_ge1_r = enc_non_zero_abs_4_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_5_ge1_r = enc_non_zero_abs_5_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_6_ge1_r = enc_non_zero_abs_6_r>'d1 ? 1 : 0;
assign enc_non_zero_abs_7_ge1_r = enc_non_zero_abs_7_r>'d1 ? 1 : 0;
// end
// else begin
// enc_non_zero_abs_0_ge1_r = 'd0;
// enc_non_zero_abs_1_ge1_r = 'd0;
// enc_non_zero_abs_2_ge1_r = 'd0;
// enc_non_zero_abs_3_ge1_r = 'd0;
// enc_non_zero_abs_4_ge1_r = 'd0;
// enc_non_zero_abs_5_ge1_r = 'd0;
// enc_non_zero_abs_6_ge1_r = 'd0;
// enc_non_zero_abs_7_ge1_r = 'd0;
// end
//end
//always @* begin
// if(tu_en_w) begin
assign enc_non_zero_abs_0_ge2_r = enc_non_zero_abs_0_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_1_ge2_r = enc_non_zero_abs_1_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_2_ge2_r = enc_non_zero_abs_2_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_3_ge2_r = enc_non_zero_abs_3_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_4_ge2_r = enc_non_zero_abs_4_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_5_ge2_r = enc_non_zero_abs_5_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_6_ge2_r = enc_non_zero_abs_6_r>'d2 ? 1 : 0;
assign enc_non_zero_abs_7_ge2_r = enc_non_zero_abs_7_r>'d2 ? 1 : 0;
// end
// else begin
// enc_non_zero_abs_0_ge2_r = 'd0;
// enc_non_zero_abs_1_ge2_r = 'd0;
// enc_non_zero_abs_2_ge2_r = 'd0;
// enc_non_zero_abs_3_ge2_r = 'd0;
// enc_non_zero_abs_4_ge2_r = 'd0;
// enc_non_zero_abs_5_ge2_r = 'd0;
// enc_non_zero_abs_6_ge2_r = 'd0;
// enc_non_zero_abs_7_ge2_r = 'd0;
// end
//end
//coeff_a_b_r
always @* begin
if(coeff_a_r!=0 && coeff_b_r!=0)
coeff_a_b_r = 2'b11;
else if(coeff_a_r!=0 && coeff_b_r==0)
coeff_a_b_r = 2'b10;
else if(coeff_a_r==0 && coeff_b_r!=0)
coeff_a_b_r = 2'b01;
else
coeff_a_b_r = 2'b00;
end
//coeff_a_r & coeff_b_r
always @* begin
case(scan_cyc_cnt_r)
0: begin coeff_a_r = scan_res_data_r[15 : 0 ]; coeff_b_r = scan_res_data_r[31 : 16 ]; end
1: begin coeff_a_r = scan_res_data_r[47 : 32 ]; coeff_b_r = scan_res_data_r[63 : 48 ]; end
2: begin coeff_a_r = scan_res_data_r[79 : 64 ]; coeff_b_r = scan_res_data_r[95 : 80 ]; end
3: begin coeff_a_r = scan_res_data_r[111 : 96 ]; coeff_b_r = scan_res_data_r[127 : 112]; end
4: begin coeff_a_r = scan_res_data_r[143 : 128]; coeff_b_r = scan_res_data_r[159 : 144]; end
5: begin coeff_a_r = scan_res_data_r[175 : 160]; coeff_b_r = scan_res_data_r[191 : 176]; end
6: begin coeff_a_r = scan_res_data_r[207 : 192]; coeff_b_r = scan_res_data_r[223 : 208]; end
7: begin coeff_a_r = scan_res_data_r[239 : 224]; coeff_b_r = scan_res_data_r[255 : 240]; end
default:
begin coeff_a_r = 0; coeff_b_r = 0; end
endcase
end
//enc_pattern_sig_ctx_r
always @* begin
if(sig_right_blk_r=='d0 && sig_lower_blk_r=='d0)
enc_pattern_sig_ctx_r = 'd0;
else if(sig_right_blk_r=='d0 && sig_lower_blk_r=='d1)
enc_pattern_sig_ctx_r = 'd2;
else if(sig_right_blk_r=='d1 && sig_lower_blk_r=='d0)
enc_pattern_sig_ctx_r = 'd1;
else
enc_pattern_sig_ctx_r = 'd3;
end
//sig_right_blk_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: sig_right_blk_r = tu_cbf_z2s_luma32x32_rer_w[blk_cbf_idx_r];
'd2: sig_right_blk_r = tu_cbf_z2s_luma16x16_rer_w[blk_cbf_idx_r];
'd3: sig_right_blk_r = tu_cbf_z2s_luma8x8_rer_r[blk_cbf_idx_r];
default: sig_right_blk_r = 'd0;
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF) begin
case(cu_depth_i)
'd0, 'd1: sig_right_blk_r = tu_cbf_z2s_cr16x16_rer_w[blk_cbf_idx_r];
'd2: sig_right_blk_r = tu_cbf_z2s_cr8x8_rer_w[blk_cbf_idx_r];
'd3: sig_right_blk_r = tu_cbf_z2s_cr4x4_rer_w;//[blk_cbf_idx_r];
default: sig_right_blk_r = 'd0;
endcase
end
else if(res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0, 'd1: sig_right_blk_r = tu_cbf_z2s_cb16x16_rer_w[blk_cbf_idx_r];
'd2: sig_right_blk_r = tu_cbf_z2s_cb8x8_rer_w[blk_cbf_idx_r];
'd3: sig_right_blk_r = tu_cbf_z2s_cb4x4_rer_w;//[blk_cbf_idx_r];
default: sig_right_blk_r = 'd0;
endcase
end
else
sig_right_blk_r = 'd0;
end
//sig_lower_blk_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: sig_lower_blk_r = tu_cbf_z2s_luma32x32_ler_w[blk_cbf_idx_r];
'd2: sig_lower_blk_r = tu_cbf_z2s_luma16x16_ler_w[blk_cbf_idx_r];
'd3: sig_lower_blk_r = tu_cbf_z2s_luma8x8_ler_r[blk_cbf_idx_r];
default: sig_lower_blk_r = 'd0;
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF) begin
case(cu_depth_i)
'd0, 'd1: sig_lower_blk_r = tu_cbf_z2s_cr16x16_ler_w[blk_cbf_idx_r];
'd2: sig_lower_blk_r = tu_cbf_z2s_cr8x8_ler_w[blk_cbf_idx_r];
'd3: sig_lower_blk_r = tu_cbf_z2s_cr4x4_ler_w;//[blk_cbf_idx_r];
default: sig_lower_blk_r = 'd0;
endcase
end
else if(res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0, 'd1: sig_lower_blk_r = tu_cbf_z2s_cb16x16_ler_w[blk_cbf_idx_r];
'd2: sig_lower_blk_r = tu_cbf_z2s_cb8x8_ler_w[blk_cbf_idx_r];
'd3: sig_lower_blk_r = tu_cbf_z2s_cb4x4_ler_w;//[blk_cbf_idx_r];
default: sig_lower_blk_r = 'd0;
endcase
end
else
sig_lower_blk_r = 'd0;
end
// *********************************************************
// root_cbf
assign ctx_pair_root_cbf_w = {2'b00, bin_string_root_cbf_w, ctx_idx_root_cbf_w};
//valid_num_bin_root_cbf_r
always @* begin
if(res_curr_state_r==RESIDUAL_ROOT_CBF && slice_type_i==(`SLICE_TYPE_P)) begin
valid_num_bin_root_cbf_r = 'd1;
end
else begin
valid_num_bin_root_cbf_r = 'd0;
end
end
//bin_string_root_cbf_w
assign bin_string_root_cbf_w = cbf_ne_zero_flag_w;
//ctx_idx_root_cbf_w
assign ctx_idx_root_cbf_w = {3'd3, 5'd0};
// *********************************************************
// chroma_root_cbf
assign ctx_pair_chroma_root_cbf_0_w = {2'b00, bin_string_chroma_root_cbf_w[1], ctx_idx_chroma_root_cbf_0_w};
assign ctx_pair_chroma_root_cbf_1_w = {2'b00, bin_string_chroma_root_cbf_w[0], ctx_idx_chroma_root_cbf_1_w};
//valid_num_bin_chroma_root_cbf_w
assign valid_num_bin_chroma_root_cbf_w = 'd2;
//bin_string_chroma_root_cbf_r
assign bin_string_chroma_root_cbf_w = {(cu_cr_cbf_r!='d0 ? 1'b1 : 1'b0), (cu_cb_cbf_r!='d0 ? 1'b1 : 1'b0)};
//ctx_idx_chroma_root_cbf_0_r
assign ctx_idx_chroma_root_cbf_0_w = {3'd2, 5'd1};//
assign ctx_idx_chroma_root_cbf_1_w = {3'd2, 5'd1};
// *********************************************************
// sub_div
assign ctx_pair_sub_div_w = {2'b00, bin_string_sub_div_r, ctx_idx_sub_div_r};
//valid_num_bin_sub_div_r
always @* begin
if(res_curr_state_r==RESIDUAL_SUB_DIV)
valid_num_bin_sub_div_r = 'd1;
else
valid_num_bin_sub_div_r = 'd0;
end
//bin_string_sub_div_r
always @* begin
if(res_curr_state_r==RESIDUAL_SUB_DIV)
bin_string_sub_div_r = 'd0;
else
bin_string_sub_div_r = 'd0;
end
//ctx_idx_sub_div_r
always @* begin
case(cu_depth_i)
'd0, 'd1: ctx_idx_sub_div_r = {3'd3, 5'd1};
'd2: ctx_idx_sub_div_r = {3'd1, 5'd0};
'd3: ctx_idx_sub_div_r = {3'd2, 5'd0};
default: ctx_idx_sub_div_r = {3'd3, 5'd1};
endcase
end
// *********************************************************
// chroma_cbf
assign ctx_pair_chroma_cbf_0_w = {2'b00, bin_string_chroma_cbf_w[1], ctx_idx_chroma_cbf_0_w};
assign ctx_pair_chroma_cbf_1_w = {2'b00, bin_string_chroma_cbf_w[0], ctx_idx_chroma_cbf_1_w};
//valid_num_bin_chroma_cbf_r
always @* begin
if(res_curr_state_r==RESIDUAL_CHROMA_CBF) begin
if(cu_cb_cbf_r!='d0 && cu_cr_cbf_r!='d0)
valid_num_bin_chroma_cbf_r = 'd2;
else if(cu_cr_cbf_r=='d0 && cu_cb_cbf_r=='d0)
valid_num_bin_chroma_cbf_r = 'd0;
else
valid_num_bin_chroma_cbf_r = 'd1;
end
else begin
valid_num_bin_chroma_cbf_r = 'd0;
end
end
//bin_string_chroma_cbf_r
assign bin_string_chroma_cbf_w = {(cu_cr_cbf_r!=0 ? (cu_cr_cbf_r[tu_cnt_r]!=0) : (cu_cb_cbf_r[tu_cnt_r]!=0)), (cu_cb_cbf_r[tu_cnt_r]!=0) };
// {(cu_cr_cbf_r[tu_cnt_r]!='d0 ? 1'b1 : 1'b0), (cu_cb_cbf_r[tu_cnt_r]!='d0 ? 1'b1 : 1'b0)};
//ctx_idx_chroma_cbf_0_r
assign ctx_idx_chroma_cbf_0_w = {3'd3, 5'd2};
assign ctx_idx_chroma_cbf_1_w = {3'd3, 5'd2};
// *********************************************************
// luma_cbf
assign ctx_pair_luma_cbf_w ={2'b00, bin_string_luma_cbf_r, ctx_idx_luma_cbf_r};
//valid_num_bin_luma_cbf_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_P) && cu_depth_i>'d0 && cu_cb_cbf_r=='d0 && cu_cr_cbf_r=='d0)
valid_num_bin_luma_cbf_r = 'd0;
else
valid_num_bin_luma_cbf_r = 'd1;
end
//bin_string_luma_cbf_r
always @* begin
if(cu_depth_i=='d0)
bin_string_luma_cbf_r = cu_luma_cbf_r[tu_cnt_r];
else
bin_string_luma_cbf_r = cu_luma_cbf_r!='d0;
end
//ctx_idx_luma_cbf_r
always @* begin
if(cu_depth_i=='d0)
ctx_idx_luma_cbf_r = {3'd0, 5'd0};
else
ctx_idx_luma_cbf_r = {3'd1, 5'd1};
end
// *********************************************************
// qp_delta
//reg [10:0] ctx_pair_qp_delta_0_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_1_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_2_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_3_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_4_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_5_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_6_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_7_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_8_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_9_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_10_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_11_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_12_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_13_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_14_w ; //context pair of qp_delta
//reg [10:0] ctx_pair_qp_delta_15_w ; //context pair of qp_delta
//
//
//reg [3:0] valid_num_bin_qp_delta_r ; //valid number bin of qp_delta
//reg [2:0] valid_num_bin_qp_delta_pre_r ; //valid number bin of qp_delta prefix
//reg [3:0] valid_num_bin_qp_delta_suf_r ; //valid number bin of qp_delta suffix
//reg [1:0] qp_delta_pre_cyc_tot_r ; //prefix cycle total
//reg [2:0] qp_delta_suf_cyc_tot_r ; //suffix cycle total
//reg [2:0] qp_delta_cyc_tot_r ; //total cycle
//reg [2:0] qp_delta_cyc_cnt_r ; //total cycle count
//reg [15:0] bin_string_qp_delta_r ; //bin string of qp_delta
//
//
//reg [5:0] cu_qp_r ; //current cu qp
//reg [5:0] cu_qp_left_r ; //left cu qp
//reg [5:0] cu_qp_top_r ; //top cu qp
//reg [5:0] cu_qp_last_r ; //last cu qp
//reg [5:0] ref_qp_r ; //reference cu qp
//reg signed [5:0] qp_delta_r ; //qp delta
//reg [5:0] qp_delta_abs_r ; //qp delta abs
//wire [5:0] qp_delta_abs_m5_w ; //qp delta abs minus 5
//reg [2:0] tu_value_r ; //min(qp_delta_abs_r, 5)
//reg qp_suffix_r ; //suffix flag
//wire qp_delta_sign_w ; //qp delta sign
//
//
//wire [5:0] qp_delta_abs_m5m1_w ;
//wire [5:0] qp_delta_abs_m5m3_w ;
//wire [5:0] qp_delta_abs_m5m7_w ;
//wire [5:0] qp_delta_abs_m5m15_w ;
reg [5:0] slice_qp_r ;
reg [5:0] qp_of_cu_r [63:0] ;
assign qp_delta_sign_w = qp_delta_r[5];
assign qp_delta_abs_m5_w = qp_delta_abs_r - 'd5;
//cu_qp_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
cu_qp_r <= 'd0;
else if(residual_en_i) begin
cu_qp_r <= cu_qp_i;
end
else
cu_qp_r <= 'd0;
end
//cu_qp_left_r
always @* begin
case(cu_idx_i)
'd0, 'd1, 'd3, 'd5, 'd7,
'd13, 'd15, 'd21, 'd23,
'd29, 'd31, 'd53, 'd55,
'd61, 'd63:
cu_qp_left_r = 'h3f;
default:
cu_qp_left_r = cu_qp_r;
endcase
end
//cu_qp_top_r
always @* begin
case(cu_idx_i)
'd0, 'd1, 'd2, 'd5, 'd6,
'd9, 'd10, 'd21, 'd22,
'd25, 'd26, 'd37, 'd38,
'd41, 'd42:
cu_qp_top_r = 'h3f;
default:
cu_qp_top_r = cu_qp_r;
endcase
end
//cu_qp_last_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
cu_qp_last_r <= 'd0;
else if(~residual_en_i)
cu_qp_last_r <= cu_qp_last_r;
else if(residual_done_r) begin
if(~cbf_ne_zero_flag_w)
cu_qp_last_r <= cu_qp_last_r;
else
cu_qp_last_r <= cu_qp_r;
end
else if(mb_x_i=='d0 && mb_y_i=='d0 &&
(cu_idx_i==0 || cu_idx_i==1 || cu_idx_i==5 || cu_idx_i==21))
cu_qp_last_r <= cu_qp_i;// (`INIT_QP);
else
cu_qp_last_r <= cu_qp_last_r;
end
//ref_qp_r
always @* begin
if(res_curr_state_r==RESIDUAL_DQP)
ref_qp_r = ((cu_qp_left_r=='h3f ? cu_qp_last_r : cu_qp_left_r) +
(cu_qp_top_r=='h3f ? cu_qp_last_r : cu_qp_top_r) + 'd1) >> 1;
else
ref_qp_r = 'd0;
end
//qp_delta_r
always @* begin
if(res_curr_state_r==RESIDUAL_DQP)
qp_delta_r = cu_qp_r - ref_qp_r;
else
qp_delta_r = 'd0;
end
//qp_delta_abs_r
always @* begin
if(res_curr_state_r==RESIDUAL_DQP)
qp_delta_abs_r = qp_delta_r[5] ? ((~qp_delta_r)+1) : qp_delta_r;
else
qp_delta_abs_r = 'd0;
end
//tu_value_r
always @* begin
if(res_curr_state_r==RESIDUAL_DQP)
tu_value_r = qp_delta_abs_r<'d5 ? qp_delta_abs_r : 'd5;
else
tu_value_r = 'd0;
end
// qp_delta
always @* begin
if(qp_suffix_r) begin
ctx_pair_qp_delta_0_w = {2'b01, bin_string_qp_delta_r[15], 8'd0};
ctx_pair_qp_delta_1_w = {2'b01, bin_string_qp_delta_r[14], 8'd0};
ctx_pair_qp_delta_2_w = {2'b01, bin_string_qp_delta_r[13], 8'd0};
ctx_pair_qp_delta_3_w = {2'b01, bin_string_qp_delta_r[12], 8'd0};
ctx_pair_qp_delta_4_w = {2'b01, bin_string_qp_delta_r[11], 8'd0};
ctx_pair_qp_delta_5_w = {2'b01, bin_string_qp_delta_r[10], 8'd0};
ctx_pair_qp_delta_6_w = {2'b01, bin_string_qp_delta_r[ 9], 8'd0};
ctx_pair_qp_delta_7_w = {2'b01, bin_string_qp_delta_r[ 8], 8'd0};
ctx_pair_qp_delta_8_w = {2'b01, bin_string_qp_delta_r[ 7], 8'd0};
ctx_pair_qp_delta_9_w = {2'b01, bin_string_qp_delta_r[ 6], 8'd0};
ctx_pair_qp_delta_10_w = {2'b01, bin_string_qp_delta_r[ 5], 8'd0};
ctx_pair_qp_delta_11_w = {2'b01, bin_string_qp_delta_r[ 4], 8'd0};
ctx_pair_qp_delta_12_w = {2'b01, bin_string_qp_delta_r[ 3], 8'd0};
ctx_pair_qp_delta_13_w = {2'b01, bin_string_qp_delta_r[ 2], 8'd0};
ctx_pair_qp_delta_14_w = {2'b01, bin_string_qp_delta_r[ 1], 8'd0};
ctx_pair_qp_delta_15_w = {2'b01, bin_string_qp_delta_r[ 0], 8'd0};
end
else begin
ctx_pair_qp_delta_0_w = {2'b00, bin_string_qp_delta_r[15], 3'd3, 5'd3}; //0
ctx_pair_qp_delta_1_w = {2'b00, bin_string_qp_delta_r[14], 3'd1, 5'd2}; //1
ctx_pair_qp_delta_2_w = {2'b00, bin_string_qp_delta_r[13], 3'd1, 5'd2}; //1
ctx_pair_qp_delta_3_w = {2'b00, bin_string_qp_delta_r[12], 3'd1, 5'd2}; //1
ctx_pair_qp_delta_4_w = {2'b00, bin_string_qp_delta_r[11], 3'd1, 5'd2};
ctx_pair_qp_delta_5_w = {2'b00, bin_string_qp_delta_r[10], 3'd1, 5'd2};
ctx_pair_qp_delta_6_w = {2'b00, bin_string_qp_delta_r[ 9], 3'd1, 5'd2};
ctx_pair_qp_delta_7_w = {2'b00, bin_string_qp_delta_r[ 8], 3'd1, 5'd2};
ctx_pair_qp_delta_8_w = {2'b00, bin_string_qp_delta_r[ 7], 3'd1, 5'd2};
ctx_pair_qp_delta_9_w = {2'b00, bin_string_qp_delta_r[ 6], 3'd1, 5'd2};
ctx_pair_qp_delta_10_w = {2'b00, bin_string_qp_delta_r[ 5], 3'd1, 5'd2};
ctx_pair_qp_delta_11_w = {2'b00, bin_string_qp_delta_r[ 4], 3'd1, 5'd2};
ctx_pair_qp_delta_12_w = {2'b00, bin_string_qp_delta_r[ 3], 3'd1, 5'd2};
ctx_pair_qp_delta_13_w = {2'b00, bin_string_qp_delta_r[ 2], 3'd1, 5'd2};
ctx_pair_qp_delta_14_w = {2'b00, bin_string_qp_delta_r[ 1], 3'd1, 5'd2};
ctx_pair_qp_delta_15_w = {2'b00, bin_string_qp_delta_r[ 0], 3'd1, 5'd2};
end
end
//valid_num_bin_qp_delta_pre_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
valid_num_bin_qp_delta_pre_r = 'd0;
else if(qp_delta_abs_r=='d0)
valid_num_bin_qp_delta_pre_r = 'd1;
else if(qp_delta_abs_r<'d5)
valid_num_bin_qp_delta_pre_r = 'd1 + tu_value_r;
else
valid_num_bin_qp_delta_pre_r = 'd5;
end
//valid_num_bin_qp_delta_suf_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
valid_num_bin_qp_delta_suf_r = 'd0;
else if(qp_delta_abs_r=='d0)
valid_num_bin_qp_delta_suf_r = 'd0;
else if(qp_delta_abs_r<'d5)
valid_num_bin_qp_delta_suf_r = 'd1;
else begin
case(qp_delta_abs_m5_w)
'd0: valid_num_bin_qp_delta_suf_r = 'd2;
'd1, 'd2: valid_num_bin_qp_delta_suf_r = 'd4;
'd3, 'd4, 'd5, 'd6: valid_num_bin_qp_delta_suf_r = 'd6;
'd7, 'd8, 'd9, 'd10,
'd11, 'd12, 'd13, 'd14: valid_num_bin_qp_delta_suf_r = 'd8;
default: valid_num_bin_qp_delta_suf_r = 'd10;
endcase
end
end
//qp_delta_pre_cyc_tot_r
always @* begin
case(valid_num_bin_qp_delta_pre_r)
'd0: qp_delta_pre_cyc_tot_r = 'd0;
'd1, 'd2, 'd3, 'd4: qp_delta_pre_cyc_tot_r = 'd1;
'd5, 'd6, 'd7, 'd8: qp_delta_pre_cyc_tot_r = 'd2;
default: qp_delta_pre_cyc_tot_r = 'd0;
endcase
end
//qp_delta_suf_cyc_tot_r
always @* begin
case(valid_num_bin_qp_delta_suf_r)
'd0: qp_delta_suf_cyc_tot_r = 'd0;
'd1, 'd2, 'd3, 'd4: qp_delta_suf_cyc_tot_r = 'd1;
'd5, 'd6, 'd7, 'd8: qp_delta_suf_cyc_tot_r = 'd2;
'd9, 'd10, 'd11, 'd12:qp_delta_suf_cyc_tot_r = 'd3;
default: qp_delta_suf_cyc_tot_r = 'd0;
endcase
end
//qp_delta_cyc_tot_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
qp_delta_cyc_tot_r = 'd0;
else
qp_delta_cyc_tot_r = qp_delta_pre_cyc_tot_r + qp_delta_suf_cyc_tot_r;
end
//qp_delta_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
qp_delta_cyc_cnt_r <= 'd0;
else if(res_curr_state_r!=RESIDUAL_DQP)
qp_delta_cyc_cnt_r <= 'd0;
else if(qp_delta_cyc_cnt_r==(qp_delta_cyc_tot_r-1))
qp_delta_cyc_cnt_r <= 'd0;
else
qp_delta_cyc_cnt_r <= qp_delta_cyc_cnt_r + 'd1;
end
//qp_suffix_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
qp_suffix_r = 'd0;
else if(qp_delta_cyc_cnt_r<qp_delta_pre_cyc_tot_r)
qp_suffix_r = 'd0;
else
qp_suffix_r = 'd1;
end
//valid_num_bin_qp_delta_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
valid_num_bin_qp_delta_r = 'd0;
else if(qp_suffix_r) begin
if(cu_depth_i=='d0 && tu_cnt_r!='d0)
valid_num_bin_qp_delta_r = 'd0;
else
valid_num_bin_qp_delta_r = valid_num_bin_qp_delta_suf_r;
end
else begin
if(cu_depth_i=='d0 && tu_cnt_r!='d0)
valid_num_bin_qp_delta_r = 'd0;
else
valid_num_bin_qp_delta_r = valid_num_bin_qp_delta_pre_r;
end
end
assign qp_delta_abs_m5m1_w = qp_delta_abs_r - 'd6;
assign qp_delta_abs_m5m3_w = qp_delta_abs_r - 'd8;
assign qp_delta_abs_m5m7_w = qp_delta_abs_r - 'd12;
assign qp_delta_abs_m5m15_w = qp_delta_abs_r - 'd20;
//bin_string_qp_delta_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
bin_string_qp_delta_r = 'd0;
else if(qp_suffix_r) begin
if(qp_delta_abs_r<5)
bin_string_qp_delta_r = {qp_delta_sign_w, 15'd0};
else begin
case(qp_delta_abs_m5_w)
'd0: bin_string_qp_delta_r = {1'b0, qp_delta_sign_w, 14'd0};
'd1, 'd2: bin_string_qp_delta_r = {2'b10, qp_delta_abs_m5m1_w[0], qp_delta_sign_w, 12'd0};
'd3, 'd4, 'd5, 'd6: bin_string_qp_delta_r = {3'b110, qp_delta_abs_m5m3_w[1:0], qp_delta_sign_w, 10'd0};
'd7, 'd8, 'd9, 'd10,
'd11, 'd12, 'd13, 'd14: bin_string_qp_delta_r = {4'b1110, qp_delta_abs_m5m7_w[2:0], qp_delta_sign_w, 8'd0};
default: bin_string_qp_delta_r = {5'b11110, qp_delta_abs_m5m15_w[3:0], qp_delta_sign_w, 6'd0};
endcase
end
end
else begin
case(tu_value_r)
'd0: bin_string_qp_delta_r = 'd0;
'd1: bin_string_qp_delta_r = {1'b1, 15'd0};
'd2: bin_string_qp_delta_r = {1'b1, 1'b1, 14'd0};
'd3: bin_string_qp_delta_r = {1'b1, 2'b11, 13'd0};
'd4: bin_string_qp_delta_r = {1'b1, 3'b111, 12'd0};
default:bin_string_qp_delta_r = {1'b1, 4'b1111, 11'd0};
endcase
end
end
//qp_done_r
always @* begin
if(res_curr_state_r!=RESIDUAL_DQP)
qp_done_r = 'd0;
else if(qp_delta_cyc_cnt_r==(qp_delta_cyc_tot_r-1))
qp_done_r = 'd1;
else
qp_done_r = 'd0;
end
// ******************************************************
// transform_skip
assign ctx_pair_transform_skip_w = {2'b00, 1'b0, ctx_idx_transform_skip_w};
assign ctx_idx_transform_skip_w = (res_curr_state_r==RESIDUAL_LUMA_COEFF) ? {3'd3, 5'd4} : {3'd2, 5'd2};
// *******************************************************
// last_significant_xy
assign ctx_pair_last_x_prefix_0_w = {2'b00, bin_string_last_x_prefix_r[9], ctx_idx_last_x_prefix_0_r};
assign ctx_pair_last_x_prefix_1_w = {2'b00, bin_string_last_x_prefix_r[8], ctx_idx_last_x_prefix_1_r};
assign ctx_pair_last_x_prefix_2_w = {2'b00, bin_string_last_x_prefix_r[7], ctx_idx_last_x_prefix_2_r};
assign ctx_pair_last_x_prefix_3_w = {2'b00, bin_string_last_x_prefix_r[6], ctx_idx_last_x_prefix_3_r};
assign ctx_pair_last_x_prefix_4_w = {2'b00, bin_string_last_x_prefix_r[5], ctx_idx_last_x_prefix_4_r};
assign ctx_pair_last_x_prefix_5_w = {2'b00, bin_string_last_x_prefix_r[4], ctx_idx_last_x_prefix_5_r};
assign ctx_pair_last_x_prefix_6_w = {2'b00, bin_string_last_x_prefix_r[3], ctx_idx_last_x_prefix_6_r};
assign ctx_pair_last_x_prefix_7_w = {2'b00, bin_string_last_x_prefix_r[2], ctx_idx_last_x_prefix_7_r};
assign ctx_pair_last_x_prefix_8_w = {2'b00, bin_string_last_x_prefix_r[1], ctx_idx_last_x_prefix_8_r};
assign ctx_pair_last_x_prefix_9_w = {2'b00, bin_string_last_x_prefix_r[0], ctx_idx_last_x_prefix_9_r};
assign ctx_pair_last_y_prefix_0_w = {2'b00, bin_string_last_y_prefix_r[9], ctx_idx_last_y_prefix_0_r};
assign ctx_pair_last_y_prefix_1_w = {2'b00, bin_string_last_y_prefix_r[8], ctx_idx_last_y_prefix_1_r};
assign ctx_pair_last_y_prefix_2_w = {2'b00, bin_string_last_y_prefix_r[7], ctx_idx_last_y_prefix_2_r};
assign ctx_pair_last_y_prefix_3_w = {2'b00, bin_string_last_y_prefix_r[6], ctx_idx_last_y_prefix_3_r};
assign ctx_pair_last_y_prefix_4_w = {2'b00, bin_string_last_y_prefix_r[5], ctx_idx_last_y_prefix_4_r};
assign ctx_pair_last_y_prefix_5_w = {2'b00, bin_string_last_y_prefix_r[4], ctx_idx_last_y_prefix_5_r};
assign ctx_pair_last_y_prefix_6_w = {2'b00, bin_string_last_y_prefix_r[3], ctx_idx_last_y_prefix_6_r};
assign ctx_pair_last_y_prefix_7_w = {2'b00, bin_string_last_y_prefix_r[2], ctx_idx_last_y_prefix_7_r};
assign ctx_pair_last_y_prefix_8_w = {2'b00, bin_string_last_y_prefix_r[1], ctx_idx_last_y_prefix_8_r};
assign ctx_pair_last_y_prefix_9_w = {2'b00, bin_string_last_y_prefix_r[0], ctx_idx_last_y_prefix_9_r};
assign ctx_pair_last_x_suffix_0_w = {2'b01, bin_string_last_x_suffix_r[2], 8'd0};
assign ctx_pair_last_x_suffix_1_w = {2'b01, bin_string_last_x_suffix_r[1], 8'd0};
assign ctx_pair_last_x_suffix_2_w = {2'b01, bin_string_last_x_suffix_r[0], 8'd0};
assign ctx_pair_last_y_suffix_0_w = {2'b01, bin_string_last_y_suffix_r[2], 8'd0};
assign ctx_pair_last_y_suffix_1_w = {2'b01, bin_string_last_y_suffix_r[1], 8'd0};
assign ctx_pair_last_y_suffix_2_w = {2'b01, bin_string_last_y_suffix_r[0], 8'd0};
//last_sig_enc_done_r
always @* begin
if(last_xy_cyc_cnt_r==(last_xy_cyc_tot_w-1))
last_sig_enc_done_r = 'd1;
else
last_sig_enc_done_r = 'd0;
end
//last_x_prefix_cyc_tot_r
always @* begin
case(valid_num_bin_last_x_prefix_w)
'd0: last_x_prefix_cyc_tot_r = 'd0;
'd1, 'd2, 'd3, 'd4: last_x_prefix_cyc_tot_r = 'd1;
'd5, 'd6, 'd7, 'd8: last_x_prefix_cyc_tot_r = 'd2;
'd9, 'd10: last_x_prefix_cyc_tot_r = 'd3;
default: last_x_prefix_cyc_tot_r = 'd0;
endcase
end
//last_y_prefix_cyc_tot_r
always @* begin
case(valid_num_bin_last_y_prefix_w)
'd0: last_y_prefix_cyc_tot_r = 'd0;
'd1, 'd2, 'd3, 'd4: last_y_prefix_cyc_tot_r = 'd1;
'd5, 'd6, 'd7, 'd8: last_y_prefix_cyc_tot_r = 'd2;
'd9, 'd10: last_y_prefix_cyc_tot_r = 'd3;
default: last_y_prefix_cyc_tot_r = 'd0;
endcase
end
//last_x_suffix_cyc_tot_r
always @* begin
if(valid_num_bin_last_x_suffix_r!='d0)
last_x_suffix_cyc_tot_r = 'd1;
else
last_x_suffix_cyc_tot_r = 'd0;
end
//last_y_suffix_cyc_tot_r
always @* begin
if(valid_num_bin_last_y_suffix_r!='d0)
last_y_suffix_cyc_tot_r = 'd1;
else
last_y_suffix_cyc_tot_r = 'd0;
end
//last_xy_cyc_tot_w
assign last_xy_cyc_tot_w = last_x_prefix_cyc_tot_r + last_x_suffix_cyc_tot_r
+ last_y_prefix_cyc_tot_r + last_y_suffix_cyc_tot_r;
//last_xy_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
last_xy_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r!=TU_LAST_SIG)
last_xy_cyc_cnt_r <= 'd0;
else if(last_xy_cyc_cnt_r==last_xy_cyc_tot_w)
last_xy_cyc_cnt_r <= last_xy_cyc_tot_w;
else
last_xy_cyc_cnt_r <= last_xy_cyc_cnt_r + 'd1;
end
//last_xy_r
always @* begin
if(last_xy_cyc_cnt_r<last_x_prefix_cyc_tot_r)
last_xy_r = 'd0;
else if(last_xy_cyc_cnt_r>=last_x_prefix_cyc_tot_r
&& last_xy_cyc_cnt_r<(last_x_prefix_cyc_tot_r+last_y_prefix_cyc_tot_r))
last_xy_r = 'd1;
else if(last_x_suffix_cyc_tot_r && last_xy_cyc_cnt_r==(last_x_prefix_cyc_tot_r+last_y_prefix_cyc_tot_r))
last_xy_r = 'd2;
else if(last_xy_cyc_cnt_r<last_xy_cyc_tot_w)
last_xy_r = 'd3;
else
last_xy_r = 'd7;
end
//valid_num_bin_last_x_prefix_w
assign valid_num_bin_last_x_prefix_w = group_idx_x_r + group_idx_x_1_r;
//valid_num_bin_last_y_prefix_w
assign valid_num_bin_last_y_prefix_w = group_idx_y_r + group_idx_y_1_r;
//valid_num_bin_last_x_suffix_r
always @* begin
if(group_idx_x_r>3) begin
case(group_idx_x_r)
4, 5: valid_num_bin_last_x_suffix_r = 'd1;
6, 7: valid_num_bin_last_x_suffix_r = 'd2;
8, 9: valid_num_bin_last_x_suffix_r = 'd3;
default:valid_num_bin_last_x_suffix_r = 'd0;
endcase
end
else
valid_num_bin_last_x_suffix_r = 'd0;
end
//valid_num_bin_last_y_suffix_r
always @* begin
if(group_idx_y_r>3) begin
case(group_idx_y_r)
4, 5: valid_num_bin_last_y_suffix_r = 'd1;
6, 7: valid_num_bin_last_y_suffix_r = 'd2;
8, 9: valid_num_bin_last_y_suffix_r = 'd3;
default:valid_num_bin_last_y_suffix_r = 'd0;
endcase
end
else
valid_num_bin_last_y_suffix_r = 'd0;
end
//bin_string_last_x_prefix_r
always @* begin
case(group_idx_x_r)
0: bin_string_last_x_prefix_r = 'b00_0000_0000;
1: bin_string_last_x_prefix_r = 'b10_0000_0000;
2: bin_string_last_x_prefix_r = 'b11_0000_0000;
3: bin_string_last_x_prefix_r = 'b11_1000_0000;
4: bin_string_last_x_prefix_r = 'b11_1100_0000;
5: bin_string_last_x_prefix_r = 'b11_1110_0000;
6: bin_string_last_x_prefix_r = 'b11_1111_0000;
7: bin_string_last_x_prefix_r = 'b11_1111_1000;
8: bin_string_last_x_prefix_r = 'b11_1111_1100;
9: bin_string_last_x_prefix_r = 'b11_1111_1110;
default:bin_string_last_x_prefix_r = 'b00_0000_0000;
endcase
end
//bin_string_last_y_prefix_r
always @* begin
case(group_idx_y_r)
0: bin_string_last_y_prefix_r = 'b00_0000_0000;
1: bin_string_last_y_prefix_r = 'b10_0000_0000;
2: bin_string_last_y_prefix_r = 'b11_0000_0000;
3: bin_string_last_y_prefix_r = 'b11_1000_0000;
4: bin_string_last_y_prefix_r = 'b11_1100_0000;
5: bin_string_last_y_prefix_r = 'b11_1110_0000;
6: bin_string_last_y_prefix_r = 'b11_1111_0000;
7: bin_string_last_y_prefix_r = 'b11_1111_1000;
8: bin_string_last_y_prefix_r = 'b11_1111_1100;
9: bin_string_last_y_prefix_r = 'b11_1111_1110;
default:bin_string_last_y_prefix_r = 'b00_0000_0000;
endcase
end
//bin_string_last_x_suffix_r
always @* begin
case(valid_num_bin_last_x_suffix_r)
'd0: bin_string_last_x_suffix_r = 3'b000;
'd1: bin_string_last_x_suffix_r = {pos_x_mar_r[0], 2'b00};
'd2: bin_string_last_x_suffix_r = {pos_x_mar_r[1:0], 1'b0};
'd3: bin_string_last_x_suffix_r = pos_x_mar_r[2:0];
default:bin_string_last_x_suffix_r = 3'b000;
endcase
end
//bin_string_last_y_suffix_r
always @* begin
case(valid_num_bin_last_y_suffix_r)
'd0: bin_string_last_y_suffix_r = 3'b000;
'd1: bin_string_last_y_suffix_r = {pos_y_mar_r[0], 2'b00};
'd2: bin_string_last_y_suffix_r = {pos_y_mar_r[1:0], 1'b0};
'd3: bin_string_last_y_suffix_r = pos_y_mar_r[2:0];
default:bin_string_last_y_suffix_r = 3'b000;
endcase
end
//ctx_idx_last_x_prefix_0_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_0_r = {3'd0, 5'd4};//'d10; //10+(0>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_0_r = {3'd0, 5'd3};//'d6; //6+(0>>1) luma
end
'd3: begin
ctx_idx_last_x_prefix_0_r = {3'd0, 5'd2};//'d3; //3+(0>>1) luma
end
default: begin
ctx_idx_last_x_prefix_0_r = 'd0;
end
endcase
end
else begin
ctx_idx_last_x_prefix_0_r = {3'd0, 5'd6};//'d15; //15+0+(0>>1) chroma
end
end
// ctx_idx_last_x_prefix_1_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_1_r = {3'd0, 5'd4};//'d10; //10+(1>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_1_r = {3'd0, 5'd3};//'d6; //6+(1>>1) luma
end
'd3: begin
ctx_idx_last_x_prefix_1_r = {3'd0, 5'd2};//'d3; //3+(1>>1) luma
end
default: begin
ctx_idx_last_x_prefix_1_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1, 'd2: begin
ctx_idx_last_x_prefix_1_r = {3'd0, 5'd6};//'d15; //15+0+(1>>2) chroma
end
'd3: begin
ctx_idx_last_x_prefix_1_r = {3'd1, 5'd8};//'d16; //15+0+(1>>0) chroma
end
default: begin
ctx_idx_last_x_prefix_1_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_2_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_2_r = {3'd1, 5'd6};//'d11; //10+(2>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_2_r = {3'd1, 5'd5}; //'d7; //6+(2>>1) luma
end
'd3: begin
ctx_idx_last_x_prefix_2_r = {3'd1, 5'd4};//'d4; //3+(2>>1) luma
end
default: begin
ctx_idx_last_x_prefix_2_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_2_r = {3'd0, 5'd6};//'d15; //15+0+(2>>2) chroma
end
'd2: begin
ctx_idx_last_x_prefix_2_r = {3'd1, 5'd8};//'d16; //15+0+(2>>1) chroma
end
'd3: begin
ctx_idx_last_x_prefix_2_r = {3'd2, 5'd4};//'d17; //15+0+(2>>0) chroma
end
default: begin
ctx_idx_last_x_prefix_2_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_3_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_3_r = {3'd1, 5'd6};//'d11; //10+(3>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_3_r = {3'd1, 5'd5};//'d7; //6+(3>>1) luma
end
'd3: begin
ctx_idx_last_x_prefix_3_r = {3'd1, 5'd4};//'d4; //3+(3>>1) luma
end
default: begin
ctx_idx_last_x_prefix_3_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_3_r = {3'd0, 5'd6};//'d15; //15+0+(3>>2) chroma
end
'd2: begin
ctx_idx_last_x_prefix_3_r = {3'd1, 5'd8};//'d16; //15+0+(3>>1) chroma
end
'd3: begin
ctx_idx_last_x_prefix_3_r = {3'd3, 5'd9};//'d18; //15+0+(3>>0) chroma
end
default: begin
ctx_idx_last_x_prefix_3_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_4_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_4_r = {3'd3, 5'd8};//'d12; //10+(4>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_4_r = {3'd2, 5'd3};//'d8; //6+(4>>1) luma
end
'd3: begin
ctx_idx_last_x_prefix_4_r = {3'd3, 5'd6};//'d5; //3+(4>>1) luma
end
default: begin
ctx_idx_last_x_prefix_4_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_4_r = {3'd1, 5'd8};//'d1; //0+(4>>2) chroma
end
'd2: begin
ctx_idx_last_x_prefix_4_r = {3'd2, 5'd4};//'d2; //0+(4>>1) chroma
end
default: begin
ctx_idx_last_x_prefix_4_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_5_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_5_r = {3'd3, 5'd8};//'d12; //10+(5>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_5_r = {3'd2, 5'd3};//'d8; //6+(5>>1) luma
end
'd3: begin
ctx_idx_last_x_prefix_5_r = {3'd1, 5'd7};//'d5; //3+(5>>1) luma
end
default: begin
ctx_idx_last_x_prefix_5_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_5_r = {3'd1, 5'd8};//'d1; //0+(5>>2) chroma
end
'd2: begin
ctx_idx_last_x_prefix_5_r = {3'd2, 5'd4};//'d2; //0+(5>>1) chroma
end
default: begin
ctx_idx_last_x_prefix_5_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_6_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_6_r = {3'd0, 5'd5};//'d13; //10+(6>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_6_r = {3'd3, 5'd7};//'d9; //6+(6>>1) luma
end
default: begin
ctx_idx_last_x_prefix_6_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_6_r = {3'd1, 5'd8};//'d1; //15+0+(6>>2) chroma
end
default: begin
ctx_idx_last_x_prefix_6_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_7_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_7_r = {3'd0, 5'd5};//'d13; //10+(7>>1) luma
end
'd2: begin
ctx_idx_last_x_prefix_7_r = {3'd3, 5'd7};//'d9; //6+(7>>1) luma
end
default: begin
ctx_idx_last_x_prefix_7_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_7_r = {3'd0, 5'd6};//'d1; //0+(7>>2) chroma
end
default: begin
ctx_idx_last_x_prefix_7_r = 'd0;
end
endcase
end
end
// ctx_idx_last_x_prefix_8_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_x_prefix_8_r = {3'd1, 5'd7};//'d14; //10+(8>>1) luma
end
default: begin
ctx_idx_last_x_prefix_8_r = 'd0;
end
endcase
end
else begin
ctx_idx_last_x_prefix_8_r = 'd0;
end
end
// ctx_idx_last_x_prefix_9_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF)
ctx_idx_last_x_prefix_9_r = {3'd1, 5'd7};//'d14; //10+(9>>1) luma ;
else
ctx_idx_last_x_prefix_9_r = 'd0;
end
//ctx_idx_last_y_prefix_0_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_0_r = {3'd0, 5'd10};//'d10; //10+(0>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_0_r = {3'd0, 5'd9};//'d6; //6+(0>>1) luma
end
'd3: begin
ctx_idx_last_y_prefix_0_r = {3'd0, 5'd8};//'d3; //3+(0>>1) luma
end
default: begin
ctx_idx_last_y_prefix_0_r = 'd0;
end
endcase
end
else begin
ctx_idx_last_y_prefix_0_r = {3'd0, 5'd12};//'d0; //0+(0>>1) chroma
end
end
// ctx_idx_last_y_prefix_1_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_1_r = {3'd0, 5'd10};//'d10; //10+(1>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_1_r = {3'd0, 5'd9};//'d6; //6+(1>>1) luma
end
'd3: begin
ctx_idx_last_y_prefix_1_r = {3'd0, 5'd8};//'d3; //3+(1>>1) luma
end
default: begin
ctx_idx_last_y_prefix_1_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1, 'd2: begin
ctx_idx_last_y_prefix_1_r = {3'd0, 5'd12};//'d0; //0+(1>>1) chroma
end
'd3: begin
ctx_idx_last_y_prefix_1_r = {3'd1, 5'd14};//'d1; //0+(1>>0) chroma
end
default: begin
ctx_idx_last_y_prefix_1_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_2_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_2_r = {3'd1, 5'd12};//'d11; //10+(2>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_2_r = {3'd1, 5'd11};//'d7; //6+(2>>1) luma
end
'd3: begin
ctx_idx_last_y_prefix_2_r = {3'd1, 5'd10};//'d4; //3+(2>>1) luma
end
default: begin
ctx_idx_last_y_prefix_2_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_2_r = {3'd0, 5'd12};//'d0; //0+(2>>2) chroma
end
'd2: begin
ctx_idx_last_y_prefix_2_r = {3'd1, 5'd14};//'d1; //0+(2>>1) chroma
end
'd3: begin
ctx_idx_last_y_prefix_2_r = {3'd2, 5'd6};//'d2; //0+(2>>0) chroma
end
default: begin
ctx_idx_last_y_prefix_2_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_3_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_3_r = {3'd1, 5'd12};//'d11; //10+(3>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_3_r = {3'd1, 5'd11};//'d7; //6+(3>>1) luma
end
'd3: begin
ctx_idx_last_y_prefix_3_r = {3'd1, 5'd10};//'d4; //3+(3>>1) luma
end
default: begin
ctx_idx_last_y_prefix_3_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_3_r = {3'd0, 5'd12};//'d0; //0+(3>>2) chroma
end
'd2: begin
ctx_idx_last_y_prefix_3_r = {3'd1, 5'd14};//'d1; //0+(3>>1) chroma
end
'd3: begin
ctx_idx_last_y_prefix_3_r = {3'd3, 5'd14};//'d3; //0+(3>>0) chroma
end
default: begin
ctx_idx_last_y_prefix_3_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_4_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_4_r = {3'd3, 5'd13};//'d12; //10+(4>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_4_r = {3'd2, 5'd5};//'d8; //6+(4>>1) luma
end
'd3: begin
ctx_idx_last_y_prefix_4_r = {3'd3, 5'd11};//'d5; //3+(4>>1) luma
end
default: begin
ctx_idx_last_y_prefix_4_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_4_r = {3'd1, 5'd14};//'d1; //0+(4>>2) chroma
end
'd2: begin
ctx_idx_last_y_prefix_4_r = {3'd2, 5'd6};//'d2; //0+(4>>1) chroma
end
default: begin
ctx_idx_last_y_prefix_4_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_5_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_5_r = {3'd3, 5'd13};//'d12; //10+(5>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_5_r = {3'd2, 5'd5};//'d8; //6+(5>>1) luma
end
'd3: begin
ctx_idx_last_y_prefix_5_r = {3'd3, 5'd11};//'d5; //3+(5>>1) luma
end
default: begin
ctx_idx_last_y_prefix_5_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_5_r = {3'd1, 5'd14};//'d1; //0+(5>>2) chroma
end
'd2: begin
ctx_idx_last_y_prefix_5_r = {3'd2, 5'd6};//'d2; //0+(5>>1) chroma
end
default: begin
ctx_idx_last_y_prefix_5_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_6_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_6_r = {3'd0, 5'd11};//'d13; //10+(6>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_6_r = {3'd3, 5'd12};//'d9; //6+(6>>1) luma
end
default: begin
ctx_idx_last_y_prefix_6_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_6_r = {3'd1, 5'd14};//'d1; //0+(6>>2) chroma
end
default: begin
ctx_idx_last_y_prefix_6_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_7_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_7_r = {3'd0, 5'd11};//'d13; //10+(7>>1) luma
end
'd2: begin
ctx_idx_last_y_prefix_7_r = {3'd3, 5'd12};//'d9; //6+(7>>1) luma
end
default: begin
ctx_idx_last_y_prefix_7_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_7_r = {3'd1, 5'd14};//'d1; //0+(7>>2) chroma
end
default: begin
ctx_idx_last_y_prefix_7_r = 'd0;
end
endcase
end
end
// ctx_idx_last_y_prefix_8_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_idx_last_y_prefix_8_r = {3'd1, 5'd13};//'d14; //10+(8>>1) luma
end
default: begin
ctx_idx_last_y_prefix_8_r = 'd0;
end
endcase
end
else begin
ctx_idx_last_y_prefix_8_r = 'd0;
end
end
// ctx_idx_last_y_prefix_9_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF)
ctx_idx_last_y_prefix_9_r = {3'd1, 5'd13};//'d14; //10+(9>>1) luma
else
ctx_idx_last_y_prefix_9_r = 'd0;
end
//pos_x_w
assign pos_x_w = (scan_idx_r!=(`SCAN_VER)) ? (pos_x_base_r + pos_x_inc_r) : (pos_y_base_r + pos_y_inc_r);
//pos_y_w
assign pos_y_w = (scan_idx_r!=(`SCAN_VER)) ? (pos_y_base_r + pos_y_inc_r) : (pos_x_base_r + pos_x_inc_r);
//pos_x_mar_r
always @* begin
case(group_idx_x_r)
'd0: pos_x_mar_r = pos_x_w - 'd0;
'd1: pos_x_mar_r = pos_x_w - 'd1;
'd2: pos_x_mar_r = pos_x_w - 'd2;
'd3: pos_x_mar_r = pos_x_w - 'd3;
'd4: pos_x_mar_r = pos_x_w - 'd4;
'd5: pos_x_mar_r = pos_x_w - 'd6;
'd6: pos_x_mar_r = pos_x_w - 'd8;
'd7: pos_x_mar_r = pos_x_w - 'd12;
'd8: pos_x_mar_r = pos_x_w - 'd16;
'd9: pos_x_mar_r = pos_x_w - 'd24;
default:pos_x_mar_r = 'd0;
endcase
end
//pos_x_mar_r
always @* begin
case(group_idx_y_r)
'd0: pos_y_mar_r = pos_y_w - 'd0;
'd1: pos_y_mar_r = pos_y_w - 'd1;
'd2: pos_y_mar_r = pos_y_w - 'd2;
'd3: pos_y_mar_r = pos_y_w - 'd3;
'd4: pos_y_mar_r = pos_y_w - 'd4;
'd5: pos_y_mar_r = pos_y_w - 'd6;
'd6: pos_y_mar_r = pos_y_w - 'd8;
'd7: pos_y_mar_r = pos_y_w - 'd12;
'd8: pos_y_mar_r = pos_y_w - 'd16;
'd9: pos_y_mar_r = pos_y_w - 'd24;
default:pos_y_mar_r = 'd0;
endcase
end
//group_idx_x_r
always @* begin
case(pos_x_w)
0: group_idx_x_r = 'd0;
1: group_idx_x_r = 'd1;
2: group_idx_x_r = 'd2;
3: group_idx_x_r = 'd3;
4, 5:
group_idx_x_r = 'd4;
6, 7:
group_idx_x_r = 'd5;
8, 9, 10, 11:
group_idx_x_r = 'd6;
12, 13, 14, 15:
group_idx_x_r = 'd7;
16, 17, 18, 19, 20, 21, 22, 23:
group_idx_x_r = 'd8;
default:
group_idx_x_r = 'd9;
endcase
end
//group_idx_y_r
always @* begin
case(pos_y_w)
0: group_idx_y_r = 'd0;
1: group_idx_y_r = 'd1;
2: group_idx_y_r = 'd2;
3: group_idx_y_r = 'd3;
4, 5:
group_idx_y_r = 'd4;
6, 7:
group_idx_y_r = 'd5;
8, 9, 10, 11:
group_idx_y_r = 'd6;
12, 13, 14, 15:
group_idx_y_r = 'd7;
16, 17, 18, 19, 20, 21, 22, 23:
group_idx_y_r = 'd8;
default:
group_idx_y_r = 'd9;
endcase
end
//group_idx_x_1_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
0, 1: begin
if(pos_x_w<'d24)
group_idx_x_1_r = 'd1;
else
group_idx_x_1_r = 'd0;
end
2: begin
if(pos_x_w<'d12)
group_idx_x_1_r = 'd1;
else
group_idx_x_1_r = 'd0;
end
3: begin
if(pos_x_w<'d6)
group_idx_x_1_r = 'd1;
else
group_idx_x_1_r = 'd0;
end
default:begin
group_idx_x_1_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
0, 1: begin
if(pos_x_w<'d12)
group_idx_x_1_r = 'd1;
else
group_idx_x_1_r = 'd0;
end
2: begin
if(pos_x_w<'d6)
group_idx_x_1_r = 'd1;
else
group_idx_x_1_r = 'd0;
end
3: begin
if(pos_x_w<'d3)
group_idx_x_1_r = 'd1;
else
group_idx_x_1_r = 'd0;
end
default:begin
group_idx_x_1_r = 'd0;
end
endcase
end
end
//group_idx_y_1_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
0, 1: begin
if(pos_y_w<'d24)
group_idx_y_1_r = 'd1;
else
group_idx_y_1_r = 'd0;
end
2: begin
if(pos_y_w<'d12)
group_idx_y_1_r = 'd1;
else
group_idx_y_1_r = 'd0;
end
3: begin
if(pos_y_w<'d6)
group_idx_y_1_r = 'd1;
else
group_idx_y_1_r = 'd0;
end
default:begin
group_idx_y_1_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
0, 1: begin
if(pos_y_w<'d12)
group_idx_y_1_r = 'd1;
else
group_idx_y_1_r = 'd0;
end
2: begin
if(pos_y_w<'d6)
group_idx_y_1_r = 'd1;
else
group_idx_y_1_r = 'd0;
end
3: begin
if(pos_y_w<'d3)
group_idx_y_1_r = 'd1;
else
group_idx_y_1_r = 'd0;
end
default:begin
group_idx_y_1_r = 'd0;
end
endcase
end
end
//pos_x_base_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
pos_x_base_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0) begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
0, 1: begin
case(last_blk_idx_r)
0, 1, 3, 6, 10, 15, 21, 28: begin
pos_x_base_r <= 'd0;
end
2, 4, 7, 11, 16, 22, 29, 36: begin
pos_x_base_r <= 'd4;
end
5, 8, 12, 17, 23, 30, 37, 43: begin
pos_x_base_r <= 'd8;
end
9, 13, 18, 24, 31, 38, 44, 49: begin
pos_x_base_r <= 'd12;
end
14, 19, 25, 32, 39, 45, 50, 54: begin
pos_x_base_r <= 'd16;
end
20, 26, 33, 40, 46, 51, 55, 58: begin
pos_x_base_r <= 'd20;
end
27, 34, 41, 47, 52, 56, 59, 61: begin
pos_x_base_r <= 'd24;
end
default: begin
pos_x_base_r <= 'd28;
end
endcase
end
2: begin
case(last_blk_idx_r)
0, 1, 3, 6: begin
pos_x_base_r <= 'd0;
end
2, 4, 7, 10: begin
pos_x_base_r <= 'd4;
end
5, 8, 11, 13: begin
pos_x_base_r <= 'd8;
end
default: begin
pos_x_base_r <= 'd12;
end
endcase
end
3: begin
if(scan_idx_r!=(`SCAN_HOR)) begin
if(~last_blk_idx_r[1])
pos_x_base_r <= 'd0;
else
pos_x_base_r <= 'd4;
end
else begin
if(~last_blk_idx_r[0])
pos_x_base_r <= 'd0;
else
pos_x_base_r <= 'd4;
end
end
default:begin
pos_x_base_r <= 'd0;
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF || res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
0, 1: begin
case(last_blk_idx_r)
0, 1, 3, 6: begin
pos_x_base_r <= 'd0;
end
2, 4, 7, 10: begin
pos_x_base_r <= 'd4;
end
5, 8, 11, 13: begin
pos_x_base_r <= 'd8;
end
default: begin
pos_x_base_r <= 'd12;
end
endcase
end
2: begin
if(~last_blk_idx_r[1])
pos_x_base_r <= 'd0;
else
pos_x_base_r <= 'd4;
end
3: begin
pos_x_base_r <= 'd0;
end
default:begin
pos_x_base_r <= 'd0;
end
endcase
end
else begin
pos_x_base_r <= 'd0;
end
end
else begin
pos_x_base_r <= pos_x_base_r;
end
end
//pos_y_base_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
pos_y_base_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0) begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
0, 1: begin
case(last_blk_idx_r)
0, 2, 5, 9, 14, 20, 27, 35: begin
pos_y_base_r <= 'd0;
end
1, 4, 8, 13, 19, 26, 34, 42: begin
pos_y_base_r <= 'd4;
end
3, 7, 12, 18, 25, 33, 41, 48: begin
pos_y_base_r <= 'd8;
end
6, 11, 17, 24, 32, 40, 47, 53: begin
pos_y_base_r <= 'd12;
end
10, 16, 23, 31, 39, 46, 52, 57: begin
pos_y_base_r <= 'd16;
end
15, 22, 30, 38, 45, 51, 56, 60: begin
pos_y_base_r <= 'd20;
end
21, 29, 37, 44, 50, 55, 59, 62: begin
pos_y_base_r <= 'd24;
end
default: begin
pos_y_base_r <= 'd28;
end
endcase
end
2: begin
case(last_blk_idx_r)
0, 2, 5, 9: begin
pos_y_base_r <= 'd0;
end
1, 4, 8, 12: begin
pos_y_base_r <= 'd4;
end
3, 7, 11, 14: begin
pos_y_base_r <= 'd8;
end
default: begin
pos_y_base_r <= 'd12;
end
endcase
end
3: begin
if(scan_idx_r!=(`SCAN_HOR)) begin
if(~last_blk_idx_r[0])
pos_y_base_r <= 'd0;
else
pos_y_base_r <= 'd4;
end
else begin
if(~last_blk_idx_r[1])
pos_y_base_r <= 'd0;
else
pos_y_base_r <= 'd4;
end
end
default:begin
pos_y_base_r <= 'd0;
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF || res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
0, 1: begin
case(last_blk_idx_r)
0, 2, 5, 9: begin
pos_y_base_r <= 'd0;
end
1, 4, 8, 12: begin
pos_y_base_r <= 'd4;
end
3, 7, 11, 14: begin
pos_y_base_r <= 'd8;
end
default: begin
pos_y_base_r <= 'd12;
end
endcase
end
2: begin
if(~last_blk_idx_r[0])
pos_y_base_r <= 'd0;
else
pos_y_base_r <= 'd4;
end
3: begin
pos_y_base_r <= 'd0;
end
default:begin
pos_y_base_r <= 'd0;
end
endcase
end
else begin
pos_y_base_r <= 'd0;
end
end
else begin
pos_y_base_r <= pos_y_base_r;
end
end
//last_blk_res_r
assign last_blk_res_r = tu_curr_state_r==TU_LAST_SIG_0 ? last_blk_data_w : scan_res_data_r;
//pos_x_inc_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
pos_x_inc_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0) begin
case(scan_idx_r)
(`SCAN_DIAG): begin
if(last_blk_res_r[127:0]=='d0) begin
if(last_blk_res_r[191:128]=='d0) begin
if(last_blk_res_r[223:192]=='d0) begin
if(last_blk_res_r[239:224]=='d0) begin
pos_x_inc_r <= 'd0; //0
end
else begin //1
pos_x_inc_r <= 'd0;
end
end
else begin
if(last_blk_res_r[207:192]=='d0) begin
pos_x_inc_r <= 'd1; //2
end
else begin
pos_x_inc_r <= 'd0; //3
end
end
end
else begin
if(last_blk_res_r[159:128]=='d0) begin
if(last_blk_res_r[175:160]=='d0) begin
pos_x_inc_r <= 'd1; //4
end
else begin
pos_x_inc_r <= 'd2; //5
end
end
else begin
if(last_blk_res_r[143:128]=='d0) begin
pos_x_inc_r <= 'd0; //6
end
else begin
pos_x_inc_r <= 'd1; //7
end
end
end
end
else begin
if(last_blk_res_r[63:0]=='d0) begin
if(last_blk_res_r[95:64]=='d0) begin
if(last_blk_res_r[111:96]=='d0) begin
pos_x_inc_r <= 'd2; //8
end
else begin
pos_x_inc_r <= 'd3; //9
end
end
else begin
if(last_blk_res_r[79:64]=='d0) begin
pos_x_inc_r <= 'd1; //10
end
else begin
pos_x_inc_r <= 'd2; //11
end
end
end
else begin
if(last_blk_res_r[31:0]=='d0) begin
if(last_blk_res_r[47:32]=='d0) begin
pos_x_inc_r <= 'd3; //12
end
else begin
pos_x_inc_r <= 'd2; //13
end
end
else begin
if(last_blk_res_r[15:0]=='d0) begin
pos_x_inc_r <= 'd3; //14
end
else begin
pos_x_inc_r <= 'd3; //15
end
end
end
end
end
(`SCAN_VER): begin
if(last_blk_res_r[127:0]=='d0) begin
if(last_blk_res_r[191:128]=='d0) begin
pos_x_inc_r <= 'd0; //0-3
end
else begin
pos_x_inc_r <= 'd1; //4-7
end
end
else begin
if(last_blk_res_r[63:0]=='d0) begin
pos_x_inc_r <= 'd2; //8-11
end
else begin
pos_x_inc_r <= 'd3; //12-15
end
end
end
(`SCAN_HOR): begin
if(last_blk_res_r[127:0]=='d0) begin
if(last_blk_res_r[191:128]=='d0) begin
if(last_blk_res_r[223:192]=='d0) begin
if(last_blk_res_r[239:224]=='d0) begin
pos_x_inc_r <= 'd0; //0
end
else begin //1
pos_x_inc_r <= 'd1;
end
end
else begin
if(last_blk_res_r[207:192]=='d0) begin
pos_x_inc_r <= 'd2; //2
end
else begin
pos_x_inc_r <= 'd3; //3
end
end
end
else begin
if(last_blk_res_r[159:128]=='d0) begin
if(last_blk_res_r[175:160]=='d0) begin
pos_x_inc_r <= 'd0; //4
end
else begin
pos_x_inc_r <= 'd1; //5
end
end
else begin
if(last_blk_res_r[143:128]=='d0) begin
pos_x_inc_r <= 'd2; //6
end
else begin
pos_x_inc_r <= 'd3; //7
end
end
end
end
else begin
if(last_blk_res_r[63:0]=='d0) begin
if(last_blk_res_r[95:64]=='d0) begin
if(last_blk_res_r[111:96]=='d0) begin
pos_x_inc_r <= 'd0; //8
end
else begin
pos_x_inc_r <= 'd1; //9
end
end
else begin
if(last_blk_res_r[79:64]=='d0) begin
pos_x_inc_r <= 'd2; //10
end
else begin
pos_x_inc_r <= 'd3; //11
end
end
end
else begin
if(last_blk_res_r[31:0]=='d0) begin
if(last_blk_res_r[47:32]=='d0) begin
pos_x_inc_r <= 'd0; //12
end
else begin
pos_x_inc_r <= 'd1; //13
end
end
else begin
if(last_blk_res_r[15:0]=='d0) begin
pos_x_inc_r <= 'd2; //14
end
else begin
pos_x_inc_r <= 'd3; //15
end
end
end
end
end
default: begin
pos_x_inc_r <= 'd0;
end
endcase
end
else
pos_x_inc_r <= pos_x_inc_r;
end
//pos_y_inc_r
//pos_y_inc_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
pos_y_inc_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG_0) begin
case(scan_idx_r)
(`SCAN_DIAG): begin
if(last_blk_res_r[127:0]=='d0) begin
if(last_blk_res_r[191:128]=='d0) begin
if(last_blk_res_r[223:192]=='d0) begin
if(last_blk_res_r[239:224]=='d0) begin
pos_y_inc_r <= 'd0; //0
end
else begin //1
pos_y_inc_r <= 'd1;
end
end
else begin
if(last_blk_res_r[207:192]=='d0) begin
pos_y_inc_r <= 'd0; //2
end
else begin
pos_y_inc_r <= 'd2; //3
end
end
end
else begin
if(last_blk_res_r[159:128]=='d0) begin
if(last_blk_res_r[175:160]=='d0) begin
pos_y_inc_r <= 'd1; //4
end
else begin
pos_y_inc_r <= 'd0; //5
end
end
else begin
if(last_blk_res_r[143:128]=='d0) begin
pos_y_inc_r <= 'd3; //6
end
else begin
pos_y_inc_r <= 'd2; //7
end
end
end
end
else begin
if(last_blk_res_r[63:0]=='d0) begin
if(last_blk_res_r[95:64]=='d0) begin
if(last_blk_res_r[111:96]=='d0) begin
pos_y_inc_r <= 'd1; //8
end
else begin
pos_y_inc_r <= 'd0; //9
end
end
else begin
if(last_blk_res_r[79:64]=='d0) begin
pos_y_inc_r <= 'd3; //10
end
else begin
pos_y_inc_r <= 'd2; //11
end
end
end
else begin
if(last_blk_res_r[31:0]=='d0) begin
if(last_blk_res_r[47:32]=='d0) begin
pos_y_inc_r <= 'd1; //12
end
else begin
pos_y_inc_r <= 'd3; //13
end
end
else begin
if(last_blk_res_r[15:0]=='d0) begin
pos_y_inc_r <= 'd2; //14
end
else begin
pos_y_inc_r <= 'd3; //15
end
end
end
end
end
(`SCAN_VER): begin
if(last_blk_res_r[127:0]=='d0) begin
if(last_blk_res_r[191:128]=='d0) begin
if(last_blk_res_r[223:192]=='d0) begin
if(last_blk_res_r[239:224]=='d0) begin
pos_y_inc_r <= 'd0; //0
end
else begin //1
pos_y_inc_r <= 'd1;
end
end
else begin
if(last_blk_res_r[207:192]=='d0) begin
pos_y_inc_r <= 'd2; //2
end
else begin
pos_y_inc_r <= 'd3; //3
end
end
end
else begin
if(last_blk_res_r[159:128]=='d0) begin
if(last_blk_res_r[175:160]=='d0) begin
pos_y_inc_r <= 'd0; //4
end
else begin
pos_y_inc_r <= 'd1; //5
end
end
else begin
if(last_blk_res_r[143:128]=='d0) begin
pos_y_inc_r <= 'd2; //6
end
else begin
pos_y_inc_r <= 'd3; //7
end
end
end
end
else begin
if(last_blk_res_r[63:0]=='d0) begin
if(last_blk_res_r[95:64]=='d0) begin
if(last_blk_res_r[111:96]=='d0) begin
pos_y_inc_r <= 'd0; //8
end
else begin
pos_y_inc_r <= 'd1; //9
end
end
else begin
if(last_blk_res_r[79:64]=='d0) begin
pos_y_inc_r <= 'd2; //10
end
else begin
pos_y_inc_r <= 'd3; //11
end
end
end
else begin
if(last_blk_res_r[31:0]=='d0) begin
if(last_blk_res_r[47:32]=='d0) begin
pos_y_inc_r <= 'd0; //12
end
else begin
pos_y_inc_r <= 'd1; //13
end
end
else begin
if(last_blk_res_r[15:0]=='d0) begin
pos_y_inc_r <= 'd2; //14
end
else begin
pos_y_inc_r <= 'd3; //15
end
end
end
end
end
(`SCAN_HOR): begin
if(last_blk_res_r[127:0]=='d0) begin
if(last_blk_res_r[191:128]=='d0) begin
pos_y_inc_r <= 'd0; //0-3
end
else begin
pos_y_inc_r <= 'd1; //4-7
end
end
else begin
if(last_blk_res_r[63:0]=='d0) begin
pos_y_inc_r <= 'd2; //8-11
end
else begin
pos_y_inc_r <= 'd3; //12-15
end
end
end
default: begin
pos_y_inc_r <= 'd0;
end
endcase
end
else
pos_y_inc_r <= pos_y_inc_r;
end
// *********************************************************
// sub_blk_sig_flag
assign ctx_pair_sub_blk_sig_w = {2'b00, bin_string_sub_blk_sig_r, ctx_idx_sub_blk_sig_r};
assign bin_string_sub_blk_sig_r = enc_bin_cbf_r;
always @* begin
if(enc_blk_cnt_r>'d0 && enc_blk_cnt_r<blk_tot_r)
valid_num_bin_sub_blk_sig_r = 'd1;
else
valid_num_bin_sub_blk_sig_r = 'd0;
end
//ctx_idx_sub_blk_sig_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
if(ctx_sub_blk_sig_r[0])
ctx_idx_sub_blk_sig_r = {3'd1, 5'd15};//1
else
ctx_idx_sub_blk_sig_r = {3'd0, 5'd13};//0
end
else begin
if(ctx_sub_blk_sig_r[0])
ctx_idx_sub_blk_sig_r = {3'd3, 5'd15};//3
else
ctx_idx_sub_blk_sig_r = {3'd2, 5'd7};//2
end
end
//ctx_sub_blk_sig_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_luma32x32_ler_w[blk_cbf_idx_r] | tu_cbf_z2s_luma32x32_rer_w[blk_cbf_idx_r];
end
'd2: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_luma16x16_ler_w[blk_cbf_idx_r] | tu_cbf_z2s_luma16x16_rer_w[blk_cbf_idx_r];
end
'd3: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_luma8x8_ler_r[blk_cbf_idx_r] | tu_cbf_z2s_luma8x8_rer_r[blk_cbf_idx_r];
end
default: begin
ctx_sub_blk_sig_r = 'd0;
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CR_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_cr16x16_ler_w[blk_cbf_idx_r] | tu_cbf_z2s_cr16x16_rer_w[blk_cbf_idx_r];
end
'd2: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_cr8x8_ler_w[blk_cbf_idx_r] | tu_cbf_z2s_cr8x8_rer_w[blk_cbf_idx_r];
end
'd3: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_cr4x4_ler_w | tu_cbf_z2s_cr4x4_rer_w;
end
default: begin
end
endcase
end
else if(res_curr_state_r==RESIDUAL_CB_COEFF) begin
case(cu_depth_i)
'd0, 'd1: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_cb16x16_ler_w[blk_cbf_idx_r] | tu_cbf_z2s_cb16x16_rer_w[blk_cbf_idx_r];
end
'd2: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_cb8x8_ler_w[blk_cbf_idx_r] | tu_cbf_z2s_cb8x8_rer_w[blk_cbf_idx_r];
end
'd3: begin
ctx_sub_blk_sig_r = tu_cbf_z2s_cb4x4_ler_w | tu_cbf_z2s_cb4x4_rer_w;
end
default: begin
end
endcase
end
else begin
ctx_sub_blk_sig_r = 'd0;
end
end
// **********************************************************
// sig_flag
//ctx_pair_sig_flag_0_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_0_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_0_r = 'd0;
'd1: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_15_w;
'd2: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_14_w;
'd3: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_13_w;
'd4: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_12_w;
'd5: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_11_w;
'd6: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_10_w;
'd7: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_9_w;
'd8: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_8_w;
'd9: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_7_w;
'd10: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_6_w;
'd11: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_5_w;
'd12: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_4_w;
'd13: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_3_w;
'd14: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_2_w;
'd15: ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_1_w;
default:ctx_pair_sig_flag_0_r = ctx_pair_sig_flag_1_w;
endcase
end
end
//ctx_pair_sig_flag_1_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_1_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_1_r = 'd0;
'd1: ctx_pair_sig_flag_1_r = 'd0;
'd2: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_15_w;
'd3: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_14_w;
'd4: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_13_w;
'd5: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_12_w;
'd6: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_11_w;
'd7: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_10_w;
'd8: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_9_w;
'd9: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_8_w;
'd10: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_7_w;
'd11: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_6_w;
'd12: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_5_w;
'd13: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_4_w;
'd14: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_3_w;
'd15: ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_2_w;
default:ctx_pair_sig_flag_1_r = ctx_pair_sig_flag_2_w;
endcase
end
end
//ctx_pair_sig_flag_2_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_2_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_2_r = 'd0;
'd1: ctx_pair_sig_flag_2_r = 'd0;
'd2: ctx_pair_sig_flag_2_r = 'd0;
'd3: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_15_w;
'd4: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_14_w;
'd5: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_13_w;
'd6: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_12_w;
'd7: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_11_w;
'd8: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_10_w;
'd9: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_9_w;
'd10: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_8_w;
'd11: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_7_w;
'd12: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_6_w;
'd13: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_5_w;
'd14: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_4_w;
'd15: ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_3_w;
default:ctx_pair_sig_flag_2_r = ctx_pair_sig_flag_3_w;
endcase
end
end
//ctx_pair_sig_flag_3_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_3_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_3_r = 'd0;
'd1: ctx_pair_sig_flag_3_r = 'd0;
'd2: ctx_pair_sig_flag_3_r = 'd0;
'd3: ctx_pair_sig_flag_3_r = 'd0;
'd4: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_15_w;
'd5: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_14_w;
'd6: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_13_w;
'd7: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_12_w;
'd8: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_11_w;
'd9: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_10_w;
'd10: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_9_w;
'd11: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_8_w;
'd12: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_7_w;
'd13: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_6_w;
'd14: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_5_w;
'd15: ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_4_w;
default:ctx_pair_sig_flag_3_r = ctx_pair_sig_flag_4_w;
endcase
end
end
//ctx_pair_sig_flag_4_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_4_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_4_r = 'd0;
'd1: ctx_pair_sig_flag_4_r = 'd0;
'd2: ctx_pair_sig_flag_4_r = 'd0;
'd3: ctx_pair_sig_flag_4_r = 'd0;
'd4: ctx_pair_sig_flag_4_r = 'd0;
'd5: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_15_w;
'd6: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_14_w;
'd7: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_13_w;
'd8: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_12_w;
'd9: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_11_w;
'd10: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_10_w;
'd11: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_9_w;
'd12: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_8_w;
'd13: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_7_w;
'd14: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_6_w;
'd15: ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_5_w;
default:ctx_pair_sig_flag_4_r = ctx_pair_sig_flag_5_w;
endcase
end
end
//ctx_pair_sig_flag_5_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_5_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_5_r = 'd0;
'd1: ctx_pair_sig_flag_5_r = 'd0;
'd2: ctx_pair_sig_flag_5_r = 'd0;
'd3: ctx_pair_sig_flag_5_r = 'd0;
'd4: ctx_pair_sig_flag_5_r = 'd0;
'd5: ctx_pair_sig_flag_5_r = 'd0;
'd6: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_15_w;
'd7: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_14_w;
'd8: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_13_w;
'd9: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_12_w;
'd10: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_11_w;
'd11: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_10_w;
'd12: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_9_w;
'd13: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_8_w;
'd14: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_7_w;
'd15: ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_6_w;
default:ctx_pair_sig_flag_5_r = ctx_pair_sig_flag_6_w;
endcase
end
end
//ctx_pair_sig_flag_6_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_6_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_6_r = 'd0;
'd1: ctx_pair_sig_flag_6_r = 'd0;
'd2: ctx_pair_sig_flag_6_r = 'd0;
'd3: ctx_pair_sig_flag_6_r = 'd0;
'd4: ctx_pair_sig_flag_6_r = 'd0;
'd5: ctx_pair_sig_flag_6_r = 'd0;
'd6: ctx_pair_sig_flag_6_r = 'd0;
'd7: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_15_w;
'd8: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_14_w;
'd9: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_13_w;
'd10: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_12_w;
'd11: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_11_w;
'd12: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_10_w;
'd13: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_9_w;
'd14: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_8_w;
'd15: ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_7_w;
default:ctx_pair_sig_flag_6_r = ctx_pair_sig_flag_7_w;
endcase
end
end
//ctx_pair_sig_flag_7_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_7_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_7_r = 'd0;
'd1: ctx_pair_sig_flag_7_r = 'd0;
'd2: ctx_pair_sig_flag_7_r = 'd0;
'd3: ctx_pair_sig_flag_7_r = 'd0;
'd4: ctx_pair_sig_flag_7_r = 'd0;
'd5: ctx_pair_sig_flag_7_r = 'd0;
'd6: ctx_pair_sig_flag_7_r = 'd0;
'd7: ctx_pair_sig_flag_7_r = 'd0;
'd8: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_15_w;
'd9: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_14_w;
'd10: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_13_w;
'd11: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_12_w;
'd12: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_11_w;
'd13: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_10_w;
'd14: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_9_w;
'd15: ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_8_w;
default:ctx_pair_sig_flag_7_r = ctx_pair_sig_flag_8_w;
endcase
end
end
//ctx_pair_sig_flag_8_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_8_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_8_r = 'd0;
'd1: ctx_pair_sig_flag_8_r = 'd0;
'd2: ctx_pair_sig_flag_8_r = 'd0;
'd3: ctx_pair_sig_flag_8_r = 'd0;
'd4: ctx_pair_sig_flag_8_r = 'd0;
'd5: ctx_pair_sig_flag_8_r = 'd0;
'd6: ctx_pair_sig_flag_8_r = 'd0;
'd7: ctx_pair_sig_flag_8_r = 'd0;
'd8: ctx_pair_sig_flag_8_r = 'd0;
'd9: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_15_w;
'd10: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_14_w;
'd11: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_13_w;
'd12: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_12_w;
'd13: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_11_w;
'd14: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_10_w;
'd15: ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_9_w;
default:ctx_pair_sig_flag_8_r = ctx_pair_sig_flag_9_w;
endcase
end
end
//ctx_pair_sig_flag_9_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_9_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_9_r = 'd0;
'd1: ctx_pair_sig_flag_9_r = 'd0;
'd2: ctx_pair_sig_flag_9_r = 'd0;
'd3: ctx_pair_sig_flag_9_r = 'd0;
'd4: ctx_pair_sig_flag_9_r = 'd0;
'd5: ctx_pair_sig_flag_9_r = 'd0;
'd6: ctx_pair_sig_flag_9_r = 'd0;
'd7: ctx_pair_sig_flag_9_r = 'd0;
'd8: ctx_pair_sig_flag_9_r = 'd0;
'd9: ctx_pair_sig_flag_9_r = 'd0;
'd10: ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_15_w;
'd11: ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_14_w;
'd12: ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_13_w;
'd13: ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_12_w;
'd14: ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_11_w;
'd15: ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_10_w;
default:ctx_pair_sig_flag_9_r = ctx_pair_sig_flag_10_w;
endcase
end
end
//ctx_pair_sig_flag_10_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_10_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_10_r = 'd0;
'd1: ctx_pair_sig_flag_10_r = 'd0;
'd2: ctx_pair_sig_flag_10_r = 'd0;
'd3: ctx_pair_sig_flag_10_r = 'd0;
'd4: ctx_pair_sig_flag_10_r = 'd0;
'd5: ctx_pair_sig_flag_10_r = 'd0;
'd6: ctx_pair_sig_flag_10_r = 'd0;
'd7: ctx_pair_sig_flag_10_r = 'd0;
'd8: ctx_pair_sig_flag_10_r = 'd0;
'd9: ctx_pair_sig_flag_10_r = 'd0;
'd10: ctx_pair_sig_flag_10_r = 'd0;
'd11: ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_15_w;
'd12: ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_14_w;
'd13: ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_13_w;
'd14: ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_12_w;
'd15: ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_11_w;
default:ctx_pair_sig_flag_10_r = ctx_pair_sig_flag_11_w;
endcase
end
end
//ctx_pair_sig_flag_11_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_11_r = ctx_pair_sig_flag_11_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_11_r = 'd0;
'd1: ctx_pair_sig_flag_11_r = 'd0;
'd2: ctx_pair_sig_flag_11_r = 'd0;
'd3: ctx_pair_sig_flag_11_r = 'd0;
'd4: ctx_pair_sig_flag_11_r = 'd0;
'd5: ctx_pair_sig_flag_11_r = 'd0;
'd6: ctx_pair_sig_flag_11_r = 'd0;
'd7: ctx_pair_sig_flag_11_r = 'd0;
'd8: ctx_pair_sig_flag_11_r = 'd0;
'd9: ctx_pair_sig_flag_11_r = 'd0;
'd10: ctx_pair_sig_flag_11_r = 'd0;
'd11: ctx_pair_sig_flag_11_r = 'd0;
'd12: ctx_pair_sig_flag_11_r = ctx_pair_sig_flag_15_w;
'd13: ctx_pair_sig_flag_11_r = ctx_pair_sig_flag_14_w;
'd14: ctx_pair_sig_flag_11_r = ctx_pair_sig_flag_13_w;
'd15: ctx_pair_sig_flag_11_r = ctx_pair_sig_flag_12_w;
default:ctx_pair_sig_flag_11_r = ctx_pair_sig_flag_12_w;
endcase
end
end
//ctx_pair_sig_flag_12_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_12_r = ctx_pair_sig_flag_12_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_12_r = 'd0;
'd1: ctx_pair_sig_flag_12_r = 'd0;
'd2: ctx_pair_sig_flag_12_r = 'd0;
'd3: ctx_pair_sig_flag_12_r = 'd0;
'd4: ctx_pair_sig_flag_12_r = 'd0;
'd5: ctx_pair_sig_flag_12_r = 'd0;
'd6: ctx_pair_sig_flag_12_r = 'd0;
'd7: ctx_pair_sig_flag_12_r = 'd0;
'd8: ctx_pair_sig_flag_12_r = 'd0;
'd9: ctx_pair_sig_flag_12_r = 'd0;
'd10: ctx_pair_sig_flag_12_r = 'd0;
'd11: ctx_pair_sig_flag_12_r = 'd0;
'd12: ctx_pair_sig_flag_12_r = 'd0;
'd13: ctx_pair_sig_flag_12_r = ctx_pair_sig_flag_15_w;
'd14: ctx_pair_sig_flag_12_r = ctx_pair_sig_flag_14_w;
'd15: ctx_pair_sig_flag_12_r = ctx_pair_sig_flag_13_w;
default:ctx_pair_sig_flag_12_r = ctx_pair_sig_flag_13_w;
endcase
end
end
//ctx_pair_sig_flag_13_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_13_r = ctx_pair_sig_flag_13_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_13_r = 'd0;
'd1: ctx_pair_sig_flag_13_r = 'd0;
'd2: ctx_pair_sig_flag_13_r = 'd0;
'd3: ctx_pair_sig_flag_13_r = 'd0;
'd4: ctx_pair_sig_flag_13_r = 'd0;
'd5: ctx_pair_sig_flag_13_r = 'd0;
'd6: ctx_pair_sig_flag_13_r = 'd0;
'd7: ctx_pair_sig_flag_13_r = 'd0;
'd8: ctx_pair_sig_flag_13_r = 'd0;
'd9: ctx_pair_sig_flag_13_r = 'd0;
'd10: ctx_pair_sig_flag_13_r = 'd0;
'd11: ctx_pair_sig_flag_13_r = 'd0;
'd12: ctx_pair_sig_flag_13_r = 'd0;
'd13: ctx_pair_sig_flag_13_r = 'd0;
'd14: ctx_pair_sig_flag_13_r = ctx_pair_sig_flag_15_w;
'd15: ctx_pair_sig_flag_13_r = ctx_pair_sig_flag_14_w;
default:ctx_pair_sig_flag_13_r = ctx_pair_sig_flag_14_w;
endcase
end
end
//ctx_pair_sig_flag_14_r
always @* begin
if(enc_blk_cnt_r!='d0 && blk_tot_r!='d0)
ctx_pair_sig_flag_14_r = ctx_pair_sig_flag_14_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_14_r = 'd0;
'd1: ctx_pair_sig_flag_14_r = 'd0;
'd2: ctx_pair_sig_flag_14_r = 'd0;
'd3: ctx_pair_sig_flag_14_r = 'd0;
'd4: ctx_pair_sig_flag_14_r = 'd0;
'd5: ctx_pair_sig_flag_14_r = 'd0;
'd6: ctx_pair_sig_flag_14_r = 'd0;
'd7: ctx_pair_sig_flag_14_r = 'd0;
'd8: ctx_pair_sig_flag_14_r = 'd0;
'd9: ctx_pair_sig_flag_14_r = 'd0;
'd10: ctx_pair_sig_flag_14_r = 'd0;
'd11: ctx_pair_sig_flag_14_r = 'd0;
'd12: ctx_pair_sig_flag_14_r = 'd0;
'd13: ctx_pair_sig_flag_14_r = 'd0;
'd14: ctx_pair_sig_flag_14_r = 'd0;
'd15: ctx_pair_sig_flag_14_r = ctx_pair_sig_flag_15_w;
default:ctx_pair_sig_flag_14_r = ctx_pair_sig_flag_15_w;
endcase
end
end
//ctx_pair_sig_flag_15_r
always @* begin
if(enc_blk_cnt_r!='d0)
ctx_pair_sig_flag_15_r = ctx_pair_sig_flag_15_w;
else begin
case(enc_last_coeff_idx_r)
'd0: ctx_pair_sig_flag_15_r = 'd0;
'd1: ctx_pair_sig_flag_15_r = 'd0;
'd2: ctx_pair_sig_flag_15_r = 'd0;
'd3: ctx_pair_sig_flag_15_r = 'd0;
'd4: ctx_pair_sig_flag_15_r = 'd0;
'd5: ctx_pair_sig_flag_15_r = 'd0;
'd6: ctx_pair_sig_flag_15_r = 'd0;
'd7: ctx_pair_sig_flag_15_r = 'd0;
'd8: ctx_pair_sig_flag_15_r = 'd0;
'd9: ctx_pair_sig_flag_15_r = 'd0;
'd10: ctx_pair_sig_flag_15_r = 'd0;
'd11: ctx_pair_sig_flag_15_r = 'd0;
'd12: ctx_pair_sig_flag_15_r = 'd0;
'd13: ctx_pair_sig_flag_15_r = 'd0;
'd14: ctx_pair_sig_flag_15_r = 'd0;
'd15: ctx_pair_sig_flag_15_r = 'd0;
default:ctx_pair_sig_flag_15_r = ctx_pair_sig_flag_15_w;
endcase
end
end
assign ctx_pair_sig_flag_0_w = {2'b00, bin_string_sig_flag_r[15], ctx_idx_sig_flag_0_r };
assign ctx_pair_sig_flag_1_w = {2'b00, bin_string_sig_flag_r[14], ctx_idx_sig_flag_1_r };
assign ctx_pair_sig_flag_2_w = {2'b00, bin_string_sig_flag_r[13], ctx_idx_sig_flag_2_r };
assign ctx_pair_sig_flag_3_w = {2'b00, bin_string_sig_flag_r[12], ctx_idx_sig_flag_3_r };
assign ctx_pair_sig_flag_4_w = {2'b00, bin_string_sig_flag_r[11], ctx_idx_sig_flag_4_r };
assign ctx_pair_sig_flag_5_w = {2'b00, bin_string_sig_flag_r[10], ctx_idx_sig_flag_5_r };
assign ctx_pair_sig_flag_6_w = {2'b00, bin_string_sig_flag_r[ 9], ctx_idx_sig_flag_6_r };
assign ctx_pair_sig_flag_7_w = {2'b00, bin_string_sig_flag_r[ 8], ctx_idx_sig_flag_7_r };
assign ctx_pair_sig_flag_8_w = {2'b00, bin_string_sig_flag_r[ 7], ctx_idx_sig_flag_8_r };
assign ctx_pair_sig_flag_9_w = {2'b00, bin_string_sig_flag_r[ 6], ctx_idx_sig_flag_9_r };
assign ctx_pair_sig_flag_10_w = {2'b00, bin_string_sig_flag_r[ 5], ctx_idx_sig_flag_10_r};
assign ctx_pair_sig_flag_11_w = {2'b00, bin_string_sig_flag_r[ 4], ctx_idx_sig_flag_11_r};
assign ctx_pair_sig_flag_12_w = {2'b00, bin_string_sig_flag_r[ 3], ctx_idx_sig_flag_12_r};
assign ctx_pair_sig_flag_13_w = {2'b00, bin_string_sig_flag_r[ 2], ctx_idx_sig_flag_13_r};
assign ctx_pair_sig_flag_14_w = {2'b00, bin_string_sig_flag_r[ 1], ctx_idx_sig_flag_14_r};
assign ctx_pair_sig_flag_15_w = {2'b00, bin_string_sig_flag_r[ 0], ctx_idx_sig_flag_15_r};
//enc_sig_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_sig_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r!=TU_SIG_FLAG)
enc_sig_cyc_cnt_r <= 'd0;
else if(enc_sig_cyc_cnt_r==enc_sig_cyc_tot_r)
enc_sig_cyc_cnt_r <= 'd0;
else
enc_sig_cyc_cnt_r <= enc_sig_cyc_cnt_r + 'd1;
end
//enc_sig_cyc_tot_r
always @* begin
case(valid_num_bin_sig_flag_r)
'd0, 'd1, 'd2, 'd3, 'd4: enc_sig_cyc_tot_r = 'd0;
'd5, 'd6, 'd7, 'd8: enc_sig_cyc_tot_r = 'd1;
'd9, 'd10, 'd11, 'd12: enc_sig_cyc_tot_r = 'd2;
'd13, 'd14, 'd15, 'd16: enc_sig_cyc_tot_r = 'd3;
default: enc_sig_cyc_tot_r = 'd0;
endcase
end
//valid_num_bin_sig_flag_r
always @* begin
if(enc_blk_cnt_r=='d0) begin
//if(enc_last_coeff_idx_r=='d0)
// valid_num_bin_sig_flag_r = 'd0;
//else
valid_num_bin_sig_flag_r = enc_last_coeff_idx_r;
end
else if(enc_blk_cnt_r<blk_tot_r) begin
if(enc_last_coeff_idx_r=='d0)
valid_num_bin_sig_flag_r = 'd15;
else
valid_num_bin_sig_flag_r = 'd16;
end
else begin
valid_num_bin_sig_flag_r = 'd16;
end
end
//bin_string_sig_flag_r
always @* begin
if(enc_blk_cnt_r=='d0)
bin_string_sig_flag_r = enc_coeff_sig_r;// << (5'd16-enc_last_coeff_idx_r);
else
bin_string_sig_flag_r = enc_coeff_sig_r;
end
//ctx_idx_sig_flag
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(cu_depth_i)
'd0, 'd1, 'd2: begin
if(enc_blk_cnt_r<blk_tot_r) begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_14_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_13_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_12_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_11_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_10_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_9_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_8_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_7_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_6_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_5_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_4_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_3_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_2_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_1_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_0_r = {3'd0, 5'd21};//'d24;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_14_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_13_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_12_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_11_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_10_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_9_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_8_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_7_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_6_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_5_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_4_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_3_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_2_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_1_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_0_r = {3'd0, 5'd21};//'d24;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_14_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_13_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_12_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_11_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_10_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_9_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_8_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_7_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_6_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_5_r = {3'd4, 5'd6 };//'d25;
ctx_idx_sig_flag_4_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_3_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_2_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_1_r = {3'd0, 5'd21};//'d24;
ctx_idx_sig_flag_0_r = {3'd0, 5'd21};//'d24;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_14_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_13_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_12_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_11_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_10_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_9_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_8_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_7_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_6_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_5_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_4_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_3_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_2_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_1_r = {3'd2, 5'd15};//'d26;
ctx_idx_sig_flag_0_r = {3'd2, 5'd15};//'d26;
end
endcase
end
else begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_13_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_12_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_11_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_10_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_9_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_8_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_7_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_6_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_5_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_4_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_3_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_2_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_1_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_0_r = {3'd0, 5'd20};//'d21;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31 };//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_13_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_12_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_11_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_10_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_9_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_8_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_7_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_6_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_5_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_4_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_3_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_2_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_1_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_0_r = {3'd0, 5'd20};//'d21;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31 };//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_13_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_12_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_11_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_10_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_9_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_8_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_7_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_6_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_5_r = {3'd4, 5'd5 };//'d22;
ctx_idx_sig_flag_4_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_3_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_2_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_1_r = {3'd0, 5'd20};//'d21;
ctx_idx_sig_flag_0_r = {3'd0, 5'd20};//'d21;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_13_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_12_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_11_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_10_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_9_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_8_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_7_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_6_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_5_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_4_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_3_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_2_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_1_r = {3'd2, 5'd14};//'d23;
ctx_idx_sig_flag_0_r = {3'd2, 5'd14};//'d23;
end
endcase
end
end
'd3: begin
case(scan_idx_r)
(`SCAN_DIAG): begin
if(enc_blk_cnt_r<blk_tot_r) begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_14_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_13_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_12_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_11_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_10_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_9_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_8_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_7_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_6_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_5_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_4_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_3_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_2_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_1_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_0_r = {3'd0, 5'd17};//'d12;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_14_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_13_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_12_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_11_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_10_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_9_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_8_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_7_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_6_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_5_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_4_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_3_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_2_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_1_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_0_r = {3'd0, 5'd17};//'d12;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_14_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_13_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_12_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_11_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_10_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_9_r = {3'd2, 5'd11};//'d14;
ctx_idx_sig_flag_8_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_7_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_6_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_5_r = {3'd4, 5'd2 };//'d13;
ctx_idx_sig_flag_4_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_3_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_2_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_1_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_0_r = {3'd0, 5'd17};//'d12;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_14_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_13_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_12_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_11_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_10_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_9_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_8_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_7_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_6_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_5_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_4_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_3_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_2_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_1_r = {3'd0, 5'd17};//'d12;
ctx_idx_sig_flag_0_r = {3'd0, 5'd17};//'d12;
end
endcase
end
else begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_13_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_12_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_11_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_10_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_9_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_8_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_7_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_6_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_5_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_4_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_3_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_2_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_1_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_0_r = {3'd0, 5'd16};//'d9;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_13_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_12_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_11_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_10_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_9_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_8_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_7_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_6_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_5_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_4_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_3_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_2_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_1_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_0_r = {3'd0, 5'd16};//'d9;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_13_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_12_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_11_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_10_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_9_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_8_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_7_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_6_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_5_r = {3'd4, 5'd1 };//'d10;
ctx_idx_sig_flag_4_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_3_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_2_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_1_r = {3'd0, 5'd16};//'d9;
ctx_idx_sig_flag_0_r = {3'd0, 5'd16};//'d9;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_13_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_12_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_11_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_10_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_9_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_8_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_7_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_6_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_5_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_4_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_3_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_2_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_1_r = {3'd2, 5'd10};//'d11;
ctx_idx_sig_flag_0_r = {3'd2, 5'd10};//'d11;
end
endcase
end
end
(`SCAN_HOR): begin
if(enc_blk_cnt_r<blk_tot_r) begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_13_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_12_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_11_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_10_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_9_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_8_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_7_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_6_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_5_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_4_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_3_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_2_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_1_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_0_r = {3'd0, 5'd19};//'d18;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_13_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_12_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_11_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_10_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_9_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_8_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_7_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_6_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_5_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_4_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_3_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_2_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_1_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_0_r = {3'd0, 5'd19};//'d18;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_13_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_12_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_11_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_10_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_9_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_8_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_7_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_6_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_5_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_4_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_3_r = {3'd2, 5'd13};//'d19;
ctx_idx_sig_flag_2_r = {3'd4, 5'd4 };//'d20;
ctx_idx_sig_flag_1_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_0_r = {3'd0, 5'd19};//'d18;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_13_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_12_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_11_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_10_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_9_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_8_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_7_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_6_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_5_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_4_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_3_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_2_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_1_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_0_r = {3'd2, 5'd13};//'d20;
end
endcase
end
else begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31 };//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_13_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_12_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_11_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_10_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_9_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_8_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_7_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_6_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_5_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_4_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_3_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_2_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_1_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_0_r = {3'd0, 5'd18};//'d15;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_13_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_12_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_11_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_10_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_9_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_8_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_7_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_6_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_5_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_4_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_3_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_2_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_1_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_0_r = {3'd0, 5'd18};//'d15;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_13_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_12_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_11_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_10_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_9_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_8_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_7_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_6_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_5_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_4_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_3_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_2_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_1_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_0_r = {3'd0, 5'd18};//'d15;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_13_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_12_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_11_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_10_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_9_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_8_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_7_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_6_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_5_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_4_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_3_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_2_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_1_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_0_r = {3'd2, 5'd12};//'d17;
end
endcase
end
end
(`SCAN_VER): begin
if(enc_blk_cnt_r<blk_tot_r) begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_13_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_12_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_11_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_10_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_9_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_8_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_7_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_6_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_5_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_4_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_3_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_2_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_1_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_0_r = {3'd0, 5'd19};//'d18;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_13_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_12_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_11_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_10_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_9_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_8_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_7_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_6_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_5_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_4_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_3_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_2_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_1_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_0_r = {3'd0, 5'd19};//'d18;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_13_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_12_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_11_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_10_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_9_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_8_r = {3'd4, 5'd4 };//'d19;
ctx_idx_sig_flag_7_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_6_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_5_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_4_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_3_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_2_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_1_r = {3'd0, 5'd19};//'d18;
ctx_idx_sig_flag_0_r = {3'd0, 5'd19};//'d18;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_14_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_13_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_12_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_11_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_10_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_9_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_8_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_7_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_6_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_5_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_4_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_3_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_2_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_1_r = {3'd2, 5'd13};//'d20;
ctx_idx_sig_flag_0_r = {3'd2, 5'd13};//'d20;
end
endcase
end
else begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_13_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_12_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_11_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_10_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_9_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_8_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_7_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_6_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_5_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_4_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_3_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_2_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_1_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_0_r = {3'd0, 5'd18};//'d15;
end
'd1: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_13_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_12_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_11_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_10_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_9_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_8_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_7_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_6_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_5_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_4_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_3_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_2_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_1_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_0_r = {3'd0, 5'd18};//'d15;
end
'd2: begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_13_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_12_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_11_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_10_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_9_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_8_r = {3'd4, 5'd3 };//'d16;
ctx_idx_sig_flag_7_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_6_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_5_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_4_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_3_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_2_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_1_r = {3'd0, 5'd18};//'d15;
ctx_idx_sig_flag_0_r = {3'd0, 5'd18};//'d15;
end
default:begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd31};//'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_13_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_12_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_11_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_10_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_9_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_8_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_7_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_6_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_5_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_4_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_3_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_2_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_1_r = {3'd2, 5'd12};//'d17;
ctx_idx_sig_flag_0_r = {3'd2, 5'd12};//'d17;
end
endcase
end
end
default: begin
ctx_idx_sig_flag_15_r = 'd0;
ctx_idx_sig_flag_14_r = 'd0;
ctx_idx_sig_flag_13_r = 'd0;
ctx_idx_sig_flag_12_r = 'd0;
ctx_idx_sig_flag_11_r = 'd0;
ctx_idx_sig_flag_10_r = 'd0;
ctx_idx_sig_flag_9_r = 'd0;
ctx_idx_sig_flag_8_r = 'd0;
ctx_idx_sig_flag_7_r = 'd0;
ctx_idx_sig_flag_6_r = 'd0;
ctx_idx_sig_flag_5_r = 'd0;
ctx_idx_sig_flag_4_r = 'd0;
ctx_idx_sig_flag_3_r = 'd0;
ctx_idx_sig_flag_2_r = 'd0;
ctx_idx_sig_flag_1_r = 'd0;
ctx_idx_sig_flag_0_r = 'd0;
end
endcase
end
default:begin
ctx_idx_sig_flag_15_r = 'd0;
ctx_idx_sig_flag_14_r = 'd0;
ctx_idx_sig_flag_13_r = 'd0;
ctx_idx_sig_flag_12_r = 'd0;
ctx_idx_sig_flag_11_r = 'd0;
ctx_idx_sig_flag_10_r = 'd0;
ctx_idx_sig_flag_9_r = 'd0;
ctx_idx_sig_flag_8_r = 'd0;
ctx_idx_sig_flag_7_r = 'd0;
ctx_idx_sig_flag_6_r = 'd0;
ctx_idx_sig_flag_5_r = 'd0;
ctx_idx_sig_flag_4_r = 'd0;
ctx_idx_sig_flag_3_r = 'd0;
ctx_idx_sig_flag_2_r = 'd0;
ctx_idx_sig_flag_1_r = 'd0;
ctx_idx_sig_flag_0_r = 'd0;
end
endcase
end
else begin
case(cu_depth_i)
'd0, 'd1: begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd20};//'d27 : 'd41;
ctx_idx_sig_flag_14_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_13_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_12_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_11_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_10_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_9_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_8_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_7_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_6_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_5_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_4_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_3_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_2_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_1_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_0_r = {3'd4, 5'd11};//'d39; //'d12;
end
'd1: begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd20};//'d27 : 'd41;
ctx_idx_sig_flag_14_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_13_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_12_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_11_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_10_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_9_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_8_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_7_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_6_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_5_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_4_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_3_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_2_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_1_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_0_r = {3'd4, 5'd11};//'d39; //'d12;
end
'd2: begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd20};//'d27 : 'd41;
ctx_idx_sig_flag_14_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_13_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_12_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_11_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_10_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_9_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_8_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_7_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_6_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_5_r = {3'd1, 5'd20};//'d40; //'d13;
ctx_idx_sig_flag_4_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_3_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_2_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_1_r = {3'd4, 5'd11};//'d39; //'d12;
ctx_idx_sig_flag_0_r = {3'd4, 5'd11};//'d39; //'d12;
end
default:begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd20};//'d27 : 'd41;
ctx_idx_sig_flag_14_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_13_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_12_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_11_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_10_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_9_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_8_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_7_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_6_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_5_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_4_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_3_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_2_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_1_r = {3'd2, 5'd20};//'d41; //'d14;
ctx_idx_sig_flag_0_r = {3'd2, 5'd20};//'d41; //'d14;
end
endcase
end
'd2: begin
case(enc_pattern_sig_ctx_r)
'd0: begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd19};//'d27 : 'd38;
ctx_idx_sig_flag_14_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_13_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_12_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_11_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_10_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_9_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_8_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_7_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_6_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_5_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_4_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_3_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_2_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_1_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_0_r = {3'd4, 5'd10};//'d36; //'d9;
end
'd1: begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd19};//'d27 : 'd38;
ctx_idx_sig_flag_14_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_13_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_12_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_11_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_10_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_9_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_8_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_7_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_6_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_5_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_4_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_3_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_2_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_1_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_0_r = {3'd4, 5'd10};//'d36; //'d9;
end
'd2: begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd19};//'d27 : 'd38;
ctx_idx_sig_flag_14_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_13_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_12_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_11_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_10_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_9_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_8_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_7_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_6_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_5_r = {3'd1, 5'd19};//'d37; //'d10;
ctx_idx_sig_flag_4_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_3_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_2_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_1_r = {3'd4, 5'd10};//'d36; //'d9;
ctx_idx_sig_flag_0_r = {3'd4, 5'd10};//'d36; //'d9;
end
default:begin
ctx_idx_sig_flag_15_r = enc_blk_cnt_r==blk_tot_r ? {3'd3, 5'd16} : {3'd2, 5'd19};//'d27 : 'd38;
ctx_idx_sig_flag_14_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_13_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_12_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_11_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_10_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_9_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_8_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_7_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_6_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_5_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_4_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_3_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_2_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_1_r = {3'd2, 5'd19};//'d38; //'d11;
ctx_idx_sig_flag_0_r = {3'd2, 5'd19};//'d38; //'d11;
end
endcase
end
'd3: begin
case(scan_idx_r)
(`SCAN_DIAG): begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd16};//27 //'d0;
ctx_idx_sig_flag_14_r = {3'd0, 5'd14};//29 //'d2;
ctx_idx_sig_flag_13_r = {3'd2, 5'd8 };//28 //'d1;
ctx_idx_sig_flag_12_r = {3'd5, 5'd0 };//33 //'d6;
ctx_idx_sig_flag_11_r = {3'd3, 5'd30};//30 //'d3;
ctx_idx_sig_flag_10_r = {3'd1, 5'd16};//31 //'d4;
ctx_idx_sig_flag_9_r = {3'd5, 5'd1 };//34 //'d7;
ctx_idx_sig_flag_8_r = {3'd5, 5'd0 };//33 //'d6;
ctx_idx_sig_flag_7_r = {3'd1, 5'd16};//31 //'d4;
ctx_idx_sig_flag_6_r = {3'd4, 5'd0 };//32 //'d5;
ctx_idx_sig_flag_5_r = {3'd5, 5'd1 };//34 //'d7;
ctx_idx_sig_flag_4_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_3_r = {3'd4, 5'd0 };//32 //'d5;
ctx_idx_sig_flag_2_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_1_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_0_r = {3'd2, 5'd9 };//35 //'d8;
end
(`SCAN_HOR): begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd16};//27 //'d0;
ctx_idx_sig_flag_14_r = {3'd2, 5'd8 };//28 //'d1;
ctx_idx_sig_flag_13_r = {3'd1, 5'd16};//31 //'d4;
ctx_idx_sig_flag_12_r = {3'd4, 5'd0 };//32 //'d5;
ctx_idx_sig_flag_11_r = {3'd0, 5'd14};//29 //'d2;
ctx_idx_sig_flag_10_r = {3'd3, 5'd30};//30 //'d3;
ctx_idx_sig_flag_9_r = {3'd1, 5'd16};//31 //'d4;
ctx_idx_sig_flag_8_r = {3'd4, 5'd0 };//32 //'d5;
ctx_idx_sig_flag_7_r = {3'd5, 5'd0 };//33 //'d6;
ctx_idx_sig_flag_6_r = {3'd5, 5'd0 };//33 //'d6;
ctx_idx_sig_flag_5_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_4_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_3_r = {3'd5, 5'd1 };//34 //'d7;
ctx_idx_sig_flag_2_r = {3'd5, 5'd1 };//34 //'d7;
ctx_idx_sig_flag_1_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_0_r = {3'd2, 5'd9 };//35 //'d8;
end
(`SCAN_VER): begin
ctx_idx_sig_flag_15_r = {3'd3, 5'd16};//27 //'d0;
ctx_idx_sig_flag_14_r = {3'd0, 5'd14};//29 //'d2;
ctx_idx_sig_flag_13_r = {3'd5, 5'd0 };//33 //'d6;
ctx_idx_sig_flag_12_r = {3'd5, 5'd1 };//34 //'d7;
ctx_idx_sig_flag_11_r = {3'd2, 5'd8 };//28 //'d1;
ctx_idx_sig_flag_10_r = {3'd3, 5'd30};//30 //'d3;
ctx_idx_sig_flag_9_r = {3'd5, 5'd0 };//33 //'d6;
ctx_idx_sig_flag_8_r = {3'd5, 5'd1 };//34 //'d7;
ctx_idx_sig_flag_7_r = {3'd1, 5'd16};//31 //'d4;
ctx_idx_sig_flag_6_r = {3'd1, 5'd16};//31 //'d4;
ctx_idx_sig_flag_5_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_4_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_3_r = {3'd4, 5'd0 };//32 //'d5;
ctx_idx_sig_flag_2_r = {3'd4, 5'd0 };//32 //'d5;
ctx_idx_sig_flag_1_r = {3'd2, 5'd9 };//35 //'d8;
ctx_idx_sig_flag_0_r = {3'd2, 5'd9 };//35 //'d8;
end
default: begin
ctx_idx_sig_flag_15_r = 'd0;
ctx_idx_sig_flag_14_r = 'd0;
ctx_idx_sig_flag_13_r = 'd0;
ctx_idx_sig_flag_12_r = 'd0;
ctx_idx_sig_flag_11_r = 'd0;
ctx_idx_sig_flag_10_r = 'd0;
ctx_idx_sig_flag_9_r = 'd0;
ctx_idx_sig_flag_8_r = 'd0;
ctx_idx_sig_flag_7_r = 'd0;
ctx_idx_sig_flag_6_r = 'd0;
ctx_idx_sig_flag_5_r = 'd0;
ctx_idx_sig_flag_4_r = 'd0;
ctx_idx_sig_flag_3_r = 'd0;
ctx_idx_sig_flag_2_r = 'd0;
ctx_idx_sig_flag_1_r = 'd0;
ctx_idx_sig_flag_0_r = 'd0;
end
endcase
end
default:begin
ctx_idx_sig_flag_15_r = 'd0;
ctx_idx_sig_flag_14_r = 'd0;
ctx_idx_sig_flag_13_r = 'd0;
ctx_idx_sig_flag_12_r = 'd0;
ctx_idx_sig_flag_11_r = 'd0;
ctx_idx_sig_flag_10_r = 'd0;
ctx_idx_sig_flag_9_r = 'd0;
ctx_idx_sig_flag_8_r = 'd0;
ctx_idx_sig_flag_7_r = 'd0;
ctx_idx_sig_flag_6_r = 'd0;
ctx_idx_sig_flag_5_r = 'd0;
ctx_idx_sig_flag_4_r = 'd0;
ctx_idx_sig_flag_3_r = 'd0;
ctx_idx_sig_flag_2_r = 'd0;
ctx_idx_sig_flag_1_r = 'd0;
ctx_idx_sig_flag_0_r = 'd0;
end
endcase
end
end
// **********************************************************
// ge12
wire [3:0] num_c1_flag_w ;
assign num_c1_flag_w = enc_coeff_tot_r>=8 ? 8 : enc_coeff_tot_r;
assign valid_num_bin_ge12_r = num_c1_flag_w + coeff_ge1_r;
assign ctx_pair_ge12_0_w = {2'b00, bin_string_ge12_r[8], ctx_idx_ge12_0_r};
assign ctx_pair_ge12_1_w = {2'b00, bin_string_ge12_r[7], ctx_idx_ge12_1_r};
assign ctx_pair_ge12_2_w = {2'b00, bin_string_ge12_r[6], ctx_idx_ge12_2_r};
assign ctx_pair_ge12_3_w = {2'b00, bin_string_ge12_r[5], ctx_idx_ge12_3_r};
assign ctx_pair_ge12_4_w = {2'b00, bin_string_ge12_r[4], ctx_idx_ge12_4_r};
assign ctx_pair_ge12_5_w = {2'b00, bin_string_ge12_r[3], ctx_idx_ge12_5_r};
assign ctx_pair_ge12_6_w = {2'b00, bin_string_ge12_r[2], ctx_idx_ge12_6_r};
assign ctx_pair_ge12_7_w = {2'b00, bin_string_ge12_r[1], ctx_idx_ge12_7_r};
assign ctx_pair_ge12_8_w = {2'b00, bin_string_ge12_r[0], ctx_idx_ge12_8_r};
//coeff_ge1_r
always @* begin
case(num_c1_flag_w)
'd1: coeff_ge1_r = enc_non_zero_abs_0_ge1_r;
'd2: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r;
'd3: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r | enc_non_zero_abs_2_ge1_r;
'd4: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r | enc_non_zero_abs_2_ge1_r | enc_non_zero_abs_3_ge1_r;
'd5: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r | enc_non_zero_abs_2_ge1_r | enc_non_zero_abs_3_ge1_r
| enc_non_zero_abs_4_ge1_r;
'd6: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r | enc_non_zero_abs_2_ge1_r | enc_non_zero_abs_3_ge1_r
| enc_non_zero_abs_4_ge1_r | enc_non_zero_abs_5_ge1_r;
'd7: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r | enc_non_zero_abs_2_ge1_r | enc_non_zero_abs_3_ge1_r
| enc_non_zero_abs_4_ge1_r | enc_non_zero_abs_5_ge1_r | enc_non_zero_abs_6_ge1_r;
'd8: coeff_ge1_r = enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r | enc_non_zero_abs_2_ge1_r | enc_non_zero_abs_3_ge1_r
| enc_non_zero_abs_4_ge1_r | enc_non_zero_abs_5_ge1_r | enc_non_zero_abs_6_ge1_r | enc_non_zero_abs_7_ge1_r;
default:coeff_ge1_r = 'd0;
endcase
end
//coeff_ge2_r
always @* begin
if(enc_non_zero_abs_0_ge1_r)
coeff_ge2_r = enc_non_zero_abs_0_ge2_r;
else if(enc_non_zero_abs_1_ge1_r)
coeff_ge2_r = enc_non_zero_abs_1_ge2_r;
else if(enc_non_zero_abs_2_ge1_r)
coeff_ge2_r = enc_non_zero_abs_2_ge2_r;
else if(enc_non_zero_abs_3_ge1_r)
coeff_ge2_r = enc_non_zero_abs_3_ge2_r;
else if(enc_non_zero_abs_4_ge1_r)
coeff_ge2_r = enc_non_zero_abs_4_ge2_r;
else if(enc_non_zero_abs_5_ge1_r)
coeff_ge2_r = enc_non_zero_abs_5_ge2_r;
else if(enc_non_zero_abs_6_ge1_r)
coeff_ge2_r = enc_non_zero_abs_6_ge2_r;
else if(enc_non_zero_abs_7_ge1_r)
coeff_ge2_r = enc_non_zero_abs_7_ge2_r;
else coeff_ge2_r = 'd0;
end
//enc_ge12_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_ge12_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r!=TU_GE12)
enc_ge12_cyc_cnt_r <= 'd0;
else if(enc_ge12_cyc_cnt_r==enc_ge12_cyc_tot_r)
enc_ge12_cyc_cnt_r <= 'd0;
else
enc_ge12_cyc_cnt_r <= enc_ge12_cyc_cnt_r + 'd1;
end
//enc_ge12_cyc_tot_r
always @* begin
case(valid_num_bin_ge12_r)
'd0, 'd1, 'd2, 'd3, 'd4: enc_ge12_cyc_tot_r = 'd0;
'd5, 'd6, 'd7, 'd8: enc_ge12_cyc_tot_r = 'd1;
'd9: enc_ge12_cyc_tot_r = 'd2;
default: enc_ge12_cyc_tot_r = 'd0;
endcase
end
always @* begin
case(num_c1_flag_w)
'd1: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, coeff_ge2_r, 7'd0};
'd2: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, coeff_ge2_r, 6'd0};
'd3: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, enc_non_zero_abs_2_ge1_r, coeff_ge2_r, 5'd0};
'd4: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, enc_non_zero_abs_2_ge1_r,
enc_non_zero_abs_3_ge1_r, coeff_ge2_r, 4'd0};
'd5: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, enc_non_zero_abs_2_ge1_r,
enc_non_zero_abs_3_ge1_r, enc_non_zero_abs_4_ge1_r, coeff_ge2_r, 3'd0};
'd6: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, enc_non_zero_abs_2_ge1_r,
enc_non_zero_abs_3_ge1_r, enc_non_zero_abs_4_ge1_r, enc_non_zero_abs_5_ge1_r, coeff_ge2_r, 2'd0};
'd7: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, enc_non_zero_abs_2_ge1_r,
enc_non_zero_abs_3_ge1_r, enc_non_zero_abs_4_ge1_r, enc_non_zero_abs_5_ge1_r,
enc_non_zero_abs_6_ge1_r, coeff_ge2_r, 1'd0};
'd8: bin_string_ge12_r = {enc_non_zero_abs_0_ge1_r, enc_non_zero_abs_1_ge1_r, enc_non_zero_abs_2_ge1_r,
enc_non_zero_abs_3_ge1_r, enc_non_zero_abs_4_ge1_r, enc_non_zero_abs_5_ge1_r,
enc_non_zero_abs_6_ge1_r, enc_non_zero_abs_7_ge1_r, coeff_ge2_r};
default:bin_string_ge12_r = 'd0;
endcase
end
//c1_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
c1_r <= 'd0;
else if(tu_curr_state_r==TU_LAST_SIG)
c1_r <= 'd1;
else if(blk_e_done_r) begin
if(enc_bin_cbf_r=='d0)
c1_r <= c1_r;
else if(coeff_ge1_r)
c1_r <= 'd0;
else
c1_r <= 'd1;
end
else
c1_r <= c1_r;
end
//i_ctx_set_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF && enc_blk_cnt_r!=blk_tot_r) begin
if(c1_r=='d0)
i_ctx_set_r = 'd3;
else
i_ctx_set_r = 'd2;
end
else begin
if(c1_r=='d0)
i_ctx_set_r = 'd1;
else
i_ctx_set_r = 'd0;
end
end
reg [7:0] ctx_idx_ge12_00_w ;
always @* begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_00_w = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd0, 5'd23} : {3'd0, 5'd27};//'d0 : 'd16;
'd1: ctx_idx_ge12_00_w = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd0, 5'd24} : {3'd0, 5'd28};//'d4 : 'd20;
'd2: ctx_idx_ge12_00_w = {3'd0, 5'd25};//'d8;
'd3: ctx_idx_ge12_00_w = {3'd0, 5'd26};//'d12;
default:ctx_idx_ge12_00_w = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd0, 5'd23} : {3'd0, 5'd27};//'d0 : 'd16;
endcase
end
//ctx_idx_ge12_0_r
always @* begin
if(res_curr_state_r==RESIDUAL_LUMA_COEFF) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_0_r = {3'd1, 5'd21};//'d1;
'd1: ctx_idx_ge12_0_r = {3'd1, 5'd22};//'d5;
'd2: ctx_idx_ge12_0_r = {3'd1, 5'd23};//'d9;
'd3: ctx_idx_ge12_0_r = {3'd1, 5'd24};//'d13;
default:ctx_idx_ge12_0_r = {3'd1, 5'd21};//'d1;
endcase
end
else begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_0_r = {3'd1, 5'd25};//'d17;
'd1: ctx_idx_ge12_0_r = {3'd1, 5'd26};//'d21;
default:ctx_idx_ge12_0_r = {3'd1, 5'd25};//'d17;
endcase
end
end
//ctx_idx_ge12_1_r
always @* begin
if(num_c1_flag_w=='d1) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_1_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 'd4
'd1: ctx_idx_ge12_1_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 'd5
'd2: ctx_idx_ge12_1_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_1_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_1_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_1_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
if(~enc_non_zero_abs_0_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_1_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd2, 5'd21} : {3'd2, 5'd25};//'d2 : 'd18;
'd1: ctx_idx_ge12_1_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd2, 5'd22} : {3'd2, 5'd26};//'d6 : 'd22;
'd2: ctx_idx_ge12_1_r = {3'd2, 5'd23};//'d10;
'd3: ctx_idx_ge12_1_r = {3'd2, 5'd24};//'d14;
default:ctx_idx_ge12_1_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd2, 5'd21} : {3'd2, 5'd25};//'d2 : 'd18;
endcase
end
else begin
ctx_idx_ge12_1_r = ctx_idx_ge12_00_w;
end
end
end
//ctx_idx_ge12_2_r
always @* begin
if(num_c1_flag_w=='d2) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_2_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_2_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_2_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_2_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_2_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_2_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
if(~(enc_non_zero_abs_0_ge1_r | enc_non_zero_abs_1_ge1_r)) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_2_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd3, 5'd17} : {3'd3, 5'd21};//'d3 : 'd19;
'd1: ctx_idx_ge12_2_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd3, 5'd18} : {3'd3, 5'd22};//'d7 : 'd23;
'd2: ctx_idx_ge12_2_r = {3'd3, 5'd19};//'d11;
'd3: ctx_idx_ge12_2_r = {3'd3, 5'd20};//'d15;
default:ctx_idx_ge12_2_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd3, 5'd17} : {3'd3, 5'd21};//'d3 : 'd19;
endcase
end
else begin
ctx_idx_ge12_2_r = ctx_idx_ge12_00_w;
end
end
end
//ctx_idx_ge12_3_r
always @* begin
if(num_c1_flag_w=='d3) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_3_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_3_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_3_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_3_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_3_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_3_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
ctx_idx_ge12_3_r = bin_string_ge12_r[8:6]!='d0 ? ctx_idx_ge12_00_w : ctx_idx_ge12_2_r;
end
end
//ctx_idx_ge12_4_r
always @* begin
if(num_c1_flag_w=='d4) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_4_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_4_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_4_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_4_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_4_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_4_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
ctx_idx_ge12_4_r = bin_string_ge12_r[8:5]!='d0 ? ctx_idx_ge12_00_w : ctx_idx_ge12_3_r;
end
end
//ctx_idx_ge12_5_r
always @* begin
if(num_c1_flag_w=='d5) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_5_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_5_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_5_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_5_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_5_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_5_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
ctx_idx_ge12_5_r = bin_string_ge12_r[8:4]!='d0 ? ctx_idx_ge12_00_w : ctx_idx_ge12_4_r;
end
end
//ctx_idx_ge12_6_r
always @* begin
if(num_c1_flag_w=='d6) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_6_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_6_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_6_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_6_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_6_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_6_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
ctx_idx_ge12_6_r = bin_string_ge12_r[8:3]!='d0 ? ctx_idx_ge12_00_w : ctx_idx_ge12_5_r;
end
end
//ctx_idx_ge12_7_r
always @* begin
if(num_c1_flag_w=='d7) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_7_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_7_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_7_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_7_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_7_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_7_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
ctx_idx_ge12_7_r = bin_string_ge12_r[8:2]!='d0 ? ctx_idx_ge12_00_w : ctx_idx_ge12_6_r;
end
end
//ctx_idx_ge12_8_r
always @* begin
if(num_c1_flag_w=='d8) begin //ge2
if(coeff_ge1_r) begin
case(i_ctx_set_r)
'd0: ctx_idx_ge12_8_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd12} : {3'd4, 5'd16};//'d0 : 4;
'd1: ctx_idx_ge12_8_r = res_curr_state_r==RESIDUAL_LUMA_COEFF ? {3'd4, 5'd13} : {3'd4, 5'd17};//'d1 : 5;
'd2: ctx_idx_ge12_8_r = {3'd4, 5'd14};//'d2;
'd3: ctx_idx_ge12_8_r = {3'd4, 5'd15};//'d3;
default:ctx_idx_ge12_8_r = {3'd4, 5'd12};//'d0;
endcase
end
else begin
ctx_idx_ge12_8_r = 'd0;// {3'd4, 5'd12};//'d0;
end
end
else begin
ctx_idx_ge12_8_r = {3'd4, 5'd12};//'d0;
end
end
// *********************************************************
// coefficient signs
assign ctx_pair_sign_0_w = {2'b01, bin_string_sign_flag_r[15], 8'd0};
assign ctx_pair_sign_1_w = {2'b01, bin_string_sign_flag_r[14], 8'd0};
assign ctx_pair_sign_2_w = {2'b01, bin_string_sign_flag_r[13], 8'd0};
assign ctx_pair_sign_3_w = {2'b01, bin_string_sign_flag_r[12], 8'd0};
assign ctx_pair_sign_4_w = {2'b01, bin_string_sign_flag_r[11], 8'd0};
assign ctx_pair_sign_5_w = {2'b01, bin_string_sign_flag_r[10], 8'd0};
assign ctx_pair_sign_6_w = {2'b01, bin_string_sign_flag_r[ 9], 8'd0};
assign ctx_pair_sign_7_w = {2'b01, bin_string_sign_flag_r[ 8], 8'd0};
assign ctx_pair_sign_8_w = {2'b01, bin_string_sign_flag_r[ 7], 8'd0};
assign ctx_pair_sign_9_w = {2'b01, bin_string_sign_flag_r[ 6], 8'd0};
assign ctx_pair_sign_10_w = {2'b01, bin_string_sign_flag_r[ 5], 8'd0};
assign ctx_pair_sign_11_w = {2'b01, bin_string_sign_flag_r[ 4], 8'd0};
assign ctx_pair_sign_12_w = {2'b01, bin_string_sign_flag_r[ 3], 8'd0};
assign ctx_pair_sign_13_w = {2'b01, bin_string_sign_flag_r[ 2], 8'd0};
assign ctx_pair_sign_14_w = {2'b01, bin_string_sign_flag_r[ 1], 8'd0};
assign ctx_pair_sign_15_w = {2'b01, bin_string_sign_flag_r[ 0], 8'd0};
assign valid_num_bin_sign_r = enc_coeff_tot_r;
assign bin_string_sign_flag_r = {enc_non_zero_0_w[15], enc_non_zero_1_w[15], enc_non_zero_2_w[15], enc_non_zero_3_w[15],
enc_non_zero_4_w[15], enc_non_zero_5_w[15], enc_non_zero_6_w[15], enc_non_zero_7_w[15],
enc_non_zero_8_w[15], enc_non_zero_9_w[15], enc_non_zero_10_w[15], enc_non_zero_11_w[15],
enc_non_zero_12_w[15], enc_non_zero_13_w[15], enc_non_zero_14_w[15], enc_non_zero_15_w[15]};
//enc_sign_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_sign_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r!=TU_RES_SIGN)
enc_sign_cyc_cnt_r <= 'd0;
else if(enc_sign_done_w)
enc_sign_cyc_cnt_r <= 'd0;
else
enc_sign_cyc_cnt_r <= enc_sign_cyc_cnt_r + 'd1;
end
//enc_sign_cyc_tot_r
always @* begin
case(enc_coeff_tot_r)
'd0, 'd1, 'd2, 'd3, 'd4: enc_sign_cyc_tot_r = 'd0;
'd5, 'd6, 'd7, 'd8: enc_sign_cyc_tot_r = 'd1;
'd9, 'd10, 'd11, 'd12: enc_sign_cyc_tot_r = 'd2;
'd13, 'd14, 'd15, 'd16: enc_sign_cyc_tot_r = 'd3;
default: enc_sign_cyc_tot_r = 'd0;
endcase
end
assign enc_sign_done_w = (enc_sign_cyc_cnt_r==enc_sign_cyc_tot_r) ? 'd1 : 'd0;
// **********************************************************
// coefficient remains
assign ctx_pair_remain_0_w = {2'b01, bin_string_remain_r[15], 8'd0};
assign ctx_pair_remain_1_w = {2'b01, bin_string_remain_r[14], 8'd0};
assign ctx_pair_remain_2_w = {2'b01, bin_string_remain_r[13], 8'd0};
assign ctx_pair_remain_3_w = {2'b01, bin_string_remain_r[12], 8'd0};
assign ctx_pair_remain_4_w = {2'b01, bin_string_remain_r[11], 8'd0};
assign ctx_pair_remain_5_w = {2'b01, bin_string_remain_r[10], 8'd0};
assign ctx_pair_remain_6_w = {2'b01, bin_string_remain_r[ 9], 8'd0};
assign ctx_pair_remain_7_w = {2'b01, bin_string_remain_r[ 8], 8'd0};
assign ctx_pair_remain_8_w = {2'b01, bin_string_remain_r[ 7], 8'd0};
assign ctx_pair_remain_9_w = {2'b01, bin_string_remain_r[ 6], 8'd0};
assign ctx_pair_remain_10_w = {2'b01, bin_string_remain_r[ 5], 8'd0};
assign ctx_pair_remain_11_w = {2'b01, bin_string_remain_r[ 4], 8'd0};
assign ctx_pair_remain_12_w = {2'b01, bin_string_remain_r[ 3], 8'd0};
assign ctx_pair_remain_13_w = {2'b01, bin_string_remain_r[ 2], 8'd0};
assign ctx_pair_remain_14_w = {2'b01, bin_string_remain_r[ 1], 8'd0};
assign ctx_pair_remain_15_w = {2'b01, bin_string_remain_r[ 0], 8'd0};
//first_non_one_coeff_idx_r
always @* begin
if(enc_non_zero_abs_0_r!='d1)
first_non_one_coeff_idx_r = 'd0;
else if(enc_non_zero_abs_1_r!='d1)
first_non_one_coeff_idx_r = 'd1;
else if(enc_non_zero_abs_2_r!='d1)
first_non_one_coeff_idx_r = 'd2;
else if(enc_non_zero_abs_3_r!='d1)
first_non_one_coeff_idx_r = 'd3;
else if(enc_non_zero_abs_4_r!='d1)
first_non_one_coeff_idx_r = 'd4;
else if(enc_non_zero_abs_5_r!='d1)
first_non_one_coeff_idx_r = 'd5;
else if(enc_non_zero_abs_6_r!='d1)
first_non_one_coeff_idx_r = 'd6;
else if(enc_non_zero_abs_7_r!='d1)
first_non_one_coeff_idx_r = 'd7;
else
first_non_one_coeff_idx_r = 'd15;
end
assign enc_remain_done_w = ((enc_remain_cnt_r==(enc_remain_tot_r-1))
&& (enc_remain_cyc_cnt_r==(enc_remain_cyc_tot_r-1))) ? 'd1 : 'd0;
//enc_remain_tot_r
always @* begin
if(tu_curr_state_r==TU_RES_REMAIN)
enc_remain_tot_r = enc_coeff_tot_r;
else
enc_remain_tot_r = 'd0;
end
//enc_remain_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_remain_cnt_r <= 'd0;
else if(tu_curr_state_r!=TU_RES_REMAIN)
enc_remain_cnt_r <= 'd0;
else if(enc_remain_cyc_cnt_r==(enc_remain_cyc_tot_r-1)) begin
if(enc_remain_cnt_r==(enc_remain_tot_r-1))
enc_remain_cnt_r <= 'd0;
else
enc_remain_cnt_r <= enc_remain_cnt_r + 'd1;
end
else
enc_remain_cnt_r <= enc_remain_cnt_r;
end
//enc_remain_cyc_tot_r
always @* begin
case(valid_num_remain_all_r)
'd0, 'd1, 'd2, 'd3, 'd4 : enc_remain_cyc_tot_r = 'd1;
'd5, 'd6, 'd7, 'd8 : enc_remain_cyc_tot_r = 'd2;
'd9, 'd10, 'd11, 'd12 : enc_remain_cyc_tot_r = 'd3;
'd13, 'd14, 'd15, 'd16 : enc_remain_cyc_tot_r = 'd4;
'd17, 'd18, 'd19, 'd20 : enc_remain_cyc_tot_r = 'd5;
'd21, 'd22, 'd23, 'd24 : enc_remain_cyc_tot_r = 'd6;
'd25, 'd26, 'd27, 'd28 : enc_remain_cyc_tot_r = 'd7;
'd29, 'd30, 'd31 : enc_remain_cyc_tot_r = 'd8;
default: enc_remain_cyc_tot_r = 'd1;
endcase
end
//enc_remain_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
enc_remain_cyc_cnt_r <= 'd0;
else if(tu_curr_state_r!=TU_RES_REMAIN)
enc_remain_cyc_cnt_r <= 'd0;
else if(enc_remain_cyc_cnt_r==(enc_remain_cyc_tot_r-1))
enc_remain_cyc_cnt_r <= 'd0;
else
enc_remain_cyc_cnt_r <= enc_remain_cyc_cnt_r + 'd1;
end
//base_level_r
always @* begin
if(tu_curr_state_r==TU_RES_REMAIN) begin
case(first_non_one_coeff_idx_r)
'd0: begin
if(enc_remain_cnt_r>'d0)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd1: begin
if(enc_remain_cnt_r>'d1)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd2: begin
if(enc_remain_cnt_r>'d2)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd3: begin
if(enc_remain_cnt_r>'d3)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd4: begin
if(enc_remain_cnt_r>'d4)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd5: begin
if(enc_remain_cnt_r>'d5)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd6: begin
if(enc_remain_cnt_r>'d6)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
'd7: begin
if(enc_remain_cnt_r>'d7)
base_level_r = 'd2;
else
base_level_r = 'd3;
end
default:begin
if(enc_remain_cnt_r[3])
base_level_r = 'd1;
else
base_level_r = 'd3;
end
endcase
end
else
base_level_r = 'd0;
end
//encoding_coeff_abs_r
always @* begin
case(enc_remain_cnt_r)
'd0: encoding_coeff_abs_r = enc_non_zero_abs_0_r ;
'd1: encoding_coeff_abs_r = enc_non_zero_abs_1_r ;
'd2: encoding_coeff_abs_r = enc_non_zero_abs_2_r ;
'd3: encoding_coeff_abs_r = enc_non_zero_abs_3_r ;
'd4: encoding_coeff_abs_r = enc_non_zero_abs_4_r ;
'd5: encoding_coeff_abs_r = enc_non_zero_abs_5_r ;
'd6: encoding_coeff_abs_r = enc_non_zero_abs_6_r ;
'd7: encoding_coeff_abs_r = enc_non_zero_abs_7_r ;
'd8: encoding_coeff_abs_r = enc_non_zero_abs_8_r ;
'd9: encoding_coeff_abs_r = enc_non_zero_abs_9_r ;
'd10: encoding_coeff_abs_r = enc_non_zero_abs_10_r ;
'd11: encoding_coeff_abs_r = enc_non_zero_abs_11_r ;
'd12: encoding_coeff_abs_r = enc_non_zero_abs_12_r ;
'd13: encoding_coeff_abs_r = enc_non_zero_abs_13_r ;
'd14: encoding_coeff_abs_r = enc_non_zero_abs_14_r ;
'd15: encoding_coeff_abs_r = enc_non_zero_abs_15_r ;
default:encoding_coeff_abs_r = 'd0;
endcase
end
//encoding_coeff_abs_remain_r
always @* begin
if(enc_remain_cnt_r[3])
encoding_coeff_abs_remain_r = encoding_coeff_abs_r - 'd1;
else
encoding_coeff_abs_remain_r = encoding_coeff_abs_r - base_level_r;
end
//i_go_rice_param_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
i_go_rice_param_r <= 'd0;
else if(blk_e_done_r)
i_go_rice_param_r <= 'd0;
else begin
if(enc_remain_cyc_cnt_r==(enc_remain_cyc_tot_r-1)) begin
case(i_go_rice_param_r)
'd0: if(encoding_coeff_abs_r>3)
i_go_rice_param_r <= 'd1;
else
i_go_rice_param_r <= 'd0;
'd1: if(encoding_coeff_abs_r>6)
i_go_rice_param_r <= 'd2;
else
i_go_rice_param_r <= 'd1;
'd2: if(encoding_coeff_abs_r>12)
i_go_rice_param_r <= 'd3;
else
i_go_rice_param_r <= 'd2;
'd3: if(encoding_coeff_abs_r>24)
i_go_rice_param_r <= 'd4;
else
i_go_rice_param_r <= 'd3;
'd4: i_go_rice_param_r <= i_go_rice_param_r;
default:i_go_rice_param_r <= i_go_rice_param_r;
endcase
end
else begin
i_go_rice_param_r <= i_go_rice_param_r;
end
end
end
//valid_num_remain_all_r
always @* begin
if(encoding_coeff_abs_remain_r[15])
valid_num_remain_all_r = 'd0;
else begin
case(i_go_rice_param_r)
'd0: begin
if(encoding_coeff_abs_remain_r<'d4)
valid_num_remain_all_r = encoding_coeff_abs_remain_r + 'd1;
else if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d5)
valid_num_remain_all_r = 'd6;
else if(encoding_coeff_abs_remain_r>='d6 && encoding_coeff_abs_remain_r<='d9)
valid_num_remain_all_r = 'd8;
else if(encoding_coeff_abs_remain_r>='d10 && encoding_coeff_abs_remain_r<='d17)
valid_num_remain_all_r = 'd10;
else if(encoding_coeff_abs_remain_r>='d18 && encoding_coeff_abs_remain_r<='d33)
valid_num_remain_all_r = 'd12;
else if(encoding_coeff_abs_remain_r>='d34 && encoding_coeff_abs_remain_r<='d65)
valid_num_remain_all_r = 'd14;
else if(encoding_coeff_abs_remain_r>='d66 && encoding_coeff_abs_remain_r<='d129)
valid_num_remain_all_r = 'd16;
else if(encoding_coeff_abs_remain_r>='d130 && encoding_coeff_abs_remain_r<='d257)
valid_num_remain_all_r = 'd18;
else if(encoding_coeff_abs_remain_r>='d258 && encoding_coeff_abs_remain_r<='d513)
valid_num_remain_all_r = 'd20;
else if(encoding_coeff_abs_remain_r>='d514 && encoding_coeff_abs_remain_r<='d1025)
valid_num_remain_all_r = 'd22;
else if(encoding_coeff_abs_remain_r>='d1026 && encoding_coeff_abs_remain_r<='d2049)
valid_num_remain_all_r = 'd24;
else
valid_num_remain_all_r = 'd26;
end
'd1: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d1)
valid_num_remain_all_r = 'd2;
else if(encoding_coeff_abs_remain_r>='d2 && encoding_coeff_abs_remain_r<='d3)
valid_num_remain_all_r = 'd3;
else if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d5)
valid_num_remain_all_r = 'd4;
else if(encoding_coeff_abs_remain_r>='d6 && encoding_coeff_abs_remain_r<='d7)
valid_num_remain_all_r = 'd5;
else if(encoding_coeff_abs_remain_r>='d8 && encoding_coeff_abs_remain_r<='d11)
valid_num_remain_all_r = 'd7;
else if(encoding_coeff_abs_remain_r>='d12 && encoding_coeff_abs_remain_r<='d19)
valid_num_remain_all_r = 'd9;
else if(encoding_coeff_abs_remain_r>='d20 && encoding_coeff_abs_remain_r<='d35)
valid_num_remain_all_r = 'd11;
else if(encoding_coeff_abs_remain_r>='d36 && encoding_coeff_abs_remain_r<='d67)
valid_num_remain_all_r = 'd13;
else if(encoding_coeff_abs_remain_r>='d68 && encoding_coeff_abs_remain_r<='d131)
valid_num_remain_all_r = 'd15;
else if(encoding_coeff_abs_remain_r>='d132 && encoding_coeff_abs_remain_r<='d259)
valid_num_remain_all_r = 'd17;
else if(encoding_coeff_abs_remain_r>='d260 && encoding_coeff_abs_remain_r<='d515)
valid_num_remain_all_r = 'd19;
else if(encoding_coeff_abs_remain_r>='d516 && encoding_coeff_abs_remain_r<='d1027)
valid_num_remain_all_r = 'd21;
else if(encoding_coeff_abs_remain_r>='d1028 && encoding_coeff_abs_remain_r<='d2051)
valid_num_remain_all_r = 'd23;
else
valid_num_remain_all_r = 'd25;
end
'd2: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d3)
valid_num_remain_all_r = 'd3;
else if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d7)
valid_num_remain_all_r = 'd4;
else if(encoding_coeff_abs_remain_r>='d8 && encoding_coeff_abs_remain_r<='d11)
valid_num_remain_all_r = 'd5;
else if(encoding_coeff_abs_remain_r>='d12 && encoding_coeff_abs_remain_r<='d15)
valid_num_remain_all_r = 'd6;
else if(encoding_coeff_abs_remain_r>='d16 && encoding_coeff_abs_remain_r<='d23)
valid_num_remain_all_r = 'd8;
else if(encoding_coeff_abs_remain_r>='d24 && encoding_coeff_abs_remain_r<='d39)
valid_num_remain_all_r = 'd10;
else if(encoding_coeff_abs_remain_r>='d40 && encoding_coeff_abs_remain_r<='d71)
valid_num_remain_all_r = 'd12;
else if(encoding_coeff_abs_remain_r>='d72 && encoding_coeff_abs_remain_r<='d135)
valid_num_remain_all_r = 'd14;
else if(encoding_coeff_abs_remain_r>='d136 && encoding_coeff_abs_remain_r<='d263)
valid_num_remain_all_r = 'd16;
else if(encoding_coeff_abs_remain_r>='d264 && encoding_coeff_abs_remain_r<='d519)
valid_num_remain_all_r = 'd18;
else if(encoding_coeff_abs_remain_r>='d520 && encoding_coeff_abs_remain_r<='d1031)
valid_num_remain_all_r = 'd20;
else if(encoding_coeff_abs_remain_r>='d1032 && encoding_coeff_abs_remain_r<='d2055)
valid_num_remain_all_r = 'd22;
else if(encoding_coeff_abs_remain_r>='d2056 && encoding_coeff_abs_remain_r<='d4103)
valid_num_remain_all_r = 'd24;
else
valid_num_remain_all_r = 'd26;
end
'd3: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d7)
valid_num_remain_all_r = 'd4;
else if(encoding_coeff_abs_remain_r>='d8 && encoding_coeff_abs_remain_r<='d15)
valid_num_remain_all_r = 'd5;
else if(encoding_coeff_abs_remain_r>='d16 && encoding_coeff_abs_remain_r<='d23)
valid_num_remain_all_r = 'd6;
else if(encoding_coeff_abs_remain_r>='d24 && encoding_coeff_abs_remain_r<='d31)
valid_num_remain_all_r = 'd7;
else if(encoding_coeff_abs_remain_r>='d32&& encoding_coeff_abs_remain_r<='d47)
valid_num_remain_all_r = 'd9;
else if(encoding_coeff_abs_remain_r>='d48 && encoding_coeff_abs_remain_r<='d79)
valid_num_remain_all_r = 'd11;
else if(encoding_coeff_abs_remain_r>='d80 && encoding_coeff_abs_remain_r<='d143)
valid_num_remain_all_r = 'd13;
else if(encoding_coeff_abs_remain_r>='d144 && encoding_coeff_abs_remain_r<='d271)
valid_num_remain_all_r = 'd15;
else if(encoding_coeff_abs_remain_r>='d272 && encoding_coeff_abs_remain_r<='d527)
valid_num_remain_all_r = 'd17;
else if(encoding_coeff_abs_remain_r>='d528 && encoding_coeff_abs_remain_r<='d1039)
valid_num_remain_all_r = 'd19;
else if(encoding_coeff_abs_remain_r>='d1040 && encoding_coeff_abs_remain_r<='d2063)
valid_num_remain_all_r = 'd21;
else if(encoding_coeff_abs_remain_r>='d2064 && encoding_coeff_abs_remain_r<='d4111)
valid_num_remain_all_r = 'd23;
else if(encoding_coeff_abs_remain_r>='d4112 && encoding_coeff_abs_remain_r<='d8207)
valid_num_remain_all_r = 'd25;
else
valid_num_remain_all_r = 'd27;
end
'd4: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d15)
valid_num_remain_all_r = 'd5;
else if(encoding_coeff_abs_remain_r>='d16 && encoding_coeff_abs_remain_r<='d31)
valid_num_remain_all_r = 'd6;
else if(encoding_coeff_abs_remain_r>='d32 && encoding_coeff_abs_remain_r<='d47)
valid_num_remain_all_r = 'd7;
else if(encoding_coeff_abs_remain_r>='d48 && encoding_coeff_abs_remain_r<='d63)
valid_num_remain_all_r = 'd8;
else if(encoding_coeff_abs_remain_r>='d64 && encoding_coeff_abs_remain_r<='d95)
valid_num_remain_all_r = 'd10;
else if(encoding_coeff_abs_remain_r>='d96 && encoding_coeff_abs_remain_r<='d159)
valid_num_remain_all_r = 'd12;
else if(encoding_coeff_abs_remain_r>='d160 && encoding_coeff_abs_remain_r<='d287)
valid_num_remain_all_r = 'd14;
else if(encoding_coeff_abs_remain_r>='d288 && encoding_coeff_abs_remain_r<='d543)
valid_num_remain_all_r = 'd16;
else if(encoding_coeff_abs_remain_r>='d544 && encoding_coeff_abs_remain_r<='d1055)
valid_num_remain_all_r = 'd18;
else if(encoding_coeff_abs_remain_r>='d1056 && encoding_coeff_abs_remain_r<='d2079)
valid_num_remain_all_r = 'd20;
else if(encoding_coeff_abs_remain_r>='d2080 && encoding_coeff_abs_remain_r<='d4127)
valid_num_remain_all_r = 'd22;
else if(encoding_coeff_abs_remain_r>='d4128 && encoding_coeff_abs_remain_r<='d8223)
valid_num_remain_all_r = 'd24;
else
valid_num_remain_all_r = 'd26;
end
default:begin
valid_num_remain_all_r = 'd0;
end
endcase
end
end
reg [15:0] encoding_coeff_abs_remain_trun_w;
always @* begin
case(i_go_rice_param_r)
'd0: begin
if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d5)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd4;
else if(encoding_coeff_abs_remain_r>='d6 && encoding_coeff_abs_remain_r<='d9)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd6;
else if(encoding_coeff_abs_remain_r>='d10 && encoding_coeff_abs_remain_r<='d17)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd10;
else if(encoding_coeff_abs_remain_r>='d18 && encoding_coeff_abs_remain_r<='d33)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd18;
else if(encoding_coeff_abs_remain_r>='d34 && encoding_coeff_abs_remain_r<='d65)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd34;
else if(encoding_coeff_abs_remain_r>='d66 && encoding_coeff_abs_remain_r<='d129)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd66;
else if(encoding_coeff_abs_remain_r>='d130 && encoding_coeff_abs_remain_r<='d257)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd130;
else if(encoding_coeff_abs_remain_r>='d258 && encoding_coeff_abs_remain_r<='d513)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd258;
else if(encoding_coeff_abs_remain_r>='d514 && encoding_coeff_abs_remain_r<='d1025)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd514;
else if(encoding_coeff_abs_remain_r>='d1026 && encoding_coeff_abs_remain_r<='d2049)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd1026;
else
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd2050;
end
'd1: begin
if(encoding_coeff_abs_remain_r>='d12 && encoding_coeff_abs_remain_r<='d19)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd12;
else if(encoding_coeff_abs_remain_r>='d20 && encoding_coeff_abs_remain_r<='d35)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd20;
else if(encoding_coeff_abs_remain_r>='d36 && encoding_coeff_abs_remain_r<='d67)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd36;
else if(encoding_coeff_abs_remain_r>='d68 && encoding_coeff_abs_remain_r<='d131)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd68;
else if(encoding_coeff_abs_remain_r>='d132 && encoding_coeff_abs_remain_r<='d259)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd132;
else if(encoding_coeff_abs_remain_r>='d260 && encoding_coeff_abs_remain_r<='d515)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd260;
else if(encoding_coeff_abs_remain_r>='d516 && encoding_coeff_abs_remain_r<='d1027)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd516;
else if(encoding_coeff_abs_remain_r>='d1028 && encoding_coeff_abs_remain_r<='d2051)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd1028;
else
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd2052;
end
'd2: begin
if(encoding_coeff_abs_remain_r>='d24 && encoding_coeff_abs_remain_r<='d39)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd24;
else if(encoding_coeff_abs_remain_r>='d40 && encoding_coeff_abs_remain_r<='d71)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd40;
else if(encoding_coeff_abs_remain_r>='d72 && encoding_coeff_abs_remain_r<='d135)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd72;
else if(encoding_coeff_abs_remain_r>='d136 && encoding_coeff_abs_remain_r<='d263)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd136;
else if(encoding_coeff_abs_remain_r>='d264 && encoding_coeff_abs_remain_r<='d519)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd264;
else if(encoding_coeff_abs_remain_r>='d520 && encoding_coeff_abs_remain_r<='d1031)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd520;
else if(encoding_coeff_abs_remain_r>='d1032 && encoding_coeff_abs_remain_r<='d2055)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd1032;
else if(encoding_coeff_abs_remain_r>='d2056 && encoding_coeff_abs_remain_r<='d4103)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd2056;
else
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd4104;
end
'd3: begin
if(encoding_coeff_abs_remain_r>='d48 && encoding_coeff_abs_remain_r<='d79)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd48;
else if(encoding_coeff_abs_remain_r>='d80 && encoding_coeff_abs_remain_r<='d143)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd80;
else if(encoding_coeff_abs_remain_r>='d144 && encoding_coeff_abs_remain_r<='d271)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd144;
else if(encoding_coeff_abs_remain_r>='d272 && encoding_coeff_abs_remain_r<='d527)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd272;
else if(encoding_coeff_abs_remain_r>='d528 && encoding_coeff_abs_remain_r<='d1039)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd528;
else if(encoding_coeff_abs_remain_r>='d1040 && encoding_coeff_abs_remain_r<='d2063)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd1040;
else if(encoding_coeff_abs_remain_r>='d2064 && encoding_coeff_abs_remain_r<='d4111)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd2064;
else if(encoding_coeff_abs_remain_r>='d4112 && encoding_coeff_abs_remain_r<='d8207)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd4112;
else
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd8208;
end
'd4: begin
if(encoding_coeff_abs_remain_r>='d96 && encoding_coeff_abs_remain_r<='d159)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd96;
else if(encoding_coeff_abs_remain_r>='d160 && encoding_coeff_abs_remain_r<='d287)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd160;
else if(encoding_coeff_abs_remain_r>='d288 && encoding_coeff_abs_remain_r<='d543)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd288;
else if(encoding_coeff_abs_remain_r>='d544 && encoding_coeff_abs_remain_r<='d1055)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd544;
else if(encoding_coeff_abs_remain_r>='d1056 && encoding_coeff_abs_remain_r<='d2079)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd1056;
else if(encoding_coeff_abs_remain_r>='d2080 && encoding_coeff_abs_remain_r<='d4127)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd2080;
else if(encoding_coeff_abs_remain_r>='d4128 && encoding_coeff_abs_remain_r<='d8223)
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd4128;
else
encoding_coeff_abs_remain_trun_w = encoding_coeff_abs_remain_r - 'd8224;
end
default:begin
encoding_coeff_abs_remain_trun_w = 'd0;
end
endcase
end
//bin_string_remain_all_r
always @* begin
case(i_go_rice_param_r)
'd0: begin
if(encoding_coeff_abs_remain_r=='d0)
bin_string_remain_all_r = 'd0;
else if(encoding_coeff_abs_remain_r=='d1)
bin_string_remain_all_r = 32'h8000_0000;
else if(encoding_coeff_abs_remain_r=='d2)
bin_string_remain_all_r = 32'hc000_0000;
else if(encoding_coeff_abs_remain_r=='d3)
bin_string_remain_all_r = 32'he000_0000;
else if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d5)
bin_string_remain_all_r = {5'b11110, encoding_coeff_abs_remain_trun_w[0], 26'd0};
else if(encoding_coeff_abs_remain_r>='d6 && encoding_coeff_abs_remain_r<='d9)
bin_string_remain_all_r = {6'b111110, encoding_coeff_abs_remain_trun_w[1:0], 24'd0};
else if(encoding_coeff_abs_remain_r>='d10 && encoding_coeff_abs_remain_r<='d17)
bin_string_remain_all_r = {7'b1111110, encoding_coeff_abs_remain_trun_w[2:0], 22'd0};
else if(encoding_coeff_abs_remain_r>='d18 && encoding_coeff_abs_remain_r<='d33)
bin_string_remain_all_r = {8'b11111110, encoding_coeff_abs_remain_trun_w[3:0], 20'd0};
else if(encoding_coeff_abs_remain_r>='d34 && encoding_coeff_abs_remain_r<='d65)
bin_string_remain_all_r = {9'b111111110, encoding_coeff_abs_remain_trun_w[4:0], 18'd0};
else if(encoding_coeff_abs_remain_r>='d66 && encoding_coeff_abs_remain_r<='d129)
bin_string_remain_all_r = {10'b1111111110, encoding_coeff_abs_remain_trun_w[5:0], 16'd0};
else if(encoding_coeff_abs_remain_r>='d130 && encoding_coeff_abs_remain_r<='d257)
bin_string_remain_all_r = {11'b11111111110, encoding_coeff_abs_remain_trun_w[6:0], 14'd0};
else if(encoding_coeff_abs_remain_r>='d258 && encoding_coeff_abs_remain_r<='d513)
bin_string_remain_all_r = {12'b111111111110, encoding_coeff_abs_remain_trun_w[7:0], 12'd0};
else if(encoding_coeff_abs_remain_r>='d514 && encoding_coeff_abs_remain_r<='d1025)
bin_string_remain_all_r = {13'b1111111111110, encoding_coeff_abs_remain_trun_w[8:0], 10'd0};
else if(encoding_coeff_abs_remain_r>='d1026 && encoding_coeff_abs_remain_r<='d2049)
bin_string_remain_all_r = {14'b11111111111110, encoding_coeff_abs_remain_trun_w[9:0], 8'd0};
else
bin_string_remain_all_r = {15'b111111111111110, encoding_coeff_abs_remain_trun_w[10:0], 6'd0};
end
'd1: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d1)
bin_string_remain_all_r = {1'b0, encoding_coeff_abs_remain_r[0], 30'd0};
else if(encoding_coeff_abs_remain_r>='d2 && encoding_coeff_abs_remain_r<='d3)
bin_string_remain_all_r = {2'b10, encoding_coeff_abs_remain_r[0], 29'd0};
else if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d5)
bin_string_remain_all_r = {3'b110, encoding_coeff_abs_remain_r[0], 28'd0};
else if(encoding_coeff_abs_remain_r>='d6 && encoding_coeff_abs_remain_r<='d7)
bin_string_remain_all_r = {4'b1110, encoding_coeff_abs_remain_r[0], 27'd0};
else if(encoding_coeff_abs_remain_r>='d8 && encoding_coeff_abs_remain_r<='d11)
bin_string_remain_all_r = {5'b11110, encoding_coeff_abs_remain_r[1:0], 25'd0};
else if(encoding_coeff_abs_remain_r>='d12 && encoding_coeff_abs_remain_r<='d19)
bin_string_remain_all_r = {6'b111110, encoding_coeff_abs_remain_trun_w[2:0], 23'd0};
else if(encoding_coeff_abs_remain_r>='d20 && encoding_coeff_abs_remain_r<='d35)
bin_string_remain_all_r = {7'b1111110, encoding_coeff_abs_remain_trun_w[3:0], 21'd0};
else if(encoding_coeff_abs_remain_r>='d36 && encoding_coeff_abs_remain_r<='d67)
bin_string_remain_all_r = {8'b11111110, encoding_coeff_abs_remain_trun_w[4:0], 19'd0};
else if(encoding_coeff_abs_remain_r>='d68 && encoding_coeff_abs_remain_r<='d131)
bin_string_remain_all_r = {9'b111111110, encoding_coeff_abs_remain_trun_w[5:0], 17'd0};
else if(encoding_coeff_abs_remain_r>='d132 && encoding_coeff_abs_remain_r<='d259)
bin_string_remain_all_r = {10'b1111111110, encoding_coeff_abs_remain_trun_w[6:0], 15'd0};
else if(encoding_coeff_abs_remain_r>='d260 && encoding_coeff_abs_remain_r<='d515)
bin_string_remain_all_r = {11'b11111111110, encoding_coeff_abs_remain_trun_w[7:0], 13'd0};
else if(encoding_coeff_abs_remain_r>='d516 && encoding_coeff_abs_remain_r<='d1027)
bin_string_remain_all_r = {12'b111111111110, encoding_coeff_abs_remain_trun_w[8:0], 11'd0};
else if(encoding_coeff_abs_remain_r>='d1028 && encoding_coeff_abs_remain_r<='d2051)
bin_string_remain_all_r = {13'b1111111111110, encoding_coeff_abs_remain_trun_w[9:0], 9'd0};
else
bin_string_remain_all_r = {14'b11111111111110, encoding_coeff_abs_remain_trun_w[10:0], 7'd0};
end
'd2: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d3)
bin_string_remain_all_r = {1'b0, encoding_coeff_abs_remain_r[1:0], 29'd0};
else if(encoding_coeff_abs_remain_r>='d4 && encoding_coeff_abs_remain_r<='d7)
bin_string_remain_all_r = {2'b10, encoding_coeff_abs_remain_r[1:0], 28'd0};
else if(encoding_coeff_abs_remain_r>='d8 && encoding_coeff_abs_remain_r<='d11)
bin_string_remain_all_r = {3'b110, encoding_coeff_abs_remain_r[1:0], 27'd0};
else if(encoding_coeff_abs_remain_r>='d12 && encoding_coeff_abs_remain_r<='d15)
bin_string_remain_all_r = {4'b1110, encoding_coeff_abs_remain_r[1:0], 26'd0};
else if(encoding_coeff_abs_remain_r>='d16 && encoding_coeff_abs_remain_r<='d23)
bin_string_remain_all_r = {5'b11110, encoding_coeff_abs_remain_r[2:0], 24'd0};
else if(encoding_coeff_abs_remain_r>='d24 && encoding_coeff_abs_remain_r<='d39)
bin_string_remain_all_r = {6'b111110, encoding_coeff_abs_remain_trun_w[3:0], 22'd0};
else if(encoding_coeff_abs_remain_r>='d40 && encoding_coeff_abs_remain_r<='d71)
bin_string_remain_all_r = {7'b1111110, encoding_coeff_abs_remain_trun_w[4:0], 20'd0};
else if(encoding_coeff_abs_remain_r>='d72 && encoding_coeff_abs_remain_r<='d135)
bin_string_remain_all_r = {8'b11111110, encoding_coeff_abs_remain_trun_w[5:0], 18'd0};
else if(encoding_coeff_abs_remain_r>='d136 && encoding_coeff_abs_remain_r<='d263)
bin_string_remain_all_r = {9'b111111110, encoding_coeff_abs_remain_trun_w[6:0], 16'd0};
else if(encoding_coeff_abs_remain_r>='d264 && encoding_coeff_abs_remain_r<='d519)
bin_string_remain_all_r = {10'b1111111110, encoding_coeff_abs_remain_trun_w[7:0], 14'd0};
else if(encoding_coeff_abs_remain_r>='d520 && encoding_coeff_abs_remain_r<='d1031)
bin_string_remain_all_r = {11'b11111111110, encoding_coeff_abs_remain_trun_w[8:0], 12'd0};
else if(encoding_coeff_abs_remain_r>='d1032 && encoding_coeff_abs_remain_r<='d2055)
bin_string_remain_all_r = {12'b111111111110, encoding_coeff_abs_remain_trun_w[9:0], 10'd0};
else if(encoding_coeff_abs_remain_r>='d2056 && encoding_coeff_abs_remain_r<='d4103)
bin_string_remain_all_r = {13'b1111111111110, encoding_coeff_abs_remain_trun_w[10:0], 8'd0};
else
bin_string_remain_all_r = {14'b11111111111110, encoding_coeff_abs_remain_trun_w[11:0], 6'd0};
end
'd3: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d7)
bin_string_remain_all_r = {1'b0, encoding_coeff_abs_remain_r[2:0], 28'd0};
else if(encoding_coeff_abs_remain_r>='d8 && encoding_coeff_abs_remain_r<='d15)
bin_string_remain_all_r = {2'b10, encoding_coeff_abs_remain_r[2:0], 27'd0};
else if(encoding_coeff_abs_remain_r>='d16 && encoding_coeff_abs_remain_r<='d23)
bin_string_remain_all_r = {3'b110, encoding_coeff_abs_remain_r[2:0], 26'd0};
else if(encoding_coeff_abs_remain_r>='d24 && encoding_coeff_abs_remain_r<='d31)
bin_string_remain_all_r = {4'b1110, encoding_coeff_abs_remain_r[2:0], 25'd0};
else if(encoding_coeff_abs_remain_r>='d32&& encoding_coeff_abs_remain_r<='d47)
bin_string_remain_all_r = {5'b11110, encoding_coeff_abs_remain_r[3:0], 23'd0};
else if(encoding_coeff_abs_remain_r>='d48 && encoding_coeff_abs_remain_r<='d79)
bin_string_remain_all_r = {6'b111110, encoding_coeff_abs_remain_trun_w[4:0], 21'd0};
else if(encoding_coeff_abs_remain_r>='d80 && encoding_coeff_abs_remain_r<='d143)
bin_string_remain_all_r = {7'b1111110, encoding_coeff_abs_remain_trun_w[5:0], 19'd0};
else if(encoding_coeff_abs_remain_r>='d144 && encoding_coeff_abs_remain_r<='d271)
bin_string_remain_all_r = {8'b11111110, encoding_coeff_abs_remain_trun_w[6:0], 17'd0};
else if(encoding_coeff_abs_remain_r>='d272 && encoding_coeff_abs_remain_r<='d527)
bin_string_remain_all_r = {9'b111111110, encoding_coeff_abs_remain_trun_w[7:0], 15'd0};
else if(encoding_coeff_abs_remain_r>='d528 && encoding_coeff_abs_remain_r<='d1039)
bin_string_remain_all_r = {10'b1111111110, encoding_coeff_abs_remain_trun_w[8:0], 13'd0};
else if(encoding_coeff_abs_remain_r>='d1040 && encoding_coeff_abs_remain_r<='d2063)
bin_string_remain_all_r = {11'b11111111110, encoding_coeff_abs_remain_trun_w[9:0], 11'd0};
else if(encoding_coeff_abs_remain_r>='d2064 && encoding_coeff_abs_remain_r<='d4111)
bin_string_remain_all_r = {12'b111111111110, encoding_coeff_abs_remain_trun_w[10:0], 9'd0};
else if(encoding_coeff_abs_remain_r>='d4112 && encoding_coeff_abs_remain_r<='d8207)
bin_string_remain_all_r = {13'b1111111111110, encoding_coeff_abs_remain_trun_w[11:0], 7'd0};
else
bin_string_remain_all_r = {14'b11111111111110, encoding_coeff_abs_remain_trun_w[12:0], 5'd0};
end
'd4: begin
if(encoding_coeff_abs_remain_r>='d0 && encoding_coeff_abs_remain_r<='d15)
bin_string_remain_all_r = {1'b0, encoding_coeff_abs_remain_r[3:0], 27'd0};
else if(encoding_coeff_abs_remain_r>='d16 && encoding_coeff_abs_remain_r<='d31)
bin_string_remain_all_r = {2'b10, encoding_coeff_abs_remain_r[3:0], 26'd0};
else if(encoding_coeff_abs_remain_r>='d32 && encoding_coeff_abs_remain_r<='d47)
bin_string_remain_all_r = {3'b110, encoding_coeff_abs_remain_r[3:0], 25'd0};
else if(encoding_coeff_abs_remain_r>='d48 && encoding_coeff_abs_remain_r<='d63)
bin_string_remain_all_r = {4'b1110, encoding_coeff_abs_remain_r[3:0], 24'd0};
else if(encoding_coeff_abs_remain_r>='d64 && encoding_coeff_abs_remain_r<='d95)
bin_string_remain_all_r = {5'b11110, encoding_coeff_abs_remain_r[4:0], 22'd0};
else if(encoding_coeff_abs_remain_r>='d96 && encoding_coeff_abs_remain_r<='d159)
bin_string_remain_all_r = {6'b111110, encoding_coeff_abs_remain_trun_w[5:0], 20'd0};
else if(encoding_coeff_abs_remain_r>='d160 && encoding_coeff_abs_remain_r<='d287)
bin_string_remain_all_r = {7'b1111110, encoding_coeff_abs_remain_trun_w[6:0], 18'd0};
else if(encoding_coeff_abs_remain_r>='d288 && encoding_coeff_abs_remain_r<='d543)
bin_string_remain_all_r = {8'b11111110, encoding_coeff_abs_remain_trun_w[7:0], 16'd0};
else if(encoding_coeff_abs_remain_r>='d544 && encoding_coeff_abs_remain_r<='d1055)
bin_string_remain_all_r = {9'b111111110, encoding_coeff_abs_remain_trun_w[8:0], 14'd0};
else if(encoding_coeff_abs_remain_r>='d1056 && encoding_coeff_abs_remain_r<='d2079)
bin_string_remain_all_r = {10'b1111111110, encoding_coeff_abs_remain_trun_w[9:0], 12'd0};
else if(encoding_coeff_abs_remain_r>='d2080 && encoding_coeff_abs_remain_r<='d4127)
bin_string_remain_all_r = {11'b11111111110, encoding_coeff_abs_remain_trun_w[10:0], 10'd0};
else if(encoding_coeff_abs_remain_r>='d4128 && encoding_coeff_abs_remain_r<='d8223)
bin_string_remain_all_r = {12'b111111111110, encoding_coeff_abs_remain_trun_w[11:0], 8'd0};
else
bin_string_remain_all_r = {13'b1111111111110, encoding_coeff_abs_remain_trun_w[12:0], 6'd0};
end
default:begin
bin_string_remain_all_r = 'd0;
end
endcase
end
//bin_string_remain_r
always @* begin
if(tu_curr_state_r!=TU_RES_REMAIN)
bin_string_remain_r = 'd0;
else if(enc_remain_cyc_cnt_r<'d4)
bin_string_remain_r = bin_string_remain_all_r[31:16];
else
bin_string_remain_r = bin_string_remain_all_r[15:0];
end
//valid_num_remain_r
always @* begin
if(tu_curr_state_r!=TU_RES_REMAIN)
valid_num_remain_r = 'd0;
else if(enc_remain_cyc_cnt_r<'d4) begin
if(valid_num_remain_all_r>='d16)
valid_num_remain_r = 'd16;
else
valid_num_remain_r = valid_num_remain_all_r;
end
else
valid_num_remain_r = valid_num_remain_all_r - 'd16;
end
//output
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
ctx_pair_residual0_o <= 'd0;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= 'd0;
end
else begin
case(res_curr_state_r)
RESIDUAL_ROOT_CBF: begin
ctx_pair_residual0_o <= ctx_pair_root_cbf_w;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_root_cbf_r;
end
RESIDUAL_CHROMA_CBF_ROOT: begin
ctx_pair_residual0_o <= ctx_pair_chroma_root_cbf_0_w;
ctx_pair_residual1_o <= ctx_pair_chroma_root_cbf_1_w;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_chroma_root_cbf_w;
end
RESIDUAL_SUB_DIV: begin
ctx_pair_residual0_o <= ctx_pair_sub_div_w;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_sub_div_r;
end
RESIDUAL_CHROMA_CBF: begin
ctx_pair_residual0_o <= ctx_pair_chroma_cbf_0_w;
ctx_pair_residual1_o <= ctx_pair_chroma_cbf_1_w;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_chroma_cbf_r;
end
RESIDUAL_LUMA_CBF: begin
ctx_pair_residual0_o <= ctx_pair_luma_cbf_w;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_luma_cbf_r;
end
RESIDUAL_DQP: begin
ctx_pair_residual0_o <= ctx_pair_qp_delta_0_w;
ctx_pair_residual1_o <= ctx_pair_qp_delta_1_w;
ctx_pair_residual2_o <= ctx_pair_qp_delta_2_w;
ctx_pair_residual3_o <= ctx_pair_qp_delta_3_w;
ctx_pair_residual4_o <= ctx_pair_qp_delta_4_w;
ctx_pair_residual5_o <= ctx_pair_qp_delta_5_w;
ctx_pair_residual6_o <= ctx_pair_qp_delta_6_w;
ctx_pair_residual7_o <= ctx_pair_qp_delta_7_w;
ctx_pair_residual8_o <= ctx_pair_qp_delta_8_w;
ctx_pair_residual9_o <= ctx_pair_qp_delta_9_w;
ctx_pair_residual10_o <= ctx_pair_qp_delta_10_w;
ctx_pair_residual11_o <= ctx_pair_qp_delta_11_w;
ctx_pair_residual12_o <= ctx_pair_qp_delta_12_w;
ctx_pair_residual13_o <= ctx_pair_qp_delta_13_w;
ctx_pair_residual14_o <= ctx_pair_qp_delta_14_w;
ctx_pair_residual15_o <= ctx_pair_qp_delta_15_w;
valid_num_residual_o <= valid_num_bin_qp_delta_r;
end
RESIDUAL_LUMA_COEFF,
RESIDUAL_CR_COEFF,
RESIDUAL_CB_COEFF: begin
case(tu_curr_state_r)
TU_SKIP_LAST_SIG: begin
ctx_pair_residual0_o <= ctx_pair_transform_skip_w;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= 'd1;
end
TU_LAST_SIG: begin
case(last_xy_r)
'd0: begin
//x_prefix
ctx_pair_residual0_o <= ctx_pair_last_x_prefix_0_w;
ctx_pair_residual1_o <= ctx_pair_last_x_prefix_1_w;
ctx_pair_residual2_o <= ctx_pair_last_x_prefix_2_w;
ctx_pair_residual3_o <= ctx_pair_last_x_prefix_3_w;
ctx_pair_residual4_o <= ctx_pair_last_x_prefix_4_w;
ctx_pair_residual5_o <= ctx_pair_last_x_prefix_5_w;
ctx_pair_residual6_o <= ctx_pair_last_x_prefix_6_w;
ctx_pair_residual7_o <= ctx_pair_last_x_prefix_7_w;
ctx_pair_residual8_o <= ctx_pair_last_x_prefix_8_w;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_last_x_prefix_w;
end
'd2: begin
//x_suffix
ctx_pair_residual0_o <= ctx_pair_last_x_suffix_0_w;
ctx_pair_residual1_o <= ctx_pair_last_x_suffix_1_w;
ctx_pair_residual2_o <= ctx_pair_last_x_suffix_2_w;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_last_x_suffix_r;
end
'd1: begin
//y_prefix
ctx_pair_residual0_o <= ctx_pair_last_y_prefix_0_w;
ctx_pair_residual1_o <= ctx_pair_last_y_prefix_1_w;
ctx_pair_residual2_o <= ctx_pair_last_y_prefix_2_w;
ctx_pair_residual3_o <= ctx_pair_last_y_prefix_3_w;
ctx_pair_residual4_o <= ctx_pair_last_y_prefix_4_w;
ctx_pair_residual5_o <= ctx_pair_last_y_prefix_5_w;
ctx_pair_residual6_o <= ctx_pair_last_y_prefix_6_w;
ctx_pair_residual7_o <= ctx_pair_last_y_prefix_7_w;
ctx_pair_residual8_o <= ctx_pair_last_y_prefix_8_w;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_last_y_prefix_w;
end
'd3: begin
//y_suffix
ctx_pair_residual0_o <= ctx_pair_last_y_suffix_0_w;
ctx_pair_residual1_o <= ctx_pair_last_y_suffix_1_w;
ctx_pair_residual2_o <= ctx_pair_last_y_suffix_2_w;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_last_y_suffix_r;
end
default:begin
ctx_pair_residual0_o <= 'd0;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= 'd0;
end
endcase
end
TU_BLK_CBF: begin
ctx_pair_residual0_o <= ctx_pair_sub_blk_sig_w;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_sub_blk_sig_r;
end
TU_SIG_FLAG: begin
ctx_pair_residual0_o <= ctx_pair_sig_flag_0_r;
ctx_pair_residual1_o <= ctx_pair_sig_flag_1_r;
ctx_pair_residual2_o <= ctx_pair_sig_flag_2_r;
ctx_pair_residual3_o <= ctx_pair_sig_flag_3_r;
ctx_pair_residual4_o <= ctx_pair_sig_flag_4_r;
ctx_pair_residual5_o <= ctx_pair_sig_flag_5_r;
ctx_pair_residual6_o <= ctx_pair_sig_flag_6_r;
ctx_pair_residual7_o <= ctx_pair_sig_flag_7_r;
ctx_pair_residual8_o <= ctx_pair_sig_flag_8_r;
ctx_pair_residual9_o <= ctx_pair_sig_flag_9_r;
ctx_pair_residual10_o <= ctx_pair_sig_flag_10_r;
ctx_pair_residual11_o <= ctx_pair_sig_flag_11_r;
ctx_pair_residual12_o <= ctx_pair_sig_flag_12_r;
ctx_pair_residual13_o <= ctx_pair_sig_flag_13_r;
ctx_pair_residual14_o <= ctx_pair_sig_flag_14_r;
ctx_pair_residual15_o <= ctx_pair_sig_flag_15_r;
valid_num_residual_o <= valid_num_bin_sig_flag_r;
end
TU_GE12: begin
ctx_pair_residual0_o <= ctx_pair_ge12_0_w;
ctx_pair_residual1_o <= ctx_pair_ge12_1_w;
ctx_pair_residual2_o <= ctx_pair_ge12_2_w;
ctx_pair_residual3_o <= ctx_pair_ge12_3_w;
ctx_pair_residual4_o <= ctx_pair_ge12_4_w;
ctx_pair_residual5_o <= ctx_pair_ge12_5_w;
ctx_pair_residual6_o <= ctx_pair_ge12_6_w;
ctx_pair_residual7_o <= ctx_pair_ge12_7_w;
ctx_pair_residual8_o <= ctx_pair_ge12_8_w;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= valid_num_bin_ge12_r;
end
TU_RES_SIGN: begin
ctx_pair_residual0_o <= ctx_pair_sign_0_w;
ctx_pair_residual1_o <= ctx_pair_sign_1_w;
ctx_pair_residual2_o <= ctx_pair_sign_2_w;
ctx_pair_residual3_o <= ctx_pair_sign_3_w;
ctx_pair_residual4_o <= ctx_pair_sign_4_w;
ctx_pair_residual5_o <= ctx_pair_sign_5_w;
ctx_pair_residual6_o <= ctx_pair_sign_6_w;
ctx_pair_residual7_o <= ctx_pair_sign_7_w;
ctx_pair_residual8_o <= ctx_pair_sign_8_w;
ctx_pair_residual9_o <= ctx_pair_sign_9_w;
ctx_pair_residual10_o <= ctx_pair_sign_10_w;
ctx_pair_residual11_o <= ctx_pair_sign_11_w;
ctx_pair_residual12_o <= ctx_pair_sign_12_w;
ctx_pair_residual13_o <= ctx_pair_sign_13_w;
ctx_pair_residual14_o <= ctx_pair_sign_14_w;
ctx_pair_residual15_o <= ctx_pair_sign_15_w;
valid_num_residual_o <= valid_num_bin_sign_r;
end
TU_RES_REMAIN: begin
ctx_pair_residual0_o <= ctx_pair_remain_0_w;
ctx_pair_residual1_o <= ctx_pair_remain_1_w;
ctx_pair_residual2_o <= ctx_pair_remain_2_w;
ctx_pair_residual3_o <= ctx_pair_remain_3_w;
ctx_pair_residual4_o <= ctx_pair_remain_4_w;
ctx_pair_residual5_o <= ctx_pair_remain_5_w;
ctx_pair_residual6_o <= ctx_pair_remain_6_w;
ctx_pair_residual7_o <= ctx_pair_remain_7_w;
ctx_pair_residual8_o <= ctx_pair_remain_8_w;
ctx_pair_residual9_o <= ctx_pair_remain_9_w;
ctx_pair_residual10_o <= ctx_pair_remain_10_w;
ctx_pair_residual11_o <= ctx_pair_remain_11_w;
ctx_pair_residual12_o <= ctx_pair_remain_12_w;
ctx_pair_residual13_o <= ctx_pair_remain_13_w;
ctx_pair_residual14_o <= ctx_pair_remain_14_w;
ctx_pair_residual15_o <= ctx_pair_remain_15_w;
valid_num_residual_o <= valid_num_remain_r;
end
default: begin
ctx_pair_residual0_o <= 'd0;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= 'd0;
end
endcase
end
default: begin
ctx_pair_residual0_o <= 'd0;
ctx_pair_residual1_o <= 'd0;
ctx_pair_residual2_o <= 'd0;
ctx_pair_residual3_o <= 'd0;
ctx_pair_residual4_o <= 'd0;
ctx_pair_residual5_o <= 'd0;
ctx_pair_residual6_o <= 'd0;
ctx_pair_residual7_o <= 'd0;
ctx_pair_residual8_o <= 'd0;
ctx_pair_residual9_o <= 'd0;
ctx_pair_residual10_o <= 'd0;
ctx_pair_residual11_o <= 'd0;
ctx_pair_residual12_o <= 'd0;
ctx_pair_residual13_o <= 'd0;
ctx_pair_residual14_o <= 'd0;
ctx_pair_residual15_o <= 'd0;
valid_num_residual_o <= 'd0;
end
endcase
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_xlconcat_0_0 (
In0,
dout
);
input wire [0 : 0] In0;
output wire [0 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(1),
.NUM_PORTS(1)
) inst (
.In0(In0),
.In1(1'B0),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_phy2.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_phy2 (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire locked = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire4),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 4,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Stratix II GX",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Fast",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_enable0 = "PORT_UNUSED",
altpll_component.port_enable1 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.port_sclkout0 = "PORT_UNUSED",
altpll_component.port_sclkout1 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "31.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "250.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "31.25000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy2.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Fast"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.ppf TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -- (c) Copyright 2011-2016 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXIS Broadcaster
// Generic single-channel AXIS to multiple channel AXIS.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module top_design_1_axis_broadcaster_0_0 #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "rtl",
parameter integer C_NUM_MI_SLOTS = 2,
parameter integer C_S_AXIS_TDATA_WIDTH = 8,
parameter integer C_M_AXIS_TDATA_WIDTH = 8,
parameter integer C_AXIS_TID_WIDTH = 1,
parameter integer C_AXIS_TDEST_WIDTH = 1,
parameter integer C_S_AXIS_TUSER_WIDTH = 1,
parameter integer C_M_AXIS_TUSER_WIDTH = 1,
parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire aclk,
input wire aresetn,
input wire aclken,
// Slave side
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
input wire s_axis_tlast,
input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input wire [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// Master side
output wire [C_NUM_MI_SLOTS-1:0] m_axis_tvalid,
input wire [C_NUM_MI_SLOTS-1:0] m_axis_tready,
output wire [C_NUM_MI_SLOTS*C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire [(C_NUM_MI_SLOTS*C_M_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tstrb,
output wire [(C_NUM_MI_SLOTS*C_M_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep,
output wire [C_NUM_MI_SLOTS-1:0] m_axis_tlast,
output wire [(C_NUM_MI_SLOTS*C_AXIS_TID_WIDTH)-1:0] m_axis_tid,
output wire [(C_NUM_MI_SLOTS*C_AXIS_TDEST_WIDTH)-1:0] m_axis_tdest,
output wire [(C_NUM_MI_SLOTS*C_M_AXIS_TUSER_WIDTH)-1:0] m_axis_tuser
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TPAYLOAD_WIDTH = f_payload_width(C_S_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH,
C_AXIS_TDEST_WIDTH, C_S_AXIS_TUSER_WIDTH,
C_AXIS_SIGNAL_SET);
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TDATA_WIDTH)-1:0] m_axis_tdata_i;
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep_i;
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tstrb_i;
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TUSER_WIDTH)-1:0] m_axis_tuser_i;
axis_broadcaster_v1_1_9_core #(
.C_FAMILY (C_FAMILY),
.C_NUM_MI_SLOTS ( C_NUM_MI_SLOTS ),
.C_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ),
.C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ),
.C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ),
.C_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ),
.C_AXIS_SIGNAL_SET ( C_AXIS_SIGNAL_SET )
)
broadcaster_core
(
.aclk (aclk),
.aresetn (aresetn),
.aclken (aclken),
.s_axis_tvalid (s_axis_tvalid),
.s_axis_tready (s_axis_tready),
.s_axis_tdata (s_axis_tdata),
.s_axis_tstrb (s_axis_tstrb),
.s_axis_tkeep (s_axis_tkeep),
.s_axis_tlast (s_axis_tlast),
.s_axis_tid (s_axis_tid),
.s_axis_tdest (s_axis_tdest),
.s_axis_tuser (s_axis_tuser),
.m_axis_tvalid (m_axis_tvalid),
.m_axis_tready (m_axis_tready),
.m_axis_tdata (m_axis_tdata_i),
.m_axis_tstrb (m_axis_tstrb_i),
.m_axis_tkeep (m_axis_tkeep_i),
.m_axis_tlast (m_axis_tlast),
.m_axis_tid (m_axis_tid),
.m_axis_tdest (m_axis_tdest),
.m_axis_tuser (m_axis_tuser_i)
);
tdata_design_1_axis_broadcaster_0_0 #(
.C_S_AXIS_TDATA_WIDTH ( C_NUM_MI_SLOTS * C_S_AXIS_TDATA_WIDTH ),
.C_M_AXIS_TDATA_WIDTH ( C_NUM_MI_SLOTS * C_M_AXIS_TDATA_WIDTH )
)
tdata (
.tdata (m_axis_tdata_i),
.tdata_out (m_axis_tdata )
);
assign m_axis_tstrb = (C_S_AXIS_TDATA_WIDTH == C_M_AXIS_TDATA_WIDTH) ? m_axis_tstrb_i : {(C_NUM_MI_SLOTS*(C_M_AXIS_TDATA_WIDTH/8)){1'b0}};
assign m_axis_tkeep = (C_S_AXIS_TDATA_WIDTH == C_M_AXIS_TDATA_WIDTH) ? m_axis_tkeep_i : {(C_NUM_MI_SLOTS*(C_M_AXIS_TDATA_WIDTH/8)){1'b0}};
tuser_design_1_axis_broadcaster_0_0 #(
.C_S_AXIS_TUSER_WIDTH ( C_NUM_MI_SLOTS * C_S_AXIS_TUSER_WIDTH ),
.C_M_AXIS_TUSER_WIDTH ( C_NUM_MI_SLOTS * C_M_AXIS_TUSER_WIDTH )
)
tuser (
.tuser (m_axis_tuser_i),
.tuser_out (m_axis_tuser )
);
endmodule // axis_broadcaster_top
`default_nettype wire
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_pipe_lane.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_pipe_lane.v //
// Description : Implements the PIPE interface PIPELINE for all per lane //
// interface signals //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_pipe_lane.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_pipe_lane #
(
parameter TCQ = 100,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
) (
output wire [ 1:0] pipe_rx_char_is_k_o ,// Pipelined PIPE Rx Char Is K
output wire [31:0] pipe_rx_data_o ,// Pipelined PIPE Rx Data
output wire pipe_rx_valid_o ,// Pipelined PIPE Rx Valid
output wire pipe_rx_data_valid_o ,// Pipelined PIPE Rx Data Valid
output wire [ 2:0] pipe_rx_status_o ,// Pipelined PIPE Rx Status
output wire pipe_rx_phy_status_o ,// Pipelined PIPE Rx Phy Status
output wire pipe_rx_elec_idle_o ,// Pipelined PIPE Rx Electrical Idle
output wire pipe_rx_eqdone_o ,// Pipelined PIPE Rx Eq
output wire pipe_rx_eqlpadaptdone_o ,// Pipelined PIPE Rx Eq
output wire pipe_rx_eqlplffssel_o ,// Pipelined PIPE Rx Eq
output wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_o,// Pipelined PIPE Rx Eq
output wire pipe_rx_startblock_o ,// Pipelined PIPE Rx Start Block
output wire [ 1:0] pipe_rx_syncheader_o ,// Pipelined PIPE Rx Sync Header
output wire pipe_rx_slide_o ,// Pipelined PIPE Rx Slide
output wire pipe_rx_syncdone_o ,// Pipelined PIPE Rx Sync done
input wire pipe_rx_polarity_i ,// PIPE Rx Polarity
input wire [ 1:0] pipe_rx_eqcontrol_i ,// PIPE Rx Eq control
input wire [ 5:0] pipe_rx_eqlplffs_i ,// PIPE Rx Eq
input wire [ 3:0] pipe_rx_eqlptxpreset_i ,// PIPE Rx Eq
input wire [ 2:0] pipe_rx_eqpreset_i ,// PIPE Rx Eq
output wire [17:0] pipe_tx_eqcoeff_o ,// Pipelined Tx Eq Coefficient
output wire pipe_tx_eqdone_o ,// Pipelined Tx Eq Done
input wire pipe_tx_compliance_i ,// PIPE Tx Compliance
input wire [ 1:0] pipe_tx_char_is_k_i ,// PIPE Tx Char Is K
input wire [31:0] pipe_tx_data_i ,// PIPE Tx Data
input wire pipe_tx_elec_idle_i ,// PIPE Tx Electrical Idle
input wire [ 1:0] pipe_tx_powerdown_i ,// PIPE Tx Powerdown
input wire pipe_tx_datavalid_i ,// PIPE Tx Data Valid
input wire pipe_tx_startblock_i ,// PIPE Tx Start Block
input wire [ 1:0] pipe_tx_syncheader_i ,// PIPE Tx Sync Header
input wire [ 1:0] pipe_tx_eqcontrol_i ,// PIPE Tx Eq Control
input wire [ 5:0] pipe_tx_eqdeemph_i ,// PIPE Tx Eq Deemphesis
input wire [ 3:0] pipe_tx_eqpreset_i ,// PIPE Tx Preset
input wire [ 1:0] pipe_rx_char_is_k_i ,// PIPE Rx Char Is K
input wire [31:0] pipe_rx_data_i ,// PIPE Rx Data
input wire pipe_rx_valid_i ,// PIPE Rx Valid
input wire pipe_rx_data_valid_i ,// PIPE Rx Data Valid
input wire [ 2:0] pipe_rx_status_i ,// PIPE Rx Status
input wire pipe_rx_phy_status_i ,// PIPE Rx Phy Status
input wire pipe_rx_elec_idle_i ,// PIPE Rx Electrical Idle
input wire pipe_rx_eqdone_i ,// PIPE Rx Eq
input wire pipe_rx_eqlpadaptdone_i ,// PIPE Rx Eq
input wire pipe_rx_eqlplffssel_i ,// PIPE Rx Eq
input wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_i,// PIPE Rx Eq
input wire pipe_rx_startblock_i ,// PIPE Rx Start Block
input wire [ 1:0] pipe_rx_syncheader_i ,// PIPE Rx Sync Header
input wire pipe_rx_slide_i ,// PIPE Rx Slide
input wire pipe_rx_syncdone_i ,// PIPE Rx Sync done
output wire pipe_rx_polarity_o ,// Pipelined PIPE Rx Polarity
output wire [ 1:0] pipe_rx_eqcontrol_o ,// Pipelined PIPE Rx Eq control
output wire [ 5:0] pipe_rx_eqlplffs_o ,// Pipelined PIPE Rx Eq
output wire [ 3:0] pipe_rx_eqlptxpreset_o ,// Pipelined PIPE Rx Eq
output wire [ 2:0] pipe_rx_eqpreset_o ,// Pipelined PIPE Rx Eq
input wire [17:0] pipe_tx_eqcoeff_i ,// PIPE Tx Eq Coefficient
input wire pipe_tx_eqdone_i ,// PIPE Tx Eq Done
output wire pipe_tx_compliance_o ,// Pipelined PIPE Tx Compliance
output wire [ 1:0] pipe_tx_char_is_k_o ,// Pipelined PIPE Tx Char Is K
output wire [31:0] pipe_tx_data_o ,// Pipelined PIPE Tx Data
output wire pipe_tx_elec_idle_o ,// Pipelined PIPE Tx Electrical Idle
output wire [ 1:0] pipe_tx_powerdown_o ,// Pipelined PIPE Tx Powerdown
output wire pipe_tx_datavalid_o ,// Pipelined PIPE Tx Data Valid
output wire pipe_tx_startblock_o ,// Pipelined PIPE Tx Start Block
output wire [ 1:0] pipe_tx_syncheader_o ,// Pipelined PIPE Tx Sync Header
output wire [ 1:0] pipe_tx_eqcontrol_o ,// Pipelined PIPE Tx Eq Control
output wire [ 5:0] pipe_tx_eqdeemph_o ,// Pipelined PIPE Tx Eq Deemphesis
output wire [ 3:0] pipe_tx_eqpreset_o ,// Pipelined PIPE Tx Preset
input wire pipe_clk ,// PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [31:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_data_valid_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_eqdone_q ;
reg pipe_rx_eqlpadaptdone_q ;
reg pipe_rx_eqlplffssel_q ;
reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_q ;
reg pipe_rx_startblock_q ;
reg [ 1:0] pipe_rx_syncheader_q ;
reg pipe_rx_slide_q ;
reg pipe_rx_syncdone_q ;
reg pipe_rx_polarity_q ;
reg [ 1:0] pipe_rx_eqcontrol_q ;
reg [ 5:0] pipe_rx_eqlplffs_q ;
reg [ 3:0] pipe_rx_eqlptxpreset_q ;
reg [ 2:0] pipe_rx_eqpreset_q ;
reg [17:0] pipe_tx_eqcoeff_q ;
reg pipe_tx_eqdone_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [31:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg pipe_tx_datavalid_q ;
reg pipe_tx_startblock_q ;
reg [ 1:0] pipe_tx_syncheader_q ;
reg [ 1:0] pipe_tx_eqcontrol_q ;
reg [ 5:0] pipe_tx_eqdeemph_q ;
reg [ 3:0] pipe_tx_eqpreset_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [31:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_data_valid_qq ;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_eqdone_qq ;
reg pipe_rx_eqlpadaptdone_qq ;
reg pipe_rx_eqlplffssel_qq ;
reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_qq ;
reg pipe_rx_startblock_qq ;
reg [ 1:0] pipe_rx_syncheader_qq ;
reg pipe_rx_slide_qq ;
reg pipe_rx_syncdone_qq ;
reg pipe_rx_polarity_qq ;
reg [ 1:0] pipe_rx_eqcontrol_qq ;
reg [ 5:0] pipe_rx_eqlplffs_qq ;
reg [ 3:0] pipe_rx_eqlptxpreset_qq ;
reg [ 2:0] pipe_rx_eqpreset_qq ;
reg [17:0] pipe_tx_eqcoeff_qq ;
reg pipe_tx_eqdone_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [31:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
reg pipe_tx_datavalid_qq ;
reg pipe_tx_startblock_qq ;
reg [ 1:0] pipe_tx_syncheader_qq ;
reg [ 1:0] pipe_tx_eqcontrol_qq ;
reg [ 5:0] pipe_tx_eqdeemph_qq ;
reg [ 3:0] pipe_tx_eqpreset_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ;
assign pipe_rx_data_o = pipe_rx_data_i ;
assign pipe_rx_valid_o = pipe_rx_valid_i ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ;
assign pipe_rx_status_o = pipe_rx_status_i ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ;
assign pipe_rx_startblock_o = pipe_rx_startblock_i ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ;
assign pipe_rx_slide_o = pipe_rx_slide_i ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ;
assign pipe_rx_polarity_o = pipe_rx_polarity_i ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ;
assign pipe_tx_compliance_o = pipe_tx_compliance_i ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ;
assign pipe_tx_data_o = pipe_tx_data_i ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ;
assign pipe_tx_startblock_o = pipe_tx_startblock_i ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 2'b00;
pipe_rx_data_q <= #TCQ 32'h00000000;
pipe_rx_valid_q <= #TCQ 1'b0;
pipe_rx_data_valid_q <= #TCQ 1'b0;
pipe_rx_status_q <= #TCQ 2'b00;
pipe_rx_phy_status_q <= #TCQ 1'b0;
pipe_rx_elec_idle_q <= #TCQ 1'b1;
pipe_rx_eqdone_q <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0;
pipe_rx_eqlplffssel_q <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000;
pipe_rx_startblock_q <= #TCQ 1'b0;
pipe_rx_syncheader_q <= #TCQ 2'b00;
pipe_rx_slide_q <= #TCQ 1'b0;
pipe_rx_syncdone_q <= #TCQ 1'b0;
pipe_rx_polarity_q <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_q <= #TCQ 1'b0;
pipe_rx_eqlplffs_q <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_q <= #TCQ 2'b00;
pipe_rx_eqpreset_q <= #TCQ 6'b000000;
pipe_tx_eqcoeff_q <= #TCQ 4'h0;
pipe_tx_eqdone_q <= #TCQ 3'b000;
pipe_tx_compliance_q <= #TCQ 1'b0;
pipe_tx_char_is_k_q <= #TCQ 2'b00;
pipe_tx_data_q <= #TCQ 32'h00000000;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b00;
pipe_tx_datavalid_q <= #TCQ 1'b0;
pipe_tx_startblock_q <= #TCQ 1'b0;
pipe_tx_syncheader_q <= #TCQ 2'b00;
pipe_tx_eqcontrol_q <= #TCQ 2'b00;
pipe_tx_eqdeemph_q <= #TCQ 6'b000000;
pipe_tx_eqpreset_q <= #TCQ 4'h0;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ;
pipe_rx_data_q <= #TCQ pipe_rx_data_i ;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ;
pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ;
pipe_rx_status_q <= #TCQ pipe_rx_status_i ;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ;
pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ;
pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ;
pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ;
pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ;
pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ;
pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ;
pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ;
pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ;
pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ;
pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ;
pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ;
pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ;
pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ;
pipe_tx_data_q <= #TCQ pipe_tx_data_i ;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ;
pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ;
pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ;
pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ;
pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ;
pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ;
pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q ;
assign pipe_rx_data_o = pipe_rx_data_q ;
assign pipe_rx_valid_o = pipe_rx_valid_q ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_q ;
assign pipe_rx_status_o = pipe_rx_status_q ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_q ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_q ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_q ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_q ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_q ;
assign pipe_rx_startblock_o = pipe_rx_startblock_q ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_q ;
assign pipe_rx_slide_o = pipe_rx_slide_q ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_q ;
assign pipe_rx_polarity_o = pipe_rx_polarity_q ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_q ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_q ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_q ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_q ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_q ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_q ;
assign pipe_tx_compliance_o = pipe_tx_compliance_q ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q ;
assign pipe_tx_data_o = pipe_tx_data_q ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_q ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_q ;
assign pipe_tx_startblock_o = pipe_tx_startblock_q ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_q ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_q ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_q ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_q ;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 2'b00;
pipe_rx_data_q <= #TCQ 32'h00000000;
pipe_rx_valid_q <= #TCQ 1'b0;
pipe_rx_data_valid_q <= #TCQ 1'b0;
pipe_rx_status_q <= #TCQ 2'b00;
pipe_rx_phy_status_q <= #TCQ 1'b0;
pipe_rx_elec_idle_q <= #TCQ 1'b1;
pipe_rx_eqdone_q <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0;
pipe_rx_eqlplffssel_q <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000;
pipe_rx_startblock_q <= #TCQ 1'b0;
pipe_rx_syncheader_q <= #TCQ 2'b00;
pipe_rx_slide_q <= #TCQ 1'b0;
pipe_rx_syncdone_q <= #TCQ 1'b0;
pipe_rx_polarity_q <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_q <= #TCQ 1'b0;
pipe_rx_eqlplffs_q <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_q <= #TCQ 2'b00;
pipe_rx_eqpreset_q <= #TCQ 6'b000000;
pipe_tx_eqcoeff_q <= #TCQ 4'h0;
pipe_tx_eqdone_q <= #TCQ 3'b000;
pipe_tx_compliance_q <= #TCQ 1'b0;
pipe_tx_char_is_k_q <= #TCQ 2'b00;
pipe_tx_data_q <= #TCQ 32'h00000000;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b00;
pipe_tx_datavalid_q <= #TCQ 1'b0;
pipe_tx_startblock_q <= #TCQ 1'b0;
pipe_tx_syncheader_q <= #TCQ 2'b00;
pipe_tx_eqcontrol_q <= #TCQ 2'b00;
pipe_tx_eqdeemph_q <= #TCQ 6'b000000;
pipe_tx_eqpreset_q <= #TCQ 4'h0;
pipe_rx_char_is_k_qq <= #TCQ 2'b00;
pipe_rx_data_qq <= #TCQ 32'h00000000;
pipe_rx_valid_qq <= #TCQ 1'b0;
pipe_rx_data_valid_qq <= #TCQ 1'b0;
pipe_rx_status_qq <= #TCQ 2'b00;
pipe_rx_phy_status_qq <= #TCQ 1'b0;
pipe_rx_elec_idle_qq <= #TCQ 1'b1;
pipe_rx_eqdone_qq <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_qq <= #TCQ 1'b0;
pipe_rx_eqlplffssel_qq <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ 17'b00000000000000000;
pipe_rx_startblock_qq <= #TCQ 1'b0;
pipe_rx_syncheader_qq <= #TCQ 2'b00;
pipe_rx_slide_qq <= #TCQ 1'b0;
pipe_rx_syncdone_qq <= #TCQ 1'b0;
pipe_rx_polarity_qq <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_qq <= #TCQ 1'b0;
pipe_rx_eqlplffs_qq <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_qq <= #TCQ 2'b00;
pipe_rx_eqpreset_qq <= #TCQ 6'b000000;
pipe_tx_eqcoeff_qq <= #TCQ 4'h0;
pipe_tx_eqdone_qq <= #TCQ 3'b000;
pipe_tx_compliance_qq <= #TCQ 1'b0;
pipe_tx_char_is_k_qq <= #TCQ 2'b00;
pipe_tx_data_qq <= #TCQ 32'h00000000;
pipe_tx_elec_idle_qq <= #TCQ 1'b1;
pipe_tx_powerdown_qq <= #TCQ 2'b00;
pipe_tx_datavalid_qq <= #TCQ 1'b0;
pipe_tx_startblock_qq <= #TCQ 1'b0;
pipe_tx_syncheader_qq <= #TCQ 2'b00;
pipe_tx_eqcontrol_qq <= #TCQ 2'b00;
pipe_tx_eqdeemph_qq <= #TCQ 6'b000000;
pipe_tx_eqpreset_qq <= #TCQ 4'h0;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ;
pipe_rx_data_q <= #TCQ pipe_rx_data_i ;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ;
pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ;
pipe_rx_status_q <= #TCQ pipe_rx_status_i ;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ;
pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ;
pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ;
pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ;
pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ;
pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ;
pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ;
pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ;
pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ;
pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ;
pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ;
pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ;
pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ;
pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ;
pipe_tx_data_q <= #TCQ pipe_tx_data_i ;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ;
pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ;
pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ;
pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ;
pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ;
pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ;
pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ;
pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q ;
pipe_rx_data_qq <= #TCQ pipe_rx_data_q ;
pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q ;
pipe_rx_data_valid_qq <= #TCQ pipe_rx_data_valid_q ;
pipe_rx_status_qq <= #TCQ pipe_rx_status_q ;
pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q ;
pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q ;
pipe_rx_eqdone_qq <= #TCQ pipe_rx_eqdone_q ;
pipe_rx_eqlpadaptdone_qq <= #TCQ pipe_rx_eqlpadaptdone_q ;
pipe_rx_eqlplffssel_qq <= #TCQ pipe_rx_eqlplffssel_q ;
pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ pipe_rx_eqlpnewtxcoefforpreset_q ;
pipe_rx_startblock_qq <= #TCQ pipe_rx_startblock_q ;
pipe_rx_syncheader_qq <= #TCQ pipe_rx_syncheader_q ;
pipe_rx_slide_qq <= #TCQ pipe_rx_slide_q ;
pipe_rx_syncdone_qq <= #TCQ pipe_rx_syncdone_q ;
pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q ;
pipe_rx_eqcontrol_qq <= #TCQ pipe_rx_eqcontrol_q ;
pipe_rx_eqlplffs_qq <= #TCQ pipe_rx_eqlplffs_q ;
pipe_rx_eqlptxpreset_qq <= #TCQ pipe_rx_eqlptxpreset_q ;
pipe_rx_eqpreset_qq <= #TCQ pipe_rx_eqpreset_q ;
pipe_tx_eqcoeff_qq <= #TCQ pipe_tx_eqcoeff_q ;
pipe_tx_eqdone_qq <= #TCQ pipe_tx_eqdone_q ;
pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q ;
pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q ;
pipe_tx_data_qq <= #TCQ pipe_tx_data_q ;
pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q ;
pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q ;
pipe_tx_datavalid_qq <= #TCQ pipe_tx_datavalid_q ;
pipe_tx_startblock_qq <= #TCQ pipe_tx_startblock_q ;
pipe_tx_syncheader_qq <= #TCQ pipe_tx_syncheader_q ;
pipe_tx_eqcontrol_qq <= #TCQ pipe_tx_eqcontrol_q ;
pipe_tx_eqdeemph_qq <= #TCQ pipe_tx_eqdeemph_q ;
pipe_tx_eqpreset_qq <= #TCQ pipe_tx_eqpreset_q ;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq ;
assign pipe_rx_data_o = pipe_rx_data_qq ;
assign pipe_rx_valid_o = pipe_rx_valid_qq ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_qq ;
assign pipe_rx_status_o = pipe_rx_status_qq ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_qq ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_qq ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_qq ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_qq ;
assign pipe_rx_startblock_o = pipe_rx_startblock_qq ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_qq ;
assign pipe_rx_slide_o = pipe_rx_slide_qq ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_qq ;
assign pipe_rx_polarity_o = pipe_rx_polarity_qq ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_qq ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_qq ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_qq ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_qq ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_qq ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_qq ;
assign pipe_tx_compliance_o = pipe_tx_compliance_qq ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq ;
assign pipe_tx_data_o = pipe_tx_data_qq ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_qq ;
assign pipe_tx_startblock_o = pipe_tx_startblock_qq ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_qq ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_qq ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_qq ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_qq ;
end // if (PIPE_PIPELINE_STAGES == 2)
// Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2
else begin
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ;
assign pipe_rx_data_o = pipe_rx_data_i ;
assign pipe_rx_valid_o = pipe_rx_valid_i ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ;
assign pipe_rx_status_o = pipe_rx_status_i ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ;
assign pipe_rx_startblock_o = pipe_rx_startblock_i ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ;
assign pipe_rx_slide_o = pipe_rx_slide_i ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ;
assign pipe_rx_polarity_o = pipe_rx_polarity_i ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ;
assign pipe_tx_compliance_o = pipe_tx_compliance_i ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ;
assign pipe_tx_data_o = pipe_tx_data_i ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ;
assign pipe_tx_startblock_o = pipe_tx_startblock_i ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ;
end
endgenerate
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V |
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:46:57 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/RAT_RegisterFile_0_0_sim_netlist.v
// Design : RAT_RegisterFile_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_RegisterFile_0_0,RegisterFile,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "RegisterFile,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_RegisterFile_0_0
(D_IN,
DX_OUT,
DY_OUT,
ADRX,
ADRY,
WE,
CLK);
input [7:0]D_IN;
output [7:0]DX_OUT;
output [7:0]DY_OUT;
input [4:0]ADRX;
input [4:0]ADRY;
input WE;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
wire [4:0]ADRX;
wire [4:0]ADRY;
wire CLK;
wire [7:0]DX_OUT;
wire [7:0]DY_OUT;
wire [7:0]D_IN;
wire WE;
RAT_RegisterFile_0_0_RegisterFile U0
(.ADRX(ADRX),
.ADRY(ADRY),
.CLK(CLK),
.DX_OUT(DX_OUT),
.DY_OUT(DY_OUT),
.D_IN(D_IN),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RegisterFile" *)
module RAT_RegisterFile_0_0_RegisterFile
(DY_OUT,
DX_OUT,
CLK,
D_IN,
WE,
ADRX,
ADRY);
output [7:0]DY_OUT;
output [7:0]DX_OUT;
input CLK;
input [7:0]D_IN;
input WE;
input [4:0]ADRX;
input [4:0]ADRY;
wire [4:0]ADRX;
wire [4:0]ADRY;
wire CLK;
wire [7:0]DX_OUT;
wire [7:0]DY_OUT;
wire [7:0]D_IN;
wire WE;
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_0_0
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[0]),
.DPO(DY_OUT[0]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[0]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_1_1
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[1]),
.DPO(DY_OUT[1]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[1]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_2_2
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[2]),
.DPO(DY_OUT[2]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[2]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_3_3
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[3]),
.DPO(DY_OUT[3]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[3]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_4_4
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[4]),
.DPO(DY_OUT[4]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[4]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_5_5
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[5]),
.DPO(DY_OUT[5]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[5]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_6_6
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[6]),
.DPO(DY_OUT[6]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[6]),
.WCLK(CLK),
.WE(WE));
RAM32X1D #(
.INIT(32'h00000000))
REG_reg_0_31_7_7
(.A0(ADRX[0]),
.A1(ADRX[1]),
.A2(ADRX[2]),
.A3(ADRX[3]),
.A4(ADRX[4]),
.D(D_IN[7]),
.DPO(DY_OUT[7]),
.DPRA0(ADRY[0]),
.DPRA1(ADRY[1]),
.DPRA2(ADRY[2]),
.DPRA3(ADRY[3]),
.DPRA4(ADRY[4]),
.SPO(DX_OUT[7]),
.WCLK(CLK),
.WE(WE));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %ALTACCUMULATE%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altaccumulate
// ============================================================
// File Name: accum32.v
// Megafunction Name(s):
// altaccumulate
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule //accum32_accum_nta
//VALID FILE
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
// Retrieval info: PRIVATE: CIN NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: COUT NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program combines two events with an event or. The tricky part
* for the vvp target is that there is a mix of posedge and negedge
* events.
*/
module ndFF ( nset, reset, Q );
input nset; // clk negedge set Q=1
input reset; // reset posedge set Q=0
output Q ; // Q output
reg Q ;
always @(negedge nset or posedge reset)
begin
if (nset ==1'b0) Q = 1'b1;
else if (reset==1'b1) Q = 1'b0;
end
endmodule
module main;
reg nset, reset;
wire Q;
ndFF dut(nset, reset, Q);
initial begin
#0 nset = 1;
reset = 1;
#1 nset = 0;
#1 if (Q !== 1'b1) begin
$display("FAILED (a) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
nset = 1;
#1 if (Q !== 1'b1) begin
$display("FAILED (b) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
reset = 0;
#1 if (Q !== 1'b1) begin
$display("FAILED (c) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
reset = 1;
#1 if (Q !== 1'b0) begin
$display("FAILED (d) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
supply0 [1:0] low;
supply1 [1:0] high;
reg [7:0] isizedwire;
reg ionewire;
`ifdef never_just_for_verilog_mode
wire oonewire; // From sub of t_inst_v2k__sub.v
`endif
wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v
wire [1:0] tied;
wire [3:0] tied_also;
hello hsub (.tied_also);
// Double underscore tests bug631
t_inst_v2k__sub sub
(
// Outputs
.osizedreg (osizedreg[7:0]),
// verilator lint_off IMPLICIT
.oonewire (oonewire),
// verilator lint_on IMPLICIT
.tied (tied[1:0]),
// Inputs
.isizedwire (isizedwire[7:0]),
.ionewire (ionewire));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
ionewire <= 1'b1;
isizedwire <= 8'd8;
end
if (cyc==2) begin
if (low != 2'b00) $stop;
if (high != 2'b11) $stop;
if (oonewire !== 1'b1) $stop;
if (isizedwire !== 8'd8) $stop;
if (tied != 2'b10) $stop;
if (tied_also != 4'b1010) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module hello(tied_also);
initial $write ("Hello\n");
output reg [3:0] tied_also = 4'b1010;
endmodule
|