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/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_2_bhv_ver_as
* |
* +-fifo_generator_v13_1_2_bhv_ver_ss
* |
* +-fifo_generator_v13_1_2_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_2_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_2_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_2_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_2_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_2_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_2_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_2_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_2_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_2_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_2_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_2_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_2_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_2_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_2_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_2_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_2_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_2_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_2_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_2
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_2_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_2_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_2_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_2_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_2_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_2_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_2_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_2_conv_ver
module fifo_generator_v13_1_2_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_2_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_2_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_2_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_2_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_2_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_2_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_2_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_2_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_2_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_2_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_2_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_2_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] loops;
reg [31:0] loops2;
integer i;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
// Unwind <
loops = 0;
loops2 = 0;
for (i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (i !== 16) $stop;
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Unwind <=
loops = 0;
for (i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Don't unwind breaked loops
loops = 0;
for (i=0; i<16; i=i+1) begin
loops = loops + 1;
if (i==7) i=99; // break out of loop
end
if (loops !== 8) $stop;
// Don't unwind large loops!
loops = 0;
for (i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
// Test post-increment
loops = 0;
for (i=0; i<=16; i++) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test pre-increment
loops = 0;
for (i=0; i<=16; ++i) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test post-decrement
loops = 0;
for (i=16; i>=0; i--) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
// Test pre-decrement
loops = 0;
for (i=16; i>=0; --i) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire r1_en /*verilator public*/ = crc[12];
wire [1:0] r1_ad /*verilator public*/ = crc[9:8];
wire r2_en /*verilator public*/ = 1'b1;
wire [1:0] r2_ad /*verilator public*/ = crc[11:10];
wire w1_en /*verilator public*/ = crc[5];
wire [1:0] w1_a /*verilator public*/ = crc[1:0];
wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}};
wire w2_en /*verilator public*/ = crc[4];
wire [1:0] w2_a /*verilator public*/ = crc[3:2];
wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
r1_d_d2r, r2_d_d2r,
// Inputs
clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d
);
input clk;
input r1_en;
input [1:0] r1_ad;
output [63:0] r1_d_d2r;
input r2_en;
input [1:0] r2_ad;
output [63:0] r2_d_d2r;
input w1_en;
input [1:0] w1_a;
input [63:0] w1_d;
input w2_en;
input [1:0] w2_a;
input [63:0] w2_d;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 13.1.0 Build 162 10/23/2013
`ifdef MODEL_TECH
`mti_v2k_int_delays_on
`endif
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONEIII_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive CYCLONEIII_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive CYCLONEIII_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module cycloneiii_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONEIII_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cycloneiii_mux21
module cycloneiii_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cycloneiii_mux41
module cycloneiii_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cycloneiii_and1
module cycloneiii_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cycloneiii_and16
module cycloneiii_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cycloneiii_bmux21
module cycloneiii_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneiii_b17mux21
module cycloneiii_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneiii_nmux21
module cycloneiii_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cycloneiii_b5mux21
module cycloneiii_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** cycloneiii_latch
module cycloneiii_latch(D, ENA, PRE, CLR, Q);
input D;
input ENA, PRE, CLR;
output Q;
reg q_out;
specify
$setup (D, negedge ENA, 0) ;
$hold (negedge ENA, D, 0) ;
(D => Q) = (0, 0);
(negedge ENA => (Q +: q_out)) = (0, 0);
(negedge PRE => (Q +: q_out)) = (0, 0);
(negedge CLR => (Q +: q_out)) = (0, 0);
endspecify
wire D_in;
wire ENA_in;
wire PRE_in;
wire CLR_in;
buf (D_in, D);
buf (ENA_in, ENA);
buf (PRE_in, PRE);
buf (CLR_in, CLR);
initial
begin
q_out <= 1'b0;
end
always @(D_in or ENA_in or PRE_in or CLR_in)
begin
if (PRE_in == 1'b0)
begin
// latch being preset, preset is active low
q_out <= 1'b1;
end
else if (CLR_in == 1'b0)
begin
// latch being cleared, clear is active low
q_out <= 1'b0;
end
else if (ENA_in == 1'b1)
begin
// latch is transparent
q_out <= D_in;
end
end
and (Q, q_out, 1'b1);
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//------------------------------------------------------------------
//
// Module Name : cycloneiii_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneiii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cycloneiii_routing_wire
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiii_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the CYCLONEIII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneiii_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneiii_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiii_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the CYCLONEIII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneiii_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // cycloneiii_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiii_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0-C9
// output counters of the CYCLONEIII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneiii_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneiii_scale_cntr
//BEGIN MF PORTING DELETE
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiii_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneiii_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // cycloneiii_pll_reg
//END MF PORTING DELETE
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiii_pll
//
// Description : Timing simulation model for the Cyclone III PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
// New Features : The list below outlines key new features in CYCLONEIII:
// 1. Dynamic Phase Reconfiguration
// 2. Dynamic PLL Reconfiguration (different protocol)
// 3. More output counters
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cycloneiii_pll (inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange
);
parameter operation_mode = "normal";
parameter pll_type = "auto"; // auto,fast(left_right),enhanced(top_bottom)
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0; // 0 .. 4095
parameter lock_low = 0; // 0 .. 7
parameter lock_window_ui = "0.05"; // "0.05", "0.1", "0.15", "0.2"
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1; // 1 .. 2
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; // "1.0", "2.0", "4.0", "6.0", "8.0", "12.0", "16.0", "20.0"
parameter loop_filter_c = 0; // 0 , 2 , 4
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "cycloneiii_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter lock_c = 4;
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk3_phase_shift_num = 0;
parameter clk4_phase_shift_num = 0;
parameter family_name = "Cyclone III";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
// TEST ONLY
parameter init_block_reset_a_count = 1;
parameter init_block_reset_b_count = 1;
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter phase_counter_select_width = 3;
parameter lock_window = 5;
parameter inclk0_freq = inclk0_input_frequency;
parameter inclk1_freq = inclk1_input_frequency;
parameter charge_pump_current_bits = 0;
parameter lock_window_ui_bits = 0;
parameter loop_filter_c_bits = 0;
parameter loop_filter_r_bits = 0;
parameter test_counter_c0_delay_chain_bits = 0;
parameter test_counter_c1_delay_chain_bits = 0;
parameter test_counter_c2_delay_chain_bits = 0;
parameter test_counter_c3_delay_chain_bits = 0;
parameter test_counter_c4_delay_chain_bits = 0;
parameter test_counter_c5_delay_chain_bits = 0;
parameter test_counter_m_delay_chain_bits = 0;
parameter test_counter_n_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter test_input_comp_delay_chain_bits = 0;
parameter test_volt_reg_output_mode_bits = 0;
parameter test_volt_reg_output_voltage_bits = 0;
parameter test_volt_reg_test_mode = "false";
parameter vco_range_detector_high_bits = -1;
parameter vco_range_detector_low_bits = -1;
parameter scan_chain_mif_file = "";
parameter auto_settings = "true";
// LOCAL_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
// OUTPUT PORTS
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
// TIMING CHECKS
specify
$setuphold(negedge scanclk, scandata, 0, 0);
$setuphold(negedge scanclk, scanclkena, 0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
reg [8*6:1] clk_num[0:4];
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
reg switch_clock;
reg [31:0] real_lock_high;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg locked_tmp;
reg areset_last_value;
reg pfdena_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
// Test bypass lock detect
reg pfd_locked;
integer cycles_pfd_low, cycles_pfd_high;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:9];
reg [31:0] c_low_val[0:9];
reg [8*6:1] c_mode_val[0:9];
reg [31:0] c_initial_val[0:9];
integer c_ph_val[0:9];
reg [31:0] c_val; // placeholder for c_high,c_low values
// VCO Frequency Range control
reg vco_over, vco_under;
// temporary registers for reprogramming
integer c_ph_val_tmp[0:9];
reg [31:0] c_high_val_tmp[0:9];
reg [31:0] c_hval[0:9];
reg [31:0] c_low_val_tmp[0:9];
reg [31:0] c_lval[0:9];
reg [8*6:1] c_mode_val_tmp[0:9];
// hold registers for reprogramming
integer c_ph_val_hold[0:9];
reg [31:0] c_high_val_hold[0:9];
reg [31:0] c_low_val_hold[0:9];
reg [8*6:1] c_mode_val_hold[0:9];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:9];
reg [31:0] c_low_val_old[0:9];
reg [8*6:1] c_mode_val_old[0:9];
integer c_ph_val_old[0:9];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
integer vco_cur;
integer vco_old;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [1:2] lfc_val_bit_setting, lfc_val_old_bit_setting;
reg vco_val_bit_setting, vco_val_old_bit_setting;
reg [3:7] lfr_val_bit_setting, lfr_val_old_bit_setting;
reg [14:16] cp_curr_bit_setting, cp_curr_old_bit_setting;
// Setting on - display real values
// Setting off - display only bits
reg pll_reconfig_display_full_setting;
reg [7:0] m_hi;
reg [7:0] m_lo;
reg [7:0] n_hi;
reg [7:0] n_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:9];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg inclk_man;
reg inclk_es;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c0_from_vco;
wire inclk_c1_from_vco;
wire inclk_c2_from_vco;
wire inclk_c3_from_vco;
wire inclk_c4_from_vco;
wire inclk_m_from_vco;
wire inclk_m;
wire pfdena_wire;
wire [4:0] clk_tmp, clk_out_pfd;
wire [4:0] clk_out;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
reg first_schedule;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
// Self Reset
wire reset_self;
// Clock Switchover
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandata_in, scandata_out; // hold scan data in negative-edge triggered ff (on either side on chain)
reg scandone_tmp;
reg initiate_reconfig;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
wire update_conf_latches;
reg update_conf_latches_reg;
reg [-1:142] scan_data;
reg scanclkena_reg; // register scanclkena on negative edge of scanclk
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// Phase reconfig
reg [2:0] phasecounterselect_reg;
reg phaseupdown_reg;
reg phasestep_reg;
integer select_counter;
integer phasestep_high_count;
reg update_phase;
// LOCAL_PARAMETERS_BEGIN
parameter SCAN_CHAIN = 144;
parameter GPP_SCAN_CHAIN = 234;
parameter FAST_SCAN_CHAIN = 180;
// primary clk is always inclk0
parameter num_phase_taps = 8;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_clk6_mult_by;
integer i_clk6_div_by;
integer i_clk7_mult_by;
integer i_clk7_div_by;
integer i_clk8_mult_by;
integer i_clk8_div_by;
integer i_clk9_mult_by;
integer i_clk9_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
integer i_clk3_phase_shift;
integer i_clk4_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_c_high[0:9];
integer i_c_low[0:9];
integer i_c_initial[0:9];
integer i_c_ph[0:9];
reg [8*6:1] i_c_mode[0:9];
integer i_vco_min;
integer i_vco_max;
integer i_vco_min_no_division;
integer i_vco_max_no_division;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_has_just_been_reconfigured;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
reg [8*`WORD_LENGTH:1] l_vco_frequency_control;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_self_reset_on_loss_lock;
integer current_clock;
integer current_clock_man;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg init;
reg tap0_is_active;
real inclk0_period, last_inclk0_period,inclk1_period, last_inclk1_period;
real last_inclk0_edge,last_inclk1_edge,diff_percent_period;
reg first_inclk0_edge_detect,first_inclk1_edge_detect;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = (numerator == 0) ? 1 : numerator;
den = (denominator == 0) ? 1 : denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
fraction_num = m_value;
fraction_div = d_value;
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, C6, C6_mode, C7, C7_mode, C8, C8_mode, C9, C9_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5, C6, C7, C8, C9;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode, C6_mode, C7_mode, C8_mode, C9_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if (C6 > max_modulus && C6_mode != "bypass" && C6_mode != " off")
max_modulus = C6;
if (C7 > max_modulus && C7_mode != "bypass" && C7_mode != " off")
max_modulus = C7;
if (C8 > max_modulus && C8_mode != "bypass" && C8_mode != " off")
max_modulus = C8;
if (C9 > max_modulus && C9_mode != "bypass" && C9_mode != " off")
max_modulus = C9;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the M and N values for Manual phase based on the following 5 criterias:
// 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
// 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
// 3. M is less than 512
// 4. N is less than 512
// 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
// of the desired vco-phase-shift-step
task find_m_and_n_4_manual_phase;
input inclock_period;
input vco_phase_shift_step;
input clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
input clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
input clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
input clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
input clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
input clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
output m;
output n;
parameter max_m = 511;
parameter max_n = 511;
parameter max_pfd = 720;
parameter min_pfd = 5;
parameter max_vco = 1600; // max vco frequency. (in mHz)
parameter min_vco = 300; // min vco frequency. (in mHz)
parameter max_offset = 0.004;
reg[160:1] clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
reg[160:1] clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
integer inclock_period;
integer vco_phase_shift_step;
integer clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
integer clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
integer clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
integer clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
integer m;
integer n;
integer pre_m;
integer pre_n;
integer m_out;
integer n_out;
integer closest_vco_step_value;
integer vco_period;
integer pfd_freq;
integer vco_freq;
integer vco_ps_step_value;
real clk0_div_factor_real;
real clk1_div_factor_real;
real clk2_div_factor_real;
real clk3_div_factor_real;
real clk4_div_factor_real;
real clk5_div_factor_real;
real clk6_div_factor_real;
real clk7_div_factor_real;
real clk8_div_factor_real;
real clk9_div_factor_real;
real clk0_div_factor_diff;
real clk1_div_factor_diff;
real clk2_div_factor_diff;
real clk3_div_factor_diff;
real clk4_div_factor_diff;
real clk5_div_factor_diff;
real clk6_div_factor_diff;
real clk7_div_factor_diff;
real clk8_div_factor_diff;
real clk9_div_factor_diff;
integer clk0_div_factor_int;
integer clk1_div_factor_int;
integer clk2_div_factor_int;
integer clk3_div_factor_int;
integer clk4_div_factor_int;
integer clk5_div_factor_int;
integer clk6_div_factor_int;
integer clk7_div_factor_int;
integer clk8_div_factor_int;
integer clk9_div_factor_int;
begin
vco_period = vco_phase_shift_step * 8;
pre_m = 0;
pre_n = 0;
closest_vco_step_value = 0;
begin : LOOP_1
for (n_out = 1; n_out < max_n; n_out = n_out +1)
begin
for (m_out = 1; m_out < max_m; m_out = m_out +1)
begin
clk0_div_factor_real = (clk0_div * m_out * 1.0 ) / (clk0_mult * n_out);
clk1_div_factor_real = (clk1_div * m_out * 1.0) / (clk1_mult * n_out);
clk2_div_factor_real = (clk2_div * m_out * 1.0) / (clk2_mult * n_out);
clk3_div_factor_real = (clk3_div * m_out * 1.0) / (clk3_mult * n_out);
clk4_div_factor_real = (clk4_div * m_out * 1.0) / (clk4_mult * n_out);
clk5_div_factor_real = (clk5_div * m_out * 1.0) / (clk5_mult * n_out);
clk6_div_factor_real = (clk6_div * m_out * 1.0) / (clk6_mult * n_out);
clk7_div_factor_real = (clk7_div * m_out * 1.0) / (clk7_mult * n_out);
clk8_div_factor_real = (clk8_div * m_out * 1.0) / (clk8_mult * n_out);
clk9_div_factor_real = (clk9_div * m_out * 1.0) / (clk9_mult * n_out);
clk0_div_factor_int = clk0_div_factor_real;
clk1_div_factor_int = clk1_div_factor_real;
clk2_div_factor_int = clk2_div_factor_real;
clk3_div_factor_int = clk3_div_factor_real;
clk4_div_factor_int = clk4_div_factor_real;
clk5_div_factor_int = clk5_div_factor_real;
clk6_div_factor_int = clk6_div_factor_real;
clk7_div_factor_int = clk7_div_factor_real;
clk8_div_factor_int = clk8_div_factor_real;
clk9_div_factor_int = clk9_div_factor_real;
clk0_div_factor_diff = (clk0_div_factor_real - clk0_div_factor_int < 0) ? (clk0_div_factor_real - clk0_div_factor_int) * -1.0 : clk0_div_factor_real - clk0_div_factor_int;
clk1_div_factor_diff = (clk1_div_factor_real - clk1_div_factor_int < 0) ? (clk1_div_factor_real - clk1_div_factor_int) * -1.0 : clk1_div_factor_real - clk1_div_factor_int;
clk2_div_factor_diff = (clk2_div_factor_real - clk2_div_factor_int < 0) ? (clk2_div_factor_real - clk2_div_factor_int) * -1.0 : clk2_div_factor_real - clk2_div_factor_int;
clk3_div_factor_diff = (clk3_div_factor_real - clk3_div_factor_int < 0) ? (clk3_div_factor_real - clk3_div_factor_int) * -1.0 : clk3_div_factor_real - clk3_div_factor_int;
clk4_div_factor_diff = (clk4_div_factor_real - clk4_div_factor_int < 0) ? (clk4_div_factor_real - clk4_div_factor_int) * -1.0 : clk4_div_factor_real - clk4_div_factor_int;
clk5_div_factor_diff = (clk5_div_factor_real - clk5_div_factor_int < 0) ? (clk5_div_factor_real - clk5_div_factor_int) * -1.0 : clk5_div_factor_real - clk5_div_factor_int;
clk6_div_factor_diff = (clk6_div_factor_real - clk6_div_factor_int < 0) ? (clk6_div_factor_real - clk6_div_factor_int) * -1.0 : clk6_div_factor_real - clk6_div_factor_int;
clk7_div_factor_diff = (clk7_div_factor_real - clk7_div_factor_int < 0) ? (clk7_div_factor_real - clk7_div_factor_int) * -1.0 : clk7_div_factor_real - clk7_div_factor_int;
clk8_div_factor_diff = (clk8_div_factor_real - clk8_div_factor_int < 0) ? (clk8_div_factor_real - clk8_div_factor_int) * -1.0 : clk8_div_factor_real - clk8_div_factor_int;
clk9_div_factor_diff = (clk9_div_factor_real - clk9_div_factor_int < 0) ? (clk9_div_factor_real - clk9_div_factor_int) * -1.0 : clk9_div_factor_real - clk9_div_factor_int;
if (((clk0_div_factor_diff < max_offset) || (clk0_used == "unused")) &&
((clk1_div_factor_diff < max_offset) || (clk1_used == "unused")) &&
((clk2_div_factor_diff < max_offset) || (clk2_used == "unused")) &&
((clk3_div_factor_diff < max_offset) || (clk3_used == "unused")) &&
((clk4_div_factor_diff < max_offset) || (clk4_used == "unused")) &&
((clk5_div_factor_diff < max_offset) || (clk5_used == "unused")) &&
((clk6_div_factor_diff < max_offset) || (clk6_used == "unused")) &&
((clk7_div_factor_diff < max_offset) || (clk7_used == "unused")) &&
((clk8_div_factor_diff < max_offset) || (clk8_used == "unused")) &&
((clk9_div_factor_diff < max_offset) || (clk9_used == "unused")) )
begin
if ((m_out != 0) && (n_out != 0))
begin
pfd_freq = 1000000 / (inclock_period * n_out);
vco_freq = (1000000 * m_out) / (inclock_period * n_out);
vco_ps_step_value = (inclock_period * n_out) / (8 * m_out);
if ( (m_out < max_m) && (n_out < max_n) && (pfd_freq >= min_pfd) && (pfd_freq <= max_pfd) &&
(vco_freq >= min_vco) && (vco_freq <= max_vco) )
begin
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
begin
pre_m = m_out;
pre_n = n_out;
disable LOOP_1;
end
else
begin
if ((closest_vco_step_value == 0) || (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
begin
pre_m = m_out;
pre_n = n_out;
closest_vco_step_value = vco_ps_step_value;
end
end
end
end
end
end
end
end
if ((pre_m != 0) && (pre_n != 0))
begin
find_simple_integer_fraction(pre_m, pre_n,
max_n, m, n);
end
else
begin
n = 1;
m = lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end
end
endtask // find_m_and_n_4_manual_phase
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
real r;
integer r_int;
begin
r = (clk_divide * M * 1.0)/(clk_mult * N);
r_int = r;
output_counter_value = r_int;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360.0 * n)) + 0.6;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45.0;
if (counter_ph == 8)
counter_ph = 0;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cycloneiii lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_freq;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
scandata_out = 1'b0;
first_inclk0_edge_detect = 1'b0;
first_inclk1_edge_detect = 1'b0;
pll_reconfig_display_full_setting = 1'b0;
initiate_reconfig = 1'b0;
switch_over_count = 0;
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_compensate_clock = alpha_tolower(compensate_clock);
l_switch_over_type = alpha_tolower(switch_over_type);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
l_vco_frequency_control = alpha_tolower(vco_frequency_control);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_self_reset_on_loss_lock = alpha_tolower(self_reset_on_loss_lock);
real_lock_high = (l_sim_gate_lock_device_behavior == "on") ? lock_high : 0;
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 0;
loop_filter_c_arr[1] = 0;
loop_filter_c_arr[2] = 0;
loop_filter_c_arr[3] = 0;
fpll_loop_filter_c_arr[0] = 0;
fpll_loop_filter_c_arr[1] = 0;
fpll_loop_filter_c_arr[2] = 0;
fpll_loop_filter_c_arr[3] = 0;
charge_pump_curr_arr[0] = 0;
charge_pump_curr_arr[1] = 0;
charge_pump_curr_arr[2] = 0;
charge_pump_curr_arr[3] = 0;
charge_pump_curr_arr[4] = 0;
charge_pump_curr_arr[5] = 0;
charge_pump_curr_arr[6] = 0;
charge_pump_curr_arr[7] = 0;
charge_pump_curr_arr[8] = 0;
charge_pump_curr_arr[9] = 0;
charge_pump_curr_arr[10] = 0;
charge_pump_curr_arr[11] = 0;
charge_pump_curr_arr[12] = 0;
charge_pump_curr_arr[13] = 0;
charge_pump_curr_arr[14] = 0;
charge_pump_curr_arr[15] = 0;
i_vco_max = vco_max;
i_vco_min = vco_min;
if(vco_post_scale == 1)
begin
i_vco_max_no_division = vco_max * 2;
i_vco_min_no_division = vco_min * 2;
end
else
begin
i_vco_max_no_division = vco_max;
i_vco_min_no_division = vco_min;
end
if (m == 0)
begin
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 1500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
// convert user parameters to advanced
if (l_vco_frequency_control == "manual_phase")
begin
find_m_and_n_4_manual_phase(inclk0_freq, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
1, 1, 1, 1, 1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,i_clk4_div_by,
1, 1, 1, 1, 1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,clk4_counter,
"unused", "unused", "unused", "unused", "unused",
i_m, i_n);
end
else if (((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
if (((l_pll_type == "fast") || (l_pll_type == "left_right")) && (l_compensate_clock == "lvdsclk"))
i_m = i_clk0_mult_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
1, 1, 1, 1, 1,
inclk0_freq);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
i_clk3_phase_shift = 0;
i_clk4_phase_shift = 0;
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
i_clk3_phase_shift = get_int_phase_shift(clk3_phase_shift, clk3_phase_shift_num);
i_clk4_phase_shift = get_int_phase_shift(clk4_phase_shift, clk4_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
i_clk3_phase_shift,
i_clk4_phase_shift,
0,
0,
0,
0,
0
);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(i_clk3_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(i_clk4_phase_shift, max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle,output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(i_clk3_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(i_clk4_phase_shift,max_neg_abs)), i_m, i_n);
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
switch_clock = 1'b0;
refclk_period = inclk0_freq * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
inclk_es = 0;
inclk_man = 0;
cycle_to_adjust = 0;
m_delay = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
inclk_out_of_range = 0;
scandone_tmp = 1'b0;
schedule_vco_last_value = 0;
scan_chain_length = SCAN_CHAIN;
num_output_cntrs = 5;
phasestep_high_count = 0;
update_phase = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 10; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_hval[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
c_lval[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
vco_cur = vco_post_scale;
i = 0;
j = 0;
inclk_last_value = 0;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
current_clock = 0;
current_clock_man = 0;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast" || (l_pll_type == "left_right"))
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch === 1'b1)
begin
current_clock_man = 1;
active_clock = 1;
end
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
c_high_val[6]+c_low_val[6], c_mode_val[6],
c_high_val[7]+c_low_val[7], c_mode_val[7],
c_high_val[8]+c_low_val[8], c_mode_val[8],
c_high_val[9]+c_low_val[9], c_mode_val[9],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
vco_over = 1'b0;
vco_under = 1'b0;
// Initialize the scan chain
// LF unused : bit 1
scan_data[-1:0] = 2'b00;
// LF Capacitance : bits 1,2 : all values are legal
scan_data[1:2] = loop_filter_c_bits;
// LF Resistance : bits 3-7
scan_data[3:7] = loop_filter_r_bits;
// VCO post scale
if(vco_post_scale == 1)
begin
scan_data[8] = 1'b1;
vco_val_old_bit_setting = 1'b1;
end
else
begin
scan_data[8] = 1'b0;
vco_val_old_bit_setting = 1'b0;
end
scan_data[9:13] = 5'b00000;
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
scan_data[14:16] = charge_pump_current_bits;
// store as old values
cp_curr_old_bit_setting = charge_pump_current_bits;
lfc_val_old_bit_setting = loop_filter_c_bits;
lfr_val_old_bit_setting = loop_filter_r_bits;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (c_mode_val[i] == "bypass")
begin
scan_data[53 + i*18 + 0] = 1'b1;
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
else
begin
scan_data[53 + i*18 + 0] = 1'b0;
// 3. Mode - odd/even
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
// 2. Hi
c_val = c_high_val[i];
for (j = 1; j <= 8; j = j + 1)
scan_data[53 + i*18 + j] = c_val[8 - j];
// 4. Low
c_val = c_low_val[i];
for (j = 10; j <= 17; j = j + 1)
scan_data[53 + i*18 + j] = c_val[17 - j];
end
// M counter
// 1. Mode - bypass (bit 17)
if (m_mode_val[0] == "bypass")
scan_data[35] = 1'b1;
else
scan_data[35] = 1'b0;
// 2. High (bit 18-25)
// 3. Mode - odd/even (bit 26)
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[36:43]= m_val[0]/2;
scan_data[44] = 1'b0;
end
else
begin
// M is odd : M high = low + 1
scan_data[36:43] = m_val[0]/2 + 1;
scan_data[44] = 1'b1;
end
// 4. Low (bit 27-34)
scan_data[45:52] = m_val[0]/2;
// N counter
// 1. Mode - bypass (bit 35)
if (n_mode_val[0] == "bypass")
scan_data[17] = 1'b1;
else
scan_data[17] = 1'b0;
// 2. High (bit 36-43)
// 3. Mode - odd/even (bit 44)
if (n_val[0] % 2 == 0)
begin
// N is an even no. : set N high = low,
// set odd/even bit to 0
scan_data[18:25] = n_val[0]/2;
scan_data[26] = 1'b0;
end
else
begin // N is odd : N high = N low + 1
scan_data[18:25] = n_val[0]/2+ 1;
scan_data[26] = 1'b1;
end
// 4. Low (bit 45-52)
scan_data[27:34] = n_val[0]/2;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
no_warn = 1'b0;
pfd_locked = 1'b0;
cycles_pfd_high = 0;
cycles_pfd_low = 0;
// check if pll is in test mode
if (m_test_source != -1 || c0_test_source != -1 || c1_test_source != -1 || c2_test_source != -1 || c3_test_source != -1 || c4_test_source != -1)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_has_just_been_reconfigured = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
tap0_is_active = 1;
// To display clock mapping
case( i_clk0_counter)
"c0" : clk_num[0] = " clk0";
"c1" : clk_num[0] = " clk1";
"c2" : clk_num[0] = " clk2";
"c3" : clk_num[0] = " clk3";
"c4" : clk_num[0] = " clk4";
default:clk_num[0] = "unused";
endcase
case( i_clk1_counter)
"c0" : clk_num[1] = " clk0";
"c1" : clk_num[1] = " clk1";
"c2" : clk_num[1] = " clk2";
"c3" : clk_num[1] = " clk3";
"c4" : clk_num[1] = " clk4";
default:clk_num[1] = "unused";
endcase
case( i_clk2_counter)
"c0" : clk_num[2] = " clk0";
"c1" : clk_num[2] = " clk1";
"c2" : clk_num[2] = " clk2";
"c3" : clk_num[2] = " clk3";
"c4" : clk_num[2] = " clk4";
default:clk_num[2] = "unused";
endcase
case( i_clk3_counter)
"c0" : clk_num[3] = " clk0";
"c1" : clk_num[3] = " clk1";
"c2" : clk_num[3] = " clk2";
"c3" : clk_num[3] = " clk3";
"c4" : clk_num[3] = " clk4";
default:clk_num[3] = "unused";
endcase
case( i_clk4_counter)
"c0" : clk_num[4] = " clk0";
"c1" : clk_num[4] = " clk1";
"c2" : clk_num[4] = " clk2";
"c3" : clk_num[4] = " clk3";
"c4" : clk_num[4] = " clk4";
default:clk_num[4] = "unused";
endcase
end
// Clock Switchover
always @(clkswitch)
begin
if (clkswitch === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if(clkswitch === 1'b1)
switch_clock = 1'b1;
else
switch_clock = 1'b0;
end
end
always @(posedge inclk[0])
begin
// Determine the inclk0 frequency
if (first_inclk0_edge_detect == 1'b0)
begin
first_inclk0_edge_detect = 1'b1;
end
else
begin
last_inclk0_period = inclk0_period;
inclk0_period = $realtime - last_inclk0_edge;
end
last_inclk0_edge = $realtime;
end
always @(posedge inclk[1])
begin
// Determine the inclk1 frequency
if (first_inclk1_edge_detect == 1'b0)
begin
first_inclk1_edge_detect = 1'b1;
end
else
begin
last_inclk1_period = inclk1_period;
inclk1_period = $realtime - last_inclk1_edge;
end
last_inclk1_edge = $realtime;
end
always @(inclk[0] or inclk[1])
begin
if(switch_clock == 1'b1)
begin
if(current_clock_man == 0)
begin
current_clock_man = 1;
active_clock = 1;
end
else
begin
current_clock_man = 0;
active_clock = 0;
end
switch_clock = 1'b0;
end
if (current_clock_man == 0)
inclk_man = inclk[0];
else
inclk_man = inclk[1];
// save the inclk event value
if (inclk[0] !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk[0];
end
if (inclk[1] !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk[1];
end
// check if either input clk is bad
if (inclk[0] === 1'b1 && inclk[0] !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk[1] === 1'b1 && inclk[1] !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk[0] !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[0] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[0];
end
end
else inclk_es = inclk[0];
end
if ((inclk[1] !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[1] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[1];
end
end
else inclk_es = inclk[1];
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (primary_clk_is_bad && (clkswitch !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
if (areset === 1'b0)
begin
if ((inclk0_period > inclk1_period) && (inclk1_period != 0))
diff_percent_period = (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else if (inclk0_period != 0)
diff_percent_period = (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
if((diff_percent_period > 20)&& (l_switch_over_type == "auto"))
begin
$display ("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.");
$display ("Time: %0t Instance: %m", $time);
end
end
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
else if(l_switch_over_type == "auto")
begin
if(current_clock == 0 && clk0_is_bad == 1'b1 && clk1_is_bad == 1'b0 )
begin
current_clock = 1;
active_clock = ~active_clock;
end
if(current_clock == 1 && clk1_is_bad == 1'b1 && clk0_is_bad == 1'b0 )
begin
current_clock = 0;
active_clock = ~active_clock;
end
end
end
if(l_switch_over_type == "manual")
inclk_n = inclk_man;
else
inclk_n = inclk_es;
inclk0_last_value = inclk[0];
inclk1_last_value = inclk[1];
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
assign inclk_m = (m_test_source == 0) ? fbclk : (m_test_source == 1) ? refclk : inclk_m_from_vco;
cycloneiii_m_cntr m1 (.clk(inclk_m),
.reset(areset || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
cycloneiii_n_cntr n1 (.clk(inclk_n),
.reset(areset),
.cout(refclk),
.modulus(n_val[0]));
// Update clock on /o counters from corresponding VCO tap
assign inclk_m_from_vco = vco_tap[m_ph_val];
assign inclk_c0_from_vco = vco_tap[c_ph_val[0]];
assign inclk_c1_from_vco = vco_tap[c_ph_val[1]];
assign inclk_c2_from_vco = vco_tap[c_ph_val[2]];
assign inclk_c3_from_vco = vco_tap[c_ph_val[3]];
assign inclk_c4_from_vco = vco_tap[c_ph_val[4]];
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// Update phase taps for C/M counters on negative edge of VCO clock output
if (update_phase == 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y < 10; y = y + 1)
begin
if (c_ph_val_tmp[y] == x)
c_ph_val[y] = c_ph_val_tmp[y];
end
if (m_ph_val_tmp == x)
m_ph_val = m_ph_val_tmp;
end
end
update_phase <= #(0.5*scanclk_period) 1'b0;
end
// On reset, set all C/M counter phase taps to POF programmed values
if (areset === 1'b1)
begin
m_ph_val = m_ph_val_orig;
m_ph_val_tmp = m_ph_val_orig;
for (i=0; i<= 9; i=i+1)
begin
c_ph_val[i] = c_ph_val_orig[i];
c_ph_val_tmp[i] = c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 0) ? fbclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
cycloneiii_scale_cntr c0 (.clk(inclk_c0),
.reset(areset || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
// Update /o counters mode and duty cycle immediately after configupdate is asserted
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 0) ? fbclk : (c1_test_source == 1) ? refclk : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
cycloneiii_scale_cntr c1 (.clk(inclk_c1),
.reset(areset || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 0) ? fbclk : (c2_test_source == 1) ? refclk :(ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
cycloneiii_scale_cntr c2 (.clk(inclk_c2),
.reset(areset || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? fbclk : (c3_test_source == 1) ? refclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
cycloneiii_scale_cntr c3 (.clk(inclk_c3),
.reset(areset || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? fbclk : (c4_test_source == 1) ? refclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
cycloneiii_scale_cntr c4 (.clk(inclk_c4),
.reset(areset || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign locked = (test_bypass_lock_detect == "on") ? pfd_locked : locked_tmp;
// Register scanclk enable
always @(negedge scanclk)
scanclkena_reg <= scanclkena;
// Negative edge flip-flop in front of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_in <= scandata;
end
end
// Scan chain
always @(posedge scanclk)
begin
if (got_first_scanclk === 1'b0)
got_first_scanclk = 1'b1;
else
scanclk_period = $time - scanclk_last_rising_edge;
if (scanclkena_reg)
begin
for (j = scan_chain_length-2; j >= 0; j = j - 1)
scan_data[j] = scan_data[j - 1];
scan_data[-1] <= scandata_in;
end
scanclk_last_rising_edge = $realtime;
end
// Scan output
assign scandataout_tmp = scan_data[SCAN_CHAIN - 2];
// Negative edge flip-flop in rear of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_out <= scandataout_tmp;
end
end
// Scan complete
always @(negedge scandone_tmp)
begin
if (got_first_scanclk === 1'b1)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" %s : C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s)", clk_num[i],i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i]);
end
// display Charge pump and loop filter values
if (pll_reconfig_display_full_setting == 1'b1)
begin
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
$display (" VCO_Post_Scale = %0d (%0d) ", vco_cur, vco_old);
end
else
begin
$display (" Charge Pump Current = %0d (%0d) ", cp_curr_bit_setting, cp_curr_old_bit_setting);
$display (" Loop Filter Capacitor = %0d (%0d) ", lfc_val_bit_setting, lfc_val_old_bit_setting);
$display (" Loop Filter Resistor = %0d (%0d) ", lfr_val_bit_setting, lfr_val_old_bit_setting);
$display (" VCO_Post_Scale = %b (%b) ", vco_val_bit_setting, vco_val_old_bit_setting);
end
cp_curr_old_bit_setting = cp_curr_bit_setting;
lfc_val_old_bit_setting = lfc_val_bit_setting;
lfr_val_old_bit_setting = lfr_val_bit_setting;
vco_val_old_bit_setting = vco_val_bit_setting;
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
// ************ PLL Phase Reconfiguration ************* //
// Latch updown,counter values at pos edge of scan clock
always @(posedge scanclk)
begin
if (phasestep_reg == 1'b1)
begin
if (phasestep_high_count == 1)
begin
phasecounterselect_reg <= phasecounterselect;
phaseupdown_reg <= phaseupdown;
// start reconfiguration
if (phasecounterselect < 3'b111) // no counters selected
begin
if (phasecounterselect == 0) // all output counters selected
begin
for (i = 0; i < num_output_cntrs; i = i + 1)
c_ph_val_tmp[i] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[i] + 1) % num_phase_taps :
(c_ph_val_tmp[i] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[i] - 1) % num_phase_taps ;
end
else if (phasecounterselect == 1) // select M counter
begin
m_ph_val_tmp = (phaseupdown == 1'b1) ?
(m_ph_val + 1) % num_phase_taps :
(m_ph_val == 0) ? num_phase_taps - 1 : (m_ph_val - 1) % num_phase_taps ;
end
else // select C counters
begin
select_counter = phasecounterselect - 2;
c_ph_val_tmp[select_counter] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[select_counter] + 1) % num_phase_taps :
(c_ph_val_tmp[select_counter] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[select_counter] - 1) % num_phase_taps ;
end
update_phase <= 1'b1;
end
end
phasestep_high_count = phasestep_high_count + 1;
end
end
// Latch phase enable (same as phasestep) on neg edge of scan clock
always @(negedge scanclk)
begin
phasestep_reg <= phasestep;
end
always @(posedge phasestep)
begin
if (update_phase == 1'b0) phasestep_high_count = 0; // phase adjustments must be 1 cycle apart
// if not, next phasestep cycle is skipped
end
// ************ PLL Full Reconfiguration ************* //
assign update_conf_latches = configupdate;
// reset counter transfer flags
always @(negedge scandone_tmp)
begin
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
update_conf_latches_reg <= 1'b0;
end
always @(posedge update_conf_latches)
begin
initiate_reconfig <= 1'b1;
end
always @(posedge areset)
begin
if (scandone_tmp == 1'b1) scandone_tmp = 1'b0;
end
always @(posedge scanclk)
begin
if (initiate_reconfig == 1'b1)
begin
initiate_reconfig <= 1'b0;
$display ("NOTE : PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
scandone_tmp <= #(scanclk_period) 1'b1;
update_conf_latches_reg <= update_conf_latches;
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
vco_old = vco_cur;
// save old values of bit settings
cp_curr_bit_setting = scan_data[14:16];
lfc_val_bit_setting = scan_data[1:2];
lfr_val_bit_setting = scan_data[3:7];
vco_val_bit_setting = scan_data[8];
// LF unused : bit 1
// LF Capacitance : bits 1,2 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
lfc_val = fpll_loop_filter_c_arr[scan_data[1:2]];
else
lfc_val = loop_filter_c_arr[scan_data[1:2]];
// LF Resistance : bits 3-7
// valid values - 00000,00100,10000,10100,11000,11011,11100,11110
if (((scan_data[3:7] == 5'b00000) || (scan_data[3:7] == 5'b00100)) ||
((scan_data[3:7] == 5'b10000) || (scan_data[3:7] == 5'b10100)) ||
((scan_data[3:7] == 5'b11000) || (scan_data[3:7] == 5'b11011)) ||
((scan_data[3:7] == 5'b11100) || (scan_data[3:7] == 5'b11110))
)
begin
lfr_val = (scan_data[3:7] == 5'b00000) ? "20" :
(scan_data[3:7] == 5'b00100) ? "16" :
(scan_data[3:7] == 5'b10000) ? "12" :
(scan_data[3:7] == 5'b10100) ? "8" :
(scan_data[3:7] == 5'b11000) ? "6" :
(scan_data[3:7] == 5'b11011) ? "4" :
(scan_data[3:7] == 5'b11100) ? "2" : "1";
end
//VCO post scale value
if (scan_data[8] === 1'b1) // vco_post_scale = 1
begin
i_vco_max = i_vco_max_no_division/2;
i_vco_min = i_vco_min_no_division/2;
vco_cur = 1;
end
else
begin
i_vco_max = vco_max;
i_vco_min = vco_min;
vco_cur = 2;
end
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
cp_curr_val = scan_data[14:16];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
for (i=0; i< num_output_cntrs; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// M counter
// 1. Mode - bypass (bit 17)
if (scan_data[17] == 1'b1)
n_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 26)
else if (scan_data[26] == 1'b1)
n_mode_val[0] = " odd";
else
n_mode_val[0] = " even";
// 2. High (bit 18-25)
n_hi = scan_data[18:25];
// 4. Low (bit 27-34)
n_lo = scan_data[27:34];
// N counter
// 1. Mode - bypass (bit 35)
if (scan_data[35] == 1'b1)
m_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 44)
else if (scan_data[44] == 1'b1)
m_mode_val[0] = " odd";
else
m_mode_val[0] = " even";
// 2. High (bit 36-43)
m_hi = scan_data[36:43];
// 4. Low (bit 45-52)
m_lo = scan_data[45:52];
//Update the current M and N counter values if the counters are NOT bypassed
if (m_mode_val[0] != "bypass")
m_val[0] = m_hi + m_lo;
if (n_mode_val[0] != "bypass")
n_val[0] = n_hi + n_lo;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (scan_data[53 + i*18 + 0] == 1'b1)
c_mode_val_tmp[i] = "bypass";
// 3. Mode - odd/even
else if (scan_data[53 + i*18 + 9] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
// 2. Hi
for (j = 1; j <= 8; j = j + 1)
c_val[8-j] = scan_data[53 + i*18 + j];
c_hval[i] = c_val[7:0];
if (c_hval[i] !== 32'h00000000)
c_high_val_tmp[i] = c_hval[i];
else
c_high_val_tmp[i] = 9'b100000000;
// 4. Low
for (j = 10; j <= 17; j = j + 1)
c_val[17 - j] = scan_data[53 + i*18 + j];
c_lval[i] = c_val[7:0];
if (c_lval[i] !== 32'h00000000)
c_low_val_tmp[i] = c_lval[i];
else
c_low_val_tmp[i] = 9'b100000000;
end
// Legality Checks
if (m_mode_val[0] != "bypass")
begin
if ((m_hi !== m_lo) && (m_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (m_hi !== 8'b00000000)
begin
// counter value
m_val_tmp[0] = m_hi + m_lo;
end
else
m_val_tmp[0] = 9'b100000000;
end
else
m_val_tmp[0] = 8'b00000001;
if (n_mode_val[0] != "bypass")
begin
if ((n_hi !== n_lo) && (n_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The N counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (n_hi !== 8'b00000000)
begin
// counter value
n_val[0] = n_hi + n_lo;
end
else
n_val[0] = 9'b100000000;
end
else
n_val[0] = 8'b00000001;
// TODO : Give warnings/errors in the following cases?
// 1. Illegal counter values (error)
// 2. Change of mode (warning)
// 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
end
end
// Self reset on loss of lock
assign reset_self = (l_self_reset_on_loss_lock == "on") ? ~pll_is_locked : 1'b0;
always @(posedge reset_self)
begin
$display (" Note : %s PLL self reset due to loss of lock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// Phase shift on /o counters
always @(schedule_vco or areset)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset === 1'b1 && areset_last_value !== areset)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
tap0_is_active = 0;
phase_adjust_was_scheduled = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// illegal value on areset
if (areset === 1'bx && (areset_last_value === 1'b0 || areset_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((areset == 1'b1))
begin
pll_is_in_reset = 1;
got_first_refclk = 0;
got_second_refclk = 0;
end
if ((schedule_vco !== schedule_vco_last_value) && (areset == 1'b1 || stop_vco == 1'b1))
begin
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end else if (areset === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset === 1'b0 && areset_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
locked_tmp = 1'b0;
end
pll_is_in_reset = 0;
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
pull_back_M = initial_delay + fbk_phase;
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_last_value = areset;
schedule_vco_last_value = schedule_vco;
end
assign pfdena_wire = (pfdena === 1'b0) ? 1'b0 : 1'b1;
// PFD enable
always @(pfdena_wire)
begin
if (pfdena_wire === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_wire === 1'b1 && pfdena_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_last_value = pfdena_wire;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
// Bypass lock detect
always @(posedge refclk)
begin
if (test_bypass_lock_detect == "on")
begin
if (pfdena_wire === 1'b1)
begin
cycles_pfd_low = 0;
if (pfd_locked == 1'b0)
begin
if (cycles_pfd_high == lock_high)
begin
$display ("Note : %s PLL locked in test mode on PFD enable assert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b1;
end
cycles_pfd_high = cycles_pfd_high + 1;
end
end
if (pfdena_wire === 1'b0)
begin
cycles_pfd_high = 0;
if (pfd_locked == 1'b1)
begin
if (cycles_pfd_low == lock_low)
begin
$display ("Note : %s PLL lost lock in test mode on PFD enable deassert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b0;
end
cycles_pfd_low = cycles_pfd_low + 1;
end
end
end
end
always @(posedge scandone_tmp or posedge locked_tmp)
begin
if(scandone_tmp == 1)
pll_has_just_been_reconfigured <= 1;
else
pll_has_just_been_reconfigured <= 0;
end
// VCO Frequency Range check
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((i_vco_max != 0 && i_vco_min != 0) && (pfdena_wire === 1'b1) &&
((refclk_period/loop_xplier > i_vco_max) ||
(refclk_period/loop_xplier < i_vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
vco_over = 1'b0;
vco_under = 1'b0;
inclk_out_of_range = 0;
no_warn = 1'b0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
// Update M counter value on feedback clock edge
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (update_conf_latches === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_wire === 1'b1 && pll_is_locked === 1'b1) ||
( ($time - refclk_time > 5 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 0) ) ||
( ($time - refclk_time > 50 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 1) ) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.", family_name);
if ((i_vco_max == 0) && (i_vco_min == 0))
$display ("Note : Please run timing simulation to check whether the input clock is operating within the supported VCO range or not.");
$display ("Time: %0t Instance: %m", $time);
end
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
// Core lock functionality
if (got_second_refclk && pfdena_wire === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= lock_window || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
// considered in phase
if (cycles_to_lock == real_lock_high)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == lock_low)
begin
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = abs(m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = abs(m_times_vco_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : 1'b0;
assign clk_out_pfd[0] = (pfd_locked == 1'b1) ? clk_tmp[0] : 1'bx;
assign clk_out_pfd[1] = (pfd_locked == 1'b1) ? clk_tmp[1] : 1'bx;
assign clk_out_pfd[2] = (pfd_locked == 1'b1) ? clk_tmp[2] : 1'bx;
assign clk_out_pfd[3] = (pfd_locked == 1'b1) ? clk_tmp[3] : 1'bx;
assign clk_out_pfd[4] = (pfd_locked == 1'b1) ? clk_tmp[4] : 1'bx;
assign clk_out[0] = (test_bypass_lock_detect == "on") ? clk_out_pfd[0] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx);
assign clk_out[1] = (test_bypass_lock_detect == "on") ? clk_out_pfd[1] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx);
assign clk_out[2] = (test_bypass_lock_detect == "on") ? clk_out_pfd[2] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx);
assign clk_out[3] = (test_bypass_lock_detect == "on") ? clk_out_pfd[3] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx);
assign clk_out[4] = (test_bypass_lock_detect == "on") ? clk_out_pfd[4] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx);
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (clk[3], 1'b1, clk_out[3]);
and (clk[4], 1'b1, clk_out[4]);
and (scandataout, 1'b1, scandata_out);
and (scandone, 1'b1, scandone_tmp);
assign fbout = fbclk;
assign vcooverrange = (vco_range_detector_high_bits == -1) ? 1'bz : vco_over;
assign vcounderrange = (vco_range_detector_low_bits == -1) ? 1'bz :vco_under;
assign phasedone = ~update_phase;
endmodule // cycloneiii_pll
//------------------------------------------------------------------
//
// Module Name : cycloneiii_lcell_comb
//
// Description : Cyclone II LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";
parameter lpm_type = "cycloneiii_lcell_comb";
reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire cin_in;
buf (dataa_in, dataa);
buf (datab_in, datab);
buf (datac_in, datac);
buf (datad_in, datad);
buf (cin_in, cin);
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
endspecify
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 2;
end
end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
end
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_ff
//
// Description : Cyclone III FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "cycloneiii_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
input sload;
input asdata;
input ena;
input devclrn;
input devpor;
output q;
tri1 devclrn;
tri1 devpor;
reg q_tmp;
wire reset;
reg d_viol;
reg sclr_viol;
reg sload_viol;
reg asdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire d_in;
wire clk_in;
wire clrn_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire asdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (d_in, d);
buf (clk_in, clk);
buf (clrn_in, clrn);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (asdata_in, asdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && clrn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, asdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
if (power_up == "low")
q_tmp = 'b0;
else if (power_up == "high")
q_tmp = 'b1;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (d_viol or sclr_viol or sload_viol or ena_viol or asdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (asdata_in or clrn_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
q_tmp <= 'b0;
else if (devclrn == 'b0)
q_tmp <= 'b0;
else if (clrn_in == 'b0)
q_tmp <= 'b0;
else if (aload_in == 'b1)
q_tmp <= asdata_in;
end
always @ (clk_in or posedge clrn_in or posedge aload_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
q_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || clrn_in === 'b0)
q_tmp <= 'b0;
else if (aload_in === 'b1)
q_tmp <= asdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
q_tmp <= 'b0 ;
else if (sload_in === 'b1)
q_tmp <= asdata_in;
else
q_tmp <= d_in;
end
end
clk_last_value = clk_in;
end
and (q, q_tmp, 1'b1);
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneiii_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneiii_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cycloneiii_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cycloneiii_ram_block
(
portadatain,
portaaddr,
portawe,
portare,
portbdatain,
portbaddr,
portbwe,
portbre,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_write_enable_clock = "clock1";
parameter port_b_read_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter port_a_read_during_write_mode = "new_data_no_nbe_read";
parameter port_b_read_during_write_mode = "new_data_no_nbe_read";
parameter power_up_uninitialized = "false";
parameter lpm_type = "cycloneiii_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2048'b0;
parameter mem_init2 = 2048'b0;
parameter mem_init3 = 2048'b0;
parameter mem_init4 = 2048'b0;
parameter port_a_byte_size = 0;
parameter port_b_byte_size = 0;
parameter safe_write = "err_on_2clk";
parameter init_file_restructured = "unused";
parameter clk0_input_clock_enable = "none"; // ena0,ena2,none
parameter clk0_core_clock_enable = "none"; // ena0,ena2,none
parameter clk0_output_clock_enable = "none"; // ena0,none
parameter clk1_input_clock_enable = "none"; // ena1,ena3,none
parameter clk1_core_clock_enable = "none"; // ena1,ena3,none
parameter clk1_output_clock_enable = "none"; // ena1,none
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_address_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_read_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// Hardware write modes
parameter dual_clock = ((operation_mode == "dual_port") ||
(operation_mode == "bidir_dual_port")) &&
(port_b_address_clock == "clock1");
parameter both_new_data_same_port = (
((port_a_read_during_write_mode == "new_data_no_nbe_read") ||
(port_a_read_during_write_mode == "dont_care")) &&
((port_b_read_during_write_mode == "new_data_no_nbe_read") ||
(port_b_read_during_write_mode == "dont_care"))
) ? 1'b1 : 1'b0;
parameter hw_write_mode_a = (
((port_a_read_during_write_mode == "old_data") ||
(port_a_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter hw_write_mode_b = (
((port_b_read_during_write_mode == "old_data") ||
(port_b_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter delay_write_pulse_a = (hw_write_mode_a != "FW") ? 1'b1 : 1'b0;
parameter delay_write_pulse_b = (hw_write_mode_b != "FW") ? 1'b1 : 1'b0;
parameter be_mask_write_a = (port_a_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter be_mask_write_b = (port_b_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter old_data_write_a = (port_a_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter old_data_write_b = (port_b_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter read_before_write_a = (hw_write_mode_a == "R+W") ? 1'b1 : 1'b0;
parameter read_before_write_b = (hw_write_mode_b == "R+W") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input portare;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbwe, portbre;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input ena2,ena3;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri1 portare_int;
assign portare_int = portare;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbwe_int;
assign portbwe_int = portbwe;
tri1 portbre_int;
assign portbre_int = portbre;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 ena2_int,ena3_int;
assign ena2_int = ena2;
assign ena3_int = ena3;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_a_rena, clk_a_wena;
wire clk_a_core;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire clk_b_rena, clk_b_wena;
wire clk_b_core;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire dataout_a_clr_reg, dataout_b_clr_reg;
wire dataout_a_clr_reg_latch, dataout_b_clr_reg_latch;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr, re_a_clr, we_b_clr, re_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in, re_a_clr_in, we_b_clr_in, re_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire re_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire we_b_reg, re_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire rw_pulse_a, rw_pulse_b;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
wire rw_pulse_prime, rw_pulse_sec;
reg read_pulse_prime_last_value, read_pulse_sec_last_value;
reg rw_pulse_prime_last_value, rw_pulse_sec_last_value;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a_in, active_b_in;
wire active_a_core,active_a_core_in,active_b_core,active_b_core_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = 0;
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {
mem_init4 , mem_init3 , mem_init2 ,
mem_init1 , mem_init0
};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_wena = (port_a_write_enable_clock == "none") ? 1'b0 : clk0_int;
assign clk_a_rena = (port_a_read_enable_clock == "none") ? 1'b0 : clk0_int;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk0_int;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_address_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_wena = (port_b_write_enable_clock == "none") ? 1'b0 : (
(port_b_write_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_rena = (port_b_read_enable_clock == "none") ? 1'b0 : (
(port_b_read_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = 1'b0;
assign dataout_a_clr = (port_a_data_out_clock == "none") ? (
(port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int)) : 1'b0;
assign dataout_a_clr_reg = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = 1'b0;
assign dataout_b_clr = (port_b_data_out_clock == "none") ? (
(port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int)) : 1'b0;
assign dataout_b_clr_reg = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = 1'b0;
assign byteena_b_clr_in = 1'b0;
assign we_a_clr_in = 1'b0;
assign re_a_clr_in = 1'b0;
assign we_b_clr_in = 1'b0;
assign re_b_clr_in = 1'b0;
assign active_a_in = (clk0_input_clock_enable == "none") ? 1'b1 : (
(clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_a_core_in = (clk0_core_clock_enable == "none") ? 1'b1 : (
(clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_b_in = (port_b_address_clock == "clock0") ? (
(clk0_input_clock_enable == "none") ? 1'b1 : ((clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_input_clock_enable == "none") ? 1'b1 : ((clk1_input_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_b_core_in = (port_b_address_clock == "clock0") ? (
(clk0_core_clock_enable == "none") ? 1'b1 : ((clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_core_clock_enable == "none") ? 1'b1 : ((clk1_core_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_write_a = (byteena_a_reg !== 'b0);
assign active_write_b = (byteena_b_reg !== 'b0);
// Store core clock enable value for delayed write
// port A core active
cycloneiii_ram_register active_core_port_a (
.d(active_a_core_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a_core),.aclrout()
);
defparam active_core_port_a.width = 1;
// port B core active
cycloneiii_ram_register active_core_port_b (
.d(active_b_core_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b_core),.aclrout()
);
defparam active_core_port_b.width = 1;
// ------- A input registers -------
// write enable
cycloneiii_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_wena),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// read enable
cycloneiii_ram_register re_a_register (
.d(portare_int),
.clk(clk_a_rena),
.aclr(re_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(re_a_reg),
.aclrout(re_a_clr)
);
// address
cycloneiii_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cycloneiii_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cycloneiii_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// write enable
cycloneiii_ram_register we_b_register (
.d(portbwe_int),
.clk(clk_b_wena),
.aclr(we_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(we_b_reg),
.aclrout(we_b_clr)
);
defparam we_b_register.width = 1;
defparam we_b_register.preset = 1'b0;
// read enable
cycloneiii_ram_register re_b_register (
.d(portbre_int),
.clk(clk_b_rena),
.aclr(re_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(re_b_reg),
.aclrout(re_b_clr)
);
defparam re_b_register.width = 1;
defparam re_b_register.preset = 1'b0;
// address
cycloneiii_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cycloneiii_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cycloneiii_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Hardware Write Modes
// CYCLONEIII
// Write pulse generation
cycloneiii_ram_pulse_generator wpgen_a (
.clk(clk_a_in),
.ena(active_a_core & active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
defparam wpgen_a.delay_pulse = delay_write_pulse_a;
cycloneiii_ram_pulse_generator wpgen_b (
.clk(clk_b_in),
.ena(active_b_core & active_write_b & mode_is_bdp & we_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
defparam wpgen_b.delay_pulse = delay_write_pulse_b;
// Read pulse generation
cycloneiii_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & ~we_a_reg & ~dataout_a_clr),
.pulse(read_pulse_a),
.cycle(clk_a_core)
);
cycloneiii_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~we_b_reg & ~dataout_b_clr),
.pulse(read_pulse_b),
.cycle(clk_b_core)
);
// Read during write pulse generation
cycloneiii_ram_pulse_generator rwpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & we_a_reg & read_before_write_a & ~dataout_a_clr),
.pulse(rw_pulse_a),.cycle()
);
cycloneiii_ram_pulse_generator rwpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & re_b_reg & we_b_reg & read_before_write_b & ~dataout_b_clr),
.pulse(rw_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign rw_pulse_prime = (primary_port_is_a) ? rw_pulse_a : rw_pulse_b;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
assign rw_pulse_sec = (primary_port_is_a) ? rw_pulse_b : rw_pulse_a;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
// Latch Clear port A
always @(posedge dataout_a_clr)
begin
if (primary_port_is_a) begin read_data_latch = 'b0; dataout_a = 'b0; end
else begin read_unit_data_latch = 'b0; dataout_a = 'b0; end
end
// Latch Clear port B
always @(posedge dataout_b_clr)
begin
if (primary_port_is_b) begin read_data_latch = 'b0; dataout_b = 'b0; end
else begin read_unit_data_latch = 'b0; dataout_b = 'b0; end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
or posedge rw_pulse_prime or posedge rw_pulse_sec
)
begin
// Read before Write stage 1 : read data from memory
if (rw_pulse_prime && (rw_pulse_prime !== rw_pulse_prime_last_value))
begin
read_data_latch = mem[addr_prime_reg];
rw_pulse_prime_last_value = rw_pulse_prime;
end
if (rw_pulse_sec && (rw_pulse_sec !== rw_pulse_sec_last_value))
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
rw_pulse_sec_last_value = rw_pulse_sec;
end
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
if ((row_sec == addr_prime_reg) && (read_pulse_sec))
begin
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime && read_pulse_prime !== read_pulse_prime_last_value)
begin
read_data_latch = mem[addr_prime_reg];
read_pulse_prime_last_value = read_pulse_prime;
end
if (read_pulse_sec && read_pulse_sec !== read_pulse_sec_last_value)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
read_pulse_sec_last_value = read_pulse_sec;
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
always @(negedge read_pulse_prime) read_pulse_prime_last_value = 1'b0;
always @(negedge read_pulse_sec) read_pulse_sec_last_value = 1'b0;
always @(negedge rw_pulse_prime) rw_pulse_prime_last_value = 1'b0;
always @(negedge rw_pulse_sec) rw_pulse_sec_last_value = 1'b0;
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Read during Write stage 2 : Send data to output
always @(negedge rw_pulse_prime)
begin
if (primary_port_is_a)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_a[i] = read_data_latch[i];
end
else
dataout_a = read_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_b[i] = read_data_latch[i];
end
else
dataout_b = read_data_latch;
end
end
always @(negedge rw_pulse_sec)
begin
if (primary_port_is_b)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_a[i] = read_unit_data_latch[i];
end
else
dataout_a = read_unit_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_b[i] = read_unit_data_latch[i];
end
else
dataout_b = read_unit_data_latch;
end
end
// Same port feed through
cycloneiii_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a_core & ~mode_is_dp & ~old_data_write_a & we_a_reg & re_a_reg & ~dataout_a_clr),
.pulse(read_pulse_a_feedthru),.cycle()
);
cycloneiii_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & ~old_data_write_b & we_b_reg & re_b_reg & ~dataout_b_clr),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_a[i] = datain_prime_reg[i];
end
else
dataout_a = datain_prime_reg ^ mask_vector_prime;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_b[i] = datain_prime_reg[i];
end
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_a[i] = datain_sec_reg[i];
end
else
dataout_a = datain_sec_reg ^ mask_vector_sec;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_b[i] = datain_sec_reg[i];
end
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a_core & re_a_reg & ~dataout_a_clr & ~dataout_a_clr_reg_latch)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge we_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
mem_invalidate = 1'b1;
else if ((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~dataout_b_clr & ~dataout_b_clr_reg_latch)
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge we_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Aclr mux registers (Latch Clear) --------
// port A
cycloneiii_ram_register aclr__a__mux_register (
.d(dataout_a_clr),
.clk(clk_a_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_a_clr_reg_latch),.aclrout()
);
// port B
cycloneiii_ram_register aclr__b__mux_register (
.d(dataout_b_clr),
.clk(clk_b_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_b_clr_reg_latch),.aclrout()
);
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
cycloneiii_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr_reg),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
cycloneiii_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr_reg),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cycloneiii_ram_block
//---------------------------------------------------------------------
//
// Module Name : cycloneiii_mac_data_reg
//
// Description : Simulation model for the data input register of
// Cyclone II MAC_MULT
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_mac_data_reg (clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp;
wire [17:0] dataout_wire;
// INTERNAL VARIABLES
wire [17:0] data_ipd;
wire enable;
wire no_clr;
reg d_viol;
reg ena_viol;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
// BUFFER INPUTS
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
buf (data_ipd[0], data[0]);
buf (data_ipd[1], data[1]);
buf (data_ipd[2], data[2]);
buf (data_ipd[3], data[3]);
buf (data_ipd[4], data[4]);
buf (data_ipd[5], data[5]);
buf (data_ipd[6], data[6]);
buf (data_ipd[7], data[7]);
buf (data_ipd[8], data[8]);
buf (data_ipd[9], data[9]);
buf (data_ipd[10], data[10]);
buf (data_ipd[11], data[11]);
buf (data_ipd[12], data[12]);
buf (data_ipd[13], data[13]);
buf (data_ipd[14], data[14]);
buf (data_ipd[15], data[15]);
buf (data_ipd[16], data[16]);
buf (data_ipd[17], data[17]);
assign enable = (!aclr_ipd) && (ena_ipd);
assign no_clr = (!aclr_ipd);
// TIMING PATHS
specify
$setuphold (posedge clk &&& enable, data, 0, 0, d_viol);
$setuphold (posedge clk &&& no_clr, ena, 0, 0, ena_viol);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
(posedge aclr => (dataout +: 1'b0)) = (0, 0);
endspecify
initial
begin
clk_last_value <= 'b0;
dataout_tmp <= 18'b0;
end
always @(clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
dataout_tmp <= 'bX;
end
else if (aclr_ipd == 1'b1)
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd === 1'b1)
dataout_tmp <= data_ipd;
end
clk_last_value <= clk_ipd;
end // always
assign dataout_wire = dataout_tmp;
and (dataout[0], dataout_wire[0], 1'b1);
and (dataout[1], dataout_wire[1], 1'b1);
and (dataout[2], dataout_wire[2], 1'b1);
and (dataout[3], dataout_wire[3], 1'b1);
and (dataout[4], dataout_wire[4], 1'b1);
and (dataout[5], dataout_wire[5], 1'b1);
and (dataout[6], dataout_wire[6], 1'b1);
and (dataout[7], dataout_wire[7], 1'b1);
and (dataout[8], dataout_wire[8], 1'b1);
and (dataout[9], dataout_wire[9], 1'b1);
and (dataout[10], dataout_wire[10], 1'b1);
and (dataout[11], dataout_wire[11], 1'b1);
and (dataout[12], dataout_wire[12], 1'b1);
and (dataout[13], dataout_wire[13], 1'b1);
and (dataout[14], dataout_wire[14], 1'b1);
and (dataout[15], dataout_wire[15], 1'b1);
and (dataout[16], dataout_wire[16], 1'b1);
and (dataout[17], dataout_wire[17], 1'b1);
endmodule //cycloneiii_mac_data_reg
//------------------------------------------------------------------
//
// Module Name : cycloneiii_mac_sign_reg
//
// Description : Simulation model for the sign input register of
// Cyclone II MAC_MULT
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneiii_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs
tri1 aclr, ena;
wire d_ipd;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
buf (d_ipd, d);
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
assign enable = (!aclr_ipd) && (ena_ipd);
specify
$setuphold (posedge clk &&& enable, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& enable, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge aclr => (q +: 1'b0)) = 0 ;
endspecify
initial
begin
clk_last_value <= 'b0;
q_tmp <= 'b0;
end
always @ (clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
q_tmp <= 'bX;
end
else
begin
if (aclr_ipd == 1'b1)
q_tmp <= 0;
else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd == 1'b1)
q_tmp <= d_ipd;
end
clk_last_value <= clk_ipd;
end
and (q, q_tmp, 'b1);
endmodule // cycloneiii_mac_sign_reg
//------------------------------------------------------------------
//
// Module Name : cycloneiii_mac_mult_internal
//
// Description : Cyclone II MAC_MULT_INTERNAL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_mac_mult_internal
(
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
// OUTPUT
output [dataout_width-1:0] dataout;
// Internal variables
wire [17:0] dataa_ipd;
wire [17:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire [dataout_width-1:0] dataout_tmp;
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
reg [17:0] i_ones; // padding with 1's for input negation
// Input buffers
buf (signa_ipd, signa);
buf (signb_ipd, signb);
buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// get signs of a and b, and get absolute values since Verilog '*' operator
// is an unsigned multiplication
assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
// multiply a * b
assign iabsresult = iabsa * iabsb;
assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_mac_mult
//
// Description : Cyclone II MAC_MULT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiii_mac_mult";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataout_width-1:0] dataout_tmp;
wire [17:0] idataa_reg; // optional register for dataa input
wire [17:0] idatab_reg; // optional register for datab input
wire [17:0] dataa_pad; // padded dataa input
wire [17:0] datab_pad; // padded datab input
wire isigna_reg; // optional register for signa input
wire isignb_reg; // optional register for signb input
wire [17:0] idataa_int; // dataa as seen by the multiplier input
wire [17:0] idatab_int; // datab as seen by the multiplier input
wire isigna_int; // signa as seen by the multiplier input
wire isignb_int; // signb as seen by the multiplier input
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
wire dataa_use_reg; // equivalent to dataa_clock parameter
wire datab_use_reg; // equivalent to datab_clock parameter
wire signa_use_reg; // equivalent to signa_clock parameter
wire signb_use_reg; // equivalent to signb_clock parameter
reg [17:0] i_ones; // padding with 1's for input negation
wire reg_aclr;
assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
// optional registering parameters
assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// Optional input registers for dataa,b and signa,b
cycloneiii_mac_data_reg dataa_reg (
.clk(clk),
.data(dataa_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idataa_reg)
);
defparam dataa_reg.data_width = dataa_width;
cycloneiii_mac_data_reg datab_reg (
.clk(clk),
.data(datab_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idatab_reg)
);
defparam datab_reg.data_width = datab_width;
cycloneiii_mac_sign_reg signa_reg (
.clk(clk),
.d(signa),
.ena(ena),
.aclr(reg_aclr),
.q(isigna_reg)
);
cycloneiii_mac_sign_reg signb_reg (
.clk(clk),
.d(signb),
.ena(ena),
.aclr(reg_aclr),
.q(isignb_reg)
);
// mux input sources from direct inputs or optional registers
assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
cycloneiii_mac_mult_internal mac_multiply (
.dataa(idataa_int[dataa_width-1:0]),
.datab(idatab_int[datab_width-1:0]),
.signa(isigna_int),
.signb(isignb_int),
.dataout(dataout)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = dataout_width;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_mac_out
//
// Description : Cyclone II MAC_OUT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_mac_out
(
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiii_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataa_width-1:0] dataa_ipd; // internal dataa
wire clk_ipd; // internal clk
wire aclr_ipd; // internal aclr
wire ena_ipd; // internal ena
// internal variable
wire [dataout_width-1:0] dataout_tmp;
reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
wire use_reg; // equivalent to dataout_clock parameter
wire enable;
wire no_aclr;
// Input buffers
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
// optional registering parameter
assign use_reg = (output_clock != "none") ? 1 : 0;
assign enable = (!aclr) && (ena) && use_reg;
assign no_aclr = (!aclr) && use_reg;
specify
if (use_reg)
(posedge clk => (dataout +: dataout_tmp)) = 0;
(posedge aclr => (dataout +: 1'b0)) = 0;
ifnone
(dataa *> dataout) = (0, 0);
$setuphold (posedge clk &&& enable, dataa, 0, 0);
$setuphold (posedge clk &&& no_aclr, ena, 0, 0);
endspecify
initial
begin
// initial values for optional register
idataout_reg = 0;
end
// Optional input registers for dataa,b and signa,b
always @ (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
begin
idataout_reg <= 0;
end
else if (ena_ipd == 1)
begin
idataout_reg <= dataa_ipd;
end
end
// mux input sources from direct inputs or optional registers
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
// accelerate outputs
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiii_io_ibuf //
//Description: Simulation model for Cyclone III IO Input Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
// Deactivate the following LEDA rules for cycloneiii_io_atom.v
// G_521_3B: Use uppercase letters for all parameter names
// B_3416: Use blocking assignments in combinatorial block
// B_3417: Use non-blocking assignments in sequential block
// B_3418: Redundant signal in sensitivity list
// B_3419: Missing signal in sensitivity list
// leda G_521_3_B off
// leda B_3416 off
// leda B_3417 off
// leda B_3418 off
// leda B_3419 off
module cycloneiii_io_ibuf (
i,
ibar,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cycloneiii_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val ;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial
begin
prev_value = 1'b0;
end
always@(i or ibar)
begin
if(differential_mode == "false")
begin
if(i == 1'b1)
begin
o_tmp = 1'b1;
prev_value = 1'b1;
end
else if(i == 1'b0)
begin
o_tmp = 1'b0;
prev_value = 1'b0;
end
else if( i === 1'bz)
o_tmp = out_val;
else
o_tmp = i;
if( bus_hold == "true")
out_tmp = prev_value;
else
out_tmp = o_tmp;
end
else
begin
case({i,ibar})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiii_io_obuf //
//Description: Simulation model for Cyclone III IO Output Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiii_io_obuf (
i,
oe,
seriesterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter lpm_type = "cycloneiii_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input [15:0] seriesterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
tri1 oe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
out_tmp = 'bz;
end
always@(i or oe)
begin
if(oe == 1'b1)
begin
if(open_drain_output == "true")
begin
if(i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end
else
begin
if( i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else if( i == 'b1)
begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end
else
begin
out_tmp = i;
out_tmp_bar = i;
end
end
end
else if(oe == 1'b0)
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
else
begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = (devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar = (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiii_ddio_out //
//Description: Simulation model for Cyclone III DDIO Output //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiii_ddio_out (
datainlo,
datainhi,
clk,
clkhi,
clklo,
muxsel,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter use_new_clocking_model = "false";
parameter lpm_type = "cycloneiii_ddio_out";
//Input Ports Declaration
input datainlo;
input datainhi;
input clk;
input clkhi;
input clklo;
input muxsel;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi ;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg ddioreg_prn;
reg viol_notifier;
wire dfflo_tmp;
wire dffhi_tmp;
wire mux_sel;
wire sel_mux_hi_in;
wire clk_hi;
wire clk_lo;
wire datainlo_tmp;
wire datainhi_tmp;
reg dinhi_tmp;
reg dinlo_tmp;
reg clk1;
reg clk2;
reg muxsel1;
reg muxsel2;
reg muxsel_tmp;
reg sel_mux_lo_in_tmp;
reg sel_mux_hi_in_tmp;
reg dffhi_tmp1;
wire muxsel3;
wire clk3;
wire sel_mux_lo_in;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = (sync_mode == "preset") ? 1'b1: 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
always@(clk)
begin
clk1 = clk;
clk2 <= clk1;
end
always@(muxsel)
begin
muxsel1 = muxsel;
muxsel2 <= muxsel1;
end
always@(dfflo_tmp)
begin
sel_mux_lo_in_tmp <= dfflo_tmp;
end
always@(datainlo)
begin
dinlo_tmp <= datainlo;
end
always@(datainhi)
begin
dinhi_tmp <= datainhi;
end
always @(mux_sel) begin
muxsel_tmp <= mux_sel;
end
always@(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end
always@(dffhi_tmp1)
begin
sel_mux_hi_in_tmp <= dffhi_tmp1;
end
always@(areset)
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
end
else if(async_mode == "preset")
begin
ddioreg_prn = !areset;
end
end
always@(sreset )
begin
if(sync_mode == "clear")
begin
ddioreg_sclr = sreset;
end
else if(sync_mode == "preset")
begin
ddioreg_sload = sreset;
end
end
//DDIO HIGH Register
cycloneiii_latch ddioreg_hi(
.D(datainhi_tmp),
.ENA(!clk_hi & ena),
.PRE(ddioreg_prn),
.CLR(ddioreg_aclr),
.Q(dffhi_tmp)
);
assign clk_hi = (use_new_clocking_model == "true") ? clkhi : clk;
assign datainhi_tmp = (ddioreg_sclr == 1'b0 && ddioreg_sload == 1'b1)? 1'b1 : (ddioreg_sclr == 1'b1 && ddioreg_sload == 1'b0)? 1'b0: dinhi_tmp;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datainlo_tmp),
.clk(clk_lo),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
assign clk_lo = (use_new_clocking_model == "true") ? clklo : clk;
assign datainlo_tmp = dinlo_tmp;
//DDIO High Register
wire bdataout;
cycloneiii_routing_wire wire_delay (
.datain(bdataout),
.dataout(dataout)
);
//registered output selection
cycloneiii_mux21 sel_mux(
.MO(bdataout),
.A(sel_mux_hi_in),
.B(sel_mux_lo_in),
.S(!muxsel_tmp)
);
assign muxsel3 = muxsel2;
assign clk3 = clk2;
assign mux_sel = (use_new_clocking_model == "true")? muxsel3 : clk3;
assign sel_mux_lo_in = sel_mux_lo_in_tmp;
assign sel_mux_hi_in = sel_mux_hi_in_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiii_ddio_oe //
//Description: Simulation model for Cyclone III DDIO OE //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiii_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneiii_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi(
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
cycloneiii_mux21 or_gate(
.MO(dataout),
.A(dffhi_tmp),
.B(dfflo_tmp),
.S(dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule
// Re-activate the following LEDA rules
// leda G_521_3_B off
// leda B_3416 off
// leda B_3417 off
// leda B_3418 off
// leda B_3419 off
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiii_pseudo_diff_out //
//Description: Simulation model for Cyclone III Pseudo Differential //
// Output Buffer //
//////////////////////////////////////////////////////////////////////////////////
// Deactivate the following LEDA rules for cycloneiii_pseudo_diff_atom.v
// G_521_3B: Use uppercase letters for all parameter names
// leda G_521_3_B off
module cycloneiii_pseudo_diff_out(
i,
o,
obar
);
parameter lpm_type = "cycloneiii_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always@(i)
begin
if( i == 1'b1)
begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end
else if( i == 1'b0)
begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end
else
begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
// Re-activate the LEDA rules
// leda G_521_3_B on
//--------------------------------------------------------------------------
// Module Name : cycloneiii_io_pad
// Description : Simulation model for cycloneiii IO pad
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_io_pad (
padin,
padout
);
parameter lpm_type = "cycloneiii_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout;//Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_ipd,padin);
assign padout_opd = padin_ipd;
//OUTPUT BUFFER INSERTION FOR VERILOG-XL
buf padout_buf (padout, padout_opd);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneiii_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk_in;
end
always @ (clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_last_value === 'b0) & (clk_in === 1'b1) & (ena == 1'b1))
q_tmp <= d_in;
clk_last_value = clk_in;
end
and (q, q_tmp, 'b1);
endmodule // cycloneiii_ena_reg
//------------------------------------------------------------------
//
// Module Name : cycloneiii_clkctrl
//
// Description : Cycloneiii CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
tri1 devclrn;
tri1 devpor;
parameter clock_type = "auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "cycloneiii_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg1_out; // output of ENA register1
wire cereg2_out; // output of ENA register2
wire ena_out; // choice of registered ENA or none.
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
specify
(inclk *> outclk) = (0, 0) ;
endspecify
cycloneiii_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
cycloneiii_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg1_out)
);
cycloneiii_ena_reg extena1_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(cereg1_out),
.clrn(1'b1),
.prn(devpor),
.q(cereg2_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg1_out :
((ena_register_mode == "none") ? ena_ipd : cereg2_out);
and (outclk, ena_out, clkmux_out);
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIII RUBLOCK ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiii_rublock
(
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter lpm_type = "cycloneiii_rublock";
input clk;
input shiftnld;
input captnupdt;
input regin;
input rsttimer;
input rconfig;
output regout;
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIII_APFCONTROLLER ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiii_apfcontroller
(
usermode,
nceout
);
parameter lpm_type = "cycloneiii_apfcontroller";
output usermode;
output nceout;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_termination_ctrl_sub
//
// Description : Cyclone III Termination Ctrl Sub-block
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_termination_ctrl (
clkusr,
intosc,
nclrusr,
nfrzdrv,
rclkdiv,
rclrusrinv,
rdivsel,
roctusr,
rsellvrefdn,
rsellvrefup,
rtest,
vccnx,
vssn,
clken,
clkin,
maskbit,
nclr,
noctdoneuser,
octdone,
oregclk,
oregnclr,
vref,
vrefh,
vrefl);
input clkusr;
input intosc; // clk source in powerup mode
input nclrusr;
input nfrzdrv; // devclrn
input rclkdiv; // - 14
input rclrusrinv; // invert nclrusr signal - 13
input rdivsel; // 0 = /32; 1 = /4; - 16
input roctusr; // run_time_control - 15
input rsellvrefdn; // shift_vref_rdn - 26
input rsellvrefup; // shift_vref_rup - 25
input rtest; // test_mode - 2
input vccnx; // VCC voltage src
input vssn; // GND voltage src
output clken;
output clkin;
output [8:0] maskbit;
output nclr;
output noctdoneuser;
output octdone;
output oregclk;
output oregnclr;
output vref;
output vrefh;
output vrefl;
parameter REG_TCO_DLY = 0; // 1;
reg divby2;
reg divby4;
reg divby8;
reg divby16;
reg divby32;
reg oregclk;
reg oregclkclk;
reg intosc_div4;
reg intosc_div32;
reg clken;
reg octdoneuser;
reg startbit;
reg [8:0] maskbit;
reg octdone;
wire [8:0] maskbit_d;
wire intoscin;
wire clk_sel;
wire intosc_clk;
wire clkin;
wire oregnclr;
wire clr_invert;
wire nclr;
wire adcclk;
// data flow in user mode:
// oregnclr = 1 forever so clkin is clkusr
//
// deasserting nclrusr starts off USER calibration
// upon rising edge of nclrusr
// (1). at 1st neg edge of clkin, clken = 1
// (2). enable adcclk
// (3). Mask bits [8:0] shifts from MSB=1 into LSB=1
// (4). oregclkclk = bit[0] (=1); 7th cycle
// (5). oregclk = 1 (after falling edge of oregclkclk) 8th cycle
// (6). clken = 0 (!oregclk)
// (7). octdoneuser = 1 (falling edge of clken)
initial
begin
octdone = 1'b1; // from powerup stage
octdoneuser = 1'b0;
startbit = 1'b0;
maskbit = 9'b000000000;
oregclk = 1'b0;
oregclkclk = 1'b0;
clken = 1'b0;
divby2 = 1'b0;
divby4 = 1'b0;
divby8 = 1'b0;
divby16 = 1'b0;
divby32 = 1'b0;
intosc_div4 = 1'b0;
intosc_div32 = 1'b0;
end
assign noctdoneuser = ~octdoneuser;
// c7216 clkdiv
always @(posedge intosc or negedge nfrzdrv) begin
if (!nfrzdrv) divby2 <= #(REG_TCO_DLY) 1'b0;
else divby2 <= #(REG_TCO_DLY) ~divby2;
end
always @(posedge divby2 or negedge nfrzdrv) begin
if (!nfrzdrv) divby4 <= #(REG_TCO_DLY) 1'b0;
else divby4 <= #(REG_TCO_DLY) ~divby4;
end
always @(posedge divby4 or negedge nfrzdrv) begin
if (!nfrzdrv) divby8 <= #(REG_TCO_DLY) 1'b0;
else divby8 <= #(REG_TCO_DLY) ~divby8;
end
always @(posedge divby8 or negedge nfrzdrv) begin
if (!nfrzdrv) divby16 <= #(REG_TCO_DLY) 1'b0;
else divby16 <= #(REG_TCO_DLY) ~divby16;
end
always @(posedge divby16 or negedge nfrzdrv) begin
if (!nfrzdrv) divby32 <= #(REG_TCO_DLY) 1'b0;
else divby32 <= #(REG_TCO_DLY) ~divby32;
end
assign intoscin = rdivsel ? divby4 : divby32;
assign clk_sel = octdone & roctusr; // always 1
assign intosc_clk = rclkdiv ? intoscin : intosc;
assign clkin = clk_sel ? clkusr : intosc_clk;
assign oregnclr = rtest | nfrzdrv; // always 1
assign clr_invert = rclrusrinv ? ~nclrusr : nclrusr;
assign nclr = clk_sel ? clr_invert : nfrzdrv;
// c7206
always @(negedge clkin or negedge nclr) begin
if (!nclr) clken <= #(REG_TCO_DLY) 1'b0;
else clken <= #(REG_TCO_DLY) ~oregclk;
end
always @(negedge clken or negedge oregnclr) begin
if (!oregnclr) octdone <= #(REG_TCO_DLY) 1'b0;
else octdone <= #(REG_TCO_DLY) 1'b1;
end
assign adcclk = clkin & clken;
always @(posedge adcclk or negedge nclr) begin
if (!nclr)
startbit <= #(REG_TCO_DLY) 1'b0;
else
startbit <= #(REG_TCO_DLY) 1'b1;
end
assign maskbit_d = {~startbit, maskbit[8:1]};
always @(posedge adcclk or negedge nclr) begin
if (!nclr) begin
maskbit <= #(REG_TCO_DLY) 9'b0;
oregclkclk <= #(REG_TCO_DLY) 1'b0;
end
else begin
maskbit <= #(REG_TCO_DLY) maskbit_d;
oregclkclk <= #(REG_TCO_DLY) maskbit[0];
end
end
always @(negedge oregclkclk or negedge nclr) begin
if (~nclr) oregclk <= #(REG_TCO_DLY) 1'b0;
else oregclk <= #(REG_TCO_DLY) 1'b1;
end
always @(negedge clken or negedge nclr) begin
if (~nclr) octdoneuser <= #(REG_TCO_DLY) 1'b0;
else octdoneuser <= #(REG_TCO_DLY) 1'b1;
end
// OCT VREF c7207 xvref (
// Functional code
assign vrefh = 1'b1;
assign vref = 1'b1;
assign vrefl = 1'b0;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_termination_ctrl_sub
//
// Description : Cyclone III Termination Ctrl Sub-block
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_termination_rupdn (
clken,
clkin,
compout,
maskbit,
nclr,
octcal,
octpin,
octrpcd,
oregclk,
oregnclr,
radd,
rcompoutinv,
roctdone,
rpwrdn,
rshift,
rshiftvref,
rtest,
shiftedvref,
vccnx,
vref
);
input clken;
input clkin;
input [8:0] maskbit;
input nclr;
input octpin;
input oregclk;
input oregnclr;
input [7:0] radd;
input rcompoutinv;
input roctdone;
input rpwrdn;
input rshift;
input rshiftvref;
input rtest;
input shiftedvref;
input vccnx;
input vref;
output compout;
output [7:0] octcal; // to IO bank
output [7:0] octrpcd; // to the reference RUP/RDN
parameter is_rdn = "false";// initial value of octcal differ
parameter OCTCAL_DLY = 0; // 1;
parameter REG_TCO_DLY = 0; // 1;
//supply0 vss;
reg [7:0] comp_octrpcd;
reg [7:0] octcal_reg;
wire octref;
wire shftref_out;
wire compout_tmp;
wire nout;
wire nbias;
wire pbias;
wire [7:0] octrpcd;
wire [7:0] octcal_reg_in;
wire [7:0] reg_clk;
wire [7:0] srpcd;
wire [7:0] rpcdi;
wire [8:0] rpcdi_temp;
wire shift;
wire shftvrefhv;
wire compout;
wire clr;
wire reg_clkin;
wire reg_nclr;
wire shiftvref;
wire compadcen;
assign shift = rtest & ~clken;
assign compadcen = ~roctdone & clken;
assign shiftvref = ~(rshiftvref | maskbit[1]);
//c6419 xinverted_ls (
//vss, shiftvref, shftvrefhv, vccnx );
//c7223 xbias_ckt (
assign nbias = (compadcen === 1'b1) ? 1'b1 : 1'b0;
assign pbias = (compadcen === 1'b1) ? 1'b0 : 1'bz;
//c7202 xoct_comp (
assign compout_tmp = (compadcen === 1'b1) ? octpin : 1'b0;
assign shftvrefhv = shftref_out;
assign octref = shftvrefhv ? shiftedvref : vref;
assign compout = rcompoutinv ? compout_tmp : ~compout_tmp;
// c7208
assign reg_clk[7:0] = maskbit[7:0];
assign reg_nclr = (compadcen | ~rpwrdn) & nclr;
always @(posedge reg_clk[7] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[7] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[7] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[6] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[6] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[6] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[5] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[5] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[5] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[4] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[4] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[4] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[3] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[3] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[3] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[2] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[2] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[2] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[1] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[1] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[1] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[0] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[0] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[0] <= #(REG_TCO_DLY) compout;
end
// output sends to RUP/DN reference pins
assign octrpcd[7] = maskbit[8] ? 1'b1 : comp_octrpcd[7];
assign octrpcd[6] = maskbit[7] ? 1'b1 : comp_octrpcd[6];
// below: set octrpcd[5] and clear prior bit octrpcd[6] based on compout
assign octrpcd[5] = maskbit[6] ? 1'b1 : comp_octrpcd[5];
assign octrpcd[4] = maskbit[5] ? 1'b1 : comp_octrpcd[4];
assign octrpcd[3] = maskbit[4] ? 1'b1 : comp_octrpcd[3];
assign octrpcd[2] = maskbit[3] ? 1'b1 : comp_octrpcd[2];
assign octrpcd[1] = maskbit[2] ? 1'b1 : comp_octrpcd[1];
assign octrpcd[0] = maskbit[1] ? 1'b1 : comp_octrpcd[0];
// c7210 - leftshift
assign srpcd = rshift ? {octrpcd[6:0], 1'b0} : octrpcd;
// c7214 - Adder:
// overflow => max value 8'b1
// underflow => 0;
assign rpcdi_temp[8:0] = srpcd[7:0] + radd[7:0];
assign rpcdi[7:0] = {8{(~radd[7] & rpcdi_temp[8])}} | rpcdi_temp[7:0];
// left shift rotation in test mode - only when calibration is done (clken=0)
// calibration code (octcal) is 0 until calibration completed
// oregclk indicates 10th cycle since masket[8]=1 --> masket[0]=1 + one cycle
// clken is ~oregclk
assign reg_clkin = ~shift ? oregclk : clkin;
assign octcal_reg_in[7:0] = ~shift ? rpcdi[7:0] : ({octcal[6:0], octcal[7]});
initial begin
if (is_rdn == "true")
octcal_reg[7:0] = 8'hFF;
else
octcal_reg[7:0] = 8'h00;
end
// calibrated code cannot be cleared by user_clr
// it is only changed by code from calibration block which is
always @(posedge reg_clkin or negedge oregnclr) begin
if (!oregnclr) octcal_reg[7:0] <= #(REG_TCO_DLY) 8'h00;
else octcal_reg[7:0] <= #(REG_TCO_DLY) octcal_reg_in[7:0];
end
assign #(OCTCAL_DLY) octcal = octcal_reg;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiii_termination
//
// Description : Cyclone III Termination Atom Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_termination (
rup,
rdn,
terminationclock,
terminationclear,
devpor,
devclrn,
comparatorprobe,
terminationcontrolprobe,
calibrationdone,
terminationcontrol);
input rup;
input rdn;
input terminationclock;
input terminationclear;
input devpor;
input devclrn;
output comparatorprobe;
output terminationcontrolprobe;
output calibrationdone;
output [15:0] terminationcontrol;
parameter pullup_control_to_core = "false";
parameter power_down = "true";
parameter test_mode = "false";
parameter left_shift_termination_code = "false";
parameter pullup_adder = 0; // -128, 127
parameter pulldown_adder = 0; // -128, 127
parameter clock_divide_by = 32; // 1, 4, 32
parameter runtime_control = "false";
parameter shift_vref_rup = "true";
parameter shift_vref_rdn = "true";
parameter shifted_vref_control = "true";
parameter lpm_type = "cycloneiii_termination";
tri1 devclrn;
tri1 devpor;
wire m_gnd;
wire m_vcc;
// interconnecting wires
// ctrl -----------------------------------------
wire xcbout_clken;
wire xcbout_clkin;
wire [8:0] xcbout_maskbit;
wire xcbout_nclr;
wire xcbout_noctdoneuser;
wire xcbout_octdone;
wire xcbout_oregclk;
wire xcbout_oregnclr;
wire xcbout_vref; // to run/dn comparator
wire xcbout_vrefh; // to rdn - shfitedvref
wire xcbout_vrefl; // to rup - shiftedvref
wire xcbin_clkusr;
wire xcbin_intosc; // clk source in powerup mode
wire xcbin_nclrusr;
wire xcbin_nfrzdrv; // devclrn
wire xcbin_rclkdiv; // - 14
wire xcbin_rclrusrinv; // invert nclrusr signal - 13
wire xcbin_rdivsel; // 0 = /32; 1 = /4; - 16
wire xcbin_roctusr; // run_time_control - 15
wire xcbin_rsellvrefdn; // shift_vref_rdn - 26
wire xcbin_rsellvrefup; // shift_vref_rup - 25
wire xcbin_rtest; // test_mode - 2
wire xcbin_vccnx; // VCC voltage src
wire xcbin_vssn; // GND voltage src
// rup and rdn ------------------------------------
// common
wire rshift_in;
wire rpwrdn_in;
wire rup_compout;
wire [7:0] rup_octrupn; // out from XRUP to rupref pin
wire [7:0] rup_octcalnout; // to the I/O bank
wire rupin;
reg [7:0] rup_radd;
wire rdn_compout;
wire [7:0] rdn_octrdnp; // out from XRDN to rdnref pin
wire [7:0] rdn_octcalpout; // to the I/O bank
wire rdnin;
reg [7:0] rdn_radd;
wire calout; // MSB of the calibration code
// primary input and outputs
assign rupin = rup;
assign rdnin = rdn;
// terminationclk and clear feeding into CTRL sub directly
assign calibrationdone = xcbout_octdone;
assign terminationcontrol = {rup_octcalnout, rdn_octcalpout};
assign comparatorprobe = (pullup_control_to_core == "true") ? rup_compout : rdn_compout;
assign calout = (pullup_control_to_core == "true") ? rup_octcalnout[7] : rdn_octcalpout[7];
assign terminationcontrolprobe = (test_mode == "true") ? calout : xcbout_noctdoneuser;
initial begin
rup_radd = pullup_adder;
rdn_radd = pulldown_adder;
end
// CTRL sub-block
assign xcbin_clkusr = terminationclock;
assign xcbin_intosc = 1'b0; // clk source in powerup mode
assign xcbin_nclrusr = (terminationclear === 1'b1) ? 1'b0 : 1'b1;
assign xcbin_nfrzdrv = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign xcbin_vccnx = 1'b1; // VCC voltage src
assign xcbin_vssn = 1'b0; // GND voltage src
assign xcbin_rclkdiv = (clock_divide_by != 1) ? 1'b1 : 1'b0; //- 14
assign xcbin_rclrusrinv = 1'b0; // invert nclrusr signal - 13
assign xcbin_rdivsel = (clock_divide_by == 32) ? 1'b0 : 1'b1; //- 16
assign xcbin_roctusr = (runtime_control == "true") ? 1'b1 : 1'b0; //- 15
assign xcbin_rsellvrefdn = (shift_vref_rdn == "true") ? 1'b1 : 1'b0; //- 26
assign xcbin_rsellvrefup = (shift_vref_rup == "true") ? 1'b1 : 1'b0; //- 25
assign xcbin_rtest = (test_mode == "true") ? 1'b1 : 1'b0; // - 2
cycloneiii_termination_ctrl m_ctrl (
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.noctdoneuser (xcbout_noctdoneuser ),
.octdone (xcbout_octdone ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr ),
.vref (xcbout_vref ),
.vrefh (xcbout_vrefh ),
.vrefl (xcbout_vrefl ),
.clkusr (xcbin_clkusr ),
.intosc (xcbin_intosc ),
.nclrusr (xcbin_nclrusr ),
.nfrzdrv (xcbin_nfrzdrv ),
.vccnx (xcbin_vccnx ),
.vssn (xcbin_vssn ),
.rclkdiv (xcbin_rclkdiv ),
.rclrusrinv (xcbin_rclrusrinv ),
.rdivsel (xcbin_rdivsel ),
.roctusr (xcbin_roctusr ),
.rsellvrefdn (xcbin_rsellvrefdn ),
.rsellvrefup (xcbin_rsellvrefup ),
.rtest (xcbin_rtest )
);
assign m_vcc = 1'b1;
assign m_gnd = 1'b0;
assign rshift_in = (left_shift_termination_code == "true") ? 1'b1 : 1'b0;
assign rpwrdn_in = (power_down == "true") ? 1'b1 : 1'b0;
cycloneiii_termination_rupdn m_rup (
.compout (rup_compout ),
.octrpcd (rup_octrupn ),
.octcal (rup_octcalnout ),
.octpin (rupin ),
.rcompoutinv (m_vcc ), // no inversion
.radd (rup_radd ),
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr),
.shiftedvref (xcbout_vrefl ),
.vccnx (xcbin_vccnx ),
.vref (xcbout_vref ),
.roctdone (m_gnd ), // [12]
.rpwrdn (rpwrdn_in ), // [1]
.rshift (rshift_in ), // [3]
.rshiftvref (m_vcc ), // [27]
.rtest (xcbin_rtest )
);
defparam m_rup.is_rdn = "false";
cycloneiii_termination_rupdn m_rdn (
.compout (rdn_compout ),
.octrpcd (rdn_octrdnp ),
.octcal (rdn_octcalpout ),
.octpin (rdnin ),
.rcompoutinv (m_gnd ), // invert compout
.radd (rdn_radd ),
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr),
.shiftedvref (xcbout_vrefh ),
.vccnx (xcbin_vccnx ),
.vref (xcbout_vref ),
.roctdone (m_gnd ), // [12]
.rpwrdn (rpwrdn_in ), // [1]
.rshift (rshift_in ), // [3]
.rshiftvref (m_vcc ), // [27]
.rtest (xcbin_rtest )
);
defparam m_rdn.is_rdn = "true";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneiii_jtag
//
// Description : Cyclone III JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_jtag (
tms,
tck,
tdi,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "cycloneiii_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneiii_crcblock
//
// Description : Cyclone III CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiii_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneiii_crcblock";
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIII OSCILLATOR ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiii_oscillator
(
oscena,
clkout
);
parameter lpm_type = "cycloneiii_oscillator";
input oscena;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
// LOCAL_PARAMETERS_END
// INTERNAL wire
reg int_osc; // internal oscillator
specify
(posedge oscena => (clkout +: 1'b1)) = (0, 0);
endspecify
initial
int_osc = 1'b0;
always @(int_osc or oscena)
begin
if (oscena == 1'b1)
int_osc <= #OSC_PW ~int_osc;
end
and (clkout, int_osc, 1'b1);
endmodule
`ifdef MODEL_TECH
`mti_v2k_int_delays_off
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V |
module foo
(/*AUTOARG*/
// Outputs
aa
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
// End of automatics
// Check that if aa is connected differently in a input, it doesn't make conflicts.
autoinst_signed_fubar2 inst
(
// Outputs
.an_output2 (hi.ear.ial),
.another_output2 (aa[FOO:0]),
// Inputs
.an_input2 (an_input2[1:0])
/*AUTOINST*/);
autoinst_signed_fubar2 instx
(
// Outputs
.an_output2 (hi.ear.ial),
// Inputs
.an_input2 (an_input2[1:0]),
.another_output2 (aa[Y:X]),
/*AUTOINST*/);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_oen,
linear_flash_wen,
linear_flash_dq_io,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
rx_ref_clk_0_p,
rx_ref_clk_0_n,
rx_data_0_p,
rx_data_0_n,
rx_ref_clk_1_p,
rx_ref_clk_1_n,
rx_data_1_p,
rx_data_1_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_0_p,
rx_sync_0_n,
rx_sync_1_p,
rx_sync_1_n,
spi_csn_0,
spi_csn_1,
spi_clk,
spi_sdio,
spi_dirn,
trig_p,
trig_n,
vdither_p,
vdither_n,
pwr_good,
dac_clk,
dac_data,
dac_sync_0,
dac_sync_1,
fd_1,
irq_1,
fd_0,
irq_0,
pwdn_1,
rst_1,
drst_1,
arst_1,
pwdn_0,
rst_0,
drst_0,
arst_0);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [ 13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
output linear_flash_oen;
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
inout [ 6:0] gpio_lcd;
inout [ 20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_0_p;
input rx_ref_clk_0_n;
input [ 7:0] rx_data_0_p;
input [ 7:0] rx_data_0_n;
input rx_ref_clk_1_p;
input rx_ref_clk_1_n;
input [ 7:0] rx_data_1_p;
input [ 7:0] rx_data_1_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_0_p;
output rx_sync_0_n;
output rx_sync_1_p;
output rx_sync_1_n;
output spi_csn_0;
output spi_csn_1;
output spi_clk;
inout spi_sdio;
output spi_dirn;
output dac_clk;
output dac_data;
output dac_sync_0;
output dac_sync_1;
input trig_p;
input trig_n;
output vdither_p;
output vdither_n;
inout pwr_good;
inout fd_1;
inout irq_1;
inout fd_0;
inout irq_0;
inout pwdn_1;
inout rst_1;
inout drst_1;
inout arst_1;
inout pwdn_0;
inout rst_0;
inout drst_0;
inout arst_0;
// internal registers
reg adc_wr = 'd0;
reg [511:0] adc_wdata = 'd0;
// internal signals
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire rx_ref_clk_0;
wire rx_ref_clk_1;
wire rx_sysref;
wire rx_sync_0;
wire rx_sync_1;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [255:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [255:0] adc_data_1;
// interleaving
always @(posedge adc_clk) begin
adc_wr <= adc_enable_0 & adc_enable_1;
adc_wdata[((16*31)+15):(16*31)] <= adc_data_1[((16*15)+15):(16*15)];
adc_wdata[((16*30)+15):(16*30)] <= adc_data_0[((16*15)+15):(16*15)];
adc_wdata[((16*29)+15):(16*29)] <= adc_data_1[((16*14)+15):(16*14)];
adc_wdata[((16*28)+15):(16*28)] <= adc_data_0[((16*14)+15):(16*14)];
adc_wdata[((16*27)+15):(16*27)] <= adc_data_1[((16*13)+15):(16*13)];
adc_wdata[((16*26)+15):(16*26)] <= adc_data_0[((16*13)+15):(16*13)];
adc_wdata[((16*25)+15):(16*25)] <= adc_data_1[((16*12)+15):(16*12)];
adc_wdata[((16*24)+15):(16*24)] <= adc_data_0[((16*12)+15):(16*12)];
adc_wdata[((16*23)+15):(16*23)] <= adc_data_1[((16*11)+15):(16*11)];
adc_wdata[((16*22)+15):(16*22)] <= adc_data_0[((16*11)+15):(16*11)];
adc_wdata[((16*21)+15):(16*21)] <= adc_data_1[((16*10)+15):(16*10)];
adc_wdata[((16*20)+15):(16*20)] <= adc_data_0[((16*10)+15):(16*10)];
adc_wdata[((16*19)+15):(16*19)] <= adc_data_1[((16* 9)+15):(16* 9)];
adc_wdata[((16*18)+15):(16*18)] <= adc_data_0[((16* 9)+15):(16* 9)];
adc_wdata[((16*17)+15):(16*17)] <= adc_data_1[((16* 8)+15):(16* 8)];
adc_wdata[((16*16)+15):(16*16)] <= adc_data_0[((16* 8)+15):(16* 8)];
adc_wdata[((16*15)+15):(16*15)] <= adc_data_1[((16* 7)+15):(16* 7)];
adc_wdata[((16*14)+15):(16*14)] <= adc_data_0[((16* 7)+15):(16* 7)];
adc_wdata[((16*13)+15):(16*13)] <= adc_data_1[((16* 6)+15):(16* 6)];
adc_wdata[((16*12)+15):(16*12)] <= adc_data_0[((16* 6)+15):(16* 6)];
adc_wdata[((16*11)+15):(16*11)] <= adc_data_1[((16* 5)+15):(16* 5)];
adc_wdata[((16*10)+15):(16*10)] <= adc_data_0[((16* 5)+15):(16* 5)];
adc_wdata[((16* 9)+15):(16* 9)] <= adc_data_1[((16* 4)+15):(16* 4)];
adc_wdata[((16* 8)+15):(16* 8)] <= adc_data_0[((16* 4)+15):(16* 4)];
adc_wdata[((16* 7)+15):(16* 7)] <= adc_data_1[((16* 3)+15):(16* 3)];
adc_wdata[((16* 6)+15):(16* 6)] <= adc_data_0[((16* 3)+15):(16* 3)];
adc_wdata[((16* 5)+15):(16* 5)] <= adc_data_1[((16* 2)+15):(16* 2)];
adc_wdata[((16* 4)+15):(16* 4)] <= adc_data_0[((16* 2)+15):(16* 2)];
adc_wdata[((16* 3)+15):(16* 3)] <= adc_data_1[((16* 1)+15):(16* 1)];
adc_wdata[((16* 2)+15):(16* 2)] <= adc_data_0[((16* 1)+15):(16* 1)];
adc_wdata[((16* 1)+15):(16* 1)] <= adc_data_1[((16* 0)+15):(16* 0)];
adc_wdata[((16* 0)+15):(16* 0)] <= adc_data_0[((16* 0)+15):(16* 0)];
end
// spi
assign iic_rstn = 1'b1;
assign fan_pwm = 1'b1;
assign dac_clk = spi_clk;
assign dac_data = spi_mosi;
assign dac_sync_1 = spi_csn[3];
assign dac_sync_0 = spi_csn[2];
assign spi_csn_1 = spi_csn[1];
assign spi_csn_0 = spi_csn[0];
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk_0 (
.CEB (1'd0),
.I (rx_ref_clk_0_p),
.IB (rx_ref_clk_0_n),
.O (rx_ref_clk_0),
.ODIV2 ());
IBUFDS_GTE2 i_ibufds_rx_ref_clk_1 (
.CEB (1'd0),
.I (rx_ref_clk_1_p),
.IB (rx_ref_clk_1_n),
.O (rx_ref_clk_1),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync_0 (
.I (rx_sync_0),
.O (rx_sync_0_p),
.OB (rx_sync_0_n));
OBUFDS i_obufds_rx_sync_1 (
.I (rx_sync_1),
.O (rx_sync_1_p),
.OB (rx_sync_1_n));
IBUFDS i_ibufds_trig (
.I (trig_p),
.IB (trig_n),
.O (gpio_i[46]));
OBUFDS i_obufds_vdither (
.I (gpio_o[45]),
.O (vdither_p),
.OB (vdither_n));
fmcadc5_spi i_fmcadc5_spi (
.spi_csn_0 (spi_csn_0),
.spi_csn_1 (spi_csn_1),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio),
.spi_dirn (spi_dirn));
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf (
.dio_t (gpio_t[44:32]),
.dio_i (gpio_o[44:32]),
.dio_o (gpio_i[44:32]),
.dio_p ({ pwr_good, // 44
fd_1, // 43
irq_1, // 42
fd_0, // 41
irq_0, // 40
pwdn_1, // 39
rst_1, // 38
drst_1, // 37
arst_1, // 36
pwdn_0, // 35
rst_0, // 34
drst_0, // 33
arst_0})); // 32
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.adc_wdata (adc_wdata),
.adc_wr (adc_wr),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io(linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_12 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.rx_data_0_n (rx_data_0_n),
.rx_data_0_p (rx_data_0_p),
.rx_data_1_n (rx_data_1_n),
.rx_data_1_p (rx_data_1_p),
.rx_ref_clk_0 (rx_ref_clk_0),
.rx_ref_clk_1 (rx_ref_clk_1),
.rx_sync_0 (rx_sync_0),
.rx_sync_1 (rx_sync_1),
.rx_sysref (rx_sysref),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (8'hff),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_4_V
`define SKY130_FD_SC_HS__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_4_V
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_sqrt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=30 ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 12.0 cbx_altfp_sqrt 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//alt_sqrt_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=30 WIDTH_SQRT=54 aclr clken clock rad root_result
//VERSION_BEGIN 12.0 cbx_altfp_sqrt 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 54 reg 2383
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sqrt_s5_double_alt_sqrt_block_odb
(
aclr,
clken,
clock,
rad,
root_result) ;
input aclr;
input clken;
input clock;
input [54:0] rad;
output [53:0] root_result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] q_ff0c;
reg [51:0] q_ff10c;
reg [51:0] q_ff12c;
reg [51:0] q_ff14c;
reg [51:0] q_ff16c;
reg [51:0] q_ff18c;
reg [51:0] q_ff20c;
reg [51:0] q_ff22c;
reg [51:0] q_ff24c;
reg [51:0] q_ff26c;
reg [51:0] q_ff28c;
reg [51:0] q_ff2c;
reg [51:0] q_ff30c;
reg [51:0] q_ff32c;
reg [51:0] q_ff34c;
reg [51:0] q_ff36c;
reg [51:0] q_ff38c;
reg [51:0] q_ff40c;
reg [51:0] q_ff42c;
reg [51:0] q_ff44c;
reg [51:0] q_ff46c;
reg [51:0] q_ff48c;
reg [51:0] q_ff4c;
reg [51:0] q_ff50c;
reg [26:0] q_ff52c;
reg [51:0] q_ff6c;
reg [51:0] q_ff8c;
reg [43:0] rad_ff11c;
reg [41:0] rad_ff13c;
reg [39:0] rad_ff15c;
reg [37:0] rad_ff17c;
reg [35:0] rad_ff19c;
reg [53:0] rad_ff1c;
reg [33:0] rad_ff21c;
reg [31:0] rad_ff23c;
reg [29:0] rad_ff25c;
reg [27:0] rad_ff27c;
reg [28:0] rad_ff29c;
reg [30:0] rad_ff31c;
reg [32:0] rad_ff33c;
reg [34:0] rad_ff35c;
reg [36:0] rad_ff37c;
reg [38:0] rad_ff39c;
reg [51:0] rad_ff3c;
reg [40:0] rad_ff41c;
reg [42:0] rad_ff43c;
reg [44:0] rad_ff45c;
reg [46:0] rad_ff47c;
reg [48:0] rad_ff49c;
reg [50:0] rad_ff51c;
reg [49:0] rad_ff5c;
reg [47:0] rad_ff7c;
reg [45:0] rad_ff9c;
wire [8:0] wire_add_sub10_result;
wire [9:0] wire_add_sub11_result;
wire [10:0] wire_add_sub12_result;
wire [11:0] wire_add_sub13_result;
wire [12:0] wire_add_sub14_result;
wire [13:0] wire_add_sub15_result;
wire [14:0] wire_add_sub16_result;
wire [15:0] wire_add_sub17_result;
wire [16:0] wire_add_sub18_result;
wire [17:0] wire_add_sub19_result;
wire [18:0] wire_add_sub20_result;
wire [19:0] wire_add_sub21_result;
wire [20:0] wire_add_sub22_result;
wire [21:0] wire_add_sub23_result;
wire [22:0] wire_add_sub24_result;
wire [23:0] wire_add_sub25_result;
wire [24:0] wire_add_sub26_result;
wire [25:0] wire_add_sub27_result;
wire [26:0] wire_add_sub28_result;
wire [27:0] wire_add_sub29_result;
wire [28:0] wire_add_sub30_result;
wire [27:0] wire_add_sub31_result;
wire [27:0] wire_add_sub32_result;
wire [28:0] wire_add_sub33_result;
wire [29:0] wire_add_sub34_result;
wire [30:0] wire_add_sub35_result;
wire [31:0] wire_add_sub36_result;
wire [32:0] wire_add_sub37_result;
wire [33:0] wire_add_sub38_result;
wire [34:0] wire_add_sub39_result;
wire [2:0] wire_add_sub4_result;
wire [35:0] wire_add_sub40_result;
wire [36:0] wire_add_sub41_result;
wire [37:0] wire_add_sub42_result;
wire [38:0] wire_add_sub43_result;
wire [39:0] wire_add_sub44_result;
wire [40:0] wire_add_sub45_result;
wire [41:0] wire_add_sub46_result;
wire [42:0] wire_add_sub47_result;
wire [43:0] wire_add_sub48_result;
wire [44:0] wire_add_sub49_result;
wire [3:0] wire_add_sub5_result;
wire [45:0] wire_add_sub50_result;
wire [46:0] wire_add_sub51_result;
wire [47:0] wire_add_sub52_result;
wire [48:0] wire_add_sub53_result;
wire [49:0] wire_add_sub54_result;
wire [50:0] wire_add_sub55_result;
wire [51:0] wire_add_sub56_result;
wire [52:0] wire_add_sub57_result;
wire [4:0] wire_add_sub6_result;
wire [5:0] wire_add_sub7_result;
wire [6:0] wire_add_sub8_result;
wire [7:0] wire_add_sub9_result;
wire [55:0] addnode_w0c;
wire [55:0] addnode_w10c;
wire [55:0] addnode_w11c;
wire [55:0] addnode_w12c;
wire [55:0] addnode_w13c;
wire [55:0] addnode_w14c;
wire [55:0] addnode_w15c;
wire [55:0] addnode_w16c;
wire [55:0] addnode_w17c;
wire [55:0] addnode_w18c;
wire [55:0] addnode_w19c;
wire [55:0] addnode_w1c;
wire [55:0] addnode_w20c;
wire [55:0] addnode_w21c;
wire [55:0] addnode_w22c;
wire [55:0] addnode_w23c;
wire [55:0] addnode_w24c;
wire [55:0] addnode_w25c;
wire [55:0] addnode_w26c;
wire [55:0] addnode_w27c;
wire [55:0] addnode_w28c;
wire [55:0] addnode_w29c;
wire [55:0] addnode_w2c;
wire [55:0] addnode_w30c;
wire [55:0] addnode_w31c;
wire [55:0] addnode_w32c;
wire [55:0] addnode_w33c;
wire [55:0] addnode_w34c;
wire [55:0] addnode_w35c;
wire [55:0] addnode_w36c;
wire [55:0] addnode_w37c;
wire [55:0] addnode_w38c;
wire [55:0] addnode_w39c;
wire [55:0] addnode_w3c;
wire [55:0] addnode_w40c;
wire [55:0] addnode_w41c;
wire [55:0] addnode_w42c;
wire [55:0] addnode_w43c;
wire [55:0] addnode_w44c;
wire [55:0] addnode_w45c;
wire [55:0] addnode_w46c;
wire [55:0] addnode_w47c;
wire [55:0] addnode_w48c;
wire [55:0] addnode_w49c;
wire [55:0] addnode_w4c;
wire [55:0] addnode_w50c;
wire [55:0] addnode_w51c;
wire [55:0] addnode_w52c;
wire [55:0] addnode_w53c;
wire [55:0] addnode_w5c;
wire [55:0] addnode_w6c;
wire [55:0] addnode_w7c;
wire [55:0] addnode_w8c;
wire [55:0] addnode_w9c;
wire [2:0] qlevel_w0c;
wire [12:0] qlevel_w10c;
wire [13:0] qlevel_w11c;
wire [14:0] qlevel_w12c;
wire [15:0] qlevel_w13c;
wire [16:0] qlevel_w14c;
wire [17:0] qlevel_w15c;
wire [18:0] qlevel_w16c;
wire [19:0] qlevel_w17c;
wire [20:0] qlevel_w18c;
wire [21:0] qlevel_w19c;
wire [3:0] qlevel_w1c;
wire [22:0] qlevel_w20c;
wire [23:0] qlevel_w21c;
wire [24:0] qlevel_w22c;
wire [25:0] qlevel_w23c;
wire [26:0] qlevel_w24c;
wire [27:0] qlevel_w25c;
wire [28:0] qlevel_w26c;
wire [29:0] qlevel_w27c;
wire [30:0] qlevel_w28c;
wire [31:0] qlevel_w29c;
wire [4:0] qlevel_w2c;
wire [32:0] qlevel_w30c;
wire [33:0] qlevel_w31c;
wire [34:0] qlevel_w32c;
wire [35:0] qlevel_w33c;
wire [36:0] qlevel_w34c;
wire [37:0] qlevel_w35c;
wire [38:0] qlevel_w36c;
wire [39:0] qlevel_w37c;
wire [40:0] qlevel_w38c;
wire [41:0] qlevel_w39c;
wire [5:0] qlevel_w3c;
wire [42:0] qlevel_w40c;
wire [43:0] qlevel_w41c;
wire [44:0] qlevel_w42c;
wire [45:0] qlevel_w43c;
wire [46:0] qlevel_w44c;
wire [47:0] qlevel_w45c;
wire [48:0] qlevel_w46c;
wire [49:0] qlevel_w47c;
wire [50:0] qlevel_w48c;
wire [51:0] qlevel_w49c;
wire [6:0] qlevel_w4c;
wire [52:0] qlevel_w50c;
wire [53:0] qlevel_w51c;
wire [54:0] qlevel_w52c;
wire [55:0] qlevel_w53c;
wire [7:0] qlevel_w5c;
wire [8:0] qlevel_w6c;
wire [9:0] qlevel_w7c;
wire [10:0] qlevel_w8c;
wire [11:0] qlevel_w9c;
wire [55:0] slevel_w0c;
wire [55:0] slevel_w10c;
wire [55:0] slevel_w11c;
wire [55:0] slevel_w12c;
wire [55:0] slevel_w13c;
wire [55:0] slevel_w14c;
wire [55:0] slevel_w15c;
wire [55:0] slevel_w16c;
wire [55:0] slevel_w17c;
wire [55:0] slevel_w18c;
wire [55:0] slevel_w19c;
wire [55:0] slevel_w1c;
wire [55:0] slevel_w20c;
wire [55:0] slevel_w21c;
wire [55:0] slevel_w22c;
wire [55:0] slevel_w23c;
wire [55:0] slevel_w24c;
wire [55:0] slevel_w25c;
wire [55:0] slevel_w26c;
wire [55:0] slevel_w27c;
wire [55:0] slevel_w28c;
wire [55:0] slevel_w29c;
wire [55:0] slevel_w2c;
wire [55:0] slevel_w30c;
wire [55:0] slevel_w31c;
wire [55:0] slevel_w32c;
wire [55:0] slevel_w33c;
wire [55:0] slevel_w34c;
wire [55:0] slevel_w35c;
wire [55:0] slevel_w36c;
wire [55:0] slevel_w37c;
wire [55:0] slevel_w38c;
wire [55:0] slevel_w39c;
wire [55:0] slevel_w3c;
wire [55:0] slevel_w40c;
wire [55:0] slevel_w41c;
wire [55:0] slevel_w42c;
wire [55:0] slevel_w43c;
wire [55:0] slevel_w44c;
wire [55:0] slevel_w45c;
wire [55:0] slevel_w46c;
wire [55:0] slevel_w47c;
wire [55:0] slevel_w48c;
wire [55:0] slevel_w49c;
wire [55:0] slevel_w4c;
wire [55:0] slevel_w50c;
wire [55:0] slevel_w51c;
wire [55:0] slevel_w52c;
wire [55:0] slevel_w53c;
wire [55:0] slevel_w5c;
wire [55:0] slevel_w6c;
wire [55:0] slevel_w7c;
wire [55:0] slevel_w8c;
wire [55:0] slevel_w9c;
// synopsys translate_off
initial
q_ff0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff0c <= 2'b0;
else if (clken == 1'b1) q_ff0c <= {(~ addnode_w52c[55]), (~ addnode_w53c[55])};
// synopsys translate_off
initial
q_ff10c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff10c <= 52'b0;
else if (clken == 1'b1) q_ff10c <= {q_ff10c[49:0], (~ addnode_w42c[55]), (~ addnode_w43c[55])};
// synopsys translate_off
initial
q_ff12c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff12c <= 52'b0;
else if (clken == 1'b1) q_ff12c <= {q_ff12c[49:0], (~ addnode_w40c[55]), (~ addnode_w41c[55])};
// synopsys translate_off
initial
q_ff14c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff14c <= 52'b0;
else if (clken == 1'b1) q_ff14c <= {q_ff14c[49:0], (~ addnode_w38c[55]), (~ addnode_w39c[55])};
// synopsys translate_off
initial
q_ff16c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff16c <= 52'b0;
else if (clken == 1'b1) q_ff16c <= {q_ff16c[49:0], (~ addnode_w36c[55]), (~ addnode_w37c[55])};
// synopsys translate_off
initial
q_ff18c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff18c <= 52'b0;
else if (clken == 1'b1) q_ff18c <= {q_ff18c[49:0], (~ addnode_w34c[55]), (~ addnode_w35c[55])};
// synopsys translate_off
initial
q_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff20c <= 52'b0;
else if (clken == 1'b1) q_ff20c <= {q_ff20c[49:0], (~ addnode_w32c[55]), (~ addnode_w33c[55])};
// synopsys translate_off
initial
q_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff22c <= 52'b0;
else if (clken == 1'b1) q_ff22c <= {q_ff22c[49:0], (~ addnode_w30c[55]), (~ addnode_w31c[55])};
// synopsys translate_off
initial
q_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff24c <= 52'b0;
else if (clken == 1'b1) q_ff24c <= {q_ff24c[49:0], (~ addnode_w28c[55]), (~ addnode_w29c[55])};
// synopsys translate_off
initial
q_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff26c <= 52'b0;
else if (clken == 1'b1) q_ff26c <= {q_ff26c[49:0], (~ addnode_w26c[55]), (~ addnode_w27c[55])};
// synopsys translate_off
initial
q_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff28c <= 52'b0;
else if (clken == 1'b1) q_ff28c <= {q_ff28c[49:0], (~ addnode_w24c[55]), (~ addnode_w25c[55])};
// synopsys translate_off
initial
q_ff2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff2c <= 52'b0;
else if (clken == 1'b1) q_ff2c <= {q_ff2c[49:0], (~ addnode_w50c[55]), (~ addnode_w51c[55])};
// synopsys translate_off
initial
q_ff30c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff30c <= 52'b0;
else if (clken == 1'b1) q_ff30c <= {q_ff30c[49:0], (~ addnode_w22c[55]), (~ addnode_w23c[55])};
// synopsys translate_off
initial
q_ff32c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff32c <= 52'b0;
else if (clken == 1'b1) q_ff32c <= {q_ff32c[49:0], (~ addnode_w20c[55]), (~ addnode_w21c[55])};
// synopsys translate_off
initial
q_ff34c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff34c <= 52'b0;
else if (clken == 1'b1) q_ff34c <= {q_ff34c[49:0], (~ addnode_w18c[55]), (~ addnode_w19c[55])};
// synopsys translate_off
initial
q_ff36c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff36c <= 52'b0;
else if (clken == 1'b1) q_ff36c <= {q_ff36c[49:0], (~ addnode_w16c[55]), (~ addnode_w17c[55])};
// synopsys translate_off
initial
q_ff38c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff38c <= 52'b0;
else if (clken == 1'b1) q_ff38c <= {q_ff38c[49:0], (~ addnode_w14c[55]), (~ addnode_w15c[55])};
// synopsys translate_off
initial
q_ff40c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff40c <= 52'b0;
else if (clken == 1'b1) q_ff40c <= {q_ff40c[49:0], (~ addnode_w12c[55]), (~ addnode_w13c[55])};
// synopsys translate_off
initial
q_ff42c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff42c <= 52'b0;
else if (clken == 1'b1) q_ff42c <= {q_ff42c[49:0], (~ addnode_w10c[55]), (~ addnode_w11c[55])};
// synopsys translate_off
initial
q_ff44c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff44c <= 52'b0;
else if (clken == 1'b1) q_ff44c <= {q_ff44c[49:0], (~ addnode_w8c[55]), (~ addnode_w9c[55])};
// synopsys translate_off
initial
q_ff46c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff46c <= 52'b0;
else if (clken == 1'b1) q_ff46c <= {q_ff46c[49:0], (~ addnode_w6c[55]), (~ addnode_w7c[55])};
// synopsys translate_off
initial
q_ff48c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff48c <= 52'b0;
else if (clken == 1'b1) q_ff48c <= {q_ff48c[49:0], (~ addnode_w4c[55]), (~ addnode_w5c[55])};
// synopsys translate_off
initial
q_ff4c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff4c <= 52'b0;
else if (clken == 1'b1) q_ff4c <= {q_ff4c[49:0], (~ addnode_w48c[55]), (~ addnode_w49c[55])};
// synopsys translate_off
initial
q_ff50c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff50c <= 52'b0;
else if (clken == 1'b1) q_ff50c <= {q_ff50c[49:0], (~ addnode_w2c[55]), (~ addnode_w3c[55])};
// synopsys translate_off
initial
q_ff52c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff52c <= 27'b0;
else if (clken == 1'b1) q_ff52c <= {q_ff52c[25:0], (~ addnode_w1c[55])};
// synopsys translate_off
initial
q_ff6c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff6c <= 52'b0;
else if (clken == 1'b1) q_ff6c <= {q_ff6c[49:0], (~ addnode_w46c[55]), (~ addnode_w47c[55])};
// synopsys translate_off
initial
q_ff8c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff8c <= 52'b0;
else if (clken == 1'b1) q_ff8c <= {q_ff8c[49:0], (~ addnode_w44c[55]), (~ addnode_w45c[55])};
// synopsys translate_off
initial
rad_ff11c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff11c <= 44'b0;
else if (clken == 1'b1) rad_ff11c <= addnode_w11c[55:12];
// synopsys translate_off
initial
rad_ff13c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff13c <= 42'b0;
else if (clken == 1'b1) rad_ff13c <= addnode_w13c[55:14];
// synopsys translate_off
initial
rad_ff15c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff15c <= 40'b0;
else if (clken == 1'b1) rad_ff15c <= addnode_w15c[55:16];
// synopsys translate_off
initial
rad_ff17c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff17c <= 38'b0;
else if (clken == 1'b1) rad_ff17c <= addnode_w17c[55:18];
// synopsys translate_off
initial
rad_ff19c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff19c <= 36'b0;
else if (clken == 1'b1) rad_ff19c <= addnode_w19c[55:20];
// synopsys translate_off
initial
rad_ff1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff1c <= 54'b0;
else if (clken == 1'b1) rad_ff1c <= addnode_w1c[55:2];
// synopsys translate_off
initial
rad_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff21c <= 34'b0;
else if (clken == 1'b1) rad_ff21c <= addnode_w21c[55:22];
// synopsys translate_off
initial
rad_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff23c <= 32'b0;
else if (clken == 1'b1) rad_ff23c <= addnode_w23c[55:24];
// synopsys translate_off
initial
rad_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff25c <= 30'b0;
else if (clken == 1'b1) rad_ff25c <= addnode_w25c[55:26];
// synopsys translate_off
initial
rad_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff27c <= 28'b0;
else if (clken == 1'b1) rad_ff27c <= addnode_w27c[55:28];
// synopsys translate_off
initial
rad_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff29c <= 29'b0;
else if (clken == 1'b1) rad_ff29c <= addnode_w29c[55:27];
// synopsys translate_off
initial
rad_ff31c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff31c <= 31'b0;
else if (clken == 1'b1) rad_ff31c <= addnode_w31c[55:25];
// synopsys translate_off
initial
rad_ff33c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff33c <= 33'b0;
else if (clken == 1'b1) rad_ff33c <= addnode_w33c[55:23];
// synopsys translate_off
initial
rad_ff35c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff35c <= 35'b0;
else if (clken == 1'b1) rad_ff35c <= addnode_w35c[55:21];
// synopsys translate_off
initial
rad_ff37c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff37c <= 37'b0;
else if (clken == 1'b1) rad_ff37c <= addnode_w37c[55:19];
// synopsys translate_off
initial
rad_ff39c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff39c <= 39'b0;
else if (clken == 1'b1) rad_ff39c <= addnode_w39c[55:17];
// synopsys translate_off
initial
rad_ff3c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff3c <= 52'b0;
else if (clken == 1'b1) rad_ff3c <= addnode_w3c[55:4];
// synopsys translate_off
initial
rad_ff41c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff41c <= 41'b0;
else if (clken == 1'b1) rad_ff41c <= addnode_w41c[55:15];
// synopsys translate_off
initial
rad_ff43c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff43c <= 43'b0;
else if (clken == 1'b1) rad_ff43c <= addnode_w43c[55:13];
// synopsys translate_off
initial
rad_ff45c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff45c <= 45'b0;
else if (clken == 1'b1) rad_ff45c <= addnode_w45c[55:11];
// synopsys translate_off
initial
rad_ff47c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff47c <= 47'b0;
else if (clken == 1'b1) rad_ff47c <= addnode_w47c[55:9];
// synopsys translate_off
initial
rad_ff49c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff49c <= 49'b0;
else if (clken == 1'b1) rad_ff49c <= addnode_w49c[55:7];
// synopsys translate_off
initial
rad_ff51c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff51c <= 51'b0;
else if (clken == 1'b1) rad_ff51c <= addnode_w51c[55:5];
// synopsys translate_off
initial
rad_ff5c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff5c <= 50'b0;
else if (clken == 1'b1) rad_ff5c <= addnode_w5c[55:6];
// synopsys translate_off
initial
rad_ff7c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff7c <= 48'b0;
else if (clken == 1'b1) rad_ff7c <= addnode_w7c[55:8];
// synopsys translate_off
initial
rad_ff9c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff9c <= 46'b0;
else if (clken == 1'b1) rad_ff9c <= addnode_w9c[55:10];
lpm_add_sub add_sub10
(
.cout(),
.dataa({slevel_w6c[55:47]}),
.datab({(({7{(~ rad_ff5c[49])}} & (~ qlevel_w6c[8:2])) | ({7{rad_ff5c[49]}} & qlevel_w6c[8:2])), qlevel_w6c[1:0]}),
.overflow(),
.result(wire_add_sub10_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub10.lpm_direction = "ADD",
add_sub10.lpm_pipeline = 0,
add_sub10.lpm_width = 9,
add_sub10.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub11
(
.cout(),
.dataa({slevel_w7c[55:46]}),
.datab({(({8{(~ addnode_w6c[55])}} & (~ qlevel_w7c[9:2])) | ({8{addnode_w6c[55]}} & qlevel_w7c[9:2])), qlevel_w7c[1:0]}),
.overflow(),
.result(wire_add_sub11_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub11.lpm_direction = "ADD",
add_sub11.lpm_pipeline = 0,
add_sub11.lpm_width = 10,
add_sub11.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub12
(
.cout(),
.dataa({slevel_w8c[55:45]}),
.datab({(({9{(~ rad_ff7c[47])}} & (~ qlevel_w8c[10:2])) | ({9{rad_ff7c[47]}} & qlevel_w8c[10:2])), qlevel_w8c[1:0]}),
.overflow(),
.result(wire_add_sub12_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub12.lpm_direction = "ADD",
add_sub12.lpm_pipeline = 0,
add_sub12.lpm_width = 11,
add_sub12.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub13
(
.cout(),
.dataa({slevel_w9c[55:44]}),
.datab({(({10{(~ addnode_w8c[55])}} & (~ qlevel_w9c[11:2])) | ({10{addnode_w8c[55]}} & qlevel_w9c[11:2])), qlevel_w9c[1:0]}),
.overflow(),
.result(wire_add_sub13_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub13.lpm_direction = "ADD",
add_sub13.lpm_pipeline = 0,
add_sub13.lpm_width = 12,
add_sub13.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub14
(
.cout(),
.dataa({slevel_w10c[55:43]}),
.datab({(({11{(~ rad_ff9c[45])}} & (~ qlevel_w10c[12:2])) | ({11{rad_ff9c[45]}} & qlevel_w10c[12:2])), qlevel_w10c[1:0]}),
.overflow(),
.result(wire_add_sub14_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub14.lpm_direction = "ADD",
add_sub14.lpm_pipeline = 0,
add_sub14.lpm_width = 13,
add_sub14.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub15
(
.cout(),
.dataa({slevel_w11c[55:42]}),
.datab({(({12{(~ addnode_w10c[55])}} & (~ qlevel_w11c[13:2])) | ({12{addnode_w10c[55]}} & qlevel_w11c[13:2])), qlevel_w11c[1:0]}),
.overflow(),
.result(wire_add_sub15_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub15.lpm_direction = "ADD",
add_sub15.lpm_pipeline = 0,
add_sub15.lpm_width = 14,
add_sub15.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub16
(
.cout(),
.dataa({slevel_w12c[55:41]}),
.datab({(({13{(~ rad_ff11c[43])}} & (~ qlevel_w12c[14:2])) | ({13{rad_ff11c[43]}} & qlevel_w12c[14:2])), qlevel_w12c[1:0]}),
.overflow(),
.result(wire_add_sub16_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub16.lpm_direction = "ADD",
add_sub16.lpm_pipeline = 0,
add_sub16.lpm_width = 15,
add_sub16.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub17
(
.cout(),
.dataa({slevel_w13c[55:40]}),
.datab({(({14{(~ addnode_w12c[55])}} & (~ qlevel_w13c[15:2])) | ({14{addnode_w12c[55]}} & qlevel_w13c[15:2])), qlevel_w13c[1:0]}),
.overflow(),
.result(wire_add_sub17_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub17.lpm_direction = "ADD",
add_sub17.lpm_pipeline = 0,
add_sub17.lpm_width = 16,
add_sub17.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub18
(
.cout(),
.dataa({slevel_w14c[55:39]}),
.datab({(({15{(~ rad_ff13c[41])}} & (~ qlevel_w14c[16:2])) | ({15{rad_ff13c[41]}} & qlevel_w14c[16:2])), qlevel_w14c[1:0]}),
.overflow(),
.result(wire_add_sub18_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub18.lpm_direction = "ADD",
add_sub18.lpm_pipeline = 0,
add_sub18.lpm_width = 17,
add_sub18.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub19
(
.cout(),
.dataa({slevel_w15c[55:38]}),
.datab({(({16{(~ addnode_w14c[55])}} & (~ qlevel_w15c[17:2])) | ({16{addnode_w14c[55]}} & qlevel_w15c[17:2])), qlevel_w15c[1:0]}),
.overflow(),
.result(wire_add_sub19_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub19.lpm_direction = "ADD",
add_sub19.lpm_pipeline = 0,
add_sub19.lpm_width = 18,
add_sub19.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub20
(
.cout(),
.dataa({slevel_w16c[55:37]}),
.datab({(({17{(~ rad_ff15c[39])}} & (~ qlevel_w16c[18:2])) | ({17{rad_ff15c[39]}} & qlevel_w16c[18:2])), qlevel_w16c[1:0]}),
.overflow(),
.result(wire_add_sub20_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub20.lpm_direction = "ADD",
add_sub20.lpm_pipeline = 0,
add_sub20.lpm_width = 19,
add_sub20.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub21
(
.cout(),
.dataa({slevel_w17c[55:36]}),
.datab({(({18{(~ addnode_w16c[55])}} & (~ qlevel_w17c[19:2])) | ({18{addnode_w16c[55]}} & qlevel_w17c[19:2])), qlevel_w17c[1:0]}),
.overflow(),
.result(wire_add_sub21_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub21.lpm_direction = "ADD",
add_sub21.lpm_pipeline = 0,
add_sub21.lpm_width = 20,
add_sub21.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub22
(
.cout(),
.dataa({slevel_w18c[55:35]}),
.datab({(({19{(~ rad_ff17c[37])}} & (~ qlevel_w18c[20:2])) | ({19{rad_ff17c[37]}} & qlevel_w18c[20:2])), qlevel_w18c[1:0]}),
.overflow(),
.result(wire_add_sub22_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub22.lpm_direction = "ADD",
add_sub22.lpm_pipeline = 0,
add_sub22.lpm_width = 21,
add_sub22.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub23
(
.cout(),
.dataa({slevel_w19c[55:34]}),
.datab({(({20{(~ addnode_w18c[55])}} & (~ qlevel_w19c[21:2])) | ({20{addnode_w18c[55]}} & qlevel_w19c[21:2])), qlevel_w19c[1:0]}),
.overflow(),
.result(wire_add_sub23_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub23.lpm_direction = "ADD",
add_sub23.lpm_pipeline = 0,
add_sub23.lpm_width = 22,
add_sub23.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub24
(
.cout(),
.dataa({slevel_w20c[55:33]}),
.datab({(({21{(~ rad_ff19c[35])}} & (~ qlevel_w20c[22:2])) | ({21{rad_ff19c[35]}} & qlevel_w20c[22:2])), qlevel_w20c[1:0]}),
.overflow(),
.result(wire_add_sub24_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub24.lpm_direction = "ADD",
add_sub24.lpm_pipeline = 0,
add_sub24.lpm_width = 23,
add_sub24.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub25
(
.cout(),
.dataa({slevel_w21c[55:32]}),
.datab({(({22{(~ addnode_w20c[55])}} & (~ qlevel_w21c[23:2])) | ({22{addnode_w20c[55]}} & qlevel_w21c[23:2])), qlevel_w21c[1:0]}),
.overflow(),
.result(wire_add_sub25_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub25.lpm_direction = "ADD",
add_sub25.lpm_pipeline = 0,
add_sub25.lpm_width = 24,
add_sub25.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub26
(
.cout(),
.dataa({slevel_w22c[55:31]}),
.datab({(({23{(~ rad_ff21c[33])}} & (~ qlevel_w22c[24:2])) | ({23{rad_ff21c[33]}} & qlevel_w22c[24:2])), qlevel_w22c[1:0]}),
.overflow(),
.result(wire_add_sub26_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub26.lpm_direction = "ADD",
add_sub26.lpm_pipeline = 0,
add_sub26.lpm_width = 25,
add_sub26.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub27
(
.cout(),
.dataa({slevel_w23c[55:30]}),
.datab({(({24{(~ addnode_w22c[55])}} & (~ qlevel_w23c[25:2])) | ({24{addnode_w22c[55]}} & qlevel_w23c[25:2])), qlevel_w23c[1:0]}),
.overflow(),
.result(wire_add_sub27_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub27.lpm_direction = "ADD",
add_sub27.lpm_pipeline = 0,
add_sub27.lpm_width = 26,
add_sub27.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub28
(
.cout(),
.dataa({slevel_w24c[55:29]}),
.datab({(({25{(~ rad_ff23c[31])}} & (~ qlevel_w24c[26:2])) | ({25{rad_ff23c[31]}} & qlevel_w24c[26:2])), qlevel_w24c[1:0]}),
.overflow(),
.result(wire_add_sub28_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub28.lpm_direction = "ADD",
add_sub28.lpm_pipeline = 0,
add_sub28.lpm_width = 27,
add_sub28.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub29
(
.cout(),
.dataa({slevel_w25c[55:28]}),
.datab({(({26{(~ addnode_w24c[55])}} & (~ qlevel_w25c[27:2])) | ({26{addnode_w24c[55]}} & qlevel_w25c[27:2])), qlevel_w25c[1:0]}),
.overflow(),
.result(wire_add_sub29_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub29.lpm_direction = "ADD",
add_sub29.lpm_pipeline = 0,
add_sub29.lpm_width = 28,
add_sub29.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub30
(
.cout(),
.dataa({slevel_w26c[55:27]}),
.datab({(({27{(~ rad_ff25c[29])}} & (~ qlevel_w26c[28:2])) | ({27{rad_ff25c[29]}} & qlevel_w26c[28:2])), qlevel_w26c[1:0]}),
.overflow(),
.result(wire_add_sub30_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub30.lpm_direction = "ADD",
add_sub30.lpm_pipeline = 0,
add_sub30.lpm_width = 29,
add_sub30.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub31
(
.cout(),
.dataa({slevel_w27c[55:28]}),
.datab({(({28{(~ addnode_w26c[55])}} & (~ qlevel_w27c[29:2])) | ({28{addnode_w26c[55]}} & qlevel_w27c[29:2]))}),
.overflow(),
.result(wire_add_sub31_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub31.lpm_direction = "ADD",
add_sub31.lpm_pipeline = 0,
add_sub31.lpm_width = 28,
add_sub31.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub32
(
.cout(),
.dataa({slevel_w28c[55:28]}),
.datab({(({28{(~ rad_ff27c[27])}} & (~ qlevel_w28c[30:3])) | ({28{rad_ff27c[27]}} & qlevel_w28c[30:3]))}),
.overflow(),
.result(wire_add_sub32_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub32.lpm_direction = "ADD",
add_sub32.lpm_pipeline = 0,
add_sub32.lpm_width = 28,
add_sub32.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub33
(
.cout(),
.dataa({slevel_w29c[55:27]}),
.datab({(({29{(~ addnode_w28c[55])}} & (~ qlevel_w29c[31:3])) | ({29{addnode_w28c[55]}} & qlevel_w29c[31:3]))}),
.overflow(),
.result(wire_add_sub33_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub33.lpm_direction = "ADD",
add_sub33.lpm_pipeline = 0,
add_sub33.lpm_width = 29,
add_sub33.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub34
(
.cout(),
.dataa({slevel_w30c[55:26]}),
.datab({(({30{(~ rad_ff29c[28])}} & (~ qlevel_w30c[32:3])) | ({30{rad_ff29c[28]}} & qlevel_w30c[32:3]))}),
.overflow(),
.result(wire_add_sub34_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub34.lpm_direction = "ADD",
add_sub34.lpm_pipeline = 0,
add_sub34.lpm_width = 30,
add_sub34.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub35
(
.cout(),
.dataa({slevel_w31c[55:25]}),
.datab({(({31{(~ addnode_w30c[55])}} & (~ qlevel_w31c[33:3])) | ({31{addnode_w30c[55]}} & qlevel_w31c[33:3]))}),
.overflow(),
.result(wire_add_sub35_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub35.lpm_direction = "ADD",
add_sub35.lpm_pipeline = 0,
add_sub35.lpm_width = 31,
add_sub35.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub36
(
.cout(),
.dataa({slevel_w32c[55:24]}),
.datab({(({32{(~ rad_ff31c[30])}} & (~ qlevel_w32c[34:3])) | ({32{rad_ff31c[30]}} & qlevel_w32c[34:3]))}),
.overflow(),
.result(wire_add_sub36_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub36.lpm_direction = "ADD",
add_sub36.lpm_pipeline = 0,
add_sub36.lpm_width = 32,
add_sub36.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub37
(
.cout(),
.dataa({slevel_w33c[55:23]}),
.datab({(({33{(~ addnode_w32c[55])}} & (~ qlevel_w33c[35:3])) | ({33{addnode_w32c[55]}} & qlevel_w33c[35:3]))}),
.overflow(),
.result(wire_add_sub37_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub37.lpm_direction = "ADD",
add_sub37.lpm_pipeline = 0,
add_sub37.lpm_width = 33,
add_sub37.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub38
(
.cout(),
.dataa({slevel_w34c[55:22]}),
.datab({(({34{(~ rad_ff33c[32])}} & (~ qlevel_w34c[36:3])) | ({34{rad_ff33c[32]}} & qlevel_w34c[36:3]))}),
.overflow(),
.result(wire_add_sub38_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub38.lpm_direction = "ADD",
add_sub38.lpm_pipeline = 0,
add_sub38.lpm_width = 34,
add_sub38.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub39
(
.cout(),
.dataa({slevel_w35c[55:21]}),
.datab({(({35{(~ addnode_w34c[55])}} & (~ qlevel_w35c[37:3])) | ({35{addnode_w34c[55]}} & qlevel_w35c[37:3]))}),
.overflow(),
.result(wire_add_sub39_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub39.lpm_direction = "ADD",
add_sub39.lpm_pipeline = 0,
add_sub39.lpm_width = 35,
add_sub39.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa({slevel_w0c[55:53]}),
.datab({qlevel_w0c[2:0]}),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_pipeline = 0,
add_sub4.lpm_width = 3,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub40
(
.cout(),
.dataa({slevel_w36c[55:20]}),
.datab({(({36{(~ rad_ff35c[34])}} & (~ qlevel_w36c[38:3])) | ({36{rad_ff35c[34]}} & qlevel_w36c[38:3]))}),
.overflow(),
.result(wire_add_sub40_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub40.lpm_direction = "ADD",
add_sub40.lpm_pipeline = 0,
add_sub40.lpm_width = 36,
add_sub40.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub41
(
.cout(),
.dataa({slevel_w37c[55:19]}),
.datab({(({37{(~ addnode_w36c[55])}} & (~ qlevel_w37c[39:3])) | ({37{addnode_w36c[55]}} & qlevel_w37c[39:3]))}),
.overflow(),
.result(wire_add_sub41_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub41.lpm_direction = "ADD",
add_sub41.lpm_pipeline = 0,
add_sub41.lpm_width = 37,
add_sub41.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub42
(
.cout(),
.dataa({slevel_w38c[55:18]}),
.datab({(({38{(~ rad_ff37c[36])}} & (~ qlevel_w38c[40:3])) | ({38{rad_ff37c[36]}} & qlevel_w38c[40:3]))}),
.overflow(),
.result(wire_add_sub42_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub42.lpm_direction = "ADD",
add_sub42.lpm_pipeline = 0,
add_sub42.lpm_width = 38,
add_sub42.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub43
(
.cout(),
.dataa({slevel_w39c[55:17]}),
.datab({(({39{(~ addnode_w38c[55])}} & (~ qlevel_w39c[41:3])) | ({39{addnode_w38c[55]}} & qlevel_w39c[41:3]))}),
.overflow(),
.result(wire_add_sub43_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub43.lpm_direction = "ADD",
add_sub43.lpm_pipeline = 0,
add_sub43.lpm_width = 39,
add_sub43.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub44
(
.cout(),
.dataa({slevel_w40c[55:16]}),
.datab({(({40{(~ rad_ff39c[38])}} & (~ qlevel_w40c[42:3])) | ({40{rad_ff39c[38]}} & qlevel_w40c[42:3]))}),
.overflow(),
.result(wire_add_sub44_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub44.lpm_direction = "ADD",
add_sub44.lpm_pipeline = 0,
add_sub44.lpm_width = 40,
add_sub44.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub45
(
.cout(),
.dataa({slevel_w41c[55:15]}),
.datab({(({41{(~ addnode_w40c[55])}} & (~ qlevel_w41c[43:3])) | ({41{addnode_w40c[55]}} & qlevel_w41c[43:3]))}),
.overflow(),
.result(wire_add_sub45_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub45.lpm_direction = "ADD",
add_sub45.lpm_pipeline = 0,
add_sub45.lpm_width = 41,
add_sub45.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub46
(
.cout(),
.dataa({slevel_w42c[55:14]}),
.datab({(({42{(~ rad_ff41c[40])}} & (~ qlevel_w42c[44:3])) | ({42{rad_ff41c[40]}} & qlevel_w42c[44:3]))}),
.overflow(),
.result(wire_add_sub46_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub46.lpm_direction = "ADD",
add_sub46.lpm_pipeline = 0,
add_sub46.lpm_width = 42,
add_sub46.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub47
(
.cout(),
.dataa({slevel_w43c[55:13]}),
.datab({(({43{(~ addnode_w42c[55])}} & (~ qlevel_w43c[45:3])) | ({43{addnode_w42c[55]}} & qlevel_w43c[45:3]))}),
.overflow(),
.result(wire_add_sub47_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub47.lpm_direction = "ADD",
add_sub47.lpm_pipeline = 0,
add_sub47.lpm_width = 43,
add_sub47.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub48
(
.cout(),
.dataa({slevel_w44c[55:12]}),
.datab({(({44{(~ rad_ff43c[42])}} & (~ qlevel_w44c[46:3])) | ({44{rad_ff43c[42]}} & qlevel_w44c[46:3]))}),
.overflow(),
.result(wire_add_sub48_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub48.lpm_direction = "ADD",
add_sub48.lpm_pipeline = 0,
add_sub48.lpm_width = 44,
add_sub48.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub49
(
.cout(),
.dataa({slevel_w45c[55:11]}),
.datab({(({45{(~ addnode_w44c[55])}} & (~ qlevel_w45c[47:3])) | ({45{addnode_w44c[55]}} & qlevel_w45c[47:3]))}),
.overflow(),
.result(wire_add_sub49_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub49.lpm_direction = "ADD",
add_sub49.lpm_pipeline = 0,
add_sub49.lpm_width = 45,
add_sub49.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.cout(),
.dataa({slevel_w1c[55:52]}),
.datab({qlevel_w1c[3:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 0,
add_sub5.lpm_width = 4,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub50
(
.cout(),
.dataa({slevel_w46c[55:10]}),
.datab({(({46{(~ rad_ff45c[44])}} & (~ qlevel_w46c[48:3])) | ({46{rad_ff45c[44]}} & qlevel_w46c[48:3]))}),
.overflow(),
.result(wire_add_sub50_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub50.lpm_direction = "ADD",
add_sub50.lpm_pipeline = 0,
add_sub50.lpm_width = 46,
add_sub50.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub51
(
.cout(),
.dataa({slevel_w47c[55:9]}),
.datab({(({47{(~ addnode_w46c[55])}} & (~ qlevel_w47c[49:3])) | ({47{addnode_w46c[55]}} & qlevel_w47c[49:3]))}),
.overflow(),
.result(wire_add_sub51_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub51.lpm_direction = "ADD",
add_sub51.lpm_pipeline = 0,
add_sub51.lpm_width = 47,
add_sub51.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub52
(
.cout(),
.dataa({slevel_w48c[55:8]}),
.datab({(({48{(~ rad_ff47c[46])}} & (~ qlevel_w48c[50:3])) | ({48{rad_ff47c[46]}} & qlevel_w48c[50:3]))}),
.overflow(),
.result(wire_add_sub52_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub52.lpm_direction = "ADD",
add_sub52.lpm_pipeline = 0,
add_sub52.lpm_width = 48,
add_sub52.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub53
(
.cout(),
.dataa({slevel_w49c[55:7]}),
.datab({(({49{(~ addnode_w48c[55])}} & (~ qlevel_w49c[51:3])) | ({49{addnode_w48c[55]}} & qlevel_w49c[51:3]))}),
.overflow(),
.result(wire_add_sub53_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub53.lpm_direction = "ADD",
add_sub53.lpm_pipeline = 0,
add_sub53.lpm_width = 49,
add_sub53.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub54
(
.cout(),
.dataa({slevel_w50c[55:6]}),
.datab({(({50{(~ rad_ff49c[48])}} & (~ qlevel_w50c[52:3])) | ({50{rad_ff49c[48]}} & qlevel_w50c[52:3]))}),
.overflow(),
.result(wire_add_sub54_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub54.lpm_direction = "ADD",
add_sub54.lpm_pipeline = 0,
add_sub54.lpm_width = 50,
add_sub54.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub55
(
.cout(),
.dataa({slevel_w51c[55:5]}),
.datab({(({51{(~ addnode_w50c[55])}} & (~ qlevel_w51c[53:3])) | ({51{addnode_w50c[55]}} & qlevel_w51c[53:3]))}),
.overflow(),
.result(wire_add_sub55_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub55.lpm_direction = "ADD",
add_sub55.lpm_pipeline = 0,
add_sub55.lpm_width = 51,
add_sub55.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub56
(
.cout(),
.dataa({slevel_w52c[55:4]}),
.datab({(({52{(~ rad_ff51c[50])}} & (~ qlevel_w52c[54:3])) | ({52{rad_ff51c[50]}} & qlevel_w52c[54:3]))}),
.overflow(),
.result(wire_add_sub56_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub56.lpm_direction = "ADD",
add_sub56.lpm_pipeline = 0,
add_sub56.lpm_width = 52,
add_sub56.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub57
(
.cout(),
.dataa({slevel_w53c[55:3]}),
.datab({qlevel_w53c[55:54], (({51{(~ addnode_w52c[55])}} & (~ qlevel_w53c[53:3])) | ({51{addnode_w52c[55]}} & qlevel_w53c[53:3]))}),
.overflow(),
.result(wire_add_sub57_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub57.lpm_direction = "ADD",
add_sub57.lpm_pipeline = 0,
add_sub57.lpm_width = 53,
add_sub57.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa({slevel_w2c[55:51]}),
.datab({(({3{(~ rad_ff1c[53])}} & (~ qlevel_w2c[4:2])) | ({3{rad_ff1c[53]}} & qlevel_w2c[4:2])), qlevel_w2c[1:0]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_pipeline = 0,
add_sub6.lpm_width = 5,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub7
(
.cout(),
.dataa({slevel_w3c[55:50]}),
.datab({(({4{(~ addnode_w2c[55])}} & (~ qlevel_w3c[5:2])) | ({4{addnode_w2c[55]}} & qlevel_w3c[5:2])), qlevel_w3c[1:0]}),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_pipeline = 0,
add_sub7.lpm_width = 6,
add_sub7.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub8
(
.cout(),
.dataa({slevel_w4c[55:49]}),
.datab({(({5{(~ rad_ff3c[51])}} & (~ qlevel_w4c[6:2])) | ({5{rad_ff3c[51]}} & qlevel_w4c[6:2])), qlevel_w4c[1:0]}),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_pipeline = 0,
add_sub8.lpm_width = 7,
add_sub8.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub9
(
.cout(),
.dataa({slevel_w5c[55:48]}),
.datab({(({6{(~ addnode_w4c[55])}} & (~ qlevel_w5c[7:2])) | ({6{addnode_w4c[55]}} & qlevel_w5c[7:2])), qlevel_w5c[1:0]}),
.overflow(),
.result(wire_add_sub9_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub9.lpm_direction = "ADD",
add_sub9.lpm_pipeline = 0,
add_sub9.lpm_width = 8,
add_sub9.lpm_type = "lpm_add_sub";
assign
addnode_w0c = {wire_add_sub4_result[2:0], slevel_w0c[52:0]},
addnode_w10c = {wire_add_sub14_result[12:0], slevel_w10c[42:0]},
addnode_w11c = {wire_add_sub15_result[13:0], slevel_w11c[41:0]},
addnode_w12c = {wire_add_sub16_result[14:0], slevel_w12c[40:0]},
addnode_w13c = {wire_add_sub17_result[15:0], slevel_w13c[39:0]},
addnode_w14c = {wire_add_sub18_result[16:0], slevel_w14c[38:0]},
addnode_w15c = {wire_add_sub19_result[17:0], slevel_w15c[37:0]},
addnode_w16c = {wire_add_sub20_result[18:0], slevel_w16c[36:0]},
addnode_w17c = {wire_add_sub21_result[19:0], slevel_w17c[35:0]},
addnode_w18c = {wire_add_sub22_result[20:0], slevel_w18c[34:0]},
addnode_w19c = {wire_add_sub23_result[21:0], slevel_w19c[33:0]},
addnode_w1c = {wire_add_sub5_result[3:0], slevel_w1c[51:0]},
addnode_w20c = {wire_add_sub24_result[22:0], slevel_w20c[32:0]},
addnode_w21c = {wire_add_sub25_result[23:0], slevel_w21c[31:0]},
addnode_w22c = {wire_add_sub26_result[24:0], slevel_w22c[30:0]},
addnode_w23c = {wire_add_sub27_result[25:0], slevel_w23c[29:0]},
addnode_w24c = {wire_add_sub28_result[26:0], slevel_w24c[28:0]},
addnode_w25c = {wire_add_sub29_result[27:0], slevel_w25c[27:0]},
addnode_w26c = {wire_add_sub30_result[28:0], slevel_w26c[26:0]},
addnode_w27c = {wire_add_sub31_result[27:0], qlevel_w27c[1:0], slevel_w27c[25:0]},
addnode_w28c = {wire_add_sub32_result[27:0], 1'b1, qlevel_w28c[1:0], slevel_w28c[24:0]},
addnode_w29c = {wire_add_sub33_result[28:0], 1'b1, qlevel_w29c[1:0], slevel_w29c[23:0]},
addnode_w2c = {wire_add_sub6_result[4:0], slevel_w2c[50:0]},
addnode_w30c = {wire_add_sub34_result[29:0], 1'b1, qlevel_w30c[1:0], slevel_w30c[22:0]},
addnode_w31c = {wire_add_sub35_result[30:0], 1'b1, qlevel_w31c[1:0], slevel_w31c[21:0]},
addnode_w32c = {wire_add_sub36_result[31:0], 1'b1, qlevel_w32c[1:0], slevel_w32c[20:0]},
addnode_w33c = {wire_add_sub37_result[32:0], 1'b1, qlevel_w33c[1:0], slevel_w33c[19:0]},
addnode_w34c = {wire_add_sub38_result[33:0], 1'b1, qlevel_w34c[1:0], slevel_w34c[18:0]},
addnode_w35c = {wire_add_sub39_result[34:0], 1'b1, qlevel_w35c[1:0], slevel_w35c[17:0]},
addnode_w36c = {wire_add_sub40_result[35:0], 1'b1, qlevel_w36c[1:0], slevel_w36c[16:0]},
addnode_w37c = {wire_add_sub41_result[36:0], 1'b1, qlevel_w37c[1:0], slevel_w37c[15:0]},
addnode_w38c = {wire_add_sub42_result[37:0], 1'b1, qlevel_w38c[1:0], slevel_w38c[14:0]},
addnode_w39c = {wire_add_sub43_result[38:0], 1'b1, qlevel_w39c[1:0], slevel_w39c[13:0]},
addnode_w3c = {wire_add_sub7_result[5:0], slevel_w3c[49:0]},
addnode_w40c = {wire_add_sub44_result[39:0], 1'b1, qlevel_w40c[1:0], slevel_w40c[12:0]},
addnode_w41c = {wire_add_sub45_result[40:0], 1'b1, qlevel_w41c[1:0], slevel_w41c[11:0]},
addnode_w42c = {wire_add_sub46_result[41:0], 1'b1, qlevel_w42c[1:0], slevel_w42c[10:0]},
addnode_w43c = {wire_add_sub47_result[42:0], 1'b1, qlevel_w43c[1:0], slevel_w43c[9:0]},
addnode_w44c = {wire_add_sub48_result[43:0], 1'b1, qlevel_w44c[1:0], slevel_w44c[8:0]},
addnode_w45c = {wire_add_sub49_result[44:0], 1'b1, qlevel_w45c[1:0], slevel_w45c[7:0]},
addnode_w46c = {wire_add_sub50_result[45:0], 1'b1, qlevel_w46c[1:0], slevel_w46c[6:0]},
addnode_w47c = {wire_add_sub51_result[46:0], 1'b1, qlevel_w47c[1:0], slevel_w47c[5:0]},
addnode_w48c = {wire_add_sub52_result[47:0], 1'b1, qlevel_w48c[1:0], slevel_w48c[4:0]},
addnode_w49c = {wire_add_sub53_result[48:0], 1'b1, qlevel_w49c[1:0], slevel_w49c[3:0]},
addnode_w4c = {wire_add_sub8_result[6:0], slevel_w4c[48:0]},
addnode_w50c = {wire_add_sub54_result[49:0], 1'b1, qlevel_w50c[1:0], slevel_w50c[2:0]},
addnode_w51c = {wire_add_sub55_result[50:0], 1'b1, qlevel_w51c[1:0], slevel_w51c[1:0]},
addnode_w52c = {wire_add_sub56_result[51:0], 1'b1, qlevel_w52c[1:0], slevel_w52c[0]},
addnode_w53c = {wire_add_sub57_result[52:0], 1'b1, qlevel_w53c[1:0]},
addnode_w5c = {wire_add_sub9_result[7:0], slevel_w5c[47:0]},
addnode_w6c = {wire_add_sub10_result[8:0], slevel_w6c[46:0]},
addnode_w7c = {wire_add_sub11_result[9:0], slevel_w7c[45:0]},
addnode_w8c = {wire_add_sub12_result[10:0], slevel_w8c[44:0]},
addnode_w9c = {wire_add_sub13_result[11:0], slevel_w9c[43:0]},
qlevel_w0c = {3{1'b1}},
qlevel_w10c = {1'b0, 1'b1, q_ff52c[4], q_ff50c[7:6], q_ff48c[5:4], q_ff46c[3:2], q_ff44c[1:0], {2{1'b1}}},
qlevel_w11c = {1'b0, 1'b1, q_ff52c[4], q_ff50c[7:6], q_ff48c[5:4], q_ff46c[3:2], q_ff44c[1:0], (~ addnode_w10c[55]), {2{1'b1}}},
qlevel_w12c = {1'b0, 1'b1, q_ff52c[5], q_ff50c[9:8], q_ff48c[7:6], q_ff46c[5:4], q_ff44c[3:2], q_ff42c[1:0], {2{1'b1}}},
qlevel_w13c = {1'b0, 1'b1, q_ff52c[5], q_ff50c[9:8], q_ff48c[7:6], q_ff46c[5:4], q_ff44c[3:2], q_ff42c[1:0], (~ addnode_w12c[55]), {2{1'b1}}},
qlevel_w14c = {1'b0, 1'b1, q_ff52c[6], q_ff50c[11:10], q_ff48c[9:8], q_ff46c[7:6], q_ff44c[5:4], q_ff42c[3:2], q_ff40c[1:0], {2{1'b1}}},
qlevel_w15c = {1'b0, 1'b1, q_ff52c[6], q_ff50c[11:10], q_ff48c[9:8], q_ff46c[7:6], q_ff44c[5:4], q_ff42c[3:2], q_ff40c[1:0], (~ addnode_w14c[55]), {2{1'b1}}},
qlevel_w16c = {1'b0, 1'b1, q_ff52c[7], q_ff50c[13:12], q_ff48c[11:10], q_ff46c[9:8], q_ff44c[7:6], q_ff42c[5:4], q_ff40c[3:2], q_ff38c[1:0], {2{1'b1}}},
qlevel_w17c = {1'b0, 1'b1, q_ff52c[7], q_ff50c[13:12], q_ff48c[11:10], q_ff46c[9:8], q_ff44c[7:6], q_ff42c[5:4], q_ff40c[3:2], q_ff38c[1:0], (~ addnode_w16c[55]), {2{1'b1}}},
qlevel_w18c = {1'b0, 1'b1, q_ff52c[8], q_ff50c[15:14], q_ff48c[13:12], q_ff46c[11:10], q_ff44c[9:8], q_ff42c[7:6], q_ff40c[5:4], q_ff38c[3:2], q_ff36c[1:0], {2{1'b1}}},
qlevel_w19c = {1'b0, 1'b1, q_ff52c[8], q_ff50c[15:14], q_ff48c[13:12], q_ff46c[11:10], q_ff44c[9:8], q_ff42c[7:6], q_ff40c[5:4], q_ff38c[3:2], q_ff36c[1:0], (~ addnode_w18c[55]), {2{1'b1}}},
qlevel_w1c = {1'b1, 1'b0, {2{1'b1}}},
qlevel_w20c = {1'b0, 1'b1, q_ff52c[9], q_ff50c[17:16], q_ff48c[15:14], q_ff46c[13:12], q_ff44c[11:10], q_ff42c[9:8], q_ff40c[7:6], q_ff38c[5:4], q_ff36c[3:2], q_ff34c[1:0], {2{1'b1}}},
qlevel_w21c = {1'b0, 1'b1, q_ff52c[9], q_ff50c[17:16], q_ff48c[15:14], q_ff46c[13:12], q_ff44c[11:10], q_ff42c[9:8], q_ff40c[7:6], q_ff38c[5:4], q_ff36c[3:2], q_ff34c[1:0], (~ addnode_w20c[55]), {2{1'b1}}},
qlevel_w22c = {1'b0, 1'b1, q_ff52c[10], q_ff50c[19:18], q_ff48c[17:16], q_ff46c[15:14], q_ff44c[13:12], q_ff42c[11:10], q_ff40c[9:8], q_ff38c[7:6], q_ff36c[5:4], q_ff34c[3:2], q_ff32c[1:0], {2{1'b1}}},
qlevel_w23c = {1'b0, 1'b1, q_ff52c[10], q_ff50c[19:18], q_ff48c[17:16], q_ff46c[15:14], q_ff44c[13:12], q_ff42c[11:10], q_ff40c[9:8], q_ff38c[7:6], q_ff36c[5:4], q_ff34c[3:2], q_ff32c[1:0], (~ addnode_w22c[55]), {2{1'b1}}},
qlevel_w24c = {1'b0, 1'b1, q_ff52c[11], q_ff50c[21:20], q_ff48c[19:18], q_ff46c[17:16], q_ff44c[15:14], q_ff42c[13:12], q_ff40c[11:10], q_ff38c[9:8], q_ff36c[7:6], q_ff34c[5:4], q_ff32c[3:2], q_ff30c[1:0], {2{1'b1}}},
qlevel_w25c = {1'b0, 1'b1, q_ff52c[11], q_ff50c[21:20], q_ff48c[19:18], q_ff46c[17:16], q_ff44c[15:14], q_ff42c[13:12], q_ff40c[11:10], q_ff38c[9:8], q_ff36c[7:6], q_ff34c[5:4], q_ff32c[3:2], q_ff30c[1:0], (~ addnode_w24c[55]), {2{1'b1}}},
qlevel_w26c = {1'b0, 1'b1, q_ff52c[12], q_ff50c[23:22], q_ff48c[21:20], q_ff46c[19:18], q_ff44c[17:16], q_ff42c[15:14], q_ff40c[13:12], q_ff38c[11:10], q_ff36c[9:8], q_ff34c[7:6], q_ff32c[5:4], q_ff30c[3:2], q_ff28c[1:0], {2{1'b1}}},
qlevel_w27c = {1'b0, 1'b1, q_ff52c[12], q_ff50c[23:22], q_ff48c[21:20], q_ff46c[19:18], q_ff44c[17:16], q_ff42c[15:14], q_ff40c[13:12], q_ff38c[11:10], q_ff36c[9:8], q_ff34c[7:6], q_ff32c[5:4], q_ff30c[3:2], q_ff28c[1:0], (~ addnode_w26c[55]), {2{1'b1}}},
qlevel_w28c = {1'b0, 1'b1, q_ff52c[13], q_ff50c[25:24], q_ff48c[23:22], q_ff46c[21:20], q_ff44c[19:18], q_ff42c[17:16], q_ff40c[15:14], q_ff38c[13:12], q_ff36c[11:10], q_ff34c[9:8], q_ff32c[7:6], q_ff30c[5:4], q_ff28c[3:2], q_ff26c[1:0], {2{1'b1}}},
qlevel_w29c = {1'b0, 1'b1, q_ff52c[13], q_ff50c[25:24], q_ff48c[23:22], q_ff46c[21:20], q_ff44c[19:18], q_ff42c[17:16], q_ff40c[15:14], q_ff38c[13:12], q_ff36c[11:10], q_ff34c[9:8], q_ff32c[7:6], q_ff30c[5:4], q_ff28c[3:2], q_ff26c[1:0], (~ addnode_w28c[55]), {2{1'b1}}},
qlevel_w2c = {1'b0, 1'b1, q_ff52c[0], {2{1'b1}}},
qlevel_w30c = {1'b0, 1'b1, q_ff52c[14], q_ff50c[27:26], q_ff48c[25:24], q_ff46c[23:22], q_ff44c[21:20], q_ff42c[19:18], q_ff40c[17:16], q_ff38c[15:14], q_ff36c[13:12], q_ff34c[11:10], q_ff32c[9:8], q_ff30c[7:6], q_ff28c[5:4], q_ff26c[3:2], q_ff24c[1:0], {2{1'b1}}},
qlevel_w31c = {1'b0, 1'b1, q_ff52c[14], q_ff50c[27:26], q_ff48c[25:24], q_ff46c[23:22], q_ff44c[21:20], q_ff42c[19:18], q_ff40c[17:16], q_ff38c[15:14], q_ff36c[13:12], q_ff34c[11:10], q_ff32c[9:8], q_ff30c[7:6], q_ff28c[5:4], q_ff26c[3:2], q_ff24c[1:0], (~ addnode_w30c[55]), {2{1'b1}}},
qlevel_w32c = {1'b0, 1'b1, q_ff52c[15], q_ff50c[29:28], q_ff48c[27:26], q_ff46c[25:24], q_ff44c[23:22], q_ff42c[21:20], q_ff40c[19:18], q_ff38c[17:16], q_ff36c[15:14], q_ff34c[13:12], q_ff32c[11:10], q_ff30c[9:8], q_ff28c[7:6], q_ff26c[5:4], q_ff24c[3:2], q_ff22c[1:0], {2{1'b1}}},
qlevel_w33c = {1'b0, 1'b1, q_ff52c[15], q_ff50c[29:28], q_ff48c[27:26], q_ff46c[25:24], q_ff44c[23:22], q_ff42c[21:20], q_ff40c[19:18], q_ff38c[17:16], q_ff36c[15:14], q_ff34c[13:12], q_ff32c[11:10], q_ff30c[9:8], q_ff28c[7:6], q_ff26c[5:4], q_ff24c[3:2], q_ff22c[1:0], (~ addnode_w32c[55]), {2{1'b1}}},
qlevel_w34c = {1'b0, 1'b1, q_ff52c[16], q_ff50c[31:30], q_ff48c[29:28], q_ff46c[27:26], q_ff44c[25:24], q_ff42c[23:22], q_ff40c[21:20], q_ff38c[19:18], q_ff36c[17:16], q_ff34c[15:14], q_ff32c[13:12], q_ff30c[11:10], q_ff28c[9:8], q_ff26c[7:6], q_ff24c[5:4], q_ff22c[3:2], q_ff20c[1:0], {2{1'b1}}},
qlevel_w35c = {1'b0, 1'b1, q_ff52c[16], q_ff50c[31:30], q_ff48c[29:28], q_ff46c[27:26], q_ff44c[25:24], q_ff42c[23:22], q_ff40c[21:20], q_ff38c[19:18], q_ff36c[17:16], q_ff34c[15:14], q_ff32c[13:12], q_ff30c[11:10], q_ff28c[9:8], q_ff26c[7:6], q_ff24c[5:4], q_ff22c[3:2], q_ff20c[1:0], (~ addnode_w34c[55]), {2{1'b1}}},
qlevel_w36c = {1'b0, 1'b1, q_ff52c[17], q_ff50c[33:32], q_ff48c[31:30], q_ff46c[29:28], q_ff44c[27:26], q_ff42c[25:24], q_ff40c[23:22], q_ff38c[21:20], q_ff36c[19:18], q_ff34c[17:16], q_ff32c[15:14], q_ff30c[13:12], q_ff28c[11:10], q_ff26c[9:8], q_ff24c[7:6], q_ff22c[5:4], q_ff20c[3:2], q_ff18c[1:0], {2{1'b1}}},
qlevel_w37c = {1'b0, 1'b1, q_ff52c[17], q_ff50c[33:32], q_ff48c[31:30], q_ff46c[29:28], q_ff44c[27:26], q_ff42c[25:24], q_ff40c[23:22], q_ff38c[21:20], q_ff36c[19:18], q_ff34c[17:16], q_ff32c[15:14], q_ff30c[13:12], q_ff28c[11:10], q_ff26c[9:8], q_ff24c[7:6], q_ff22c[5:4], q_ff20c[3:2], q_ff18c[1:0], (~ addnode_w36c[55]), {2{1'b1}}},
qlevel_w38c = {1'b0, 1'b1, q_ff52c[18], q_ff50c[35:34], q_ff48c[33:32], q_ff46c[31:30], q_ff44c[29:28], q_ff42c[27:26], q_ff40c[25:24], q_ff38c[23:22], q_ff36c[21:20], q_ff34c[19:18], q_ff32c[17:16], q_ff30c[15:14], q_ff28c[13:12], q_ff26c[11:10], q_ff24c[9:8], q_ff22c[7:6], q_ff20c[5:4], q_ff18c[3:2], q_ff16c[1:0], {2{1'b1}}},
qlevel_w39c = {1'b0, 1'b1, q_ff52c[18], q_ff50c[35:34], q_ff48c[33:32], q_ff46c[31:30], q_ff44c[29:28], q_ff42c[27:26], q_ff40c[25:24], q_ff38c[23:22], q_ff36c[21:20], q_ff34c[19:18], q_ff32c[17:16], q_ff30c[15:14], q_ff28c[13:12], q_ff26c[11:10], q_ff24c[9:8], q_ff22c[7:6], q_ff20c[5:4], q_ff18c[3:2], q_ff16c[1:0], (~ addnode_w38c[55]), {2{1'b1}}},
qlevel_w3c = {1'b0, 1'b1, q_ff52c[0], (~ addnode_w2c[55]), {2{1'b1}}},
qlevel_w40c = {1'b0, 1'b1, q_ff52c[19], q_ff50c[37:36], q_ff48c[35:34], q_ff46c[33:32], q_ff44c[31:30], q_ff42c[29:28], q_ff40c[27:26], q_ff38c[25:24], q_ff36c[23:22], q_ff34c[21:20], q_ff32c[19:18], q_ff30c[17:16], q_ff28c[15:14], q_ff26c[13:12], q_ff24c[11:10], q_ff22c[9:8], q_ff20c[7:6], q_ff18c[5:4], q_ff16c[3:2], q_ff14c[1:0], {2{1'b1}}},
qlevel_w41c = {1'b0, 1'b1, q_ff52c[19], q_ff50c[37:36], q_ff48c[35:34], q_ff46c[33:32], q_ff44c[31:30], q_ff42c[29:28], q_ff40c[27:26], q_ff38c[25:24], q_ff36c[23:22], q_ff34c[21:20], q_ff32c[19:18], q_ff30c[17:16], q_ff28c[15:14], q_ff26c[13:12], q_ff24c[11:10], q_ff22c[9:8], q_ff20c[7:6], q_ff18c[5:4], q_ff16c[3:2], q_ff14c[1:0], (~ addnode_w40c[55]), {2{1'b1}}},
qlevel_w42c = {1'b0, 1'b1, q_ff52c[20], q_ff50c[39:38], q_ff48c[37:36], q_ff46c[35:34], q_ff44c[33:32], q_ff42c[31:30], q_ff40c[29:28], q_ff38c[27:26], q_ff36c[25:24], q_ff34c[23:22], q_ff32c[21:20], q_ff30c[19:18], q_ff28c[17:16], q_ff26c[15:14], q_ff24c[13:12], q_ff22c[11:10], q_ff20c[9:8], q_ff18c[7:6], q_ff16c[5:4], q_ff14c[3:2], q_ff12c[1:0], {2{1'b1}}},
qlevel_w43c = {1'b0, 1'b1, q_ff52c[20], q_ff50c[39:38], q_ff48c[37:36], q_ff46c[35:34], q_ff44c[33:32], q_ff42c[31:30], q_ff40c[29:28], q_ff38c[27:26], q_ff36c[25:24], q_ff34c[23:22], q_ff32c[21:20], q_ff30c[19:18], q_ff28c[17:16], q_ff26c[15:14], q_ff24c[13:12], q_ff22c[11:10], q_ff20c[9:8], q_ff18c[7:6], q_ff16c[5:4], q_ff14c[3:2], q_ff12c[1:0], (~ addnode_w42c[55]), {2{1'b1}}},
qlevel_w44c = {1'b0, 1'b1, q_ff52c[21], q_ff50c[41:40], q_ff48c[39:38], q_ff46c[37:36], q_ff44c[35:34], q_ff42c[33:32], q_ff40c[31:30], q_ff38c[29:28], q_ff36c[27:26], q_ff34c[25:24], q_ff32c[23:22], q_ff30c[21:20], q_ff28c[19:18], q_ff26c[17:16], q_ff24c[15:14], q_ff22c[13:12], q_ff20c[11:10], q_ff18c[9:8], q_ff16c[7:6], q_ff14c[5:4], q_ff12c[3:2], q_ff10c[1:0], {2{1'b1}}},
qlevel_w45c = {1'b0, 1'b1, q_ff52c[21], q_ff50c[41:40], q_ff48c[39:38], q_ff46c[37:36], q_ff44c[35:34], q_ff42c[33:32], q_ff40c[31:30], q_ff38c[29:28], q_ff36c[27:26], q_ff34c[25:24], q_ff32c[23:22], q_ff30c[21:20], q_ff28c[19:18], q_ff26c[17:16], q_ff24c[15:14], q_ff22c[13:12], q_ff20c[11:10], q_ff18c[9:8], q_ff16c[7:6], q_ff14c[5:4], q_ff12c[3:2], q_ff10c[1:0], (~ addnode_w44c[55]), {2{1'b1}}},
qlevel_w46c = {1'b0, 1'b1, q_ff52c[22], q_ff50c[43:42], q_ff48c[41:40], q_ff46c[39:38], q_ff44c[37:36], q_ff42c[35:34], q_ff40c[33:32], q_ff38c[31:30], q_ff36c[29:28], q_ff34c[27:26], q_ff32c[25:24], q_ff30c[23:22], q_ff28c[21:20], q_ff26c[19:18], q_ff24c[17:16], q_ff22c[15:14], q_ff20c[13:12], q_ff18c[11:10], q_ff16c[9:8], q_ff14c[7:6], q_ff12c[5:4], q_ff10c[3:2], q_ff8c[1:0], {2{1'b1}}},
qlevel_w47c = {1'b0, 1'b1, q_ff52c[22], q_ff50c[43:42], q_ff48c[41:40], q_ff46c[39:38], q_ff44c[37:36], q_ff42c[35:34], q_ff40c[33:32], q_ff38c[31:30], q_ff36c[29:28], q_ff34c[27:26], q_ff32c[25:24], q_ff30c[23:22], q_ff28c[21:20], q_ff26c[19:18], q_ff24c[17:16], q_ff22c[15:14], q_ff20c[13:12], q_ff18c[11:10], q_ff16c[9:8], q_ff14c[7:6], q_ff12c[5:4], q_ff10c[3:2], q_ff8c[1:0], (~ addnode_w46c[55]), {2{1'b1}}},
qlevel_w48c = {1'b0, 1'b1, q_ff52c[23], q_ff50c[45:44], q_ff48c[43:42], q_ff46c[41:40], q_ff44c[39:38], q_ff42c[37:36], q_ff40c[35:34], q_ff38c[33:32], q_ff36c[31:30], q_ff34c[29:28], q_ff32c[27:26], q_ff30c[25:24], q_ff28c[23:22], q_ff26c[21:20], q_ff24c[19:18], q_ff22c[17:16], q_ff20c[15:14], q_ff18c[13:12], q_ff16c[11:10], q_ff14c[9:8], q_ff12c[7:6], q_ff10c[5:4], q_ff8c[3:2], q_ff6c[1:0], {2{1'b1}}},
qlevel_w49c = {1'b0, 1'b1, q_ff52c[23], q_ff50c[45:44], q_ff48c[43:42], q_ff46c[41:40], q_ff44c[39:38], q_ff42c[37:36], q_ff40c[35:34], q_ff38c[33:32], q_ff36c[31:30], q_ff34c[29:28], q_ff32c[27:26], q_ff30c[25:24], q_ff28c[23:22], q_ff26c[21:20], q_ff24c[19:18], q_ff22c[17:16], q_ff20c[15:14], q_ff18c[13:12], q_ff16c[11:10], q_ff14c[9:8], q_ff12c[7:6], q_ff10c[5:4], q_ff8c[3:2], q_ff6c[1:0], (~ addnode_w48c[55]), {2{1'b1}}},
qlevel_w4c = {1'b0, 1'b1, q_ff52c[1], q_ff50c[1:0], {2{1'b1}}},
qlevel_w50c = {1'b0, 1'b1, q_ff52c[24], q_ff50c[47:46], q_ff48c[45:44], q_ff46c[43:42], q_ff44c[41:40], q_ff42c[39:38], q_ff40c[37:36], q_ff38c[35:34], q_ff36c[33:32], q_ff34c[31:30], q_ff32c[29:28], q_ff30c[27:26], q_ff28c[25:24], q_ff26c[23:22], q_ff24c[21:20], q_ff22c[19:18], q_ff20c[17:16], q_ff18c[15:14], q_ff16c[13:12], q_ff14c[11:10], q_ff12c[9:8], q_ff10c[7:6], q_ff8c[5:4], q_ff6c[3:2], q_ff4c[1:0], {2{1'b1}}},
qlevel_w51c = {1'b0, 1'b1, q_ff52c[24], q_ff50c[47:46], q_ff48c[45:44], q_ff46c[43:42], q_ff44c[41:40], q_ff42c[39:38], q_ff40c[37:36], q_ff38c[35:34], q_ff36c[33:32], q_ff34c[31:30], q_ff32c[29:28], q_ff30c[27:26], q_ff28c[25:24], q_ff26c[23:22], q_ff24c[21:20], q_ff22c[19:18], q_ff20c[17:16], q_ff18c[15:14], q_ff16c[13:12], q_ff14c[11:10], q_ff12c[9:8], q_ff10c[7:6], q_ff8c[5:4], q_ff6c[3:2], q_ff4c[1:0], (~ addnode_w50c[55]), {2{1'b1}}},
qlevel_w52c = {1'b0, 1'b1, q_ff52c[25], q_ff50c[49:48], q_ff48c[47:46], q_ff46c[45:44], q_ff44c[43:42], q_ff42c[41:40], q_ff40c[39:38], q_ff38c[37:36], q_ff36c[35:34], q_ff34c[33:32], q_ff32c[31:30], q_ff30c[29:28], q_ff28c[27:26], q_ff26c[25:24], q_ff24c[23:22], q_ff22c[21:20], q_ff20c[19:18], q_ff18c[17:16], q_ff16c[15:14], q_ff14c[13:12], q_ff12c[11:10], q_ff10c[9:8], q_ff8c[7:6], q_ff6c[5:4], q_ff4c[3:2], q_ff2c[1:0], {2{1'b1}}},
qlevel_w53c = {(~ addnode_w52c[55]), addnode_w52c[55], q_ff52c[25], q_ff50c[49:48], q_ff48c[47:46], q_ff46c[45:44], q_ff44c[43:42], q_ff42c[41:40], q_ff40c[39:38], q_ff38c[37:36], q_ff36c[35:34], q_ff34c[33:32], q_ff32c[31:30], q_ff30c[29:28], q_ff28c[27:26], q_ff26c[25:24], q_ff24c[23:22], q_ff22c[21:20], q_ff20c[19:18], q_ff18c[17:16], q_ff16c[15:14], q_ff14c[13:12], q_ff12c[11:10], q_ff10c[9:8], q_ff8c[7:6], q_ff6c[5:4], q_ff4c[3:2], q_ff2c[1:0], (~ addnode_w52c[55]), {2{1'b1}}},
qlevel_w5c = {1'b0, 1'b1, q_ff52c[1], q_ff50c[1:0], (~ addnode_w4c[55]), {2{1'b1}}},
qlevel_w6c = {1'b0, 1'b1, q_ff52c[2], q_ff50c[3:2], q_ff48c[1:0], {2{1'b1}}},
qlevel_w7c = {1'b0, 1'b1, q_ff52c[2], q_ff50c[3:2], q_ff48c[1:0], (~ addnode_w6c[55]), {2{1'b1}}},
qlevel_w8c = {1'b0, 1'b1, q_ff52c[3], q_ff50c[5:4], q_ff48c[3:2], q_ff46c[1:0], {2{1'b1}}},
qlevel_w9c = {1'b0, 1'b1, q_ff52c[3], q_ff50c[5:4], q_ff48c[3:2], q_ff46c[1:0], (~ addnode_w8c[55]), {2{1'b1}}},
root_result = {1'b1, q_ff52c[26], q_ff50c[51:50], q_ff48c[49:48], q_ff46c[47:46], q_ff44c[45:44], q_ff42c[43:42], q_ff40c[41:40], q_ff38c[39:38], q_ff36c[37:36], q_ff34c[35:34], q_ff32c[33:32], q_ff30c[31:30], q_ff28c[29:28], q_ff26c[27:26], q_ff24c[25:24], q_ff22c[23:22], q_ff20c[21:20], q_ff18c[19:18], q_ff16c[17:16], q_ff14c[15:14], q_ff12c[13:12], q_ff10c[11:10], q_ff8c[9:8], q_ff6c[7:6], q_ff4c[5:4], q_ff2c[3:2], q_ff0c[1:0]},
slevel_w0c = {1'b0, rad},
slevel_w10c = {rad_ff9c[44:0], {11{1'b0}}},
slevel_w11c = {addnode_w10c[54:11], {12{1'b0}}},
slevel_w12c = {rad_ff11c[42:0], {13{1'b0}}},
slevel_w13c = {addnode_w12c[54:13], {14{1'b0}}},
slevel_w14c = {rad_ff13c[40:0], {15{1'b0}}},
slevel_w15c = {addnode_w14c[54:15], {16{1'b0}}},
slevel_w16c = {rad_ff15c[38:0], {17{1'b0}}},
slevel_w17c = {addnode_w16c[54:17], {18{1'b0}}},
slevel_w18c = {rad_ff17c[36:0], {19{1'b0}}},
slevel_w19c = {addnode_w18c[54:19], {20{1'b0}}},
slevel_w1c = {addnode_w0c[54:1], {2{1'b0}}},
slevel_w20c = {rad_ff19c[34:0], {21{1'b0}}},
slevel_w21c = {addnode_w20c[54:21], {22{1'b0}}},
slevel_w22c = {rad_ff21c[32:0], {23{1'b0}}},
slevel_w23c = {addnode_w22c[54:23], {24{1'b0}}},
slevel_w24c = {rad_ff23c[30:0], {25{1'b0}}},
slevel_w25c = {addnode_w24c[54:25], {26{1'b0}}},
slevel_w26c = {rad_ff25c[28:0], {27{1'b0}}},
slevel_w27c = {addnode_w26c[54:27], {28{1'b0}}},
slevel_w28c = {rad_ff27c[26:0], {2{1'b1}}, {27{1'b0}}},
slevel_w29c = {addnode_w28c[54:28], {3{1'b1}}, {26{1'b0}}},
slevel_w2c = {rad_ff1c[52:0], {3{1'b0}}},
slevel_w30c = {rad_ff29c[27:0], {3{1'b1}}, {25{1'b0}}},
slevel_w31c = {addnode_w30c[54:26], {3{1'b1}}, {24{1'b0}}},
slevel_w32c = {rad_ff31c[29:0], {3{1'b1}}, {23{1'b0}}},
slevel_w33c = {addnode_w32c[54:24], {3{1'b1}}, {22{1'b0}}},
slevel_w34c = {rad_ff33c[31:0], {3{1'b1}}, {21{1'b0}}},
slevel_w35c = {addnode_w34c[54:22], {3{1'b1}}, {20{1'b0}}},
slevel_w36c = {rad_ff35c[33:0], {3{1'b1}}, {19{1'b0}}},
slevel_w37c = {addnode_w36c[54:20], {3{1'b1}}, {18{1'b0}}},
slevel_w38c = {rad_ff37c[35:0], {3{1'b1}}, {17{1'b0}}},
slevel_w39c = {addnode_w38c[54:18], {3{1'b1}}, {16{1'b0}}},
slevel_w3c = {addnode_w2c[54:3], {4{1'b0}}},
slevel_w40c = {rad_ff39c[37:0], {3{1'b1}}, {15{1'b0}}},
slevel_w41c = {addnode_w40c[54:16], {3{1'b1}}, {14{1'b0}}},
slevel_w42c = {rad_ff41c[39:0], {3{1'b1}}, {13{1'b0}}},
slevel_w43c = {addnode_w42c[54:14], {3{1'b1}}, {12{1'b0}}},
slevel_w44c = {rad_ff43c[41:0], {3{1'b1}}, {11{1'b0}}},
slevel_w45c = {addnode_w44c[54:12], {3{1'b1}}, {10{1'b0}}},
slevel_w46c = {rad_ff45c[43:0], {3{1'b1}}, {9{1'b0}}},
slevel_w47c = {addnode_w46c[54:10], {3{1'b1}}, {8{1'b0}}},
slevel_w48c = {rad_ff47c[45:0], {3{1'b1}}, {7{1'b0}}},
slevel_w49c = {addnode_w48c[54:8], {3{1'b1}}, {6{1'b0}}},
slevel_w4c = {rad_ff3c[50:0], {5{1'b0}}},
slevel_w50c = {rad_ff49c[47:0], {3{1'b1}}, {5{1'b0}}},
slevel_w51c = {addnode_w50c[54:6], {3{1'b1}}, {4{1'b0}}},
slevel_w52c = {rad_ff51c[49:0], {3{1'b1}}, {3{1'b0}}},
slevel_w53c = {addnode_w52c[54:4], {3{1'b1}}, {2{1'b0}}},
slevel_w5c = {addnode_w4c[54:5], {6{1'b0}}},
slevel_w6c = {rad_ff5c[48:0], {7{1'b0}}},
slevel_w7c = {addnode_w6c[54:7], {8{1'b0}}},
slevel_w8c = {rad_ff7c[46:0], {9{1'b0}}},
slevel_w9c = {addnode_w8c[54:9], {10{1'b0}}};
endmodule //acl_fp_sqrt_s5_double_alt_sqrt_block_odb
//synthesis_resources = lpm_add_sub 56 reg 2983
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sqrt_s5_double_altfp_sqrt_n9d
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] wire_alt_sqrt_block2_root_result;
reg exp_all_one_ff;
reg [10:0] exp_ff1;
reg [10:0] exp_ff20c;
reg [10:0] exp_ff210c;
reg [10:0] exp_ff211c;
reg [10:0] exp_ff212c;
reg [10:0] exp_ff213c;
reg [10:0] exp_ff214c;
reg [10:0] exp_ff215c;
reg [10:0] exp_ff216c;
reg [10:0] exp_ff217c;
reg [10:0] exp_ff218c;
reg [10:0] exp_ff219c;
reg [10:0] exp_ff21c;
reg [10:0] exp_ff220c;
reg [10:0] exp_ff221c;
reg [10:0] exp_ff222c;
reg [10:0] exp_ff223c;
reg [10:0] exp_ff224c;
reg [10:0] exp_ff225c;
reg [10:0] exp_ff226c;
reg [10:0] exp_ff22c;
reg [10:0] exp_ff23c;
reg [10:0] exp_ff24c;
reg [10:0] exp_ff25c;
reg [10:0] exp_ff26c;
reg [10:0] exp_ff27c;
reg [10:0] exp_ff28c;
reg [10:0] exp_ff29c;
reg [10:0] exp_in_ff;
reg exp_not_zero_ff;
reg [10:0] exp_result_ff;
reg [0:0] infinity_ff0;
reg [0:0] infinity_ff1;
reg [0:0] infinity_ff2;
reg [0:0] infinity_ff3;
reg [0:0] infinity_ff4;
reg [0:0] infinity_ff5;
reg [0:0] infinity_ff6;
reg [0:0] infinity_ff7;
reg [0:0] infinity_ff8;
reg [0:0] infinity_ff9;
reg [0:0] infinity_ff10;
reg [0:0] infinity_ff11;
reg [0:0] infinity_ff12;
reg [0:0] infinity_ff13;
reg [0:0] infinity_ff14;
reg [0:0] infinity_ff15;
reg [0:0] infinity_ff16;
reg [0:0] infinity_ff17;
reg [0:0] infinity_ff18;
reg [0:0] infinity_ff19;
reg [0:0] infinity_ff20;
reg [0:0] infinity_ff21;
reg [0:0] infinity_ff22;
reg [0:0] infinity_ff23;
reg [0:0] infinity_ff24;
reg [0:0] infinity_ff25;
reg [0:0] infinity_ff26;
reg [51:0] man_in_ff;
reg man_not_zero_ff;
reg [51:0] man_result_ff;
reg [51:0] man_rounding_ff;
reg [0:0] nan_man_ff0;
reg [0:0] nan_man_ff1;
reg [0:0] nan_man_ff2;
reg [0:0] nan_man_ff3;
reg [0:0] nan_man_ff4;
reg [0:0] nan_man_ff5;
reg [0:0] nan_man_ff6;
reg [0:0] nan_man_ff7;
reg [0:0] nan_man_ff8;
reg [0:0] nan_man_ff9;
reg [0:0] nan_man_ff10;
reg [0:0] nan_man_ff11;
reg [0:0] nan_man_ff12;
reg [0:0] nan_man_ff13;
reg [0:0] nan_man_ff14;
reg [0:0] nan_man_ff15;
reg [0:0] nan_man_ff16;
reg [0:0] nan_man_ff17;
reg [0:0] nan_man_ff18;
reg [0:0] nan_man_ff19;
reg [0:0] nan_man_ff20;
reg [0:0] nan_man_ff21;
reg [0:0] nan_man_ff22;
reg [0:0] nan_man_ff23;
reg [0:0] nan_man_ff24;
reg [0:0] nan_man_ff25;
reg [0:0] nan_man_ff26;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg [0:0] sign_node_ff10;
reg [0:0] sign_node_ff11;
reg [0:0] sign_node_ff12;
reg [0:0] sign_node_ff13;
reg [0:0] sign_node_ff14;
reg [0:0] sign_node_ff15;
reg [0:0] sign_node_ff16;
reg [0:0] sign_node_ff17;
reg [0:0] sign_node_ff18;
reg [0:0] sign_node_ff19;
reg [0:0] sign_node_ff20;
reg [0:0] sign_node_ff21;
reg [0:0] sign_node_ff22;
reg [0:0] sign_node_ff23;
reg [0:0] sign_node_ff24;
reg [0:0] sign_node_ff25;
reg [0:0] sign_node_ff26;
reg [0:0] sign_node_ff27;
reg [0:0] sign_node_ff28;
reg [0:0] sign_node_ff29;
reg [0:0] zero_exp_ff0;
reg [0:0] zero_exp_ff1;
reg [0:0] zero_exp_ff2;
reg [0:0] zero_exp_ff3;
reg [0:0] zero_exp_ff4;
reg [0:0] zero_exp_ff5;
reg [0:0] zero_exp_ff6;
reg [0:0] zero_exp_ff7;
reg [0:0] zero_exp_ff8;
reg [0:0] zero_exp_ff9;
reg [0:0] zero_exp_ff10;
reg [0:0] zero_exp_ff11;
reg [0:0] zero_exp_ff12;
reg [0:0] zero_exp_ff13;
reg [0:0] zero_exp_ff14;
reg [0:0] zero_exp_ff15;
reg [0:0] zero_exp_ff16;
reg [0:0] zero_exp_ff17;
reg [0:0] zero_exp_ff18;
reg [0:0] zero_exp_ff19;
reg [0:0] zero_exp_ff20;
reg [0:0] zero_exp_ff21;
reg [0:0] zero_exp_ff22;
reg [0:0] zero_exp_ff23;
reg [0:0] zero_exp_ff24;
reg [0:0] zero_exp_ff25;
reg [0:0] zero_exp_ff26;
wire [11:0] wire_add_sub1_result;
wire [51:0] wire_add_sub3_result;
wire aclr;
wire [10:0] bias;
wire [10:0] exp_all_one_w;
wire [10:0] exp_div_w;
wire [10:0] exp_ff2_w;
wire [10:0] exp_not_zero_w;
wire infinitycondition_w;
wire [51:0] man_not_zero_w;
wire [53:0] man_root_result_w;
wire nancondition_w;
wire preadjust_w;
wire [54:0] radicand_w;
wire roundbit_w;
acl_fp_sqrt_s5_double_alt_sqrt_block_odb alt_sqrt_block2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.rad(radicand_w),
.root_result(wire_alt_sqrt_block2_root_result));
// synopsys translate_off
initial
exp_all_one_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_all_one_ff <= 1'b0;
else if (clk_en == 1'b1) exp_all_one_ff <= exp_all_one_w[10];
// synopsys translate_off
initial
exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff1 <= 11'b0;
else if (clk_en == 1'b1) exp_ff1 <= exp_div_w;
// synopsys translate_off
initial
exp_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff20c <= 11'b0;
else if (clk_en == 1'b1) exp_ff20c <= exp_ff1;
// synopsys translate_off
initial
exp_ff210c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff210c <= 11'b0;
else if (clk_en == 1'b1) exp_ff210c <= exp_ff29c;
// synopsys translate_off
initial
exp_ff211c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff211c <= 11'b0;
else if (clk_en == 1'b1) exp_ff211c <= exp_ff210c;
// synopsys translate_off
initial
exp_ff212c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff212c <= 11'b0;
else if (clk_en == 1'b1) exp_ff212c <= exp_ff211c;
// synopsys translate_off
initial
exp_ff213c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff213c <= 11'b0;
else if (clk_en == 1'b1) exp_ff213c <= exp_ff212c;
// synopsys translate_off
initial
exp_ff214c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff214c <= 11'b0;
else if (clk_en == 1'b1) exp_ff214c <= exp_ff213c;
// synopsys translate_off
initial
exp_ff215c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff215c <= 11'b0;
else if (clk_en == 1'b1) exp_ff215c <= exp_ff214c;
// synopsys translate_off
initial
exp_ff216c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff216c <= 11'b0;
else if (clk_en == 1'b1) exp_ff216c <= exp_ff215c;
// synopsys translate_off
initial
exp_ff217c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff217c <= 11'b0;
else if (clk_en == 1'b1) exp_ff217c <= exp_ff216c;
// synopsys translate_off
initial
exp_ff218c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff218c <= 11'b0;
else if (clk_en == 1'b1) exp_ff218c <= exp_ff217c;
// synopsys translate_off
initial
exp_ff219c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff219c <= 11'b0;
else if (clk_en == 1'b1) exp_ff219c <= exp_ff218c;
// synopsys translate_off
initial
exp_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff21c <= 11'b0;
else if (clk_en == 1'b1) exp_ff21c <= exp_ff20c;
// synopsys translate_off
initial
exp_ff220c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff220c <= 11'b0;
else if (clk_en == 1'b1) exp_ff220c <= exp_ff219c;
// synopsys translate_off
initial
exp_ff221c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff221c <= 11'b0;
else if (clk_en == 1'b1) exp_ff221c <= exp_ff220c;
// synopsys translate_off
initial
exp_ff222c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff222c <= 11'b0;
else if (clk_en == 1'b1) exp_ff222c <= exp_ff221c;
// synopsys translate_off
initial
exp_ff223c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff223c <= 11'b0;
else if (clk_en == 1'b1) exp_ff223c <= exp_ff222c;
// synopsys translate_off
initial
exp_ff224c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff224c <= 11'b0;
else if (clk_en == 1'b1) exp_ff224c <= exp_ff223c;
// synopsys translate_off
initial
exp_ff225c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff225c <= 11'b0;
else if (clk_en == 1'b1) exp_ff225c <= exp_ff224c;
// synopsys translate_off
initial
exp_ff226c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff226c <= 11'b0;
else if (clk_en == 1'b1) exp_ff226c <= exp_ff225c;
// synopsys translate_off
initial
exp_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff22c <= 11'b0;
else if (clk_en == 1'b1) exp_ff22c <= exp_ff21c;
// synopsys translate_off
initial
exp_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff23c <= 11'b0;
else if (clk_en == 1'b1) exp_ff23c <= exp_ff22c;
// synopsys translate_off
initial
exp_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff24c <= 11'b0;
else if (clk_en == 1'b1) exp_ff24c <= exp_ff23c;
// synopsys translate_off
initial
exp_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff25c <= 11'b0;
else if (clk_en == 1'b1) exp_ff25c <= exp_ff24c;
// synopsys translate_off
initial
exp_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff26c <= 11'b0;
else if (clk_en == 1'b1) exp_ff26c <= exp_ff25c;
// synopsys translate_off
initial
exp_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff27c <= 11'b0;
else if (clk_en == 1'b1) exp_ff27c <= exp_ff26c;
// synopsys translate_off
initial
exp_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff28c <= 11'b0;
else if (clk_en == 1'b1) exp_ff28c <= exp_ff27c;
// synopsys translate_off
initial
exp_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff29c <= 11'b0;
else if (clk_en == 1'b1) exp_ff29c <= exp_ff28c;
// synopsys translate_off
initial
exp_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_in_ff <= 11'b0;
else if (clk_en == 1'b1) exp_in_ff <= data[62:52];
// synopsys translate_off
initial
exp_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) exp_not_zero_ff <= exp_not_zero_w[10];
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 11'b0;
else if (clk_en == 1'b1) exp_result_ff <= (((exp_ff2_w & {11{zero_exp_ff26[0:0]}}) | {11{nan_man_ff26[0:0]}}) | {11{infinity_ff26[0:0]}});
// synopsys translate_off
initial
infinity_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff0 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff0 <= (infinitycondition_w & (~ sign_node_ff1[0:0]));
// synopsys translate_off
initial
infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff1 <= infinity_ff0[0:0];
// synopsys translate_off
initial
infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff2 <= infinity_ff1[0:0];
// synopsys translate_off
initial
infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff3 <= infinity_ff2[0:0];
// synopsys translate_off
initial
infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff4 <= infinity_ff3[0:0];
// synopsys translate_off
initial
infinity_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff5 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff5 <= infinity_ff4[0:0];
// synopsys translate_off
initial
infinity_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff6 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff6 <= infinity_ff5[0:0];
// synopsys translate_off
initial
infinity_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff7 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff7 <= infinity_ff6[0:0];
// synopsys translate_off
initial
infinity_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff8 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff8 <= infinity_ff7[0:0];
// synopsys translate_off
initial
infinity_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff9 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff9 <= infinity_ff8[0:0];
// synopsys translate_off
initial
infinity_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff10 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff10 <= infinity_ff9[0:0];
// synopsys translate_off
initial
infinity_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff11 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff11 <= infinity_ff10[0:0];
// synopsys translate_off
initial
infinity_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff12 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff12 <= infinity_ff11[0:0];
// synopsys translate_off
initial
infinity_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff13 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff13 <= infinity_ff12[0:0];
// synopsys translate_off
initial
infinity_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff14 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff14 <= infinity_ff13[0:0];
// synopsys translate_off
initial
infinity_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff15 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff15 <= infinity_ff14[0:0];
// synopsys translate_off
initial
infinity_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff16 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff16 <= infinity_ff15[0:0];
// synopsys translate_off
initial
infinity_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff17 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff17 <= infinity_ff16[0:0];
// synopsys translate_off
initial
infinity_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff18 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff18 <= infinity_ff17[0:0];
// synopsys translate_off
initial
infinity_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff19 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff19 <= infinity_ff18[0:0];
// synopsys translate_off
initial
infinity_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff20 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff20 <= infinity_ff19[0:0];
// synopsys translate_off
initial
infinity_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff21 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff21 <= infinity_ff20[0:0];
// synopsys translate_off
initial
infinity_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff22 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff22 <= infinity_ff21[0:0];
// synopsys translate_off
initial
infinity_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff23 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff23 <= infinity_ff22[0:0];
// synopsys translate_off
initial
infinity_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff24 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff24 <= infinity_ff23[0:0];
// synopsys translate_off
initial
infinity_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff25 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff25 <= infinity_ff24[0:0];
// synopsys translate_off
initial
infinity_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff26 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff26 <= infinity_ff25[0:0];
// synopsys translate_off
initial
man_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_in_ff <= 52'b0;
else if (clk_en == 1'b1) man_in_ff <= data[51:0];
// synopsys translate_off
initial
man_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) man_not_zero_ff <= man_not_zero_w[51];
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 52'b0;
else if (clk_en == 1'b1) man_result_ff <= ((man_rounding_ff & {52{zero_exp_ff26[0:0]}}) | {52{nan_man_ff26[0:0]}});
// synopsys translate_off
initial
man_rounding_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_rounding_ff <= 52'b0;
else if (clk_en == 1'b1) man_rounding_ff <= wire_add_sub3_result;
// synopsys translate_off
initial
nan_man_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff0 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff0 <= nancondition_w;
// synopsys translate_off
initial
nan_man_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff1 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff1 <= nan_man_ff0[0:0];
// synopsys translate_off
initial
nan_man_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff2 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff2 <= nan_man_ff1[0:0];
// synopsys translate_off
initial
nan_man_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff3 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff3 <= nan_man_ff2[0:0];
// synopsys translate_off
initial
nan_man_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff4 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff4 <= nan_man_ff3[0:0];
// synopsys translate_off
initial
nan_man_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff5 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff5 <= nan_man_ff4[0:0];
// synopsys translate_off
initial
nan_man_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff6 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff6 <= nan_man_ff5[0:0];
// synopsys translate_off
initial
nan_man_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff7 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff7 <= nan_man_ff6[0:0];
// synopsys translate_off
initial
nan_man_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff8 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff8 <= nan_man_ff7[0:0];
// synopsys translate_off
initial
nan_man_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff9 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff9 <= nan_man_ff8[0:0];
// synopsys translate_off
initial
nan_man_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff10 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff10 <= nan_man_ff9[0:0];
// synopsys translate_off
initial
nan_man_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff11 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff11 <= nan_man_ff10[0:0];
// synopsys translate_off
initial
nan_man_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff12 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff12 <= nan_man_ff11[0:0];
// synopsys translate_off
initial
nan_man_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff13 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff13 <= nan_man_ff12[0:0];
// synopsys translate_off
initial
nan_man_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff14 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff14 <= nan_man_ff13[0:0];
// synopsys translate_off
initial
nan_man_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff15 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff15 <= nan_man_ff14[0:0];
// synopsys translate_off
initial
nan_man_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff16 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff16 <= nan_man_ff15[0:0];
// synopsys translate_off
initial
nan_man_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff17 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff17 <= nan_man_ff16[0:0];
// synopsys translate_off
initial
nan_man_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff18 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff18 <= nan_man_ff17[0:0];
// synopsys translate_off
initial
nan_man_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff19 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff19 <= nan_man_ff18[0:0];
// synopsys translate_off
initial
nan_man_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff20 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff20 <= nan_man_ff19[0:0];
// synopsys translate_off
initial
nan_man_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff21 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff21 <= nan_man_ff20[0:0];
// synopsys translate_off
initial
nan_man_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff22 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff22 <= nan_man_ff21[0:0];
// synopsys translate_off
initial
nan_man_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff23 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff23 <= nan_man_ff22[0:0];
// synopsys translate_off
initial
nan_man_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff24 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff24 <= nan_man_ff23[0:0];
// synopsys translate_off
initial
nan_man_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff25 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff25 <= nan_man_ff24[0:0];
// synopsys translate_off
initial
nan_man_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff26 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff26 <= nan_man_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= data[63];
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sign_node_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff10 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff10 <= sign_node_ff9[0:0];
// synopsys translate_off
initial
sign_node_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff11 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff11 <= sign_node_ff10[0:0];
// synopsys translate_off
initial
sign_node_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff12 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff12 <= sign_node_ff11[0:0];
// synopsys translate_off
initial
sign_node_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff13 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff13 <= sign_node_ff12[0:0];
// synopsys translate_off
initial
sign_node_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff14 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff14 <= sign_node_ff13[0:0];
// synopsys translate_off
initial
sign_node_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff15 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff15 <= sign_node_ff14[0:0];
// synopsys translate_off
initial
sign_node_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff16 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff16 <= sign_node_ff15[0:0];
// synopsys translate_off
initial
sign_node_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff17 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff17 <= sign_node_ff16[0:0];
// synopsys translate_off
initial
sign_node_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff18 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff18 <= sign_node_ff17[0:0];
// synopsys translate_off
initial
sign_node_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff19 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff19 <= sign_node_ff18[0:0];
// synopsys translate_off
initial
sign_node_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff20 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff20 <= sign_node_ff19[0:0];
// synopsys translate_off
initial
sign_node_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff21 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff21 <= sign_node_ff20[0:0];
// synopsys translate_off
initial
sign_node_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff22 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff22 <= sign_node_ff21[0:0];
// synopsys translate_off
initial
sign_node_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff23 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff23 <= sign_node_ff22[0:0];
// synopsys translate_off
initial
sign_node_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff24 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff24 <= sign_node_ff23[0:0];
// synopsys translate_off
initial
sign_node_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff25 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff25 <= sign_node_ff24[0:0];
// synopsys translate_off
initial
sign_node_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff26 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff26 <= sign_node_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff27 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff27 <= sign_node_ff26[0:0];
// synopsys translate_off
initial
sign_node_ff28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff28 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff28 <= sign_node_ff27[0:0];
// synopsys translate_off
initial
sign_node_ff29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff29 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff29 <= sign_node_ff28[0:0];
// synopsys translate_off
initial
zero_exp_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff0 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff0 <= exp_not_zero_ff;
// synopsys translate_off
initial
zero_exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff1 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff1 <= zero_exp_ff0[0:0];
// synopsys translate_off
initial
zero_exp_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff2 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff2 <= zero_exp_ff1[0:0];
// synopsys translate_off
initial
zero_exp_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff3 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff3 <= zero_exp_ff2[0:0];
// synopsys translate_off
initial
zero_exp_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff4 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff4 <= zero_exp_ff3[0:0];
// synopsys translate_off
initial
zero_exp_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff5 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff5 <= zero_exp_ff4[0:0];
// synopsys translate_off
initial
zero_exp_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff6 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff6 <= zero_exp_ff5[0:0];
// synopsys translate_off
initial
zero_exp_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff7 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff7 <= zero_exp_ff6[0:0];
// synopsys translate_off
initial
zero_exp_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff8 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff8 <= zero_exp_ff7[0:0];
// synopsys translate_off
initial
zero_exp_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff9 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff9 <= zero_exp_ff8[0:0];
// synopsys translate_off
initial
zero_exp_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff10 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff10 <= zero_exp_ff9[0:0];
// synopsys translate_off
initial
zero_exp_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff11 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff11 <= zero_exp_ff10[0:0];
// synopsys translate_off
initial
zero_exp_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff12 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff12 <= zero_exp_ff11[0:0];
// synopsys translate_off
initial
zero_exp_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff13 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff13 <= zero_exp_ff12[0:0];
// synopsys translate_off
initial
zero_exp_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff14 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff14 <= zero_exp_ff13[0:0];
// synopsys translate_off
initial
zero_exp_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff15 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff15 <= zero_exp_ff14[0:0];
// synopsys translate_off
initial
zero_exp_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff16 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff16 <= zero_exp_ff15[0:0];
// synopsys translate_off
initial
zero_exp_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff17 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff17 <= zero_exp_ff16[0:0];
// synopsys translate_off
initial
zero_exp_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff18 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff18 <= zero_exp_ff17[0:0];
// synopsys translate_off
initial
zero_exp_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff19 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff19 <= zero_exp_ff18[0:0];
// synopsys translate_off
initial
zero_exp_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff20 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff20 <= zero_exp_ff19[0:0];
// synopsys translate_off
initial
zero_exp_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff21 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff21 <= zero_exp_ff20[0:0];
// synopsys translate_off
initial
zero_exp_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff22 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff22 <= zero_exp_ff21[0:0];
// synopsys translate_off
initial
zero_exp_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff23 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff23 <= zero_exp_ff22[0:0];
// synopsys translate_off
initial
zero_exp_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff24 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff24 <= zero_exp_ff23[0:0];
// synopsys translate_off
initial
zero_exp_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff25 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff25 <= zero_exp_ff24[0:0];
// synopsys translate_off
initial
zero_exp_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff26 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff26 <= zero_exp_ff25[0:0];
lpm_add_sub add_sub1
(
.cout(),
.dataa({1'b0, exp_in_ff}),
.datab({1'b0, bias}),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_pipeline = 0,
add_sub1.lpm_width = 12,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(man_root_result_w[52:1]),
.datab({{51{1'b0}}, roundbit_w}),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "ADD",
add_sub3.lpm_pipeline = 0,
add_sub3.lpm_width = 52,
add_sub3.lpm_type = "lpm_add_sub";
assign
aclr = 1'b0,
bias = {1'b0, {10{1'b1}}},
exp_all_one_w = {(exp_in_ff[10] & exp_all_one_w[9]), (exp_in_ff[9] & exp_all_one_w[8]), (exp_in_ff[8] & exp_all_one_w[7]), (exp_in_ff[7] & exp_all_one_w[6]), (exp_in_ff[6] & exp_all_one_w[5]), (exp_in_ff[5] & exp_all_one_w[4]), (exp_in_ff[4] & exp_all_one_w[3]), (exp_in_ff[3] & exp_all_one_w[2]), (exp_in_ff[2] & exp_all_one_w[1]), (exp_in_ff[1] & exp_all_one_w[0]), exp_in_ff[0]},
exp_div_w = {wire_add_sub1_result[11:1]},
exp_ff2_w = exp_ff226c,
exp_not_zero_w = {(exp_in_ff[10] | exp_not_zero_w[9]), (exp_in_ff[9] | exp_not_zero_w[8]), (exp_in_ff[8] | exp_not_zero_w[7]), (exp_in_ff[7] | exp_not_zero_w[6]), (exp_in_ff[6] | exp_not_zero_w[5]), (exp_in_ff[5] | exp_not_zero_w[4]), (exp_in_ff[4] | exp_not_zero_w[3]), (exp_in_ff[3] | exp_not_zero_w[2]), (exp_in_ff[2] | exp_not_zero_w[1]), (exp_in_ff[1] | exp_not_zero_w[0]), exp_in_ff[0]},
infinitycondition_w = ((~ man_not_zero_ff) & exp_all_one_ff),
man_not_zero_w = {(man_in_ff[51] | man_not_zero_w[50]), (man_in_ff[50] | man_not_zero_w[49]), (man_in_ff[49] | man_not_zero_w[48]), (man_in_ff[48] | man_not_zero_w[47]), (man_in_ff[47] | man_not_zero_w[46]), (man_in_ff[46] | man_not_zero_w[45]), (man_in_ff[45] | man_not_zero_w[44]), (man_in_ff[44] | man_not_zero_w[43]), (man_in_ff[43] | man_not_zero_w[42]), (man_in_ff[42] | man_not_zero_w[41]), (man_in_ff[41] | man_not_zero_w[40]), (man_in_ff[40] | man_not_zero_w[39]), (man_in_ff[39] | man_not_zero_w[38]), (man_in_ff[38] | man_not_zero_w[37]), (man_in_ff[37] | man_not_zero_w[36]), (man_in_ff[36] | man_not_zero_w[35]), (man_in_ff[35] | man_not_zero_w[34]), (man_in_ff[34] | man_not_zero_w[33]), (man_in_ff[33] | man_not_zero_w[32]), (man_in_ff[32] | man_not_zero_w[31]), (man_in_ff[31] | man_not_zero_w[30]), (man_in_ff[30] | man_not_zero_w[29]), (man_in_ff[29] | man_not_zero_w[28]), (man_in_ff[28] | man_not_zero_w[27]), (man_in_ff[27] | man_not_zero_w[26]), (man_in_ff[26] | man_not_zero_w[25]), (man_in_ff[25] | man_not_zero_w[24]), (man_in_ff[24] | man_not_zero_w[23]), (man_in_ff[23] | man_not_zero_w[22]), (man_in_ff[22] | man_not_zero_w[21]), (man_in_ff[21] | man_not_zero_w[20]), (man_in_ff[20] | man_not_zero_w[19]), (man_in_ff[19] | man_not_zero_w[18]), (man_in_ff[18] | man_not_zero_w[17]), (man_in_ff[17] | man_not_zero_w[16]), (man_in_ff[16] | man_not_zero_w[15]), (man_in_ff[15] | man_not_zero_w[14]), (man_in_ff[14] | man_not_zero_w[13]), (man_in_ff[13] | man_not_zero_w[12]), (man_in_ff[12] | man_not_zero_w[11]), (man_in_ff[11] | man_not_zero_w[10]), (man_in_ff[10] | man_not_zero_w[9]), (man_in_ff[9] | man_not_zero_w[8]), (man_in_ff[8] | man_not_zero_w[7]), (man_in_ff[7] | man_not_zero_w[6]), (man_in_ff[6] | man_not_zero_w[5]), (man_in_ff[5] | man_not_zero_w[4]), (man_in_ff[4] | man_not_zero_w[3]), (man_in_ff[3] | man_not_zero_w[2]), (man_in_ff[2] | man_not_zero_w[1]), (man_in_ff[1] | man_not_zero_w[0]), man_in_ff[0]},
man_root_result_w = wire_alt_sqrt_block2_root_result,
nancondition_w = ((sign_node_ff1[0:0] & exp_not_zero_ff) | (exp_all_one_ff & man_not_zero_ff)),
preadjust_w = exp_in_ff[0],
radicand_w = {(~ preadjust_w), (preadjust_w | (man_in_ff[51] & (~ preadjust_w))), ((man_in_ff[51:1] & {51{preadjust_w}}) | (man_in_ff[50:0] & {51{(~ preadjust_w)}})), (man_in_ff[0] & preadjust_w), 1'b0},
result = {sign_node_ff29[0:0], exp_result_ff, man_result_ff},
roundbit_w = wire_alt_sqrt_block2_root_result[0];
endmodule //acl_fp_sqrt_s5_double_altfp_sqrt_n9d
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sqrt_s5_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_sqrt_s5_double_altfp_sqrt_n9d acl_fp_sqrt_s5_double_altfp_sqrt_n9d_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "30"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: spll_pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module spll_pll (
areset,
inclk0,
pllena,
c0,
c1,
locked);
input areset;
input inclk0;
input pllena;
output c0;
output c1;
output locked;
wire [5:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.pllena (pllena),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "-2174",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 8695,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "FAST",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_USED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_enable0 = "PORT_UNUSED",
altpll_component.port_enable1 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.port_extclkena0 = "PORT_UNUSED",
altpll_component.port_extclkena1 = "PORT_UNUSED",
altpll_component.port_extclkena2 = "PORT_UNUSED",
altpll_component.port_extclkena3 = "PORT_UNUSED",
altpll_component.port_sclkout0 = "PORT_UNUSED",
altpll_component.port_sclkout1 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "115.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "115.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "115.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2174"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8695"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_wave*.jpg FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.ppf TRUE FALSE
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg c;
reg [3:0] a,b;
wire [3:0] d;
assign d = c ? a : b;
initial begin
a = 4'd5;
b = 4'd6;
c = 0;
#1;
if (d!==4'd6) begin
$display("FAILED");
$finish;
end
c = 1;
#1;
if (d!==4'd5) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4kx16_dc.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.wrempty (),
.rdfull ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:07:49 02/11/2009
// Design Name:
// Module Name: utils
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_TX (
input CLK,
input CLKDIV,
input RST,
input [31:0] DATA_IN,
input SEND_EN,
input TRAINING_DONE,
output [3:0] OSER_OQ,
output RDEN
);
reg [31:0] frame_data;
reg [8:0] count;
parameter NUM = 10'h008; // packet payload size on a single LVDS channel is 8-byte
reg RDEN_REG;
assign RDEN = RDEN_REG;
wire [7:0] PATTERN;
wire [31:0] data_to_oserdes;
// assign data_to_oserdes = TRAINING_DONE ? frame_data : {PATTERN,PATTERN,PATTERN,PATTERN};
assign data_to_oserdes = TRAINING_DONE ? frame_data : {8'h5c,8'h5c,8'h5c,8'h5c}; // training pattern for Spartan6
// using counter to implement the state machine, state transition
always @ (posedge CLKDIV) begin
if (RST == 1'b1) begin
count <= 9'h000;
end else begin
if (count == 9'h000) begin
if (SEND_EN == 1'b1)
count <= 9'h001;
else
count <= 9'h000;
//end else if (count == (NUM+9'h004) ) begin // determine how many 00 will be inserted in two successive packets
end else if (count == (NUM+9'h002) ) begin // no 00 will be inserted in two successive packets
if (SEND_EN == 1'b1) begin
count <= 9'h001;
end else begin
count <= 9'h000;
end
end else begin
count <= count + 9'h001;
end
end
end
// RDEN_REG
always @ (posedge CLKDIV) begin
if (RST == 1'b1) begin
RDEN_REG <= 1'b0;
end
else if (count == 9'h001) begin
RDEN_REG <= 1'b1;
end
else if (count == NUM+9'h001) begin
RDEN_REG <= 1'b0;
end
end
// training pattern generator
RCB_FRL_TrainingPattern RCB_FRL_TrainingPattern_inst(
.clk (CLKDIV),
.rst (RST),
.trainingpattern (PATTERN)
);
// frame encapsulation
always @ (posedge CLKDIV) begin
if ( RST == 1'b1 ) begin
frame_data[31:0] <= 32'h00000000;
end else if (count == 9'h001) begin // frame header
frame_data[31:0] <= 32'hF5F5F5F5;
end else if (count == 9'h002) begin
frame_data[31:0] <= {NUM[7:0],NUM[7:0],NUM[7:0],NUM[7:0]}; // frame size
end else if (count == 9'h000) begin
frame_data[31:0] <= 32'h44444444; // dummy
end else if (count > NUM+9'h002) begin
frame_data[31:0] <= 32'h00000000; // error, should never in this state
end else begin
frame_data[31:0] <= DATA_IN[31:0]; // frame payload
end
end
// output serdes
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst1 (
.OQ(OSER_OQ[0]),
.CLK(CLK),
.CLKDIV(CLKDIV),
.DI(data_to_oserdes[7:0]),
.OCE(1'b1),
.SR(RST)
);
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst2 (
.OQ(OSER_OQ[1]),
.CLK(CLK),
.CLKDIV(CLKDIV),
.DI(data_to_oserdes[15:8]),
.OCE(1'b1),
.SR(RST)
);
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst3 (
.OQ(OSER_OQ[2]),
.CLK(CLK),
.CLKDIV(CLKDIV),
.DI(data_to_oserdes[23:16]),
.OCE(1'b1),
.SR(RST)
);
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst4 (
.OQ(OSER_OQ[3]),
.CLK(CLK),
.CLKDIV(CLKDIV),
.DI(data_to_oserdes[31:24]),
.OCE(1'b1),
.SR(RST)
);
endmodule |
/*WARNING: INCOMPLETE MODEL, DON'T USE. I RECOMMEND AGAINST USING THIS
*BLOCK ALL TOGETHER. NOT OPEN SOURCE FRIENDLY /AO
*/
module ISERDESE2 (/*AUTOARG*/
// Outputs
O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2,
// Inputs
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY,
DYNCLKDIVSEL, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2
);
parameter DATA_RATE = 0; // "DDR" or "SDR"
parameter DATA_WIDTH = 0; // 4,2,3,5,6,7,8,10,14
parameter DYN_CLK_INV_EN = 0; // "FALSE", "TRUE"
parameter DYN_CLKDIV_INV_EN = 0; // "FALSE", "TRUE"
parameter INIT_Q1 = 0; // 1'b0 to 1'b1
parameter INIT_Q2 = 0; // 1'b0 to 1'b1
parameter INIT_Q3 = 0; // 1'b0 to 1'b1
parameter INIT_Q4 = 0; // 1'b0 to 1'b1
parameter INTERFACE_TYPE = 0; // "MEMORY","MEMORY_DDR3", "MEMORY_QDR",
// "NETWORKING", "OVERSAMPLE"
parameter IOBDELAY = 0; // "NONE", "BOTH", "IBUF", "IFD"
parameter NUM_CE = 0; // 2,1
parameter OFB_USED = 0; // "FALSE", "TRUE"
parameter SERDES_MODE = 0; // "MASTER" or "SLAVE"
parameter SRVAL_Q1 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q2 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q3 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q4 = 0; // 1'b0 or 1'b1
input BITSLIP; // performs bitslip operation
input CE1; // clock enable
input CE2; // clock enable
input CLK; // high speed clock input
input CLKB; // high speed clock input (inverted)
input CLKDIV; // divided clock (for bitslip and CE module)
input CLKDIVP; // for MIG only
input D; // serial input data pin
input DDLY; // serial input data from IDELAYE2
input DYNCLKDIVSEL; // dynamically select CLKDIV inversion
input DYNCLKSEL; // dynamically select CLK and CLKB inversion.
input OCLK; // clock for strobe based memory interfaces
input OCLKB; // clock for strobe based memory interfaces
input OFB; // data feebdack from OSERDESE2?
input RST; // asynchronous reset
input SHIFTIN1; // slave of multie serdes
input SHIFTIN2; // slave of multie serdes
//outputs
output O; // pass through from D or DDLY
output Q1; // parallel data out (last bit)
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output Q7;
output Q8; // first bit of D appears here
output SHIFTOUT1; // master of multi serdes
output SHIFTOUT2; // master of multi serdes
reg [3:0] even_samples;
reg [3:0] odd_samples;
reg Q1;
reg Q2;
reg Q3;
reg Q4;
reg Q5;
reg Q6;
reg Q7;
reg Q8;
always @ (posedge CLK)
odd_samples[3:0] <= {odd_samples[2:0],D};//#0.1
always @ (negedge CLK)
even_samples[3:0] <= {even_samples[2:0],D};//#0.1
always @ (posedge CLKDIV)
begin
Q1 <= odd_samples[0];
Q2 <= even_samples[0];
Q3 <= odd_samples[1];
Q4 <= even_samples[1];
Q5 <= odd_samples[2];
Q6 <= even_samples[2];
Q7 <= odd_samples[3];
Q8 <= even_samples[3];
end
//pass through
assign O=D;
//not implemented
assign SHIFTOUT1=1'b0;
assign SHIFTOUT2=1'b0;
endmodule // ISERDESE2
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx espresso fetch unit
Fetch insn, advance PC (or take new branch address) on padv_i.
What we might want to do is have a 1-insn buffer here, so when the current
insn is fetched, but the main pipeline doesn't want it yet
indicate ibus errors
Copyright (C) 2012 Authors
Author(s): Julius Baxter <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_fetch_espresso
(/*AUTOARG*/
// Outputs
ibus_adr_o, ibus_req_o, ibus_burst_o, decode_insn_o,
next_fetch_done_o, fetch_rfa_adr_o, fetch_rfb_adr_o, pc_fetch_o,
pc_fetch_next_o, decode_except_ibus_err_o, fetch_advancing_o,
// Inputs
clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, padv_i,
branch_occur_i, branch_dest_i, du_restart_i, du_restart_pc_i,
fetch_take_exception_branch_i, execute_waiting_i, du_stall_i,
stepping_i
);
parameter OPTION_OPERAND_WIDTH = 32;
parameter OPTION_RF_ADDR_WIDTH = 5;
parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
`OR1K_RESET_VECTOR,8'd0};
input clk, rst;
// interface to ibus
output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o;
output ibus_req_o;
output ibus_burst_o;
input ibus_err_i;
input ibus_ack_i;
input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i;
// pipeline control input
input padv_i;
// interface to decode unit
output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o;
// Indication to pipeline control that the fetch is valid
output next_fetch_done_o;
output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;
output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;
// Signal back to the control
output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_o;
output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;
// branch/jump indication
input branch_occur_i;
input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i;
// restart signals from debug unit
input du_restart_i;
input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i;
input fetch_take_exception_branch_i;
input execute_waiting_i;
// CPU is stalled
input du_stall_i;
// We're single stepping - this should cause us to fetch only a single insn
input stepping_i;
// instruction ibus error indication out
output reg decode_except_ibus_err_o;
output fetch_advancing_o;
// registers
reg [OPTION_OPERAND_WIDTH-1:0] pc_fetch;
reg fetch_req;
reg next_insn_buffered;
reg [OPTION_OPERAND_WIDTH-1:0] insn_buffer;
reg branch_occur_r;
reg bus_access_done_re_r;
reg advancing_into_branch;
reg bus_access_done_r;
reg wait_for_exception_after_ibus_err;
wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next;
wire bus_access_done;
wire bus_access_done_fe;
wire branch_occur_re;
wire awkward_transition_to_branch_target;
wire taking_branch;
wire jal_buffered;
wire retain_fetch_pc;
assign taking_branch = branch_occur_i & padv_i;
assign bus_access_done = (ibus_ack_i | ibus_err_i) & !(taking_branch);
assign pc_fetch_next = pc_fetch + 4;
assign ibus_adr_o = pc_fetch;
assign ibus_req_o = fetch_req;
assign ibus_burst_o = 0;
assign fetch_advancing_o = (padv_i | fetch_take_exception_branch_i |
stepping_i) &
next_fetch_done_o;
// Early RF address fetch
assign fetch_rfa_adr_o = insn_buffer[`OR1K_RA_SELECT];
assign fetch_rfb_adr_o = insn_buffer[`OR1K_RB_SELECT];
assign jal_buffered = insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JALR ||
insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JAL;
assign retain_fetch_pc = jal_buffered & bus_access_done;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
pc_fetch <= OPTION_RESET_PC;
else if (fetch_take_exception_branch_i |
(((bus_access_done & !ibus_err_i) | taking_branch) &
(!execute_waiting_i | !next_insn_buffered) &
!retain_fetch_pc) |
awkward_transition_to_branch_target |
du_restart_i)
// next PC - are we going somewhere else or advancing?
pc_fetch <= du_restart_i ? du_restart_pc_i :
(fetch_take_exception_branch_i | taking_branch) ?
branch_dest_i : pc_fetch_next;
// Actually goes to pipeline control
assign pc_fetch_o = pc_fetch;
assign pc_fetch_next_o = pc_fetch_next;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
fetch_req <= 1;
else if (fetch_take_exception_branch_i | du_restart_i)
fetch_req <= 1;
else if (padv_i)
// Force de-assert of req signal when branching.
// This is to stop (ironically) the case where we've got the
// instruction we're branching to already coming in on the bus,
// which we usually don't assume will happen.
// TODO: fix things so that we don't have to force a penalty to make
// it work properly.
fetch_req <= !branch_occur_i & !du_stall_i;
else if (du_stall_i)
fetch_req <= fetch_req & !bus_access_done;
else if (!fetch_req & !execute_waiting_i &
!wait_for_exception_after_ibus_err & !retain_fetch_pc &
!du_stall_i & !stepping_i)
fetch_req <= 1;
else if (bus_access_done & (fetch_take_exception_branch_i |
execute_waiting_i | ibus_err_i | stepping_i))
fetch_req <= 0;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
begin
bus_access_done_r <= 0;
branch_occur_r <= 0;
end
else
begin
bus_access_done_r <= bus_access_done;
branch_occur_r <= branch_occur_i;
end
always @(posedge clk `OR_ASYNC_RST)
if (rst)
advancing_into_branch <= 0;
else
advancing_into_branch <= fetch_advancing_o & branch_occur_i;
assign next_fetch_done_o = (bus_access_done_r | next_insn_buffered) &
// Whenever we've just changed the fetch PC to
// take a branch this will gate off any ACKs we
// might get (legit or otherwise) from where we're
// getting our instructions from (bus/cache).
!(advancing_into_branch);
assign branch_occur_re = branch_occur_i & !branch_occur_r;
/* When this occurs we had the insn burst stream finish just as we
had a new branch address requested. Because the control logic will
immediately continue onto the delay slot instruction, the branch target
is only valid for 1 cycle. The PC out to the bus/cache will then need
to change 1 cycle after it requested the insn after the delay slot.
This is annoying for the bus control/cache logic, but should result in
less cycles wasted fetching something we don't need, and as well reduce
the number of flops as we don't need to save the target PC which we had
for only 1 cycle */
assign awkward_transition_to_branch_target = branch_occur_re &
bus_access_done_fe;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
else if (fetch_take_exception_branch_i | (du_stall_i & !execute_waiting_i))
// Put a NOP in the pipeline when starting exception - remove any state
// which may be causing the exception
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
else if ((padv_i & (
bus_access_done_r |
bus_access_done |
next_insn_buffered
) &
!branch_occur_r ) |
// This case is when we stalled to get the delay-slot instruction
// and we don't get enough padv to push it through the buffer
(branch_occur_i & padv_i & bus_access_done_re_r) |
(bus_access_done_fe & stepping_i))
decode_insn_o <= insn_buffer;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
decode_except_ibus_err_o <= 0;
else if ((padv_i | fetch_take_exception_branch_i) & branch_occur_i |
du_stall_i)
decode_except_ibus_err_o <= 0;
else if (fetch_req)
decode_except_ibus_err_o <= ibus_err_i;
// Register rising edge on bus_access_done
always @(posedge clk `OR_ASYNC_RST)
if (rst)
bus_access_done_re_r <= 0;
else
bus_access_done_re_r <= bus_access_done & !bus_access_done_r;
assign bus_access_done_fe = !bus_access_done & bus_access_done_r;
/* If insn_buffer contains the next insn we need, save that information
here */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
next_insn_buffered <= 0;
else if (fetch_take_exception_branch_i)
next_insn_buffered <= 0;
else if (padv_i)
// Next instruction is usually buffered when we've got bus ack and
// pipeline advance, except when we're branching (usually throw
// away the fetch when branch is being indicated)
next_insn_buffered <= ibus_ack_i & !branch_occur_i;
else if (ibus_ack_i & execute_waiting_i)
next_insn_buffered <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
insn_buffer <= {`OR1K_OPCODE_NOP,26'd0};
else if (ibus_ack_i & (!execute_waiting_i | !next_insn_buffered) &
// Don't buffer instruction after delay slot instruction
// (usually we're receiving it as taking branch is asserted)
// it could be another jump instruction and having it in
// the insn_buffer has annoying side-effects.
!taking_branch)
insn_buffer <= ibus_dat_i;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
wait_for_exception_after_ibus_err <= 0;
else if (fetch_take_exception_branch_i)
wait_for_exception_after_ibus_err <= 0;
else if (ibus_err_i)
wait_for_exception_after_ibus_err <= 1;
endmodule // mor1kx_fetch_espresso
|
module alu_tb;
wire [15:0] C;
wire overflow;
reg [15:0] A, B;
reg [4:0] alu_code;
reg enable;
alu alu(C, overflow, A, B, alu_code, enable);
initial begin
$display("ALU Testbench Initiated");
$dumpfile("alu.vcd");
$dumpvars;
$display("\ttime, \tA, \tB, \talu_code, \tC");
$monitor("%d, \t%h, \t%h, \t%b, \t%h", $time, A, B, alu_code, C);
enable = 1'b0;
end
initial begin
enable = 1'b1;
#5
alu_code = 5'b00000;
A = 16'h0000;
B = 16'h0001;
#5
A = 16'h000F;
B = 16'h000F;
#5
A = 16'h7F00;
B = 16'h0300;
#5
A = 16'hFF00;
B = 16'h0100;
#5
A = 16'h8100;
B = 16'h8000;
#5
alu_code = 5'b00010;
A = 16'h0000;
B = 16'h0001;
#5
A = 16'h000F;
B = 16'h000F;
#5
A = 16'h7F00;
B = 16'h0300;
#5
A = 16'hFF00;
B = 16'h0100;
#5
A = 16'h8100;
B = 16'h8000;
#5
alu_code = 5'b00100;
A = 16'h0000;
B = 16'h0100;
#5
A = 16'h0F00;
B = 16'h0F00;
#5
A = 16'h7FFF;
B = 16'h0300;
#5
A = 16'hFF00;
B = 16'h0100;
#5
A = 16'h8100;
B = 16'h8000;
#5
alu_code = 5'b00001;
A = 16'h0000;
B = 16'h0001;
#5
A = 16'h000F;
B = 16'h000F;
#5
A = 16'h7F00;
B = 16'h0300;
#5
A = 16'hFF00;
B = 16'h0100;
#5
A = 16'h8100;
B = 16'h8000;
#5
alu_code = 5'b00011;
A = 16'h0000;
B = 16'h0001;
#5
A = 16'hFF00;
B = 16'hFCE0;
#5
A = 16'h7F00;
B = 16'h0300;
#5
A = 16'hFF00;
B = 16'h0100;
#5
A = 16'h8100;
B = 16'h8000;
#5
alu_code = 5'b00101;
A = 16'h0000;
B = 16'h0100;
#5
A = 16'h000F;
B = 16'h000F;
#5
A = 16'h7F00;
B = 16'h0300;
#5
A = 16'hFF00;
B = 16'h0100;
#5
A = 16'h8000;
B = 16'h8000;
#5
$finish;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_2_V
`define SKY130_FD_SC_HD__DFSTP_2_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_2 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_2 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_2_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_2_V
`define SKY130_FD_SC_HD__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_2_V
|
// $Id: rtr_flit_buffer.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// flit buffer
//==============================================================================
module rtr_flit_buffer
(clk, reset, push_active, push_valid, push_head, push_tail, push_sel_ivc,
push_data, pop_active, pop_valid, pop_sel_ivc, pop_data, pop_tail_ivc,
pop_next_header_info, almost_empty_ivc, empty_ivc, full, errors_ivc);
`include "c_functions.v"
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of VCs
parameter num_vcs = 4;
// total buffer size per port in flits
parameter buffer_size = 32;
// width of payload data
parameter flit_data_width = 64;
// total number of bits of header information encoded in header flit payload
parameter header_info_width = 8;
// implementation variant for register file
parameter regfile_type = `REGFILE_TYPE_FF_2D;
// use explicit pipeline register between flit buffer and crossbar?
parameter explicit_pipeline_register = 1;
// gate buffer write port if bypassing
// (requires explicit pipeline register; may increase cycle time)
parameter gate_buffer_write = 0;
// select buffer management scheme
parameter mgmt_type = `FB_MGMT_TYPE_STATIC;
// improve timing for peek access
parameter fast_peek = 1;
// use atomic VC allocation
parameter atomic_vc_allocation = 1;
// allow bypassing through empty FIFO (i.e., empty & push & pop)
parameter enable_bypass = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// buffer size per VC in flits
localparam buffer_size_per_vc = buffer_size / num_vcs;
// address width required for selecting an individual entry
localparam addr_width = clogb(buffer_size);
// address width required for selecting an individual entry in a VC
localparam vc_addr_width = clogb(buffer_size_per_vc);
// difference between the two
localparam addr_pad_width = addr_width - vc_addr_width;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
input clk;
input reset;
// activity indicator for insertion
input push_active;
// insert data
input push_valid;
// inserting head flit
input push_head;
// inserting tail flit
input push_tail;
// VC to insert into
input [0:num_vcs-1] push_sel_ivc;
// data to be inserted
input [0:flit_data_width-1] push_data;
// activity indicator for read / removal
input pop_active;
// read and remove data
input pop_valid;
// VC to remove from
input [0:num_vcs-1] pop_sel_ivc;
// read data
// NOTE: This is valid in the cycle after pop_valid!
output [0:flit_data_width-1] pop_data;
wire [0:flit_data_width-1] pop_data;
// tail bit for the element to be read next in each VC
output [0:num_vcs-1] pop_tail_ivc;
wire [0:num_vcs-1] pop_tail_ivc;
// peek-ahead at the element in each VC after the one to be read next
output [0:header_info_width-1] pop_next_header_info;
wire [0:header_info_width-1] pop_next_header_info;
// VC state flags
output [0:num_vcs-1] almost_empty_ivc;
wire [0:num_vcs-1] almost_empty_ivc;
output [0:num_vcs-1] empty_ivc;
wire [0:num_vcs-1] empty_ivc;
output full;
wire full;
// internal error conditions detected
output [0:num_vcs*2-1] errors_ivc;
wire [0:num_vcs*2-1] errors_ivc;
wire [0:addr_width-1] push_addr;
wire [0:num_vcs*addr_width-1] pop_addr_ivc;
wire [0:num_vcs*addr_width-1] pop_next_addr_ivc;
generate
//------------------------------------------------------------------------
// tail flit tracking (atomic)
//------------------------------------------------------------------------
if(atomic_vc_allocation)
begin
wire [0:num_vcs-1] has_tail_ivc_s, has_tail_ivc_q;
assign has_tail_ivc_s
= push_valid ?
((has_tail_ivc_q &
~({num_vcs{push_head}} & push_sel_ivc)) |
({num_vcs{push_tail}} & push_sel_ivc)) :
has_tail_ivc_q;
c_dff
#(.width(num_vcs),
.reset_type(reset_type))
has_tail_ivcq
(.clk(clk),
.reset(reset),
.active(push_active),
.d(has_tail_ivc_s),
.q(has_tail_ivc_q));
assign pop_tail_ivc = almost_empty_ivc & has_tail_ivc_q;
end
case(mgmt_type)
`FB_MGMT_TYPE_STATIC:
begin
//-----------------------------------------------------------------
// tail flit tracking (non-atomic)
//-----------------------------------------------------------------
wire [0:num_vcs*addr_width-1] push_addr_ivc;
if(!atomic_vc_allocation)
begin
genvar ivc;
for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
begin:ivcs
wire push_sel;
assign push_sel = push_sel_ivc[ivc];
wire push_valid_sel;
assign push_valid_sel = push_valid & push_sel;
wire [0:addr_width-1] push_addr;
assign push_addr
= push_addr_ivc[ivc*addr_width:(ivc+1)*addr_width-1];
wire [0:buffer_size_per_vc-1] push_mask;
if(buffer_size_per_vc == 1)
assign push_mask = 1'b1;
else if(buffer_size_per_vc > 1)
begin
wire [0:vc_addr_width-1] push_vc_addr;
assign push_vc_addr
= push_addr[addr_pad_width:addr_width-1];
c_decode
#(.num_ports(buffer_size_per_vc),
.offset((ivc * buffer_size_per_vc) %
(1 << vc_addr_width)))
push_mask_dec
(.data_in(push_vc_addr),
.data_out(push_mask));
end
wire [0:buffer_size_per_vc-1] tail_s, tail_q;
assign tail_s
= push_valid_sel ?
(({buffer_size_per_vc{push_tail}} & push_mask) |
(tail_q & ~push_mask)) :
tail_q;
c_dff
#(.width(buffer_size_per_vc),
.reset_type(reset_type))
tailq
(.clk(clk),
.reset(1'b0),
.active(push_active),
.d(tail_s),
.q(tail_q));
wire [0:addr_width-1] pop_addr;
assign pop_addr
= pop_addr_ivc[ivc*addr_width:(ivc+1)*addr_width-1];
wire [0:buffer_size_per_vc-1] pop_mask;
if(buffer_size_per_vc == 1)
assign pop_mask = 1'b1;
else if(buffer_size_per_vc > 1)
begin
wire [0:vc_addr_width-1] pop_vc_addr;
assign pop_vc_addr
= pop_addr[addr_pad_width:addr_width-1];
c_decode
#(.num_ports(buffer_size_per_vc),
.offset((ivc * buffer_size_per_vc) %
(1 << vc_addr_width)))
pop_mask_dec
(.data_in(pop_vc_addr),
.data_out(pop_mask));
end
wire pop_tail;
c_select_1ofn
#(.num_ports(buffer_size_per_vc),
.width(1))
pop_tail_sel
(.select(pop_mask),
.data_in(tail_q),
.data_out(pop_tail));
assign pop_tail_ivc[ivc] = pop_tail;
end
end
//-----------------------------------------------------------------
// buffer control
//-----------------------------------------------------------------
wire [0:num_vcs-1] full_ivc;
c_samq_ctrl
#(.num_queues(num_vcs),
.num_slots_per_queue(buffer_size_per_vc),
.enable_bypass(enable_bypass),
.fast_pop_next_addr(fast_peek),
.reset_type(reset_type))
samqc
(.clk(clk),
.reset(reset),
.push_active(push_active),
.push_valid(push_valid),
.push_sel_qu(push_sel_ivc),
.push_addr_qu(push_addr_ivc),
.pop_active(pop_active),
.pop_valid(pop_valid),
.pop_sel_qu(pop_sel_ivc),
.pop_addr_qu(pop_addr_ivc),
.pop_next_addr_qu(pop_next_addr_ivc),
.almost_empty_qu(almost_empty_ivc),
.empty_qu(empty_ivc),
.full_qu(full_ivc),
.errors_qu(errors_ivc));
c_select_1ofn
#(.num_ports(num_vcs),
.width(addr_width))
push_addr_sel
(.select(push_sel_ivc),
.data_in(push_addr_ivc),
.data_out(push_addr));
assign full = &full_ivc;
end
`FB_MGMT_TYPE_DYNAMIC:
begin
//-----------------------------------------------------------------
// tail flit tracking (non-atomic)
//-----------------------------------------------------------------
if(!atomic_vc_allocation)
begin
wire [0:buffer_size-1] push_mask;
c_decode
#(.num_ports(buffer_size))
push_mask_dec
(.data_in(push_addr),
.data_out(push_mask));
wire [0:buffer_size-1] tail_s, tail_q;
assign tail_s = push_valid ?
(({buffer_size{push_tail}} & push_mask) |
(tail_q & ~push_mask)) :
tail_q;
c_dff
#(.width(buffer_size),
.reset_type(reset_type))
tailq
(.clk(clk),
.reset(1'b0),
.active(push_active),
.d(tail_s),
.q(tail_q));
genvar ivc;
for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
begin:ivcs
wire [0:addr_width-1] pop_addr;
assign pop_addr
= pop_addr_ivc[ivc*addr_width:(ivc+1)*addr_width-1];
wire [0:buffer_size-1] pop_mask;
c_decode
#(.num_ports(buffer_size))
pop_mask_dec
(.data_in(pop_addr),
.data_out(pop_mask));
wire pop_tail;
c_select_1ofn
#(.num_ports(buffer_size),
.width(1))
pop_tail_sel
(.select(pop_mask),
.data_in(tail_q),
.data_out(pop_tail));
assign pop_tail_ivc[ivc] = pop_tail;
end
end
//-----------------------------------------------------------------
// buffer control
//-----------------------------------------------------------------
c_damq_ctrl
#(.num_queues(num_vcs),
.num_slots(buffer_size),
.enable_bypass(enable_bypass),
.fast_pop_next_addr(fast_peek),
.reset_type(reset_type))
damqc
(.clk(clk),
.reset(reset),
.push_active(push_active),
.push_valid(push_valid),
.push_sel_qu(push_sel_ivc),
.push_addr(push_addr),
.pop_active(pop_active),
.pop_valid(pop_valid),
.pop_sel_qu(pop_sel_ivc),
.pop_addr_qu(pop_addr_ivc),
.pop_next_addr_qu(pop_next_addr_ivc),
.almost_empty_qu(almost_empty_ivc),
.empty_qu(empty_ivc),
.full(full),
.errors_qu(errors_ivc));
end
endcase
endgenerate
//---------------------------------------------------------------------------
// storage
//---------------------------------------------------------------------------
wire [0:addr_width-1] pop_addr;
c_select_1ofn
#(.num_ports(num_vcs),
.width(addr_width))
pop_addr_sel
(.select(pop_sel_ivc),
.data_in(pop_addr_ivc),
.data_out(pop_addr));
wire write_active;
assign write_active = push_active;
wire [0:addr_width-1] write_addr;
assign write_addr = push_addr;
wire [0:flit_data_width-1] write_data;
assign write_data = push_data;
wire [0:flit_data_width-1] read_data;
wire write_enable;
wire [0:addr_width-1] read_addr;
generate
if(explicit_pipeline_register)
begin
wire empty;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
empty_sel
(.select(pop_sel_ivc),
.data_in(empty_ivc),
.data_out(empty));
if(gate_buffer_write)
assign write_enable = push_valid & ~(pop_valid & empty);
else
assign write_enable = push_valid;
assign read_addr = pop_addr;
wire [0:flit_data_width-1] pop_data_s, pop_data_q;
assign pop_data_s
= pop_valid ? (empty ? write_data : read_data) : pop_data_q;
c_dff
#(.width(flit_data_width),
.reset_type(reset_type))
pop_dataq
(.clk(clk),
.reset(1'b0),
.active(pop_active),
.d(pop_data_s),
.q(pop_data_q));
assign pop_data = pop_data_q;
end
else
begin
assign write_enable = push_valid;
wire [0:addr_width-1] read_addr_s, read_addr_q;
assign read_addr_s = pop_valid ? pop_addr : read_addr_q;
c_dff
#(.width(addr_width),
.reset_type(reset_type))
read_addrq
(.clk(clk),
.reset(1'b0),
.active(pop_active),
.d(read_addr_s),
.q(read_addr_q));
assign read_addr = read_addr_q;
assign pop_data = read_data;
end
if(atomic_vc_allocation)
begin
c_regfile
#(.depth(buffer_size),
.width(flit_data_width),
.regfile_type(regfile_type))
bf
(.clk(clk),
.write_active(write_active),
.write_enable(write_enable),
.write_address(write_addr),
.write_data(write_data),
.read_address(read_addr),
.read_data(read_data));
assign pop_next_header_info = {header_info_width{1'bx}};
end
else
begin
wire [0:addr_width-1] pop_next_addr;
c_select_1ofn
#(.num_ports(num_vcs),
.width(addr_width))
pop_next_addr_sel
(.select(pop_sel_ivc),
.data_in(pop_next_addr_ivc),
.data_out(pop_next_addr));
wire [0:flit_data_width-1] pop_next_data;
c_regfile
#(.depth(buffer_size),
.width(flit_data_width),
.num_read_ports(2),
.regfile_type(regfile_type))
bf
(.clk(clk),
.write_active(write_active),
.write_enable(write_enable),
.write_address(write_addr),
.write_data(write_data),
.read_address({read_addr, pop_next_addr}),
.read_data({read_data, pop_next_data}));
assign pop_next_header_info = pop_next_data[0:header_info_width-1];
end
endgenerate
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module assignsigned();
parameter foo = 10;
reg signed [15:0] bar = -1;
wire baz;
assign baz = (bar < $signed(foo));
initial begin
#1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);
if (baz !== 1'b1) begin
$display("FAILED -- Compare returns %b instead of 1.", baz);
$finish;
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (osc_clk);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 1 will completely
// unroll the calculations, resulting in 128 rounds and a large, fast
// design.
//
// A setting of 2 will result in 64 rounds, with half the size and
// half the speed. 3 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
parameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
parameter LOOP_LOG2 = 0;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input osc_clk;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
`ifndef SIM
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("STAT")) midstate_vw_blk(.probe(), .source(midstate_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
`endif
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
`ifndef SIM
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce), .source());
`endif
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
`ifndef SIM
wire reset;
assign reset = 1'b0;
`else
reg reset = 1'b0; // NOTE: Reset is not currently used in the actual FPGA; for simulation only.
`endif
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd133;//32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
end
`ifdef SIM
if (!feedback_d1)
$display ("nonce: %8x\nhash2: %64x\n", nonce, hash2);
`endif
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: adc_data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module Sec4(
input A,
input B,
input C,
input AnalogLDir,
input AnalogRDir,
output Len,
output Ldir,
output Ren,
output Rdir
);
wire Z_A;
wire Z_B;
wire Z_C;
wire Ldir_int;
wire Len_int;
wire Rdir_int;
wire Ren_int;
wire Analog_select;
supply0 GND;
assign Analog_select = AnalogLDir & AnalogRDir;
inv invA(.A(A), .Z(Z_A));
inv invB(.A(B), .Z(Z_B));
inv invC(.A(C), .Z(Z_C));
section2_schematic lab2Logic(.A(Z_A),
.B(Z_B),
.C(Z_C),
.Ld(Ldir_int),
.Le(Len_int),
.Rd(Rdir_int),
.Re(Ren_int)
);
mux2 mux_1(.d0(AnalogLDir), .d1(Ldir_int), .s(Analog_select), .y(Ldir));
mux2 mux_2(.d0(GND), .d1(Len_int), .s(Analog_select), .y(Len));
mux2 mux_3(.d0(AnalogRDir), .d1(Rdir_int), .s(Analog_select), .y(Rdir));
mux2 mux_4(.d0(GND), .d1(Ren_int), .s(Analog_select), .y(Ren));
endmodule
module mux2(
input d0,
input d1,
input s,
output y);
assign y = (s) ? d1 : d0;
endmodule
module inv (input A,
output Z);
assign Z = ~A;
endmodule
|
`timescale 1ns/1ps
module lookup(
clk,
reset,
p2k_valid,
p2k_ingress,
p2k_rloc_src,
p2k_eid_dst,
p2k_metadata,
mode,
xtr_id,
action2parser_en,
transmit2action_en,
pkt_buffer_label_valid_in,
pkt_buffer_label_in,
pkt_head_valid_in,
pkt_head_in,
fragment_valid,
fragment_pkt_buffer_label,
outrule_valid,
outrule,
pkt_buffer_label_valid_out,
pkt_buffer_label_out,
pkt_head_valid_out,
pkt_head_out,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input p2k_valid;
input [7:0] p2k_ingress;
input [127:0] p2k_rloc_src;
input [127:0] p2k_eid_dst;
input [71:0] p2k_metadata;
input mode;
input [7:0] xtr_id;
output action2parser_en;
input transmit2action_en;
input pkt_buffer_label_valid_in;
input [31:0] pkt_buffer_label_in;
input pkt_head_valid_in;
input [138:0] pkt_head_in;
output fragment_valid;
output [31:0] fragment_pkt_buffer_label;
output outrule_valid;
output [15:0] outrule;
output pkt_buffer_label_valid_out;
output [31:0] pkt_buffer_label_out;
output pkt_head_valid_out;
output [138:0] pkt_head_out;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output [31:0] localbus_data_out;
wire fragment_valid;
wire [31:0] fragment_pkt_buffer_label;
wire action2parser_en;
wire outrule_valid;
wire [15:0] outrule;
wire pkt_buffer_label_valid_out;
wire [31:0] pkt_buffer_label_out;
wire pkt_head_valid_out;
wire [138:0] pkt_head_out;
wire localbus_ack_n;
wire [31:0] localbus_data_out;
wire k2m_metadata_valid;
wire [107:0] k2m_metadata;
wire action_valid;
wire [15:0] action;
wire action_data_valid;
wire [351:0] action_data;
key_gen key_gen(
.clk(clk),
.reset(reset),
.p2k_valid(p2k_valid),
.p2k_ingress(p2k_ingress),
.p2k_rloc_src(p2k_rloc_src),
.p2k_eid_dst(p2k_eid_dst),
.p2k_metadata(p2k_metadata[71:64]),
.mode(mode),
.k2m_metadata_valid(k2m_metadata_valid),
.k2m_metadata(k2m_metadata)
);
match match(
.clk(clk),
.reset(reset),
.metadata_valid(k2m_metadata_valid),
.metadata(k2m_metadata),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
.action_valid(action_valid),
.action(action),
.action_data_valid(action_data_valid),
.action_data(action_data)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Simple parameter declaration
//
// D: Declare a parameter value, then assign it to a variable.
// D: Check the value of the variable.
//
module main();
parameter VAL_1 = 16'h0001;
parameter VAL_2 = 16'h5432;
reg [15:0] test_var;
initial // Excitation block
begin
test_var = VAL_1 ;
#5 ;
test_var = VAL_2 ;
#5 ;
end
initial // Validation block
begin
#1 ;
if(test_var != 16'h0001)
begin
$display("FAILED - param 1st assign didn't work\n");
$finish ;
end
#5 ;
if(test_var != 16'h5432)
begin
$display("FAILED - param 2nd assign didn't work\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// Signals in the JTAG clock domain
input wire tck,
input wire tdi,
output wire tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire clk,
input wire reset_n,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
wire jtag_clock_reset_n; // system reset is synchronized with tck
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(tck),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(tck),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(tck),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_BNC_P_read_AW30h for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_BNC_P_read_AW30h
// Module Name: NPCG_Toggle_BNC_P_read_AW30h
// File Name: NPCG_Toggle_BNC_P_read_AW30h.v
//
// Version: v1.0.0
//
// Description: Page read trigger FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_BNC_P_read_AW30h
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
iColAddress ,
iRowAddress ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
input [15:0] iColAddress ;
input [23:0] iRowAddress ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
reg [NumberOfWays - 1:0] rTargetWay ;
reg [15:0] rColAddress ;
reg [23:0] rRowAddress ;
wire wModuleTriggered;
wire wTMStart ;
reg [7:0] rPMTrigger ;
reg [2:0] rPCommandOption ;
reg [15:0] rNumOfData ;
reg [7:0] rCAData ;
reg rPMCommandOrAddress ;
localparam State_Idle = 4'b0000 ;
localparam State_NCALIssue = 4'b0001 ;
localparam State_NCmdWrite0 = 4'b0011 ;
localparam State_NAddrWrite0 = 4'b0010 ;
localparam State_NAddrWrite1 = 4'b0110 ;
localparam State_NAddrWrite2 = 4'b0111 ;
localparam State_NAddrWrite3 = 4'b0101 ;
localparam State_NAddrWrite4 = 4'b0100 ;
localparam State_NCmdWrite1 = 4'b1100 ;
localparam State_NTMIssue = 4'b1101 ;
localparam State_WaitDone = 4'b1111 ;
reg [3:0] rCurState ;
reg [3:0] rNextState ;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_NCALIssue:State_Idle;
State_NCALIssue:
rNextState <= (iPM_Ready)?State_NCmdWrite0:State_NCALIssue;
State_NCmdWrite0:
rNextState <= State_NAddrWrite0;
State_NAddrWrite0:
rNextState <= State_NAddrWrite1;
State_NAddrWrite1:
rNextState <= State_NAddrWrite2;
State_NAddrWrite2:
rNextState <= State_NAddrWrite3;
State_NAddrWrite3:
rNextState <= State_NAddrWrite4;
State_NAddrWrite4:
rNextState <= State_NCmdWrite1;
State_NCmdWrite1:
rNextState <= State_NTMIssue;
State_NTMIssue:
rNextState <= (wTMStart)?State_WaitDone:State_NTMIssue;
State_WaitDone:
rNextState <= (oLastStep)?State_Idle:State_WaitDone;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b000000);
assign wTMStart = (rCurState == State_NTMIssue) & iPM_LastStep[3];
assign oCMDReady = (rCurState == State_Idle);
always @ (posedge iSystemClock)
if (iReset)
begin
rTargetWay <= {(NumberOfWays){1'b0}};
rColAddress <= 16'b0;
rRowAddress <= 24'b0;
end
else
if (wModuleTriggered && (rCurState == State_Idle))
begin
rTargetWay <= iWaySelect ;
rColAddress <= iColAddress ;
rRowAddress <= iRowAddress ;
end
always @ (*)
case (rCurState)
State_NCALIssue:
rPMTrigger <= 8'b00001000;
State_NTMIssue:
rPMTrigger <= 8'b00000001;
default:
rPMTrigger <= 0;
endcase
always @ (*)
case (rCurState)
State_NTMIssue:
rPCommandOption[2:0] <= 3'b110;
default:
rPCommandOption[2:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCALIssue:
rNumOfData[15:0] <= 16'd6; // 1 cmd + 5 addr + 1 cmd = 7 (=> 6)
State_NTMIssue:
rNumOfData[15:0] <= 16'd3; // 40 ns
default:
rNumOfData[15:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCmdWrite0:
rPMCommandOrAddress <= 1'b0;
State_NCmdWrite1:
rPMCommandOrAddress <= 1'b0;
State_NAddrWrite0:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite1:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite2:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite3:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite4:
rPMCommandOrAddress <= 1'b1;
default:
rPMCommandOrAddress <= 1'b0;
endcase
always @ (posedge iSystemClock)
if (iReset)
rCAData <= 0;
else
case (rNextState)
State_NCmdWrite0:
rCAData <= 8'h00;
State_NAddrWrite0:
rCAData <= rColAddress[7:0];
State_NAddrWrite1:
rCAData <= rColAddress[15:8];
State_NAddrWrite2:
rCAData <= rRowAddress[7:0];
State_NAddrWrite3:
rCAData <= rRowAddress[15:8];
State_NAddrWrite4:
rCAData <= rRowAddress[23:16];
State_NCmdWrite1:
rCAData <= 8'h30;
default:
rCAData <= 0;
endcase
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_WaitDone) & iPM_LastStep[0];
assign oPM_PCommand = rPMTrigger;
assign oPM_PCommandOption = rPCommandOption;//1'b0;
assign oPM_TargetWay = rTargetWay;
assign oPM_NumOfData = rNumOfData; //16'd6;
assign oPM_CASelect = rPMCommandOrAddress;
assign oPM_CAData = rCAData;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//-----------------------------------------------------------------------------
// system_processing_system7_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "processing_system7_v4_03_a" *)
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_ENET0_PERIPHERAL_ENABLE = 1,C_USB0_PERIPHERAL_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_DDR_V4.00.A_C_S_AXI_HP3_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP2_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP1_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP0_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP3_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP2_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP1_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF,C_GPIO_PERIPHERAL_ENABLE = 1,C_GPIO_V2.00.A_C_EN_EMIO_GPIO = 0,C:GPIO_EMIO_GPIO_WIDTH = 64,C_CAN_PERIPHERAL_FREQMHZ = 100,C_FPGA3_PERIPHERAL_FREQMHZ = 25.000000,C_FPGA0_PERIPHERAL_FREQMHZ = 100.000000,C_PRESET_GLOBAL_DEFAULT = powerup,C_FPGA1_PERIPHERAL_FREQMHZ = 150.000000,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_FPGA_SPEED = -1,C_PRESET_FPGA_PARTNUMBER = xc7z020clg484-1,C_SD0_PERIPHERAL_ENABLE = 1,C_UART1_PERIPHERAL_ENABLE = 1}" *)
module system_processing_system7_0_wrapper
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0] M_AXI_GP0_ARID;
output [11:0] M_AXI_GP0_AWID;
output [11:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0] M_AXI_GP0_BID;
input [11:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0] M_AXI_GP1_ARID;
output [11:0] M_AXI_GP1_AWID;
output [11:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0] M_AXI_GP1_BID;
input [11:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [1:0] S_AXI_HP0_BID;
output [1:0] S_AXI_HP0_RID;
output [63:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [1:0] S_AXI_HP0_ARID;
input [1:0] S_AXI_HP0_AWID;
input [1:0] S_AXI_HP0_WID;
input [63:0] S_AXI_HP0_WDATA;
input [7:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [63:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [63:0] S_AXI_HP1_WDATA;
input [7:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [63:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [63:0] S_AXI_HP2_WDATA;
input [7:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [63:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [63:0] S_AXI_HP3_WDATA;
input [7:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [0:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_ENET0_PERIPHERAL_ENABLE = 1,C_USB0_PERIPHERAL_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_DDR_V4.00.A_C_S_AXI_HP3_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP2_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP1_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP0_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP3_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP2_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP1_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF,C_GPIO_PERIPHERAL_ENABLE = 1,C_GPIO_V2.00.A_C_EN_EMIO_GPIO = 0,C:GPIO_EMIO_GPIO_WIDTH = 64,C_CAN_PERIPHERAL_FREQMHZ = 100,C_FPGA3_PERIPHERAL_FREQMHZ = 25.000000,C_FPGA0_PERIPHERAL_FREQMHZ = 100.000000,C_PRESET_GLOBAL_DEFAULT = powerup,C_FPGA1_PERIPHERAL_FREQMHZ = 150.000000,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_FPGA_SPEED = -1,C_PRESET_FPGA_PARTNUMBER = xc7z020clg484-1,C_SD0_PERIPHERAL_ENABLE = 1,C_UART1_PERIPHERAL_ENABLE = 1}" *)
processing_system7
#(
.C_EN_EMIO_ENET0 ( 1 ),
.C_EN_EMIO_ENET1 ( 0 ),
.C_EN_EMIO_TRACE ( 0 ),
.C_INCLUDE_TRACE_BUFFER ( 0 ),
.C_TRACE_BUFFER_FIFO_SIZE ( 128 ),
.USE_TRACE_DATA_EDGE_DETECTOR ( 0 ),
.C_TRACE_BUFFER_CLOCK_DELAY ( 12 ),
.C_EMIO_GPIO_WIDTH ( 64 ),
.C_INCLUDE_ACP_TRANS_CHECK ( 0 ),
.C_USE_DEFAULT_ACP_USER_VAL ( 0 ),
.C_S_AXI_ACP_ARUSER_VAL ( 31 ),
.C_S_AXI_ACP_AWUSER_VAL ( 31 ),
.C_DQ_WIDTH ( 32 ),
.C_DQS_WIDTH ( 4 ),
.C_DM_WIDTH ( 4 ),
.C_MIO_PRIMITIVE ( 54 ),
.C_PACKAGE_NAME ( "clg484" ),
.C_PS7_SI_REV ( "PRODUCTION" ),
.C_M_AXI_GP0_ID_WIDTH ( 12 ),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP ( 0 ),
.C_M_AXI_GP1_ID_WIDTH ( 12 ),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP ( 0 ),
.C_S_AXI_GP0_ID_WIDTH ( 6 ),
.C_S_AXI_GP1_ID_WIDTH ( 6 ),
.C_S_AXI_ACP_ID_WIDTH ( 3 ),
.C_S_AXI_HP0_ID_WIDTH ( 2 ),
.C_S_AXI_HP0_DATA_WIDTH ( 64 ),
.C_S_AXI_HP1_ID_WIDTH ( 6 ),
.C_S_AXI_HP1_DATA_WIDTH ( 64 ),
.C_S_AXI_HP2_ID_WIDTH ( 6 ),
.C_S_AXI_HP2_DATA_WIDTH ( 64 ),
.C_S_AXI_HP3_ID_WIDTH ( 6 ),
.C_S_AXI_HP3_DATA_WIDTH ( 64 ),
.C_M_AXI_GP0_THREAD_ID_WIDTH ( 12 ),
.C_M_AXI_GP1_THREAD_ID_WIDTH ( 12 ),
.C_NUM_F2P_INTR_INPUTS ( 1 ),
.C_FCLK_CLK0_BUF ( "TRUE" ),
.C_FCLK_CLK1_BUF ( "FALSE" ),
.C_FCLK_CLK2_BUF ( "FALSE" ),
.C_FCLK_CLK3_BUF ( "TRUE" )
)
processing_system7_0 (
.CAN0_PHY_TX ( CAN0_PHY_TX ),
.CAN0_PHY_RX ( CAN0_PHY_RX ),
.CAN1_PHY_TX ( CAN1_PHY_TX ),
.CAN1_PHY_RX ( CAN1_PHY_RX ),
.ENET0_GMII_TX_EN ( ENET0_GMII_TX_EN ),
.ENET0_GMII_TX_ER ( ENET0_GMII_TX_ER ),
.ENET0_MDIO_MDC ( ENET0_MDIO_MDC ),
.ENET0_MDIO_O ( ENET0_MDIO_O ),
.ENET0_MDIO_T ( ENET0_MDIO_T ),
.ENET0_PTP_DELAY_REQ_RX ( ENET0_PTP_DELAY_REQ_RX ),
.ENET0_PTP_DELAY_REQ_TX ( ENET0_PTP_DELAY_REQ_TX ),
.ENET0_PTP_PDELAY_REQ_RX ( ENET0_PTP_PDELAY_REQ_RX ),
.ENET0_PTP_PDELAY_REQ_TX ( ENET0_PTP_PDELAY_REQ_TX ),
.ENET0_PTP_PDELAY_RESP_RX ( ENET0_PTP_PDELAY_RESP_RX ),
.ENET0_PTP_PDELAY_RESP_TX ( ENET0_PTP_PDELAY_RESP_TX ),
.ENET0_PTP_SYNC_FRAME_RX ( ENET0_PTP_SYNC_FRAME_RX ),
.ENET0_PTP_SYNC_FRAME_TX ( ENET0_PTP_SYNC_FRAME_TX ),
.ENET0_SOF_RX ( ENET0_SOF_RX ),
.ENET0_SOF_TX ( ENET0_SOF_TX ),
.ENET0_GMII_TXD ( ENET0_GMII_TXD ),
.ENET0_GMII_COL ( ENET0_GMII_COL ),
.ENET0_GMII_CRS ( ENET0_GMII_CRS ),
.ENET0_EXT_INTIN ( ENET0_EXT_INTIN ),
.ENET0_GMII_RX_CLK ( ENET0_GMII_RX_CLK ),
.ENET0_GMII_RX_DV ( ENET0_GMII_RX_DV ),
.ENET0_GMII_RX_ER ( ENET0_GMII_RX_ER ),
.ENET0_GMII_TX_CLK ( ENET0_GMII_TX_CLK ),
.ENET0_MDIO_I ( ENET0_MDIO_I ),
.ENET0_GMII_RXD ( ENET0_GMII_RXD ),
.ENET1_GMII_TX_EN ( ENET1_GMII_TX_EN ),
.ENET1_GMII_TX_ER ( ENET1_GMII_TX_ER ),
.ENET1_MDIO_MDC ( ENET1_MDIO_MDC ),
.ENET1_MDIO_O ( ENET1_MDIO_O ),
.ENET1_MDIO_T ( ENET1_MDIO_T ),
.ENET1_PTP_DELAY_REQ_RX ( ENET1_PTP_DELAY_REQ_RX ),
.ENET1_PTP_DELAY_REQ_TX ( ENET1_PTP_DELAY_REQ_TX ),
.ENET1_PTP_PDELAY_REQ_RX ( ENET1_PTP_PDELAY_REQ_RX ),
.ENET1_PTP_PDELAY_REQ_TX ( ENET1_PTP_PDELAY_REQ_TX ),
.ENET1_PTP_PDELAY_RESP_RX ( ENET1_PTP_PDELAY_RESP_RX ),
.ENET1_PTP_PDELAY_RESP_TX ( ENET1_PTP_PDELAY_RESP_TX ),
.ENET1_PTP_SYNC_FRAME_RX ( ENET1_PTP_SYNC_FRAME_RX ),
.ENET1_PTP_SYNC_FRAME_TX ( ENET1_PTP_SYNC_FRAME_TX ),
.ENET1_SOF_RX ( ENET1_SOF_RX ),
.ENET1_SOF_TX ( ENET1_SOF_TX ),
.ENET1_GMII_TXD ( ENET1_GMII_TXD ),
.ENET1_GMII_COL ( ENET1_GMII_COL ),
.ENET1_GMII_CRS ( ENET1_GMII_CRS ),
.ENET1_EXT_INTIN ( ENET1_EXT_INTIN ),
.ENET1_GMII_RX_CLK ( ENET1_GMII_RX_CLK ),
.ENET1_GMII_RX_DV ( ENET1_GMII_RX_DV ),
.ENET1_GMII_RX_ER ( ENET1_GMII_RX_ER ),
.ENET1_GMII_TX_CLK ( ENET1_GMII_TX_CLK ),
.ENET1_MDIO_I ( ENET1_MDIO_I ),
.ENET1_GMII_RXD ( ENET1_GMII_RXD ),
.GPIO_I ( GPIO_I ),
.GPIO_O ( GPIO_O ),
.GPIO_T ( GPIO_T ),
.I2C0_SDA_I ( I2C0_SDA_I ),
.I2C0_SDA_O ( I2C0_SDA_O ),
.I2C0_SDA_T ( I2C0_SDA_T ),
.I2C0_SCL_I ( I2C0_SCL_I ),
.I2C0_SCL_O ( I2C0_SCL_O ),
.I2C0_SCL_T ( I2C0_SCL_T ),
.I2C1_SDA_I ( I2C1_SDA_I ),
.I2C1_SDA_O ( I2C1_SDA_O ),
.I2C1_SDA_T ( I2C1_SDA_T ),
.I2C1_SCL_I ( I2C1_SCL_I ),
.I2C1_SCL_O ( I2C1_SCL_O ),
.I2C1_SCL_T ( I2C1_SCL_T ),
.PJTAG_TCK ( PJTAG_TCK ),
.PJTAG_TMS ( PJTAG_TMS ),
.PJTAG_TD_I ( PJTAG_TD_I ),
.PJTAG_TD_T ( PJTAG_TD_T ),
.PJTAG_TD_O ( PJTAG_TD_O ),
.SDIO0_CLK ( SDIO0_CLK ),
.SDIO0_CLK_FB ( SDIO0_CLK_FB ),
.SDIO0_CMD_O ( SDIO0_CMD_O ),
.SDIO0_CMD_I ( SDIO0_CMD_I ),
.SDIO0_CMD_T ( SDIO0_CMD_T ),
.SDIO0_DATA_I ( SDIO0_DATA_I ),
.SDIO0_DATA_O ( SDIO0_DATA_O ),
.SDIO0_DATA_T ( SDIO0_DATA_T ),
.SDIO0_LED ( SDIO0_LED ),
.SDIO0_CDN ( SDIO0_CDN ),
.SDIO0_WP ( SDIO0_WP ),
.SDIO0_BUSPOW ( SDIO0_BUSPOW ),
.SDIO0_BUSVOLT ( SDIO0_BUSVOLT ),
.SDIO1_CLK ( SDIO1_CLK ),
.SDIO1_CLK_FB ( SDIO1_CLK_FB ),
.SDIO1_CMD_O ( SDIO1_CMD_O ),
.SDIO1_CMD_I ( SDIO1_CMD_I ),
.SDIO1_CMD_T ( SDIO1_CMD_T ),
.SDIO1_DATA_I ( SDIO1_DATA_I ),
.SDIO1_DATA_O ( SDIO1_DATA_O ),
.SDIO1_DATA_T ( SDIO1_DATA_T ),
.SDIO1_LED ( SDIO1_LED ),
.SDIO1_CDN ( SDIO1_CDN ),
.SDIO1_WP ( SDIO1_WP ),
.SDIO1_BUSPOW ( SDIO1_BUSPOW ),
.SDIO1_BUSVOLT ( SDIO1_BUSVOLT ),
.SPI0_SCLK_I ( SPI0_SCLK_I ),
.SPI0_SCLK_O ( SPI0_SCLK_O ),
.SPI0_SCLK_T ( SPI0_SCLK_T ),
.SPI0_MOSI_I ( SPI0_MOSI_I ),
.SPI0_MOSI_O ( SPI0_MOSI_O ),
.SPI0_MOSI_T ( SPI0_MOSI_T ),
.SPI0_MISO_I ( SPI0_MISO_I ),
.SPI0_MISO_O ( SPI0_MISO_O ),
.SPI0_MISO_T ( SPI0_MISO_T ),
.SPI0_SS_I ( SPI0_SS_I ),
.SPI0_SS_O ( SPI0_SS_O ),
.SPI0_SS1_O ( SPI0_SS1_O ),
.SPI0_SS2_O ( SPI0_SS2_O ),
.SPI0_SS_T ( SPI0_SS_T ),
.SPI1_SCLK_I ( SPI1_SCLK_I ),
.SPI1_SCLK_O ( SPI1_SCLK_O ),
.SPI1_SCLK_T ( SPI1_SCLK_T ),
.SPI1_MOSI_I ( SPI1_MOSI_I ),
.SPI1_MOSI_O ( SPI1_MOSI_O ),
.SPI1_MOSI_T ( SPI1_MOSI_T ),
.SPI1_MISO_I ( SPI1_MISO_I ),
.SPI1_MISO_O ( SPI1_MISO_O ),
.SPI1_MISO_T ( SPI1_MISO_T ),
.SPI1_SS_I ( SPI1_SS_I ),
.SPI1_SS_O ( SPI1_SS_O ),
.SPI1_SS1_O ( SPI1_SS1_O ),
.SPI1_SS2_O ( SPI1_SS2_O ),
.SPI1_SS_T ( SPI1_SS_T ),
.UART0_DTRN ( UART0_DTRN ),
.UART0_RTSN ( UART0_RTSN ),
.UART0_TX ( UART0_TX ),
.UART0_CTSN ( UART0_CTSN ),
.UART0_DCDN ( UART0_DCDN ),
.UART0_DSRN ( UART0_DSRN ),
.UART0_RIN ( UART0_RIN ),
.UART0_RX ( UART0_RX ),
.UART1_DTRN ( UART1_DTRN ),
.UART1_RTSN ( UART1_RTSN ),
.UART1_TX ( UART1_TX ),
.UART1_CTSN ( UART1_CTSN ),
.UART1_DCDN ( UART1_DCDN ),
.UART1_DSRN ( UART1_DSRN ),
.UART1_RIN ( UART1_RIN ),
.UART1_RX ( UART1_RX ),
.TTC0_WAVE0_OUT ( TTC0_WAVE0_OUT ),
.TTC0_WAVE1_OUT ( TTC0_WAVE1_OUT ),
.TTC0_WAVE2_OUT ( TTC0_WAVE2_OUT ),
.TTC0_CLK0_IN ( TTC0_CLK0_IN ),
.TTC0_CLK1_IN ( TTC0_CLK1_IN ),
.TTC0_CLK2_IN ( TTC0_CLK2_IN ),
.TTC1_WAVE0_OUT ( TTC1_WAVE0_OUT ),
.TTC1_WAVE1_OUT ( TTC1_WAVE1_OUT ),
.TTC1_WAVE2_OUT ( TTC1_WAVE2_OUT ),
.TTC1_CLK0_IN ( TTC1_CLK0_IN ),
.TTC1_CLK1_IN ( TTC1_CLK1_IN ),
.TTC1_CLK2_IN ( TTC1_CLK2_IN ),
.WDT_CLK_IN ( WDT_CLK_IN ),
.WDT_RST_OUT ( WDT_RST_OUT ),
.TRACE_CLK ( TRACE_CLK ),
.TRACE_CTL ( TRACE_CTL ),
.TRACE_DATA ( TRACE_DATA ),
.USB0_PORT_INDCTL ( USB0_PORT_INDCTL ),
.USB1_PORT_INDCTL ( USB1_PORT_INDCTL ),
.USB0_VBUS_PWRSELECT ( USB0_VBUS_PWRSELECT ),
.USB1_VBUS_PWRSELECT ( USB1_VBUS_PWRSELECT ),
.USB0_VBUS_PWRFAULT ( USB0_VBUS_PWRFAULT ),
.USB1_VBUS_PWRFAULT ( USB1_VBUS_PWRFAULT ),
.SRAM_INTIN ( SRAM_INTIN ),
.M_AXI_GP0_ARESETN ( M_AXI_GP0_ARESETN ),
.M_AXI_GP0_ARVALID ( M_AXI_GP0_ARVALID ),
.M_AXI_GP0_AWVALID ( M_AXI_GP0_AWVALID ),
.M_AXI_GP0_BREADY ( M_AXI_GP0_BREADY ),
.M_AXI_GP0_RREADY ( M_AXI_GP0_RREADY ),
.M_AXI_GP0_WLAST ( M_AXI_GP0_WLAST ),
.M_AXI_GP0_WVALID ( M_AXI_GP0_WVALID ),
.M_AXI_GP0_ARID ( M_AXI_GP0_ARID ),
.M_AXI_GP0_AWID ( M_AXI_GP0_AWID ),
.M_AXI_GP0_WID ( M_AXI_GP0_WID ),
.M_AXI_GP0_ARBURST ( M_AXI_GP0_ARBURST ),
.M_AXI_GP0_ARLOCK ( M_AXI_GP0_ARLOCK ),
.M_AXI_GP0_ARSIZE ( M_AXI_GP0_ARSIZE ),
.M_AXI_GP0_AWBURST ( M_AXI_GP0_AWBURST ),
.M_AXI_GP0_AWLOCK ( M_AXI_GP0_AWLOCK ),
.M_AXI_GP0_AWSIZE ( M_AXI_GP0_AWSIZE ),
.M_AXI_GP0_ARPROT ( M_AXI_GP0_ARPROT ),
.M_AXI_GP0_AWPROT ( M_AXI_GP0_AWPROT ),
.M_AXI_GP0_ARADDR ( M_AXI_GP0_ARADDR ),
.M_AXI_GP0_AWADDR ( M_AXI_GP0_AWADDR ),
.M_AXI_GP0_WDATA ( M_AXI_GP0_WDATA ),
.M_AXI_GP0_ARCACHE ( M_AXI_GP0_ARCACHE ),
.M_AXI_GP0_ARLEN ( M_AXI_GP0_ARLEN ),
.M_AXI_GP0_ARQOS ( M_AXI_GP0_ARQOS ),
.M_AXI_GP0_AWCACHE ( M_AXI_GP0_AWCACHE ),
.M_AXI_GP0_AWLEN ( M_AXI_GP0_AWLEN ),
.M_AXI_GP0_AWQOS ( M_AXI_GP0_AWQOS ),
.M_AXI_GP0_WSTRB ( M_AXI_GP0_WSTRB ),
.M_AXI_GP0_ACLK ( M_AXI_GP0_ACLK ),
.M_AXI_GP0_ARREADY ( M_AXI_GP0_ARREADY ),
.M_AXI_GP0_AWREADY ( M_AXI_GP0_AWREADY ),
.M_AXI_GP0_BVALID ( M_AXI_GP0_BVALID ),
.M_AXI_GP0_RLAST ( M_AXI_GP0_RLAST ),
.M_AXI_GP0_RVALID ( M_AXI_GP0_RVALID ),
.M_AXI_GP0_WREADY ( M_AXI_GP0_WREADY ),
.M_AXI_GP0_BID ( M_AXI_GP0_BID ),
.M_AXI_GP0_RID ( M_AXI_GP0_RID ),
.M_AXI_GP0_BRESP ( M_AXI_GP0_BRESP ),
.M_AXI_GP0_RRESP ( M_AXI_GP0_RRESP ),
.M_AXI_GP0_RDATA ( M_AXI_GP0_RDATA ),
.M_AXI_GP1_ARESETN ( M_AXI_GP1_ARESETN ),
.M_AXI_GP1_ARVALID ( M_AXI_GP1_ARVALID ),
.M_AXI_GP1_AWVALID ( M_AXI_GP1_AWVALID ),
.M_AXI_GP1_BREADY ( M_AXI_GP1_BREADY ),
.M_AXI_GP1_RREADY ( M_AXI_GP1_RREADY ),
.M_AXI_GP1_WLAST ( M_AXI_GP1_WLAST ),
.M_AXI_GP1_WVALID ( M_AXI_GP1_WVALID ),
.M_AXI_GP1_ARID ( M_AXI_GP1_ARID ),
.M_AXI_GP1_AWID ( M_AXI_GP1_AWID ),
.M_AXI_GP1_WID ( M_AXI_GP1_WID ),
.M_AXI_GP1_ARBURST ( M_AXI_GP1_ARBURST ),
.M_AXI_GP1_ARLOCK ( M_AXI_GP1_ARLOCK ),
.M_AXI_GP1_ARSIZE ( M_AXI_GP1_ARSIZE ),
.M_AXI_GP1_AWBURST ( M_AXI_GP1_AWBURST ),
.M_AXI_GP1_AWLOCK ( M_AXI_GP1_AWLOCK ),
.M_AXI_GP1_AWSIZE ( M_AXI_GP1_AWSIZE ),
.M_AXI_GP1_ARPROT ( M_AXI_GP1_ARPROT ),
.M_AXI_GP1_AWPROT ( M_AXI_GP1_AWPROT ),
.M_AXI_GP1_ARADDR ( M_AXI_GP1_ARADDR ),
.M_AXI_GP1_AWADDR ( M_AXI_GP1_AWADDR ),
.M_AXI_GP1_WDATA ( M_AXI_GP1_WDATA ),
.M_AXI_GP1_ARCACHE ( M_AXI_GP1_ARCACHE ),
.M_AXI_GP1_ARLEN ( M_AXI_GP1_ARLEN ),
.M_AXI_GP1_ARQOS ( M_AXI_GP1_ARQOS ),
.M_AXI_GP1_AWCACHE ( M_AXI_GP1_AWCACHE ),
.M_AXI_GP1_AWLEN ( M_AXI_GP1_AWLEN ),
.M_AXI_GP1_AWQOS ( M_AXI_GP1_AWQOS ),
.M_AXI_GP1_WSTRB ( M_AXI_GP1_WSTRB ),
.M_AXI_GP1_ACLK ( M_AXI_GP1_ACLK ),
.M_AXI_GP1_ARREADY ( M_AXI_GP1_ARREADY ),
.M_AXI_GP1_AWREADY ( M_AXI_GP1_AWREADY ),
.M_AXI_GP1_BVALID ( M_AXI_GP1_BVALID ),
.M_AXI_GP1_RLAST ( M_AXI_GP1_RLAST ),
.M_AXI_GP1_RVALID ( M_AXI_GP1_RVALID ),
.M_AXI_GP1_WREADY ( M_AXI_GP1_WREADY ),
.M_AXI_GP1_BID ( M_AXI_GP1_BID ),
.M_AXI_GP1_RID ( M_AXI_GP1_RID ),
.M_AXI_GP1_BRESP ( M_AXI_GP1_BRESP ),
.M_AXI_GP1_RRESP ( M_AXI_GP1_RRESP ),
.M_AXI_GP1_RDATA ( M_AXI_GP1_RDATA ),
.S_AXI_GP0_ARESETN ( S_AXI_GP0_ARESETN ),
.S_AXI_GP0_ARREADY ( S_AXI_GP0_ARREADY ),
.S_AXI_GP0_AWREADY ( S_AXI_GP0_AWREADY ),
.S_AXI_GP0_BVALID ( S_AXI_GP0_BVALID ),
.S_AXI_GP0_RLAST ( S_AXI_GP0_RLAST ),
.S_AXI_GP0_RVALID ( S_AXI_GP0_RVALID ),
.S_AXI_GP0_WREADY ( S_AXI_GP0_WREADY ),
.S_AXI_GP0_BRESP ( S_AXI_GP0_BRESP ),
.S_AXI_GP0_RRESP ( S_AXI_GP0_RRESP ),
.S_AXI_GP0_RDATA ( S_AXI_GP0_RDATA ),
.S_AXI_GP0_BID ( S_AXI_GP0_BID ),
.S_AXI_GP0_RID ( S_AXI_GP0_RID ),
.S_AXI_GP0_ACLK ( S_AXI_GP0_ACLK ),
.S_AXI_GP0_ARVALID ( S_AXI_GP0_ARVALID ),
.S_AXI_GP0_AWVALID ( S_AXI_GP0_AWVALID ),
.S_AXI_GP0_BREADY ( S_AXI_GP0_BREADY ),
.S_AXI_GP0_RREADY ( S_AXI_GP0_RREADY ),
.S_AXI_GP0_WLAST ( S_AXI_GP0_WLAST ),
.S_AXI_GP0_WVALID ( S_AXI_GP0_WVALID ),
.S_AXI_GP0_ARBURST ( S_AXI_GP0_ARBURST ),
.S_AXI_GP0_ARLOCK ( S_AXI_GP0_ARLOCK ),
.S_AXI_GP0_ARSIZE ( S_AXI_GP0_ARSIZE ),
.S_AXI_GP0_AWBURST ( S_AXI_GP0_AWBURST ),
.S_AXI_GP0_AWLOCK ( S_AXI_GP0_AWLOCK ),
.S_AXI_GP0_AWSIZE ( S_AXI_GP0_AWSIZE ),
.S_AXI_GP0_ARPROT ( S_AXI_GP0_ARPROT ),
.S_AXI_GP0_AWPROT ( S_AXI_GP0_AWPROT ),
.S_AXI_GP0_ARADDR ( S_AXI_GP0_ARADDR ),
.S_AXI_GP0_AWADDR ( S_AXI_GP0_AWADDR ),
.S_AXI_GP0_WDATA ( S_AXI_GP0_WDATA ),
.S_AXI_GP0_ARCACHE ( S_AXI_GP0_ARCACHE ),
.S_AXI_GP0_ARLEN ( S_AXI_GP0_ARLEN ),
.S_AXI_GP0_ARQOS ( S_AXI_GP0_ARQOS ),
.S_AXI_GP0_AWCACHE ( S_AXI_GP0_AWCACHE ),
.S_AXI_GP0_AWLEN ( S_AXI_GP0_AWLEN ),
.S_AXI_GP0_AWQOS ( S_AXI_GP0_AWQOS ),
.S_AXI_GP0_WSTRB ( S_AXI_GP0_WSTRB ),
.S_AXI_GP0_ARID ( S_AXI_GP0_ARID ),
.S_AXI_GP0_AWID ( S_AXI_GP0_AWID ),
.S_AXI_GP0_WID ( S_AXI_GP0_WID ),
.S_AXI_GP1_ARESETN ( S_AXI_GP1_ARESETN ),
.S_AXI_GP1_ARREADY ( S_AXI_GP1_ARREADY ),
.S_AXI_GP1_AWREADY ( S_AXI_GP1_AWREADY ),
.S_AXI_GP1_BVALID ( S_AXI_GP1_BVALID ),
.S_AXI_GP1_RLAST ( S_AXI_GP1_RLAST ),
.S_AXI_GP1_RVALID ( S_AXI_GP1_RVALID ),
.S_AXI_GP1_WREADY ( S_AXI_GP1_WREADY ),
.S_AXI_GP1_BRESP ( S_AXI_GP1_BRESP ),
.S_AXI_GP1_RRESP ( S_AXI_GP1_RRESP ),
.S_AXI_GP1_RDATA ( S_AXI_GP1_RDATA ),
.S_AXI_GP1_BID ( S_AXI_GP1_BID ),
.S_AXI_GP1_RID ( S_AXI_GP1_RID ),
.S_AXI_GP1_ACLK ( S_AXI_GP1_ACLK ),
.S_AXI_GP1_ARVALID ( S_AXI_GP1_ARVALID ),
.S_AXI_GP1_AWVALID ( S_AXI_GP1_AWVALID ),
.S_AXI_GP1_BREADY ( S_AXI_GP1_BREADY ),
.S_AXI_GP1_RREADY ( S_AXI_GP1_RREADY ),
.S_AXI_GP1_WLAST ( S_AXI_GP1_WLAST ),
.S_AXI_GP1_WVALID ( S_AXI_GP1_WVALID ),
.S_AXI_GP1_ARBURST ( S_AXI_GP1_ARBURST ),
.S_AXI_GP1_ARLOCK ( S_AXI_GP1_ARLOCK ),
.S_AXI_GP1_ARSIZE ( S_AXI_GP1_ARSIZE ),
.S_AXI_GP1_AWBURST ( S_AXI_GP1_AWBURST ),
.S_AXI_GP1_AWLOCK ( S_AXI_GP1_AWLOCK ),
.S_AXI_GP1_AWSIZE ( S_AXI_GP1_AWSIZE ),
.S_AXI_GP1_ARPROT ( S_AXI_GP1_ARPROT ),
.S_AXI_GP1_AWPROT ( S_AXI_GP1_AWPROT ),
.S_AXI_GP1_ARADDR ( S_AXI_GP1_ARADDR ),
.S_AXI_GP1_AWADDR ( S_AXI_GP1_AWADDR ),
.S_AXI_GP1_WDATA ( S_AXI_GP1_WDATA ),
.S_AXI_GP1_ARCACHE ( S_AXI_GP1_ARCACHE ),
.S_AXI_GP1_ARLEN ( S_AXI_GP1_ARLEN ),
.S_AXI_GP1_ARQOS ( S_AXI_GP1_ARQOS ),
.S_AXI_GP1_AWCACHE ( S_AXI_GP1_AWCACHE ),
.S_AXI_GP1_AWLEN ( S_AXI_GP1_AWLEN ),
.S_AXI_GP1_AWQOS ( S_AXI_GP1_AWQOS ),
.S_AXI_GP1_WSTRB ( S_AXI_GP1_WSTRB ),
.S_AXI_GP1_ARID ( S_AXI_GP1_ARID ),
.S_AXI_GP1_AWID ( S_AXI_GP1_AWID ),
.S_AXI_GP1_WID ( S_AXI_GP1_WID ),
.S_AXI_ACP_ARESETN ( S_AXI_ACP_ARESETN ),
.S_AXI_ACP_AWREADY ( S_AXI_ACP_AWREADY ),
.S_AXI_ACP_ARREADY ( S_AXI_ACP_ARREADY ),
.S_AXI_ACP_BVALID ( S_AXI_ACP_BVALID ),
.S_AXI_ACP_RLAST ( S_AXI_ACP_RLAST ),
.S_AXI_ACP_RVALID ( S_AXI_ACP_RVALID ),
.S_AXI_ACP_WREADY ( S_AXI_ACP_WREADY ),
.S_AXI_ACP_BRESP ( S_AXI_ACP_BRESP ),
.S_AXI_ACP_RRESP ( S_AXI_ACP_RRESP ),
.S_AXI_ACP_BID ( S_AXI_ACP_BID ),
.S_AXI_ACP_RID ( S_AXI_ACP_RID ),
.S_AXI_ACP_RDATA ( S_AXI_ACP_RDATA ),
.S_AXI_ACP_ACLK ( S_AXI_ACP_ACLK ),
.S_AXI_ACP_ARVALID ( S_AXI_ACP_ARVALID ),
.S_AXI_ACP_AWVALID ( S_AXI_ACP_AWVALID ),
.S_AXI_ACP_BREADY ( S_AXI_ACP_BREADY ),
.S_AXI_ACP_RREADY ( S_AXI_ACP_RREADY ),
.S_AXI_ACP_WLAST ( S_AXI_ACP_WLAST ),
.S_AXI_ACP_WVALID ( S_AXI_ACP_WVALID ),
.S_AXI_ACP_ARID ( S_AXI_ACP_ARID ),
.S_AXI_ACP_ARPROT ( S_AXI_ACP_ARPROT ),
.S_AXI_ACP_AWID ( S_AXI_ACP_AWID ),
.S_AXI_ACP_AWPROT ( S_AXI_ACP_AWPROT ),
.S_AXI_ACP_WID ( S_AXI_ACP_WID ),
.S_AXI_ACP_ARADDR ( S_AXI_ACP_ARADDR ),
.S_AXI_ACP_AWADDR ( S_AXI_ACP_AWADDR ),
.S_AXI_ACP_ARCACHE ( S_AXI_ACP_ARCACHE ),
.S_AXI_ACP_ARLEN ( S_AXI_ACP_ARLEN ),
.S_AXI_ACP_ARQOS ( S_AXI_ACP_ARQOS ),
.S_AXI_ACP_AWCACHE ( S_AXI_ACP_AWCACHE ),
.S_AXI_ACP_AWLEN ( S_AXI_ACP_AWLEN ),
.S_AXI_ACP_AWQOS ( S_AXI_ACP_AWQOS ),
.S_AXI_ACP_ARBURST ( S_AXI_ACP_ARBURST ),
.S_AXI_ACP_ARLOCK ( S_AXI_ACP_ARLOCK ),
.S_AXI_ACP_ARSIZE ( S_AXI_ACP_ARSIZE ),
.S_AXI_ACP_AWBURST ( S_AXI_ACP_AWBURST ),
.S_AXI_ACP_AWLOCK ( S_AXI_ACP_AWLOCK ),
.S_AXI_ACP_AWSIZE ( S_AXI_ACP_AWSIZE ),
.S_AXI_ACP_ARUSER ( S_AXI_ACP_ARUSER ),
.S_AXI_ACP_AWUSER ( S_AXI_ACP_AWUSER ),
.S_AXI_ACP_WDATA ( S_AXI_ACP_WDATA ),
.S_AXI_ACP_WSTRB ( S_AXI_ACP_WSTRB ),
.S_AXI_HP0_ARESETN ( S_AXI_HP0_ARESETN ),
.S_AXI_HP0_ARREADY ( S_AXI_HP0_ARREADY ),
.S_AXI_HP0_AWREADY ( S_AXI_HP0_AWREADY ),
.S_AXI_HP0_BVALID ( S_AXI_HP0_BVALID ),
.S_AXI_HP0_RLAST ( S_AXI_HP0_RLAST ),
.S_AXI_HP0_RVALID ( S_AXI_HP0_RVALID ),
.S_AXI_HP0_WREADY ( S_AXI_HP0_WREADY ),
.S_AXI_HP0_BRESP ( S_AXI_HP0_BRESP ),
.S_AXI_HP0_RRESP ( S_AXI_HP0_RRESP ),
.S_AXI_HP0_BID ( S_AXI_HP0_BID ),
.S_AXI_HP0_RID ( S_AXI_HP0_RID ),
.S_AXI_HP0_RDATA ( S_AXI_HP0_RDATA ),
.S_AXI_HP0_RCOUNT ( S_AXI_HP0_RCOUNT ),
.S_AXI_HP0_WCOUNT ( S_AXI_HP0_WCOUNT ),
.S_AXI_HP0_RACOUNT ( S_AXI_HP0_RACOUNT ),
.S_AXI_HP0_WACOUNT ( S_AXI_HP0_WACOUNT ),
.S_AXI_HP0_ACLK ( S_AXI_HP0_ACLK ),
.S_AXI_HP0_ARVALID ( S_AXI_HP0_ARVALID ),
.S_AXI_HP0_AWVALID ( S_AXI_HP0_AWVALID ),
.S_AXI_HP0_BREADY ( S_AXI_HP0_BREADY ),
.S_AXI_HP0_RDISSUECAP1_EN ( S_AXI_HP0_RDISSUECAP1_EN ),
.S_AXI_HP0_RREADY ( S_AXI_HP0_RREADY ),
.S_AXI_HP0_WLAST ( S_AXI_HP0_WLAST ),
.S_AXI_HP0_WRISSUECAP1_EN ( S_AXI_HP0_WRISSUECAP1_EN ),
.S_AXI_HP0_WVALID ( S_AXI_HP0_WVALID ),
.S_AXI_HP0_ARBURST ( S_AXI_HP0_ARBURST ),
.S_AXI_HP0_ARLOCK ( S_AXI_HP0_ARLOCK ),
.S_AXI_HP0_ARSIZE ( S_AXI_HP0_ARSIZE ),
.S_AXI_HP0_AWBURST ( S_AXI_HP0_AWBURST ),
.S_AXI_HP0_AWLOCK ( S_AXI_HP0_AWLOCK ),
.S_AXI_HP0_AWSIZE ( S_AXI_HP0_AWSIZE ),
.S_AXI_HP0_ARPROT ( S_AXI_HP0_ARPROT ),
.S_AXI_HP0_AWPROT ( S_AXI_HP0_AWPROT ),
.S_AXI_HP0_ARADDR ( S_AXI_HP0_ARADDR ),
.S_AXI_HP0_AWADDR ( S_AXI_HP0_AWADDR ),
.S_AXI_HP0_ARCACHE ( S_AXI_HP0_ARCACHE ),
.S_AXI_HP0_ARLEN ( S_AXI_HP0_ARLEN ),
.S_AXI_HP0_ARQOS ( S_AXI_HP0_ARQOS ),
.S_AXI_HP0_AWCACHE ( S_AXI_HP0_AWCACHE ),
.S_AXI_HP0_AWLEN ( S_AXI_HP0_AWLEN ),
.S_AXI_HP0_AWQOS ( S_AXI_HP0_AWQOS ),
.S_AXI_HP0_ARID ( S_AXI_HP0_ARID ),
.S_AXI_HP0_AWID ( S_AXI_HP0_AWID ),
.S_AXI_HP0_WID ( S_AXI_HP0_WID ),
.S_AXI_HP0_WDATA ( S_AXI_HP0_WDATA ),
.S_AXI_HP0_WSTRB ( S_AXI_HP0_WSTRB ),
.S_AXI_HP1_ARESETN ( S_AXI_HP1_ARESETN ),
.S_AXI_HP1_ARREADY ( S_AXI_HP1_ARREADY ),
.S_AXI_HP1_AWREADY ( S_AXI_HP1_AWREADY ),
.S_AXI_HP1_BVALID ( S_AXI_HP1_BVALID ),
.S_AXI_HP1_RLAST ( S_AXI_HP1_RLAST ),
.S_AXI_HP1_RVALID ( S_AXI_HP1_RVALID ),
.S_AXI_HP1_WREADY ( S_AXI_HP1_WREADY ),
.S_AXI_HP1_BRESP ( S_AXI_HP1_BRESP ),
.S_AXI_HP1_RRESP ( S_AXI_HP1_RRESP ),
.S_AXI_HP1_BID ( S_AXI_HP1_BID ),
.S_AXI_HP1_RID ( S_AXI_HP1_RID ),
.S_AXI_HP1_RDATA ( S_AXI_HP1_RDATA ),
.S_AXI_HP1_RCOUNT ( S_AXI_HP1_RCOUNT ),
.S_AXI_HP1_WCOUNT ( S_AXI_HP1_WCOUNT ),
.S_AXI_HP1_RACOUNT ( S_AXI_HP1_RACOUNT ),
.S_AXI_HP1_WACOUNT ( S_AXI_HP1_WACOUNT ),
.S_AXI_HP1_ACLK ( S_AXI_HP1_ACLK ),
.S_AXI_HP1_ARVALID ( S_AXI_HP1_ARVALID ),
.S_AXI_HP1_AWVALID ( S_AXI_HP1_AWVALID ),
.S_AXI_HP1_BREADY ( S_AXI_HP1_BREADY ),
.S_AXI_HP1_RDISSUECAP1_EN ( S_AXI_HP1_RDISSUECAP1_EN ),
.S_AXI_HP1_RREADY ( S_AXI_HP1_RREADY ),
.S_AXI_HP1_WLAST ( S_AXI_HP1_WLAST ),
.S_AXI_HP1_WRISSUECAP1_EN ( S_AXI_HP1_WRISSUECAP1_EN ),
.S_AXI_HP1_WVALID ( S_AXI_HP1_WVALID ),
.S_AXI_HP1_ARBURST ( S_AXI_HP1_ARBURST ),
.S_AXI_HP1_ARLOCK ( S_AXI_HP1_ARLOCK ),
.S_AXI_HP1_ARSIZE ( S_AXI_HP1_ARSIZE ),
.S_AXI_HP1_AWBURST ( S_AXI_HP1_AWBURST ),
.S_AXI_HP1_AWLOCK ( S_AXI_HP1_AWLOCK ),
.S_AXI_HP1_AWSIZE ( S_AXI_HP1_AWSIZE ),
.S_AXI_HP1_ARPROT ( S_AXI_HP1_ARPROT ),
.S_AXI_HP1_AWPROT ( S_AXI_HP1_AWPROT ),
.S_AXI_HP1_ARADDR ( S_AXI_HP1_ARADDR ),
.S_AXI_HP1_AWADDR ( S_AXI_HP1_AWADDR ),
.S_AXI_HP1_ARCACHE ( S_AXI_HP1_ARCACHE ),
.S_AXI_HP1_ARLEN ( S_AXI_HP1_ARLEN ),
.S_AXI_HP1_ARQOS ( S_AXI_HP1_ARQOS ),
.S_AXI_HP1_AWCACHE ( S_AXI_HP1_AWCACHE ),
.S_AXI_HP1_AWLEN ( S_AXI_HP1_AWLEN ),
.S_AXI_HP1_AWQOS ( S_AXI_HP1_AWQOS ),
.S_AXI_HP1_ARID ( S_AXI_HP1_ARID ),
.S_AXI_HP1_AWID ( S_AXI_HP1_AWID ),
.S_AXI_HP1_WID ( S_AXI_HP1_WID ),
.S_AXI_HP1_WDATA ( S_AXI_HP1_WDATA ),
.S_AXI_HP1_WSTRB ( S_AXI_HP1_WSTRB ),
.S_AXI_HP2_ARESETN ( S_AXI_HP2_ARESETN ),
.S_AXI_HP2_ARREADY ( S_AXI_HP2_ARREADY ),
.S_AXI_HP2_AWREADY ( S_AXI_HP2_AWREADY ),
.S_AXI_HP2_BVALID ( S_AXI_HP2_BVALID ),
.S_AXI_HP2_RLAST ( S_AXI_HP2_RLAST ),
.S_AXI_HP2_RVALID ( S_AXI_HP2_RVALID ),
.S_AXI_HP2_WREADY ( S_AXI_HP2_WREADY ),
.S_AXI_HP2_BRESP ( S_AXI_HP2_BRESP ),
.S_AXI_HP2_RRESP ( S_AXI_HP2_RRESP ),
.S_AXI_HP2_BID ( S_AXI_HP2_BID ),
.S_AXI_HP2_RID ( S_AXI_HP2_RID ),
.S_AXI_HP2_RDATA ( S_AXI_HP2_RDATA ),
.S_AXI_HP2_RCOUNT ( S_AXI_HP2_RCOUNT ),
.S_AXI_HP2_WCOUNT ( S_AXI_HP2_WCOUNT ),
.S_AXI_HP2_RACOUNT ( S_AXI_HP2_RACOUNT ),
.S_AXI_HP2_WACOUNT ( S_AXI_HP2_WACOUNT ),
.S_AXI_HP2_ACLK ( S_AXI_HP2_ACLK ),
.S_AXI_HP2_ARVALID ( S_AXI_HP2_ARVALID ),
.S_AXI_HP2_AWVALID ( S_AXI_HP2_AWVALID ),
.S_AXI_HP2_BREADY ( S_AXI_HP2_BREADY ),
.S_AXI_HP2_RDISSUECAP1_EN ( S_AXI_HP2_RDISSUECAP1_EN ),
.S_AXI_HP2_RREADY ( S_AXI_HP2_RREADY ),
.S_AXI_HP2_WLAST ( S_AXI_HP2_WLAST ),
.S_AXI_HP2_WRISSUECAP1_EN ( S_AXI_HP2_WRISSUECAP1_EN ),
.S_AXI_HP2_WVALID ( S_AXI_HP2_WVALID ),
.S_AXI_HP2_ARBURST ( S_AXI_HP2_ARBURST ),
.S_AXI_HP2_ARLOCK ( S_AXI_HP2_ARLOCK ),
.S_AXI_HP2_ARSIZE ( S_AXI_HP2_ARSIZE ),
.S_AXI_HP2_AWBURST ( S_AXI_HP2_AWBURST ),
.S_AXI_HP2_AWLOCK ( S_AXI_HP2_AWLOCK ),
.S_AXI_HP2_AWSIZE ( S_AXI_HP2_AWSIZE ),
.S_AXI_HP2_ARPROT ( S_AXI_HP2_ARPROT ),
.S_AXI_HP2_AWPROT ( S_AXI_HP2_AWPROT ),
.S_AXI_HP2_ARADDR ( S_AXI_HP2_ARADDR ),
.S_AXI_HP2_AWADDR ( S_AXI_HP2_AWADDR ),
.S_AXI_HP2_ARCACHE ( S_AXI_HP2_ARCACHE ),
.S_AXI_HP2_ARLEN ( S_AXI_HP2_ARLEN ),
.S_AXI_HP2_ARQOS ( S_AXI_HP2_ARQOS ),
.S_AXI_HP2_AWCACHE ( S_AXI_HP2_AWCACHE ),
.S_AXI_HP2_AWLEN ( S_AXI_HP2_AWLEN ),
.S_AXI_HP2_AWQOS ( S_AXI_HP2_AWQOS ),
.S_AXI_HP2_ARID ( S_AXI_HP2_ARID ),
.S_AXI_HP2_AWID ( S_AXI_HP2_AWID ),
.S_AXI_HP2_WID ( S_AXI_HP2_WID ),
.S_AXI_HP2_WDATA ( S_AXI_HP2_WDATA ),
.S_AXI_HP2_WSTRB ( S_AXI_HP2_WSTRB ),
.S_AXI_HP3_ARESETN ( S_AXI_HP3_ARESETN ),
.S_AXI_HP3_ARREADY ( S_AXI_HP3_ARREADY ),
.S_AXI_HP3_AWREADY ( S_AXI_HP3_AWREADY ),
.S_AXI_HP3_BVALID ( S_AXI_HP3_BVALID ),
.S_AXI_HP3_RLAST ( S_AXI_HP3_RLAST ),
.S_AXI_HP3_RVALID ( S_AXI_HP3_RVALID ),
.S_AXI_HP3_WREADY ( S_AXI_HP3_WREADY ),
.S_AXI_HP3_BRESP ( S_AXI_HP3_BRESP ),
.S_AXI_HP3_RRESP ( S_AXI_HP3_RRESP ),
.S_AXI_HP3_BID ( S_AXI_HP3_BID ),
.S_AXI_HP3_RID ( S_AXI_HP3_RID ),
.S_AXI_HP3_RDATA ( S_AXI_HP3_RDATA ),
.S_AXI_HP3_RCOUNT ( S_AXI_HP3_RCOUNT ),
.S_AXI_HP3_WCOUNT ( S_AXI_HP3_WCOUNT ),
.S_AXI_HP3_RACOUNT ( S_AXI_HP3_RACOUNT ),
.S_AXI_HP3_WACOUNT ( S_AXI_HP3_WACOUNT ),
.S_AXI_HP3_ACLK ( S_AXI_HP3_ACLK ),
.S_AXI_HP3_ARVALID ( S_AXI_HP3_ARVALID ),
.S_AXI_HP3_AWVALID ( S_AXI_HP3_AWVALID ),
.S_AXI_HP3_BREADY ( S_AXI_HP3_BREADY ),
.S_AXI_HP3_RDISSUECAP1_EN ( S_AXI_HP3_RDISSUECAP1_EN ),
.S_AXI_HP3_RREADY ( S_AXI_HP3_RREADY ),
.S_AXI_HP3_WLAST ( S_AXI_HP3_WLAST ),
.S_AXI_HP3_WRISSUECAP1_EN ( S_AXI_HP3_WRISSUECAP1_EN ),
.S_AXI_HP3_WVALID ( S_AXI_HP3_WVALID ),
.S_AXI_HP3_ARBURST ( S_AXI_HP3_ARBURST ),
.S_AXI_HP3_ARLOCK ( S_AXI_HP3_ARLOCK ),
.S_AXI_HP3_ARSIZE ( S_AXI_HP3_ARSIZE ),
.S_AXI_HP3_AWBURST ( S_AXI_HP3_AWBURST ),
.S_AXI_HP3_AWLOCK ( S_AXI_HP3_AWLOCK ),
.S_AXI_HP3_AWSIZE ( S_AXI_HP3_AWSIZE ),
.S_AXI_HP3_ARPROT ( S_AXI_HP3_ARPROT ),
.S_AXI_HP3_AWPROT ( S_AXI_HP3_AWPROT ),
.S_AXI_HP3_ARADDR ( S_AXI_HP3_ARADDR ),
.S_AXI_HP3_AWADDR ( S_AXI_HP3_AWADDR ),
.S_AXI_HP3_ARCACHE ( S_AXI_HP3_ARCACHE ),
.S_AXI_HP3_ARLEN ( S_AXI_HP3_ARLEN ),
.S_AXI_HP3_ARQOS ( S_AXI_HP3_ARQOS ),
.S_AXI_HP3_AWCACHE ( S_AXI_HP3_AWCACHE ),
.S_AXI_HP3_AWLEN ( S_AXI_HP3_AWLEN ),
.S_AXI_HP3_AWQOS ( S_AXI_HP3_AWQOS ),
.S_AXI_HP3_ARID ( S_AXI_HP3_ARID ),
.S_AXI_HP3_AWID ( S_AXI_HP3_AWID ),
.S_AXI_HP3_WID ( S_AXI_HP3_WID ),
.S_AXI_HP3_WDATA ( S_AXI_HP3_WDATA ),
.S_AXI_HP3_WSTRB ( S_AXI_HP3_WSTRB ),
.DMA0_DATYPE ( DMA0_DATYPE ),
.DMA0_DAVALID ( DMA0_DAVALID ),
.DMA0_DRREADY ( DMA0_DRREADY ),
.DMA0_RSTN ( DMA0_RSTN ),
.DMA0_ACLK ( DMA0_ACLK ),
.DMA0_DAREADY ( DMA0_DAREADY ),
.DMA0_DRLAST ( DMA0_DRLAST ),
.DMA0_DRVALID ( DMA0_DRVALID ),
.DMA0_DRTYPE ( DMA0_DRTYPE ),
.DMA1_DATYPE ( DMA1_DATYPE ),
.DMA1_DAVALID ( DMA1_DAVALID ),
.DMA1_DRREADY ( DMA1_DRREADY ),
.DMA1_RSTN ( DMA1_RSTN ),
.DMA1_ACLK ( DMA1_ACLK ),
.DMA1_DAREADY ( DMA1_DAREADY ),
.DMA1_DRLAST ( DMA1_DRLAST ),
.DMA1_DRVALID ( DMA1_DRVALID ),
.DMA1_DRTYPE ( DMA1_DRTYPE ),
.DMA2_DATYPE ( DMA2_DATYPE ),
.DMA2_DAVALID ( DMA2_DAVALID ),
.DMA2_DRREADY ( DMA2_DRREADY ),
.DMA2_RSTN ( DMA2_RSTN ),
.DMA2_ACLK ( DMA2_ACLK ),
.DMA2_DAREADY ( DMA2_DAREADY ),
.DMA2_DRLAST ( DMA2_DRLAST ),
.DMA2_DRVALID ( DMA2_DRVALID ),
.DMA3_DRVALID ( DMA3_DRVALID ),
.DMA3_DATYPE ( DMA3_DATYPE ),
.DMA3_DAVALID ( DMA3_DAVALID ),
.DMA3_DRREADY ( DMA3_DRREADY ),
.DMA3_RSTN ( DMA3_RSTN ),
.DMA3_ACLK ( DMA3_ACLK ),
.DMA3_DAREADY ( DMA3_DAREADY ),
.DMA3_DRLAST ( DMA3_DRLAST ),
.DMA2_DRTYPE ( DMA2_DRTYPE ),
.DMA3_DRTYPE ( DMA3_DRTYPE ),
.FTMD_TRACEIN_DATA ( FTMD_TRACEIN_DATA ),
.FTMD_TRACEIN_VALID ( FTMD_TRACEIN_VALID ),
.FTMD_TRACEIN_CLK ( FTMD_TRACEIN_CLK ),
.FTMD_TRACEIN_ATID ( FTMD_TRACEIN_ATID ),
.FTMT_F2P_TRIG ( FTMT_F2P_TRIG ),
.FTMT_F2P_TRIGACK ( FTMT_F2P_TRIGACK ),
.FTMT_F2P_DEBUG ( FTMT_F2P_DEBUG ),
.FTMT_P2F_TRIGACK ( FTMT_P2F_TRIGACK ),
.FTMT_P2F_TRIG ( FTMT_P2F_TRIG ),
.FTMT_P2F_DEBUG ( FTMT_P2F_DEBUG ),
.FCLK_CLK3 ( FCLK_CLK3 ),
.FCLK_CLK2 ( FCLK_CLK2 ),
.FCLK_CLK1 ( FCLK_CLK1 ),
.FCLK_CLK0 ( FCLK_CLK0 ),
.FCLK_CLKTRIG3_N ( FCLK_CLKTRIG3_N ),
.FCLK_CLKTRIG2_N ( FCLK_CLKTRIG2_N ),
.FCLK_CLKTRIG1_N ( FCLK_CLKTRIG1_N ),
.FCLK_CLKTRIG0_N ( FCLK_CLKTRIG0_N ),
.FCLK_RESET3_N ( FCLK_RESET3_N ),
.FCLK_RESET2_N ( FCLK_RESET2_N ),
.FCLK_RESET1_N ( FCLK_RESET1_N ),
.FCLK_RESET0_N ( FCLK_RESET0_N ),
.FPGA_IDLE_N ( FPGA_IDLE_N ),
.DDR_ARB ( DDR_ARB ),
.IRQ_F2P ( IRQ_F2P ),
.Core0_nFIQ ( Core0_nFIQ ),
.Core0_nIRQ ( Core0_nIRQ ),
.Core1_nFIQ ( Core1_nFIQ ),
.Core1_nIRQ ( Core1_nIRQ ),
.EVENT_EVENTO ( EVENT_EVENTO ),
.EVENT_STANDBYWFE ( EVENT_STANDBYWFE ),
.EVENT_STANDBYWFI ( EVENT_STANDBYWFI ),
.EVENT_EVENTI ( EVENT_EVENTI ),
.MIO ( MIO ),
.DDR_Clk ( DDR_Clk ),
.DDR_Clk_n ( DDR_Clk_n ),
.DDR_CKE ( DDR_CKE ),
.DDR_CS_n ( DDR_CS_n ),
.DDR_RAS_n ( DDR_RAS_n ),
.DDR_CAS_n ( DDR_CAS_n ),
.DDR_WEB ( DDR_WEB ),
.DDR_BankAddr ( DDR_BankAddr ),
.DDR_Addr ( DDR_Addr ),
.DDR_ODT ( DDR_ODT ),
.DDR_DRSTB ( DDR_DRSTB ),
.DDR_DQ ( DDR_DQ ),
.DDR_DM ( DDR_DM ),
.DDR_DQS ( DDR_DQS ),
.DDR_DQS_n ( DDR_DQS_n ),
.DDR_VRN ( DDR_VRN ),
.DDR_VRP ( DDR_VRP ),
.PS_SRSTB ( PS_SRSTB ),
.PS_CLK ( PS_CLK ),
.PS_PORB ( PS_PORB ),
.IRQ_P2F_DMAC_ABORT ( IRQ_P2F_DMAC_ABORT ),
.IRQ_P2F_DMAC0 ( IRQ_P2F_DMAC0 ),
.IRQ_P2F_DMAC1 ( IRQ_P2F_DMAC1 ),
.IRQ_P2F_DMAC2 ( IRQ_P2F_DMAC2 ),
.IRQ_P2F_DMAC3 ( IRQ_P2F_DMAC3 ),
.IRQ_P2F_DMAC4 ( IRQ_P2F_DMAC4 ),
.IRQ_P2F_DMAC5 ( IRQ_P2F_DMAC5 ),
.IRQ_P2F_DMAC6 ( IRQ_P2F_DMAC6 ),
.IRQ_P2F_DMAC7 ( IRQ_P2F_DMAC7 ),
.IRQ_P2F_SMC ( IRQ_P2F_SMC ),
.IRQ_P2F_QSPI ( IRQ_P2F_QSPI ),
.IRQ_P2F_CTI ( IRQ_P2F_CTI ),
.IRQ_P2F_GPIO ( IRQ_P2F_GPIO ),
.IRQ_P2F_USB0 ( IRQ_P2F_USB0 ),
.IRQ_P2F_ENET0 ( IRQ_P2F_ENET0 ),
.IRQ_P2F_ENET_WAKE0 ( IRQ_P2F_ENET_WAKE0 ),
.IRQ_P2F_SDIO0 ( IRQ_P2F_SDIO0 ),
.IRQ_P2F_I2C0 ( IRQ_P2F_I2C0 ),
.IRQ_P2F_SPI0 ( IRQ_P2F_SPI0 ),
.IRQ_P2F_UART0 ( IRQ_P2F_UART0 ),
.IRQ_P2F_CAN0 ( IRQ_P2F_CAN0 ),
.IRQ_P2F_USB1 ( IRQ_P2F_USB1 ),
.IRQ_P2F_ENET1 ( IRQ_P2F_ENET1 ),
.IRQ_P2F_ENET_WAKE1 ( IRQ_P2F_ENET_WAKE1 ),
.IRQ_P2F_SDIO1 ( IRQ_P2F_SDIO1 ),
.IRQ_P2F_I2C1 ( IRQ_P2F_I2C1 ),
.IRQ_P2F_SPI1 ( IRQ_P2F_SPI1 ),
.IRQ_P2F_UART1 ( IRQ_P2F_UART1 ),
.IRQ_P2F_CAN1 ( IRQ_P2F_CAN1 )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:40:01 08/24/2014
// Design Name:
// Module Name: ps2_kbd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_kbd (
clk,
clrn,
ps2_clk,
ps2_data,
rdn,
data,
ready,
overflow
);
input clk, clrn; // clock and reset (active low)
input ps2_clk, ps2_data; // ps2 signals from keyboard
input rdn; // read (active low) signal from cpu
output [ 7: 0] data; // keyboard code
output ready; // queue (fifo) state
output reg overflow; // queue (fifo) overflow
reg [ 3: 0] count; // count ps2_data bits
reg [ 9: 0] buffer; // ps2_data bits
reg [ 7: 0] fifoo[7:0]; // data queue (fifo)
reg [ 2: 0] w_ptr, r_ptr; // fifo write and read pointers
reg [ 2: 0] ps2_clk_sync; // for detecting the falling-edge of a frame
integer i;
initial begin
count <= 0; // clear count
w_ptr <= 0; // clear w_ptr
r_ptr <= 0; // clear r_ptr
overflow <= 0; // clear overflow
for(i = 0; i < 8; i = i + 1) fifoo[i]=0;
end
always @ (posedge clk) begin // this is a common method to
ps2_clk_sync <= {ps2_clk_sync[1:0],ps2_clk}; // detect
end // falling-edge
wire sampling = ps2_clk_sync[2] & ~ps2_clk_sync[1]; // (start bit)
reg [1:0] rdn_falling;
always @ (posedge clk) begin
rdn_falling <= {rdn_falling[0],rdn};
if (clrn == 0) begin
count <= 0;
w_ptr <= 0;
r_ptr <= 0;
overflow <= 0;
end else if (sampling) begin
if (count == 4'd10) begin // for one frame
if ((buffer[0] == 0) && (ps2_data) && (^buffer[9:1])) begin // odd prity
fifoo[w_ptr] <= buffer[8:1]; // write fifo
w_ptr <= w_ptr + 3'b1; // w_ptr++
overflow <= overflow | (r_ptr == (w_ptr + 3'b1));
end
count <= 0; // for next
end else begin // within one frame
buffer[count] <= ps2_data; // store ps2_data
count <= count + 3'b1; // count ps2_data bits
end
end
if ((rdn_falling == 2'b01) && ready) begin // when cpu reads fifo
r_ptr <= r_ptr + 3'b1; // r_ptr++
overflow <= 0; // clear overflow
end
end
assign ready = (w_ptr != r_ptr); // fifo has data
assign data = fifoo[r_ptr]; // fifo data
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : GTHE3_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE3_CHANNEL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'hF800,
parameter [15:0] ADAPT_CFG1 = 16'h0000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h20F8,
parameter [15:0] CPLL_CFG1 = 16'hA494,
parameter [15:0] CPLL_CFG2 = 16'hF001,
parameter [5:0] CPLL_CFG3 = 6'h00,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [7:0] CPLL_INIT_CFG1 = 8'h00,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DFE_D_X_REL_POS = 1'b0,
parameter [0:0] DFE_VCM_COMP_EN = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h000,
parameter [9:0] ES_PMA_CFG = 10'b0000000000,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] GM_BIAS_SELECT = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000,
parameter [2:0] PCS_RSVD1 = 3'b000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0,
parameter [15:0] PMA_RSV1 = 16'h0000,
parameter [2:0] PROCESS_PAR = 3'b010,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0000,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG1 = 16'h0080,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG2 = 16'h07E6,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG3 = 16'h0000,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG4 = 16'h0000,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG5 = 16'h0000,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [15:0] RXCFOK_CFG0 = 16'h4000,
parameter [15:0] RXCFOK_CFG1 = 16'h0060,
parameter [15:0] RXCFOK_CFG2 = 16'h000E,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000,
parameter [15:0] RXDFE_CFG0 = 16'h0A00,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG1 = 16'h7840,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG0 = 16'h4000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H5_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H6_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG0 = 16'h2000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG0 = 16'h2000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG0 = 16'h8000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG0 = 16'h8000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0003,
parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0033,
parameter [15:0] RXDLY_CFG = 16'h001F,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "Sigcfg_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h0000,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002,
parameter [15:0] RXLPM_OS_CFG0 = 16'h8000,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0002,
parameter [8:0] RXOOB_CFG = 9'b000000110,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h6622,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] RXPI_CFG0 = 2'b00,
parameter [1:0] RXPI_CFG1 = 2'b00,
parameter [1:0] RXPI_CFG2 = 2'b00,
parameter [1:0] RXPI_CFG3 = 2'b00,
parameter [0:0] RXPI_CFG4 = 1'b0,
parameter [0:0] RXPI_CFG5 = 1'b1,
parameter [2:0] RXPI_CFG6 = 3'b000,
parameter [0:0] RXPI_LPM = 1'b0,
parameter [0:0] RXPI_VREFSEL = 1'b0,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b1010,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter [1:0] RX_CM_SEL = 2'b11,
parameter [3:0] RX_CM_TRIM = 4'b0100,
parameter [7:0] RX_CTLE3_LPF = 8'b00000000,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110,
parameter [0:0] RX_DFELPM_CFG1 = 1'b0,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00,
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100,
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_HI_LR = 1'b0,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter real RX_PROGDIV_CFG = 4.0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000,
parameter [1:0] RX_SUM_RES_CTRL = 2'b00,
parameter [3:0] RX_SUM_VCMTUNE = 4'b0000,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b000,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [0:0] RX_WIDEMODE_CDR = 1'b0,
parameter RX_XCLK_SEL = "RXDES",
parameter integer SAS_MAX_COM = 64,
parameter integer SAS_MIN_COM = 36,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter integer SATA_MAX_BURST = 8,
parameter integer SATA_MAX_INIT = 21,
parameter integer SATA_MAX_WAKE = 7,
parameter integer SATA_MIN_BURST = 4,
parameter integer SATA_MIN_INIT = 12,
parameter integer SATA_MIN_WAKE = 4,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0,
parameter SIM_VERSION = "Ver_1",
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [3:0] TEMPERATUR_PAR = 4'b0010,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h001F,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter [3:0] TXDRVBIAS_N = 4'b1010,
parameter [3:0] TXDRVBIAS_P = 4'b1100,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h2020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0001,
parameter [15:0] TXPH_CFG = 16'h0980,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] TXPI_CFG0 = 2'b00,
parameter [1:0] TXPI_CFG1 = 2'b00,
parameter [1:0] TXPI_CFG2 = 2'b00,
parameter [0:0] TXPI_CFG3 = 1'b0,
parameter [0:0] TXPI_CFG4 = 1'b1,
parameter [2:0] TXPI_CFG5 = 3'b000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_LPM = 1'b0,
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2",
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [0:0] TXPI_VREFSEL = 1'b0,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter integer TX_DATA_WIDTH = 20,
parameter [5:0] TX_DCD_CFG = 6'b000010,
parameter [0:0] TX_DCD_EN = 1'b0,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_EML_PHI_TUNE = 1'b0,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [2:0] TX_MODE_SEL = 3'b000,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 4.0,
parameter [0:0] TX_QPI_STATUS_EN = 1'b0,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter [2:0] TX_RXDETECT_REF = 3'b100,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0,
parameter [1:0] WB_MODE = 2'b00
)(
output [2:0] BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output [2:0] BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [16:0] DMONITOROUT,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTHTXN,
output GTHTXP,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [11:0] PCSRSVDOUT,
output PHYSTATUS,
output [7:0] PINRSRVDAS,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output [6:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXQPISENN,
output RXQPISENP,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXQPISENN,
output TXQPISENP,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input EVODDPHICALDONE,
input EVODDPHICALSTART,
input EVODDPHIDRDEN,
input EVODDPHIDWREN,
input EVODDPHIXRDEN,
input EVODDPHIXWREN,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTGREFCLK,
input GTHRXN,
input GTHRXP,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTRESETSEL,
input [15:0] GTRSVD,
input GTRXRESET,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input [2:0] LOOPBACK,
input LPBKRXTXSEREN,
input LPBKTXRXSEREN,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input QPLL0CLK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1REFCLK,
input RESETOVRD,
input RSTCLKENTX,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCOMMADETEN,
input [1:0] RXDFEAGCCTRL,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEVSEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input [3:0] RXOSINTCFG,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTOVRDEN,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input RXQPIEN,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [2:0] TXBUFDIFFCTRL,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDEEMPH,
input TXDETECTRX,
input [3:0] TXDIFFCTRL,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXPROGDIVRESET,
input TXQPIBIASEN,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTHE3_CHANNEL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0;
localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1;
localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2;
localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3;
localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1;
localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
localparam [1:0] DDI_CTRL_REG = DDI_CTRL;
localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS;
localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN;
localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
localparam [5:0] ES_CONTROL_REG = ES_CONTROL;
localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG;
localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE;
localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG;
localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT;
localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL;
localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP;
localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0;
localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1;
localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12;
localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3;
localparam [15:0] PMA_RSV1_REG = PMA_RSV1;
localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR;
localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE;
localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
localparam [40:1] RXBUF_EN_REG = RXBUF_EN;
localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG;
localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG;
localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG;
localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
localparam [4:0] RXOUT_DIV_REG = RXOUT_DIV;
localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
localparam [1:0] RXPI_CFG0_REG = RXPI_CFG0;
localparam [1:0] RXPI_CFG1_REG = RXPI_CFG1;
localparam [1:0] RXPI_CFG2_REG = RXPI_CFG2;
localparam [1:0] RXPI_CFG3_REG = RXPI_CFG3;
localparam [0:0] RXPI_CFG4_REG = RXPI_CFG4;
localparam [0:0] RXPI_CFG5_REG = RXPI_CFG5;
localparam [2:0] RXPI_CFG6_REG = RXPI_CFG6;
localparam [0:0] RXPI_LPM_REG = RXPI_LPM;
localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL;
localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL;
localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
localparam [7:0] RX_CTLE3_LPF_REG = RX_CTLE3_LPF;
localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
localparam [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0;
localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR;
localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
localparam real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG;
localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
localparam [1:0] RX_SUM_RES_CTRL_REG = RX_SUM_RES_CTRL;
localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
localparam [0:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM;
localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM;
localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST;
localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT;
localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE;
localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST;
localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT;
localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE;
localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
localparam [56:1] SIM_VERSION_REG = SIM_VERSION;
localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
localparam [3:0] TEMPERATUR_PAR_REG = TEMPERATUR_PAR;
localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
localparam [7:0] TST_RSV0_REG = TST_RSV0;
localparam [7:0] TST_RSV1_REG = TST_RSV1;
localparam [40:1] TXBUF_EN_REG = TXBUF_EN;
localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG;
localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
localparam [3:0] TXDRVBIAS_N_REG = TXDRVBIAS_N;
localparam [3:0] TXDRVBIAS_P_REG = TXDRVBIAS_P;
localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
localparam [4:0] TXOUT_DIV_REG = TXOUT_DIV;
localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
localparam [15:0] TXPH_CFG_REG = TXPH_CFG;
localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0;
localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1;
localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2;
localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3;
localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4;
localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5;
localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
localparam [0:0] TXPI_LPM_REG = TXPI_LPM;
localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL;
localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL;
localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG;
localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN;
localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE;
localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL;
localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
localparam real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG;
localparam [0:0] TX_QPI_STATUS_EN_REG = TX_QPI_STATUS_EN;
localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB;
localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
localparam [1:0] WB_MODE_REG = WB_MODE;
`endif
localparam [0:0] AEN_CPLL_REG = 1'b0;
localparam [0:0] AEN_EYESCAN_REG = 1'b1;
localparam [0:0] AEN_LOOPBACK_REG = 1'b0;
localparam [0:0] AEN_MASTER_REG = 1'b0;
localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
localparam [0:0] AEN_POLARITY_REG = 1'b0;
localparam [0:0] AEN_PRBS_REG = 1'b0;
localparam [0:0] AEN_QPI_REG = 1'b0;
localparam [0:0] AEN_RESET_REG = 1'b0;
localparam [0:0] AEN_RXCDR_REG = 1'b0;
localparam [0:0] AEN_RXDFE_REG = 1'b0;
localparam [0:0] AEN_RXDFELPM_REG = 1'b0;
localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXPHDLY_REG = 1'b0;
localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXPHDLY_REG = 1'b0;
localparam [0:0] AEN_TXPI_PPM_REG = 1'b0;
localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
localparam [15:0] AMONITOR_CFG_REG = 16'h0000;
localparam [0:0] A_AFECFOKEN_REG = 1'b0;
localparam [0:0] A_CPLLLOCKEN_REG = 1'b0;
localparam [0:0] A_CPLLPD_REG = 1'b0;
localparam [0:0] A_CPLLRESET_REG = 1'b0;
localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000;
localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000;
localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0;
localparam [0:0] A_DFECFOKHOLD_REG = 1'b0;
localparam [0:0] A_DFECFOKOVREN_REG = 1'b0;
localparam [0:0] A_EYESCANMODE_REG = 1'b0;
localparam [0:0] A_EYESCANRESET_REG = 1'b0;
localparam [0:0] A_GTRESETSEL_REG = 1'b0;
localparam [0:0] A_GTRXRESET_REG = 1'b0;
localparam [0:0] A_GTTXRESET_REG = 1'b0;
localparam [80:1] A_LOOPBACK_REG = "NoLoopBack";
localparam [0:0] A_LPMGCHOLD_REG = 1'b0;
localparam [0:0] A_LPMGCOVREN_REG = 1'b0;
localparam [0:0] A_LPMOSHOLD_REG = 1'b0;
localparam [0:0] A_LPMOSOVREN_REG = 1'b0;
localparam [0:0] A_RXBUFRESET_REG = 1'b0;
localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0;
localparam [0:0] A_RXCDRHOLD_REG = 1'b0;
localparam [0:0] A_RXCDROVRDEN_REG = 1'b0;
localparam [0:0] A_RXCDRRESET_REG = 1'b0;
localparam [1:0] A_RXDFEAGCCTRL_REG = 2'b00;
localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0;
localparam [0:0] A_RXDFELFHOLD_REG = 1'b0;
localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFELPMRESET_REG = 1'b0;
localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVSEN_REG = 1'b0;
localparam [0:0] A_RXDFEXYDEN_REG = 1'b0;
localparam [0:0] A_RXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_RXDLYEN_REG = 1'b0;
localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDLYSRESET_REG = 1'b0;
localparam [0:0] A_RXLPMEN_REG = 1'b0;
localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
localparam [1:0] A_RXMONITORSEL_REG = 2'b00;
localparam [0:0] A_RXOOBRESET_REG = 1'b0;
localparam [0:0] A_RXOSHOLD_REG = 1'b0;
localparam [0:0] A_RXOSOVRDEN_REG = 1'b0;
localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_RXPCSRESET_REG = 1'b0;
localparam [24:1] A_RXPD_REG = "P0";
localparam [0:0] A_RXPHALIGN_REG = 1'b0;
localparam [0:0] A_RXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_RXPHDLYPD_REG = 1'b0;
localparam [0:0] A_RXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_RXPHOVRDEN_REG = 1'b0;
localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_RXPMARESET_REG = 1'b0;
localparam [0:0] A_RXPOLARITY_REG = 1'b0;
localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
localparam [48:1] A_RXPRBSSEL_REG = "PRBS7";
localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
localparam [0:0] A_TXDEEMPH_REG = 1'b0;
localparam [3:0] A_TXDIFFCTRL_REG = 4'b1100;
localparam [0:0] A_TXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_TXDLYEN_REG = 1'b0;
localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_TXDLYSRESET_REG = 1'b0;
localparam [0:0] A_TXELECIDLE_REG = 1'b0;
localparam [0:0] A_TXINHIBIT_REG = 1'b0;
localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
localparam [2:0] A_TXMARGIN_REG = 3'b000;
localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_TXPCSRESET_REG = 1'b0;
localparam [24:1] A_TXPD_REG = "P0";
localparam [0:0] A_TXPHALIGN_REG = 1'b0;
localparam [0:0] A_TXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_TXPHDLYPD_REG = 1'b0;
localparam [0:0] A_TXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_TXPHINIT_REG = 1'b0;
localparam [0:0] A_TXPHOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMPD_REG = 1'b0;
localparam [0:0] A_TXPIPPMSEL_REG = 1'b0;
localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_TXPMARESET_REG = 1'b0;
localparam [0:0] A_TXPOLARITY_REG = 1'b0;
localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
localparam [0:0] A_TXPOSTCURSORINV_REG = 1'b0;
localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
localparam [96:1] A_TXPRBSSEL_REG = "PRBS7";
localparam [4:0] A_TXPRECURSOR_REG = 5'b00000;
localparam [0:0] A_TXPRECURSORINV_REG = 1'b0;
localparam [0:0] A_TXQPIBIASEN_REG = 1'b0;
localparam [0:0] A_TXSWING_REG = 1'b0;
localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [40:1] GEN_RXUSRCLK_REG = "TRUE";
localparam [40:1] GEN_TXUSRCLK_REG = "TRUE";
localparam [0:0] GT_INSTANTIATED_REG = 1'b1;
localparam [40:1] RXPLL_SEL_REG = "CPLL";
localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
wire [63:0] RX_PROGDIV_CFG_BIN;
wire [63:0] TX_PROGDIV_CFG_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTHE3_CHANNEL_dr.v"
`endif
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTHTXN_out;
wire GTHTXP_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXQPISENN_out;
wire RXQPISENP_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXQPISENN_out;
wire TXQPISENP_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [11:0] PCSRSVDOUT_out;
wire [11:0] PMASCANOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DRPDO_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [16:0] DMONITOROUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTCE_out;
wire [2:0] BUFGTRESET_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [6:0] RXMONITOROUT_out;
wire [7:0] PINRSRVDAS_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [8:0] BUFGTDIV_out;
wire CPLLFBCLKLOST_delay;
wire CPLLLOCK_delay;
wire CPLLREFCLKLOST_delay;
wire DRPRDY_delay;
wire EYESCANDATAERROR_delay;
wire GTHTXN_delay;
wire GTHTXP_delay;
wire GTPOWERGOOD_delay;
wire GTREFCLKMONITOR_delay;
wire PCIERATEGEN3_delay;
wire PCIERATEIDLE_delay;
wire PCIESYNCTXSYNCDONE_delay;
wire PCIEUSERGEN3RDY_delay;
wire PCIEUSERPHYSTATUSRST_delay;
wire PCIEUSERRATESTART_delay;
wire PHYSTATUS_delay;
wire RESETEXCEPTION_delay;
wire RXBYTEISALIGNED_delay;
wire RXBYTEREALIGN_delay;
wire RXCDRLOCK_delay;
wire RXCDRPHDONE_delay;
wire RXCHANBONDSEQ_delay;
wire RXCHANISALIGNED_delay;
wire RXCHANREALIGN_delay;
wire RXCOMINITDET_delay;
wire RXCOMMADET_delay;
wire RXCOMSASDET_delay;
wire RXCOMWAKEDET_delay;
wire RXDLYSRESETDONE_delay;
wire RXELECIDLE_delay;
wire RXOSINTDONE_delay;
wire RXOSINTSTARTED_delay;
wire RXOSINTSTROBEDONE_delay;
wire RXOSINTSTROBESTARTED_delay;
wire RXOUTCLKFABRIC_delay;
wire RXOUTCLKPCS_delay;
wire RXOUTCLK_delay;
wire RXPHALIGNDONE_delay;
wire RXPHALIGNERR_delay;
wire RXPMARESETDONE_delay;
wire RXPRBSERR_delay;
wire RXPRBSLOCKED_delay;
wire RXPRGDIVRESETDONE_delay;
wire RXQPISENN_delay;
wire RXQPISENP_delay;
wire RXRATEDONE_delay;
wire RXRECCLKOUT_delay;
wire RXRESETDONE_delay;
wire RXSLIDERDY_delay;
wire RXSLIPDONE_delay;
wire RXSLIPOUTCLKRDY_delay;
wire RXSLIPPMARDY_delay;
wire RXSYNCDONE_delay;
wire RXSYNCOUT_delay;
wire RXVALID_delay;
wire TXCOMFINISH_delay;
wire TXDLYSRESETDONE_delay;
wire TXOUTCLKFABRIC_delay;
wire TXOUTCLKPCS_delay;
wire TXOUTCLK_delay;
wire TXPHALIGNDONE_delay;
wire TXPHINITDONE_delay;
wire TXPMARESETDONE_delay;
wire TXPRGDIVRESETDONE_delay;
wire TXQPISENN_delay;
wire TXQPISENP_delay;
wire TXRATEDONE_delay;
wire TXRESETDONE_delay;
wire TXSYNCDONE_delay;
wire TXSYNCOUT_delay;
wire [11:0] PCSRSVDOUT_delay;
wire [127:0] RXDATA_delay;
wire [15:0] DRPDO_delay;
wire [15:0] RXCTRL0_delay;
wire [15:0] RXCTRL1_delay;
wire [16:0] DMONITOROUT_delay;
wire [1:0] PCIERATEQPLLPD_delay;
wire [1:0] PCIERATEQPLLRESET_delay;
wire [1:0] RXCLKCORCNT_delay;
wire [1:0] RXDATAVALID_delay;
wire [1:0] RXHEADERVALID_delay;
wire [1:0] RXSTARTOFSEQ_delay;
wire [1:0] TXBUFSTATUS_delay;
wire [2:0] BUFGTCEMASK_delay;
wire [2:0] BUFGTCE_delay;
wire [2:0] BUFGTRESET_delay;
wire [2:0] BUFGTRSTMASK_delay;
wire [2:0] RXBUFSTATUS_delay;
wire [2:0] RXSTATUS_delay;
wire [4:0] RXCHBONDO_delay;
wire [5:0] RXHEADER_delay;
wire [6:0] RXMONITOROUT_delay;
wire [7:0] PINRSRVDAS_delay;
wire [7:0] RXCTRL2_delay;
wire [7:0] RXCTRL3_delay;
wire [7:0] RXDATAEXTENDRSVD_delay;
wire [8:0] BUFGTDIV_delay;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire EVODDPHICALDONE_in;
wire EVODDPHICALSTART_in;
wire EVODDPHIDRDEN_in;
wire EVODDPHIDWREN_in;
wire EVODDPHIXRDEN_in;
wire EVODDPHIXWREN_in;
wire EYESCANMODE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire GTGREFCLK_in;
wire GTHRXN_in;
wire GTHRXP_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESET_in;
wire LPBKRXTXSEREN_in;
wire LPBKTXRXSEREN_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RSTCLKENTX_in;
wire RX8B10BEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESETRSV_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCOMMADETEN_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEVSEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSINTEN_in;
wire RXOSINTHOLD_in;
wire RXOSINTOVRDEN_in;
wire RXOSINTSTROBE_in;
wire RXOSINTTESTOVRDEN_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPHOVRDEN_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXQPIEN_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDEEMPH_in;
wire TXDETECTRX_in;
wire TXDIFFPD_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPOSTCURSORINV_in;
wire TXPRBSFORCEERR_in;
wire TXPRECURSORINV_in;
wire TXPROGDIVRESET_in;
wire TXQPIBIASEN_in;
wire TXQPISTRONGPDOWN_in;
wire TXQPIWEAKPUP_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [11:0] PMASCANIN_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXDFEAGCCTRL_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXBUFDIFFCTRL_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXOSINTCFG_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXDIFFCTRL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] PCSRSVDIN2_in;
wire [4:0] PMARSVDIN_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [8:0] DRPADDR_in;
wire CFGRESET_delay;
wire CLKRSVD0_delay;
wire CLKRSVD1_delay;
wire CPLLLOCKDETCLK_delay;
wire CPLLLOCKEN_delay;
wire CPLLPD_delay;
wire CPLLRESET_delay;
wire DMONFIFORESET_delay;
wire DMONITORCLK_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire EVODDPHICALDONE_delay;
wire EVODDPHICALSTART_delay;
wire EVODDPHIDRDEN_delay;
wire EVODDPHIDWREN_delay;
wire EVODDPHIXRDEN_delay;
wire EVODDPHIXWREN_delay;
wire EYESCANMODE_delay;
wire EYESCANRESET_delay;
wire EYESCANTRIGGER_delay;
wire GTGREFCLK_delay;
wire GTHRXN_delay;
wire GTHRXP_delay;
wire GTNORTHREFCLK0_delay;
wire GTNORTHREFCLK1_delay;
wire GTREFCLK0_delay;
wire GTREFCLK1_delay;
wire GTRESETSEL_delay;
wire GTRXRESET_delay;
wire GTSOUTHREFCLK0_delay;
wire GTSOUTHREFCLK1_delay;
wire GTTXRESET_delay;
wire LPBKRXTXSEREN_delay;
wire LPBKTXRXSEREN_delay;
wire PCIEEQRXEQADAPTDONE_delay;
wire PCIERSTIDLE_delay;
wire PCIERSTTXSYNCSTART_delay;
wire PCIEUSERRATEDONE_delay;
wire QPLL0CLK_delay;
wire QPLL0REFCLK_delay;
wire QPLL1CLK_delay;
wire QPLL1REFCLK_delay;
wire RESETOVRD_delay;
wire RSTCLKENTX_delay;
wire RX8B10BEN_delay;
wire RXBUFRESET_delay;
wire RXCDRFREQRESET_delay;
wire RXCDRHOLD_delay;
wire RXCDROVRDEN_delay;
wire RXCDRRESETRSV_delay;
wire RXCDRRESET_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCOMMADETEN_delay;
wire RXDFEAGCHOLD_delay;
wire RXDFEAGCOVRDEN_delay;
wire RXDFELFHOLD_delay;
wire RXDFELFOVRDEN_delay;
wire RXDFELPMRESET_delay;
wire RXDFETAP10HOLD_delay;
wire RXDFETAP10OVRDEN_delay;
wire RXDFETAP11HOLD_delay;
wire RXDFETAP11OVRDEN_delay;
wire RXDFETAP12HOLD_delay;
wire RXDFETAP12OVRDEN_delay;
wire RXDFETAP13HOLD_delay;
wire RXDFETAP13OVRDEN_delay;
wire RXDFETAP14HOLD_delay;
wire RXDFETAP14OVRDEN_delay;
wire RXDFETAP15HOLD_delay;
wire RXDFETAP15OVRDEN_delay;
wire RXDFETAP2HOLD_delay;
wire RXDFETAP2OVRDEN_delay;
wire RXDFETAP3HOLD_delay;
wire RXDFETAP3OVRDEN_delay;
wire RXDFETAP4HOLD_delay;
wire RXDFETAP4OVRDEN_delay;
wire RXDFETAP5HOLD_delay;
wire RXDFETAP5OVRDEN_delay;
wire RXDFETAP6HOLD_delay;
wire RXDFETAP6OVRDEN_delay;
wire RXDFETAP7HOLD_delay;
wire RXDFETAP7OVRDEN_delay;
wire RXDFETAP8HOLD_delay;
wire RXDFETAP8OVRDEN_delay;
wire RXDFETAP9HOLD_delay;
wire RXDFETAP9OVRDEN_delay;
wire RXDFEUTHOLD_delay;
wire RXDFEUTOVRDEN_delay;
wire RXDFEVPHOLD_delay;
wire RXDFEVPOVRDEN_delay;
wire RXDFEVSEN_delay;
wire RXDFEXYDEN_delay;
wire RXDLYBYPASS_delay;
wire RXDLYEN_delay;
wire RXDLYOVRDEN_delay;
wire RXDLYSRESET_delay;
wire RXGEARBOXSLIP_delay;
wire RXLATCLK_delay;
wire RXLPMEN_delay;
wire RXLPMGCHOLD_delay;
wire RXLPMGCOVRDEN_delay;
wire RXLPMHFHOLD_delay;
wire RXLPMHFOVRDEN_delay;
wire RXLPMLFHOLD_delay;
wire RXLPMLFKLOVRDEN_delay;
wire RXLPMOSHOLD_delay;
wire RXLPMOSOVRDEN_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXOOBRESET_delay;
wire RXOSCALRESET_delay;
wire RXOSHOLD_delay;
wire RXOSINTEN_delay;
wire RXOSINTHOLD_delay;
wire RXOSINTOVRDEN_delay;
wire RXOSINTSTROBE_delay;
wire RXOSINTTESTOVRDEN_delay;
wire RXOSOVRDEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPCSRESET_delay;
wire RXPHALIGNEN_delay;
wire RXPHALIGN_delay;
wire RXPHDLYPD_delay;
wire RXPHDLYRESET_delay;
wire RXPHOVRDEN_delay;
wire RXPMARESET_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXPROGDIVRESET_delay;
wire RXQPIEN_delay;
wire RXRATEMODE_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXSLIPPMA_delay;
wire RXSYNCALLIN_delay;
wire RXSYNCIN_delay;
wire RXSYNCMODE_delay;
wire RXUSERRDY_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire SIGVALIDCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDEEMPH_delay;
wire TXDETECTRX_delay;
wire TXDIFFPD_delay;
wire TXDLYBYPASS_delay;
wire TXDLYEN_delay;
wire TXDLYHOLD_delay;
wire TXDLYOVRDEN_delay;
wire TXDLYSRESET_delay;
wire TXDLYUPDOWN_delay;
wire TXELECIDLE_delay;
wire TXINHIBIT_delay;
wire TXLATCLK_delay;
wire TXPCSRESET_delay;
wire TXPDELECIDLEMODE_delay;
wire TXPHALIGNEN_delay;
wire TXPHALIGN_delay;
wire TXPHDLYPD_delay;
wire TXPHDLYRESET_delay;
wire TXPHDLYTSTCLK_delay;
wire TXPHINIT_delay;
wire TXPHOVRDEN_delay;
wire TXPIPPMEN_delay;
wire TXPIPPMOVRDEN_delay;
wire TXPIPPMPD_delay;
wire TXPIPPMSEL_delay;
wire TXPISOPD_delay;
wire TXPMARESET_delay;
wire TXPOLARITY_delay;
wire TXPOSTCURSORINV_delay;
wire TXPRBSFORCEERR_delay;
wire TXPRECURSORINV_delay;
wire TXPROGDIVRESET_delay;
wire TXQPIBIASEN_delay;
wire TXQPISTRONGPDOWN_delay;
wire TXQPIWEAKPUP_delay;
wire TXRATEMODE_delay;
wire TXSWING_delay;
wire TXSYNCALLIN_delay;
wire TXSYNCIN_delay;
wire TXSYNCMODE_delay;
wire TXUSERRDY_delay;
wire TXUSRCLK2_delay;
wire TXUSRCLK_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] GTRSVD_delay;
wire [15:0] PCSRSVDIN_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [19:0] TSTIN_delay;
wire [1:0] RXDFEAGCCTRL_delay;
wire [1:0] RXELECIDLEMODE_delay;
wire [1:0] RXMONITORSEL_delay;
wire [1:0] RXPD_delay;
wire [1:0] RXPLLCLKSEL_delay;
wire [1:0] RXSYSCLKSEL_delay;
wire [1:0] TXPD_delay;
wire [1:0] TXPLLCLKSEL_delay;
wire [1:0] TXSYSCLKSEL_delay;
wire [2:0] CPLLREFCLKSEL_delay;
wire [2:0] LOOPBACK_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [2:0] RXOUTCLKSEL_delay;
wire [2:0] RXRATE_delay;
wire [2:0] TXBUFDIFFCTRL_delay;
wire [2:0] TXMARGIN_delay;
wire [2:0] TXOUTCLKSEL_delay;
wire [2:0] TXRATE_delay;
wire [3:0] RXOSINTCFG_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXDIFFCTRL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] PCSRSVDIN2_delay;
wire [4:0] PMARSVDIN_delay;
wire [4:0] RXCHBONDI_delay;
wire [4:0] TXPIPPMSTEPSIZE_delay;
wire [4:0] TXPOSTCURSOR_delay;
wire [4:0] TXPRECURSOR_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXMAINCURSOR_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [7:0] TXDATAEXTENDRSVD_delay;
wire [8:0] DRPADDR_delay;
assign #(out_delay) BUFGTCE = BUFGTCE_delay;
assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay;
assign #(out_delay) BUFGTDIV = BUFGTDIV_delay;
assign #(out_delay) BUFGTRESET = BUFGTRESET_delay;
assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay;
assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay;
assign #(out_delay) CPLLLOCK = CPLLLOCK_delay;
assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay;
assign #(out_delay) DMONITOROUT = DMONITOROUT_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay;
assign #(out_delay) GTHTXN = GTHTXN_delay;
assign #(out_delay) GTHTXP = GTHTXP_delay;
assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay;
assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay;
assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay;
assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay;
assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay;
assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay;
assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay;
assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay;
assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay;
assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay;
assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay;
assign #(out_delay) PHYSTATUS = PHYSTATUS_delay;
assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay;
assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay;
assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay;
assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay;
assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay;
assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay;
assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay;
assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay;
assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay;
assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay;
assign #(out_delay) RXCHBONDO = RXCHBONDO_delay;
assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay;
assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay;
assign #(out_delay) RXCOMMADET = RXCOMMADET_delay;
assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay;
assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay;
assign #(out_delay) RXCTRL0 = RXCTRL0_delay;
assign #(out_delay) RXCTRL1 = RXCTRL1_delay;
assign #(out_delay) RXCTRL2 = RXCTRL2_delay;
assign #(out_delay) RXCTRL3 = RXCTRL3_delay;
assign #(out_delay) RXDATA = RXDATA_delay;
assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay;
assign #(out_delay) RXDATAVALID = RXDATAVALID_delay;
assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay;
assign #(out_delay) RXELECIDLE = RXELECIDLE_delay;
assign #(out_delay) RXHEADER = RXHEADER_delay;
assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay;
assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay;
assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay;
assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay;
assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay;
assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay;
assign #(out_delay) RXOUTCLK = RXOUTCLK_delay;
assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay;
assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay;
assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay;
assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay;
assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay;
assign #(out_delay) RXPRBSERR = RXPRBSERR_delay;
assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay;
assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay;
assign #(out_delay) RXQPISENN = RXQPISENN_delay;
assign #(out_delay) RXQPISENP = RXQPISENP_delay;
assign #(out_delay) RXRATEDONE = RXRATEDONE_delay;
assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay;
assign #(out_delay) RXRESETDONE = RXRESETDONE_delay;
assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay;
assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay;
assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay;
assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay;
assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay;
assign #(out_delay) RXSTATUS = RXSTATUS_delay;
assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay;
assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay;
assign #(out_delay) RXVALID = RXVALID_delay;
assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay;
assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay;
assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay;
assign #(out_delay) TXOUTCLK = TXOUTCLK_delay;
assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay;
assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay;
assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay;
assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay;
assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay;
assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay;
assign #(out_delay) TXQPISENN = TXQPISENN_delay;
assign #(out_delay) TXQPISENP = TXQPISENP_delay;
assign #(out_delay) TXRATEDONE = TXRATEDONE_delay;
assign #(out_delay) TXRESETDONE = TXRESETDONE_delay;
assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay;
assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2;
assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK;
assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) RX8B10BEN_delay = RX8B10BEN;
assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN;
assign #(in_delay) RXCHBONDI_delay = RXCHBONDI;
assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL;
assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER;
assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE;
assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN;
assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP;
assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN;
assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN;
assign #(in_delay) RXPOLARITY_delay = RXPOLARITY;
assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET;
assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL;
assign #(in_delay) RXRATE_delay = RXRATE;
assign #(in_delay) RXSLIDE_delay = RXSLIDE;
assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK;
assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA;
assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS;
assign #(in_delay) TX8B10BEN_delay = TX8B10BEN;
assign #(in_delay) TXCOMINIT_delay = TXCOMINIT;
assign #(in_delay) TXCOMSAS_delay = TXCOMSAS;
assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE;
assign #(in_delay) TXCTRL0_delay = TXCTRL0;
assign #(in_delay) TXCTRL1_delay = TXCTRL1;
assign #(in_delay) TXCTRL2_delay = TXCTRL2;
assign #(in_delay) TXDATA_delay = TXDATA;
assign #(in_delay) TXDETECTRX_delay = TXDETECTRX;
assign #(in_delay) TXELECIDLE_delay = TXELECIDLE;
assign #(in_delay) TXHEADER_delay = TXHEADER;
assign #(in_delay) TXINHIBIT_delay = TXINHIBIT;
assign #(in_delay) TXPD_delay = TXPD;
assign #(in_delay) TXPOLARITY_delay = TXPOLARITY;
assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR;
assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL;
assign #(in_delay) TXRATE_delay = TXRATE;
assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0;
assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1;
assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK;
assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK;
assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK;
assign #(inclk_delay) RXLATCLK_delay = RXLATCLK;
assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK;
assign #(inclk_delay) TXLATCLK_delay = TXLATCLK;
assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK;
assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK;
assign #(in_delay) CFGRESET_delay = CFGRESET;
assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN;
assign #(in_delay) CPLLPD_delay = CPLLPD;
assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL;
assign #(in_delay) CPLLRESET_delay = CPLLRESET;
assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET;
assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE;
assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART;
assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN;
assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN;
assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN;
assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN;
assign #(in_delay) EYESCANMODE_delay = EYESCANMODE;
assign #(in_delay) EYESCANRESET_delay = EYESCANRESET;
assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER;
assign #(in_delay) GTHRXN_delay = GTHRXN;
assign #(in_delay) GTHRXP_delay = GTHRXP;
assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0;
assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1;
assign #(in_delay) GTREFCLK0_delay = GTREFCLK0;
assign #(in_delay) GTREFCLK1_delay = GTREFCLK1;
assign #(in_delay) GTRESETSEL_delay = GTRESETSEL;
assign #(in_delay) GTRSVD_delay = GTRSVD;
assign #(in_delay) GTRXRESET_delay = GTRXRESET;
assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0;
assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1;
assign #(in_delay) GTTXRESET_delay = GTTXRESET;
assign #(in_delay) LOOPBACK_delay = LOOPBACK;
assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN;
assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN;
assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE;
assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE;
assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART;
assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE;
assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2;
assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN;
assign #(in_delay) PMARSVDIN_delay = PMARSVDIN;
assign #(in_delay) QPLL0CLK_delay = QPLL0CLK;
assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK;
assign #(in_delay) QPLL1CLK_delay = QPLL1CLK;
assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK;
assign #(in_delay) RESETOVRD_delay = RESETOVRD;
assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX;
assign #(in_delay) RXBUFRESET_delay = RXBUFRESET;
assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET;
assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD;
assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN;
assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV;
assign #(in_delay) RXCDRRESET_delay = RXCDRRESET;
assign #(in_delay) RXDFEAGCCTRL_delay = RXDFEAGCCTRL;
assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD;
assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN;
assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD;
assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN;
assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET;
assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD;
assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN;
assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD;
assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN;
assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD;
assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN;
assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD;
assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN;
assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD;
assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN;
assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD;
assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN;
assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD;
assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN;
assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD;
assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN;
assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD;
assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN;
assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD;
assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN;
assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD;
assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN;
assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD;
assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN;
assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD;
assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN;
assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD;
assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN;
assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD;
assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN;
assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD;
assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN;
assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN;
assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN;
assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS;
assign #(in_delay) RXDLYEN_delay = RXDLYEN;
assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN;
assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET;
assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE;
assign #(in_delay) RXLPMEN_delay = RXLPMEN;
assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD;
assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN;
assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD;
assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN;
assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD;
assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN;
assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD;
assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN;
assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL;
assign #(in_delay) RXOOBRESET_delay = RXOOBRESET;
assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET;
assign #(in_delay) RXOSHOLD_delay = RXOSHOLD;
assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG;
assign #(in_delay) RXOSINTEN_delay = RXOSINTEN;
assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD;
assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN;
assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE;
assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN;
assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN;
assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL;
assign #(in_delay) RXPCSRESET_delay = RXPCSRESET;
assign #(in_delay) RXPD_delay = RXPD;
assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN;
assign #(in_delay) RXPHALIGN_delay = RXPHALIGN;
assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD;
assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET;
assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN;
assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL;
assign #(in_delay) RXPMARESET_delay = RXPMARESET;
assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET;
assign #(in_delay) RXQPIEN_delay = RXQPIEN;
assign #(in_delay) RXRATEMODE_delay = RXRATEMODE;
assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN;
assign #(in_delay) RXSYNCIN_delay = RXSYNCIN;
assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE;
assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL;
assign #(in_delay) RXUSERRDY_delay = RXUSERRDY;
assign #(in_delay) TSTIN_delay = TSTIN;
assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL;
assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD;
assign #(in_delay) TXDEEMPH_delay = TXDEEMPH;
assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL;
assign #(in_delay) TXDIFFPD_delay = TXDIFFPD;
assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS;
assign #(in_delay) TXDLYEN_delay = TXDLYEN;
assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD;
assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN;
assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET;
assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN;
assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR;
assign #(in_delay) TXMARGIN_delay = TXMARGIN;
assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL;
assign #(in_delay) TXPCSRESET_delay = TXPCSRESET;
assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE;
assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN;
assign #(in_delay) TXPHALIGN_delay = TXPHALIGN;
assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD;
assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET;
assign #(in_delay) TXPHINIT_delay = TXPHINIT;
assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN;
assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN;
assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN;
assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD;
assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL;
assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE;
assign #(in_delay) TXPISOPD_delay = TXPISOPD;
assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL;
assign #(in_delay) TXPMARESET_delay = TXPMARESET;
assign #(in_delay) TXPOSTCURSORINV_delay = TXPOSTCURSORINV;
assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR;
assign #(in_delay) TXPRECURSORINV_delay = TXPRECURSORINV;
assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR;
assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET;
assign #(in_delay) TXQPIBIASEN_delay = TXQPIBIASEN;
assign #(in_delay) TXQPISTRONGPDOWN_delay = TXQPISTRONGPDOWN;
assign #(in_delay) TXQPIWEAKPUP_delay = TXQPIWEAKPUP;
assign #(in_delay) TXRATEMODE_delay = TXRATEMODE;
assign #(in_delay) TXSWING_delay = TXSWING;
assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN;
assign #(in_delay) TXSYNCIN_delay = TXSYNCIN;
assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE;
assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL;
assign #(in_delay) TXUSERRDY_delay = TXUSERRDY;
assign BUFGTCEMASK_delay = BUFGTCEMASK_out;
assign BUFGTCE_delay = BUFGTCE_out;
assign BUFGTDIV_delay = BUFGTDIV_out;
assign BUFGTRESET_delay = BUFGTRESET_out;
assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out;
assign CPLLLOCK_delay = CPLLLOCK_out;
assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out;
assign DMONITOROUT_delay = DMONITOROUT_out;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out;
assign GTHTXN_delay = GTHTXN_out;
assign GTHTXP_delay = GTHTXP_out;
assign GTPOWERGOOD_delay = GTPOWERGOOD_out;
assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out;
assign PCIERATEGEN3_delay = PCIERATEGEN3_out;
assign PCIERATEIDLE_delay = PCIERATEIDLE_out;
assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out;
assign PCSRSVDOUT_delay = PCSRSVDOUT_out;
assign PHYSTATUS_delay = PHYSTATUS_out;
assign PINRSRVDAS_delay = PINRSRVDAS_out;
assign RESETEXCEPTION_delay = RESETEXCEPTION_out;
assign RXBUFSTATUS_delay = RXBUFSTATUS_out;
assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out;
assign RXCDRLOCK_delay = RXCDRLOCK_out;
assign RXCDRPHDONE_delay = RXCDRPHDONE_out;
assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out;
assign RXCHANREALIGN_delay = RXCHANREALIGN_out;
assign RXCHBONDO_delay = RXCHBONDO_out;
assign RXCLKCORCNT_delay = RXCLKCORCNT_out;
assign RXCOMINITDET_delay = RXCOMINITDET_out;
assign RXCOMMADET_delay = RXCOMMADET_out;
assign RXCOMSASDET_delay = RXCOMSASDET_out;
assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out;
assign RXCTRL0_delay = RXCTRL0_out;
assign RXCTRL1_delay = RXCTRL1_out;
assign RXCTRL2_delay = RXCTRL2_out;
assign RXCTRL3_delay = RXCTRL3_out;
assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out;
assign RXDATAVALID_delay = RXDATAVALID_out;
assign RXDATA_delay = RXDATA_out;
assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out;
assign RXELECIDLE_delay = RXELECIDLE_out;
assign RXHEADERVALID_delay = RXHEADERVALID_out;
assign RXHEADER_delay = RXHEADER_out;
assign RXMONITOROUT_delay = RXMONITOROUT_out;
assign RXOSINTDONE_delay = RXOSINTDONE_out;
assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out;
assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out;
assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out;
assign RXOUTCLK_delay = RXOUTCLK_out;
assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out;
assign RXPHALIGNERR_delay = RXPHALIGNERR_out;
assign RXPMARESETDONE_delay = RXPMARESETDONE_out;
assign RXPRBSERR_delay = RXPRBSERR_out;
assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out;
assign RXQPISENN_delay = RXQPISENN_out;
assign RXQPISENP_delay = RXQPISENP_out;
assign RXRATEDONE_delay = RXRATEDONE_out;
assign RXRECCLKOUT_delay = RXRECCLKOUT_out;
assign RXRESETDONE_delay = RXRESETDONE_out;
assign RXSLIDERDY_delay = RXSLIDERDY_out;
assign RXSLIPDONE_delay = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out;
assign RXSTATUS_delay = RXSTATUS_out;
assign RXSYNCDONE_delay = RXSYNCDONE_out;
assign RXSYNCOUT_delay = RXSYNCOUT_out;
assign RXVALID_delay = RXVALID_out;
assign TXBUFSTATUS_delay = TXBUFSTATUS_out;
assign TXCOMFINISH_delay = TXCOMFINISH_out;
assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out;
assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out;
assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out;
assign TXOUTCLK_delay = TXOUTCLK_out;
assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out;
assign TXPHINITDONE_delay = TXPHINITDONE_out;
assign TXPMARESETDONE_delay = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out;
assign TXQPISENN_delay = TXQPISENN_out;
assign TXQPISENP_delay = TXQPISENP_out;
assign TXRATEDONE_delay = TXRATEDONE_out;
assign TXRESETDONE_delay = TXRESETDONE_out;
assign TXSYNCDONE_delay = TXSYNCDONE_out;
assign TXSYNCOUT_delay = TXSYNCOUT_out;
assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET_delay; // rv 0
assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0_delay; // rv 0
assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1_delay; // rv 0
assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK_delay; // rv 0
assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN_delay; // rv 0
assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD_delay; // rv 0
assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL_delay[0]; // rv 1
assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL_delay[1]; // rv 0
assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL_delay[2]; // rv 0
assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET_delay; // rv 0
assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET_delay; // rv 0
assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK_delay; // rv 0
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign EVODDPHICALDONE_in = (EVODDPHICALDONE !== 1'bz) && EVODDPHICALDONE_delay; // rv 0
assign EVODDPHICALSTART_in = (EVODDPHICALSTART !== 1'bz) && EVODDPHICALSTART_delay; // rv 0
assign EVODDPHIDRDEN_in = (EVODDPHIDRDEN !== 1'bz) && EVODDPHIDRDEN_delay; // rv 0
assign EVODDPHIDWREN_in = (EVODDPHIDWREN !== 1'bz) && EVODDPHIDWREN_delay; // rv 0
assign EVODDPHIXRDEN_in = (EVODDPHIXRDEN !== 1'bz) && EVODDPHIXRDEN_delay; // rv 0
assign EVODDPHIXWREN_in = (EVODDPHIXWREN !== 1'bz) && EVODDPHIXWREN_delay; // rv 0
assign EYESCANMODE_in = (EYESCANMODE !== 1'bz) && EYESCANMODE_delay; // rv 0
assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET_delay; // rv 0
assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER_delay; // rv 0
assign GTGREFCLK_in = GTGREFCLK_delay;
assign GTHRXN_in = GTHRXN_delay;
assign GTHRXP_in = GTHRXP_delay;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay;
assign GTREFCLK0_in = GTREFCLK0_delay;
assign GTREFCLK1_in = GTREFCLK1_delay;
assign GTRESETSEL_in = (GTRESETSEL !== 1'bz) && GTRESETSEL_delay; // rv 0
assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD_delay[0]; // rv 0
assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD_delay[10]; // rv 0
assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD_delay[11]; // rv 0
assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD_delay[12]; // rv 0
assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD_delay[13]; // rv 0
assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD_delay[14]; // rv 0
assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD_delay[15]; // rv 0
assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD_delay[1]; // rv 0
assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD_delay[2]; // rv 0
assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD_delay[3]; // rv 0
assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD_delay[4]; // rv 0
assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD_delay[5]; // rv 0
assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD_delay[6]; // rv 0
assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD_delay[7]; // rv 0
assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD_delay[8]; // rv 0
assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD_delay[9]; // rv 0
assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET_delay; // rv 0
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay;
assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET_delay; // rv 0
assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK_delay[0]; // rv 0
assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK_delay[1]; // rv 0
assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK_delay[2]; // rv 0
assign LPBKRXTXSEREN_in = (LPBKRXTXSEREN !== 1'bz) && LPBKRXTXSEREN_delay; // rv 0
assign LPBKTXRXSEREN_in = (LPBKTXRXSEREN !== 1'bz) && LPBKTXRXSEREN_delay; // rv 0
assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE_delay; // rv 0
assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE_delay; // rv 0
assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART_delay; // rv 0
assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE_delay; // rv 0
assign PCSRSVDIN2_in[0] = (PCSRSVDIN2[0] !== 1'bz) && PCSRSVDIN2_delay[0]; // rv 0
assign PCSRSVDIN2_in[1] = (PCSRSVDIN2[1] !== 1'bz) && PCSRSVDIN2_delay[1]; // rv 0
assign PCSRSVDIN2_in[2] = (PCSRSVDIN2[2] !== 1'bz) && PCSRSVDIN2_delay[2]; // rv 0
assign PCSRSVDIN2_in[3] = (PCSRSVDIN2[3] !== 1'bz) && PCSRSVDIN2_delay[3]; // rv 0
assign PCSRSVDIN2_in[4] = (PCSRSVDIN2[4] !== 1'bz) && PCSRSVDIN2_delay[4]; // rv 0
assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] !== 1'bz) && PCSRSVDIN_delay[0]; // rv 0
assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN_delay[10]; // rv 0
assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN_delay[11]; // rv 0
assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN_delay[12]; // rv 0
assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN_delay[13]; // rv 0
assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN_delay[14]; // rv 0
assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN_delay[15]; // rv 0
assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN_delay[1]; // rv 0
assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN_delay[2]; // rv 0
assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN_delay[3]; // rv 0
assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN_delay[4]; // rv 0
assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN_delay[5]; // rv 0
assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN_delay[6]; // rv 0
assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN_delay[7]; // rv 0
assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN_delay[8]; // rv 0
assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN_delay[9]; // rv 0
assign PMARSVDIN_in[0] = (PMARSVDIN[0] !== 1'bz) && PMARSVDIN_delay[0]; // rv 0
assign PMARSVDIN_in[1] = (PMARSVDIN[1] !== 1'bz) && PMARSVDIN_delay[1]; // rv 0
assign PMARSVDIN_in[2] = (PMARSVDIN[2] !== 1'bz) && PMARSVDIN_delay[2]; // rv 0
assign PMARSVDIN_in[3] = (PMARSVDIN[3] !== 1'bz) && PMARSVDIN_delay[3]; // rv 0
assign PMARSVDIN_in[4] = (PMARSVDIN[4] !== 1'bz) && PMARSVDIN_delay[4]; // rv 0
assign QPLL0CLK_in = QPLL0CLK_delay;
assign QPLL0REFCLK_in = QPLL0REFCLK_delay;
assign QPLL1CLK_in = QPLL1CLK_delay;
assign QPLL1REFCLK_in = QPLL1REFCLK_delay;
assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD_delay; // rv 0
assign RSTCLKENTX_in = (RSTCLKENTX !== 1'bz) && RSTCLKENTX_delay; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0
assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET_delay; // rv 0
assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET_delay; // rv 0
assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD_delay; // rv 0
assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN_delay; // rv 0
assign RXCDRRESETRSV_in = (RXCDRRESETRSV !== 1'bz) && RXCDRRESETRSV_delay; // rv 0
assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET_delay; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0
assign RXDFEAGCCTRL_in[0] = (RXDFEAGCCTRL[0] !== 1'bz) && RXDFEAGCCTRL_delay[0]; // rv 0
assign RXDFEAGCCTRL_in[1] = (RXDFEAGCCTRL[1] !== 1'bz) && RXDFEAGCCTRL_delay[1]; // rv 0
assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD_delay; // rv 0
assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN_delay; // rv 0
assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD_delay; // rv 0
assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN_delay; // rv 0
assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET_delay; // rv 0
assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD_delay; // rv 0
assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN_delay; // rv 0
assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD_delay; // rv 0
assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN_delay; // rv 0
assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD_delay; // rv 0
assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN_delay; // rv 0
assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD_delay; // rv 0
assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN_delay; // rv 0
assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD_delay; // rv 0
assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN_delay; // rv 0
assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD_delay; // rv 0
assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN_delay; // rv 0
assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD_delay; // rv 0
assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN_delay; // rv 0
assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD_delay; // rv 0
assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN_delay; // rv 0
assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD_delay; // rv 0
assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN_delay; // rv 0
assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD_delay; // rv 0
assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN_delay; // rv 0
assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD_delay; // rv 0
assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN_delay; // rv 0
assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD_delay; // rv 0
assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN_delay; // rv 0
assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD_delay; // rv 0
assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN_delay; // rv 0
assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD_delay; // rv 0
assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN_delay; // rv 0
assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD_delay; // rv 0
assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN_delay; // rv 0
assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD_delay; // rv 0
assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN_delay; // rv 0
assign RXDFEVSEN_in = (RXDFEVSEN !== 1'bz) && RXDFEVSEN_delay; // rv 0
assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN_delay; // rv 0
assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS_delay; // rv 0
assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN_delay; // rv 0
assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN_delay; // rv 0
assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET_delay; // rv 0
assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE_delay[0]; // rv 0
assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE_delay[1]; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0
assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK_delay; // rv 0
assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN_delay; // rv 0
assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD_delay; // rv 0
assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN_delay; // rv 0
assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD_delay; // rv 0
assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN_delay; // rv 0
assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD_delay; // rv 0
assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN_delay; // rv 0
assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD_delay; // rv 0
assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN_delay; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0
assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL_delay[0]; // rv 0
assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL_delay[1]; // rv 0
assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET_delay; // rv 0
assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET_delay; // rv 0
assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD_delay; // rv 0
assign RXOSINTCFG_in[0] = (RXOSINTCFG[0] !== 1'bz) && RXOSINTCFG_delay[0]; // rv 0
assign RXOSINTCFG_in[1] = (RXOSINTCFG[1] === 1'bz) || RXOSINTCFG_delay[1]; // rv 1
assign RXOSINTCFG_in[2] = (RXOSINTCFG[2] === 1'bz) || RXOSINTCFG_delay[2]; // rv 1
assign RXOSINTCFG_in[3] = (RXOSINTCFG[3] !== 1'bz) && RXOSINTCFG_delay[3]; // rv 0
assign RXOSINTEN_in = (RXOSINTEN === 1'bz) || RXOSINTEN_delay; // rv 1
assign RXOSINTHOLD_in = (RXOSINTHOLD !== 1'bz) && RXOSINTHOLD_delay; // rv 0
assign RXOSINTOVRDEN_in = (RXOSINTOVRDEN !== 1'bz) && RXOSINTOVRDEN_delay; // rv 0
assign RXOSINTSTROBE_in = (RXOSINTSTROBE !== 1'bz) && RXOSINTSTROBE_delay; // rv 0
assign RXOSINTTESTOVRDEN_in = (RXOSINTTESTOVRDEN !== 1'bz) && RXOSINTTESTOVRDEN_delay; // rv 0
assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN_delay; // rv 0
assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL_delay[0]; // rv 0
assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL_delay[1]; // rv 0
assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL_delay[2]; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0
assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET_delay; // rv 0
assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD_delay[0]; // rv 0
assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD_delay[1]; // rv 0
assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN_delay; // rv 0
assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN_delay; // rv 0
assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD_delay; // rv 0
assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET_delay; // rv 0
assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN_delay; // rv 0
assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL_delay[0]; // rv 0
assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL_delay[1]; // rv 0
assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET_delay; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0
assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET_delay; // rv 0
assign RXQPIEN_in = (RXQPIEN !== 1'bz) && RXQPIEN_delay; // rv 0
assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE_delay; // rv 0
assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0
assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0
assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0
assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0
assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN_delay; // rv 0
assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN_delay; // rv 0
assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE_delay; // rv 1
assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL_delay[0]; // rv 0
assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL_delay[1]; // rv 0
assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY_delay; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0
assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK_delay; // rv 0
assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN_delay[0]; // rv 0
assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN_delay[10]; // rv 0
assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN_delay[11]; // rv 0
assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN_delay[12]; // rv 0
assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN_delay[13]; // rv 0
assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN_delay[14]; // rv 0
assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN_delay[15]; // rv 0
assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN_delay[16]; // rv 0
assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN_delay[17]; // rv 0
assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN_delay[18]; // rv 0
assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN_delay[19]; // rv 0
assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN_delay[1]; // rv 0
assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN_delay[2]; // rv 0
assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN_delay[3]; // rv 0
assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN_delay[4]; // rv 0
assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN_delay[5]; // rv 0
assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN_delay[6]; // rv 0
assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN_delay[7]; // rv 0
assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN_delay[8]; // rv 0
assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN_delay[9]; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0
assign TXBUFDIFFCTRL_in[0] = (TXBUFDIFFCTRL[0] !== 1'bz) && TXBUFDIFFCTRL_delay[0]; // rv 0
assign TXBUFDIFFCTRL_in[1] = (TXBUFDIFFCTRL[1] !== 1'bz) && TXBUFDIFFCTRL_delay[1]; // rv 0
assign TXBUFDIFFCTRL_in[2] = (TXBUFDIFFCTRL[2] !== 1'bz) && TXBUFDIFFCTRL_delay[2]; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0
assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD_delay[0]; // rv 0
assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD_delay[1]; // rv 0
assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD_delay[2]; // rv 0
assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD_delay[3]; // rv 0
assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD_delay[4]; // rv 0
assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD_delay[5]; // rv 0
assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD_delay[6]; // rv 0
assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD_delay[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0
assign TXDEEMPH_in = (TXDEEMPH !== 1'bz) && TXDEEMPH_delay; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0
assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL_delay[0]; // rv 0
assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL_delay[1]; // rv 0
assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL_delay[2]; // rv 0
assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL_delay[3]; // rv 0
assign TXDIFFPD_in = (TXDIFFPD !== 1'bz) && TXDIFFPD_delay; // rv 0
assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS_delay; // rv 0
assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN_delay; // rv 0
assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD_delay; // rv 0
assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN_delay; // rv 0
assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET_delay; // rv 0
assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN_delay; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0
assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK_delay; // rv 0
assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR_delay[0]; // rv 0
assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR_delay[1]; // rv 0
assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR_delay[2]; // rv 0
assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR_delay[3]; // rv 0
assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR_delay[4]; // rv 0
assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR_delay[5]; // rv 0
assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR_delay[6]; // rv 0
assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN_delay[0]; // rv 0
assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN_delay[1]; // rv 0
assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN_delay[2]; // rv 0
assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL_delay[0]; // rv 0
assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL_delay[1]; // rv 0
assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL_delay[2]; // rv 0
assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET_delay; // rv 0
assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE_delay; // rv 0
assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0
assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0
assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN_delay; // rv 0
assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN_delay; // rv 0
assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD_delay; // rv 0
assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET_delay; // rv 0
assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK_delay; // rv 0
assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT_delay; // rv 0
assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN_delay; // rv 0
assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN_delay; // rv 0
assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN_delay; // rv 0
assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD_delay; // rv 0
assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL_delay; // rv 0
assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE_delay[0]; // rv 0
assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE_delay[1]; // rv 0
assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE_delay[2]; // rv 0
assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE_delay[3]; // rv 0
assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE_delay[4]; // rv 0
assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD_delay; // rv 0
assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL_delay[0]; // rv 0
assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL_delay[1]; // rv 0
assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET_delay; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0
assign TXPOSTCURSORINV_in = (TXPOSTCURSORINV !== 1'bz) && TXPOSTCURSORINV_delay; // rv 0
assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR_delay[0]; // rv 0
assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR_delay[1]; // rv 0
assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR_delay[2]; // rv 0
assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR_delay[3]; // rv 0
assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR_delay[4]; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0
assign TXPRECURSORINV_in = (TXPRECURSORINV !== 1'bz) && TXPRECURSORINV_delay; // rv 0
assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR_delay[0]; // rv 0
assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR_delay[1]; // rv 0
assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR_delay[2]; // rv 0
assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR_delay[3]; // rv 0
assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR_delay[4]; // rv 0
assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET_delay; // rv 0
assign TXQPIBIASEN_in = (TXQPIBIASEN !== 1'bz) && TXQPIBIASEN_delay; // rv 0
assign TXQPISTRONGPDOWN_in = (TXQPISTRONGPDOWN !== 1'bz) && TXQPISTRONGPDOWN_delay; // rv 0
assign TXQPIWEAKPUP_in = (TXQPIWEAKPUP !== 1'bz) && TXQPIWEAKPUP_delay; // rv 0
assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE_delay; // rv 0
assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0
assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0
assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0
assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING_delay; // rv 0
assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN_delay; // rv 0
assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN_delay; // rv 0
assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE_delay; // rv 1
assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL_delay[0]; // rv 0
assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL_delay[1]; // rv 0
assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY_delay; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0
assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK_delay; // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin
$display("Error: [Unisim %s-276] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin
$display("Error: [Unisim %s-277] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-279] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-303] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin
$display("Error: [Unisim %s-381] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin
$display("Error: [Unisim %s-383] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin
$display("Error: [Unisim %s-485] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-495] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin
$display("Error: [Unisim %s-528] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127))) begin
$display("Error: [Unisim %s-538] SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63))) begin
$display("Error: [Unisim %s-539] SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63))) begin
$display("Error: [Unisim %s-544] SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63))) begin
$display("Error: [Unisim %s-545] SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-546] SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61))) begin
$display("Error: [Unisim %s-547] SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63))) begin
$display("Error: [Unisim %s-548] SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-549] SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-595] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_DEBUG_MODE_REG !== 1'b0) && (ACJTAG_DEBUG_MODE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-101] ACJTAG_DEBUG_MODE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_DEBUG_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_MODE_REG !== 1'b0) && (ACJTAG_MODE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] ACJTAG_MODE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_RESET_REG !== 1'b0) && (ACJTAG_RESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] ACJTAG_RESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_RESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG0_REG < 16'h0000) || (ADAPT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-104] ADAPT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ADAPT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG1_REG < 16'h0000) || (ADAPT_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-105] ADAPT_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ADAPT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-128] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_ENABLE_REG < 10'b0000000000) || (ALIGN_COMMA_ENABLE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-129] ALIGN_COMMA_ENABLE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_COMMA_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4))) begin
$display("Error: [Unisim %s-130] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-131] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_MCOMMA_VALUE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-132] ALIGN_MCOMMA_VALUE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-133] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_PCOMMA_VALUE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-134] ALIGN_PCOMMA_VALUE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_RXOSCALRESET_REG !== 1'b0) && (A_RXOSCALRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-204] A_RXOSCALRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_RXOSCALRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_RXPROGDIVRESET_REG !== 1'b0) && (A_RXPROGDIVRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-220] A_RXPROGDIVRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_RXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_TXPROGDIVRESET_REG !== 1'b0) && (A_TXPROGDIVRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-254] A_TXPROGDIVRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_TXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin
$display("Error: [Unisim %s-258] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CDR_SWAP_MODE_EN_REG !== 1'b0) && (CDR_SWAP_MODE_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-259] CDR_SWAP_MODE_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, CDR_SWAP_MODE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-260] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14))) begin
$display("Error: [Unisim %s-261] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-262] CHAN_BOND_SEQ_1_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-263] CHAN_BOND_SEQ_1_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-264] CHAN_BOND_SEQ_1_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-265] CHAN_BOND_SEQ_1_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_1_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-266] CHAN_BOND_SEQ_1_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-267] CHAN_BOND_SEQ_2_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-268] CHAN_BOND_SEQ_2_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-269] CHAN_BOND_SEQ_2_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-270] CHAN_BOND_SEQ_2_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_2_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-271] CHAN_BOND_SEQ_2_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-272] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-273] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-274] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-275] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-278] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_1_REG < 10'b0000000000) || (CLK_COR_SEQ_1_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-280] CLK_COR_SEQ_1_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_2_REG < 10'b0000000000) || (CLK_COR_SEQ_1_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-281] CLK_COR_SEQ_1_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_3_REG < 10'b0000000000) || (CLK_COR_SEQ_1_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-282] CLK_COR_SEQ_1_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_4_REG < 10'b0000000000) || (CLK_COR_SEQ_1_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-283] CLK_COR_SEQ_1_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_1_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-284] CLK_COR_SEQ_1_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_1_REG < 10'b0000000000) || (CLK_COR_SEQ_2_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-285] CLK_COR_SEQ_2_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_2_REG < 10'b0000000000) || (CLK_COR_SEQ_2_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-286] CLK_COR_SEQ_2_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_3_REG < 10'b0000000000) || (CLK_COR_SEQ_2_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-287] CLK_COR_SEQ_2_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_4_REG < 10'b0000000000) || (CLK_COR_SEQ_2_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-288] CLK_COR_SEQ_2_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_2_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-289] CLK_COR_SEQ_2_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-290] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-291] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG0_REG < 16'h0000) || (CPLL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-292] CPLL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG1_REG < 16'h0000) || (CPLL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-293] CPLL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG2_REG < 16'h0000) || (CPLL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-294] CPLL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG3_REG < 6'h00) || (CPLL_CFG3_REG > 6'h3F))) begin
$display("Error: [Unisim %s-295] CPLL_CFG3 attribute is set to %h. Legal values for this attribute are 6'h00 to 6'h3F. Instance: %m", MODULE_NAME, CPLL_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5))) begin
$display("Error: [Unisim %s-297] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20))) begin
$display("Error: [Unisim %s-296] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_INIT_CFG0_REG < 16'h0000) || (CPLL_INIT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-298] CPLL_INIT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_INIT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_INIT_CFG1_REG < 8'h00) || (CPLL_INIT_CFG1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-299] CPLL_INIT_CFG1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, CPLL_INIT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_LOCK_CFG_REG < 16'h0000) || (CPLL_LOCK_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-300] CPLL_LOCK_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_LOCK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-301] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_CTRL_REG < 2'b00) || (DDI_CTRL_REG > 2'b11))) begin
$display("Error: [Unisim %s-302] DDI_CTRL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, DDI_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-304] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-305] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin
$display("Error: [Unisim %s-306] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DFE_D_X_REL_POS_REG !== 1'b0) && (DFE_D_X_REL_POS_REG !== 1'b1))) begin
$display("Error: [Unisim %s-307] DFE_D_X_REL_POS attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, DFE_D_X_REL_POS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DFE_VCM_COMP_EN_REG !== 1'b0) && (DFE_VCM_COMP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-308] DFE_VCM_COMP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, DFE_VCM_COMP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DMONITOR_CFG0_REG < 10'h000) || (DMONITOR_CFG0_REG > 10'h3FF))) begin
$display("Error: [Unisim %s-309] DMONITOR_CFG0 attribute is set to %h. Legal values for this attribute are 10'h000 to 10'h3FF. Instance: %m", MODULE_NAME, DMONITOR_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DMONITOR_CFG1_REG < 8'h00) || (DMONITOR_CFG1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-310] DMONITOR_CFG1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, DMONITOR_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_CLK_PHASE_SEL_REG !== 1'b0) && (ES_CLK_PHASE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-311] ES_CLK_PHASE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ES_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_CONTROL_REG < 6'b000000) || (ES_CONTROL_REG > 6'b111111))) begin
$display("Error: [Unisim %s-312] ES_CONTROL attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, ES_CONTROL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-313] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-314] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_HORZ_OFFSET_REG < 12'h000) || (ES_HORZ_OFFSET_REG > 12'hFFF))) begin
$display("Error: [Unisim %s-315] ES_HORZ_OFFSET attribute is set to %h. Legal values for this attribute are 12'h000 to 12'hFFF. Instance: %m", MODULE_NAME, ES_HORZ_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_PMA_CFG_REG < 10'b0000000000) || (ES_PMA_CFG_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-316] ES_PMA_CFG attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ES_PMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_PRESCALE_REG < 5'b00000) || (ES_PRESCALE_REG > 5'b11111))) begin
$display("Error: [Unisim %s-317] ES_PRESCALE attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, ES_PRESCALE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER0_REG < 16'h0000) || (ES_QUALIFIER0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-318] ES_QUALIFIER0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER1_REG < 16'h0000) || (ES_QUALIFIER1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-319] ES_QUALIFIER1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER2_REG < 16'h0000) || (ES_QUALIFIER2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-320] ES_QUALIFIER2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER3_REG < 16'h0000) || (ES_QUALIFIER3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-321] ES_QUALIFIER3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER4_REG < 16'h0000) || (ES_QUALIFIER4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-322] ES_QUALIFIER4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK0_REG < 16'h0000) || (ES_QUAL_MASK0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-323] ES_QUAL_MASK0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK1_REG < 16'h0000) || (ES_QUAL_MASK1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-324] ES_QUAL_MASK1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK2_REG < 16'h0000) || (ES_QUAL_MASK2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-325] ES_QUAL_MASK2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK3_REG < 16'h0000) || (ES_QUAL_MASK3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-326] ES_QUAL_MASK3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK4_REG < 16'h0000) || (ES_QUAL_MASK4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-327] ES_QUAL_MASK4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK0_REG < 16'h0000) || (ES_SDATA_MASK0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-328] ES_SDATA_MASK0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK1_REG < 16'h0000) || (ES_SDATA_MASK1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-329] ES_SDATA_MASK1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK2_REG < 16'h0000) || (ES_SDATA_MASK2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-330] ES_SDATA_MASK2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK3_REG < 16'h0000) || (ES_SDATA_MASK3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-331] ES_SDATA_MASK3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK4_REG < 16'h0000) || (ES_SDATA_MASK4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-332] ES_SDATA_MASK4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EVODD_PHI_CFG_REG < 11'b00000000000) || (EVODD_PHI_CFG_REG > 11'b11111111111))) begin
$display("Error: [Unisim %s-333] EVODD_PHI_CFG attribute is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111. Instance: %m", MODULE_NAME, EVODD_PHI_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EYE_SCAN_SWAP_EN_REG !== 1'b0) && (EYE_SCAN_SWAP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-334] EYE_SCAN_SWAP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, EYE_SCAN_SWAP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_DESKEW_SEQ_ENABLE_REG < 4'b0000) || (FTS_DESKEW_SEQ_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-335] FTS_DESKEW_SEQ_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, FTS_DESKEW_SEQ_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_CFG_REG < 4'b0000) || (FTS_LANE_DESKEW_CFG_REG > 4'b1111))) begin
$display("Error: [Unisim %s-336] FTS_LANE_DESKEW_CFG attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-337] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((GEARBOX_MODE_REG < 5'b00000) || (GEARBOX_MODE_REG > 5'b11111))) begin
$display("Error: [Unisim %s-338] GEARBOX_MODE attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, GEARBOX_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((GM_BIAS_SELECT_REG !== 1'b0) && (GM_BIAS_SELECT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-341] GM_BIAS_SELECT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, GM_BIAS_SELECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOCAL_MASTER_REG !== 1'b0) && (LOCAL_MASTER_REG !== 1'b1))) begin
$display("Error: [Unisim %s-343] LOCAL_MASTER attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, LOCAL_MASTER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OOBDIVCTL_REG < 2'b00) || (OOBDIVCTL_REG > 2'b11))) begin
$display("Error: [Unisim %s-344] OOBDIVCTL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, OOBDIVCTL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OOB_PWRUP_REG !== 1'b0) && (OOB_PWRUP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-345] OOB_PWRUP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, OOB_PWRUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin
$display("Error: [Unisim %s-346] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_PIPE_RX_ELECIDLE_REG !== 1'b0) && (PCI3_PIPE_RX_ELECIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-347] PCI3_PIPE_RX_ELECIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_PIPE_RX_ELECIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ASYNC_EBUF_BYPASS_REG < 2'b00) || (PCI3_RX_ASYNC_EBUF_BYPASS_REG > 2'b11))) begin
$display("Error: [Unisim %s-348] PCI3_RX_ASYNC_EBUF_BYPASS attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, PCI3_RX_ASYNC_EBUF_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_EI2_ENABLE_REG !== 1'b0) && (PCI3_RX_ELECIDLE_EI2_ENABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-349] PCI3_RX_ELECIDLE_EI2_ENABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_EI2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_H2L_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_H2L_COUNT_REG > 6'b111111))) begin
$display("Error: [Unisim %s-350] PCI3_RX_ELECIDLE_H2L_COUNT attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_COUNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_H2L_DISABLE_REG < 3'b000) || (PCI3_RX_ELECIDLE_H2L_DISABLE_REG > 3'b111))) begin
$display("Error: [Unisim %s-351] PCI3_RX_ELECIDLE_H2L_DISABLE attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_HI_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_HI_COUNT_REG > 6'b111111))) begin
$display("Error: [Unisim %s-352] PCI3_RX_ELECIDLE_HI_COUNT attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_HI_COUNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_LP4_DISABLE_REG !== 1'b0) && (PCI3_RX_ELECIDLE_LP4_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-353] PCI3_RX_ELECIDLE_LP4_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_LP4_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_FIFO_DISABLE_REG !== 1'b0) && (PCI3_RX_FIFO_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-354] PCI3_RX_FIFO_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_FIFO_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_BUFG_DIV_CTRL_REG < 16'h0000) || (PCIE_BUFG_DIV_CTRL_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-355] PCIE_BUFG_DIV_CTRL attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_BUFG_DIV_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_RXPCS_CFG_GEN3_REG < 16'h0000) || (PCIE_RXPCS_CFG_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-356] PCIE_RXPCS_CFG_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_RXPCS_CFG_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_RXPMA_CFG_REG < 16'h0000) || (PCIE_RXPMA_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-357] PCIE_RXPMA_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_RXPMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_TXPCS_CFG_GEN3_REG < 16'h0000) || (PCIE_TXPCS_CFG_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-358] PCIE_TXPCS_CFG_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_TXPCS_CFG_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_TXPMA_CFG_REG < 16'h0000) || (PCIE_TXPMA_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-359] PCIE_TXPMA_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_TXPMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-360] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_RSVD0_REG < 16'b0000000000000000) || (PCS_RSVD0_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-361] PCS_RSVD0 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, PCS_RSVD0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_RSVD1_REG < 3'b000) || (PCS_RSVD1_REG > 3'b111))) begin
$display("Error: [Unisim %s-362] PCS_RSVD1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PCS_RSVD1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_FROM_P2_REG < 12'h000) || (PD_TRANS_TIME_FROM_P2_REG > 12'hFFF))) begin
$display("Error: [Unisim %s-363] PD_TRANS_TIME_FROM_P2 attribute is set to %h. Legal values for this attribute are 12'h000 to 12'hFFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_FROM_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_NONE_P2_REG < 8'h00) || (PD_TRANS_TIME_NONE_P2_REG > 8'hFF))) begin
$display("Error: [Unisim %s-364] PD_TRANS_TIME_NONE_P2 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_NONE_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_TO_P2_REG < 8'h00) || (PD_TRANS_TIME_TO_P2_REG > 8'hFF))) begin
$display("Error: [Unisim %s-365] PD_TRANS_TIME_TO_P2 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_TO_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PLL_SEL_MODE_GEN12_REG < 2'h0) || (PLL_SEL_MODE_GEN12_REG > 2'h3))) begin
$display("Error: [Unisim %s-366] PLL_SEL_MODE_GEN12 attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, PLL_SEL_MODE_GEN12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PLL_SEL_MODE_GEN3_REG < 2'h0) || (PLL_SEL_MODE_GEN3_REG > 2'h3))) begin
$display("Error: [Unisim %s-367] PLL_SEL_MODE_GEN3 attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, PLL_SEL_MODE_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PMA_RSV1_REG < 16'h0000) || (PMA_RSV1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-368] PMA_RSV1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PMA_RSV1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROCESS_PAR_REG < 3'b000) || (PROCESS_PAR_REG > 3'b111))) begin
$display("Error: [Unisim %s-369] PROCESS_PAR attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PROCESS_PAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RATE_SW_USE_DRP_REG !== 1'b0) && (RATE_SW_USE_DRP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-370] RATE_SW_USE_DRP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RATE_SW_USE_DRP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RESET_POWERSAVE_DISABLE_REG !== 1'b0) && (RESET_POWERSAVE_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-371] RESET_POWERSAVE_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RESET_POWERSAVE_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUFRESET_TIME_REG < 5'b00000) || (RXBUFRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-372] RXBUFRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXBUFRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST"))) begin
$display("Error: [Unisim %s-373] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EIDLE_HI_CNT_REG < 4'b0000) || (RXBUF_EIDLE_HI_CNT_REG > 4'b1111))) begin
$display("Error: [Unisim %s-374] RXBUF_EIDLE_HI_CNT attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RXBUF_EIDLE_HI_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EIDLE_LO_CNT_REG < 4'b0000) || (RXBUF_EIDLE_LO_CNT_REG > 4'b1111))) begin
$display("Error: [Unisim %s-375] RXBUF_EIDLE_LO_CNT attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RXBUF_EIDLE_LO_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-376] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-377] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-378] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-379] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-380] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE"))) begin
$display("Error: [Unisim %s-382] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDRFREQRESET_TIME_REG < 5'b00000) || (RXCDRFREQRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-384] RXCDRFREQRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXCDRFREQRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDRPHRESET_TIME_REG < 5'b00000) || (RXCDRPHRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-385] RXCDRPHRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXCDRPHRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG0_GEN3_REG < 16'h0000) || (RXCDR_CFG0_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-387] RXCDR_CFG0_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG0_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG0_REG < 16'h0000) || (RXCDR_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-386] RXCDR_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG1_GEN3_REG < 16'h0000) || (RXCDR_CFG1_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-389] RXCDR_CFG1_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG1_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG1_REG < 16'h0000) || (RXCDR_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-388] RXCDR_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG2_GEN3_REG < 16'h0000) || (RXCDR_CFG2_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-391] RXCDR_CFG2_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG2_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG2_REG < 16'h0000) || (RXCDR_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-390] RXCDR_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG3_GEN3_REG < 16'h0000) || (RXCDR_CFG3_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-393] RXCDR_CFG3_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG3_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG3_REG < 16'h0000) || (RXCDR_CFG3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-392] RXCDR_CFG3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG4_GEN3_REG < 16'h0000) || (RXCDR_CFG4_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-395] RXCDR_CFG4_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG4_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG4_REG < 16'h0000) || (RXCDR_CFG4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-394] RXCDR_CFG4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG5_GEN3_REG < 16'h0000) || (RXCDR_CFG5_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-397] RXCDR_CFG5_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG5_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG5_REG < 16'h0000) || (RXCDR_CFG5_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-396] RXCDR_CFG5 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_FR_RESET_ON_EIDLE_REG !== 1'b0) && (RXCDR_FR_RESET_ON_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-398] RXCDR_FR_RESET_ON_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_FR_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_HOLD_DURING_EIDLE_REG !== 1'b0) && (RXCDR_HOLD_DURING_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-399] RXCDR_HOLD_DURING_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG0_REG < 16'h0000) || (RXCDR_LOCK_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-400] RXCDR_LOCK_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG1_REG < 16'h0000) || (RXCDR_LOCK_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-401] RXCDR_LOCK_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG2_REG < 16'h0000) || (RXCDR_LOCK_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-402] RXCDR_LOCK_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_PH_RESET_ON_EIDLE_REG !== 1'b0) && (RXCDR_PH_RESET_ON_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-403] RXCDR_PH_RESET_ON_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_PH_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG0_REG < 16'h0000) || (RXCFOK_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-404] RXCFOK_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG1_REG < 16'h0000) || (RXCFOK_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-405] RXCFOK_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG2_REG < 16'h0000) || (RXCFOK_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-406] RXCFOK_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPMRESET_TIME_REG < 7'b0000000) || (RXDFELPMRESET_TIME_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-407] RXDFELPMRESET_TIME attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, RXDFELPMRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG0_REG < 16'h0000) || (RXDFELPM_KL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-408] RXDFELPM_KL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG1_REG < 16'h0000) || (RXDFELPM_KL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-409] RXDFELPM_KL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG2_REG < 16'h0000) || (RXDFELPM_KL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-410] RXDFELPM_KL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_CFG0_REG < 16'h0000) || (RXDFE_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-411] RXDFE_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_CFG1_REG < 16'h0000) || (RXDFE_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-412] RXDFE_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG0_REG < 16'h0000) || (RXDFE_GC_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-413] RXDFE_GC_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG1_REG < 16'h0000) || (RXDFE_GC_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-414] RXDFE_GC_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG2_REG < 16'h0000) || (RXDFE_GC_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-415] RXDFE_GC_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H2_CFG0_REG < 16'h0000) || (RXDFE_H2_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-416] RXDFE_H2_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H2_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H2_CFG1_REG < 16'h0000) || (RXDFE_H2_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-417] RXDFE_H2_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H2_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H3_CFG0_REG < 16'h0000) || (RXDFE_H3_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-418] RXDFE_H3_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H3_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H3_CFG1_REG < 16'h0000) || (RXDFE_H3_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-419] RXDFE_H3_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H3_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H4_CFG0_REG < 16'h0000) || (RXDFE_H4_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-420] RXDFE_H4_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H4_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H4_CFG1_REG < 16'h0000) || (RXDFE_H4_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-421] RXDFE_H4_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H4_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H5_CFG0_REG < 16'h0000) || (RXDFE_H5_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-422] RXDFE_H5_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H5_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H5_CFG1_REG < 16'h0000) || (RXDFE_H5_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-423] RXDFE_H5_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H5_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H6_CFG0_REG < 16'h0000) || (RXDFE_H6_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-424] RXDFE_H6_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H6_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H6_CFG1_REG < 16'h0000) || (RXDFE_H6_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-425] RXDFE_H6_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H6_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H7_CFG0_REG < 16'h0000) || (RXDFE_H7_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-426] RXDFE_H7_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H7_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H7_CFG1_REG < 16'h0000) || (RXDFE_H7_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-427] RXDFE_H7_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H7_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H8_CFG0_REG < 16'h0000) || (RXDFE_H8_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-428] RXDFE_H8_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H8_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H8_CFG1_REG < 16'h0000) || (RXDFE_H8_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-429] RXDFE_H8_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H8_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H9_CFG0_REG < 16'h0000) || (RXDFE_H9_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-430] RXDFE_H9_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H9_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H9_CFG1_REG < 16'h0000) || (RXDFE_H9_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-431] RXDFE_H9_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H9_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HA_CFG0_REG < 16'h0000) || (RXDFE_HA_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-432] RXDFE_HA_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HA_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HA_CFG1_REG < 16'h0000) || (RXDFE_HA_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-433] RXDFE_HA_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HA_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HB_CFG0_REG < 16'h0000) || (RXDFE_HB_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-434] RXDFE_HB_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HB_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HB_CFG1_REG < 16'h0000) || (RXDFE_HB_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-435] RXDFE_HB_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HB_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HC_CFG0_REG < 16'h0000) || (RXDFE_HC_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-436] RXDFE_HC_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HC_CFG1_REG < 16'h0000) || (RXDFE_HC_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-437] RXDFE_HC_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HD_CFG0_REG < 16'h0000) || (RXDFE_HD_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-438] RXDFE_HD_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HD_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HD_CFG1_REG < 16'h0000) || (RXDFE_HD_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-439] RXDFE_HD_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HD_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HE_CFG0_REG < 16'h0000) || (RXDFE_HE_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-440] RXDFE_HE_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HE_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HE_CFG1_REG < 16'h0000) || (RXDFE_HE_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-441] RXDFE_HE_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HE_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HF_CFG0_REG < 16'h0000) || (RXDFE_HF_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-442] RXDFE_HF_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HF_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HF_CFG1_REG < 16'h0000) || (RXDFE_HF_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-443] RXDFE_HF_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HF_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_OS_CFG0_REG < 16'h0000) || (RXDFE_OS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-444] RXDFE_OS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_OS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_OS_CFG1_REG < 16'h0000) || (RXDFE_OS_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-445] RXDFE_OS_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_OS_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_UT_CFG0_REG < 16'h0000) || (RXDFE_UT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-446] RXDFE_UT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_UT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_UT_CFG1_REG < 16'h0000) || (RXDFE_UT_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-447] RXDFE_UT_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_UT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_VP_CFG0_REG < 16'h0000) || (RXDFE_VP_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-448] RXDFE_VP_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_VP_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_VP_CFG1_REG < 16'h0000) || (RXDFE_VP_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-449] RXDFE_VP_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_VP_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDLY_CFG_REG < 16'h0000) || (RXDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-450] RXDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDLY_LCFG_REG < 16'h0000) || (RXDLY_LCFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-451] RXDLY_LCFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDLY_LCFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXELECIDLE_CFG_REG != "Sigcfg_4") &&
(RXELECIDLE_CFG_REG != "Sigcfg_1") &&
(RXELECIDLE_CFG_REG != "Sigcfg_2") &&
(RXELECIDLE_CFG_REG != "Sigcfg_3") &&
(RXELECIDLE_CFG_REG != "Sigcfg_6") &&
(RXELECIDLE_CFG_REG != "Sigcfg_8") &&
(RXELECIDLE_CFG_REG != "Sigcfg_12") &&
(RXELECIDLE_CFG_REG != "Sigcfg_16"))) begin
$display("Error: [Unisim %s-452] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are Sigcfg_4, Sigcfg_1, Sigcfg_2, Sigcfg_3, Sigcfg_6, Sigcfg_8, Sigcfg_12 or Sigcfg_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin
$display("Error: [Unisim %s-453] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-454] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXISCANRESET_TIME_REG < 5'b00000) || (RXISCANRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-455] RXISCANRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXISCANRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_CFG_REG < 16'h0000) || (RXLPM_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-456] RXLPM_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_GC_CFG_REG < 16'h0000) || (RXLPM_GC_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-457] RXLPM_GC_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_GC_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_KH_CFG0_REG < 16'h0000) || (RXLPM_KH_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-458] RXLPM_KH_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_KH_CFG1_REG < 16'h0000) || (RXLPM_KH_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-459] RXLPM_KH_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_OS_CFG0_REG < 16'h0000) || (RXLPM_OS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-460] RXLPM_OS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_OS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_OS_CFG1_REG < 16'h0000) || (RXLPM_OS_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-461] RXLPM_OS_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_OS_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CFG_REG < 9'b000000000) || (RXOOB_CFG_REG > 9'b111111111))) begin
$display("Error: [Unisim %s-462] RXOOB_CFG attribute is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111. Instance: %m", MODULE_NAME, RXOOB_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC"))) begin
$display("Error: [Unisim %s-463] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOSCALRESET_TIME_REG < 5'b00000) || (RXOSCALRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-464] RXOSCALRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXOSCALRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16))) begin
$display("Error: [Unisim %s-465] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, RXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPCSRESET_TIME_REG < 5'b00000) || (RXPCSRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-466] RXPCSRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHBEACON_CFG_REG < 16'h0000) || (RXPHBEACON_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-467] RXPHBEACON_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHBEACON_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHDLY_CFG_REG < 16'h0000) || (RXPHDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-468] RXPHDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHSAMP_CFG_REG < 16'h0000) || (RXPHSAMP_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-469] RXPHSAMP_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHSAMP_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHSLIP_CFG_REG < 16'h0000) || (RXPHSLIP_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-470] RXPHSLIP_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHSLIP_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPH_MONITOR_SEL_REG < 5'b00000) || (RXPH_MONITOR_SEL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-471] RXPH_MONITOR_SEL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG0_REG < 2'b00) || (RXPI_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-472] RXPI_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG1_REG < 2'b00) || (RXPI_CFG1_REG > 2'b11))) begin
$display("Error: [Unisim %s-473] RXPI_CFG1 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG2_REG < 2'b00) || (RXPI_CFG2_REG > 2'b11))) begin
$display("Error: [Unisim %s-474] RXPI_CFG2 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG3_REG < 2'b00) || (RXPI_CFG3_REG > 2'b11))) begin
$display("Error: [Unisim %s-475] RXPI_CFG3 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG4_REG !== 1'b0) && (RXPI_CFG4_REG !== 1'b1))) begin
$display("Error: [Unisim %s-476] RXPI_CFG4 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG5_REG !== 1'b0) && (RXPI_CFG5_REG !== 1'b1))) begin
$display("Error: [Unisim %s-477] RXPI_CFG5 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG6_REG < 3'b000) || (RXPI_CFG6_REG > 3'b111))) begin
$display("Error: [Unisim %s-478] RXPI_CFG6 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RXPI_CFG6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_LPM_REG !== 1'b0) && (RXPI_LPM_REG !== 1'b1))) begin
$display("Error: [Unisim %s-479] RXPI_LPM attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_LPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_VREFSEL_REG !== 1'b0) && (RXPI_VREFSEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-480] RXPI_VREFSEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN"))) begin
$display("Error: [Unisim %s-482] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMARESET_TIME_REG < 5'b00000) || (RXPMARESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-483] RXPMARESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_ERR_LOOPBACK_REG !== 1'b0) && (RXPRBS_ERR_LOOPBACK_REG !== 1'b1))) begin
$display("Error: [Unisim %s-484] RXPRBS_ERR_LOOPBACK attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPRBS_ERR_LOOPBACK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15))) begin
$display("Error: [Unisim %s-486] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA"))) begin
$display("Error: [Unisim %s-487] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_MULTILANE_REG !== 1'b0) && (RXSYNC_MULTILANE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-488] RXSYNC_MULTILANE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_OVRD_REG !== 1'b0) && (RXSYNC_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-489] RXSYNC_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_SKIP_DA_REG !== 1'b0) && (RXSYNC_SKIP_DA_REG !== 1'b1))) begin
$display("Error: [Unisim %s-490] RXSYNC_SKIP_DA attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_AFE_CM_EN_REG !== 1'b0) && (RX_AFE_CM_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-491] RX_AFE_CM_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_AFE_CM_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_BIAS_CFG0_REG < 16'h0000) || (RX_BIAS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-492] RX_BIAS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RX_BIAS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_BUFFER_CFG_REG < 6'b000000) || (RX_BUFFER_CFG_REG > 6'b111111))) begin
$display("Error: [Unisim %s-493] RX_BUFFER_CFG attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, RX_BUFFER_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CAPFF_SARC_ENB_REG !== 1'b0) && (RX_CAPFF_SARC_ENB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-494] RX_CAPFF_SARC_ENB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CAPFF_SARC_ENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLKMUX_EN_REG !== 1'b0) && (RX_CLKMUX_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-496] RX_CLKMUX_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK_SLIP_OVRD_REG < 5'b00000) || (RX_CLK_SLIP_OVRD_REG > 5'b11111))) begin
$display("Error: [Unisim %s-497] RX_CLK_SLIP_OVRD attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RX_CLK_SLIP_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_BUF_CFG_REG < 4'b0000) || (RX_CM_BUF_CFG_REG > 4'b1111))) begin
$display("Error: [Unisim %s-498] RX_CM_BUF_CFG attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_CM_BUF_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_BUF_PD_REG !== 1'b0) && (RX_CM_BUF_PD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-499] RX_CM_BUF_PD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CM_BUF_PD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_SEL_REG < 2'b00) || (RX_CM_SEL_REG > 2'b11))) begin
$display("Error: [Unisim %s-500] RX_CM_SEL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_TRIM_REG < 4'b0000) || (RX_CM_TRIM_REG > 4'b1111))) begin
$display("Error: [Unisim %s-501] RX_CM_TRIM attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CTLE3_LPF_REG < 8'b00000000) || (RX_CTLE3_LPF_REG > 8'b11111111))) begin
$display("Error: [Unisim %s-502] RX_CTLE3_LPF attribute is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111. Instance: %m", MODULE_NAME, RX_CTLE3_LPF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-503] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DDI_SEL_REG < 6'b000000) || (RX_DDI_SEL_REG > 6'b111111))) begin
$display("Error: [Unisim %s-504] RX_DDI_SEL attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, RX_DDI_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-505] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG0_REG < 4'b0000) || (RX_DFELPM_CFG0_REG > 4'b1111))) begin
$display("Error: [Unisim %s-506] RX_DFELPM_CFG0 attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG1_REG !== 1'b0) && (RX_DFELPM_CFG1_REG !== 1'b1))) begin
$display("Error: [Unisim %s-507] RX_DFELPM_CFG1 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFELPM_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_KLKH_AGC_STUP_EN_REG !== 1'b0) && (RX_DFELPM_KLKH_AGC_STUP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-508] RX_DFELPM_KLKH_AGC_STUP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFELPM_KLKH_AGC_STUP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG0_REG < 2'b00) || (RX_DFE_AGC_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-509] RX_DFE_AGC_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG1_REG < 3'b000) || (RX_DFE_AGC_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-510] RX_DFE_AGC_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KH_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-511] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KH_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-512] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KL_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-513] RX_DFE_KL_LPM_KL_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KL_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-514] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_LPM_HOLD_DURING_EIDLE_REG !== 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-515] RX_DFE_LPM_HOLD_DURING_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFE_LPM_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin
$display("Error: [Unisim %s-516] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DIVRESET_TIME_REG < 5'b00000) || (RX_DIVRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-517] RX_DIVRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EN_HI_LR_REG !== 1'b0) && (RX_EN_HI_LR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-518] RX_EN_HI_LR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EN_HI_LR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_CODE_REG < 7'b0000000) || (RX_EYESCAN_VS_CODE_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-519] RX_EYESCAN_VS_CODE attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_CODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_NEG_DIR_REG !== 1'b0) && (RX_EYESCAN_VS_NEG_DIR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-520] RX_EYESCAN_VS_NEG_DIR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_NEG_DIR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_RANGE_REG < 2'b00) || (RX_EYESCAN_VS_RANGE_REG > 2'b11))) begin
$display("Error: [Unisim %s-521] RX_EYESCAN_VS_RANGE attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_RANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_UT_SIGN_REG !== 1'b0) && (RX_EYESCAN_VS_UT_SIGN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-522] RX_EYESCAN_VS_UT_SIGN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_UT_SIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_FABINT_USRCLK_FLOP_REG !== 1'b0) && (RX_FABINT_USRCLK_FLOP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-523] RX_FABINT_USRCLK_FLOP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-524] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PMA_POWER_SAVE_REG !== 1'b0) && (RX_PMA_POWER_SAVE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-525] RX_PMA_POWER_SAVE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SAMPLE_PERIOD_REG < 3'b000) || (RX_SAMPLE_PERIOD_REG > 3'b111))) begin
$display("Error: [Unisim %s-527] RX_SAMPLE_PERIOD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_DFETAPREP_EN_REG !== 1'b0) && (RX_SUM_DFETAPREP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-529] RX_SUM_DFETAPREP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_SUM_DFETAPREP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_IREF_TUNE_REG < 4'b0000) || (RX_SUM_IREF_TUNE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-530] RX_SUM_IREF_TUNE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_SUM_IREF_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_RES_CTRL_REG < 2'b00) || (RX_SUM_RES_CTRL_REG > 2'b11))) begin
$display("Error: [Unisim %s-531] RX_SUM_RES_CTRL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_SUM_RES_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VCMTUNE_REG < 4'b0000) || (RX_SUM_VCMTUNE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-532] RX_SUM_VCMTUNE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_SUM_VCMTUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VCM_OVWR_REG !== 1'b0) && (RX_SUM_VCM_OVWR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-533] RX_SUM_VCM_OVWR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_SUM_VCM_OVWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VREF_TUNE_REG < 3'b000) || (RX_SUM_VREF_TUNE_REG > 3'b111))) begin
$display("Error: [Unisim %s-534] RX_SUM_VREF_TUNE attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_SUM_VREF_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_TUNE_AFE_OS_REG < 2'b00) || (RX_TUNE_AFE_OS_REG > 2'b11))) begin
$display("Error: [Unisim %s-535] RX_TUNE_AFE_OS attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_TUNE_AFE_OS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_WIDEMODE_CDR_REG !== 1'b0) && (RX_WIDEMODE_CDR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-536] RX_WIDEMODE_CDR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_WIDEMODE_CDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR"))) begin
$display("Error: [Unisim %s-537] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_BURST_SEQ_LEN_REG < 4'b0000) || (SATA_BURST_SEQ_LEN_REG > 4'b1111))) begin
$display("Error: [Unisim %s-540] SATA_BURST_SEQ_LEN attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, SATA_BURST_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_BURST_VAL_REG < 3'b000) || (SATA_BURST_VAL_REG > 3'b111))) begin
$display("Error: [Unisim %s-541] SATA_BURST_VAL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, SATA_BURST_VAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ"))) begin
$display("Error: [Unisim %s-542] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_EIDLE_VAL_REG < 3'b000) || (SATA_EIDLE_VAL_REG > 3'b111))) begin
$display("Error: [Unisim %s-543] SATA_EIDLE_VAL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, SATA_EIDLE_VAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE"))) begin
$display("Error: [Unisim %s-550] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-551] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE"))) begin
$display("Error: [Unisim %s-552] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_TX_EIDLE_DRIVE_LEVEL_REG !== 1'b0) && (SIM_TX_EIDLE_DRIVE_LEVEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-553] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != "Ver_1") &&
(SIM_VERSION_REG != "Ver_1_1") &&
(SIM_VERSION_REG != "Ver_2"))) begin
$display("Error: [Unisim %s-554] SIM_VERSION attribute is set to %s. Legal values for this attribute are Ver_1, Ver_1_1 or Ver_2. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TAPDLY_SET_TX_REG < 2'h0) || (TAPDLY_SET_TX_REG > 2'h3))) begin
$display("Error: [Unisim %s-555] TAPDLY_SET_TX attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, TAPDLY_SET_TX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TEMPERATUR_PAR_REG < 4'b0000) || (TEMPERATUR_PAR_REG > 4'b1111))) begin
$display("Error: [Unisim %s-556] TEMPERATUR_PAR attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TEMPERATUR_PAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TERM_RCAL_CFG_REG < 15'b000000000000000) || (TERM_RCAL_CFG_REG > 15'b111111111111111))) begin
$display("Error: [Unisim %s-557] TERM_RCAL_CFG attribute is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111. Instance: %m", MODULE_NAME, TERM_RCAL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TERM_RCAL_OVRD_REG < 3'b000) || (TERM_RCAL_OVRD_REG > 3'b111))) begin
$display("Error: [Unisim %s-558] TERM_RCAL_OVRD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TERM_RCAL_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TRANS_TIME_RATE_REG < 8'h00) || (TRANS_TIME_RATE_REG > 8'hFF))) begin
$display("Error: [Unisim %s-559] TRANS_TIME_RATE attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TRANS_TIME_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TST_RSV0_REG < 8'h00) || (TST_RSV0_REG > 8'hFF))) begin
$display("Error: [Unisim %s-560] TST_RSV0 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TST_RSV0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TST_RSV1_REG < 8'h00) || (TST_RSV1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-561] TST_RSV1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TST_RSV1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-562] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-563] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDLY_CFG_REG < 16'h0000) || (TXDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-564] TXDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDLY_LCFG_REG < 16'h0000) || (TXDLY_LCFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-565] TXDLY_LCFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXDLY_LCFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDRVBIAS_N_REG < 4'b0000) || (TXDRVBIAS_N_REG > 4'b1111))) begin
$display("Error: [Unisim %s-566] TXDRVBIAS_N attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TXDRVBIAS_N_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDRVBIAS_P_REG < 4'b0000) || (TXDRVBIAS_P_REG > 4'b1111))) begin
$display("Error: [Unisim %s-567] TXDRVBIAS_P attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TXDRVBIAS_P_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH"))) begin
$display("Error: [Unisim %s-568] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin
$display("Error: [Unisim %s-569] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-570] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16))) begin
$display("Error: [Unisim %s-572] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, TXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPCSRESET_TIME_REG < 5'b00000) || (TXPCSRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-573] TXPCSRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPHDLY_CFG0_REG < 16'h0000) || (TXPHDLY_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-574] TXPHDLY_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPHDLY_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPHDLY_CFG1_REG < 16'h0000) || (TXPHDLY_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-575] TXPHDLY_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPHDLY_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_CFG_REG < 16'h0000) || (TXPH_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-576] TXPH_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPH_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_MONITOR_SEL_REG < 5'b00000) || (TXPH_MONITOR_SEL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-577] TXPH_MONITOR_SEL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG0_REG < 2'b00) || (TXPI_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-578] TXPI_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG1_REG < 2'b00) || (TXPI_CFG1_REG > 2'b11))) begin
$display("Error: [Unisim %s-579] TXPI_CFG1 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG2_REG < 2'b00) || (TXPI_CFG2_REG > 2'b11))) begin
$display("Error: [Unisim %s-580] TXPI_CFG2 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG3_REG !== 1'b0) && (TXPI_CFG3_REG !== 1'b1))) begin
$display("Error: [Unisim %s-581] TXPI_CFG3 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG4_REG !== 1'b0) && (TXPI_CFG4_REG !== 1'b1))) begin
$display("Error: [Unisim %s-582] TXPI_CFG4 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG5_REG < 3'b000) || (TXPI_CFG5_REG > 3'b111))) begin
$display("Error: [Unisim %s-583] TXPI_CFG5 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_GRAY_SEL_REG !== 1'b0) && (TXPI_GRAY_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-584] TXPI_GRAY_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_GRAY_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_INVSTROBE_SEL_REG !== 1'b0) && (TXPI_INVSTROBE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-585] TXPI_INVSTROBE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_INVSTROBE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_LPM_REG !== 1'b0) && (TXPI_LPM_REG !== 1'b1))) begin
$display("Error: [Unisim %s-586] TXPI_LPM attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_LPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") &&
(TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin
$display("Error: [Unisim %s-587] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPM_CFG_REG < 8'b00000000) || (TXPI_PPM_CFG_REG > 8'b11111111))) begin
$display("Error: [Unisim %s-588] TXPI_PPM_CFG attribute is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111. Instance: %m", MODULE_NAME, TXPI_PPM_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_SYNFREQ_PPM_REG < 3'b000) || (TXPI_SYNFREQ_PPM_REG > 3'b111))) begin
$display("Error: [Unisim %s-589] TXPI_SYNFREQ_PPM attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TXPI_SYNFREQ_PPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_VREFSEL_REG !== 1'b0) && (TXPI_VREFSEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-590] TXPI_VREFSEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPMARESET_TIME_REG < 5'b00000) || (TXPMARESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-591] TXPMARESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_MULTILANE_REG !== 1'b0) && (TXSYNC_MULTILANE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-592] TXSYNC_MULTILANE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_OVRD_REG !== 1'b0) && (TXSYNC_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-593] TXSYNC_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_SKIP_DA_REG !== 1'b0) && (TXSYNC_SKIP_DA_REG !== 1'b1))) begin
$display("Error: [Unisim %s-594] TXSYNC_SKIP_DA attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLKMUX_EN_REG !== 1'b0) && (TX_CLKMUX_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-596] TX_CLKMUX_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-597] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DCD_CFG_REG < 6'b000000) || (TX_DCD_CFG_REG > 6'b111111))) begin
$display("Error: [Unisim %s-598] TX_DCD_CFG attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DCD_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DCD_EN_REG !== 1'b0) && (TX_DCD_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-599] TX_DCD_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_DCD_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DEEMPH0_REG < 6'b000000) || (TX_DEEMPH0_REG > 6'b111111))) begin
$display("Error: [Unisim %s-600] TX_DEEMPH0 attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DEEMPH0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DEEMPH1_REG < 6'b000000) || (TX_DEEMPH1_REG > 6'b111111))) begin
$display("Error: [Unisim %s-601] TX_DEEMPH1 attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DEEMPH1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DIVRESET_TIME_REG < 5'b00000) || (TX_DIVRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-602] TX_DIVRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin
$display("Error: [Unisim %s-603] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EIDLE_ASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_ASSERT_DELAY_REG > 3'b111))) begin
$display("Error: [Unisim %s-604] TX_EIDLE_ASSERT_DELAY attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_EIDLE_ASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EIDLE_DEASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_DEASSERT_DELAY_REG > 3'b111))) begin
$display("Error: [Unisim %s-605] TX_EIDLE_DEASSERT_DELAY attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_EIDLE_DEASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EML_PHI_TUNE_REG !== 1'b0) && (TX_EML_PHI_TUNE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-606] TX_EML_PHI_TUNE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_EML_PHI_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_FABINT_USRCLK_FLOP_REG !== 1'b0) && (TX_FABINT_USRCLK_FLOP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-607] TX_FABINT_USRCLK_FLOP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_IDLE_DATA_ZERO_REG !== 1'b0) && (TX_IDLE_DATA_ZERO_REG !== 1'b1))) begin
$display("Error: [Unisim %s-608] TX_IDLE_DATA_ZERO attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_IDLE_DATA_ZERO_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-609] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-610] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MAINCURSOR_SEL_REG !== 1'b0) && (TX_MAINCURSOR_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-611] TX_MAINCURSOR_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_MAINCURSOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_0_REG < 7'b0000000) || (TX_MARGIN_FULL_0_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-612] TX_MARGIN_FULL_0 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_1_REG < 7'b0000000) || (TX_MARGIN_FULL_1_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-613] TX_MARGIN_FULL_1 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_2_REG < 7'b0000000) || (TX_MARGIN_FULL_2_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-614] TX_MARGIN_FULL_2 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_3_REG < 7'b0000000) || (TX_MARGIN_FULL_3_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-615] TX_MARGIN_FULL_3 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_4_REG < 7'b0000000) || (TX_MARGIN_FULL_4_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-616] TX_MARGIN_FULL_4 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_0_REG < 7'b0000000) || (TX_MARGIN_LOW_0_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-617] TX_MARGIN_LOW_0 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_1_REG < 7'b0000000) || (TX_MARGIN_LOW_1_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-618] TX_MARGIN_LOW_1 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_2_REG < 7'b0000000) || (TX_MARGIN_LOW_2_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-619] TX_MARGIN_LOW_2 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_3_REG < 7'b0000000) || (TX_MARGIN_LOW_3_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-620] TX_MARGIN_LOW_3 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_4_REG < 7'b0000000) || (TX_MARGIN_LOW_4_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-621] TX_MARGIN_LOW_4 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MODE_SEL_REG < 3'b000) || (TX_MODE_SEL_REG > 3'b111))) begin
$display("Error: [Unisim %s-622] TX_MODE_SEL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_MODE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PMADATA_OPT_REG !== 1'b0) && (TX_PMADATA_OPT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-623] TX_PMADATA_OPT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PMADATA_OPT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PMA_POWER_SAVE_REG !== 1'b0) && (TX_PMA_POWER_SAVE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-624] TX_PMA_POWER_SAVE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI"))) begin
$display("Error: [Unisim %s-625] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_QPI_STATUS_EN_REG !== 1'b0) && (TX_QPI_STATUS_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-627] TX_QPI_STATUS_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_QPI_STATUS_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_CFG_REG < 14'h0000) || (TX_RXDETECT_CFG_REG > 14'h3FFF))) begin
$display("Error: [Unisim %s-628] TX_RXDETECT_CFG attribute is set to %h. Legal values for this attribute are 14'h0000 to 14'h3FFF. Instance: %m", MODULE_NAME, TX_RXDETECT_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_REF_REG < 3'b000) || (TX_RXDETECT_REF_REG > 3'b111))) begin
$display("Error: [Unisim %s-629] TX_RXDETECT_REF attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_SAMPLE_PERIOD_REG < 3'b000) || (TX_SAMPLE_PERIOD_REG > 3'b111))) begin
$display("Error: [Unisim %s-630] TX_SAMPLE_PERIOD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_SARC_LPBK_ENB_REG !== 1'b0) && (TX_SARC_LPBK_ENB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-631] TX_SARC_LPBK_ENB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_SARC_LPBK_ENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR"))) begin
$display("Error: [Unisim %s-636] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_PCS_CLK_PHASE_SEL_REG !== 1'b0) && (USE_PCS_CLK_PHASE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-637] USE_PCS_CLK_PHASE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, USE_PCS_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WB_MODE_REG < 2'b00) || (WB_MODE_REG > 2'b11))) begin
$display("Error: [Unisim %s-638] WB_MODE attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, WB_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PROGDIV_CFG_REG != 4.0) &&
(RX_PROGDIV_CFG_REG != 5.0) &&
(RX_PROGDIV_CFG_REG != 8.0) &&
(RX_PROGDIV_CFG_REG != 10.0) &&
(RX_PROGDIV_CFG_REG != 16.0) &&
(RX_PROGDIV_CFG_REG != 16.5) &&
(RX_PROGDIV_CFG_REG != 20.0) &&
(RX_PROGDIV_CFG_REG != 32.0) &&
(RX_PROGDIV_CFG_REG != 33.0) &&
(RX_PROGDIV_CFG_REG != 40.0) &&
(RX_PROGDIV_CFG_REG != 64.0) &&
(RX_PROGDIV_CFG_REG != 66.0))) begin
$display("Error: [Unisim %s-526] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0 or 66.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGDIV_CFG_REG != 4.0) &&
(TX_PROGDIV_CFG_REG != 5.0) &&
(TX_PROGDIV_CFG_REG != 8.0) &&
(TX_PROGDIV_CFG_REG != 10.0) &&
(TX_PROGDIV_CFG_REG != 16.0) &&
(TX_PROGDIV_CFG_REG != 16.5) &&
(TX_PROGDIV_CFG_REG != 20.0) &&
(TX_PROGDIV_CFG_REG != 32.0) &&
(TX_PROGDIV_CFG_REG != 33.0) &&
(TX_PROGDIV_CFG_REG != 40.0) &&
(TX_PROGDIV_CFG_REG != 64.0) &&
(TX_PROGDIV_CFG_REG != 66.0))) begin
$display("Error: [Unisim %s-626] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0 or 66.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 12'b111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTHE3_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG),
.SIM_VERSION (SIM_VERSION_REG)
) SIP_GTHE3_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_EYESCAN (AEN_EYESCAN_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_QPI (AEN_QPI_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.A_AFECFOKEN (A_AFECFOKEN_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG),
.A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG),
.A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG),
.A_DFECFOKHOLD (A_DFECFOKHOLD_REG),
.A_DFECFOKOVREN (A_DFECFOKOVREN_REG),
.A_EYESCANMODE (A_EYESCANMODE_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_LPMGCHOLD (A_LPMGCHOLD_REG),
.A_LPMGCOVREN (A_LPMGCOVREN_REG),
.A_LPMOSHOLD (A_LPMOSHOLD_REG),
.A_LPMOSOVREN (A_LPMOSOVREN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXDFEAGCCTRL (A_RXDFEAGCCTRL_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEVSEN (A_RXDFEVSEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPHOVRDEN (A_RXPHOVRDEN_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPOSTCURSORINV (A_TXPOSTCURSORINV_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPRECURSORINV (A_TXPRECURSORINV_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXQPIBIASEN (A_TXQPIBIASEN_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG),
.DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PMA_CFG (ES_PMA_CFG_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.EVODD_PHI_CFG (EVODD_PHI_CFG_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GM_BIAS_SELECT (GM_BIAS_SELECT_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PCS_RSVD1 (PCS_RSVD1_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG),
.PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG),
.PMA_RSV1 (PMA_RSV1_REG),
.PROCESS_PAR (PROCESS_PAR_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_CFG0 (RXPI_CFG0_REG),
.RXPI_CFG1 (RXPI_CFG1_REG),
.RXPI_CFG2 (RXPI_CFG2_REG),
.RXPI_CFG3 (RXPI_CFG3_REG),
.RXPI_CFG4 (RXPI_CFG4_REG),
.RXPI_CFG5 (RXPI_CFG5_REG),
.RXPI_CFG6 (RXPI_CFG6_REG),
.RXPI_LPM (RXPI_LPM_REG),
.RXPI_VREFSEL (RXPI_VREFSEL_REG),
.RXPLL_SEL (RXPLL_SEL_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE3_LPF (RX_CTLE3_LPF_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_HI_LR (RX_EN_HI_LR_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_RES_CTRL (RX_SUM_RES_CTRL_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.SAS_MAX_COM (SAS_MAX_COM_REG),
.SAS_MIN_COM (SAS_MIN_COM_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SATA_MAX_BURST (SATA_MAX_BURST_REG),
.SATA_MAX_INIT (SATA_MAX_INIT_REG),
.SATA_MAX_WAKE (SATA_MAX_WAKE_REG),
.SATA_MIN_BURST (SATA_MIN_BURST_REG),
.SATA_MIN_INIT (SATA_MIN_INIT_REG),
.SATA_MIN_WAKE (SATA_MIN_WAKE_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TEMPERATUR_PAR (TEMPERATUR_PAR_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXDRVBIAS_N (TXDRVBIAS_N_REG),
.TXDRVBIAS_P (TXDRVBIAS_P_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_CFG2 (TXPI_CFG2_REG),
.TXPI_CFG3 (TXPI_CFG3_REG),
.TXPI_CFG4 (TXPI_CFG4_REG),
.TXPI_CFG5 (TXPI_CFG5_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_LPM (TXPI_LPM_REG),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPI_VREFSEL (TXPI_VREFSEL_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCD_CFG (TX_DCD_CFG_REG),
.TX_DCD_EN (TX_DCD_EN_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_MODE_SEL (TX_MODE_SEL_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.WB_MODE (WB_MODE_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.DMONITOROUT (DMONITOROUT_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTHTXN (GTHTXN_out),
.GTHTXP (GTHTXP_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXQPISENN (RXQPISENN_out),
.RXQPISENP (RXQPISENP_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXQPISENN (TXQPISENN_out),
.TXQPISENP (TXQPISENP_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.EVODDPHICALDONE (EVODDPHICALDONE_in),
.EVODDPHICALSTART (EVODDPHICALSTART_in),
.EVODDPHIDRDEN (EVODDPHIDRDEN_in),
.EVODDPHIDWREN (EVODDPHIDWREN_in),
.EVODDPHIXRDEN (EVODDPHIXRDEN_in),
.EVODDPHIXWREN (EVODDPHIXWREN_in),
.EYESCANMODE (EYESCANMODE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.GTGREFCLK (GTGREFCLK_in),
.GTHRXN (GTHRXN_in),
.GTHRXP (GTHRXP_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRESETSEL (GTRESETSEL_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.LOOPBACK (LOOPBACK_in),
.LPBKRXTXSEREN (LPBKRXTXSEREN_in),
.LPBKTXRXSEREN (LPBKTXRXSEREN_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PCSRSVDIN2 (PCSRSVDIN2_in),
.PMARSVDIN (PMARSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RSTCLKENTX (RSTCLKENTX_in),
.RX8B10BEN (RX8B10BEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCDRRESETRSV (RXCDRRESETRSV_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDFEAGCCTRL (RXDFEAGCCTRL_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEVSEN (RXDFEVSEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSINTCFG (RXOSINTCFG_in),
.RXOSINTEN (RXOSINTEN_in),
.RXOSINTHOLD (RXOSINTHOLD_in),
.RXOSINTOVRDEN (RXOSINTOVRDEN_in),
.RXOSINTSTROBE (RXOSINTSTROBE_in),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPHOVRDEN (RXPHOVRDEN_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXQPIEN (RXQPIEN_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDIFFPD (TXDIFFPD_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPOSTCURSORINV (TXPOSTCURSORINV_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPRECURSORINV (TXPRECURSORINV_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXQPIBIASEN (TXQPIBIASEN_in),
.TXQPISTRONGPDOWN (TXQPISTRONGPDOWN_in),
.TXQPIWEAKPUP (TXQPIWEAKPUP_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
specify
(DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[0]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[10]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[11]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[12]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[13]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[14]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[15]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[1]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[2]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[3]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[4]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[5]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[6]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[7]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[8]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPRDY) = (0:0:0, 0:0:0);
(GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[0]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[1]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[2]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[3]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => PHYSTATUS) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANBONDSEQ) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCLKCORCNT[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCLKCORCNT[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMINITDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMMADET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMSASDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMWAKEDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATAVALID[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATAVALID[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[10]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[11]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[12]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[13]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[14]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[15]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[16]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[17]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[18]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[19]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[20]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[21]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[22]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[23]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[24]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[25]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[26]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[27]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[28]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[29]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[30]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[31]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[32]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[33]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[34]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[35]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[36]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[37]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[38]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[39]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[40]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[41]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[42]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[43]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[44]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[45]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[46]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[47]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[48]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[49]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[50]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[51]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[52]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[53]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[54]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[55]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[56]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[57]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[58]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[59]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[60]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[61]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[62]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[63]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[8]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[9]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADERVALID[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADERVALID[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSERR) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSLOCKED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRATEDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIDERDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPOUTCLKRDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPPMARDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTARTOFSEQ[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTARTOFSEQ[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXVALID) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXBUFSTATUS[0]) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXBUFSTATUS[1]) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXCOMFINISH) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRATEDONE) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRESETDONE) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 16: 0] counter_load_value;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 16: 0] internal_counter;
wire irq;
wire period_h_wr_strobe;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 17'h1869F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = 17'h1869F;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
module FSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
output Out10_o,
output Out11_o,
output Out12_o,
output Out13_o,
output Out14_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [7:0] Input_s;
wire [14:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(8),
.OutputWidth(15),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign Out10_o = Output_s[10];
assign Out11_o = Output_s[11];
assign Out12_o = Output_s[12];
assign Out13_o = Output_s[13];
assign Out14_o = Output_s[14];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : trn_rx_128.v
// Version : 1.7
`timescale 1ps/1ps
`define FIFO_LIMIT 4
module trn_rx_128 #(
parameter TCQ = 100
)(
input user_clk,
input block_clk,
input rst_n_250,
input rst_n_500,
output [6:0] trn_rbar_hit_n_o,
output[127:0] trn_rd_o,
output trn_recrc_err_n_o,
output trn_rsof_n_o,
output trn_reof_n_o,
output trn_rerrfwd_n_o,
output [1:0] trn_rrem_n_o,
output trn_rsrc_dsc_n_o,
output trn_rsrc_rdy_n_o,
input trn_rdst_rdy_n_i,
input trn_rnpok_n_i,
input [6:0] TRNRBARHITN_i,
input [63:0] TRNRD_i,
input TRNRECRCERRN_i,
input TRNRSOFN_i,
input TRNREOFN_i,
input TRNRERRFWDN_i,
input TRNRREMN_i,
input TRNRSRCDSCN_i,
input TRNRSRCRDYN_i,
output TRNRDSTRDYN_o,
output TRNRNPOKN_o
);
wire [(128+7+7)-1:0] srl_in;
wire [(128+7+7)-1:0] srl_out;
reg [6:0] trn_rbar_hit_n_o_reg;
reg trn_recrc_err_n_o_reg;
reg trn_rerrfwd_n_o_reg;
reg [63:0] trn_rd_o_reg;
reg trn_rsof_n_o_reg;
reg trn_reof_n_o_reg;
reg trn_rrem_n_o_reg;
//(* XIL_PAR_PATH = "*pcie_2_0_i.TRNRSRCRDYN.SR->D", XIL_PAR_IP_NAME = "PCIE", syn_keep = "1", keep = "TRUE" *)
reg trn_rsrc_rdy_n_o_reg;
reg trn_rsrc_dsc_n_o_reg;
reg [6:0] trn_rbar_hit_n_o_reg_d;
reg trn_recrc_err_n_o_reg_d;
reg trn_rerrfwd_n_o_reg_d;
reg [63:0] trn_rd_o_reg_d;
reg trn_rsof_n_o_reg_d;
reg trn_reof_n_o_reg_d;
reg trn_rrem_n_o_reg_d;
reg trn_rsrc_rdy_n_o_reg_d;
reg trn_rsrc_dsc_n_o_reg_d;
wire [6:0] trn_rbar_hit_n_o_spry;
wire trn_recrc_err_n_o_spry;
wire trn_rerrfwd_n_o_spry;
wire [127:0] trn_rd_o_spry;
wire trn_rsof_n_o_spry;
wire trn_reof_n_o_spry;
wire [1:0] trn_rrem_n_o_spry;
wire trn_rsrc_rdy_n_o_spry;
wire trn_rsrc_dsc_n_o_spry;
wire empty;
reg empty_plus_rdst_rdy_n_250;
wire [3:0] data_count;
reg data_count_under_limit_n_500;
reg data_count_under_limit_n_500_d;
reg data_count_under_limit_n_250;
reg data_count_under_limit_n_250_d;
reg data_count_under_limit_n_250_d2;
//(* XIL_PAR_PATH = "*trn_rx_128_i.trn_rsrc_rdy_n_o_reg.Q->D", XIL_PAR_IP_NAME = "PCIE", syn_keep = "1", keep = "TRUE" *)
reg write_en;
reg trn_rsof_n_o_reg_250;
reg trn_rsof_n_o_reg_d_250;
reg trn_reof_n_o_reg_250;
reg trn_reof_n_o_reg_d_250;
reg trn_rsrc_rdy_n_o_reg_250;
reg trn_rsrc_rdy_n_o_reg_d_250;
reg trn_rsrc_dsc_n_o_reg_250;
reg trn_rsrc_dsc_n_o_reg_d_250;
reg trn_recrc_err_n_o_reg_250;
reg trn_recrc_err_n_o_reg_d_250;
reg trn_rerrfwd_n_o_reg_250;
reg trn_rerrfwd_n_o_reg_d_250;
reg [63:0] trn_rd_o_reg_250;
reg [63:0] trn_rd_o_reg_d_250;
reg [6:0] trn_rbar_hit_n_o_reg_250;
reg [6:0] trn_rbar_hit_n_o_reg_d_250;
reg trn_rrem_n_o_reg_250;
reg trn_rrem_n_o_reg_d_250;
reg pkt_ended;
reg in_a_pkt;
reg trn_rnp_ok_n_250;
reg TRNRNPOKN_500;
reg NP_b_detect;
reg [2:0] u_cnt = 0;
reg [2:0] b_cnt = 0;
// -------------------------------------------------------------------------
// 500Mhz
// -------------------------------------------------------------------------
always @(posedge block_clk)
begin
if (~rst_n_500)
begin
data_count_under_limit_n_500 <= #TCQ 1'b1;
data_count_under_limit_n_500_d <= #TCQ 1'b1;
end else begin
data_count_under_limit_n_500 <= #TCQ ~(data_count < `FIFO_LIMIT);
data_count_under_limit_n_500_d <= #TCQ data_count_under_limit_n_500;
end
end
// Block directly to flops
always @(posedge block_clk)
begin
if (~rst_n_500)
begin
trn_rbar_hit_n_o_reg <= #TCQ 7'h7f; // 7
trn_recrc_err_n_o_reg <= #TCQ 1'b1;
trn_rerrfwd_n_o_reg <= #TCQ 1'b1;
trn_rd_o_reg <= #TCQ 64'd0; // 64
trn_rsof_n_o_reg <= #TCQ 1'b1;
trn_reof_n_o_reg <= #TCQ 1'b1;
trn_rrem_n_o_reg <= #TCQ 1'b1;
trn_rsrc_rdy_n_o_reg <= #TCQ 1'b1;
trn_rsrc_dsc_n_o_reg <= #TCQ 1'b1;
trn_rbar_hit_n_o_reg_d <= #TCQ 7'h7f; // 7
trn_recrc_err_n_o_reg_d <= #TCQ 1'b1;
trn_rerrfwd_n_o_reg_d <= #TCQ 1'b1;
trn_rd_o_reg_d <= #TCQ 64'd0; // 64
trn_rsof_n_o_reg_d <= #TCQ 1'b1;
trn_reof_n_o_reg_d <= #TCQ 1'b1;
trn_rrem_n_o_reg_d <= #TCQ 1'b1;
trn_rsrc_rdy_n_o_reg_d <= #TCQ 1'b1;
trn_rsrc_dsc_n_o_reg_d <= #TCQ 1'b1;
in_a_pkt <= #TCQ 1'b0;
end else begin
trn_rbar_hit_n_o_reg <= #TCQ TRNRBARHITN_i; // 7
trn_recrc_err_n_o_reg <= #TCQ TRNRECRCERRN_i;
trn_rerrfwd_n_o_reg <= #TCQ TRNRERRFWDN_i;
trn_rd_o_reg <= #TCQ TRNRD_i; // 64
trn_rsof_n_o_reg <= #TCQ TRNRSOFN_i;
trn_reof_n_o_reg <= #TCQ TRNREOFN_i;
trn_rrem_n_o_reg <= #TCQ TRNRREMN_i;
trn_rsrc_rdy_n_o_reg <= #TCQ (TRNRSRCRDYN_i |
data_count_under_limit_n_500_d);
trn_rsrc_dsc_n_o_reg <= #TCQ TRNRSRCDSCN_i;
trn_rbar_hit_n_o_reg_d <= #TCQ trn_rbar_hit_n_o_reg; // 7
trn_recrc_err_n_o_reg_d <= #TCQ trn_recrc_err_n_o_reg;
trn_rerrfwd_n_o_reg_d <= #TCQ trn_rerrfwd_n_o_reg;
trn_rd_o_reg_d <= #TCQ trn_rd_o_reg; // 64
trn_rsof_n_o_reg_d <= #TCQ trn_rsof_n_o_reg;
trn_reof_n_o_reg_d <= #TCQ trn_reof_n_o_reg;
trn_rrem_n_o_reg_d <= #TCQ trn_rrem_n_o_reg;
trn_rsrc_rdy_n_o_reg_d <= #TCQ trn_rsrc_rdy_n_o_reg;
trn_rsrc_dsc_n_o_reg_d <= #TCQ trn_rsrc_dsc_n_o_reg;
if (~trn_reof_n_o_reg & ~trn_rsrc_rdy_n_o_reg)
in_a_pkt <= #TCQ 1'b0;
else if (~trn_rsof_n_o_reg & ~trn_rsrc_rdy_n_o_reg)
in_a_pkt <= #TCQ 1'b1;
end
end
// -------------------------------------------------------------------------
// 250Mhz
// -------------------------------------------------------------------------
assign #TCQ srl_in = {
trn_rsof_n_o_spry,
trn_reof_n_o_spry,
trn_rd_o_spry, // 128
trn_rbar_hit_n_o_spry, // 7
trn_recrc_err_n_o_spry,
trn_rerrfwd_n_o_spry,
trn_rrem_n_o_spry, // 2
trn_rsrc_dsc_n_o_spry
};
//assign #TCQ trn_rsof_n_o_spry =
// ~(~trn_rsof_n_o_reg_250 | ~trn_rsof_n_o_reg_d_250);
// 3462
// to allow creation of <!eof sof> generation when throttled at end of pkt
assign #TCQ trn_rsof_n_o_spry = (trn_rsof_n_o_reg_d_250 &
data_count_under_limit_n_250_d) ? 1 :
~(~trn_rsof_n_o_reg_250 | ~trn_rsof_n_o_reg_d_250);
assign #TCQ trn_reof_n_o_spry =
~(~trn_reof_n_o_reg_250 | ~trn_reof_n_o_reg_d_250);
assign #TCQ trn_rd_o_spry =
{trn_rd_o_reg_d_250, trn_rd_o_reg_250};
assign #TCQ trn_rbar_hit_n_o_spry =
(trn_rsof_n_o_reg_250 ^ trn_reof_n_o_reg_d_250) ?
~(~trn_rbar_hit_n_o_reg_250 | ~trn_rbar_hit_n_o_reg_d_250) :
trn_rbar_hit_n_o_reg_250;
assign #TCQ trn_recrc_err_n_o_spry =
~(~trn_recrc_err_n_o_reg_250 | ~trn_recrc_err_n_o_reg_d_250);
assign #TCQ trn_rerrfwd_n_o_spry =
~(~trn_rerrfwd_n_o_reg_250 | ~trn_rerrfwd_n_o_reg_d_250);
assign #TCQ trn_rrem_n_o_spry[1] =
(~trn_reof_n_o_reg_d_250 | ~trn_rsof_n_o_reg_250);
assign #TCQ trn_rrem_n_o_spry[0] =
((trn_reof_n_o_reg_d_250 ? 1'b0 : trn_rrem_n_o_reg_d_250) |
(trn_reof_n_o_reg_250 ? 1'b0 : trn_rrem_n_o_reg_250)) ;
assign #TCQ trn_rsrc_rdy_n_o_spry =
~(~trn_rsrc_rdy_n_o_reg_250 | ~trn_rsrc_rdy_n_o_reg_d_250);
assign #TCQ trn_rsrc_dsc_n_o_spry =
~(~trn_rsrc_dsc_n_o_reg_250 | ~trn_rsrc_dsc_n_o_reg_d_250);
sync_fifo #(
.WIDTH(128+7+7),
.DEPTH(8),
// .STYLE("SRL")
.STYLE("REG")
) sync_fifo_128 (
.clk ( user_clk ),
.rst_n ( rst_n_250 ),
.din ( srl_in ),
.dout ( srl_out ),
.wr_en ( write_en ),
.rd_en ( ~trn_rdst_rdy_n_i ),
.data_count( data_count ),
.empty ( empty ),
.afull ( ),
.aempty ( ),
.full ( )
);
always @(posedge user_clk)
begin
if (~rst_n_250)
begin
data_count_under_limit_n_250 <= #TCQ 1'b1;
empty_plus_rdst_rdy_n_250 <= #TCQ 1'b1;
data_count_under_limit_n_250_d <= #TCQ 1'b1;
data_count_under_limit_n_250_d2 <= #TCQ 1'b1;
write_en <= #TCQ 1'b0;
trn_rsof_n_o_reg_250 <= #TCQ 1'b1;
trn_rsof_n_o_reg_d_250 <= #TCQ 1'b1;
trn_reof_n_o_reg_250 <= #TCQ 1'b1;
trn_reof_n_o_reg_d_250 <= #TCQ 1'b1;
trn_rsrc_rdy_n_o_reg_250 <= #TCQ 1'b1;
trn_rsrc_rdy_n_o_reg_d_250 <= #TCQ 1'b1;
trn_rsrc_dsc_n_o_reg_250 <= #TCQ 1'b1;
trn_rsrc_dsc_n_o_reg_d_250 <= #TCQ 1'b1;
trn_recrc_err_n_o_reg_250 <= #TCQ 1'b1;
trn_recrc_err_n_o_reg_d_250 <= #TCQ 1'b1;
trn_rerrfwd_n_o_reg_250 <= #TCQ 1'b1;
trn_rerrfwd_n_o_reg_d_250 <= #TCQ 1'b1;
trn_rd_o_reg_d_250 <= #TCQ 64'd0;
trn_rd_o_reg_250 <= #TCQ 64'd0;
trn_rbar_hit_n_o_reg_250 <= #TCQ 7'h7f;
trn_rbar_hit_n_o_reg_d_250 <= #TCQ 7'h7f;
trn_rrem_n_o_reg_250 <= #TCQ 1'b1;
trn_rrem_n_o_reg_d_250 <= #TCQ 1'b1;
pkt_ended <= #TCQ 1'b0;
end else begin
data_count_under_limit_n_250 <= #TCQ ~(data_count < `FIFO_LIMIT);
if (~trn_rdst_rdy_n_i)
empty_plus_rdst_rdy_n_250 <= #TCQ empty;
data_count_under_limit_n_250_d <= #TCQ data_count_under_limit_n_250;
data_count_under_limit_n_250_d2 <= #TCQ data_count_under_limit_n_250_d;
// when to reduce write_en by one after a rdst_rdy throttle
if (write_en)
begin
// eof --
if ((trn_rsof_n_o_spry & ~trn_reof_n_o_spry & trn_rrem_n_o_spry[1]) |
// xx eof
( ~trn_reof_n_o_spry & ~trn_rrem_n_o_spry[1]))
pkt_ended <= #TCQ 1'b1;
else
pkt_ended <= #TCQ 1'b0;
end
write_en <= #TCQ (~trn_rsrc_rdy_n_o_reg_d |
(~trn_rsrc_rdy_n_o_reg & ~in_a_pkt));
trn_rsof_n_o_reg_250 <= #TCQ trn_rsof_n_o_reg;
trn_rsof_n_o_reg_d_250 <= #TCQ trn_rsof_n_o_reg_d;
trn_reof_n_o_reg_250 <= #TCQ trn_reof_n_o_reg;
trn_reof_n_o_reg_d_250 <= #TCQ trn_reof_n_o_reg_d;
trn_rsrc_rdy_n_o_reg_250 <= #TCQ trn_rsrc_rdy_n_o_reg;
trn_rsrc_rdy_n_o_reg_d_250 <= #TCQ trn_rsrc_rdy_n_o_reg_d;
trn_rsrc_dsc_n_o_reg_250 <= #TCQ trn_rsrc_dsc_n_o_reg;
trn_rsrc_dsc_n_o_reg_d_250 <= #TCQ trn_rsrc_dsc_n_o_reg_d;
trn_recrc_err_n_o_reg_250 <= #TCQ trn_recrc_err_n_o_reg;
trn_recrc_err_n_o_reg_d_250 <= #TCQ trn_recrc_err_n_o_reg_d;
trn_rerrfwd_n_o_reg_250 <= #TCQ trn_rerrfwd_n_o_reg;
trn_rerrfwd_n_o_reg_d_250 <= #TCQ trn_rerrfwd_n_o_reg_d;
trn_rd_o_reg_250 <= #TCQ trn_rd_o_reg;
trn_rd_o_reg_d_250 <= #TCQ trn_rd_o_reg_d;
trn_rbar_hit_n_o_reg_250 <= #TCQ trn_rbar_hit_n_o_reg;
trn_rbar_hit_n_o_reg_d_250 <= #TCQ trn_rbar_hit_n_o_reg_d;
trn_rrem_n_o_reg_250 <= #TCQ trn_rrem_n_o_reg;
trn_rrem_n_o_reg_d_250 <= #TCQ trn_rrem_n_o_reg_d;
end
end
assign #TCQ trn_rsof_n_o = srl_out[141];
assign #TCQ trn_reof_n_o = srl_out[140];
assign #TCQ trn_rd_o = srl_out[139:12]; // 128
assign #TCQ trn_rbar_hit_n_o = srl_out[11:5]; // 7
assign #TCQ trn_recrc_err_n_o = srl_out[4];
assign #TCQ trn_rerrfwd_n_o = srl_out[3];
assign #TCQ trn_rrem_n_o = srl_out[2:1]; // 2
assign #TCQ trn_rsrc_rdy_n_o = empty_plus_rdst_rdy_n_250;
assign #TCQ trn_rsrc_dsc_n_o = srl_out[0];
assign #TCQ TRNRDSTRDYN_o = data_count_under_limit_n_500_d;
//////////////////////////////////////////////////////////////////////////
// trn_rnp_ok_n enhancement
//////////////////////////////////////////////////////////////////////////
always @(posedge user_clk)
begin
if (~rst_n_250)
begin
trn_rnp_ok_n_250 <= #TCQ 0;
end else begin
trn_rnp_ok_n_250 <= #TCQ trn_rnpok_n_i;
end
end
always @(posedge block_clk)
begin
if (~rst_n_500)
begin
TRNRNPOKN_500 <= #TCQ 0;
end else begin
if (~trn_rnp_ok_n_250 & (u_cnt == (b_cnt + NP_b_detect) ))
TRNRNPOKN_500 <= #TCQ 0;
else
TRNRNPOKN_500 <= #TCQ 1;
end
end
assign TRNRNPOKN_o = TRNRNPOKN_500 | NP_b_detect;
// counters
always @(posedge user_clk)
begin
if (~rst_n_250)
begin
u_cnt <= #TCQ 0;
end else begin
if( ( ( ((trn_rd_o[60:56] == 5'b00001) |
(trn_rd_o[60:56] == 5'b00010) |
(trn_rd_o[60:56] == 5'b00100) |
~trn_rd_o[62] & (trn_rd_o[60:56] == 5'b00000)) & trn_rrem_n_o[1]) |
( ((trn_rd_o[124:120] == 5'b00001) |
(trn_rd_o[124:120] == 5'b00010) |
(trn_rd_o[124:120] == 5'b00100) |
~trn_rd_o[126] & (trn_rd_o[124:120] == 5'b00000)) & ~trn_rrem_n_o[1])) &
~trn_rsof_n_o & ~trn_rsrc_rdy_n_o & ~trn_rdst_rdy_n_i )
begin
u_cnt <= #TCQ u_cnt + 1;
end
end
end
always @(posedge block_clk)
begin
if (~rst_n_500)
begin
NP_b_detect <= #TCQ 0;
end else begin
if ( ( (TRNRD_i[60:56] == 5'b00001) |
(TRNRD_i[60:56] == 5'b00010) |
(TRNRD_i[60:56] == 5'b00100) |
(~TRNRD_i[62] & (TRNRD_i[60:56] == 5'b00000)) ) &
~TRNRSOFN_i & ~TRNRSRCRDYN_i & ~TRNRDSTRDYN_o )
begin
NP_b_detect <= #TCQ 1;
end else
NP_b_detect <= #TCQ 0;
end
end
always @(posedge block_clk)
begin
if (~rst_n_500)
begin
b_cnt <= #TCQ 0;
end else begin
b_cnt <= #TCQ b_cnt + NP_b_detect;
end
end
endmodule
|
`timescale 1 ns / 1 ps
module axis_lfsr #
(
parameter integer AXIS_TDATA_WIDTH = 64,
parameter HAS_TREADY = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_lfsr_reg, int_lfsr_next;
reg int_enbl_reg, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_lfsr_reg <= 64'h5555555555555555;
int_enbl_reg <= 1'b0;
end
else
begin
int_lfsr_reg <= int_lfsr_next;
int_enbl_reg <= int_enbl_next;
end
end
generate
if(HAS_TREADY == "TRUE")
begin : HAS_TREADY
always @*
begin
int_lfsr_next = int_lfsr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg & m_axis_tready)
begin
int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
end
end
end
else
begin : NO_TREADY
always @*
begin
int_lfsr_next = int_lfsr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg)
begin
int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
end
end
end
endgenerate
assign m_axis_tdata = int_lfsr_reg;
assign m_axis_tvalid = int_enbl_reg;
endmodule |
`include "../network_params.h"
module hex_out_final(
input clock,
input reset,
input [(`FFN_OUT_WIDTH*`NUM_CLASSES)-1:0] data,
output reg [6:0] hex
);
wire signed [`FFN_OUT_BITWIDTH:0] a0;
wire signed [`FFN_OUT_BITWIDTH:0] a1;
wire signed [`FFN_OUT_BITWIDTH:0] a2;
wire signed [`FFN_OUT_BITWIDTH:0] a3;
wire signed [`FFN_OUT_BITWIDTH:0] a4;
wire signed [`FFN_OUT_BITWIDTH:0] a5;
wire signed [`FFN_OUT_BITWIDTH:0] a6;
wire signed [`FFN_OUT_BITWIDTH:0] a7;
wire signed [`FFN_OUT_BITWIDTH:0] a8;
wire signed [`FFN_OUT_BITWIDTH:0] a9;
assign a0 = data[(`FFN_OUT_WIDTH*0)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*0];
assign a1 = data[(`FFN_OUT_WIDTH*1)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*1];
assign a2 = data[(`FFN_OUT_WIDTH*2)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*2];
assign a3 = data[(`FFN_OUT_WIDTH*3)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*3];
assign a4 = data[(`FFN_OUT_WIDTH*4)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*4];
assign a5 = data[(`FFN_OUT_WIDTH*5)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*5];
assign a6 = data[(`FFN_OUT_WIDTH*6)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*6];
assign a7 = data[(`FFN_OUT_WIDTH*7)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*7];
assign a8 = data[(`FFN_OUT_WIDTH*8)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*8];
assign a9 = data[(`FFN_OUT_WIDTH*9)+`FFN_OUT_BITWIDTH:`FFN_OUT_WIDTH*9];
always@(posedge clock or negedge reset)begin
if (reset == 1'b0) begin
hex <= 7'b1110111;
end else begin
if (a0>a1) begin // 0 > 1
if (a0>a2) begin // 0 > 2
if (a0>a3) begin // 0 > 3
if (a0>a4) begin // 0 > 4
if (a0>a5) begin // 0 > 5
if (a0>a6) begin // 0 > 6
if (a0>a7) begin // 0 > 7
if (a0>a8) begin // 0 > 8
if (a0>a9) begin // 0 > 9
hex <= 7'b1000000;/*0*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a1>a0) begin // 1 > 0
if (a1>a2) begin // 1 > 2
if (a1>a3) begin // 1 > 3
if (a1>a4) begin // 1 > 4
if (a1>a5) begin // 1 > 5
if (a1>a6) begin // 1 > 6
if (a1>a7) begin // 1 > 7
if (a1>a8) begin // 1 > 8
if (a1>a9) begin // 1 > 9
hex <= 7'b1111001;/*1*/
end // 1 > 9
end// 1 > 8
end// 1 > 7
end // 1 > 6
end // 1 > 5
end // 1 > 4
end // 1 > 3
end // 1 > 2
end // 1 > 0
if (a2>a1) begin // 2 > 1
if (a2>a0) begin // 2 > 0
if (a2>a3) begin // 2 > 3
if (a2>a4) begin // 2 > 4
if (a2>a5) begin // 2 > 5
if (a2>a6) begin // 2 > 6
if (a2>a7) begin // 2 > 7
if (a2>a8) begin // 2 > 8
if (a2>a9) begin // 2 > 9
hex <= 7'b0100100;/*2*/
end // 2 > 9
end// 2 > 8
end// 2 > 7
end // 2 > 6
end // 2 > 5
end // 2 > 4
end // 2 > 3
end // 2 > 0
end // 2 > 1
if (a3>a1) begin // 3 > 1
if (a3>a2) begin // 3 > 2
if (a3>a0) begin // 3 > 0
if (a3>a4) begin // 3 > 4
if (a3>a5) begin // 3 > 5
if (a3>a6) begin // 3 > 6
if (a3>a7) begin // 3 > 7
if (a3>a8) begin // 3 > 8
if (a3>a9) begin // 3 > 9
hex <= 7'b0110000;/*3*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a4>a1) begin // 4 > 1
if (a4>a2) begin // 4 > 2
if (a4>a3) begin // 4 > 3
if (a4>a0) begin // 4 > 0
if (a4>a5) begin // 4 > 5
if (a4>a6) begin // 4 > 6
if (a4>a7) begin // 4 > 7
if (a4>a8) begin // 4 > 8
if (a4>a9) begin // 4 > 9
hex <= 7'b0011001;/*4*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a5>a1) begin // 5 > 1
if (a5>a2) begin // 5 > 2
if (a5>a3) begin // 5 > 3
if (a5>a4) begin // 5 > 4
if (a5>a0) begin // 5 >0
if (a5>a6) begin // 5 > 6
if (a5>a7) begin // 5 > 7
if (a5>a8) begin // 5 > 8
if (a5>a9) begin // 5 > 9
hex <= 7'b0010010;/*5*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a6>a1) begin // 0 > 1
if (a6>a2) begin // 0 > 2
if (a6>a3) begin // 0 > 3
if (a6>a4) begin // 0 > 4
if (a6>a5) begin // 0 > 5
if (a6>a0) begin // 0 > 6
if (a6>a7) begin // 0 > 7
if (a6>a8) begin // 0 > 8
if (a6>a9) begin // 0 > 9
hex <= 7'b0000010;/*6*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a7>a1) begin // 0 > 1
if (a7>a2) begin // 0 > 2
if (a7>a3) begin // 0 > 3
if (a7>a4) begin // 0 > 4
if (a7>a5) begin // 0 > 5
if (a7>a6) begin // 0 > 6
if (a7>a0) begin // 0 > 7
if (a7>a8) begin // 0 > 8
if (a7>a9) begin // 0 > 9
hex <= 7'b1111000;/*7*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a8>a1) begin // 0 > 1
if (a8>a2) begin // 0 > 2
if (a8>a3) begin // 0 > 3
if (a8>a4) begin // 0 > 4
if (a8>a5) begin // 0 > 5
if (a8>a6) begin // 0 > 6
if (a8>a7) begin // 0 > 7
if (a8>a0) begin // 0 > 8
if (a8>a9) begin // 0 > 9
hex <= 7'b0000000;/*8*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
if (a9>a1) begin // 0 > 1
if (a9>a2) begin // 0 > 2
if (a9>a3) begin // 0 > 3
if (a9>a4) begin // 0 > 4
if (a9>a5) begin // 0 > 5
if (a9>a6) begin // 0 > 6
if (a9>a7) begin // 0 > 7
if (a9>a8) begin // 0 > 8
if (a9>a0) begin // 0 > 9
hex <= 7'b0011000;/*9*/
end // 0 > 9
end// 0 > 8
end// 0 > 7
end // 0 > 6
end // 0 > 5
end // 0 > 4
end // 0 > 3
end // 0 > 2
end // 0 > 1
end
end // else: !if(reset == 1'b0)
endmodule // rect_linear
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for shift operators (logical and arithmetic)
module shifter_test;
reg signed [7:0] inp, out_srl, out_sll, out_sra, out_sla;
shifter dut(inp, out_srl, out_sll, out_sra, out_sla);
initial begin
inp = 8'b11101100;
#1; // wait for signal assignments
if(out_srl !== 8'b01110110)
begin
$display("FAILED 1");
$finish();
end
if(out_sll !== 8'b11011000)
begin
$display("FAILED 2");
$finish();
end
if(out_sra !== 8'b11110110)
begin
$display("FAILED 3");
$finish();
end
if(out_sla !== 8'b11011000)
begin
$display("FAILED 4");
$finish();
end
$display("PASSED");
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : LPDDR2 controller address and command decoder
//
// File : alt_mem_ddrx_lpddr2_addr_cmd.v
//
// Abstract : LPDDR2 Address and command decoder
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_lpddr2_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 20,
CFG_MEM_IF_ROW_WIDTH = 15, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_output_regd,
// AFI interface (Signals from Arbiter block)
do_write,
do_read,
do_auto_precharge,
do_activate,
do_precharge,
do_precharge_all,
do_refresh,
do_self_refresh,
do_power_down,
do_lmr,
do_lmr_read, //Currently does not exist in arbiter
do_refresh_1bank, //Currently does not exist in arbiter
do_burst_terminate, //Currently does not exist in arbiter
do_deep_pwrdwn, //Currently does not exist in arbiter
// address information
to_chip, // active high input (one hot)
to_bank,
to_row,
to_col,
to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_addr,
afi_rst_n
);
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
// Arbiter command inputs
input do_write;
input do_read;
input do_auto_precharge;
input do_activate;
input do_precharge;
input [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] do_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_power_down;
input [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
input do_lmr;
input do_lmr_read;
input do_refresh_1bank;
input do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] to_col;
input [7:0] to_lmr;
input [7:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
wire do_write;
wire do_read;
wire do_auto_precharge;
wire do_activate;
wire do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
wire do_lmr;
wire do_lmr_read;
wire do_refresh_1bank;
wire do_burst_terminate;
reg [2:0] temp_bank_addr;
reg [14:0] temp_row_addr;
reg [11:0] temp_col_addr;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
generate
if (CFG_DWIDTH_RATIO == 2) begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_addr = int_addr;
end
else begin
assign afi_cke = {int_cke,int_cke};
assign afi_cs_n = (do_burst_terminate)? {int_cs_n,int_cs_n} :{int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
// need half rate code to adjust for half rate cke or cs
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode or DPD
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((do_self_refresh) || (do_deep_pwrdwn))
chip_in_self_refresh <= do_self_refresh | do_deep_pwrdwn;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
combi_cke_r <= {CFG_MEM_IF_CKE_WIDTH{1'b1}} ;
combi_cs_n_r <= {CFG_MEM_IF_CHIP{1'b1}} ;
combi_addr_r <= {CFG_MEM_IF_ADDR_WIDTH{1'b0}};
end
else
begin
combi_cke_r <= combi_cke ;
combi_cs_n_r <= combi_cs_n ;
combi_addr_r <= combi_addr ;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_addr = combi_addr;
end
end
always @ (*)
begin
temp_row_addr = {CFG_MEM_IF_ROW_WIDTH{1'b0}} ;
temp_col_addr = {CFG_MEM_IF_COL_WIDTH{1'b0}} ;
temp_bank_addr = {CFG_MEM_IF_BA_WIDTH {1'b0}} ;
temp_row_addr = to_row ;
temp_col_addr = to_col ;
temp_bank_addr = to_bank;
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(do_self_refresh | do_power_down | do_deep_pwrdwn);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
always @(*)
begin
if (ctl_cal_success)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|do_refresh)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~do_refresh;
combi_addr[3:0] = 4'b1100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_refresh_1bank)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if ((|do_precharge_all) || do_precharge)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~ (do_precharge_all|do_precharge);
combi_addr[3:0] = 4'b1011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,2'b00,(|do_precharge_all)};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_activate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = {temp_row_addr[9:8],2'b10};
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_row_addr[12:10]};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_row_addr[14:13],temp_row_addr[7:0]};
end
if (do_write)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0001;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (do_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0101;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (|do_power_down)
begin
//combi_cke = ~do_power_down;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_deep_pwrdwn)
begin
//combi_cke = ~do_deep_pwrdwn;
combi_cs_n = ~do_deep_pwrdwn; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_self_refresh)
begin
//combi_cke = ~do_self_refresh;
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_lmr)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],lmr_opcode};
end
if (do_lmr_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b1000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],{8{1'b0}}};
end
if (do_burst_terminate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
end
else
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_PP_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Rose-Hulman Institute of Technology
// Tom D'Agostino
// ECE398 CAN Controller Design
//
// Create Date: 21:29:50 04/13/2015
// Module Name: BaudGen
// Project Name: CANBUS
// Target Devices: Nexys 3 running a Xilinx Spartan6 XC6LX16-CS324
// Description: One-shot for the CRC
//////////////////////////////////////////////////////////////////////////////////
module OneShot(
input pulse,
input clk,
input rst,
output reg out
);
initial out = 0;
parameter waiting_l = 2'b00, on = 2'b01, waiting_h = 2'b10;
reg[1:0] next_state, current_state;
always @ (posedge clk or posedge rst) begin
if(rst) begin
current_state <= waiting_l;
end
else begin
current_state <= next_state;
end
end
always @ (current_state or pulse) begin
if(current_state == on) begin
next_state <= waiting_h;
end
else if(current_state == waiting_h) begin
if(pulse) begin
next_state <= waiting_h;
end
else begin
next_state <= waiting_l;
end
end
else if(pulse) begin
next_state<= on;
end
else begin
next_state<= waiting_l;
end
end
always @(current_state or rst) begin
if(rst)
out <= 1'b0;
else if(current_state == on)
out <= 1'b1;
else
out <= 1'b0;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_PP_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_PP_V |
module SNPS_CLOCK_GATE_HIGH_DLX_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2 latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
endmodule
module DLX ( CLOCK, RESET, PORT_PC, PORT_INSTR_IRAM, PORT_REGB, PORT_ALU,
PORT_DATA_RAM, PORT_SIZE, PORT_R_W, PORT_EN, RF_ENABLE, RF_RD1, RF_RD2,
RF_WR, RF_ADD_WR, RF_ADD_RD1, RF_ADD_RD2, RF_DATAIN, RF_OUT1, RF_OUT2
);
output [31:0] PORT_PC;
input [31:0] PORT_INSTR_IRAM;
output [31:0] PORT_REGB;
output [31:0] PORT_ALU;
input [31:0] PORT_DATA_RAM;
output [1:0] PORT_SIZE;
output [4:0] RF_ADD_WR;
output [4:0] RF_ADD_RD1;
output [4:0] RF_ADD_RD2;
output [31:0] RF_DATAIN;
input [31:0] RF_OUT1;
input [31:0] RF_OUT2;
input CLOCK, RESET;
output PORT_R_W, PORT_EN, RF_ENABLE, RF_RD1, RF_RD2, RF_WR;
wire \EX_ALU_B[31] , EX_ADD_SUB, ID_SIGN_EXT_CONTROL, \ID_IMM16_EXT[31] ,
WB_SIGN_EXT_16_CONTROL, ID_REGA_ZERO, IF_STALL_SEL, ID_INSTR_31,
ID_INSTR_30, ID_INSTR_29, ID_INSTR_28, ID_INSTR_27, ID_INSTR_26,
WB_INSTR_31, WB_INSTR_30, WB_INSTR_29, WB_INSTR_28, WB_INSTR_27,
WB_INSTR_26, N730, N731, N732, N733, N734, N735, N736, N737, N738,
N739, N740, N741, N742, N743, N744, N745, N746, N747, N748, N749,
N750, N751, N752, N753, N754, N755, N756, N757, N758, N759, N760,
N761, N764, N765, N766, N767, N768, N769, N770, N771, N772, N773,
N774, N775, N776, N777, N778, N779, N780, N781, N782, N783, N784,
N785, N786, N787, N788, N789, N790, N791, N792, N793, N794, N795,
N4708, N4710, N4712, N4716, N4717, N4719, N4721, N4722, N4723, N4724,
N4726, N4727, N4728, N4729, N4730, N4831, N4832, N4833, N4834, N4835,
N4836, N4837, N4839, N4840, N4841, N4842, N4843, N4844, N4845, N4846,
N4847, N4848, N4849, N4850, N4851, N4852, N4853, N4854, N4855, N4856,
N4857, N4860, N4861, N4862, N4863, N4864, N4865, N4866, N4867, N4868,
N4869, N4870, N4871, N4872, N4873, N4874, N4875, N4876, N4877, N4878,
N4879, N4880, N4881, N4882, N4883, N4884, N4885, N4886, N4887, N4888,
N4889, N4890, N4891, N6243, N6244, N6245, N6246, N6247, N6248, N6249,
N6250, N6251, N6252, N6253, N6254, N6255, N6256, N6257, N6258, N6259,
N6260, N6261, N6262, N6263, N6264, N6265, N6266, N6267, N6268, N6269,
N6270, N6271, N6272, N6273, n319, n320, n321, n688, n690, n697, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1222, n1223, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1351, n1352, n1353, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
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\ALU_instance/ADDER_OUT[6] , \ALU_instance/ADDER_OUT[7] ,
\ALU_instance/ADDER_OUT[8] , \ALU_instance/ADDER_OUT[9] ,
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\ALU_instance/ADDER_OUT[22] , \ALU_instance/ADDER_OUT[23] ,
\ALU_instance/ADDER_OUT[24] , \ALU_instance/ADDER_OUT[25] ,
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\ALU_instance/INTERNAL_B[8] , \ALU_instance/INTERNAL_B[9] ,
\ALU_instance/INTERNAL_B[10] , \ALU_instance/INTERNAL_B[11] ,
\ALU_instance/INTERNAL_B[12] , \ALU_instance/INTERNAL_B[13] ,
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\ALU_instance/INTERNAL_B[18] , \ALU_instance/INTERNAL_B[19] ,
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\BOOTH_instance/partial_products[5][18] ,
\BOOTH_instance/partial_products[5][19] ,
\BOOTH_instance/partial_products[5][20] ,
\BOOTH_instance/partial_products[5][21] ,
\BOOTH_instance/partial_products[5][22] ,
\BOOTH_instance/partial_products[5][23] ,
\BOOTH_instance/partial_products[5][24] ,
\BOOTH_instance/partial_products[5][25] ,
\BOOTH_instance/partial_products[5][26] ,
\BOOTH_instance/partial_products[5][27] ,
\BOOTH_instance/partial_products[5][28] ,
\BOOTH_instance/partial_products[5][29] ,
\BOOTH_instance/partial_products[5][30] ,
\BOOTH_instance/partial_products[5][31] ,
\BOOTH_instance/decoded[8][16] , \BOOTH_instance/decoded[8][17] ,
\BOOTH_instance/decoded[8][18] , \BOOTH_instance/decoded[8][19] ,
\BOOTH_instance/decoded[8][20] , \BOOTH_instance/decoded[8][21] ,
\BOOTH_instance/decoded[8][22] , \BOOTH_instance/decoded[8][23] ,
\BOOTH_instance/decoded[8][24] , \BOOTH_instance/decoded[8][25] ,
\BOOTH_instance/decoded[8][26] , \BOOTH_instance/decoded[8][27] ,
\BOOTH_instance/decoded[8][28] , \BOOTH_instance/decoded[8][29] ,
\BOOTH_instance/decoded[8][30] , \BOOTH_instance/decoded[8][31] ,
\BOOTH_instance/decoded[5][10] , \BOOTH_instance/decoded[5][11] ,
\BOOTH_instance/decoded[5][12] , \BOOTH_instance/decoded[5][13] ,
\BOOTH_instance/decoded[5][14] , \BOOTH_instance/decoded[5][15] ,
\BOOTH_instance/decoded[5][16] , \BOOTH_instance/decoded[5][17] ,
\BOOTH_instance/decoded[5][18] , \BOOTH_instance/decoded[5][19] ,
\BOOTH_instance/decoded[5][20] , \BOOTH_instance/decoded[5][21] ,
\BOOTH_instance/decoded[5][22] , \BOOTH_instance/decoded[5][23] ,
\BOOTH_instance/decoded[5][24] , \BOOTH_instance/decoded[5][25] ,
\BOOTH_instance/decoded[5][26] , \BOOTH_instance/decoded[5][31] ,
\BOOTH_instance/decoded[4][10] , \BOOTH_instance/decoded[4][11] ,
\BOOTH_instance/decoded[4][12] , \BOOTH_instance/decoded[4][13] ,
\BOOTH_instance/decoded[4][14] , \BOOTH_instance/decoded[4][15] ,
\BOOTH_instance/decoded[4][16] , \BOOTH_instance/decoded[4][17] ,
\BOOTH_instance/decoded[4][18] , \BOOTH_instance/decoded[4][19] ,
\BOOTH_instance/decoded[4][20] , \BOOTH_instance/decoded[4][21] ,
\BOOTH_instance/decoded[4][22] , \BOOTH_instance/decoded[4][23] ,
\BOOTH_instance/decoded[4][24] , \BOOTH_instance/decoded[4][31] ,
\BOOTH_instance/decoded[3][6] , \BOOTH_instance/decoded[3][7] ,
\BOOTH_instance/decoded[3][8] , \BOOTH_instance/decoded[3][9] ,
\BOOTH_instance/decoded[3][10] , \BOOTH_instance/decoded[3][11] ,
\BOOTH_instance/decoded[3][12] , \BOOTH_instance/decoded[3][13] ,
\BOOTH_instance/decoded[3][14] , \BOOTH_instance/decoded[3][15] ,
\BOOTH_instance/decoded[3][16] , \BOOTH_instance/decoded[3][17] ,
\BOOTH_instance/decoded[3][18] , \BOOTH_instance/decoded[3][19] ,
\BOOTH_instance/decoded[3][20] , \BOOTH_instance/decoded[3][21] ,
\BOOTH_instance/decoded[3][22] , \BOOTH_instance/decoded[3][31] ,
\BOOTH_instance/decoded[2][6] , \BOOTH_instance/decoded[2][7] ,
\BOOTH_instance/decoded[2][8] , \BOOTH_instance/decoded[2][9] ,
\BOOTH_instance/decoded[2][10] , \BOOTH_instance/decoded[2][11] ,
\BOOTH_instance/decoded[2][12] , \BOOTH_instance/decoded[2][13] ,
\BOOTH_instance/decoded[2][14] , \BOOTH_instance/decoded[2][15] ,
\BOOTH_instance/decoded[2][16] , \BOOTH_instance/decoded[2][17] ,
\BOOTH_instance/decoded[2][18] , \BOOTH_instance/decoded[2][19] ,
\BOOTH_instance/decoded[2][20] , \BOOTH_instance/decoded[2][31] ,
\BOOTH_instance/decoded[1][2] , \BOOTH_instance/decoded[1][3] ,
\BOOTH_instance/decoded[1][4] , \BOOTH_instance/decoded[1][5] ,
\BOOTH_instance/decoded[1][6] , \BOOTH_instance/decoded[1][7] ,
\BOOTH_instance/decoded[1][8] , \BOOTH_instance/decoded[1][9] ,
\BOOTH_instance/decoded[1][10] , \BOOTH_instance/decoded[1][11] ,
\BOOTH_instance/decoded[1][12] , \BOOTH_instance/decoded[1][13] ,
\BOOTH_instance/decoded[1][14] , \BOOTH_instance/decoded[1][15] ,
\BOOTH_instance/decoded[1][16] , \BOOTH_instance/decoded[1][17] ,
\BOOTH_instance/decoded[1][18] , \BOOTH_instance/decoded[1][31] ,
\BOOTH_instance/decoded[0][31] , \PC_instance/n33 ,
\WB_SIGN_EXT_16_instance/n34 , \WB_SIGN_EXT_16_instance/n33 ,
\WB_SIGN_EXT_16_instance/n28 , \WB_SIGN_EXT_16_instance/n27 ,
\WB_SIGN_EXT_16_instance/n25 , \WB_SIGN_EXT_16_instance/n24 ,
\WB_SIGN_EXT_16_instance/n23 , \WB_SIGN_EXT_16_instance/n22 ,
\zero_instance/n10 , \zero_instance/n9 , \zero_instance/n8 ,
\zero_instance/n7 , \zero_instance/n6 , \zero_instance/n5 ,
\zero_instance/n4 , \zero_instance/n3 , \zero_instance/n2 ,
\zero_instance/n1 , \ID_EX_REGB_REG_instance/n34 ,
\ID_EX_INSTR_REG_instance/n34 , \MEM_WB_ALU_REG_instance/n34 ,
\add_502/carry[4] , \add_502/carry[5] , \add_502/carry[6] ,
\add_502/carry[7] , \add_502/carry[8] , \add_502/carry[9] ,
\add_502/carry[10] , \add_502/carry[11] , \add_502/carry[12] ,
\add_502/carry[13] , \add_502/carry[14] , \add_502/carry[15] ,
\add_502/carry[16] , \add_502/carry[17] , \add_502/carry[18] ,
\add_502/carry[19] , \add_502/carry[20] , \add_502/carry[21] ,
\add_502/carry[22] , \add_502/carry[23] , \add_502/carry[24] ,
\add_502/carry[25] , \add_502/carry[26] , \add_502/carry[27] ,
\add_502/carry[28] , \add_502/carry[29] , \add_502/carry[30] ,
\add_502/carry[31] , \add_545/carry[3] , \add_545/carry[4] ,
\add_545/carry[5] , \add_545/carry[6] , \add_545/carry[7] ,
\add_545/carry[8] , \add_545/carry[9] , \add_545/carry[10] ,
\add_545/carry[11] , \add_545/carry[12] , \add_545/carry[13] ,
\add_545/carry[14] , \add_545/carry[15] , \add_545/carry[16] ,
\add_545/carry[17] , \add_545/carry[18] , \add_545/carry[19] ,
\add_545/carry[20] , \add_545/carry[21] , \add_545/carry[22] ,
\add_545/carry[23] , \add_545/carry[24] , \add_545/carry[25] ,
\add_545/carry[26] , \add_545/carry[27] , \add_545/carry[28] ,
\add_545/carry[29] , \add_545/carry[30] , \add_545/carry[31] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ,
\ALU_instance/COMPARATOR_GENERIC_I/n19 ,
\ALU_instance/COMPARATOR_GENERIC_I/n18 ,
\ALU_instance/COMPARATOR_GENERIC_I/n17 ,
\ALU_instance/COMPARATOR_GENERIC_I/n16 ,
\ALU_instance/COMPARATOR_GENERIC_I/n15 ,
\ALU_instance/COMPARATOR_GENERIC_I/n14 ,
\ALU_instance/COMPARATOR_GENERIC_I/n13 ,
\ALU_instance/COMPARATOR_GENERIC_I/n12 ,
\ALU_instance/COMPARATOR_GENERIC_I/n11 ,
\ALU_instance/COMPARATOR_GENERIC_I/n10 ,
\ALU_instance/COMPARATOR_GENERIC_I/n9 ,
\ALU_instance/COMPARATOR_GENERIC_I/n8 ,
\ALU_instance/COMPARATOR_GENERIC_I/n7 ,
\ALU_instance/COMPARATOR_GENERIC_I/n6 ,
\ALU_instance/COMPARATOR_GENERIC_I/n5 ,
\ALU_instance/COMPARATOR_GENERIC_I/n4 ,
\ALU_instance/LOGIC_GENERIC_I/n127 ,
\ALU_instance/LOGIC_GENERIC_I/n126 ,
\ALU_instance/LOGIC_GENERIC_I/n124 ,
\ALU_instance/LOGIC_GENERIC_I/n123 ,
\ALU_instance/LOGIC_GENERIC_I/n121 ,
\ALU_instance/LOGIC_GENERIC_I/n120 ,
\ALU_instance/LOGIC_GENERIC_I/n118 ,
\ALU_instance/LOGIC_GENERIC_I/n117 ,
\ALU_instance/LOGIC_GENERIC_I/n115 ,
\ALU_instance/LOGIC_GENERIC_I/n114 ,
\ALU_instance/LOGIC_GENERIC_I/n112 ,
\ALU_instance/LOGIC_GENERIC_I/n111 ,
\ALU_instance/LOGIC_GENERIC_I/n109 ,
\ALU_instance/LOGIC_GENERIC_I/n108 ,
\ALU_instance/LOGIC_GENERIC_I/n106 ,
\ALU_instance/LOGIC_GENERIC_I/n105 ,
\ALU_instance/LOGIC_GENERIC_I/n103 ,
\ALU_instance/LOGIC_GENERIC_I/n102 ,
\ALU_instance/LOGIC_GENERIC_I/n100 ,
\ALU_instance/LOGIC_GENERIC_I/n99 ,
\ALU_instance/LOGIC_GENERIC_I/n97 ,
\ALU_instance/LOGIC_GENERIC_I/n96 ,
\ALU_instance/LOGIC_GENERIC_I/n94 ,
\ALU_instance/LOGIC_GENERIC_I/n93 ,
\ALU_instance/LOGIC_GENERIC_I/n91 ,
\ALU_instance/LOGIC_GENERIC_I/n90 ,
\ALU_instance/LOGIC_GENERIC_I/n88 ,
\ALU_instance/LOGIC_GENERIC_I/n87 ,
\ALU_instance/LOGIC_GENERIC_I/n85 ,
\ALU_instance/LOGIC_GENERIC_I/n84 ,
\ALU_instance/LOGIC_GENERIC_I/n82 ,
\ALU_instance/LOGIC_GENERIC_I/n81 ,
\ALU_instance/LOGIC_GENERIC_I/n79 ,
\ALU_instance/LOGIC_GENERIC_I/n78 ,
\ALU_instance/LOGIC_GENERIC_I/n76 ,
\ALU_instance/LOGIC_GENERIC_I/n75 ,
\ALU_instance/LOGIC_GENERIC_I/n73 ,
\ALU_instance/LOGIC_GENERIC_I/n72 ,
\ALU_instance/LOGIC_GENERIC_I/n70 ,
\ALU_instance/LOGIC_GENERIC_I/n69 ,
\ALU_instance/LOGIC_GENERIC_I/n67 ,
\ALU_instance/LOGIC_GENERIC_I/n66 ,
\ALU_instance/LOGIC_GENERIC_I/n64 ,
\ALU_instance/LOGIC_GENERIC_I/n63 ,
\ALU_instance/LOGIC_GENERIC_I/n61 ,
\ALU_instance/LOGIC_GENERIC_I/n60 ,
\ALU_instance/LOGIC_GENERIC_I/n58 ,
\ALU_instance/LOGIC_GENERIC_I/n57 ,
\ALU_instance/LOGIC_GENERIC_I/n55 ,
\ALU_instance/LOGIC_GENERIC_I/n54 ,
\ALU_instance/LOGIC_GENERIC_I/n52 ,
\ALU_instance/LOGIC_GENERIC_I/n51 ,
\ALU_instance/LOGIC_GENERIC_I/n49 ,
\ALU_instance/LOGIC_GENERIC_I/n46 ,
\ALU_instance/LOGIC_GENERIC_I/n45 ,
\ALU_instance/LOGIC_GENERIC_I/n43 ,
\ALU_instance/LOGIC_GENERIC_I/n42 ,
\ALU_instance/LOGIC_GENERIC_I/n40 ,
\ALU_instance/LOGIC_GENERIC_I/n39 ,
\ALU_instance/LOGIC_GENERIC_I/n37 ,
\ALU_instance/LOGIC_GENERIC_I/n36 ,
\ALU_instance/LOGIC_GENERIC_I/n34 ,
\ALU_instance/LOGIC_GENERIC_I/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/n89 ,
\ALU_instance/SHIFTER_GENERIC_I/n88 ,
\ALU_instance/SHIFTER_GENERIC_I/n86 ,
\ALU_instance/SHIFTER_GENERIC_I/n85 ,
\ALU_instance/SHIFTER_GENERIC_I/n84 ,
\ALU_instance/SHIFTER_GENERIC_I/n83 ,
\ALU_instance/SHIFTER_GENERIC_I/n82 ,
\ALU_instance/SHIFTER_GENERIC_I/n81 ,
\ALU_instance/SHIFTER_GENERIC_I/n80 ,
\ALU_instance/SHIFTER_GENERIC_I/n79 ,
\ALU_instance/SHIFTER_GENERIC_I/n78 ,
\ALU_instance/SHIFTER_GENERIC_I/n77 ,
\ALU_instance/SHIFTER_GENERIC_I/n76 ,
\ALU_instance/SHIFTER_GENERIC_I/n75 ,
\ALU_instance/SHIFTER_GENERIC_I/n74 ,
\ALU_instance/SHIFTER_GENERIC_I/n73 ,
\ALU_instance/SHIFTER_GENERIC_I/n72 ,
\ALU_instance/SHIFTER_GENERIC_I/n71 ,
\ALU_instance/SHIFTER_GENERIC_I/n70 ,
\ALU_instance/SHIFTER_GENERIC_I/n69 ,
\ALU_instance/SHIFTER_GENERIC_I/n68 ,
\ALU_instance/SHIFTER_GENERIC_I/n67 ,
\ALU_instance/SHIFTER_GENERIC_I/n66 ,
\ALU_instance/SHIFTER_GENERIC_I/n65 ,
\ALU_instance/SHIFTER_GENERIC_I/n64 ,
\ALU_instance/SHIFTER_GENERIC_I/n63 ,
\ALU_instance/SHIFTER_GENERIC_I/n62 ,
\ALU_instance/SHIFTER_GENERIC_I/n61 ,
\ALU_instance/SHIFTER_GENERIC_I/n60 ,
\ALU_instance/SHIFTER_GENERIC_I/n59 ,
\ALU_instance/SHIFTER_GENERIC_I/n58 ,
\ALU_instance/SHIFTER_GENERIC_I/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/n52 ,
\ALU_instance/SHIFTER_GENERIC_I/n51 ,
\ALU_instance/SHIFTER_GENERIC_I/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/n49 ,
\ALU_instance/SHIFTER_GENERIC_I/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/n44 ,
\ALU_instance/SHIFTER_GENERIC_I/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/n41 ,
\ALU_instance/SHIFTER_GENERIC_I/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/n26 ,
\ALU_instance/SHIFTER_GENERIC_I/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/N265 ,
\ALU_instance/SHIFTER_GENERIC_I/N264 ,
\ALU_instance/SHIFTER_GENERIC_I/N263 ,
\ALU_instance/SHIFTER_GENERIC_I/N262 ,
\ALU_instance/SHIFTER_GENERIC_I/N261 ,
\ALU_instance/SHIFTER_GENERIC_I/N260 ,
\ALU_instance/SHIFTER_GENERIC_I/N259 ,
\ALU_instance/SHIFTER_GENERIC_I/N258 ,
\ALU_instance/SHIFTER_GENERIC_I/N257 ,
\ALU_instance/SHIFTER_GENERIC_I/N256 ,
\ALU_instance/SHIFTER_GENERIC_I/N255 ,
\ALU_instance/SHIFTER_GENERIC_I/N254 ,
\ALU_instance/SHIFTER_GENERIC_I/N253 ,
\ALU_instance/SHIFTER_GENERIC_I/N252 ,
\ALU_instance/SHIFTER_GENERIC_I/N251 ,
\ALU_instance/SHIFTER_GENERIC_I/N250 ,
\ALU_instance/SHIFTER_GENERIC_I/N249 ,
\ALU_instance/SHIFTER_GENERIC_I/N248 ,
\ALU_instance/SHIFTER_GENERIC_I/N247 ,
\ALU_instance/SHIFTER_GENERIC_I/N246 ,
\ALU_instance/SHIFTER_GENERIC_I/N245 ,
\ALU_instance/SHIFTER_GENERIC_I/N244 ,
\ALU_instance/SHIFTER_GENERIC_I/N243 ,
\ALU_instance/SHIFTER_GENERIC_I/N242 ,
\ALU_instance/SHIFTER_GENERIC_I/N241 ,
\ALU_instance/SHIFTER_GENERIC_I/N240 ,
\ALU_instance/SHIFTER_GENERIC_I/N239 ,
\ALU_instance/SHIFTER_GENERIC_I/N238 ,
\ALU_instance/SHIFTER_GENERIC_I/N237 ,
\ALU_instance/SHIFTER_GENERIC_I/N236 ,
\ALU_instance/SHIFTER_GENERIC_I/N235 ,
\ALU_instance/SHIFTER_GENERIC_I/N234 ,
\ALU_instance/SHIFTER_GENERIC_I/N233 ,
\ALU_instance/SHIFTER_GENERIC_I/N232 ,
\ALU_instance/SHIFTER_GENERIC_I/N231 ,
\ALU_instance/SHIFTER_GENERIC_I/N230 ,
\ALU_instance/SHIFTER_GENERIC_I/N229 ,
\ALU_instance/SHIFTER_GENERIC_I/N228 ,
\ALU_instance/SHIFTER_GENERIC_I/N227 ,
\ALU_instance/SHIFTER_GENERIC_I/N226 ,
\ALU_instance/SHIFTER_GENERIC_I/N225 ,
\ALU_instance/SHIFTER_GENERIC_I/N224 ,
\ALU_instance/SHIFTER_GENERIC_I/N223 ,
\ALU_instance/SHIFTER_GENERIC_I/N222 ,
\ALU_instance/SHIFTER_GENERIC_I/N221 ,
\ALU_instance/SHIFTER_GENERIC_I/N220 ,
\ALU_instance/SHIFTER_GENERIC_I/N219 ,
\ALU_instance/SHIFTER_GENERIC_I/N218 ,
\ALU_instance/SHIFTER_GENERIC_I/N217 ,
\ALU_instance/SHIFTER_GENERIC_I/N216 ,
\ALU_instance/SHIFTER_GENERIC_I/N215 ,
\ALU_instance/SHIFTER_GENERIC_I/N214 ,
\ALU_instance/SHIFTER_GENERIC_I/N213 ,
\ALU_instance/SHIFTER_GENERIC_I/N212 ,
\ALU_instance/SHIFTER_GENERIC_I/N211 ,
\ALU_instance/SHIFTER_GENERIC_I/N210 ,
\ALU_instance/SHIFTER_GENERIC_I/N209 ,
\ALU_instance/SHIFTER_GENERIC_I/N208 ,
\ALU_instance/SHIFTER_GENERIC_I/N207 ,
\ALU_instance/SHIFTER_GENERIC_I/N206 ,
\ALU_instance/SHIFTER_GENERIC_I/N205 ,
\ALU_instance/SHIFTER_GENERIC_I/N204 ,
\ALU_instance/SHIFTER_GENERIC_I/N203 ,
\ALU_instance/SHIFTER_GENERIC_I/N202 ,
\ALU_instance/SHIFTER_GENERIC_I/N168 ,
\ALU_instance/SHIFTER_GENERIC_I/N167 ,
\ALU_instance/SHIFTER_GENERIC_I/N166 ,
\ALU_instance/SHIFTER_GENERIC_I/N165 ,
\ALU_instance/SHIFTER_GENERIC_I/N164 ,
\ALU_instance/SHIFTER_GENERIC_I/N163 ,
\ALU_instance/SHIFTER_GENERIC_I/N162 ,
\ALU_instance/SHIFTER_GENERIC_I/N161 ,
\ALU_instance/SHIFTER_GENERIC_I/N160 ,
\ALU_instance/SHIFTER_GENERIC_I/N159 ,
\ALU_instance/SHIFTER_GENERIC_I/N158 ,
\ALU_instance/SHIFTER_GENERIC_I/N157 ,
\ALU_instance/SHIFTER_GENERIC_I/N156 ,
\ALU_instance/SHIFTER_GENERIC_I/N155 ,
\ALU_instance/SHIFTER_GENERIC_I/N154 ,
\ALU_instance/SHIFTER_GENERIC_I/N153 ,
\ALU_instance/SHIFTER_GENERIC_I/N152 ,
\ALU_instance/SHIFTER_GENERIC_I/N151 ,
\ALU_instance/SHIFTER_GENERIC_I/N150 ,
\ALU_instance/SHIFTER_GENERIC_I/N149 ,
\ALU_instance/SHIFTER_GENERIC_I/N148 ,
\ALU_instance/SHIFTER_GENERIC_I/N147 ,
\ALU_instance/SHIFTER_GENERIC_I/N146 ,
\ALU_instance/SHIFTER_GENERIC_I/N145 ,
\ALU_instance/SHIFTER_GENERIC_I/N144 ,
\ALU_instance/SHIFTER_GENERIC_I/N143 ,
\ALU_instance/SHIFTER_GENERIC_I/N142 ,
\ALU_instance/SHIFTER_GENERIC_I/N141 ,
\ALU_instance/SHIFTER_GENERIC_I/N140 ,
\ALU_instance/SHIFTER_GENERIC_I/N139 ,
\ALU_instance/SHIFTER_GENERIC_I/N138 ,
\ALU_instance/SHIFTER_GENERIC_I/N137 ,
\ALU_instance/SHIFTER_GENERIC_I/N135 ,
\ALU_instance/SHIFTER_GENERIC_I/N134 ,
\ALU_instance/SHIFTER_GENERIC_I/N133 ,
\ALU_instance/SHIFTER_GENERIC_I/N132 ,
\ALU_instance/SHIFTER_GENERIC_I/N131 ,
\ALU_instance/SHIFTER_GENERIC_I/N130 ,
\ALU_instance/SHIFTER_GENERIC_I/N129 ,
\ALU_instance/SHIFTER_GENERIC_I/N128 ,
\ALU_instance/SHIFTER_GENERIC_I/N127 ,
\ALU_instance/SHIFTER_GENERIC_I/N126 ,
\ALU_instance/SHIFTER_GENERIC_I/N125 ,
\ALU_instance/SHIFTER_GENERIC_I/N124 ,
\ALU_instance/SHIFTER_GENERIC_I/N123 ,
\ALU_instance/SHIFTER_GENERIC_I/N122 ,
\ALU_instance/SHIFTER_GENERIC_I/N121 ,
\ALU_instance/SHIFTER_GENERIC_I/N120 ,
\ALU_instance/SHIFTER_GENERIC_I/N119 ,
\ALU_instance/SHIFTER_GENERIC_I/N118 ,
\ALU_instance/SHIFTER_GENERIC_I/N117 ,
\ALU_instance/SHIFTER_GENERIC_I/N116 ,
\ALU_instance/SHIFTER_GENERIC_I/N115 ,
\ALU_instance/SHIFTER_GENERIC_I/N114 ,
\ALU_instance/SHIFTER_GENERIC_I/N113 ,
\ALU_instance/SHIFTER_GENERIC_I/N112 ,
\ALU_instance/SHIFTER_GENERIC_I/N111 ,
\ALU_instance/SHIFTER_GENERIC_I/N110 ,
\ALU_instance/SHIFTER_GENERIC_I/N109 ,
\ALU_instance/SHIFTER_GENERIC_I/N108 ,
\ALU_instance/SHIFTER_GENERIC_I/N107 ,
\ALU_instance/SHIFTER_GENERIC_I/N106 ,
\ALU_instance/SHIFTER_GENERIC_I/N105 ,
\BOOTH_instance/add_0_root_add_53_G7/carry[5] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[6] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[7] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[8] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[7] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[8] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[3] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[4] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[5] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[6] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[7] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[8] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[31] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][0] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][1] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][2] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][4] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][5] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][6] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][7] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][16] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][17] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][18] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][19] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][20] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][21] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][22] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][23] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][24] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][25] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][26] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][27] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][28] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][29] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][30] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][31] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ,
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\ALU_instance/SHIFTER_GENERIC_I/C50/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n22 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n15 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n2 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n163 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n162 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n161 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n160 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n159 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n158 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n157 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n156 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n155 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n151 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n150 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n149 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n148 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n147 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n146 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n145 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n144 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n143 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n142 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n141 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n138 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n135 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n134 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n131 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n130 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n128 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n127 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n124 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n121 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n118 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n115 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n112 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n111 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n110 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n106 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n105 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n101 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n99 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n98 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n96 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n94 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n93 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n92 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n90 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n88 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n87 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n85 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n82 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n78 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n62 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n61 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n58 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n26 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n21 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n20 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n14 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[3] ,
\EX_MEM_OUT_REG_instance/n34 , \EX_MEM_REGB_REG_instance/n34 ,
\ID_EX_PC_REG_instance/n34 , \ID_EX_REGA_REG_instance/n34 ,
\ID_EX_IMM16_EXT_REG_instance/n34 , n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1623, n1624, n1626, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1721, n1822, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197;
wire [1:0] EX_ALU_SEL;
wire [5:0] EX_COMPARATOR_CW;
wire [3:1] EX_LOGIC_CW;
wire [1:0] EX_SHIFTER_CW;
wire [31:0] EX_ALU_OUT;
wire [31:0] EX_MULT_OUT;
wire [31:0] ID_IMM16_SHL2;
wire [31:0] WB_DATA_EXT_16;
wire [31:0] WB_DATA_EXT_8;
wire [31:0] IF_PC_INC;
wire [31:0] ID_PC;
wire [31:0] EX_REGA;
wire [31:0] EX_REGB;
wire [31:0] EX_IMM16_EXT;
wire [31:0] EX_PC;
wire [31:0] ID_INSTR_AFTER_CU;
wire [31:0] EX_INSTR;
wire [31:0] MEM_INSTR;
wire [31:0] WB_DATA_RAM;
wire [31:0] WB_ALU;
wire [20:0] WB_INSTR;
wire [31:0] ID_PC_SUM;
assign RF_ENABLE = 1'b1;
assign PORT_PC[1] = IF_PC_INC[1];
assign PORT_PC[0] = IF_PC_INC[0];
assign RF_DATAIN[0] = N6243;
assign RF_DATAIN[1] = N6244;
assign RF_DATAIN[2] = N6245;
assign RF_DATAIN[3] = N6246;
assign RF_DATAIN[4] = N6247;
assign RF_DATAIN[5] = N6248;
assign RF_DATAIN[6] = N6249;
assign RF_DATAIN[7] = N6250;
assign RF_DATAIN[8] = N6251;
assign RF_DATAIN[9] = N6252;
assign RF_DATAIN[10] = N6253;
assign RF_DATAIN[11] = N6254;
assign RF_DATAIN[12] = N6255;
assign RF_DATAIN[13] = N6256;
assign RF_DATAIN[14] = N6257;
assign RF_DATAIN[15] = N6258;
assign RF_DATAIN[16] = N6259;
assign RF_DATAIN[17] = N6260;
assign RF_DATAIN[18] = N6261;
assign RF_DATAIN[19] = N6262;
assign RF_DATAIN[20] = N6263;
assign RF_DATAIN[21] = N6264;
assign RF_DATAIN[22] = N6265;
assign RF_DATAIN[23] = N6266;
assign RF_DATAIN[24] = N6267;
assign RF_DATAIN[25] = N6268;
assign RF_DATAIN[26] = N6269;
assign RF_DATAIN[27] = N6270;
assign RF_DATAIN[28] = N6271;
assign RF_DATAIN[29] = N6272;
assign RF_DATAIN[30] = N6273;
TLATXL ID_HAZARD_MEM_reg ( .G(N4716), .D(N4710), .QN(n319) );
TLATXL ID_HAZARD_WB_reg ( .G(N4717), .D(N4708), .QN(n320) );
TLATXL ID_HAZARD_EX_reg ( .G(N4717), .D(N4712), .QN(n321) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[16] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[16]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[16]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(MEM_INSTR[17]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[17]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[18]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[18]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[19]), .E(1'b1), .CK(
CLOCK), .Q(WB_INSTR[19]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[20] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(MEM_INSTR[20]), .E(1'b1), .CK(
CLOCK), .Q(WB_INSTR[20]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[16] ( .RN(\PC_instance/n33 ),
.D(PORT_DATA_RAM[16]), .E(1'b1), .CK(CLOCK), .Q(WB_DATA_RAM[16]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[17] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_DATA_RAM[17]), .E(1'b1),
.CK(CLOCK), .Q(WB_DATA_RAM[17]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[18]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[18]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[19]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[19]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[20] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_DATA_RAM[20]), .E(1'b1),
.CK(CLOCK), .Q(WB_DATA_RAM[20]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[21] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[21]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[21]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[22] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[22]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[22]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[23]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[23]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[24] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[24]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[24]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[25] ( .RN(\PC_instance/n33 ),
.D(PORT_DATA_RAM[25]), .E(1'b1), .CK(CLOCK), .Q(WB_DATA_RAM[25]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[26] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[26]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[26]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[27] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_DATA_RAM[27]), .E(1'b1),
.CK(CLOCK), .Q(WB_DATA_RAM[27]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[28]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[28]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[29]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[29]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[30] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[30]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[30]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[31] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[31]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[31]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[0] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[0]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[0]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[1] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[1]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[1]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[2] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[2]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[2]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[3]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[3]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[4] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[4]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[4]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[5] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[5]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[5]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[6] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[6]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[6]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[0] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[0]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[0]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[1] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[1]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[1]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[2] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[2]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[2]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[3] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[3]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[3]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[4] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[4]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[4]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[5] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[5]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[5]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[6] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[6]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[6]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[7] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[7]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[7]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[8] ( .RN(\PC_instance/n33 ),
.D(PORT_DATA_RAM[8]), .E(1'b1), .CK(CLOCK), .Q(WB_DATA_RAM[8]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[9]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[9]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[10]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[10]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[11]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[11]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[12] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[12]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[12]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[13]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[13]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[14]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[14]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[15] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[15]), .E(1'b1), .CK(
CLOCK), .Q(WB_DATA_RAM[15]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[7] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[7]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[7]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[8] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[8]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[8]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[9] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[9]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[9]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[10] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[10]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[10]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[11] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[11]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[11]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[12] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[12]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[12]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[13] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[13]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[13]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[14] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[14]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[14]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[15] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[15]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[15]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[16] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[16]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[16]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[17] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[17]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[17]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[18] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[18]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[18]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[19] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[19]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[19]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[20] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[20]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[20]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[21] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[21]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[21]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[22] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[22]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[22]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[23] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[23]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[23]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[24] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[24]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[24]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[25] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[25]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[25]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[26] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[26]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[26]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[27] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[27]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[27]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[28] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[28]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[28]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[29] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[29]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[29]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[30] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[30]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[30]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[31] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[31]), .E(1'b1), .CK(CLOCK),
.Q(WB_ALU[31]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[4]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[4]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[5] ( .RN(\PC_instance/n33 ), .D(
MEM_INSTR[5]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[5]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[6] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(MEM_INSTR[6]), .E(1'b1), .CK(
CLOCK), .Q(WB_INSTR[6]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[9]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[9]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[8] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[8]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[8]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[10] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[10]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[10]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[7] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(MEM_INSTR[7]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[7]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[0]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[0]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[11]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[11]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[12]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[12]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[13]), .E(1'b1), .CK(
CLOCK), .Q(WB_INSTR[13]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[14] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(MEM_INSTR[14]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[14]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[15] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[15]), .E(1'b1), .CK(
CLOCK), .Q(WB_INSTR[15]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[1] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[1]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[1]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(MEM_INSTR[3]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR[3]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[2]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR[2]) );
EDFFTRXL \PC_instance/Q_reg[0] ( .RN(\PC_instance/n33 ), .D(N730), .E(n2157), .CK(n1628), .Q(IF_PC_INC[0]) );
EDFFTRXL \PC_instance/Q_reg[1] ( .RN(\PC_instance/n33 ), .D(N731), .E(n2157), .CK(n1628), .Q(IF_PC_INC[1]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[0] ( .RN(\PC_instance/n33 ), .D(
IF_PC_INC[0]), .E(n2156), .CK(n1628), .Q(ID_PC_SUM[0]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[1] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(IF_PC_INC[1]), .E(n2156), .CK(n1628), .Q(ID_PC_SUM[1]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[14] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[14]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[14]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[11] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[11]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[11]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[16] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[16]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[16]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_INSTR[14]), .E(1'b1), .CK(CLOCK), .Q(MEM_INSTR[14]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[11] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(EX_INSTR[11]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[11]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[31]), .E(n2155), .CK(n1628), .Q(ID_PC[31]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[19] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[19]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[19]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[24] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[24]), .E(n2156), .CK(n1628), .Q(ID_PC[24]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[25] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(PORT_PC[25]), .E(n2156), .CK(n1628), .Q(ID_PC[25]) );
EDFFTRXL \PC_instance/Q_reg[31] ( .RN(\PC_instance/n33 ), .D(N761), .E(
n2155), .CK(n1628), .Q(PORT_PC[31]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(EX_INSTR[19]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[19]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[16] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[16]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[16]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[12] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[12]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[12]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[12]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[12]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[15] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[15]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[15]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[17] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[17]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[17]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[13] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[13]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[13]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[18]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[18]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[15] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[15]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[15]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[13]), .E(1'b1), .CK(
CLOCK), .Q(MEM_INSTR[13]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[26]), .E(n2156), .CK(n1628), .Q(ID_PC[26]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[27] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_PC[27]), .E(n2155), .CK(n1628),
.Q(ID_PC[27]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_PC[28]), .E(n2155), .CK(n1628),
.Q(ID_PC[28]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[29] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[29]), .E(n2155), .CK(n1628), .Q(ID_PC[29]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[30] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(PORT_PC[30]), .E(n2155), .CK(n1628), .Q(ID_PC[30]) );
EDFFTRXL \PC_instance/Q_reg[22] ( .RN(\PC_instance/n33 ), .D(N752), .E(
n2157), .CK(n1628), .Q(PORT_PC[22]) );
EDFFTRXL \PC_instance/Q_reg[23] ( .RN(\PC_instance/n33 ), .D(N753), .E(
n2157), .CK(n1628), .Q(PORT_PC[23]) );
EDFFTRXL \PC_instance/Q_reg[24] ( .RN(\PC_instance/n33 ), .D(N754), .E(
n2157), .CK(n1628), .Q(PORT_PC[24]) );
EDFFTRXL \PC_instance/Q_reg[25] ( .RN(\PC_instance/n33 ), .D(N755), .E(
n2157), .CK(n1628), .Q(PORT_PC[25]) );
EDFFTRXL \PC_instance/Q_reg[26] ( .RN(\PC_instance/n33 ), .D(N756), .E(
n2157), .CK(n1628), .Q(PORT_PC[26]) );
EDFFTRXL \PC_instance/Q_reg[27] ( .RN(\PC_instance/n33 ), .D(N757), .E(
n2157), .CK(n1628), .Q(PORT_PC[27]) );
EDFFTRXL \PC_instance/Q_reg[28] ( .RN(\PC_instance/n33 ), .D(N758), .E(
n2157), .CK(n1628), .Q(PORT_PC[28]) );
EDFFTRXL \PC_instance/Q_reg[29] ( .RN(\PC_instance/n33 ), .D(N759), .E(
n2157), .CK(n1628), .Q(PORT_PC[29]) );
EDFFTRXL \PC_instance/Q_reg[30] ( .RN(\PC_instance/n33 ), .D(N760), .E(
n2157), .CK(n1628), .Q(PORT_PC[30]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[20] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[20]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[20]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[20] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[20]), .E(1'b1), .CK(CLOCK), .Q(MEM_INSTR[20]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[17] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[17]), .E(1'b1), .CK(CLOCK), .Q(MEM_INSTR[17]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[18]), .E(1'b1), .CK(
CLOCK), .Q(MEM_INSTR[18]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[28] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[28]), .E(1'b1), .CK(CLOCK), .Q(MEM_INSTR[28]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[30] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[30]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[30]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[21] ( .RN(\PC_instance/n33 ), .D(
N785), .E(n2156), .CK(n1628), .Q(RF_ADD_RD1[0]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_INSTR[26]), .E(1'b1), .CK(CLOCK), .Q(MEM_INSTR[26]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[16] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[16]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[16]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[17]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[17]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[18]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[18]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[19]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[19]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[20] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[20]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[20]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[21] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[21]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[21]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[22] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[22]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[22]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[23] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[23]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[23]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[24] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[24]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[24]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[25] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[25]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[25]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[26] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[26]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[26]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[27] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[27]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[27]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[28]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[28]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[29]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[29]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[30] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[30]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[30]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[31] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[31]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[31]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[16] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[16]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[16]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[17] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[17]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[17]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[18] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[18]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[18]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[19] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[19]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[19]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[20] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[20]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[20]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[21] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[21]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[21]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[22] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[22]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[22]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[23] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[23]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[23]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[24] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[24]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[24]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[25] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[25]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[25]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[26] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[26]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[26]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[27] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[27]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[27]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[28] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[28]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[28]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[29] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[29]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[29]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[30] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[30]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[30]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[31] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[31]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[31]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[16] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[16]), .QN(n1676) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[17] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[17]), .QN(n1675) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[18] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[18]), .QN(n1674) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[19] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[19]), .QN(n1673) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[20] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[20]), .QN(n1672) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[21] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[21]), .QN(n1671) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[22] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[22]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[23] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[23]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[24] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[24]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[25] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[25]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[26] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[26]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[27] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[27]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[28] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[28]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[29] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[29]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[30] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[30]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[31] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[31]), .QN(n1693) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[16] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[16]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[16]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[17]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[17]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[18]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[18]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[19]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[19]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[20] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[20]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[20]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[21] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[21]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[21]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[22] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[22]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[22]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[23] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[23]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[23]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[24] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[24]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[24]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[25] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[25]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[25]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[26] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[26]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[26]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[27] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[27]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[27]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[28]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[28]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[29]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[29]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[30] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[30]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[30]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[31] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[31]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[31]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[9] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(PORT_PC[9]), .E(n2155), .CK(n1628), .Q(ID_PC[9]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[10] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[10]), .E(n2155), .CK(n1628), .Q(ID_PC[10]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[11]), .E(n2155), .CK(n1628),
.Q(ID_PC[11]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[12]), .E(n2155), .CK(n1628),
.Q(ID_PC[12]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_PC[13]), .E(n2155), .CK(
n1628), .Q(ID_PC[13]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[14] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_PC[14]), .E(n2155), .CK(n1628),
.Q(ID_PC[14]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[15] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_PC[15]), .E(n2155), .CK(n1628),
.Q(ID_PC[15]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[16] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[16]), .E(n2155), .CK(n1628), .Q(ID_PC[16]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[17] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(PORT_PC[17]), .E(n2155), .CK(n1628), .Q(ID_PC[17]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[18] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[18]), .E(n2155), .CK(n1628), .Q(ID_PC[18]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[19]), .E(n2155), .CK(n1628),
.Q(ID_PC[19]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[20]), .E(n2155), .CK(n1628),
.Q(ID_PC[20]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[21] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_PC[21]), .E(n2155), .CK(
n1628), .Q(ID_PC[21]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[22] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[22]), .E(n2156), .CK(n1628),
.Q(ID_PC[22]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[23]), .E(n2156), .CK(n1628),
.Q(ID_PC[23]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[15] ( .RN(\PC_instance/n33 ), .D(
N779), .E(n2156), .CK(n1628), .Q(ID_IMM16_SHL2[31]) );
EDFFTRXL \PC_instance/Q_reg[3] ( .RN(\PC_instance/n33 ), .D(N733), .E(n2156), .CK(n1628), .Q(PORT_PC[3]) );
EDFFTRXL \PC_instance/Q_reg[4] ( .RN(\PC_instance/n33 ), .D(N734), .E(n2157), .CK(n1628), .Q(PORT_PC[4]) );
EDFFTRXL \PC_instance/Q_reg[6] ( .RN(\PC_instance/n33 ), .D(N736), .E(n2157), .CK(n1628), .Q(PORT_PC[6]) );
EDFFTRXL \PC_instance/Q_reg[7] ( .RN(\PC_instance/n33 ), .D(N737), .E(n2157), .CK(n1628), .Q(PORT_PC[7]) );
EDFFTRXL \PC_instance/Q_reg[8] ( .RN(\PC_instance/n33 ), .D(N738), .E(n2157), .CK(n1628), .Q(PORT_PC[8]) );
EDFFTRXL \PC_instance/Q_reg[9] ( .RN(\PC_instance/n33 ), .D(N739), .E(n2157), .CK(n1628), .Q(PORT_PC[9]) );
EDFFTRXL \PC_instance/Q_reg[10] ( .RN(\PC_instance/n33 ), .D(N740), .E(
n2157), .CK(n1628), .Q(PORT_PC[10]) );
EDFFTRXL \PC_instance/Q_reg[11] ( .RN(\PC_instance/n33 ), .D(N741), .E(
n2157), .CK(n1628), .Q(PORT_PC[11]) );
EDFFTRXL \PC_instance/Q_reg[12] ( .RN(\PC_instance/n33 ), .D(N742), .E(
n2157), .CK(n1628), .Q(PORT_PC[12]) );
EDFFTRXL \PC_instance/Q_reg[13] ( .RN(\PC_instance/n33 ), .D(N743), .E(
n2157), .CK(n1628), .Q(PORT_PC[13]) );
EDFFTRXL \PC_instance/Q_reg[14] ( .RN(\PC_instance/n33 ), .D(N744), .E(
n2157), .CK(n1628), .Q(PORT_PC[14]) );
EDFFTRXL \PC_instance/Q_reg[15] ( .RN(\PC_instance/n33 ), .D(N745), .E(
n2157), .CK(n1628), .Q(PORT_PC[15]) );
EDFFTRXL \PC_instance/Q_reg[16] ( .RN(\PC_instance/n33 ), .D(N746), .E(
n2157), .CK(n1628), .Q(PORT_PC[16]) );
EDFFTRXL \PC_instance/Q_reg[17] ( .RN(\PC_instance/n33 ), .D(N747), .E(
n2157), .CK(n1628), .Q(PORT_PC[17]) );
EDFFTRXL \PC_instance/Q_reg[18] ( .RN(\PC_instance/n33 ), .D(N748), .E(
n2157), .CK(n1628), .Q(PORT_PC[18]) );
EDFFTRXL \PC_instance/Q_reg[19] ( .RN(\PC_instance/n33 ), .D(N749), .E(
n2157), .CK(n1628), .Q(PORT_PC[19]) );
EDFFTRXL \PC_instance/Q_reg[20] ( .RN(\PC_instance/n33 ), .D(N750), .E(
n2157), .CK(n1628), .Q(PORT_PC[20]) );
EDFFTRXL \PC_instance/Q_reg[21] ( .RN(\PC_instance/n33 ), .D(N751), .E(
n2157), .CK(n1628), .Q(PORT_PC[21]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(N775), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[13]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N776), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[14]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N777), .E(n2156), .CK(n1628),
.Q(ID_IMM16_SHL2[15]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[14] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N778), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[16]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[7] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[7]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[7]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[8]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[8]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[9]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[9]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[10]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[10]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[11]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[11]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[12]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[12]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[13] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[13]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[13]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[14] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[14]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[14]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[15] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[15]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[15]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[7] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[7]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[7]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[8] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[8]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[8]), .QN(n1666) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[9] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[9]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[9]), .QN(n1667) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[10] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[10]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[10]), .QN(n1650) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[11] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[11]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[11]), .QN(n1668) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[12] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[12]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[12]), .QN(n1669) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[13] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[13]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[13]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[14] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[14]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[14]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[15] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[15]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[15]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[4] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[6]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[4]), .QN(n1664) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[5] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[7]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[5]), .QN(n1658) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[6] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[8]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[6]), .QN(n1653) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[7] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[9]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[7]), .QN(n1659) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[8] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[10]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[8]), .QN(n1655) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[9] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[11]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[9]), .QN(n1657) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[10] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[12]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[10]), .QN(n1656) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[11] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[13]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[11]), .QN(n1649) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[12] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[14]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[12]), .QN(n1654) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[15]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[13]), .QN(n1661) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[14] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[16]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[14]), .QN(n1652) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[15] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(n2109), .E(1'b1), .CK(CLOCK),
.Q(EX_IMM16_EXT[15]), .QN(n1660) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[4] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[4]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[4]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[5] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[5]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[5]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[6] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[6]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[6]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[7] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[7]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[7]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[8]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[8]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[9]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[9]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[10]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[10]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[11]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[11]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[12]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[12]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[13] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[13]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[13]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[14] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[14]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[14]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[15] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[15]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[15]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[5] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[5]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[5]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[6] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[6]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[6]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[5] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[5]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[5]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[6] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[6]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[6]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[9] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[9]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[9]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[8] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[8]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[8]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[7] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[7]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[7]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[3]), .E(n2155), .CK(n1628),
.Q(ID_PC[3]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[4]), .E(n2155), .CK(n1628),
.Q(ID_PC[4]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[5] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_PC[5]), .E(n2155), .CK(
n1628), .Q(ID_PC[5]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[6] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_PC[6]), .E(n2155), .CK(n1628),
.Q(ID_PC[6]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[7] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_PC[7]), .E(n2155), .CK(n1628),
.Q(ID_PC[7]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[8] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[8]), .E(n2155), .CK(n1628), .Q(ID_PC[8]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[10] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[10]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[10]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[6] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[6]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[6]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[4] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[4]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[4]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[2]), .E(n2156), .CK(n1628),
.Q(ID_PC[2]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[3] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[5]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[3]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[2] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[2]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[2]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[3]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[3]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[4] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[4]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[4]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[2] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[2]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[2]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[3] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[3]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[3]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[4] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[4]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[4]), .QN(n1665) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[0] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[2]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[0]), .QN(n1662) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[1] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[3]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[1]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[2] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[4]), .E(1'b1),
.CK(CLOCK), .Q(EX_IMM16_EXT[2]), .QN(n1663) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[0]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[0]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[1] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[1]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[1]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[2] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[2]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[2]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[3]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGB[3]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[0]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[0]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[1] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[1]), .E(1'b1), .CK(CLOCK),
.Q(EX_REGA[1]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[0] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC_SUM[0]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[0]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[1] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC_SUM[1]), .E(1'b1), .CK(CLOCK), .Q(EX_PC[1]) );
ADDFHXL \add_545/U1_30 ( .A(ID_PC[30]), .B(n2109), .CI(\add_545/carry[30] ),
.CO(\add_545/carry[31] ), .S(ID_PC_SUM[30]) );
ADDFXL \add_545/U1_3 ( .A(ID_PC[3]), .B(ID_IMM16_SHL2[3]), .CI(
\add_545/carry[3] ), .CO(\add_545/carry[4] ), .S(ID_PC_SUM[3]) );
ADDFHXL \add_545/U1_9 ( .A(ID_PC[9]), .B(ID_IMM16_SHL2[9]), .CI(
\add_545/carry[9] ), .CO(\add_545/carry[10] ), .S(ID_PC_SUM[9]) );
ADDFHXL \add_545/U1_10 ( .A(ID_PC[10]), .B(ID_IMM16_SHL2[10]), .CI(
\add_545/carry[10] ), .CO(\add_545/carry[11] ), .S(ID_PC_SUM[10]) );
ADDFHXL \add_545/U1_11 ( .A(ID_PC[11]), .B(ID_IMM16_SHL2[11]), .CI(
\add_545/carry[11] ), .CO(\add_545/carry[12] ), .S(ID_PC_SUM[11]) );
ADDFHXL \add_545/U1_12 ( .A(ID_PC[12]), .B(ID_IMM16_SHL2[12]), .CI(
\add_545/carry[12] ), .CO(\add_545/carry[13] ), .S(ID_PC_SUM[12]) );
ADDFHXL \add_545/U1_13 ( .A(ID_PC[13]), .B(ID_IMM16_SHL2[13]), .CI(
\add_545/carry[13] ), .CO(\add_545/carry[14] ), .S(ID_PC_SUM[13]) );
ADDFHXL \add_545/U1_14 ( .A(ID_PC[14]), .B(ID_IMM16_SHL2[14]), .CI(
\add_545/carry[14] ), .CO(\add_545/carry[15] ), .S(ID_PC_SUM[14]) );
ADDFHXL \add_545/U1_15 ( .A(ID_PC[15]), .B(ID_IMM16_SHL2[15]), .CI(
\add_545/carry[15] ), .CO(\add_545/carry[16] ), .S(ID_PC_SUM[15]) );
ADDFHXL \add_545/U1_16 ( .A(ID_PC[16]), .B(ID_IMM16_SHL2[16]), .CI(
\add_545/carry[16] ), .CO(\add_545/carry[17] ), .S(ID_PC_SUM[16]) );
ADDFHXL \add_545/U1_17 ( .A(ID_PC[17]), .B(n2109), .CI(\add_545/carry[17] ),
.CO(\add_545/carry[18] ), .S(ID_PC_SUM[17]) );
ADDFHXL \add_545/U1_18 ( .A(ID_PC[18]), .B(n2109), .CI(\add_545/carry[18] ),
.CO(\add_545/carry[19] ), .S(ID_PC_SUM[18]) );
ADDFHXL \add_545/U1_19 ( .A(ID_PC[19]), .B(n2109), .CI(\add_545/carry[19] ),
.CO(\add_545/carry[20] ), .S(ID_PC_SUM[19]) );
ADDFHXL \add_545/U1_20 ( .A(ID_PC[20]), .B(n2109), .CI(\add_545/carry[20] ),
.CO(\add_545/carry[21] ), .S(ID_PC_SUM[20]) );
ADDFHXL \add_545/U1_21 ( .A(ID_PC[21]), .B(n2109), .CI(\add_545/carry[21] ),
.CO(\add_545/carry[22] ), .S(ID_PC_SUM[21]) );
ADDFHXL \add_545/U1_22 ( .A(ID_PC[22]), .B(n2109), .CI(\add_545/carry[22] ),
.CO(\add_545/carry[23] ), .S(ID_PC_SUM[22]) );
ADDFHXL \add_545/U1_23 ( .A(ID_PC[23]), .B(n2109), .CI(\add_545/carry[23] ),
.CO(\add_545/carry[24] ), .S(ID_PC_SUM[23]) );
ADDFHXL \add_545/U1_24 ( .A(ID_PC[24]), .B(n2109), .CI(\add_545/carry[24] ),
.CO(\add_545/carry[25] ), .S(ID_PC_SUM[24]) );
ADDFHXL \add_545/U1_25 ( .A(ID_PC[25]), .B(n2109), .CI(\add_545/carry[25] ),
.CO(\add_545/carry[26] ), .S(ID_PC_SUM[25]) );
ADDFHXL \add_545/U1_26 ( .A(ID_PC[26]), .B(n2109), .CI(\add_545/carry[26] ),
.CO(\add_545/carry[27] ), .S(ID_PC_SUM[26]) );
ADDFHXL \add_545/U1_27 ( .A(ID_PC[27]), .B(n2109), .CI(\add_545/carry[27] ),
.CO(\add_545/carry[28] ), .S(ID_PC_SUM[27]) );
ADDFHXL \add_545/U1_28 ( .A(ID_PC[28]), .B(n2109), .CI(\add_545/carry[28] ),
.CO(\add_545/carry[29] ), .S(ID_PC_SUM[28]) );
ADDFHXL \add_545/U1_29 ( .A(ID_PC[29]), .B(n2109), .CI(\add_545/carry[29] ),
.CO(\add_545/carry[30] ), .S(ID_PC_SUM[29]) );
ADDFHXL \add_545/U1_8 ( .A(ID_PC[8]), .B(ID_IMM16_SHL2[8]), .CI(
\add_545/carry[8] ), .CO(\add_545/carry[9] ), .S(ID_PC_SUM[8]) );
ADDFHXL \add_545/U1_7 ( .A(ID_PC[7]), .B(ID_IMM16_SHL2[7]), .CI(
\add_545/carry[7] ), .CO(\add_545/carry[8] ), .S(ID_PC_SUM[7]) );
ADDFHXL \add_545/U1_6 ( .A(ID_PC[6]), .B(ID_IMM16_SHL2[6]), .CI(
\add_545/carry[6] ), .CO(\add_545/carry[7] ), .S(ID_PC_SUM[6]) );
ADDFHXL \add_545/U1_5 ( .A(ID_PC[5]), .B(ID_IMM16_SHL2[5]), .CI(
\add_545/carry[5] ), .CO(\add_545/carry[6] ), .S(ID_PC_SUM[5]) );
ADDFHXL \add_545/U1_4 ( .A(ID_PC[4]), .B(ID_IMM16_SHL2[4]), .CI(
\add_545/carry[4] ), .CO(\add_545/carry[5] ), .S(ID_PC_SUM[4]) );
XOR3XL \add_545/U1_31 ( .A(ID_PC[31]), .B(n2109), .C(\add_545/carry[31] ),
.Y(ID_PC_SUM[31]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[0] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[0]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[0]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[1] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[1]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[1]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[2]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[2]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[3] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[3]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[3]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[4]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[4]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[5] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[5]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[5]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[6] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[6]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[6]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[7] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[7]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[7]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[8] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[8]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[8]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[9] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[9]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[9]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[10] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[10]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[10]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[11]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[11]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[12]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[12]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[13]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[13]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[14]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[14]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[15] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[15]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[15]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[16] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[16]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[16]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[17] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[17]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[17]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[18] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[18]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[18]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[19]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[19]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[20]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[20]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[21] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[21]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[21]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[22] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[22]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[22]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[23]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[23]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[24] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[24]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[24]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[25] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[25]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[25]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[26]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[26]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[27] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[27]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[27]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[28] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[28]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[28]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[29] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[29]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[29]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[30] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[30]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[30]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[31]), .E(1'b1), .CK(CLOCK),
.Q(PORT_REGB[31]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[26] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(MEM_INSTR[26]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR_26) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[31]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR_31) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[28] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[28]), .E(1'b1), .CK(CLOCK),
.Q(WB_INSTR_28) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[29]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR_29) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[27] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[27]), .E(1'b1), .CK(CLOCK), .Q(WB_INSTR_27) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[30] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[30]), .E(1'b1), .CK(
CLOCK), .Q(WB_INSTR_30) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[0]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[0]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[1] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[1]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[1]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[2] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[2]), .E(1'b1), .CK(
CLOCK), .Q(MEM_INSTR[2]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[3] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[3]), .E(1'b1), .CK(CLOCK), .Q(MEM_INSTR[3]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[4] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[4]), .E(1'b1), .CK(
CLOCK), .Q(MEM_INSTR[4]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[5] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[5]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[5]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[6] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[6]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[6]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[7] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(EX_INSTR[7]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[7]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[8]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[8]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[9] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(EX_INSTR[9]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[9]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[10] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[10]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[10]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[0] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4860), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[0]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[1] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4861), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[1]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4862), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[2]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[3] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4863), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[3]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4864), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[4]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[5] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4865), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[5]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[6] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4866), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[6]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[7] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4867), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[7]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[8] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4868), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[8]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[9] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4869), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[9]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[10] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4870), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[10]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4871), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[11]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4872), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[12]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4873), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[13]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4874), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[14]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[15] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4875), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[15]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[16] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4876), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[16]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[17] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4877), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[17]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[18] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4878), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[18]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4879), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[19]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4880), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[20]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[21] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4881), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[21]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[22] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4882), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[22]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4883), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[23]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[24] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4884), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[24]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[25] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4885), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[25]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4886), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[26]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[27] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4887), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[27]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[28] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4888), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[28]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[25] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N789), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD1[4]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[27] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(EX_INSTR[27]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[27]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[24] ( .RN(\PC_instance/n33 ), .D(
N788), .E(n2156), .CK(n1628), .Q(RF_ADD_RD1[3]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[26] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(N790), .E(n2156), .CK(n1628), .Q(
ID_INSTR_26) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[23] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N787), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD1[2]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(N781), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD2[1]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[30] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N794), .E(n2156), .CK(n1628), .Q(
ID_INSTR_30) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N783), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD2[3]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[16] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N780), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD2[0]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[29] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[29]), .E(1'b1), .CK(
CLOCK), .Q(MEM_INSTR[29]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[29] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(N793), .E(n2156), .CK(n1628), .Q(
ID_INSTR_29) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[22] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N786), .E(n2156), .CK(n1628),
.Q(RF_ADD_RD1[1]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[27] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N791), .E(n2156), .CK(n1628), .Q(
ID_INSTR_27) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N782), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD2[2]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(N784), .E(n2156), .CK(n1628), .Q(
RF_ADD_RD2[4]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[31] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N795), .E(n2156), .CK(n1628),
.Q(ID_INSTR_31) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N792), .E(n2156), .CK(n1628), .Q(
ID_INSTR_28) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_30 ( .A(n1691), .B(n1682),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_31 ( .A(n1692), .B(n1691),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_5 ( .A(N4723), .B(n2190),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_15 ( .A(n1651), .B(n2177),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_17 ( .A(n1679), .B(n1684),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_18 ( .A(n1689), .B(n1679),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_19 ( .A(n1688), .B(n1689),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_20 ( .A(n1683), .B(n1688),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_21 ( .A(n1686), .B(n1683),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_22 ( .A(n1687), .B(n1686),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_23 ( .A(n1678), .B(n1687),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_24 ( .A(n1685), .B(n1678),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_25 ( .A(n1677), .B(n1685),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_26 ( .A(n1680), .B(n1677),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_27 ( .A(n1681), .B(n1680),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_28 ( .A(n1690), .B(n1681),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_29 ( .A(n1682), .B(n1690),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_16 ( .A(n1684), .B(n1651),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_2 ( .A(n2193), .B(n2115),
.S0(n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_6 ( .A(N4724), .B(N4723),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_7 ( .A(n2189), .B(N4724),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_1 ( .A(n2116), .B(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .S0(n2163), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ) );
EDFFTRXL \PC_instance/Q_reg[2] ( .RN(\PC_instance/n33 ), .D(N732), .E(n2156), .CK(n1628), .Q(PORT_PC[2]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N774), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[12]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[7] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N771), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[9]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(N772), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[10]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[9] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N773), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[11]) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1692), .B(\ALU_instance/INTERNAL_B[31] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1692), .B(\ALU_instance/INTERNAL_B[31] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1681), .B(\ALU_instance/INTERNAL_B[27] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1651), .B(\ALU_instance/INTERNAL_B[15] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1688), .B(\ALU_instance/INTERNAL_B[19] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1678), .B(\ALU_instance/INTERNAL_B[23] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1681), .B(\ALU_instance/INTERNAL_B[27] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1651), .B(\ALU_instance/INTERNAL_B[15] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1688), .B(\ALU_instance/INTERNAL_B[19] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1678), .B(\ALU_instance/INTERNAL_B[23] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1691), .B(\ALU_instance/INTERNAL_B[30] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1691), .B(\ALU_instance/INTERNAL_B[30] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1680), .B(\ALU_instance/INTERNAL_B[26] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1680), .B(\ALU_instance/INTERNAL_B[26] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1689), .B(\ALU_instance/INTERNAL_B[18] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1689), .B(\ALU_instance/INTERNAL_B[18] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1687), .B(\ALU_instance/INTERNAL_B[22] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1687), .B(\ALU_instance/INTERNAL_B[22] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1677), .B(\ALU_instance/INTERNAL_B[25] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1679), .B(\ALU_instance/INTERNAL_B[17] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1686), .B(\ALU_instance/INTERNAL_B[21] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1682), .B(\ALU_instance/INTERNAL_B[29] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1677), .B(\ALU_instance/INTERNAL_B[25] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1679), .B(\ALU_instance/INTERNAL_B[17] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1686), .B(\ALU_instance/INTERNAL_B[21] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1682), .B(\ALU_instance/INTERNAL_B[29] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[1] ) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N764), .E(n2156), .CK(n1628),
.Q(ID_IMM16_SHL2[2]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[5] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[5]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[5]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[2] ( .RN(\PC_instance/n33 ), .D(
N766), .E(n2156), .CK(n1628), .Q(ID_IMM16_SHL2[4]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[5] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N769), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[7]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[4] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N768), .E(n2156), .CK(n1628),
.Q(ID_IMM16_SHL2[6]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[6] ( .RN(\PC_instance/n33 ), .D(
N770), .E(n2156), .CK(n1628), .Q(ID_IMM16_SHL2[8]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[1] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N765), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[3]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[3] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N767), .E(n2156), .CK(n1628), .Q(
ID_IMM16_SHL2[5]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[0]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[0]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[3] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[3]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[3]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[1] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[1]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[1]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[2] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[2]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[2]) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N265 ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[8][26] ), .B(
\BOOTH_instance/partial_products[2][26] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[6][26] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2120), .B(\ALU_instance/INTERNAL_B[6] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/U1_2 (
.A(N4724), .B(\ALU_instance/INTERNAL_B[6] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[2] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[4][20] ), .B(\BOOTH_instance/decoded[5][20] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[4][20] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[4][18] ), .B(\BOOTH_instance/decoded[5][18] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[4][18] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[4][17] ), .B(\BOOTH_instance/decoded[5][17] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[4][17] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/decoded[4][16] ), .B(\BOOTH_instance/decoded[5][16] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[4][16] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/decoded[2][13] ), .B(\BOOTH_instance/decoded[3][13] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[3][13] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/N218 ), .B(\BOOTH_instance/decoded[1][9] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[10] ), .S(
\BOOTH_instance/partial_products[8][9] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_8 ( .A(
\BOOTH_instance/N217 ), .B(\BOOTH_instance/decoded[1][8] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[8] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[9] ), .S(
\BOOTH_instance/partial_products[8][8] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_4 ( .A(
\BOOTH_instance/N213 ), .B(\BOOTH_instance/decoded[1][4] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[4] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[5] ), .S(
\BOOTH_instance/partial_products[8][4] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/U1_1 (
.A(n2118), .B(\ALU_instance/INTERNAL_B[5] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/U1_1 (
.A(N4719), .B(\ALU_instance/INTERNAL_B[1] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2117), .B(\ALU_instance/INTERNAL_B[5] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2116), .B(\ALU_instance/INTERNAL_B[1] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[1] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_3 ( .A(N4721), .B(n2193),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_4 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_5 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_6 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_7 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_8 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_9 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_10 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_11 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_12 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_13 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ), .S0(n2159), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_14 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ), .S0(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_15 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_10 ( .A(n2183), .B(n2185),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_11 ( .A(n2181), .B(n2183),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_2 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_3 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ), .S0(n1601), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_4 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_5 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/U1_3 (
.A(n2181), .B(\ALU_instance/INTERNAL_B[11] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/U1_3 (
.A(n2181), .B(\ALU_instance/INTERNAL_B[11] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2183), .B(\ALU_instance/INTERNAL_B[10] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/U1_2 (
.A(n2183), .B(\ALU_instance/INTERNAL_B[10] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2177), .B(\ALU_instance/INTERNAL_B[14] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/U1_2 (
.A(n2177), .B(\ALU_instance/INTERNAL_B[14] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/U1_1 (
.A(n2185), .B(\ALU_instance/INTERNAL_B[9] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2185), .B(\ALU_instance/INTERNAL_B[9] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2178), .B(\ALU_instance/INTERNAL_B[13] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/U1_1 (
.A(n2178), .B(\ALU_instance/INTERNAL_B[13] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[1] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N262 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N263 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N264 ) );
XOR3XL \BOOTH_instance/add_0_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/partial_products[7][31] ), .B(
\BOOTH_instance/partial_products[8][31] ), .C(
\BOOTH_instance/add_0_root_add_53_G7/carry[31] ), .Y(EX_MULT_OUT[31])
);
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/U1_3 (
.A(n2189), .B(\ALU_instance/INTERNAL_B[7] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/U1_3 (
.A(n2189), .B(\ALU_instance/INTERNAL_B[7] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[3] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[8][30] ), .B(
\BOOTH_instance/partial_products[2][30] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[6][30] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/partial_products[5][13] ), .B(
\BOOTH_instance/partial_products[6][13] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[8][13] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/decoded[4][11] ), .B(\BOOTH_instance/decoded[5][11] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[4][11] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_7 ( .A(
\BOOTH_instance/decoded[2][7] ), .B(\BOOTH_instance/decoded[3][7] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[7] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[8] ), .S(
\BOOTH_instance/partial_products[7][7] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_5 ( .A(
\BOOTH_instance/partial_products[7][5] ), .B(
\BOOTH_instance/partial_products[8][5] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[5] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[6] ), .S(EX_MULT_OUT[5]) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_3 ( .A(
\BOOTH_instance/N212 ), .B(\BOOTH_instance/decoded[1][3] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[3] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[4] ), .S(EX_MULT_OUT[3]) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[8][29] ), .B(
\BOOTH_instance/partial_products[2][29] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[6][29] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[8][28] ), .B(
\BOOTH_instance/partial_products[2][28] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[6][28] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/partial_products[5][26] ), .B(
\BOOTH_instance/partial_products[6][26] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[8][26] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[8][27] ), .B(
\BOOTH_instance/partial_products[2][27] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[6][27] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][26] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[4][26] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][25] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[4][25] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/partial_products[5][24] ), .B(
\BOOTH_instance/partial_products[6][24] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[8][24] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[8][25] ), .B(
\BOOTH_instance/partial_products[2][25] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[6][25] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[4][24] ), .B(\BOOTH_instance/decoded[5][24] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[4][24] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[8][24] ), .B(
\BOOTH_instance/partial_products[2][24] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[6][24] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2193), .B(\ALU_instance/INTERNAL_B[2] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/U1_2 (
.A(n2193), .B(\ALU_instance/INTERNAL_B[2] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[2] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[4][23] ), .B(\BOOTH_instance/decoded[5][23] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[4][23] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/partial_products[5][22] ), .B(
\BOOTH_instance/partial_products[6][22] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[8][22] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[8][23] ), .B(
\BOOTH_instance/partial_products[2][23] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[6][23] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[4][22] ), .B(\BOOTH_instance/decoded[5][22] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[4][22] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][22] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[3][22] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/partial_products[5][21] ), .B(
\BOOTH_instance/partial_products[6][21] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[8][21] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[8][22] ), .B(
\BOOTH_instance/partial_products[2][22] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[6][22] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[4][21] ), .B(\BOOTH_instance/decoded[5][21] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[4][21] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/partial_products[3][20] ), .B(
\BOOTH_instance/partial_products[4][20] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[7][20] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/partial_products[5][20] ), .B(
\BOOTH_instance/partial_products[6][20] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[8][20] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[8][21] ), .B(
\BOOTH_instance/partial_products[2][21] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[6][21] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[4][19] ), .B(\BOOTH_instance/decoded[5][19] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[4][19] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/partial_products[3][18] ), .B(
\BOOTH_instance/partial_products[4][18] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[7][18] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/partial_products[5][18] ), .B(
\BOOTH_instance/partial_products[6][18] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[8][18] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[8][19] ), .B(
\BOOTH_instance/partial_products[2][19] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[6][19] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/partial_products[3][17] ), .B(
\BOOTH_instance/partial_products[4][17] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[7][17] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[2][18] ), .B(\BOOTH_instance/decoded[3][18] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[3][18] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/partial_products[5][15] ), .B(
\BOOTH_instance/partial_products[6][15] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[8][15] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][17] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[2][17] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/decoded[4][15] ), .B(\BOOTH_instance/decoded[5][15] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[4][15] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/partial_products[3][14] ), .B(
\BOOTH_instance/partial_products[4][14] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[7][14] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/decoded[2][15] ), .B(\BOOTH_instance/decoded[3][15] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[3][15] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/decoded[4][14] ), .B(\BOOTH_instance/decoded[5][14] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[4][14] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/decoded[4][13] ), .B(\BOOTH_instance/decoded[5][13] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[4][13] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/N223 ), .B(\BOOTH_instance/decoded[1][14] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[6][14] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/decoded[4][12] ), .B(\BOOTH_instance/decoded[5][12] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[4][12] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/partial_products[7][10] ), .B(
\BOOTH_instance/partial_products[8][10] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[11] ), .S(EX_MULT_OUT[10])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/partial_products[3][10] ), .B(
\BOOTH_instance/partial_products[4][10] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[11] ), .S(
\BOOTH_instance/partial_products[7][10] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/decoded[2][11] ), .B(\BOOTH_instance/decoded[3][11] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[3][11] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/N220 ), .B(\BOOTH_instance/decoded[1][11] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[8][11] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_8 ( .A(
\BOOTH_instance/partial_products[7][8] ), .B(
\BOOTH_instance/partial_products[8][8] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[8] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[9] ), .S(EX_MULT_OUT[8]) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/decoded[2][9] ), .B(\BOOTH_instance/decoded[3][9] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[10] ), .S(
\BOOTH_instance/partial_products[3][9] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_6 ( .A(
\BOOTH_instance/partial_products[7][6] ), .B(
\BOOTH_instance/partial_products[8][6] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[6] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[7] ), .S(EX_MULT_OUT[6]) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_7 ( .A(
\BOOTH_instance/N216 ), .B(\BOOTH_instance/decoded[1][7] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[7] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[8] ), .S(
\BOOTH_instance/partial_products[8][7] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_6 ( .A(
\BOOTH_instance/N215 ), .B(\BOOTH_instance/decoded[1][6] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[6] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[7] ), .S(
\BOOTH_instance/partial_products[8][6] ) );
XOR3XL \BOOTH_instance/add_3_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/decoded[8][31] ), .B(
\BOOTH_instance/partial_products[2][31] ), .C(
\BOOTH_instance/add_3_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[6][31] ) );
XOR3XL \BOOTH_instance/add_1_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/partial_products[5][31] ), .B(
\BOOTH_instance/partial_products[6][31] ), .C(
\BOOTH_instance/add_1_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[8][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_4 ( .A(n2190), .B(N4721),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_8 ( .A(n2187), .B(n2189),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_9 ( .A(n2185), .B(n2187),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_12 ( .A(n2179), .B(n2181),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_13 ( .A(n2178), .B(n2179),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_14 ( .A(n2177), .B(n2178),
.S0(n2164), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_8 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_9 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_10 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_11 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_12 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_13 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_14 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_15 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ), .S0(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ), .S0(n1602), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_12 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_13 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_14 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_15 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_8 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_9 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_10 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_11 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ), .S0(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_6 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_7 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ), .S0(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][0] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N250 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][1] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N251 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][4] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N254 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][2] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N252 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][3] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N253 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][5] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N255 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][6] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N256 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][7] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N257 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N258 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N259 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N260 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N261 ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/U1_3 (
.A(N4721), .B(\ALU_instance/INTERNAL_B[3] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/U1_3 (
.A(N4721), .B(\ALU_instance/INTERNAL_B[3] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[3] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/partial_products[5][30] ), .B(
\BOOTH_instance/partial_products[6][30] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[8][30] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[4][30] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/partial_products[5][29] ), .B(
\BOOTH_instance/partial_products[6][29] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[8][29] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[4][29] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/partial_products[5][28] ), .B(
\BOOTH_instance/partial_products[6][28] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[8][28] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[4][28] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/partial_products[5][27] ), .B(
\BOOTH_instance/partial_products[6][27] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[8][27] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[4][27] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/partial_products[3][26] ), .B(
\BOOTH_instance/partial_products[4][26] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[7][26] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/partial_products[3][25] ), .B(
\BOOTH_instance/partial_products[4][25] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[7][25] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/partial_products[5][25] ), .B(
\BOOTH_instance/partial_products[6][25] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[8][25] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/partial_products[3][24] ), .B(
\BOOTH_instance/partial_products[4][24] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[7][24] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/partial_products[3][23] ), .B(
\BOOTH_instance/partial_products[4][23] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[7][23] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/partial_products[5][23] ), .B(
\BOOTH_instance/partial_products[6][23] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[8][23] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/partial_products[3][22] ), .B(
\BOOTH_instance/partial_products[4][22] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[7][22] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/partial_products[7][21] ), .B(
\BOOTH_instance/partial_products[8][21] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[22] ), .S(EX_MULT_OUT[21])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/partial_products[7][19] ), .B(
\BOOTH_instance/partial_products[8][19] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[20] ), .S(EX_MULT_OUT[19])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/partial_products[7][17] ), .B(
\BOOTH_instance/partial_products[8][17] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[18] ), .S(EX_MULT_OUT[17])
);
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/partial_products[5][16] ), .B(
\BOOTH_instance/partial_products[6][16] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[8][16] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/partial_products[3][15] ), .B(
\BOOTH_instance/partial_products[4][15] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[7][15] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/partial_products[7][14] ), .B(
\BOOTH_instance/partial_products[8][14] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[15] ), .S(EX_MULT_OUT[14])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/partial_products[7][11] ), .B(
\BOOTH_instance/partial_products[8][11] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[12] ), .S(EX_MULT_OUT[11])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/partial_products[3][11] ), .B(
\BOOTH_instance/partial_products[4][11] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[7][11] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_7 ( .A(
\BOOTH_instance/partial_products[7][7] ), .B(
\BOOTH_instance/partial_products[8][7] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[7] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[8] ), .S(EX_MULT_OUT[7]) );
XOR3XL \BOOTH_instance/add_6_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.C(\BOOTH_instance/add_6_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[3][31] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/partial_products[3][30] ), .B(
\BOOTH_instance/partial_products[4][30] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[7][30] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[2][30] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[2][29] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/partial_products[7][25] ), .B(
\BOOTH_instance/partial_products[8][25] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[26] ), .S(EX_MULT_OUT[25])
);
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[2][28] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[2][27] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/partial_products[7][23] ), .B(
\BOOTH_instance/partial_products[8][23] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[24] ), .S(EX_MULT_OUT[23])
);
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[2][26] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[2][25] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[2][24] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[2][23] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[2][22] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[2][20] ) );
XOR3XL \BOOTH_instance/add_7_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.C(\BOOTH_instance/add_7_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[2][31] ) );
ADDFHX1 \BOOTH_instance/add_3_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[8][17] ), .B(
\BOOTH_instance/partial_products[2][17] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[6][17] ) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[29] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4889), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[29]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[30] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4890), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[30]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4891), .E(1'b1), .CK(CLOCK), .Q(
PORT_ALU[31]) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/decoded[2][12] ), .B(\BOOTH_instance/decoded[3][12] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[3][12] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_8 ( .A(
\BOOTH_instance/decoded[2][8] ), .B(\BOOTH_instance/decoded[3][8] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[8] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[9] ), .S(
\BOOTH_instance/partial_products[3][8] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/partial_products[7][12] ), .B(
\BOOTH_instance/partial_products[8][12] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[13] ), .S(EX_MULT_OUT[12])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/partial_products[3][12] ), .B(
\BOOTH_instance/partial_products[4][12] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[7][12] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/partial_products[7][9] ), .B(
\BOOTH_instance/partial_products[8][9] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[10] ), .S(EX_MULT_OUT[9])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/partial_products[3][16] ), .B(
\BOOTH_instance/partial_products[4][16] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[7][16] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/partial_products[5][14] ), .B(
\BOOTH_instance/partial_products[6][14] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[8][14] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[2][20] ), .B(\BOOTH_instance/decoded[3][20] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[3][20] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/partial_products[7][15] ), .B(
\BOOTH_instance/partial_products[8][15] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[16] ), .S(EX_MULT_OUT[15])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/partial_products[3][21] ), .B(
\BOOTH_instance/partial_products[4][21] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[7][21] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/partial_products[7][16] ), .B(
\BOOTH_instance/partial_products[8][16] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[17] ), .S(EX_MULT_OUT[16])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/partial_products[7][18] ), .B(
\BOOTH_instance/partial_products[8][18] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[19] ), .S(EX_MULT_OUT[18])
);
ADDFHX1 \BOOTH_instance/add_0_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/partial_products[7][27] ), .B(
\BOOTH_instance/partial_products[8][27] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[28] ), .S(EX_MULT_OUT[27])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/partial_products[3][29] ), .B(
\BOOTH_instance/partial_products[4][29] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[7][29] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/partial_products[7][28] ), .B(
\BOOTH_instance/partial_products[8][28] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[29] ), .S(EX_MULT_OUT[28])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/partial_products[3][27] ), .B(
\BOOTH_instance/partial_products[4][27] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[7][27] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/partial_products[3][28] ), .B(
\BOOTH_instance/partial_products[4][28] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[7][28] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/partial_products[7][29] ), .B(
\BOOTH_instance/partial_products[8][29] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[30] ), .S(EX_MULT_OUT[29])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/partial_products[3][9] ), .B(
\BOOTH_instance/partial_products[4][9] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[10] ), .S(
\BOOTH_instance/partial_products[7][9] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/partial_products[7][13] ), .B(
\BOOTH_instance/partial_products[8][13] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[14] ), .S(EX_MULT_OUT[13])
);
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/decoded[2][16] ), .B(\BOOTH_instance/decoded[3][16] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[3][16] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/decoded[2][14] ), .B(\BOOTH_instance/decoded[3][14] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[3][14] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[2][17] ), .B(\BOOTH_instance/decoded[3][17] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[3][17] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/decoded[2][10] ), .B(\BOOTH_instance/decoded[3][10] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[11] ), .S(
\BOOTH_instance/partial_products[3][10] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/partial_products[3][13] ), .B(
\BOOTH_instance/partial_products[4][13] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[7][13] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[2][19] ), .B(\BOOTH_instance/decoded[3][19] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[3][19] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/partial_products[3][19] ), .B(
\BOOTH_instance/partial_products[4][19] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[7][19] ) );
SNPS_CLOCK_GATE_HIGH_DLX_0 \clk_gate_IF_ID_INSTR_REG_instance/Q_reg ( .CLK(
CLOCK), .EN(n1626), .ENCLK(n1628), .TE(1'b0) );
DFFRQXL \IF_STALL_REG_instance/Q_reg ( .D(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .CK(CLOCK), .RN(1'b1), .Q(
IF_STALL_SEL) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[31] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(EX_INSTR[31]), .E(1'b1), .CK(CLOCK),
.Q(MEM_INSTR[31]), .QN(n1409) );
EDFFTRXL \PC_instance/Q_reg[5] ( .RN(\PC_instance/n33 ), .D(N735), .E(n697),
.CK(n1628), .Q(PORT_PC[5]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[26] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[26]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[26]), .QN(n1613) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[30] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[30]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[30]), .QN(n1611) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[29] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[29]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[29]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[28] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[28]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[28]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[27] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[27]), .E(1'b1),
.CK(CLOCK), .Q(EX_INSTR[27]) );
EDFFXL \ID_EX_INSTR_REG_instance/Q_reg[31] ( .D(n1624), .E(1'b1), .CK(CLOCK), .Q(EX_INSTR[31]), .QN(n1566) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/partial_products[7][20] ), .B(
\BOOTH_instance/partial_products[8][20] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[21] ), .S(EX_MULT_OUT[20])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/partial_products[7][22] ), .B(
\BOOTH_instance/partial_products[8][22] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[23] ), .S(EX_MULT_OUT[22])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/partial_products[7][24] ), .B(
\BOOTH_instance/partial_products[8][24] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[25] ), .S(EX_MULT_OUT[24])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/partial_products[7][26] ), .B(
\BOOTH_instance/partial_products[8][26] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[27] ), .S(EX_MULT_OUT[26])
);
ADDFHX1 \BOOTH_instance/add_0_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/partial_products[7][30] ), .B(
\BOOTH_instance/partial_products[8][30] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[31] ), .S(EX_MULT_OUT[30])
);
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/partial_products[5][17] ), .B(
\BOOTH_instance/partial_products[6][17] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[8][17] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/partial_products[5][19] ), .B(
\BOOTH_instance/partial_products[6][19] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[8][19] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[3][30] ) );
ADDFHX1 \BOOTH_instance/add_7_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/N222 ), .B(\BOOTH_instance/decoded[1][13] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[6][13] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/N224 ), .B(\BOOTH_instance/decoded[1][15] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[6][15] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[8][20] ), .B(
\BOOTH_instance/partial_products[2][20] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[6][20] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][21] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[3][21] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[3][23] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[3][24] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[3][25] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[3][26] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[3][27] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[3][28] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[3][29] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][18] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[2][18] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[2][21] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[2][19] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_5 ( .A(
\BOOTH_instance/N214 ), .B(\BOOTH_instance/decoded[1][5] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[5] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[6] ), .S(
\BOOTH_instance/partial_products[8][5] ) );
ADDFHX1 \BOOTH_instance/add_7_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/N219 ), .B(\BOOTH_instance/decoded[1][10] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[11] ), .S(
\BOOTH_instance/partial_products[8][10] ) );
ADDFHX1 \BOOTH_instance/add_7_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/N221 ), .B(\BOOTH_instance/decoded[1][12] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[6][12] ) );
ADDFHX1 \BOOTH_instance/add_7_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/N225 ), .B(\BOOTH_instance/decoded[1][16] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[2][16] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[8][18] ), .B(
\BOOTH_instance/partial_products[2][18] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[6][18] ) );
INVX1 U1339 ( .A(n1699), .Y(\BOOTH_instance/n425 ) );
CLKINVX1 U1340 ( .A(N4721), .Y(n2192) );
CLKINVX1 U1341 ( .A(n2112), .Y(\BOOTH_instance/n316 ) );
INVX3 U1342 ( .A(n2166), .Y(n2163) );
CLKINVX2 U1343 ( .A(n688), .Y(n2166) );
OAI222XL U1344 ( .A0(\BOOTH_instance/n308 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .B0(\BOOTH_instance/n290 ),
.B1(\BOOTH_instance/n445 ), .C0(n1647), .C1(\BOOTH_instance/n447 ),
.Y(\BOOTH_instance/N211 ) );
OAI222X1 U1345 ( .A0(\BOOTH_instance/n299 ), .A1(n2128), .B0(
\BOOTH_instance/n269 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N214 ) );
CLKNAND2X4 U1346 ( .A(n2163), .B(n1593), .Y(\BOOTH_instance/n447 ) );
INVXL U1347 ( .A(n1610), .Y(n1591) );
INVXL U1348 ( .A(n1591), .Y(n1592) );
INVX2 U1349 ( .A(n1591), .Y(n1593) );
NAND3X1 U1350 ( .A(n2159), .B(n2176), .C(n690), .Y(\BOOTH_instance/n434 ) );
INVX1 U1351 ( .A(\BOOTH_instance/n434 ), .Y(\BOOTH_instance/n424 ) );
XOR2X1 U1352 ( .A(N4723), .B(\BOOTH_instance/n457 ), .Y(
\BOOTH_instance/n269 ) );
AND4X1 U1353 ( .A(n1570), .B(n1377), .C(n1571), .D(n1572), .Y(n1594) );
NOR2XL U1354 ( .A(n2162), .B(n2174), .Y(n1595) );
NAND2XL U1355 ( .A(n2163), .B(n2158), .Y(\BOOTH_instance/n445 ) );
INVX1 U1356 ( .A(n1647), .Y(n2193) );
AND2X1 U1357 ( .A(n1635), .B(n1636), .Y(n1647) );
AO22X1 U1358 ( .A0(EX_PC[3]), .A1(n2142), .B0(EX_REGA[3]), .B1(n2140), .Y(
N4721) );
XOR2X1 U1359 ( .A(\BOOTH_instance/n459 ), .B(n2191), .Y(
\BOOTH_instance/n299 ) );
CLKINVX2 U1360 ( .A(n1593), .Y(n1601) );
INVXL U1361 ( .A(\BOOTH_instance/n269 ), .Y(n1596) );
AND2XL U1362 ( .A(\BOOTH_instance/decoded[2][6] ), .B(
\BOOTH_instance/decoded[3][6] ), .Y(
\BOOTH_instance/add_6_root_add_53_G7/carry[7] ) );
NAND2XL U1363 ( .A(n2192), .B(\BOOTH_instance/n460 ), .Y(n1634) );
XNOR2XL U1364 ( .A(N4831), .B(n2176), .Y(\BOOTH_instance/n419 ) );
NAND2XL U1365 ( .A(n2174), .B(\BOOTH_instance/n443 ), .Y(
\BOOTH_instance/n422 ) );
NAND2XL U1366 ( .A(n1630), .B(n1631), .Y(\BOOTH_instance/n405 ) );
OAI221XL U1367 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n421 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n432 ), .Y(\BOOTH_instance/decoded[1][3] ) );
AO22XL U1368 ( .A0(EX_PC[1]), .A1(n2142), .B0(EX_REGA[1]), .B1(n2140), .Y(
n2115) );
NOR2XL U1369 ( .A(n1602), .B(n2174), .Y(n1597) );
NOR2XL U1370 ( .A(n2162), .B(n2174), .Y(n1598) );
NOR2XL U1371 ( .A(EX_ALU_SEL[0]), .B(EX_ALU_SEL[1]), .Y(n1599) );
AOI21BXL U1372 ( .A0(EX_IMM16_EXT[3]), .A1(n2153), .B0N(n1352), .Y(n1600) );
AO2B2XL U1373 ( .B0(EX_REGB[2]), .B1(n1189), .A0(n2153), .A1N(n1663), .Y(
n690) );
OR2XL U1374 ( .A(\BOOTH_instance/n398 ), .B(\BOOTH_instance/n290 ), .Y(n1631) );
OAI222X2 U1375 ( .A0(\BOOTH_instance/n290 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .B0(\BOOTH_instance/n280 ),
.B1(\BOOTH_instance/n445 ), .C0(n2192), .C1(\BOOTH_instance/n447 ),
.Y(\BOOTH_instance/N212 ) );
OAI222XL U1376 ( .A0(\BOOTH_instance/n280 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .B0(\BOOTH_instance/n299 ),
.B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .C0(n2191), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N213 ) );
OAI222XL U1377 ( .A0(\BOOTH_instance/n269 ), .A1(n2127), .B0(
\BOOTH_instance/n259 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(\BOOTH_instance/n260 ), .C1(\BOOTH_instance/n447 ), .Y(
\BOOTH_instance/N215 ) );
CLKINVX1 U1378 ( .A(n2145), .Y(n2144) );
CLKINVX1 U1379 ( .A(n1351), .Y(n2145) );
INVXL U1380 ( .A(n1592), .Y(n2159) );
INVXL U1381 ( .A(n2162), .Y(n1602) );
CLKINVX1 U1382 ( .A(n2162), .Y(n2160) );
NAND2BXL U1383 ( .AN(n2163), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ) );
NOR2XL U1384 ( .A(n1611), .B(n1629), .Y(n1584) );
XOR2XL U1385 ( .A(\BOOTH_instance/n458 ), .B(\BOOTH_instance/n260 ), .Y(
\BOOTH_instance/n259 ) );
AND4XL U1386 ( .A(n1545), .B(n1541), .C(n1543), .D(n1538), .Y(n1551) );
NOR2XL U1387 ( .A(n1566), .B(n1613), .Y(n1573) );
NOR2XL U1388 ( .A(n1612), .B(EX_INSTR[27]), .Y(n1563) );
INVXL U1389 ( .A(N4728), .Y(n2184) );
AO22XL U1390 ( .A0(EX_PC[6]), .A1(n2142), .B0(EX_REGA[6]), .B1(n2140), .Y(
N4724) );
CLKBUFX1 U1391 ( .A(n1189), .Y(n2152) );
AO22XL U1392 ( .A0(EX_PC[5]), .A1(n2142), .B0(EX_REGA[5]), .B1(n2140), .Y(
N4723) );
NAND2XL U1393 ( .A(\BOOTH_instance/n419 ), .B(\BOOTH_instance/n396 ), .Y(
\BOOTH_instance/n397 ) );
NAND2XL U1394 ( .A(N4832), .B(\BOOTH_instance/n419 ), .Y(
\BOOTH_instance/n398 ) );
AO22XL U1395 ( .A0(EX_PC[1]), .A1(n2142), .B0(EX_REGA[1]), .B1(n2140), .Y(
n2116) );
AO22XL U1396 ( .A0(EX_PC[1]), .A1(n2142), .B0(EX_REGA[1]), .B1(n2140), .Y(
N4719) );
AO22XL U1397 ( .A0(EX_IMM16_EXT[30]), .A1(n2153), .B0(EX_REGB[30]), .B1(
n2151), .Y(N4857) );
AO22XL U1398 ( .A0(EX_IMM16_EXT[29]), .A1(n2153), .B0(EX_REGB[29]), .B1(
n2151), .Y(N4856) );
AO22XL U1399 ( .A0(EX_IMM16_EXT[28]), .A1(n2153), .B0(EX_REGB[28]), .B1(
n2151), .Y(N4855) );
AO22XL U1400 ( .A0(EX_IMM16_EXT[27]), .A1(n2153), .B0(EX_REGB[27]), .B1(
n2151), .Y(N4854) );
AO22XL U1401 ( .A0(EX_IMM16_EXT[26]), .A1(n2153), .B0(EX_REGB[26]), .B1(
n2151), .Y(N4853) );
AO22XL U1402 ( .A0(EX_IMM16_EXT[25]), .A1(n2153), .B0(EX_REGB[25]), .B1(
n2151), .Y(N4852) );
AO22XL U1403 ( .A0(EX_IMM16_EXT[24]), .A1(n2153), .B0(EX_REGB[24]), .B1(
n2151), .Y(N4851) );
AO22XL U1404 ( .A0(EX_IMM16_EXT[23]), .A1(n2153), .B0(EX_REGB[23]), .B1(
n2151), .Y(N4850) );
AO22XL U1405 ( .A0(EX_IMM16_EXT[22]), .A1(n2153), .B0(EX_REGB[22]), .B1(
n2151), .Y(N4849) );
NAND2BXL U1406 ( .AN(n2156), .B(\PC_instance/n33 ), .Y(n1626) );
NOR2BXL U1407 ( .AN(\ID_EX_INSTR_REG_instance/n34 ), .B(n1623), .Y(n1624) );
INVXL U1408 ( .A(ID_INSTR_AFTER_CU[31]), .Y(n1623) );
AOI221XL U1409 ( .A0(N4719), .A1(\BOOTH_instance/n400 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n401 ), .C0(
\BOOTH_instance/n405 ), .Y(\BOOTH_instance/n404 ) );
NAND2XL U1410 ( .A(N4840), .B(\BOOTH_instance/n322 ), .Y(n1606) );
AOI22XL U1411 ( .A0(EX_PC[7]), .A1(n2142), .B0(EX_REGA[7]), .B1(n2140), .Y(
n1607) );
AOI22XL U1412 ( .A0(EX_PC[13]), .A1(n2143), .B0(EX_REGA[13]), .B1(n2141),
.Y(n1608) );
OAI21XL U1413 ( .A0(\BOOTH_instance/n448 ), .A1(\BOOTH_instance/n156 ), .B0(
\BOOTH_instance/n151 ), .Y(n1609) );
AOI22XL U1414 ( .A0(EX_IMM16_EXT[1]), .A1(n2153), .B0(EX_REGB[1]), .B1(n1189), .Y(n1610) );
OR2XL U1415 ( .A(EX_INSTR[30]), .B(EX_INSTR[29]), .Y(n1612) );
INVXL U1416 ( .A(n1698), .Y(\BOOTH_instance/n401 ) );
INVXL U1417 ( .A(n1708), .Y(n1374) );
NOR2XL U1418 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n88 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n89 ), .Y(n1614) );
NOR2XL U1419 ( .A(EX_SHIFTER_CW[1]), .B(\ALU_instance/SHIFTER_GENERIC_I/n88 ), .Y(n1615) );
NOR2XL U1420 ( .A(EX_SHIFTER_CW[1]), .B(EX_SHIFTER_CW[0]), .Y(n1616) );
INVXL U1421 ( .A(n2168), .Y(n2167) );
AO22XL U1422 ( .A0(EX_PC[5]), .A1(n2142), .B0(EX_REGA[5]), .B1(n2140), .Y(
n2117) );
AO22XL U1423 ( .A0(EX_PC[6]), .A1(n2142), .B0(EX_REGA[6]), .B1(n2140), .Y(
n2119) );
NOR2XL U1424 ( .A(n1309), .B(n1310), .Y(n1617) );
NAND3XL U1425 ( .A(n320), .B(n319), .C(n321), .Y(n1618) );
NOR2XL U1426 ( .A(n2149), .B(n1330), .Y(n1619) );
XOR2XL U1431 ( .A(n2193), .B(\BOOTH_instance/n461 ), .Y(
\BOOTH_instance/n290 ) );
NAND2XL U1432 ( .A(n1566), .B(EX_INSTR[26]), .Y(n1629) );
OR2XL U1433 ( .A(\BOOTH_instance/n397 ), .B(n1647), .Y(n1630) );
XNOR3XL U1434 ( .A(\BOOTH_instance/partial_products[3][31] ), .B(n1640), .C(
\BOOTH_instance/add_2_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[7][31] ) );
OAI221XL U1435 ( .A0(n2192), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n403 ), .Y(\BOOTH_instance/decoded[2][7] ) );
INVXL U1436 ( .A(n1568), .Y(n1399) );
OAI2BB2XL U1437 ( .B0(n2171), .B1(\ALU_instance/LOGIC_GENERIC_I/n49 ), .A0N(
N4831), .A1N(n1642), .Y(\ALU_instance/LOGIC_OUT[4] ) );
NOR2XL U1438 ( .A(n1398), .B(EX_INSTR[28]), .Y(n1581) );
NAND3XL U1439 ( .A(n1397), .B(EX_INSTR[27]), .C(n1399), .Y(n1525) );
NOR2XL U1440 ( .A(n1576), .B(EX_INSTR[27]), .Y(n1580) );
INVXL U1441 ( .A(EX_INSTR[27]), .Y(n1398) );
NAND2XL U1442 ( .A(\BOOTH_instance/n443 ), .B(n1600), .Y(
\BOOTH_instance/n421 ) );
INVXL U1443 ( .A(n2162), .Y(n2161) );
NOR3XL U1444 ( .A(n2116), .B(n2193), .C(n2112), .Y(\BOOTH_instance/n460 ) );
CLKBUFX1 U1445 ( .A(n1355), .Y(n2140) );
CLKBUFX1 U1446 ( .A(n1355), .Y(n2141) );
INVX4 U1447 ( .A(n1594), .Y(n2153) );
AOI211XL U1448 ( .A0(n1547), .A1(n1563), .B0(n2153), .C0(n1564), .Y(n1353)
);
AOI22XL U1449 ( .A0(\BOOTH_instance/n400 ), .A1(N4721), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n402 ) );
NOR2XL U1450 ( .A(n2153), .B(n1353), .Y(n1189) );
AO22XL U1451 ( .A0(EX_PC[16]), .A1(n2143), .B0(EX_REGA[16]), .B1(n2141), .Y(
n1684) );
AO22XL U1452 ( .A0(EX_PC[22]), .A1(n2143), .B0(EX_REGA[22]), .B1(n2141), .Y(
n1687) );
AO22XL U1453 ( .A0(EX_PC[17]), .A1(n2143), .B0(EX_REGA[17]), .B1(n2141), .Y(
n1679) );
AO22XL U1454 ( .A0(EX_PC[23]), .A1(n2143), .B0(EX_REGA[23]), .B1(n2141), .Y(
n1678) );
AO22XL U1455 ( .A0(EX_PC[21]), .A1(n2143), .B0(EX_REGA[21]), .B1(n2141), .Y(
n1686) );
AO22XL U1456 ( .A0(EX_PC[20]), .A1(n2143), .B0(EX_REGA[20]), .B1(n2141), .Y(
n1683) );
AO22XL U1457 ( .A0(EX_PC[18]), .A1(n2143), .B0(EX_REGA[18]), .B1(n2141), .Y(
n1689) );
AO22XL U1458 ( .A0(EX_PC[19]), .A1(n2143), .B0(EX_REGA[19]), .B1(n2141), .Y(
n1688) );
NAND2XL U1459 ( .A(n1633), .B(n1634), .Y(\BOOTH_instance/n280 ) );
INVXL U1460 ( .A(n1593), .Y(n2158) );
NAND2XL U1461 ( .A(N4721), .B(n1632), .Y(n1633) );
INVXL U1462 ( .A(\BOOTH_instance/n460 ), .Y(n1632) );
NAND2XL U1463 ( .A(EX_PC[2]), .B(n2142), .Y(n1635) );
NAND2XL U1464 ( .A(EX_REGA[2]), .B(n2140), .Y(n1636) );
INVXL U1465 ( .A(\BOOTH_instance/n408 ), .Y(\BOOTH_instance/n400 ) );
NOR2XL U1466 ( .A(\BOOTH_instance/n459 ), .B(n2190), .Y(
\BOOTH_instance/n457 ) );
INVXL U1467 ( .A(n1355), .Y(n2142) );
AOI22XL U1468 ( .A0(\BOOTH_instance/n400 ), .A1(n2193), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n403 ) );
CLKBUFX1 U1469 ( .A(n2152), .Y(n2151) );
INVXL U1470 ( .A(n1600), .Y(n2174) );
NAND3XL U1471 ( .A(n2174), .B(\BOOTH_instance/n396 ), .C(n2167), .Y(
\BOOTH_instance/n408 ) );
INVXL U1472 ( .A(\BOOTH_instance/n320 ), .Y(\BOOTH_instance/n308 ) );
OR2XL U1473 ( .A(n2163), .B(n2159), .Y(n1643) );
AO22XL U1474 ( .A0(n2195), .A1(n2191), .B0(n2190), .B1(EX_LOGIC_CW[3]), .Y(
n1642) );
XNOR2XL U1475 ( .A(n2115), .B(\BOOTH_instance/n316 ), .Y(
\BOOTH_instance/n320 ) );
NOR2XL U1476 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N202 ), .B(n2115), .Y(
\BOOTH_instance/n461 ) );
NOR2XL U1477 ( .A(n1565), .B(n1613), .Y(n1397) );
AOI211XL U1478 ( .A0(n1569), .A1(n1573), .B0(n1574), .C0(n1558), .Y(n1572)
);
INVXL U1479 ( .A(N4832), .Y(\BOOTH_instance/n396 ) );
INVXL U1480 ( .A(n1535), .Y(n1570) );
INVXL U1481 ( .A(N4722), .Y(n2191) );
CLKBUFX1 U1482 ( .A(n1600), .Y(n2176) );
AO22XL U1483 ( .A0(EX_PC[5]), .A1(n2142), .B0(EX_REGA[5]), .B1(n2140), .Y(
n2118) );
AO22XL U1484 ( .A0(EX_PC[6]), .A1(n2142), .B0(EX_REGA[6]), .B1(n2140), .Y(
n2120) );
AO22XL U1485 ( .A0(EX_PC[0]), .A1(n2142), .B0(EX_REGA[0]), .B1(n2140), .Y(
n2112) );
NOR2XL U1486 ( .A(EX_INSTR[28]), .B(EX_INSTR[26]), .Y(n1577) );
AO22XL U1487 ( .A0(EX_PC[0]), .A1(n2142), .B0(EX_REGA[0]), .B1(n2140), .Y(
n2111) );
AO22XL U1488 ( .A0(EX_PC[0]), .A1(n2142), .B0(EX_REGA[0]), .B1(n2140), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N202 ) );
XOR2XL U1489 ( .A(n2187), .B(\BOOTH_instance/n455 ), .Y(
\BOOTH_instance/n239 ) );
XOR2XL U1490 ( .A(n2181), .B(\BOOTH_instance/n452 ), .Y(
\BOOTH_instance/n209 ) );
XOR2XL U1491 ( .A(n2178), .B(\BOOTH_instance/n449 ), .Y(
\BOOTH_instance/n189 ) );
INVXL U1492 ( .A(n2173), .Y(n2171) );
INVXL U1493 ( .A(\BOOTH_instance/n151 ), .Y(\BOOTH_instance/n157 ) );
CLKINVX2 U1494 ( .A(n1695), .Y(\BOOTH_instance/decoded[1][31] ) );
XNOR3XL U1495 ( .A(\BOOTH_instance/decoded[4][31] ), .B(
\BOOTH_instance/decoded[5][31] ), .C(
\BOOTH_instance/add_5_root_add_53_G7/carry[31] ), .Y(n1640) );
CLKINVX1 U1496 ( .A(n1696), .Y(\BOOTH_instance/decoded[0][31] ) );
INVXL U1497 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ) );
INVXL U1498 ( .A(n1697), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ) );
INVXL U1499 ( .A(n2173), .Y(n2169) );
INVXL U1500 ( .A(n2172), .Y(n2170) );
XOR2XL U1501 ( .A(\BOOTH_instance/n450 ), .B(n1670), .Y(
\BOOTH_instance/n177 ) );
XOR2XL U1502 ( .A(\BOOTH_instance/n456 ), .B(n1607), .Y(
\BOOTH_instance/n249 ) );
XOR2XL U1503 ( .A(\BOOTH_instance/n453 ), .B(n2186), .Y(
\BOOTH_instance/n229 ) );
XOR2XL U1504 ( .A(\BOOTH_instance/n451 ), .B(n2180), .Y(
\BOOTH_instance/n199 ) );
XOR2XL U1505 ( .A(n2183), .B(\BOOTH_instance/n454 ), .Y(
\BOOTH_instance/n219 ) );
NAND2XL U1506 ( .A(\BOOTH_instance/n317 ), .B(\BOOTH_instance/n315 ), .Y(
\BOOTH_instance/n166 ) );
CLKINVX1 U1507 ( .A(n1608), .Y(n2178) );
INVXL U1508 ( .A(\BOOTH_instance/n155 ), .Y(\BOOTH_instance/n168 ) );
NAND2XL U1509 ( .A(\BOOTH_instance/n448 ), .B(\BOOTH_instance/n156 ), .Y(
\BOOTH_instance/n151 ) );
AO2B2XL U1510 ( .B0(EX_ALU_OUT[0]), .B1(n2144), .A0(n2145), .A1N(n1641), .Y(
N4860) );
AO21XL U1511 ( .A0(n2129), .A1(\BOOTH_instance/n447 ), .B0(
\BOOTH_instance/n316 ), .Y(n1641) );
AOI21XL U1512 ( .A0(n1706), .A1(\BOOTH_instance/n350 ), .B0(
\BOOTH_instance/n157 ), .Y(\BOOTH_instance/decoded[4][31] ) );
CLKINVX1 U1513 ( .A(n1670), .Y(n2177) );
INVXL U1514 ( .A(EX_ADD_SUB), .Y(n2137) );
XOR2XL U1515 ( .A(n2135), .B(n2174), .Y(\ALU_instance/INTERNAL_B[3] ) );
AOI21XL U1516 ( .A0(\BOOTH_instance/n323 ), .A1(n1703), .B0(
\BOOTH_instance/n157 ), .Y(\BOOTH_instance/decoded[5][31] ) );
INVXL U1517 ( .A(n1700), .Y(\BOOTH_instance/decoded[3][31] ) );
INVXL U1518 ( .A(n1701), .Y(\BOOTH_instance/decoded[2][31] ) );
NAND2XL U1519 ( .A(n2163), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ) );
NAND2XL U1520 ( .A(n2159), .B(n2165), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ) );
NOR2BXL U1521 ( .AN(n2175), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ) );
NOR2XL U1522 ( .A(n2176), .B(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ) );
AND2XL U1523 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ), .B(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ) );
AND2XL U1524 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ), .B(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ) );
AND2XL U1525 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ), .B(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ) );
NOR2XL U1526 ( .A(n2166), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ) );
NOR2XL U1527 ( .A(n2163), .B(n2159), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ) );
NOR2XL U1528 ( .A(n2163), .B(n2159), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ) );
NAND2XL U1529 ( .A(n2163), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ) );
NAND2XL U1530 ( .A(n2159), .B(n2163), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ) );
NOR2BXL U1531 ( .AN(n2163), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ) );
OR2XL U1532 ( .A(n2166), .B(n2158), .Y(n1644) );
NAND2XL U1533 ( .A(n2159), .B(n2165), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ) );
AO2B2XL U1534 ( .B0(EX_ALU_OUT[2]), .B1(n2144), .A0(n2145), .A1N(n1645), .Y(
N4862) );
XNOR2XL U1535 ( .A(\BOOTH_instance/decoded[1][2] ), .B(\BOOTH_instance/N211 ), .Y(n1645) );
NOR2XL U1536 ( .A(n1600), .B(n2113), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ) );
NAND2XL U1537 ( .A(n2174), .B(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ) );
CLKBUFX1 U1538 ( .A(n1615), .Y(n2133) );
NOR2XL U1539 ( .A(\ALU_instance/n23 ), .B(EX_ALU_SEL[0]), .Y(
\ALU_instance/n6 ) );
INVXL U1540 ( .A(n1531), .Y(EX_LOGIC_CW[3]) );
NOR3XL U1541 ( .A(n2146), .B(n1227), .C(n2147), .Y(n1646) );
AND2XL U1542 ( .A(EX_ALU_SEL[0]), .B(EX_ALU_SEL[1]), .Y(\ALU_instance/n5 )
);
INVXL U1543 ( .A(n1702), .Y(\ALU_instance/SHIFTER_GENERIC_I/n13 ) );
CLKINVX1 U1544 ( .A(n2184), .Y(n2183) );
OAI221XL U1545 ( .A0(n1647), .A1(\BOOTH_instance/n186 ), .B0(
\BOOTH_instance/n290 ), .B1(n1606), .C0(\BOOTH_instance/n319 ), .Y(
\BOOTH_instance/n305 ) );
NAND2XL U1546 ( .A(n1648), .B(\BOOTH_instance/n348 ), .Y(
\BOOTH_instance/n323 ) );
NAND2XL U1547 ( .A(N4836), .B(\BOOTH_instance/n371 ), .Y(
\BOOTH_instance/n350 ) );
NAND2XL U1548 ( .A(N4834), .B(\BOOTH_instance/n395 ), .Y(
\BOOTH_instance/n374 ) );
NAND2XL U1549 ( .A(N4842), .B(\BOOTH_instance/n317 ), .Y(
\BOOTH_instance/n158 ) );
INVXL U1550 ( .A(n1651), .Y(\BOOTH_instance/n156 ) );
INVXL U1551 ( .A(n2120), .Y(\BOOTH_instance/n260 ) );
NAND3XL U1552 ( .A(N4841), .B(\BOOTH_instance/n315 ), .C(N4840), .Y(
\BOOTH_instance/n155 ) );
INVXL U1553 ( .A(n2116), .Y(\BOOTH_instance/n307 ) );
INVXL U1554 ( .A(N4727), .Y(n2186) );
INVXL U1555 ( .A(N4730), .Y(n2180) );
INVXL U1556 ( .A(N4726), .Y(n2188) );
INVXL U1557 ( .A(N4729), .Y(n2182) );
INVXL U1558 ( .A(N4842), .Y(\BOOTH_instance/n315 ) );
INVXL U1559 ( .A(N4836), .Y(\BOOTH_instance/n346 ) );
INVXL U1560 ( .A(N4840), .Y(\BOOTH_instance/n318 ) );
INVXL U1561 ( .A(n1706), .Y(\BOOTH_instance/n353 ) );
INVXL U1562 ( .A(n1707), .Y(\BOOTH_instance/n377 ) );
INVXL U1563 ( .A(n1704), .Y(\BOOTH_instance/n176 ) );
INVXL U1564 ( .A(n1721), .Y(\BOOTH_instance/n150 ) );
INVXL U1565 ( .A(n1705), .Y(\BOOTH_instance/n326 ) );
INVXL U1566 ( .A(n1703), .Y(\BOOTH_instance/n327 ) );
INVXL U1567 ( .A(EX_ADD_SUB), .Y(n2135) );
INVXL U1568 ( .A(EX_ADD_SUB), .Y(n2136) );
XOR2XL U1569 ( .A(n2137), .B(N4841), .Y(\ALU_instance/INTERNAL_B[14] ) );
XOR2XL U1570 ( .A(n2135), .B(N4833), .Y(\ALU_instance/INTERNAL_B[6] ) );
XOR2XL U1571 ( .A(n2137), .B(n1648), .Y(\ALU_instance/INTERNAL_B[11] ) );
XOR2XL U1572 ( .A(n2137), .B(N4837), .Y(\ALU_instance/INTERNAL_B[10] ) );
XOR2XL U1573 ( .A(n2135), .B(N4836), .Y(\ALU_instance/INTERNAL_B[9] ) );
XOR2XL U1574 ( .A(n2135), .B(N4832), .Y(\ALU_instance/INTERNAL_B[5] ) );
XOR2XL U1575 ( .A(n2135), .B(N4834), .Y(\ALU_instance/INTERNAL_B[7] ) );
XOR2XL U1576 ( .A(n2137), .B(N4840), .Y(\ALU_instance/INTERNAL_B[13] ) );
AOI222XL U1577 ( .A0(n2126), .A1(n2193), .B0(n2116), .B1(n2130), .C0(n2111),
.C1(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ) );
AOI222XL U1578 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .A1(n1682),
.B0(n2125), .B1(n1691), .C0(n2158), .C1(n1692), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ) );
OAI221XL U1579 ( .A0(n2127), .A1(n2192), .B0(n2129), .B1(n1647), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n159 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ) );
OAI221XL U1580 ( .A0(n2127), .A1(n2191), .B0(n2192), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n179 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ) );
OAI221XL U1581 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ),
.B0(n2129), .B1(n2191), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n174 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ) );
AOI222XL U1582 ( .A0(n2125), .A1(n1691), .B0(n2124), .B1(n1692), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .C1(n1682), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ) );
AOI221XL U1583 ( .A0(n2124), .A1(n2177), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1651), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n156 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ) );
AOI221XL U1584 ( .A0(n2124), .A1(n1684), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1679), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n146 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ) );
AOI221XL U1585 ( .A0(n2124), .A1(n1651), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1684), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n128 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ) );
INVXL U1586 ( .A(n690), .Y(n2162) );
INVXL U1587 ( .A(n688), .Y(n2165) );
CLKBUFX1 U1588 ( .A(EX_LOGIC_CW[2]), .Y(n2195) );
CLKBUFX1 U1589 ( .A(EX_LOGIC_CW[2]), .Y(n2194) );
NAND3XL U1590 ( .A(n1533), .B(n1531), .C(n1546), .Y(EX_ALU_SEL[1]) );
NAND2XL U1591 ( .A(n1516), .B(n1517), .Y(n1292) );
INVXL U1592 ( .A(n2121), .Y(n1310) );
INVXL U1593 ( .A(n1618), .Y(n1522) );
CLKBUFX1 U1594 ( .A(n1211), .Y(n2149) );
NOR3XL U1595 ( .A(EX_INSTR[30]), .B(EX_INSTR[31]), .C(n1576), .Y(n1535) );
AO2B2XL U1596 ( .B0(EX_REGB[11]), .B1(n2151), .A0(n2153), .A1N(n1649), .Y(
n1648) );
AO2B2XL U1597 ( .B0(EX_REGA[10]), .B1(n2141), .A0(n2142), .A1N(n1650), .Y(
N4728) );
AO22XL U1598 ( .A0(EX_PC[15]), .A1(n2143), .B0(EX_REGA[15]), .B1(n2141), .Y(
n1651) );
NOR2XL U1599 ( .A(n1611), .B(EX_INSTR[31]), .Y(n1575) );
AO2B2XL U1600 ( .B0(EX_REGB[14]), .B1(n2151), .A0(n2153), .A1N(n1652), .Y(
N4841) );
NAND2XL U1601 ( .A(EX_INSTR[26]), .B(n1356), .Y(n1355) );
AO2B2XL U1602 ( .B0(EX_REGB[6]), .B1(n2152), .A0(n2153), .A1N(n1653), .Y(
N4833) );
AO2B2XL U1603 ( .B0(EX_REGB[12]), .B1(n2151), .A0(n2153), .A1N(n1654), .Y(
N4839) );
AO2B2XL U1604 ( .B0(EX_REGB[8]), .B1(n2152), .A0(n2153), .A1N(n1655), .Y(
N4835) );
AO2B2XL U1605 ( .B0(EX_REGB[10]), .B1(n2151), .A0(n2153), .A1N(n1656), .Y(
N4837) );
AO2B2XL U1606 ( .B0(EX_REGB[9]), .B1(n2152), .A0(n2153), .A1N(n1657), .Y(
N4836) );
AO2B2XL U1607 ( .B0(EX_REGB[5]), .B1(n2152), .A0(n2153), .A1N(n1658), .Y(
N4832) );
AO2B2XL U1608 ( .B0(EX_REGB[7]), .B1(n2152), .A0(n2153), .A1N(n1659), .Y(
N4834) );
AO2B2XL U1609 ( .B0(EX_REGB[15]), .B1(n2151), .A0(n2153), .A1N(n1660), .Y(
N4842) );
AO2B2XL U1610 ( .B0(EX_REGB[13]), .B1(n2151), .A0(n2153), .A1N(n1661), .Y(
N4840) );
AO2B2XL U1611 ( .B0(EX_REGB[0]), .B1(n2152), .A0(n2153), .A1N(n1662), .Y(
n688) );
INVXL U1612 ( .A(EX_INSTR[29]), .Y(n1576) );
INVXL U1613 ( .A(EX_INSTR[28]), .Y(n1565) );
AO2B2XL U1614 ( .B0(EX_REGB[4]), .B1(n1189), .A0(n2153), .A1N(n1664), .Y(
N4831) );
AO2B2XL U1615 ( .B0(EX_REGA[4]), .B1(n2140), .A0(n2142), .A1N(n1665), .Y(
N4722) );
AO2B2XL U1616 ( .B0(EX_REGA[8]), .B1(n2141), .A0(n2142), .A1N(n1666), .Y(
N4726) );
AO2B2XL U1617 ( .B0(EX_REGA[9]), .B1(n2141), .A0(n2142), .A1N(n1667), .Y(
N4727) );
AO2B2XL U1618 ( .B0(EX_REGA[11]), .B1(n2141), .A0(n2142), .A1N(n1668), .Y(
N4729) );
AO2B2XL U1619 ( .B0(EX_REGA[12]), .B1(n2141), .A0(n2142), .A1N(n1669), .Y(
N4730) );
AOI22XL U1620 ( .A0(EX_PC[14]), .A1(n2143), .B0(EX_REGA[14]), .B1(n2141),
.Y(n1670) );
AO2B2XL U1621 ( .B0(EX_REGB[21]), .B1(n2151), .A0(n2153), .A1N(n1671), .Y(
N4848) );
AO2B2XL U1622 ( .B0(EX_REGB[20]), .B1(n2151), .A0(n2153), .A1N(n1672), .Y(
N4847) );
AO2B2XL U1623 ( .B0(EX_REGB[19]), .B1(n2151), .A0(n2153), .A1N(n1673), .Y(
N4846) );
AO2B2XL U1624 ( .B0(EX_REGB[18]), .B1(n2151), .A0(n2153), .A1N(n1674), .Y(
N4845) );
AO2B2XL U1625 ( .B0(EX_REGB[17]), .B1(n2151), .A0(n2153), .A1N(n1675), .Y(
N4844) );
AO2B2XL U1626 ( .B0(EX_REGB[16]), .B1(n2151), .A0(n2153), .A1N(n1676), .Y(
N4843) );
INVXL U1627 ( .A(EX_INSTR[1]), .Y(n1560) );
AO22XL U1628 ( .A0(EX_PC[25]), .A1(n2143), .B0(EX_REGA[25]), .B1(n2141), .Y(
n1677) );
AO22XL U1629 ( .A0(EX_PC[26]), .A1(n2143), .B0(EX_REGA[26]), .B1(n2141), .Y(
n1680) );
AO22XL U1630 ( .A0(EX_PC[27]), .A1(n2143), .B0(EX_REGA[27]), .B1(n2141), .Y(
n1681) );
AO22XL U1631 ( .A0(EX_PC[29]), .A1(n2143), .B0(EX_REGA[29]), .B1(n2141), .Y(
n1682) );
AO22XL U1632 ( .A0(EX_PC[24]), .A1(n2143), .B0(EX_REGA[24]), .B1(n2141), .Y(
n1685) );
AO22XL U1633 ( .A0(EX_PC[28]), .A1(n2143), .B0(EX_REGA[28]), .B1(n2141), .Y(
n1690) );
AO22XL U1634 ( .A0(EX_PC[30]), .A1(n2143), .B0(EX_REGA[30]), .B1(n2141), .Y(
n1691) );
AO22XL U1635 ( .A0(EX_PC[31]), .A1(n2143), .B0(EX_REGA[31]), .B1(n2141), .Y(
n1692) );
AO2B2XL U1636 ( .B0(EX_REGB[31]), .B1(n2152), .A0(n2153), .A1N(n1693), .Y(
\EX_ALU_B[31] ) );
CLKBUFX2 U1637 ( .A(ID_IMM16_SHL2[31]), .Y(n2109) );
NOR4XL U1638 ( .A(ID_INSTR_27), .B(ID_INSTR_29), .C(ID_INSTR_30), .D(
ID_INSTR_31), .Y(n1516) );
NOR3XL U1639 ( .A(n1195), .B(ID_INSTR_28), .C(n1293), .Y(n1226) );
NOR3XL U1640 ( .A(ID_INSTR_29), .B(ID_INSTR_31), .C(n1484), .Y(n1291) );
NAND2XL U1641 ( .A(n1532), .B(n1533), .Y(EX_LOGIC_CW[2]) );
INVXL U1642 ( .A(ID_INSTR_28), .Y(n1290) );
INVXL U1643 ( .A(ID_INSTR_26), .Y(n1518) );
OAI31XL U1644 ( .A0(n1196), .A1(ID_INSTR_27), .A2(n1521), .B0(n1198), .Y(
n1370) );
NAND2XL U1645 ( .A(IF_STALL_SEL), .B(n1618), .Y(n697) );
INVXL U1646 ( .A(ID_INSTR_30), .Y(n1483) );
NOR3BXL U1647 ( .AN(n1436), .B(n1213), .C(MEM_INSTR[28]), .Y(n1435) );
CLKBUFX1 U1648 ( .A(n1342), .Y(n2121) );
NAND4XL U1649 ( .A(n1215), .B(MEM_INSTR[29]), .C(n1444), .D(n1220), .Y(n1216) );
INVXL U1650 ( .A(WB_INSTR_30), .Y(n1340) );
INVXL U1651 ( .A(MEM_INSTR[28]), .Y(n1220) );
INVXL U1652 ( .A(WB_INSTR_29), .Y(n1471) );
INVXL U1653 ( .A(n1822), .Y(WB_SIGN_EXT_16_CONTROL) );
INVXL U1654 ( .A(MEM_INSTR[26]), .Y(n1445) );
INVXL U1655 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ) );
NOR2XL U1656 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n9 ), .B(
\ALU_instance/ZERO ), .Y(\ALU_instance/COMPARATOR_GENERIC_I/n7 ) );
INVXL U1657 ( .A(\BOOTH_instance/n239 ), .Y(\BOOTH_instance/n232 ) );
INVXL U1658 ( .A(\BOOTH_instance/n209 ), .Y(\BOOTH_instance/n202 ) );
INVXL U1659 ( .A(\BOOTH_instance/n189 ), .Y(\BOOTH_instance/n180 ) );
INVXL U1660 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ) );
INVXL U1661 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ) );
INVXL U1662 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n21 ) );
NOR2XL U1663 ( .A(n1697), .B(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ) );
NOR2XL U1664 ( .A(n1697), .B(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ) );
INVXL U1665 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ) );
OAI21XL U1666 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N206 ) );
OAI21XL U1667 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N205 ) );
OAI21XL U1668 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N203 ) );
INVXL U1669 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ) );
OR2XL U1670 ( .A(n1697), .B(n2171), .Y(n1694) );
INVXL U1671 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ) );
INVXL U1672 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ) );
INVXL U1673 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ) );
INVXL U1674 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ) );
NOR4XL U1675 ( .A(\ALU_instance/ADDER_OUT[5] ), .B(
\ALU_instance/ADDER_OUT[4] ), .C(\ALU_instance/ADDER_OUT[3] ), .D(
\ALU_instance/ADDER_OUT[31] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n18 ) );
OAI2BB2XL U1676 ( .B0(\BOOTH_instance/n293 ), .B1(\BOOTH_instance/n294 ),
.A0N(\BOOTH_instance/n295 ), .A1N(\BOOTH_instance/n296 ), .Y(
\BOOTH_instance/n286 ) );
NOR2XL U1677 ( .A(\BOOTH_instance/n296 ), .B(\BOOTH_instance/n295 ), .Y(
\BOOTH_instance/n294 ) );
NOR2XL U1678 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n10 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n11 ), .Y(\ALU_instance/ZERO ) );
NAND4XL U1679 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n12 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n13 ), .C(
\ALU_instance/COMPARATOR_GENERIC_I/n14 ), .D(
\ALU_instance/COMPARATOR_GENERIC_I/n15 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n11 ) );
NAND4XL U1680 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n16 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n17 ), .C(
\ALU_instance/COMPARATOR_GENERIC_I/n18 ), .D(
\ALU_instance/COMPARATOR_GENERIC_I/n19 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n10 ) );
NOR4XL U1681 ( .A(\ALU_instance/ADDER_OUT[12] ), .B(
\ALU_instance/ADDER_OUT[11] ), .C(\ALU_instance/ADDER_OUT[10] ), .D(
\ALU_instance/ADDER_OUT[0] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n12 ) );
NOR2XL U1682 ( .A(\BOOTH_instance/n451 ), .B(n2179), .Y(
\BOOTH_instance/n449 ) );
AO22XL U1683 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ) );
AO22XL U1684 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ) );
NOR2XL U1685 ( .A(\BOOTH_instance/n456 ), .B(n2189), .Y(
\BOOTH_instance/n455 ) );
AOI22XL U1686 ( .A0(\BOOTH_instance/n400 ), .A1(n2190), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n399 ) );
AOI22XL U1687 ( .A0(\BOOTH_instance/n400 ), .A1(n2189), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n416 ) );
AOI22XL U1688 ( .A0(\BOOTH_instance/n400 ), .A1(n2187), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n415 ) );
AOI22XL U1689 ( .A0(\BOOTH_instance/n400 ), .A1(n2185), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n414 ) );
AOI22XL U1690 ( .A0(\BOOTH_instance/n400 ), .A1(n2181), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n412 ) );
AOI22XL U1691 ( .A0(\BOOTH_instance/n400 ), .A1(n2179), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n411 ) );
AOI22XL U1692 ( .A0(\BOOTH_instance/n400 ), .A1(n2178), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n410 ) );
AOI22XL U1693 ( .A0(\BOOTH_instance/n400 ), .A1(n2177), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n409 ) );
AOI21XL U1694 ( .A0(\BOOTH_instance/n422 ), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/decoded[1][2] ) );
AO2B2XL U1695 ( .B0(\BOOTH_instance/n170 ), .B1(\BOOTH_instance/n171 ), .A0(
\BOOTH_instance/n172 ), .A1N(\BOOTH_instance/n173 ), .Y(
\BOOTH_instance/n159 ) );
NOR2XL U1696 ( .A(\BOOTH_instance/n171 ), .B(\BOOTH_instance/n170 ), .Y(
\BOOTH_instance/n173 ) );
AO21XL U1697 ( .A0(\BOOTH_instance/n422 ), .A1(n1699), .B0(
\BOOTH_instance/n157 ), .Y(n1695) );
OAI21XL U1698 ( .A0(\BOOTH_instance/n424 ), .A1(\BOOTH_instance/n425 ), .B0(
n2111), .Y(\BOOTH_instance/n432 ) );
OAI2BB1XL U1699 ( .A0N(\BOOTH_instance/n159 ), .A1N(\BOOTH_instance/n160 ),
.B0(\BOOTH_instance/n161 ), .Y(\BOOTH_instance/n147 ) );
OAI21XL U1700 ( .A0(\BOOTH_instance/n160 ), .A1(\BOOTH_instance/n159 ), .B0(
\BOOTH_instance/n162 ), .Y(\BOOTH_instance/n161 ) );
AO21XL U1701 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .A1(n2127),
.B0(\BOOTH_instance/n157 ), .Y(n1696) );
INVXL U1702 ( .A(\BOOTH_instance/n299 ), .Y(\BOOTH_instance/n272 ) );
INVXL U1703 ( .A(\BOOTH_instance/n177 ), .Y(\BOOTH_instance/n169 ) );
INVXL U1704 ( .A(\BOOTH_instance/n280 ), .Y(\BOOTH_instance/n292 ) );
INVXL U1705 ( .A(\BOOTH_instance/n259 ), .Y(\BOOTH_instance/n252 ) );
INVXL U1706 ( .A(\BOOTH_instance/n199 ), .Y(\BOOTH_instance/n192 ) );
INVXL U1707 ( .A(\BOOTH_instance/n219 ), .Y(\BOOTH_instance/n212 ) );
INVXL U1708 ( .A(\BOOTH_instance/n229 ), .Y(\BOOTH_instance/n222 ) );
INVXL U1709 ( .A(\BOOTH_instance/n249 ), .Y(\BOOTH_instance/n242 ) );
INVXL U1710 ( .A(\BOOTH_instance/n166 ), .Y(\BOOTH_instance/n282 ) );
AO2B2XL U1711 ( .B0(\BOOTH_instance/n223 ), .B1(\BOOTH_instance/n224 ), .A0(
\BOOTH_instance/n225 ), .A1N(\BOOTH_instance/n226 ), .Y(
\BOOTH_instance/n215 ) );
NOR2XL U1712 ( .A(\BOOTH_instance/n224 ), .B(\BOOTH_instance/n223 ), .Y(
\BOOTH_instance/n226 ) );
AO2B2XL U1713 ( .B0(\BOOTH_instance/n203 ), .B1(\BOOTH_instance/n204 ), .A0(
\BOOTH_instance/n205 ), .A1N(\BOOTH_instance/n206 ), .Y(
\BOOTH_instance/n195 ) );
NOR2XL U1714 ( .A(\BOOTH_instance/n204 ), .B(\BOOTH_instance/n203 ), .Y(
\BOOTH_instance/n206 ) );
AO2B2XL U1715 ( .B0(\BOOTH_instance/n193 ), .B1(\BOOTH_instance/n194 ), .A0(
\BOOTH_instance/n195 ), .A1N(\BOOTH_instance/n196 ), .Y(
\BOOTH_instance/n183 ) );
NOR2XL U1716 ( .A(\BOOTH_instance/n194 ), .B(\BOOTH_instance/n193 ), .Y(
\BOOTH_instance/n196 ) );
AO2B2XL U1717 ( .B0(\BOOTH_instance/n181 ), .B1(\BOOTH_instance/n182 ), .A0(
\BOOTH_instance/n183 ), .A1N(\BOOTH_instance/n184 ), .Y(
\BOOTH_instance/n172 ) );
NOR2XL U1718 ( .A(\BOOTH_instance/n182 ), .B(\BOOTH_instance/n181 ), .Y(
\BOOTH_instance/n184 ) );
XNOR2XL U1719 ( .A(\BOOTH_instance/n297 ), .B(\BOOTH_instance/n296 ), .Y(
\BOOTH_instance/partial_products[5][16] ) );
XOR2XL U1720 ( .A(\BOOTH_instance/partial_products[2][16] ), .B(
\BOOTH_instance/decoded[8][16] ), .Y(
\BOOTH_instance/partial_products[6][16] ) );
XOR2XL U1721 ( .A(\BOOTH_instance/n295 ), .B(\BOOTH_instance/n293 ), .Y(
\BOOTH_instance/n297 ) );
XNOR2XL U1722 ( .A(\BOOTH_instance/n227 ), .B(\BOOTH_instance/n224 ), .Y(
\BOOTH_instance/partial_products[5][23] ) );
XNOR2XL U1723 ( .A(\BOOTH_instance/n225 ), .B(\BOOTH_instance/n223 ), .Y(
\BOOTH_instance/n227 ) );
XNOR2XL U1724 ( .A(\BOOTH_instance/n207 ), .B(\BOOTH_instance/n204 ), .Y(
\BOOTH_instance/partial_products[5][25] ) );
XNOR2XL U1725 ( .A(\BOOTH_instance/n205 ), .B(\BOOTH_instance/n203 ), .Y(
\BOOTH_instance/n207 ) );
XNOR2XL U1726 ( .A(\BOOTH_instance/n185 ), .B(\BOOTH_instance/n182 ), .Y(
\BOOTH_instance/partial_products[5][27] ) );
XNOR2XL U1727 ( .A(\BOOTH_instance/n183 ), .B(\BOOTH_instance/n181 ), .Y(
\BOOTH_instance/n185 ) );
XNOR2XL U1728 ( .A(\BOOTH_instance/n174 ), .B(\BOOTH_instance/n171 ), .Y(
\BOOTH_instance/partial_products[5][28] ) );
XNOR2XL U1729 ( .A(\BOOTH_instance/n172 ), .B(\BOOTH_instance/n170 ), .Y(
\BOOTH_instance/n174 ) );
XOR2XL U1730 ( .A(\BOOTH_instance/n159 ), .B(\BOOTH_instance/n163 ), .Y(
\BOOTH_instance/partial_products[5][29] ) );
XNOR2XL U1731 ( .A(\BOOTH_instance/n162 ), .B(\BOOTH_instance/n146 ), .Y(
\BOOTH_instance/n163 ) );
XOR2XL U1732 ( .A(\BOOTH_instance/n147 ), .B(\BOOTH_instance/n152 ), .Y(
\BOOTH_instance/partial_products[5][30] ) );
XNOR2XL U1733 ( .A(\BOOTH_instance/n145 ), .B(\BOOTH_instance/n146 ), .Y(
\BOOTH_instance/n152 ) );
INVXL U1734 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ) );
INVXL U1735 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ) );
INVXL U1736 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ) );
INVXL U1737 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ) );
INVXL U1738 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ) );
XOR2XL U1739 ( .A(n2137), .B(n2163), .Y(\ALU_instance/INTERNAL_B[0] ) );
INVXL U1740 ( .A(\ALU_instance/OVERFLOW ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n9 ) );
AOI221XL U1741 ( .A0(n2124), .A1(n2178), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2177), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n142 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ) );
AO22XL U1742 ( .A0(n2179), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2181), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n142 ) );
NAND2XL U1743 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n47 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n48 ), .Y(
\ALU_instance/SHIFTER_OUT[27] ) );
NAND2XL U1744 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N261 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n47 ) );
AOI222XL U1745 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N229 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N132 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N164 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n48 ) );
NAND2XL U1746 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n49 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n50 ), .Y(
\ALU_instance/SHIFTER_OUT[26] ) );
NAND2XL U1747 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N260 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n49 ) );
AOI222XL U1748 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N228 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N131 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N163 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n50 ) );
NAND2XL U1749 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n51 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n52 ), .Y(
\ALU_instance/SHIFTER_OUT[25] ) );
NAND2XL U1750 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N259 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n51 ) );
AOI222XL U1751 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N227 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N130 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N162 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n52 ) );
NAND2XL U1752 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n53 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n54 ), .Y(
\ALU_instance/SHIFTER_OUT[24] ) );
NAND2XL U1753 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N258 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n53 ) );
AOI222XL U1754 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N226 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N129 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N161 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n54 ) );
NAND2XL U1755 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n55 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n56 ), .Y(
\ALU_instance/SHIFTER_OUT[23] ) );
NAND2XL U1756 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N257 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n55 ) );
AOI222XL U1757 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N225 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N128 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N160 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n56 ) );
NAND2XL U1758 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n57 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n58 ), .Y(
\ALU_instance/SHIFTER_OUT[22] ) );
NAND2XL U1759 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N256 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n57 ) );
AOI222XL U1760 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N224 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N127 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N159 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n58 ) );
NAND2XL U1761 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n59 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n60 ), .Y(
\ALU_instance/SHIFTER_OUT[21] ) );
NAND2XL U1762 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N255 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n59 ) );
AOI222XL U1763 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N223 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N126 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N158 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n60 ) );
NAND2XL U1764 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n65 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n66 ), .Y(
\ALU_instance/SHIFTER_OUT[19] ) );
NAND2XL U1765 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N253 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n65 ) );
AOI222XL U1766 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N221 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N124 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N156 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n66 ) );
NAND2XL U1767 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n67 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n68 ), .Y(
\ALU_instance/SHIFTER_OUT[18] ) );
NAND2XL U1768 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N252 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n67 ) );
AOI222XL U1769 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N220 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N123 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N155 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n68 ) );
NAND2XL U1770 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n75 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n76 ), .Y(
\ALU_instance/SHIFTER_OUT[14] ) );
NAND2XL U1771 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N248 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n75 ) );
AOI222XL U1772 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N216 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N119 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N151 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n76 ) );
NOR2BXL U1773 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N248 ) );
NAND2XL U1774 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n77 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n78 ), .Y(
\ALU_instance/SHIFTER_OUT[13] ) );
NAND2XL U1775 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N247 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n77 ) );
AOI222XL U1776 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N215 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N118 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N150 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n78 ) );
NOR2BXL U1777 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N247 ) );
NAND2XL U1778 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n81 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n82 ), .Y(
\ALU_instance/SHIFTER_OUT[11] ) );
NAND2XL U1779 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N245 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n81 ) );
AOI222XL U1780 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N213 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N116 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N148 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n82 ) );
NOR2BXL U1781 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N245 ) );
NAND2XL U1782 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n83 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n84 ), .Y(
\ALU_instance/SHIFTER_OUT[10] ) );
NAND2XL U1783 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N244 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n83 ) );
AOI222XL U1784 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N212 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N115 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N147 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n84 ) );
NOR2BXL U1785 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N244 ) );
NAND2XL U1786 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n35 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n36 ), .Y(
\ALU_instance/SHIFTER_OUT[3] ) );
NAND2XL U1787 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N237 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n35 ) );
AOI222XL U1788 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N205 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N108 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N140 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n36 ) );
NOR2XL U1789 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N237 ) );
NOR4XL U1790 ( .A(\ALU_instance/ADDER_OUT[9] ), .B(
\ALU_instance/ADDER_OUT[8] ), .C(\ALU_instance/ADDER_OUT[7] ), .D(
\ALU_instance/ADDER_OUT[6] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n19 ) );
NOR4XL U1791 ( .A(\ALU_instance/ADDER_OUT[1] ), .B(
\ALU_instance/ADDER_OUT[19] ), .C(\ALU_instance/ADDER_OUT[18] ), .D(
\ALU_instance/ADDER_OUT[17] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n14 ) );
OAI21XL U1792 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N208 ) );
OAI21XL U1793 ( .A0(n2167), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N121 ) );
OAI21XL U1794 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N123 ) );
OAI21XL U1795 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N216 ) );
OAI21XL U1796 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N212 ) );
OAI21XL U1797 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N211 ) );
OAI21XL U1798 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N125 ) );
OAI21XL U1799 ( .A0(n2167), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N124 ) );
INVXL U1800 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ) );
INVXL U1801 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ) );
INVXL U1802 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ) );
INVXL U1803 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ) );
NOR2XL U1804 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N158 ) );
NOR2XL U1805 ( .A(n2171), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N156 ) );
AO22XL U1806 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[7] ) );
AO22XL U1807 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[14] ) );
AO22XL U1808 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[10] ) );
AO22XL U1809 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[4] ) );
XNOR2XL U1810 ( .A(n2190), .B(\ALU_instance/INTERNAL_B[4] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[0] ) );
XOR2XL U1811 ( .A(\ALU_instance/INTERNAL_B[4] ), .B(n2190), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[0] ) );
AO22XL U1812 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[11] ) );
AO22XL U1813 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[9] ) );
AO22XL U1814 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[13] ) );
NAND2XL U1815 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n11 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n12 ), .Y(
\ALU_instance/SHIFTER_OUT[9] ) );
NAND2XL U1816 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N243 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n11 ) );
AOI222XL U1817 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N211 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N114 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N146 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n12 ) );
NOR2BXL U1818 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N243 ) );
NAND2XL U1819 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n25 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n26 ), .Y(
\ALU_instance/SHIFTER_OUT[8] ) );
NAND2XL U1820 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N242 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n25 ) );
AOI222XL U1821 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N210 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N113 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N145 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n26 ) );
NOR2BXL U1822 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N242 ) );
NAND2XL U1823 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n27 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n28 ), .Y(
\ALU_instance/SHIFTER_OUT[7] ) );
NAND2XL U1824 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N241 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n27 ) );
AOI222XL U1825 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N209 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N112 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N144 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n28 ) );
NOR2XL U1826 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N241 ) );
NAND2XL U1827 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n29 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n30 ), .Y(
\ALU_instance/SHIFTER_OUT[6] ) );
NAND2XL U1828 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N240 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n29 ) );
AOI222XL U1829 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N208 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N111 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N143 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n30 ) );
NOR2XL U1830 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N240 ) );
NAND2XL U1831 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n31 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n32 ), .Y(
\ALU_instance/SHIFTER_OUT[5] ) );
NAND2XL U1832 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N239 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n31 ) );
AOI222XL U1833 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N207 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N110 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N142 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n32 ) );
NOR2XL U1834 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N239 ) );
NAND2XL U1835 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n33 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n34 ), .Y(
\ALU_instance/SHIFTER_OUT[4] ) );
NAND2XL U1836 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N238 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n33 ) );
AOI222XL U1837 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N206 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N109 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N141 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n34 ) );
NOR2XL U1838 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N238 ) );
NAND2XL U1839 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n61 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n62 ), .Y(
\ALU_instance/SHIFTER_OUT[20] ) );
NAND2XL U1840 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N254 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n61 ) );
AOI222XL U1841 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N222 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N125 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N157 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n62 ) );
NAND2XL U1842 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n69 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n70 ), .Y(
\ALU_instance/SHIFTER_OUT[17] ) );
NAND2XL U1843 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N251 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n69 ) );
AOI222XL U1844 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N219 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N122 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N154 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n70 ) );
NAND2XL U1845 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n71 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n72 ), .Y(
\ALU_instance/SHIFTER_OUT[16] ) );
NAND2XL U1846 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N250 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n71 ) );
AOI222XL U1847 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N218 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N121 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N153 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n72 ) );
NAND2XL U1848 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n73 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n74 ), .Y(
\ALU_instance/SHIFTER_OUT[15] ) );
NAND2XL U1849 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N249 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n73 ) );
AOI222XL U1850 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N217 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N120 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N152 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n74 ) );
NOR2BXL U1851 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N249 ) );
NAND2XL U1852 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n79 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n80 ), .Y(
\ALU_instance/SHIFTER_OUT[12] ) );
NAND2XL U1853 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N246 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n79 ) );
AOI222XL U1854 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N214 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N117 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N149 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n80 ) );
NOR2BXL U1855 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ), .B(
n2167), .Y(\ALU_instance/SHIFTER_GENERIC_I/N246 ) );
NAND2XL U1856 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n41 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n42 ), .Y(
\ALU_instance/SHIFTER_OUT[2] ) );
NAND2XL U1857 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N236 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n41 ) );
AOI222XL U1858 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N204 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N107 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N139 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n42 ) );
NOR2XL U1859 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N236 ) );
NOR2XL U1860 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N154 ) );
INVXL U1861 ( .A(n2124), .Y(n2123) );
INVXL U1862 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .Y(n2124) );
INVXL U1863 ( .A(\BOOTH_instance/n160 ), .Y(\BOOTH_instance/n146 ) );
CLKBUFX1 U1864 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ), .Y(n2125) );
CLKBUFX1 U1865 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ), .Y(n2130) );
CLKBUFX1 U1866 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(n2126) );
CLKBUFX1 U1867 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .Y(n2127) );
CLKBUFX1 U1868 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .Y(n2122) );
INVXL U1869 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ) );
CLKBUFX1 U1870 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .Y(n2128) );
CLKBUFX1 U1871 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .Y(n2129) );
NOR2XL U1872 ( .A(n2172), .B(n2113), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ) );
AND2XL U1873 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ), .B(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ) );
AND2XL U1874 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ), .B(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ) );
NOR2XL U1875 ( .A(n2172), .B(n1697), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ) );
NOR3XL U1876 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ), .B(n2167), .C(
n2174), .Y(\ALU_instance/SHIFTER_GENERIC_I/N164 ) );
NAND2XL U1877 ( .A(n1595), .B(n2172), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ) );
NAND2XL U1878 ( .A(n1598), .B(n2172), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ) );
NAND2XL U1879 ( .A(n1598), .B(n2172), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ) );
OAI21XL U1880 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N209 ) );
OAI21XL U1881 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n7 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N207 ) );
OAI21XL U1882 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N210 ) );
OAI21XL U1883 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N128 ) );
OAI21XL U1884 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N131 ) );
OAI21XL U1885 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N130 ) );
OAI21XL U1886 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N122 ) );
OAI21XL U1887 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N129 ) );
NAND2XL U1888 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .B(n2160), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ) );
OAI21XL U1889 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N204 ) );
OAI21XL U1890 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N217 ) );
OAI21XL U1891 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N215 ) );
OAI21XL U1892 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N214 ) );
OAI21XL U1893 ( .A0(n2170), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n53 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N213 ) );
OA21XL U1894 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ) );
OA21XL U1895 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ) );
OA21XL U1896 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ) );
OAI21XL U1897 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N135 ) );
OAI21XL U1898 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N134 ) );
OAI21XL U1899 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N133 ) );
OAI21XL U1900 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N132 ) );
OAI21XL U1901 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N127 ) );
OAI21XL U1902 ( .A0(n2169), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N126 ) );
NOR2XL U1903 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N160 ) );
NOR2XL U1904 ( .A(n2171), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N159 ) );
NOR2XL U1905 ( .A(n2171), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N157 ) );
NAND2XL U1906 ( .A(n2160), .B(\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ) );
INVXL U1907 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ) );
NAND2XL U1908 ( .A(n2160), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ) );
NOR2XL U1909 ( .A(n2171), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N155 ) );
NOR2XL U1910 ( .A(n2171), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N153 ) );
NOR2XL U1911 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N161 ) );
NOR2XL U1912 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N162 ) );
NOR2XL U1913 ( .A(n2170), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N163 ) );
NAND2XL U1914 ( .A(n2160), .B(n2174), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ) );
CLKBUFX1 U1915 ( .A(\ALU_instance/n6 ), .Y(n2139) );
OR2XL U1916 ( .A(n1602), .B(n2174), .Y(n1697) );
NAND2XL U1917 ( .A(n2160), .B(n2174), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ) );
CLKBUFX1 U1918 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n13 ), .Y(n2131) );
NOR2XL U1919 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N234 ) );
CLKBUFX1 U1920 ( .A(\ALU_instance/n5 ), .Y(n2138) );
CLKBUFX1 U1921 ( .A(EX_LOGIC_CW[3]), .Y(n2197) );
INVXL U1922 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ) );
AND2XL U1923 ( .A(n2175), .B(n2172), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ) );
AND2XL U1924 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N168 ) );
INVXL U1925 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ) );
CLKBUFX1 U1926 ( .A(n1614), .Y(n2134) );
INVXL U1927 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][7] ) );
INVXL U1928 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][6] ) );
INVXL U1929 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][5] ) );
INVXL U1930 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][4] ) );
INVXL U1931 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][3] ) );
INVXL U1932 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][2] ) );
INVXL U1933 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][1] ) );
INVXL U1934 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][0] ) );
CLKBUFX1 U1935 ( .A(n1646), .Y(n2148) );
INVXL U1936 ( .A(n1619), .Y(n1309) );
INVXL U1937 ( .A(n1199), .Y(n1421) );
CLKBUFX1 U1938 ( .A(n1208), .Y(n2150) );
OAI221XL U1939 ( .A0(\BOOTH_instance/n155 ), .A1(\BOOTH_instance/n307 ),
.B0(\BOOTH_instance/n308 ), .B1(n1721), .C0(\BOOTH_instance/n309 ),
.Y(\BOOTH_instance/n295 ) );
AOI22XL U1940 ( .A0(\BOOTH_instance/n310 ), .A1(\BOOTH_instance/n149 ), .B0(
n2193), .B1(\BOOTH_instance/n282 ), .Y(\BOOTH_instance/n309 ) );
OAI221XL U1941 ( .A0(\BOOTH_instance/n186 ), .A1(n2192), .B0(
\BOOTH_instance/n280 ), .B1(n1606), .C0(\BOOTH_instance/n313 ), .Y(
\BOOTH_instance/n306 ) );
AOI22XL U1942 ( .A0(n2193), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n176 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n313 ) );
OAI221XL U1943 ( .A0(\BOOTH_instance/n166 ), .A1(\BOOTH_instance/n307 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n158 ), .C0(
\BOOTH_instance/n314 ), .Y(\BOOTH_instance/n302 ) );
OAI21XL U1944 ( .A0(\BOOTH_instance/n150 ), .A1(\BOOTH_instance/n168 ), .B0(
n2111), .Y(\BOOTH_instance/n314 ) );
NOR3XL U1945 ( .A(n2183), .B(n2185), .C(\BOOTH_instance/n453 ), .Y(
\BOOTH_instance/n452 ) );
AOI21XL U1946 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n166 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/n304 ) );
NOR4XL U1947 ( .A(\ALU_instance/ADDER_OUT[27] ), .B(
\ALU_instance/ADDER_OUT[26] ), .C(\ALU_instance/ADDER_OUT[25] ), .D(
\ALU_instance/ADDER_OUT[24] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n16 ) );
NOR4XL U1948 ( .A(\ALU_instance/ADDER_OUT[30] ), .B(
\ALU_instance/ADDER_OUT[2] ), .C(\ALU_instance/ADDER_OUT[29] ), .D(
\ALU_instance/ADDER_OUT[28] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n17 ) );
NAND2XL U1949 ( .A(\BOOTH_instance/n348 ), .B(\BOOTH_instance/n345 ), .Y(
\BOOTH_instance/n328 ) );
NAND2XL U1950 ( .A(\BOOTH_instance/n395 ), .B(\BOOTH_instance/n372 ), .Y(
\BOOTH_instance/n373 ) );
NAND2XL U1951 ( .A(\BOOTH_instance/n371 ), .B(\BOOTH_instance/n346 ), .Y(
\BOOTH_instance/n349 ) );
AOI2B1XL U1952 ( .A1N(\BOOTH_instance/n301 ), .A0(\BOOTH_instance/n302 ),
.B0(\BOOTH_instance/n303 ), .Y(\BOOTH_instance/n293 ) );
AOI21XL U1953 ( .A0(\BOOTH_instance/n304 ), .A1(\BOOTH_instance/n305 ), .B0(
\BOOTH_instance/n306 ), .Y(\BOOTH_instance/n301 ) );
NAND2XL U1954 ( .A(\BOOTH_instance/n322 ), .B(\BOOTH_instance/n318 ), .Y(
\BOOTH_instance/n186 ) );
AO22XL U1955 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ) );
AO22XL U1956 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C1 ), .A1(n2137),
.B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C0 ), .B1(EX_ADD_SUB),
.Y(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ) );
AO22XL U1957 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ) );
AO22XL U1958 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ) );
AO22XL U1959 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ) );
AOI22XL U1960 ( .A0(\BOOTH_instance/n352 ), .A1(n2193), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n368 ) );
AOI22XL U1961 ( .A0(\BOOTH_instance/n352 ), .A1(n2190), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n366 ) );
AOI22XL U1962 ( .A0(\BOOTH_instance/n400 ), .A1(n2183), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n413 ) );
AOI21XL U1963 ( .A0(\BOOTH_instance/n398 ), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/partial_products[7][4] ) );
AOI21XL U1964 ( .A0(\BOOTH_instance/n323 ), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/decoded[5][10] ) );
AOI21XL U1965 ( .A0(\BOOTH_instance/n374 ), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/decoded[3][6] ) );
AOI21XL U1966 ( .A0(\BOOTH_instance/n350 ), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/partial_products[4][8] ) );
NAND2XL U1967 ( .A(\BOOTH_instance/n449 ), .B(n1608), .Y(
\BOOTH_instance/n450 ) );
NAND2XL U1968 ( .A(\BOOTH_instance/n457 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .Y(\BOOTH_instance/n458 )
);
NOR2XL U1969 ( .A(n2185), .B(\BOOTH_instance/n453 ), .Y(
\BOOTH_instance/n454 ) );
AO22XL U1970 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/OVERFLOW ) );
OAI31XL U1971 ( .A0(\BOOTH_instance/n145 ), .A1(\BOOTH_instance/n146 ), .A2(
\BOOTH_instance/n147 ), .B0(\BOOTH_instance/n148 ), .Y(
\BOOTH_instance/partial_products[5][31] ) );
OAI21XL U1972 ( .A0(\BOOTH_instance/n149 ), .A1(\BOOTH_instance/n150 ), .B0(
\BOOTH_instance/n151 ), .Y(\BOOTH_instance/n148 ) );
INVXL U1973 ( .A(\BOOTH_instance/n355 ), .Y(\BOOTH_instance/n352 ) );
INVXL U1974 ( .A(\BOOTH_instance/n382 ), .Y(\BOOTH_instance/n376 ) );
NAND3XL U1975 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .B(
\BOOTH_instance/n260 ), .C(\BOOTH_instance/n457 ), .Y(
\BOOTH_instance/n456 ) );
NAND2XL U1976 ( .A(\BOOTH_instance/n460 ), .B(n2192), .Y(
\BOOTH_instance/n459 ) );
NAND2XL U1977 ( .A(\BOOTH_instance/n452 ), .B(n2182), .Y(
\BOOTH_instance/n451 ) );
INVXL U1978 ( .A(\BOOTH_instance/n175 ), .Y(\BOOTH_instance/n188 ) );
NAND2XL U1979 ( .A(\BOOTH_instance/n455 ), .B(n2188), .Y(
\BOOTH_instance/n453 ) );
OAI21XL U1980 ( .A0(\BOOTH_instance/n376 ), .A1(\BOOTH_instance/n377 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .Y(\BOOTH_instance/n380 ) );
OAI21XL U1981 ( .A0(\BOOTH_instance/n326 ), .A1(\BOOTH_instance/n327 ), .B0(
n2112), .Y(\BOOTH_instance/n344 ) );
XOR2XL U1982 ( .A(n2136), .B(n2159), .Y(\ALU_instance/INTERNAL_B[1] ) );
XOR2XL U1983 ( .A(n2135), .B(n2160), .Y(\ALU_instance/INTERNAL_B[2] ) );
AO22XL U1984 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[29] ) );
AO22XL U1985 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[25] ) );
AO22XL U1986 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[26] ) );
AO22XL U1987 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[30] ) );
AO22XL U1988 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[27] ) );
AO22XL U1989 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[31] ) );
AND3XL U1990 ( .A(\BOOTH_instance/n449 ), .B(n1608), .C(n1670), .Y(
\BOOTH_instance/n448 ) );
INVXL U1991 ( .A(\BOOTH_instance/n158 ), .Y(\BOOTH_instance/n149 ) );
OR3XL U1992 ( .A(n2174), .B(n2167), .C(\BOOTH_instance/n396 ), .Y(n1698) );
OR3XL U1993 ( .A(n2158), .B(n690), .C(n1600), .Y(n1699) );
INVXL U1994 ( .A(\BOOTH_instance/n290 ), .Y(\BOOTH_instance/n310 ) );
CLKINVX1 U1995 ( .A(n2186), .Y(n2185) );
NAND3XL U1996 ( .A(n1555), .B(n1557), .C(n1551), .Y(n1574) );
CLKINVX1 U1997 ( .A(n2182), .Y(n2181) );
CLKINVX1 U1998 ( .A(n1607), .Y(n2189) );
AND3XL U1999 ( .A(\BOOTH_instance/n306 ), .B(\BOOTH_instance/n305 ), .C(
\BOOTH_instance/n304 ), .Y(\BOOTH_instance/n303 ) );
OAI2BB1XL U2000 ( .A0N(\BOOTH_instance/n283 ), .A1N(\BOOTH_instance/n284 ),
.B0(\BOOTH_instance/n285 ), .Y(\BOOTH_instance/n275 ) );
OAI21XL U2001 ( .A0(\BOOTH_instance/n284 ), .A1(\BOOTH_instance/n283 ), .B0(
\BOOTH_instance/n286 ), .Y(\BOOTH_instance/n285 ) );
NAND2XL U2002 ( .A(\ALU_instance/n21 ), .B(\ALU_instance/n22 ), .Y(
EX_ALU_OUT[0]) );
AOI22XL U2003 ( .A0(\ALU_instance/LOGIC_OUT[0] ), .A1(\ALU_instance/n6 ),
.B0(\ALU_instance/ADDER_OUT[0] ), .B1(n1599), .Y(\ALU_instance/n21 )
);
AO2B2XL U2004 ( .B0(\BOOTH_instance/n263 ), .B1(\BOOTH_instance/n264 ), .A0(
\BOOTH_instance/n265 ), .A1N(\BOOTH_instance/n266 ), .Y(
\BOOTH_instance/n255 ) );
NOR2XL U2005 ( .A(\BOOTH_instance/n264 ), .B(\BOOTH_instance/n263 ), .Y(
\BOOTH_instance/n266 ) );
AO2B2XL U2006 ( .B0(\BOOTH_instance/n253 ), .B1(\BOOTH_instance/n254 ), .A0(
\BOOTH_instance/n255 ), .A1N(\BOOTH_instance/n256 ), .Y(
\BOOTH_instance/n245 ) );
NOR2XL U2007 ( .A(\BOOTH_instance/n254 ), .B(\BOOTH_instance/n253 ), .Y(
\BOOTH_instance/n256 ) );
AO2B2XL U2008 ( .B0(\BOOTH_instance/n243 ), .B1(\BOOTH_instance/n244 ), .A0(
\BOOTH_instance/n245 ), .A1N(\BOOTH_instance/n246 ), .Y(
\BOOTH_instance/n235 ) );
NOR2XL U2009 ( .A(\BOOTH_instance/n244 ), .B(\BOOTH_instance/n243 ), .Y(
\BOOTH_instance/n246 ) );
AO2B2XL U2010 ( .B0(\BOOTH_instance/n233 ), .B1(\BOOTH_instance/n234 ), .A0(
\BOOTH_instance/n235 ), .A1N(\BOOTH_instance/n236 ), .Y(
\BOOTH_instance/n225 ) );
NOR2XL U2011 ( .A(\BOOTH_instance/n234 ), .B(\BOOTH_instance/n233 ), .Y(
\BOOTH_instance/n236 ) );
AO2B2XL U2012 ( .B0(\BOOTH_instance/n213 ), .B1(\BOOTH_instance/n214 ), .A0(
\BOOTH_instance/n215 ), .A1N(\BOOTH_instance/n216 ), .Y(
\BOOTH_instance/n205 ) );
NOR2XL U2013 ( .A(\BOOTH_instance/n214 ), .B(\BOOTH_instance/n213 ), .Y(
\BOOTH_instance/n216 ) );
AO2B2XL U2014 ( .B0(\BOOTH_instance/n273 ), .B1(\BOOTH_instance/n274 ), .A0(
\BOOTH_instance/n275 ), .A1N(\BOOTH_instance/n276 ), .Y(
\BOOTH_instance/n265 ) );
NOR2XL U2015 ( .A(\BOOTH_instance/n274 ), .B(\BOOTH_instance/n273 ), .Y(
\BOOTH_instance/n276 ) );
CLKINVX1 U2016 ( .A(n2180), .Y(n2179) );
CLKINVX1 U2017 ( .A(n2188), .Y(n2187) );
CLKINVX1 U2018 ( .A(n2191), .Y(n2190) );
OAI221XL U2019 ( .A0(n2192), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n429 ), .Y(\BOOTH_instance/decoded[1][5] ) );
AOI22XL U2020 ( .A0(\BOOTH_instance/n424 ), .A1(n2193), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n429 ) );
OAI221XL U2021 ( .A0(n2191), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n428 ), .Y(\BOOTH_instance/decoded[1][6] ) );
AOI22XL U2022 ( .A0(\BOOTH_instance/n424 ), .A1(N4721), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n428 ) );
OAI222XL U2023 ( .A0(\BOOTH_instance/n259 ), .A1(n2127), .B0(
\BOOTH_instance/n249 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n1607), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N216 ) );
OAI221XL U2024 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n421 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n422 ), .C0(\BOOTH_instance/n427 ), .Y(
\BOOTH_instance/decoded[1][7] ) );
AOI22XL U2025 ( .A0(\BOOTH_instance/n424 ), .A1(n2190), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n427 ) );
XOR2XL U2026 ( .A(\BOOTH_instance/decoded[3][6] ), .B(
\BOOTH_instance/decoded[2][6] ), .Y(
\BOOTH_instance/partial_products[7][6] ) );
OAI221XL U2027 ( .A0(n2192), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n375 ), .Y(\BOOTH_instance/decoded[3][9] ) );
OAI221XL U2028 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n397 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n398 ), .C0(\BOOTH_instance/n399 ), .Y(
\BOOTH_instance/decoded[2][9] ) );
AOI22XL U2029 ( .A0(\BOOTH_instance/n376 ), .A1(n2193), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n375 ) );
XOR2XL U2030 ( .A(\BOOTH_instance/partial_products[4][8] ), .B(
\BOOTH_instance/partial_products[3][8] ), .Y(
\BOOTH_instance/partial_products[7][8] ) );
OAI221XL U2031 ( .A0(n2191), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n394 ), .Y(\BOOTH_instance/decoded[3][10] ) );
OAI221XL U2032 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n397 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n418 ), .Y(\BOOTH_instance/decoded[2][10] ) );
AOI22XL U2033 ( .A0(\BOOTH_instance/n376 ), .A1(N4721), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n394 ) );
OAI221XL U2034 ( .A0(n2186), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n441 ), .Y(\BOOTH_instance/decoded[1][11] ) );
OAI222XL U2035 ( .A0(\BOOTH_instance/n219 ), .A1(n2127), .B0(
\BOOTH_instance/n209 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n2182), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N220 ) );
AOI22XL U2036 ( .A0(\BOOTH_instance/n424 ), .A1(n2187), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n441 ) );
OAI221XL U2037 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n373 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n374 ), .C0(\BOOTH_instance/n393 ), .Y(
\BOOTH_instance/decoded[3][11] ) );
OAI221XL U2038 ( .A0(n1607), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n417 ), .Y(\BOOTH_instance/decoded[2][11] ) );
AOI22XL U2039 ( .A0(\BOOTH_instance/n376 ), .A1(n2190), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n393 ) );
XOR2XL U2040 ( .A(\BOOTH_instance/decoded[5][10] ), .B(
\BOOTH_instance/decoded[4][10] ), .Y(
\BOOTH_instance/partial_products[4][10] ) );
OAI221XL U2041 ( .A0(n2182), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n439 ), .Y(\BOOTH_instance/decoded[1][13] ) );
OAI222XL U2042 ( .A0(\BOOTH_instance/n199 ), .A1(n2127), .B0(
\BOOTH_instance/n189 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n1608), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N222 ) );
AOI22XL U2043 ( .A0(\BOOTH_instance/n424 ), .A1(n2183), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n439 ) );
OAI221XL U2044 ( .A0(n2191), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n367 ), .Y(\BOOTH_instance/decoded[4][12] ) );
INVXL U2045 ( .A(\BOOTH_instance/n342 ), .Y(\BOOTH_instance/decoded[5][12] )
);
AOI22XL U2046 ( .A0(\BOOTH_instance/n352 ), .A1(N4721), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n367 ) );
OAI221XL U2047 ( .A0(n2180), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n438 ), .Y(\BOOTH_instance/decoded[1][14] ) );
OAI222XL U2048 ( .A0(\BOOTH_instance/n189 ), .A1(n2127), .B0(
\BOOTH_instance/n177 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n1670), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N223 ) );
AOI22XL U2049 ( .A0(\BOOTH_instance/n424 ), .A1(n2181), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n438 ) );
OAI221XL U2050 ( .A0(n2192), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n341 ), .Y(\BOOTH_instance/decoded[5][13] ) );
OAI221XL U2051 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n349 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n350 ), .C0(\BOOTH_instance/n366 ), .Y(
\BOOTH_instance/decoded[4][13] ) );
AOI22XL U2052 ( .A0(\BOOTH_instance/n326 ), .A1(n2193), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n341 ) );
OAI221XL U2053 ( .A0(n1608), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n437 ), .Y(\BOOTH_instance/decoded[1][15] ) );
OAI222XL U2054 ( .A0(\BOOTH_instance/n177 ), .A1(n2127), .B0(n1609), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .C0(\BOOTH_instance/n156 ),
.C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N224 ) );
AOI22XL U2055 ( .A0(\BOOTH_instance/n424 ), .A1(n2179), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n437 ) );
XOR2XL U2056 ( .A(\BOOTH_instance/partial_products[6][12] ), .B(
\BOOTH_instance/partial_products[5][12] ), .Y(
\BOOTH_instance/partial_products[8][12] ) );
OAI221XL U2057 ( .A0(n2191), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n340 ), .Y(\BOOTH_instance/decoded[5][14] ) );
OAI221XL U2058 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n349 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n365 ), .Y(\BOOTH_instance/decoded[4][14] ) );
AOI22XL U2059 ( .A0(\BOOTH_instance/n326 ), .A1(N4721), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n340 ) );
OAI22XL U2060 ( .A0(n1609), .A1(n2127), .B0(\BOOTH_instance/n157 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .Y(\BOOTH_instance/N225 )
);
OAI221XL U2061 ( .A0(n1670), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n436 ), .Y(\BOOTH_instance/decoded[1][16] ) );
AOI22XL U2062 ( .A0(\BOOTH_instance/n424 ), .A1(n2178), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n436 ) );
XOR2XL U2063 ( .A(\BOOTH_instance/n305 ), .B(\BOOTH_instance/n304 ), .Y(
\BOOTH_instance/partial_products[5][14] ) );
OAI221XL U2064 ( .A0(n2186), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n389 ), .Y(\BOOTH_instance/decoded[3][15] ) );
OAI221XL U2065 ( .A0(n2182), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n413 ), .Y(\BOOTH_instance/decoded[2][15] ) );
AOI22XL U2066 ( .A0(\BOOTH_instance/n376 ), .A1(n2187), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n389 ) );
OAI221XL U2067 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n328 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n323 ), .C0(\BOOTH_instance/n339 ), .Y(
\BOOTH_instance/decoded[5][15] ) );
OAI221XL U2068 ( .A0(n1607), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n364 ), .Y(\BOOTH_instance/decoded[4][15] ) );
AOI22XL U2069 ( .A0(\BOOTH_instance/n326 ), .A1(n2190), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n339 ) );
OAI221XL U2070 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n421 ),
.B0(n1609), .B1(\BOOTH_instance/n422 ), .C0(\BOOTH_instance/n435 ),
.Y(\BOOTH_instance/decoded[1][17] ) );
AOI22XL U2071 ( .A0(\BOOTH_instance/n424 ), .A1(n2177), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n435 ) );
XOR2XL U2072 ( .A(\BOOTH_instance/n302 ), .B(\BOOTH_instance/n311 ), .Y(
\BOOTH_instance/partial_products[5][15] ) );
AOI2B1XL U2073 ( .A1N(\BOOTH_instance/n306 ), .A0(\BOOTH_instance/n312 ),
.B0(\BOOTH_instance/n303 ), .Y(\BOOTH_instance/n311 ) );
NAND2XL U2074 ( .A(\BOOTH_instance/n304 ), .B(\BOOTH_instance/n305 ), .Y(
\BOOTH_instance/n312 ) );
OAI222XL U2075 ( .A0(n1609), .A1(n1699), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n434 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n422 ), .Y(\BOOTH_instance/decoded[1][18] ) );
OAI221XL U2076 ( .A0(n2182), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n387 ), .Y(\BOOTH_instance/decoded[3][17] ) );
OAI221XL U2077 ( .A0(n1608), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n411 ), .Y(\BOOTH_instance/decoded[2][17] ) );
AOI22XL U2078 ( .A0(\BOOTH_instance/n376 ), .A1(n2183), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n387 ) );
XNOR2XL U2079 ( .A(\BOOTH_instance/n287 ), .B(\BOOTH_instance/n284 ), .Y(
\BOOTH_instance/partial_products[5][17] ) );
XNOR2XL U2080 ( .A(\BOOTH_instance/n286 ), .B(\BOOTH_instance/n283 ), .Y(
\BOOTH_instance/n287 ) );
OAI221XL U2081 ( .A0(n2180), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n386 ), .Y(\BOOTH_instance/decoded[3][18] ) );
OAI221XL U2082 ( .A0(n1670), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n410 ), .Y(\BOOTH_instance/decoded[2][18] ) );
AOI22XL U2083 ( .A0(\BOOTH_instance/n376 ), .A1(n2181), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n386 ) );
NOR2XL U2084 ( .A(\BOOTH_instance/n315 ), .B(n2192), .Y(
\BOOTH_instance/decoded[8][19] ) );
XNOR2XL U2085 ( .A(\BOOTH_instance/n277 ), .B(\BOOTH_instance/n274 ), .Y(
\BOOTH_instance/partial_products[5][18] ) );
XNOR2XL U2086 ( .A(\BOOTH_instance/n275 ), .B(\BOOTH_instance/n273 ), .Y(
\BOOTH_instance/n277 ) );
OAI221XL U2087 ( .A0(n1608), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n385 ), .Y(\BOOTH_instance/decoded[3][19] ) );
OAI221XL U2088 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n397 ),
.B0(n1609), .B1(\BOOTH_instance/n398 ), .C0(\BOOTH_instance/n409 ),
.Y(\BOOTH_instance/decoded[2][19] ) );
AOI22XL U2089 ( .A0(\BOOTH_instance/n376 ), .A1(n2179), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n385 ) );
OAI221XL U2090 ( .A0(n2186), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n335 ), .Y(\BOOTH_instance/decoded[5][19] ) );
OAI221XL U2091 ( .A0(n2182), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n360 ), .Y(\BOOTH_instance/decoded[4][19] ) );
AOI22XL U2092 ( .A0(\BOOTH_instance/n326 ), .A1(n2187), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n335 ) );
NOR2XL U2093 ( .A(\BOOTH_instance/n315 ), .B(n2191), .Y(
\BOOTH_instance/decoded[8][20] ) );
XNOR2XL U2094 ( .A(\BOOTH_instance/n267 ), .B(\BOOTH_instance/n264 ), .Y(
\BOOTH_instance/partial_products[5][19] ) );
XNOR2XL U2095 ( .A(\BOOTH_instance/n265 ), .B(\BOOTH_instance/n263 ), .Y(
\BOOTH_instance/n267 ) );
OAI222XL U2096 ( .A0(n1609), .A1(n1698), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n408 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n398 ), .Y(\BOOTH_instance/decoded[2][20] ) );
OAI221XL U2097 ( .A0(n1670), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n384 ), .Y(\BOOTH_instance/decoded[3][20] ) );
AOI22XL U2098 ( .A0(\BOOTH_instance/n376 ), .A1(n2178), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n384 ) );
NOR2XL U2099 ( .A(\BOOTH_instance/n315 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .Y(
\BOOTH_instance/decoded[8][21] ) );
XNOR2XL U2100 ( .A(\BOOTH_instance/n257 ), .B(\BOOTH_instance/n254 ), .Y(
\BOOTH_instance/partial_products[5][20] ) );
XNOR2XL U2101 ( .A(\BOOTH_instance/n255 ), .B(\BOOTH_instance/n253 ), .Y(
\BOOTH_instance/n257 ) );
OAI221XL U2102 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n373 ),
.B0(n1609), .B1(\BOOTH_instance/n374 ), .C0(\BOOTH_instance/n383 ),
.Y(\BOOTH_instance/decoded[3][21] ) );
AOI22XL U2103 ( .A0(\BOOTH_instance/n376 ), .A1(n2177), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n383 ) );
OAI221XL U2104 ( .A0(n2182), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n333 ), .Y(\BOOTH_instance/decoded[5][21] ) );
OAI221XL U2105 ( .A0(n1608), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n358 ), .Y(\BOOTH_instance/decoded[4][21] ) );
AOI22XL U2106 ( .A0(\BOOTH_instance/n326 ), .A1(n2183), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n333 ) );
NOR2XL U2107 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n260 ), .Y(
\BOOTH_instance/decoded[8][22] ) );
XNOR2XL U2108 ( .A(\BOOTH_instance/n247 ), .B(\BOOTH_instance/n244 ), .Y(
\BOOTH_instance/partial_products[5][21] ) );
XNOR2XL U2109 ( .A(\BOOTH_instance/n245 ), .B(\BOOTH_instance/n243 ), .Y(
\BOOTH_instance/n247 ) );
OAI222XL U2110 ( .A0(n1609), .A1(n1707), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n382 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n374 ), .Y(\BOOTH_instance/decoded[3][22] ) );
OAI221XL U2111 ( .A0(n2180), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n332 ), .Y(\BOOTH_instance/decoded[5][22] ) );
OAI221XL U2112 ( .A0(n1670), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n357 ), .Y(\BOOTH_instance/decoded[4][22] ) );
AOI22XL U2113 ( .A0(\BOOTH_instance/n326 ), .A1(n2181), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n332 ) );
NOR2XL U2114 ( .A(\BOOTH_instance/n315 ), .B(n1607), .Y(
\BOOTH_instance/decoded[8][23] ) );
XNOR2XL U2115 ( .A(\BOOTH_instance/n237 ), .B(\BOOTH_instance/n234 ), .Y(
\BOOTH_instance/partial_products[5][22] ) );
XNOR2XL U2116 ( .A(\BOOTH_instance/n235 ), .B(\BOOTH_instance/n233 ), .Y(
\BOOTH_instance/n237 ) );
OAI221XL U2117 ( .A0(n1608), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n331 ), .Y(\BOOTH_instance/decoded[5][23] ) );
OAI221XL U2118 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n349 ),
.B0(n1609), .B1(\BOOTH_instance/n350 ), .C0(\BOOTH_instance/n356 ),
.Y(\BOOTH_instance/decoded[4][23] ) );
AOI22XL U2119 ( .A0(\BOOTH_instance/n326 ), .A1(n2179), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n331 ) );
NOR2XL U2120 ( .A(\BOOTH_instance/n315 ), .B(n2188), .Y(
\BOOTH_instance/decoded[8][24] ) );
OAI222XL U2121 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n355 ),
.B0(\BOOTH_instance/n157 ), .B1(\BOOTH_instance/n350 ), .C0(n1609),
.C1(n1706), .Y(\BOOTH_instance/decoded[4][24] ) );
OAI221XL U2122 ( .A0(n1670), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n330 ), .Y(\BOOTH_instance/decoded[5][24] ) );
AOI22XL U2123 ( .A0(\BOOTH_instance/n326 ), .A1(n2178), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n330 ) );
NOR2XL U2124 ( .A(\BOOTH_instance/n315 ), .B(n2186), .Y(
\BOOTH_instance/decoded[8][25] ) );
XNOR2XL U2125 ( .A(\BOOTH_instance/n217 ), .B(\BOOTH_instance/n214 ), .Y(
\BOOTH_instance/partial_products[5][24] ) );
XNOR2XL U2126 ( .A(\BOOTH_instance/n215 ), .B(\BOOTH_instance/n213 ), .Y(
\BOOTH_instance/n217 ) );
OAI221XL U2127 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n328 ),
.B0(n1609), .B1(\BOOTH_instance/n323 ), .C0(\BOOTH_instance/n329 ),
.Y(\BOOTH_instance/decoded[5][25] ) );
AOI22XL U2128 ( .A0(\BOOTH_instance/n326 ), .A1(n2177), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n329 ) );
OAI222XL U2129 ( .A0(n1609), .A1(n1703), .B0(\BOOTH_instance/n156 ), .B1(
n1705), .C0(\BOOTH_instance/n157 ), .C1(\BOOTH_instance/n323 ), .Y(
\BOOTH_instance/decoded[5][26] ) );
NOR2XL U2130 ( .A(\BOOTH_instance/n315 ), .B(n2182), .Y(
\BOOTH_instance/decoded[8][27] ) );
XNOR2XL U2131 ( .A(\BOOTH_instance/n197 ), .B(\BOOTH_instance/n194 ), .Y(
\BOOTH_instance/partial_products[5][26] ) );
XNOR2XL U2132 ( .A(\BOOTH_instance/n195 ), .B(\BOOTH_instance/n193 ), .Y(
\BOOTH_instance/n197 ) );
NOR2XL U2133 ( .A(\BOOTH_instance/n315 ), .B(n2180), .Y(
\BOOTH_instance/decoded[8][28] ) );
NOR2XL U2134 ( .A(\BOOTH_instance/n315 ), .B(n1608), .Y(
\BOOTH_instance/decoded[8][29] ) );
AND2XL U2135 ( .A(\BOOTH_instance/N211 ), .B(\BOOTH_instance/decoded[1][2] ),
.Y(\BOOTH_instance/add_7_root_add_53_G7/carry[3] ) );
OAI221XL U2136 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n397 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n406 ), .Y(\BOOTH_instance/partial_products[7][5] ) );
AND2XL U2137 ( .A(\BOOTH_instance/partial_products[7][4] ), .B(
\BOOTH_instance/partial_products[8][4] ), .Y(
\BOOTH_instance/add_0_root_add_53_G7/carry[5] ) );
OAI21XL U2138 ( .A0(\BOOTH_instance/n400 ), .A1(\BOOTH_instance/n401 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .Y(\BOOTH_instance/n406 ) );
OAI221XL U2139 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n373 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n380 ), .Y(\BOOTH_instance/decoded[3][7] ) );
OAI221XL U2140 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n349 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n351 ), .Y(\BOOTH_instance/partial_products[4][9] ) );
AND2XL U2141 ( .A(\BOOTH_instance/partial_products[3][8] ), .B(
\BOOTH_instance/partial_products[4][8] ), .Y(
\BOOTH_instance/add_2_root_add_53_G7/carry[9] ) );
OAI21XL U2142 ( .A0(\BOOTH_instance/n352 ), .A1(\BOOTH_instance/n353 ), .B0(
n2112), .Y(\BOOTH_instance/n351 ) );
OAI221XL U2143 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n328 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n344 ), .Y(\BOOTH_instance/decoded[5][11] ) );
OAI221XL U2144 ( .A0(n2192), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n368 ), .Y(\BOOTH_instance/decoded[4][11] ) );
AND2XL U2145 ( .A(\BOOTH_instance/decoded[4][10] ), .B(
\BOOTH_instance/decoded[5][10] ), .Y(
\BOOTH_instance/add_5_root_add_53_G7/carry[11] ) );
OAI221XL U2146 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n186 ),
.B0(\BOOTH_instance/n308 ), .B1(n1606), .C0(\BOOTH_instance/n321 ),
.Y(\BOOTH_instance/partial_products[5][13] ) );
AND2XL U2147 ( .A(\BOOTH_instance/partial_products[5][12] ), .B(
\BOOTH_instance/partial_products[6][12] ), .Y(
\BOOTH_instance/add_1_root_add_53_G7/carry[13] ) );
OAI21XL U2148 ( .A0(\BOOTH_instance/n188 ), .A1(\BOOTH_instance/n176 ), .B0(
n2111), .Y(\BOOTH_instance/n321 ) );
NOR2XL U2149 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n307 ), .Y(
\BOOTH_instance/decoded[8][17] ) );
AND2XL U2150 ( .A(\BOOTH_instance/decoded[8][16] ), .B(
\BOOTH_instance/partial_products[2][16] ), .Y(
\BOOTH_instance/add_3_root_add_53_G7/carry[17] ) );
NOR2XL U2151 ( .A(\BOOTH_instance/n315 ), .B(n1670), .Y(
\BOOTH_instance/decoded[8][30] ) );
XOR2XL U2152 ( .A(n2135), .B(n2171), .Y(\ALU_instance/INTERNAL_B[4] ) );
AO22XL U2153 ( .A0(EX_MULT_OUT[31]), .A1(n2145), .B0(EX_ALU_OUT[31]), .B1(
n2144), .Y(N4891) );
OAI2BB1XL U2154 ( .A0N(\ALU_instance/ADDER_OUT[31] ), .A1N(n1599), .B0(
\ALU_instance/n39 ), .Y(EX_ALU_OUT[31]) );
AOI22XL U2155 ( .A0(\ALU_instance/SHIFTER_OUT[31] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[31] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n39 ) );
AOI221XL U2156 ( .A0(n2124), .A1(n2179), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2178), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n148 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ) );
AO22XL U2157 ( .A0(n2181), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2183), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n148 ) );
AOI221XL U2158 ( .A0(n2124), .A1(n2181), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2179), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n94 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ) );
AO22XL U2159 ( .A0(n2183), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2185), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n94 ) );
AOI221XL U2160 ( .A0(n2124), .A1(n2183), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2181), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n151 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ) );
AO22XL U2161 ( .A0(n2185), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2187), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n151 ) );
AOI222XL U2162 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .C1(n1597), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ) );
AOI222XL U2163 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ), .C1(n1597), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ) );
AOI222XL U2164 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .A1(n1597),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .B1(n1595), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ), .C1(n2175), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ) );
OAI222XL U2165 ( .A0(n1609), .A1(n1704), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n175 ), .C0(\BOOTH_instance/n157 ), .C1(n1606), .Y(
\BOOTH_instance/n171 ) );
AOI222XL U2166 ( .A0(n2112), .A1(\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N105 ), .B1(n2132), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N137 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n86 ) );
OAI221XL U2167 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n150 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N137 ) );
OAI221XL U2168 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n149 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N105 ) );
AOI222XL U2169 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n151 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n150 ) );
NAND2XL U2170 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n39 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n40 ), .Y(
\ALU_instance/SHIFTER_OUT[30] ) );
NAND2XL U2171 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N264 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n39 ) );
AOI222XL U2172 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N232 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N135 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N167 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n40 ) );
NAND2XL U2173 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n43 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n44 ), .Y(
\ALU_instance/SHIFTER_OUT[29] ) );
NAND2XL U2174 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N263 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n43 ) );
AOI222XL U2175 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N231 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N134 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N166 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n44 ) );
NAND2XL U2176 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n45 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n46 ), .Y(
\ALU_instance/SHIFTER_OUT[28] ) );
NAND2XL U2177 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N262 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n45 ) );
AOI222XL U2178 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N230 ), .A1(n2131),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N133 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N165 ), .C1(n2133), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n46 ) );
NAND2XL U2179 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n63 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n64 ), .Y(
\ALU_instance/SHIFTER_OUT[1] ) );
NAND2XL U2180 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N235 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n63 ) );
AOI222XL U2181 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N203 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N106 ), .B1(n1616), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N138 ), .C1(n1615), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n64 ) );
NOR2XL U2182 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N235 ) );
OAI221XL U2183 ( .A0(n2127), .A1(n2180), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(n2182), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n148 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ) );
AOI22XL U2184 ( .A0(n2178), .A1(n2130), .B0(n2177), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n148 ) );
OAI221XL U2185 ( .A0(n2127), .A1(n1607), .B0(n2129), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n156 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ) );
AOI22XL U2186 ( .A0(n2187), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n2185), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n156 ) );
OAI221XL U2187 ( .A0(n2128), .A1(n2186), .B0(n2129), .B1(n2188), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n172 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ) );
AOI22XL U2188 ( .A0(n2183), .A1(n2130), .B0(n2181), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n172 ) );
OAI221XL U2189 ( .A0(n2128), .A1(n2188), .B0(n2129), .B1(n1607), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n178 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ) );
AOI22XL U2190 ( .A0(n2185), .A1(n2130), .B0(n2183), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n178 ) );
OAI221XL U2191 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n167 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ) );
AOI22XL U2192 ( .A0(n2189), .A1(n2130), .B0(n2187), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n167 ) );
AOI221XL U2193 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n105 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ) );
AO22XL U2194 ( .A0(n1598), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ),
.B0(n1597), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n105 ) );
AOI221XL U2195 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n106 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ) );
AO22XL U2196 ( .A0(n1598), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ),
.B0(n1597), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n106 ) );
AOI221XL U2197 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ), .A1(n1598),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ) );
AOI221XL U2198 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ) );
AOI221XL U2199 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ) );
AOI221XL U2200 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n98 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ) );
INVXL U2201 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n98 ) );
AOI221XL U2202 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n7 ) );
AOI221XL U2203 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ), .A1(n1598),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n157 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ) );
OAI2BB2XL U2204 ( .B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ), .A0N(
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ), .A1N(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n157 ) );
AOI221XL U2205 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n93 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ) );
AO22XL U2206 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ),
.B0(n1597), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n93 ) );
AOI221XL U2207 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .B1(n1597), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n91 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ) );
AO22XL U2208 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n91 ) );
AOI221XL U2209 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .B1(n1597), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n157 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ) );
AO22XL U2210 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n157 ) );
OAI221XL U2211 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n269 ),
.B0(\BOOTH_instance/n166 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .C0(\BOOTH_instance/n271 ),
.Y(\BOOTH_instance/n263 ) );
AOI22XL U2212 ( .A0(n2190), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n272 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n271 ) );
OAI221XL U2213 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n239 ),
.B0(\BOOTH_instance/n166 ), .B1(n2188), .C0(\BOOTH_instance/n241 ),
.Y(\BOOTH_instance/n233 ) );
AOI22XL U2214 ( .A0(n2189), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n242 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n241 ) );
OAI221XL U2215 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n209 ),
.B0(\BOOTH_instance/n166 ), .B1(n2182), .C0(\BOOTH_instance/n211 ),
.Y(\BOOTH_instance/n203 ) );
AOI22XL U2216 ( .A0(n2183), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n212 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n211 ) );
OAI221XL U2217 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n177 ),
.B0(n1670), .B1(\BOOTH_instance/n166 ), .C0(\BOOTH_instance/n179 ),
.Y(\BOOTH_instance/n170 ) );
AOI22XL U2218 ( .A0(n2178), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n180 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n179 ) );
OAI221XL U2219 ( .A0(\BOOTH_instance/n155 ), .A1(n2192), .B0(n1721), .B1(
\BOOTH_instance/n280 ), .C0(\BOOTH_instance/n281 ), .Y(
\BOOTH_instance/n273 ) );
AOI22XL U2220 ( .A0(\BOOTH_instance/n272 ), .A1(\BOOTH_instance/n149 ), .B0(
n2190), .B1(\BOOTH_instance/n282 ), .Y(\BOOTH_instance/n281 ) );
OAI221XL U2221 ( .A0(\BOOTH_instance/n186 ), .A1(n2188), .B0(n1606), .B1(
\BOOTH_instance/n239 ), .C0(\BOOTH_instance/n258 ), .Y(
\BOOTH_instance/n254 ) );
AOI22XL U2222 ( .A0(n2189), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n242 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n258 ) );
OAI221XL U2223 ( .A0(\BOOTH_instance/n186 ), .A1(n2186), .B0(n1606), .B1(
\BOOTH_instance/n229 ), .C0(\BOOTH_instance/n248 ), .Y(
\BOOTH_instance/n244 ) );
AOI22XL U2224 ( .A0(n2187), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n232 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n248 ) );
OAI221XL U2225 ( .A0(\BOOTH_instance/n186 ), .A1(n2182), .B0(n1606), .B1(
\BOOTH_instance/n209 ), .C0(\BOOTH_instance/n228 ), .Y(
\BOOTH_instance/n224 ) );
AOI22XL U2226 ( .A0(n2183), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n212 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n228 ) );
OAI221XL U2227 ( .A0(\BOOTH_instance/n186 ), .A1(n2180), .B0(n1606), .B1(
\BOOTH_instance/n199 ), .C0(\BOOTH_instance/n218 ), .Y(
\BOOTH_instance/n214 ) );
AOI22XL U2228 ( .A0(n2181), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n202 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n218 ) );
OAI221XL U2229 ( .A0(\BOOTH_instance/n186 ), .A1(n1608), .B0(n1606), .B1(
\BOOTH_instance/n189 ), .C0(\BOOTH_instance/n208 ), .Y(
\BOOTH_instance/n204 ) );
AOI22XL U2230 ( .A0(n2179), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n192 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n208 ) );
OAI221XL U2231 ( .A0(n1670), .A1(\BOOTH_instance/n186 ), .B0(
\BOOTH_instance/n177 ), .B1(n1606), .C0(\BOOTH_instance/n198 ), .Y(
\BOOTH_instance/n194 ) );
AOI22XL U2232 ( .A0(n2178), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n180 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n198 ) );
OAI221XL U2233 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n186 ),
.B0(n1609), .B1(n1606), .C0(\BOOTH_instance/n187 ), .Y(
\BOOTH_instance/n182 ) );
AOI22XL U2234 ( .A0(\BOOTH_instance/n188 ), .A1(n2177), .B0(
\BOOTH_instance/n176 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n187 ) );
OAI221XL U2235 ( .A0(\BOOTH_instance/n186 ), .A1(n2191), .B0(n1606), .B1(
\BOOTH_instance/n299 ), .C0(\BOOTH_instance/n300 ), .Y(
\BOOTH_instance/n296 ) );
AOI22XL U2236 ( .A0(N4721), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n292 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n300 ) );
OAI221XL U2237 ( .A0(\BOOTH_instance/n186 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .B0(n1606), .B1(
\BOOTH_instance/n269 ), .C0(\BOOTH_instance/n288 ), .Y(
\BOOTH_instance/n284 ) );
AOI22XL U2238 ( .A0(n2190), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n272 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n288 ) );
OAI222XL U2239 ( .A0(n1721), .A1(n1609), .B0(\BOOTH_instance/n155 ), .B1(
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\BOOTH_instance/n158 ), .Y(\BOOTH_instance/n145 ) );
OAI221XL U2240 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n116 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N221 ) );
INVXL U2241 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n116 ) );
AOI222XL U2242 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n117 ) );
OAI221XL U2243 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n125 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n126 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N219 ) );
INVXL U2244 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n125 ) );
AOI222XL U2245 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n126 ) );
OAI221XL U2246 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n20 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N112 ) );
AOI222XL U2247 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n20 ) );
OAI221XL U2248 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n40 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N108 ) );
AOI222XL U2249 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
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\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
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OAI221XL U2250 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
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AOI22XL U2251 ( .A0(n2190), .A1(n2125), .B0(N4721), .B1(
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INVXL U2252 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n169 ), .Y(
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OAI211XL U2253 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ), .A1(
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\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
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\ALU_instance/SHIFTER_GENERIC_I/C86/n169 ) );
AOI22XL U2254 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
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\ALU_instance/SHIFTER_GENERIC_I/C86/n170 ) );
INVXL U2255 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n88 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ) );
OAI211XL U2256 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
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AOI22XL U2257 ( .A0(n1598), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ),
.B0(n1597), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ), .Y(
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INVXL U2258 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n68 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ) );
OAI211XL U2259 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ), .A1(
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AOI22XL U2260 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
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\ALU_instance/SHIFTER_GENERIC_I/C86/n72 ) );
AOI22XL U2261 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .A1(n1597),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .B1(n1595), .Y(
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NOR4XL U2262 ( .A(\ALU_instance/ADDER_OUT[23] ), .B(
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NOR4XL U2263 ( .A(\ALU_instance/ADDER_OUT[16] ), .B(
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\ALU_instance/ADDER_OUT[13] ), .Y(
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OAI221XL U2264 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n88 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ), .B1(n2172), .C0(
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INVXL U2265 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n88 ) );
AOI222XL U2266 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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OAI221XL U2267 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n95 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ), .B1(n2172), .C0(
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\ALU_instance/SHIFTER_GENERIC_I/N224 ) );
INVXL U2268 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n95 ) );
AOI222XL U2269 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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OAI221XL U2270 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n103 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
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INVXL U2271 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ), .Y(
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AOI222XL U2272 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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OAI221XL U2273 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
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AOI222XL U2274 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
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OAI221XL U2275 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
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AOI222XL U2276 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
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OAI221XL U2277 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n53 ), .B1(n2172), .C0(
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AOI222XL U2278 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
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OAI221XL U2279 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ), .B1(n2172), .C0(
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AOI222XL U2280 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ), .B0(
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OAI221XL U2281 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ), .B1(n2172), .C0(
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AOI222XL U2282 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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OAI221XL U2283 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ), .B1(n2172), .C0(
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AOI222XL U2284 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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OAI221XL U2285 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n121 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ), .B1(n2172), .C0(
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INVXL U2286 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ), .Y(
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AOI222XL U2287 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
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OAI221XL U2288 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ), .A1(
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AOI222XL U2289 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2290 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ), .A1(
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AOI222XL U2291 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2292 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ), .A1(
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AOI222XL U2293 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2294 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ), .A1(
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AOI222XL U2295 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2296 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ), .A1(
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AOI222XL U2297 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2298 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ), .A1(
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AOI222XL U2299 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2300 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ), .A1(
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AOI222XL U2301 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2302 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ), .A1(
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AOI222XL U2303 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
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OAI221XL U2304 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ), .A1(
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AOI222XL U2305 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
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\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n57 ) );
OAI221XL U2306 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(n2191),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n61 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n58 ) );
AOI22XL U2307 ( .A0(N4721), .A1(n2125), .B0(n2193), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n61 ) );
OAI221XL U2308 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n2 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N146 ) );
INVXL U2309 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n2 ) );
AOI222XL U2310 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n5 ) );
OAI221XL U2311 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n40 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N140 ) );
AOI222XL U2312 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n40 ) );
OAI221XL U2313 ( .A0(n2122), .A1(\BOOTH_instance/n260 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n47 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n42 ) );
AOI22XL U2314 ( .A0(n2190), .A1(n2125), .B0(N4721), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n47 ) );
OAI221XL U2315 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n57 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N139 ) );
AOI222XL U2316 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n57 ) );
OAI221XL U2317 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2191), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n60 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n58 ) );
AOI22XL U2318 ( .A0(N4721), .A1(n2125), .B0(n2193), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n60 ) );
MXI2XL U2319 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ), .S0(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ) );
AOI21XL U2320 ( .A0(n1704), .A1(n1606), .B0(\BOOTH_instance/n157 ), .Y(
\BOOTH_instance/n160 ) );
AO22XL U2321 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[0] ), .A1(
n2137), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[0] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[0] ) );
XNOR2XL U2322 ( .A(n2111), .B(\ALU_instance/INTERNAL_B[0] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[0] ) );
XOR2XL U2323 ( .A(\ALU_instance/INTERNAL_B[0] ), .B(n2111), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[0] ) );
INVXL U2324 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n138 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ) );
OAI221XL U2325 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n140 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n141 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n138 ) );
INVXL U2326 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n140 ) );
AOI22XL U2327 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n141 ) );
INVXL U2328 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n149 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ) );
OAI221XL U2329 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n150 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n151 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n149 ) );
INVXL U2330 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n150 ) );
AOI22XL U2331 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n151 ) );
AOI22XL U2332 ( .A0(\BOOTH_instance/n352 ), .A1(n2189), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n363 ) );
AOI22XL U2333 ( .A0(\BOOTH_instance/n352 ), .A1(n2187), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n362 ) );
AOI22XL U2334 ( .A0(\BOOTH_instance/n352 ), .A1(n2185), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n361 ) );
AOI22XL U2335 ( .A0(\BOOTH_instance/n352 ), .A1(n2183), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n360 ) );
AOI22XL U2336 ( .A0(\BOOTH_instance/n352 ), .A1(n2181), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n359 ) );
AOI22XL U2337 ( .A0(\BOOTH_instance/n352 ), .A1(n2179), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n358 ) );
AOI22XL U2338 ( .A0(\BOOTH_instance/n352 ), .A1(n2178), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n357 ) );
OAI221XL U2339 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n229 ),
.B0(\BOOTH_instance/n166 ), .B1(n2186), .C0(\BOOTH_instance/n231 ),
.Y(\BOOTH_instance/n223 ) );
AOI22XL U2340 ( .A0(n2187), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n232 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n231 ) );
AOI22XL U2341 ( .A0(\BOOTH_instance/n352 ), .A1(n2177), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n356 ) );
OAI221XL U2342 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n199 ),
.B0(\BOOTH_instance/n166 ), .B1(n2180), .C0(\BOOTH_instance/n201 ),
.Y(\BOOTH_instance/n193 ) );
AOI22XL U2343 ( .A0(n2181), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n202 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n201 ) );
OAI221XL U2344 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n189 ),
.B0(\BOOTH_instance/n166 ), .B1(n1608), .C0(\BOOTH_instance/n191 ),
.Y(\BOOTH_instance/n181 ) );
AOI22XL U2345 ( .A0(n2179), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n192 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n191 ) );
OAI221XL U2346 ( .A0(n1609), .A1(\BOOTH_instance/n158 ), .B0(
\BOOTH_instance/n156 ), .B1(\BOOTH_instance/n166 ), .C0(
\BOOTH_instance/n167 ), .Y(\BOOTH_instance/n162 ) );
AOI22XL U2347 ( .A0(n2177), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n169 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n167 ) );
AOI21XL U2348 ( .A0(n1606), .A1(\BOOTH_instance/n186 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/partial_products[5][12] )
);
INVXL U2349 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ) );
NOR2XL U2350 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n316 ), .Y(
\BOOTH_instance/decoded[8][16] ) );
OA21XL U2351 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ) );
INVXL U2352 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ) );
INVXL U2353 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ) );
INVXL U2354 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ) );
INVXL U2355 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ) );
AO21XL U2356 ( .A0(\BOOTH_instance/n374 ), .A1(n1707), .B0(
\BOOTH_instance/n157 ), .Y(n1700) );
INVXL U2357 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ) );
AND2XL U2358 ( .A(\ALU_instance/INTERNAL_B[12] ), .B(n2179), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[1] ) );
AO22XL U2359 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[21] ) );
AO22XL U2360 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[18] ) );
AO22XL U2361 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[3] ), .A1(
n2137), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[3] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[3] ) );
INVXL U2362 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ) );
AO22XL U2363 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[8] ) );
XNOR2XL U2364 ( .A(n2187), .B(\ALU_instance/INTERNAL_B[8] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[0] ) );
XOR2XL U2365 ( .A(\ALU_instance/INTERNAL_B[8] ), .B(n2187), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[0] ) );
AO22XL U2366 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[22] ) );
AO22XL U2367 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[19] ) );
AO22XL U2368 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[15] ) );
AO22XL U2369 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[2] ), .A1(
n2137), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[2] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[2] ) );
AO22XL U2370 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[12] ) );
XNOR2XL U2371 ( .A(n2179), .B(\ALU_instance/INTERNAL_B[12] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[0] ) );
XOR2XL U2372 ( .A(\ALU_instance/INTERNAL_B[12] ), .B(n2179), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[0] ) );
AO22XL U2373 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[5] ) );
AO22XL U2374 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[23] ) );
AO22XL U2375 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[1] ), .A1(
n2137), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[1] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[1] ) );
AO22XL U2376 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[6] ) );
AO22XL U2377 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[17] ) );
INVXL U2378 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n144 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ) );
OAI221XL U2379 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n145 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n146 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n144 ) );
INVXL U2380 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n145 ) );
AOI22XL U2381 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n146 ) );
INVXL U2382 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n102 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N150 ) );
AOI221XL U2383 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n103 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n102 ) );
INVXL U2384 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n104 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n103 ) );
AOI222XL U2385 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n104 ) );
INVXL U2386 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n129 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N218 ) );
AOI221XL U2387 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n130 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n129 ) );
INVXL U2388 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n131 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n130 ) );
AOI221XL U2389 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n131 ) );
INVXL U2390 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n110 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N120 ) );
AOI221XL U2391 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n111 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n110 ) );
INVXL U2392 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n111 ) );
AOI221XL U2393 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n112 ) );
INVXL U2394 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n95 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N152 ) );
AOI221XL U2395 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n96 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n95 ) );
INVXL U2396 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n96 ) );
AOI222XL U2397 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n97 ) );
INVXL U2398 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N151 ) );
AOI221XL U2399 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n100 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n99 ) );
INVXL U2400 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n101 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n100 ) );
AOI222XL U2401 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n101 ) );
INVXL U2402 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n118 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N149 ) );
AOI221XL U2403 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n119 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n118 ) );
INVXL U2404 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n120 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n119 ) );
AOI222XL U2405 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n120 ) );
INVXL U2406 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n176 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ) );
OAI211XL U2407 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n177 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n176 ) );
AOI22XL U2408 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n177 ) );
INVXL U2409 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n162 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ) );
OAI211XL U2410 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n163 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n162 ) );
AOI22XL U2411 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n163 ) );
INVXL U2412 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ) );
OAI211XL U2413 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n101 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n99 ) );
AOI22XL U2414 ( .A0(n1598), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n101 ) );
AO21XL U2415 ( .A0(\BOOTH_instance/n398 ), .A1(n1698), .B0(
\BOOTH_instance/n157 ), .Y(n1701) );
OR2XL U2416 ( .A(\ALU_instance/INTERNAL_B[12] ), .B(n2179), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2417 ( .A(\ALU_instance/INTERNAL_B[8] ), .B(n2187), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[1] ) );
AND2XL U2418 ( .A(\ALU_instance/INTERNAL_B[8] ), .B(n2187), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[1] ) );
AO22XL U2419 ( .A0(EX_MULT_OUT[1]), .A1(n2145), .B0(EX_ALU_OUT[1]), .B1(
n2144), .Y(N4861) );
OAI222XL U2420 ( .A0(\BOOTH_instance/n316 ), .A1(n2127), .B0(
\BOOTH_instance/n308 ), .B1(n2129), .C0(\BOOTH_instance/n307 ), .C1(
\BOOTH_instance/n447 ), .Y(EX_MULT_OUT[1]) );
OAI2BB1XL U2421 ( .A0N(\ALU_instance/ADDER_OUT[1] ), .A1N(n1599), .B0(
\ALU_instance/n20 ), .Y(EX_ALU_OUT[1]) );
AOI22XL U2422 ( .A0(\ALU_instance/SHIFTER_OUT[1] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[1] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n20 ) );
AO22XL U2423 ( .A0(EX_MULT_OUT[3]), .A1(n2145), .B0(EX_ALU_OUT[3]), .B1(
n2144), .Y(N4863) );
OAI2BB1XL U2424 ( .A0N(\ALU_instance/ADDER_OUT[3] ), .A1N(n1599), .B0(
\ALU_instance/n18 ), .Y(EX_ALU_OUT[3]) );
AOI22XL U2425 ( .A0(\ALU_instance/SHIFTER_OUT[3] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[3] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n18 ) );
OAI2B2XL U2426 ( .A1N(n2175), .A0(\ALU_instance/LOGIC_GENERIC_I/n51 ), .B0(
n2175), .B1(\ALU_instance/LOGIC_GENERIC_I/n52 ), .Y(
\ALU_instance/LOGIC_OUT[3] ) );
OAI2BB1XL U2427 ( .A0N(\ALU_instance/ADDER_OUT[2] ), .A1N(n1599), .B0(
\ALU_instance/n19 ), .Y(EX_ALU_OUT[2]) );
AOI22XL U2428 ( .A0(\ALU_instance/SHIFTER_OUT[2] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[2] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n19 ) );
AO22XL U2429 ( .A0(EX_MULT_OUT[4]), .A1(n2145), .B0(EX_ALU_OUT[4]), .B1(
n2144), .Y(N4864) );
XOR2XL U2430 ( .A(\BOOTH_instance/partial_products[8][4] ), .B(
\BOOTH_instance/partial_products[7][4] ), .Y(EX_MULT_OUT[4]) );
OAI2BB1XL U2431 ( .A0N(\ALU_instance/ADDER_OUT[4] ), .A1N(n1599), .B0(
\ALU_instance/n17 ), .Y(EX_ALU_OUT[4]) );
AOI22XL U2432 ( .A0(\ALU_instance/SHIFTER_OUT[4] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[4] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n17 ) );
INVXL U2433 ( .A(n2141), .Y(n2143) );
AOI221XL U2434 ( .A0(n1708), .A1(n1530), .B0(n1523), .B1(n1548), .C0(n1558),
.Y(n1546) );
AOI222XL U2435 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .C1(n1597), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ) );
AOI222XL U2436 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .C1(n1597), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ) );
AOI221XL U2437 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ), .A1(n1598),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ), .B1(n1597), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ) );
AOI221XL U2438 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ), .A1(n1598),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ), .B1(n1597), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ) );
AOI221XL U2439 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ), .A1(n1598),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ) );
OR2XL U2440 ( .A(EX_SHIFTER_CW[0]), .B(\ALU_instance/SHIFTER_GENERIC_I/n89 ),
.Y(n1702) );
OAI221XL U2441 ( .A0(n2122), .A1(n1670), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(n1608), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n127 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ) );
AOI22XL U2442 ( .A0(n2179), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2181), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n127 ) );
AOI221XL U2443 ( .A0(n2124), .A1(n2187), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2185), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n62 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ) );
OAI2B2XL U2444 ( .A1N(n2189), .A0(n1644), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ), .B1(n1643), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n62 ) );
AOI221XL U2445 ( .A0(n2124), .A1(n2189), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2187), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n98 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ) );
OAI22XL U2446 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ), .A1(n1644),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .B1(n1643), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n98 ) );
AOI221XL U2447 ( .A0(n2124), .A1(n2185), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2183), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n53 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ) );
AO22XL U2448 ( .A0(n2187), .A1(n2125), .B0(n2189), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n53 ) );
OAI221XL U2449 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n143 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n144 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N147 ) );
INVXL U2450 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n143 ) );
AOI222XL U2451 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n144 ) );
OAI221XL U2452 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n115 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N119 ) );
AOI222XL U2453 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n115 ) );
OAI221XL U2454 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n118 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N118 ) );
AOI222XL U2455 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n118 ) );
AOI22XL U2456 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .A1(n1597),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .B1(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ) );
AOI22XL U2457 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .A1(n1597),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B1(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ) );
OAI221XL U2458 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n37 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N141 ) );
AOI222XL U2459 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n37 ) );
OAI221XL U2460 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n22 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N144 ) );
AOI222XL U2461 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n22 ) );
OAI221XL U2462 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n108 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n109 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N222 ) );
INVXL U2463 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n108 ) );
AOI222XL U2464 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n109 ) );
OAI221XL U2465 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n13 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n15 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N145 ) );
INVXL U2466 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n13 ) );
AOI222XL U2467 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n15 ) );
OAI2B2XL U2468 ( .A1N(n2164), .A0(\ALU_instance/LOGIC_GENERIC_I/n126 ), .B0(
n2163), .B1(\ALU_instance/LOGIC_GENERIC_I/n127 ), .Y(
\ALU_instance/LOGIC_OUT[0] ) );
NAND2XL U2469 ( .A(n2195), .B(n2112), .Y(\ALU_instance/LOGIC_GENERIC_I/n127 ) );
AOI22XL U2470 ( .A0(n2194), .A1(\BOOTH_instance/n316 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n126 ) );
NAND2XL U2471 ( .A(n2195), .B(n2190), .Y(\ALU_instance/LOGIC_GENERIC_I/n49 )
);
MXI2XL U2472 ( .A(n2113), .B(\BOOTH_instance/n307 ), .S0(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ) );
NOR2BXL U2473 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ) );
NOR2XL U2474 ( .A(n2173), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ) );
OAI2B11XL U2475 ( .A1N(\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .A0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n123 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n124 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N148 ) );
AOI22XL U2476 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n124 ) );
AOI32XL U2477 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ), .A1(n1600),
.A2(n2171), .B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n123 ) );
AOI22XL U2478 ( .A0(n2195), .A1(n2186), .B0(EX_LOGIC_CW[3]), .B1(n2185), .Y(
\ALU_instance/LOGIC_GENERIC_I/n33 ) );
AOI22XL U2479 ( .A0(n2194), .A1(n1670), .B0(n2177), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n111 ) );
AOI22XL U2480 ( .A0(n2194), .A1(n1608), .B0(n2178), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n114 ) );
AOI22XL U2481 ( .A0(n2194), .A1(n2180), .B0(n2179), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n117 ) );
AOI22XL U2482 ( .A0(n2194), .A1(n2182), .B0(n2181), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n120 ) );
AOI22XL U2483 ( .A0(n2195), .A1(n2188), .B0(n2187), .B1(n2197), .Y(
\ALU_instance/LOGIC_GENERIC_I/n36 ) );
AOI22XL U2484 ( .A0(n2195), .A1(n1607), .B0(n2189), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n39 ) );
AOI22XL U2485 ( .A0(n2194), .A1(n2192), .B0(N4721), .B1(n2197), .Y(
\ALU_instance/LOGIC_GENERIC_I/n51 ) );
OAI221XL U2486 ( .A0(\BOOTH_instance/n307 ), .A1(n2128), .B0(n2113), .B1(
n2129), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n175 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ) );
AOI22XL U2487 ( .A0(n2130), .A1(n2193), .B0(N4721), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n175 ) );
OAI221XL U2488 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n1608),
.B0(n2123), .B1(n2180), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n149 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ) );
AOI22XL U2489 ( .A0(n2181), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2183), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n149 )
);
OAI221XL U2490 ( .A0(n2122), .A1(n2180), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2182), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ) );
AOI22XL U2491 ( .A0(n2183), .A1(n2125), .B0(n2185), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n84 ) );
OAI221XL U2492 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n114 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ) );
AOI22XL U2493 ( .A0(n2177), .A1(n2125), .B0(n2178), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n114 ) );
OAI221XL U2494 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ), .B0(n2123), .B1(n1670),
.C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n156 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ) );
AOI22XL U2495 ( .A0(n2178), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2179), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n156 )
);
NOR2XL U2496 ( .A(n2176), .B(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ) );
AOI2B1XL U2497 ( .A1N(n2114), .A0(n2161), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ) );
NOR2XL U2498 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N166 ) );
OA21XL U2499 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ) );
OA21XL U2500 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ) );
OA21XL U2501 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ) );
OA21XL U2502 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ), .A1(n1697),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ) );
NOR2XL U2503 ( .A(n2162), .B(n2176), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ) );
NAND2XL U2504 ( .A(n2174), .B(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ) );
NOR2XL U2505 ( .A(n1600), .B(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ) );
INVXL U2506 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ) );
INVXL U2507 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ) );
NOR2XL U2508 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n55 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N167 ) );
NAND2XL U2509 ( .A(n2195), .B(n2183), .Y(\ALU_instance/LOGIC_GENERIC_I/n124 ) );
NAND2XL U2510 ( .A(n2195), .B(n2185), .Y(\ALU_instance/LOGIC_GENERIC_I/n34 )
);
NAND2XL U2511 ( .A(n2195), .B(n2181), .Y(\ALU_instance/LOGIC_GENERIC_I/n121 ) );
NAND2XL U2512 ( .A(n2195), .B(n2189), .Y(\ALU_instance/LOGIC_GENERIC_I/n40 )
);
NAND2XL U2513 ( .A(n2196), .B(n2178), .Y(\ALU_instance/LOGIC_GENERIC_I/n115 ) );
NAND2XL U2514 ( .A(n2195), .B(N4721), .Y(\ALU_instance/LOGIC_GENERIC_I/n52 )
);
NAND2XL U2515 ( .A(n2196), .B(n2177), .Y(\ALU_instance/LOGIC_GENERIC_I/n112 ) );
NAND2XL U2516 ( .A(n2195), .B(n2179), .Y(\ALU_instance/LOGIC_GENERIC_I/n118 ) );
NAND2XL U2517 ( .A(n2195), .B(n2187), .Y(\ALU_instance/LOGIC_GENERIC_I/n37 )
);
NAND2XL U2518 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ) );
NAND2XL U2519 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ) );
NAND2XL U2520 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ) );
NAND2XL U2521 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ) );
NOR2XL U2522 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n156 ), .Y(
\BOOTH_instance/decoded[8][31] ) );
NAND2XL U2523 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ) );
NAND2XL U2524 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ) );
NAND2XL U2525 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ) );
NAND2XL U2526 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ), .B(
n1600), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ) );
INVXL U2527 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n78 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ) );
OAI211XL U2528 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n82 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n78 ) );
AOI22XL U2529 ( .A0(n1598), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n82 ) );
INVXL U2530 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n85 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ) );
OAI211XL U2531 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n87 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n85 ) );
AOI22XL U2532 ( .A0(n1598), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n87 ) );
CLKINVX2 U2533 ( .A(n1600), .Y(n2175) );
INVXL U2534 ( .A(EX_SHIFTER_CW[0]), .Y(\ALU_instance/SHIFTER_GENERIC_I/n88 )
);
INVXL U2535 ( .A(EX_ALU_SEL[1]), .Y(\ALU_instance/n23 ) );
CLKINVX2 U2536 ( .A(n2165), .Y(n2164) );
AND2XL U2537 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ), .B(
n2162), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ) );
AND2XL U2538 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ), .B(
n2162), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ) );
AND2XL U2539 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ), .B(
n2162), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ) );
AND2XL U2540 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ), .B(
n2162), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ) );
CLKBUFX1 U2541 ( .A(n2173), .Y(n2172) );
AND2XL U2542 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N165 ) );
INVXL U2543 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ) );
AND2XL U2544 ( .A(n2112), .B(n2166), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ) );
CLKBUFX1 U2545 ( .A(n1616), .Y(n2132) );
INVXL U2546 ( .A(n1536), .Y(n1548) );
NOR2XL U2547 ( .A(n1197), .B(n1478), .Y(n1190) );
CLKINVX1 U2548 ( .A(n1292), .Y(n1227) );
CLKBUFX1 U2549 ( .A(n1225), .Y(n2147) );
INVXL U2550 ( .A(n1485), .Y(n1479) );
NAND2XL U2551 ( .A(n1619), .B(n1310), .Y(n1207) );
NOR2XL U2552 ( .A(n1440), .B(n1190), .Y(n1199) );
INVXL U2553 ( .A(n1368), .Y(n1367) );
INVXL U2554 ( .A(n1338), .Y(n1495) );
NAND2XL U2555 ( .A(WB_DATA_EXT_8[9]), .B(n1330), .Y(n1208) );
CLKBUFX1 U2556 ( .A(\WB_SIGN_EXT_16_instance/n27 ), .Y(n2110) );
INVXL U2557 ( .A(n1493), .Y(n1507) );
AOI22XL U2558 ( .A0(\BOOTH_instance/n188 ), .A1(n2116), .B0(
\BOOTH_instance/n176 ), .B1(\BOOTH_instance/n320 ), .Y(
\BOOTH_instance/n319 ) );
AOI222XL U2559 ( .A0(EX_COMPARATOR_CW[1]), .A1(
\ALU_instance/COMPARATOR_GENERIC_I/n6 ), .B0(EX_COMPARATOR_CW[2]),
.B1(\ALU_instance/COMPARATOR_GENERIC_I/n7 ), .C0(EX_COMPARATOR_CW[5]),
.C1(\ALU_instance/COMPARATOR_GENERIC_I/n8 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n5 ) );
OAI31XL U2560 ( .A0(n1537), .A1(n1374), .A2(n1542), .B0(n1543), .Y(
EX_COMPARATOR_CW[2]) );
INVXL U2561 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n7 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n8 ) );
INVXL U2562 ( .A(\ALU_instance/ZERO ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n6 ) );
AOI221XL U2563 ( .A0(N4719), .A1(\BOOTH_instance/n326 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n327 ), .C0(
\BOOTH_instance/n343 ), .Y(\BOOTH_instance/n342 ) );
OAI22XL U2564 ( .A0(\BOOTH_instance/n328 ), .A1(n1647), .B0(
\BOOTH_instance/n323 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n343 ) );
INVXL U2565 ( .A(\BOOTH_instance/n404 ), .Y(\BOOTH_instance/decoded[2][6] )
);
XNOR2XL U2566 ( .A(\BOOTH_instance/n347 ), .B(N4836), .Y(
\BOOTH_instance/n348 ) );
XNOR2XL U2567 ( .A(N4841), .B(\BOOTH_instance/n318 ), .Y(
\BOOTH_instance/n317 ) );
XNOR2XL U2568 ( .A(N4833), .B(\BOOTH_instance/n396 ), .Y(
\BOOTH_instance/n395 ) );
XNOR2XL U2569 ( .A(N4835), .B(\BOOTH_instance/n372 ), .Y(
\BOOTH_instance/n371 ) );
XNOR2XL U2570 ( .A(n690), .B(n1593), .Y(\BOOTH_instance/n443 ) );
OAI22XL U2571 ( .A0(\BOOTH_instance/n373 ), .A1(n1647), .B0(
\BOOTH_instance/n374 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n379 ) );
OAI22XL U2572 ( .A0(\BOOTH_instance/n421 ), .A1(n1647), .B0(
\BOOTH_instance/n422 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n431 ) );
OR3XL U2573 ( .A(N4837), .B(N4836), .C(\BOOTH_instance/n345 ), .Y(n1703) );
OR3XL U2574 ( .A(n1648), .B(N4839), .C(\BOOTH_instance/n318 ), .Y(n1704) );
OR3XL U2575 ( .A(\BOOTH_instance/n346 ), .B(n1648), .C(\BOOTH_instance/n347 ), .Y(n1705) );
AOI22XL U2576 ( .A0(\BOOTH_instance/n352 ), .A1(n2118), .B0(
\BOOTH_instance/n353 ), .B1(n1596), .Y(\BOOTH_instance/n365 ) );
AOI22XL U2577 ( .A0(\BOOTH_instance/n352 ), .A1(n2120), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n364 ) );
NAND3XL U2578 ( .A(N4834), .B(\BOOTH_instance/n346 ), .C(N4835), .Y(
\BOOTH_instance/n355 ) );
NAND3XL U2579 ( .A(N4832), .B(\BOOTH_instance/n372 ), .C(N4833), .Y(
\BOOTH_instance/n382 ) );
AOI22XL U2580 ( .A0(\BOOTH_instance/n400 ), .A1(n2117), .B0(
\BOOTH_instance/n401 ), .B1(n1596), .Y(\BOOTH_instance/n418 ) );
AOI22XL U2581 ( .A0(\BOOTH_instance/n400 ), .A1(n2119), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n417 ) );
NAND3XL U2582 ( .A(N4839), .B(\BOOTH_instance/n318 ), .C(n1648), .Y(
\BOOTH_instance/n175 ) );
INVXL U2583 ( .A(N4834), .Y(\BOOTH_instance/n372 ) );
NAND3XL U2584 ( .A(n1580), .B(n1565), .C(n1584), .Y(n1555) );
NAND3XL U2585 ( .A(n1575), .B(n1580), .C(n1528), .Y(n1557) );
NAND3XL U2586 ( .A(n1580), .B(n1577), .C(n1575), .Y(n1545) );
NAND2XL U2587 ( .A(n1575), .B(n1576), .Y(n1568) );
AOI32XL U2588 ( .A0(EX_ALU_SEL[0]), .A1(\ALU_instance/n23 ), .A2(
\ALU_instance/COMPARATOR_OUT[0] ), .B0(\ALU_instance/SHIFTER_OUT[0] ),
.B1(n2138), .Y(\ALU_instance/n22 ) );
NAND2XL U2589 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n85 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n86 ), .Y(
\ALU_instance/SHIFTER_OUT[0] ) );
NAND2XL U2590 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n4 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n5 ), .Y(
\ALU_instance/COMPARATOR_OUT[0] ) );
NAND2XL U2591 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N234 ), .B(n1614), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n85 ) );
OR2XL U2592 ( .A(\ALU_instance/INTERNAL_B[0] ), .B(n2111), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[1] ) );
INVXL U2593 ( .A(\BOOTH_instance/n369 ), .Y(\BOOTH_instance/decoded[4][10] )
);
AOI221XL U2594 ( .A0(n2115), .A1(\BOOTH_instance/n352 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n353 ), .C0(
\BOOTH_instance/n370 ), .Y(\BOOTH_instance/n369 ) );
OAI22XL U2595 ( .A0(\BOOTH_instance/n349 ), .A1(n1647), .B0(
\BOOTH_instance/n350 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n370 ) );
AO22XL U2596 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[28] ) );
XNOR2XL U2597 ( .A(n1690), .B(\ALU_instance/INTERNAL_B[28] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[0] ) );
XOR2XL U2598 ( .A(\ALU_instance/INTERNAL_B[28] ), .B(n1690), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[0] ) );
AO22XL U2599 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[24] ) );
XNOR2XL U2600 ( .A(n1685), .B(\ALU_instance/INTERNAL_B[24] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[0] ) );
XOR2XL U2601 ( .A(\ALU_instance/INTERNAL_B[24] ), .B(n1685), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[0] ) );
OAI2BB1XL U2602 ( .A0N(n1528), .A1N(n1399), .B0(n1525), .Y(n1558) );
XOR2XL U2603 ( .A(N4839), .B(n1648), .Y(\BOOTH_instance/n322 ) );
OR3XL U2604 ( .A(N4834), .B(N4835), .C(\BOOTH_instance/n346 ), .Y(n1706) );
OR3XL U2605 ( .A(N4832), .B(N4833), .C(\BOOTH_instance/n372 ), .Y(n1707) );
AND3XL U2606 ( .A(n1577), .B(n1566), .C(n1563), .Y(n1708) );
INVXL U2607 ( .A(n1581), .Y(n1567) );
INVXL U2608 ( .A(N4837), .Y(\BOOTH_instance/n347 ) );
INVXL U2609 ( .A(n1569), .Y(n1400) );
OR2XL U2610 ( .A(n1397), .B(n1528), .Y(n1547) );
OR2XL U2611 ( .A(\ALU_instance/INTERNAL_B[4] ), .B(n2190), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[1] ) );
AND2XL U2612 ( .A(\ALU_instance/INTERNAL_B[0] ), .B(n2111), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[1] ) );
AND2XL U2613 ( .A(\ALU_instance/INTERNAL_B[4] ), .B(n2190), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[1] ) );
INVXL U2614 ( .A(\BOOTH_instance/n430 ), .Y(\BOOTH_instance/decoded[1][4] )
);
AOI221XL U2615 ( .A0(n2115), .A1(\BOOTH_instance/n424 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n425 ), .C0(
\BOOTH_instance/n431 ), .Y(\BOOTH_instance/n430 ) );
OAI221XL U2616 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n421 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n426 ), .Y(\BOOTH_instance/decoded[1][8] ) );
OAI222XL U2617 ( .A0(\BOOTH_instance/n249 ), .A1(n2127), .B0(
\BOOTH_instance/n239 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n2188), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N217 ) );
AOI22XL U2618 ( .A0(\BOOTH_instance/n424 ), .A1(n2118), .B0(
\BOOTH_instance/n425 ), .B1(n1596), .Y(\BOOTH_instance/n426 ) );
INVXL U2619 ( .A(\BOOTH_instance/n378 ), .Y(\BOOTH_instance/decoded[3][8] )
);
OAI221XL U2620 ( .A0(n2191), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n402 ), .Y(\BOOTH_instance/decoded[2][8] ) );
AOI221XL U2621 ( .A0(n2116), .A1(\BOOTH_instance/n376 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n377 ), .C0(
\BOOTH_instance/n379 ), .Y(\BOOTH_instance/n378 ) );
OAI221XL U2622 ( .A0(n1607), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n423 ), .Y(\BOOTH_instance/decoded[1][9] ) );
OAI222XL U2623 ( .A0(\BOOTH_instance/n239 ), .A1(n2127), .B0(
\BOOTH_instance/n229 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n2186), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N218 ) );
AOI22XL U2624 ( .A0(\BOOTH_instance/n424 ), .A1(n2120), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n423 ) );
OAI221XL U2625 ( .A0(n2188), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n442 ), .Y(\BOOTH_instance/decoded[1][10] ) );
OAI222XL U2626 ( .A0(\BOOTH_instance/n229 ), .A1(n2127), .B0(
\BOOTH_instance/n219 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n2184), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N219 ) );
AOI22XL U2627 ( .A0(\BOOTH_instance/n424 ), .A1(n2189), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n442 ) );
OAI221XL U2628 ( .A0(n2184), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n440 ), .Y(\BOOTH_instance/decoded[1][12] ) );
OAI222XL U2629 ( .A0(\BOOTH_instance/n209 ), .A1(n2127), .B0(
\BOOTH_instance/n199 ), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ),
.C0(n2180), .C1(\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N221 ) );
AOI22XL U2630 ( .A0(\BOOTH_instance/n424 ), .A1(n2185), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n440 ) );
OAI221XL U2631 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n373 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n392 ), .Y(\BOOTH_instance/decoded[3][12] ) );
OAI221XL U2632 ( .A0(n2188), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n416 ), .Y(\BOOTH_instance/decoded[2][12] ) );
AOI22XL U2633 ( .A0(\BOOTH_instance/n376 ), .A1(N4723), .B0(
\BOOTH_instance/n377 ), .B1(n1596), .Y(\BOOTH_instance/n392 ) );
OAI221XL U2634 ( .A0(n1607), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n391 ), .Y(\BOOTH_instance/decoded[3][13] ) );
OAI221XL U2635 ( .A0(n2186), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n415 ), .Y(\BOOTH_instance/decoded[2][13] ) );
AOI22XL U2636 ( .A0(\BOOTH_instance/n376 ), .A1(N4724), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n391 ) );
OAI221XL U2637 ( .A0(n2188), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n390 ), .Y(\BOOTH_instance/decoded[3][14] ) );
OAI221XL U2638 ( .A0(n2184), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n414 ), .Y(\BOOTH_instance/decoded[2][14] ) );
AOI22XL U2639 ( .A0(\BOOTH_instance/n376 ), .A1(n2189), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n390 ) );
OAI221XL U2640 ( .A0(n2184), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n388 ), .Y(\BOOTH_instance/decoded[3][16] ) );
OAI221XL U2641 ( .A0(n2180), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n412 ), .Y(\BOOTH_instance/decoded[2][16] ) );
AOI22XL U2642 ( .A0(\BOOTH_instance/n376 ), .A1(n2185), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n388 ) );
OAI221XL U2643 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n328 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n338 ), .Y(\BOOTH_instance/decoded[5][16] ) );
OAI221XL U2644 ( .A0(n2188), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n363 ), .Y(\BOOTH_instance/decoded[4][16] ) );
AOI22XL U2645 ( .A0(\BOOTH_instance/n326 ), .A1(n2117), .B0(
\BOOTH_instance/n327 ), .B1(n1596), .Y(\BOOTH_instance/n338 ) );
OAI221XL U2646 ( .A0(n1607), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n337 ), .Y(\BOOTH_instance/decoded[5][17] ) );
OAI221XL U2647 ( .A0(n2186), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n362 ), .Y(\BOOTH_instance/decoded[4][17] ) );
AOI22XL U2648 ( .A0(\BOOTH_instance/n326 ), .A1(n2119), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n337 ) );
NOR2XL U2649 ( .A(\BOOTH_instance/n315 ), .B(n1647), .Y(
\BOOTH_instance/decoded[8][18] ) );
OAI221XL U2650 ( .A0(n2188), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n336 ), .Y(\BOOTH_instance/decoded[5][18] ) );
OAI221XL U2651 ( .A0(n2184), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n361 ), .Y(\BOOTH_instance/decoded[4][18] ) );
AOI22XL U2652 ( .A0(\BOOTH_instance/n326 ), .A1(n2189), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n336 ) );
OAI221XL U2653 ( .A0(n2184), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n334 ), .Y(\BOOTH_instance/decoded[5][20] ) );
OAI221XL U2654 ( .A0(n2180), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n359 ), .Y(\BOOTH_instance/decoded[4][20] ) );
AOI22XL U2655 ( .A0(\BOOTH_instance/n326 ), .A1(n2185), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n334 ) );
NOR2XL U2656 ( .A(\BOOTH_instance/n315 ), .B(n2184), .Y(
\BOOTH_instance/decoded[8][26] ) );
INVXL U2657 ( .A(n2111), .Y(n2113) );
AO22XL U2658 ( .A0(EX_MULT_OUT[30]), .A1(n2145), .B0(EX_ALU_OUT[30]), .B1(
n2144), .Y(N4890) );
OAI2BB1XL U2659 ( .A0N(\ALU_instance/ADDER_OUT[30] ), .A1N(n1599), .B0(
\ALU_instance/n24 ), .Y(EX_ALU_OUT[30]) );
AOI22XL U2660 ( .A0(\ALU_instance/SHIFTER_OUT[30] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[30] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n24 ) );
OAI2B2XL U2661 ( .A1N(N4857), .A0(\ALU_instance/LOGIC_GENERIC_I/n57 ), .B0(
N4857), .B1(\ALU_instance/LOGIC_GENERIC_I/n58 ), .Y(
\ALU_instance/LOGIC_OUT[30] ) );
AO22XL U2662 ( .A0(EX_MULT_OUT[29]), .A1(n2145), .B0(EX_ALU_OUT[29]), .B1(
n2144), .Y(N4889) );
OAI2BB1XL U2663 ( .A0N(\ALU_instance/ADDER_OUT[29] ), .A1N(n1599), .B0(
\ALU_instance/n25 ), .Y(EX_ALU_OUT[29]) );
AOI22XL U2664 ( .A0(\ALU_instance/SHIFTER_OUT[29] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[29] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n25 ) );
OAI2B2XL U2665 ( .A1N(N4856), .A0(\ALU_instance/LOGIC_GENERIC_I/n63 ), .B0(
N4856), .B1(\ALU_instance/LOGIC_GENERIC_I/n64 ), .Y(
\ALU_instance/LOGIC_OUT[29] ) );
AO22XL U2666 ( .A0(EX_MULT_OUT[28]), .A1(n2145), .B0(EX_ALU_OUT[28]), .B1(
n2144), .Y(N4888) );
OAI2BB1XL U2667 ( .A0N(\ALU_instance/ADDER_OUT[28] ), .A1N(n1599), .B0(
\ALU_instance/n26 ), .Y(EX_ALU_OUT[28]) );
AOI22XL U2668 ( .A0(\ALU_instance/SHIFTER_OUT[28] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[28] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n26 ) );
OAI2B2XL U2669 ( .A1N(N4855), .A0(\ALU_instance/LOGIC_GENERIC_I/n66 ), .B0(
N4855), .B1(\ALU_instance/LOGIC_GENERIC_I/n67 ), .Y(
\ALU_instance/LOGIC_OUT[28] ) );
AO22XL U2670 ( .A0(EX_MULT_OUT[27]), .A1(n2145), .B0(EX_ALU_OUT[27]), .B1(
n2144), .Y(N4887) );
OAI2BB1XL U2671 ( .A0N(\ALU_instance/ADDER_OUT[27] ), .A1N(n1599), .B0(
\ALU_instance/n27 ), .Y(EX_ALU_OUT[27]) );
AOI22XL U2672 ( .A0(\ALU_instance/SHIFTER_OUT[27] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[27] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n27 ) );
OAI2B2XL U2673 ( .A1N(N4854), .A0(\ALU_instance/LOGIC_GENERIC_I/n69 ), .B0(
N4854), .B1(\ALU_instance/LOGIC_GENERIC_I/n70 ), .Y(
\ALU_instance/LOGIC_OUT[27] ) );
AO22XL U2674 ( .A0(EX_MULT_OUT[26]), .A1(n2145), .B0(EX_ALU_OUT[26]), .B1(
n2144), .Y(N4886) );
OAI2BB1XL U2675 ( .A0N(\ALU_instance/ADDER_OUT[26] ), .A1N(n1599), .B0(
\ALU_instance/n28 ), .Y(EX_ALU_OUT[26]) );
AOI22XL U2676 ( .A0(\ALU_instance/SHIFTER_OUT[26] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[26] ), .B1(n2139), .Y(\ALU_instance/n28 ) );
OAI2B2XL U2677 ( .A1N(N4853), .A0(\ALU_instance/LOGIC_GENERIC_I/n72 ), .B0(
N4853), .B1(\ALU_instance/LOGIC_GENERIC_I/n73 ), .Y(
\ALU_instance/LOGIC_OUT[26] ) );
AO22XL U2678 ( .A0(EX_MULT_OUT[25]), .A1(n2145), .B0(EX_ALU_OUT[25]), .B1(
n2144), .Y(N4885) );
OAI2BB1XL U2679 ( .A0N(\ALU_instance/ADDER_OUT[25] ), .A1N(n1599), .B0(
\ALU_instance/n29 ), .Y(EX_ALU_OUT[25]) );
AOI22XL U2680 ( .A0(\ALU_instance/SHIFTER_OUT[25] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[25] ), .B1(n2139), .Y(\ALU_instance/n29 ) );
OAI2B2XL U2681 ( .A1N(N4852), .A0(\ALU_instance/LOGIC_GENERIC_I/n75 ), .B0(
N4852), .B1(\ALU_instance/LOGIC_GENERIC_I/n76 ), .Y(
\ALU_instance/LOGIC_OUT[25] ) );
AO22XL U2682 ( .A0(EX_MULT_OUT[24]), .A1(n2145), .B0(EX_ALU_OUT[24]), .B1(
n2144), .Y(N4884) );
OAI2BB1XL U2683 ( .A0N(\ALU_instance/ADDER_OUT[24] ), .A1N(n1599), .B0(
\ALU_instance/n30 ), .Y(EX_ALU_OUT[24]) );
AOI22XL U2684 ( .A0(\ALU_instance/SHIFTER_OUT[24] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[24] ), .B1(n2139), .Y(\ALU_instance/n30 )
);
OAI2B2XL U2685 ( .A1N(N4851), .A0(\ALU_instance/LOGIC_GENERIC_I/n78 ), .B0(
N4851), .B1(\ALU_instance/LOGIC_GENERIC_I/n79 ), .Y(
\ALU_instance/LOGIC_OUT[24] ) );
AO22XL U2686 ( .A0(EX_MULT_OUT[23]), .A1(n2145), .B0(EX_ALU_OUT[23]), .B1(
n2144), .Y(N4883) );
OAI2BB1XL U2687 ( .A0N(\ALU_instance/ADDER_OUT[23] ), .A1N(n1599), .B0(
\ALU_instance/n31 ), .Y(EX_ALU_OUT[23]) );
AOI22XL U2688 ( .A0(\ALU_instance/SHIFTER_OUT[23] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[23] ), .B1(n2139), .Y(\ALU_instance/n31 ) );
OAI2B2XL U2689 ( .A1N(N4850), .A0(\ALU_instance/LOGIC_GENERIC_I/n81 ), .B0(
N4850), .B1(\ALU_instance/LOGIC_GENERIC_I/n82 ), .Y(
\ALU_instance/LOGIC_OUT[23] ) );
AO22XL U2690 ( .A0(EX_MULT_OUT[22]), .A1(n2145), .B0(EX_ALU_OUT[22]), .B1(
n2144), .Y(N4882) );
OAI2BB1XL U2691 ( .A0N(\ALU_instance/ADDER_OUT[22] ), .A1N(n1599), .B0(
\ALU_instance/n32 ), .Y(EX_ALU_OUT[22]) );
AOI22XL U2692 ( .A0(\ALU_instance/SHIFTER_OUT[22] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[22] ), .B1(n2139), .Y(\ALU_instance/n32 ) );
OAI2B2XL U2693 ( .A1N(N4849), .A0(\ALU_instance/LOGIC_GENERIC_I/n84 ), .B0(
N4849), .B1(\ALU_instance/LOGIC_GENERIC_I/n85 ), .Y(
\ALU_instance/LOGIC_OUT[22] ) );
AO22XL U2694 ( .A0(EX_MULT_OUT[21]), .A1(n2145), .B0(EX_ALU_OUT[21]), .B1(
n2144), .Y(N4881) );
OAI2BB1XL U2695 ( .A0N(\ALU_instance/ADDER_OUT[21] ), .A1N(n1599), .B0(
\ALU_instance/n33 ), .Y(EX_ALU_OUT[21]) );
AOI22XL U2696 ( .A0(\ALU_instance/SHIFTER_OUT[21] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[21] ), .B1(n2139), .Y(\ALU_instance/n33 ) );
OAI2B2XL U2697 ( .A1N(N4848), .A0(\ALU_instance/LOGIC_GENERIC_I/n87 ), .B0(
N4848), .B1(\ALU_instance/LOGIC_GENERIC_I/n88 ), .Y(
\ALU_instance/LOGIC_OUT[21] ) );
AO22XL U2698 ( .A0(EX_MULT_OUT[20]), .A1(n2145), .B0(EX_ALU_OUT[20]), .B1(
n2144), .Y(N4880) );
OAI2BB1XL U2699 ( .A0N(\ALU_instance/ADDER_OUT[20] ), .A1N(n1599), .B0(
\ALU_instance/n34 ), .Y(EX_ALU_OUT[20]) );
AOI22XL U2700 ( .A0(\ALU_instance/SHIFTER_OUT[20] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[20] ), .B1(n2139), .Y(\ALU_instance/n34 ) );
OAI2B2XL U2701 ( .A1N(N4847), .A0(\ALU_instance/LOGIC_GENERIC_I/n90 ), .B0(
N4847), .B1(\ALU_instance/LOGIC_GENERIC_I/n91 ), .Y(
\ALU_instance/LOGIC_OUT[20] ) );
AO22XL U2702 ( .A0(EX_MULT_OUT[19]), .A1(n2145), .B0(EX_ALU_OUT[19]), .B1(
n2144), .Y(N4879) );
OAI2BB1XL U2703 ( .A0N(\ALU_instance/ADDER_OUT[19] ), .A1N(n1599), .B0(
\ALU_instance/n35 ), .Y(EX_ALU_OUT[19]) );
AOI22XL U2704 ( .A0(\ALU_instance/SHIFTER_OUT[19] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[19] ), .B1(n2139), .Y(\ALU_instance/n35 ) );
OAI2B2XL U2705 ( .A1N(N4846), .A0(\ALU_instance/LOGIC_GENERIC_I/n96 ), .B0(
N4846), .B1(\ALU_instance/LOGIC_GENERIC_I/n97 ), .Y(
\ALU_instance/LOGIC_OUT[19] ) );
AO22XL U2706 ( .A0(EX_MULT_OUT[18]), .A1(n2145), .B0(EX_ALU_OUT[18]), .B1(
n2144), .Y(N4878) );
OAI2BB1XL U2707 ( .A0N(\ALU_instance/ADDER_OUT[18] ), .A1N(n1599), .B0(
\ALU_instance/n36 ), .Y(EX_ALU_OUT[18]) );
AOI22XL U2708 ( .A0(\ALU_instance/SHIFTER_OUT[18] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[18] ), .B1(n2139), .Y(\ALU_instance/n36 ) );
OAI2B2XL U2709 ( .A1N(N4845), .A0(\ALU_instance/LOGIC_GENERIC_I/n99 ), .B0(
N4845), .B1(\ALU_instance/LOGIC_GENERIC_I/n100 ), .Y(
\ALU_instance/LOGIC_OUT[18] ) );
INVXL U2710 ( .A(n1648), .Y(\BOOTH_instance/n345 ) );
INVXL U2711 ( .A(n2167), .Y(n2173) );
OAI221XL U2712 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n120 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ) );
AOI22XL U2713 ( .A0(n1689), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1688), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n120 )
);
OAI221XL U2714 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n124 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ) );
AOI22XL U2715 ( .A0(n1679), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1689), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n124 )
);
OAI221XL U2716 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ),
.B0(n2129), .B1(n1670), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n128 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ) );
AOI22XL U2717 ( .A0(n1684), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1679), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n128 )
);
AOI22XL U2718 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(N4723), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n159 ) );
AOI22XL U2719 ( .A0(n2119), .A1(n2130), .B0(n2189), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n174 ) );
AOI22XL U2720 ( .A0(n2117), .A1(n2130), .B0(N4724), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n179 ) );
AO22XL U2721 ( .A0(n1651), .A1(n2125), .B0(n2177), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n146 ) );
AO22XL U2722 ( .A0(n2177), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2178), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n128 ) );
AO22XL U2723 ( .A0(n2178), .A1(n2125), .B0(n2179), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n156 ) );
OAI221XL U2724 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n94 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ) );
AOI22XL U2725 ( .A0(n1687), .A1(n2130), .B0(n1678), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n94 ) );
OAI221XL U2726 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n102 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ) );
AOI22XL U2727 ( .A0(n1686), .A1(n2130), .B0(n1687), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n102 ) );
OAI221XL U2728 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n107 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ) );
AOI22XL U2729 ( .A0(n1683), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1686), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n107 )
);
OAI221XL U2730 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n114 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ) );
AOI22XL U2731 ( .A0(n1688), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1683), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n114 )
);
OAI221XL U2732 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .B0(n2129), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n141 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ) );
AOI22XL U2733 ( .A0(n1690), .A1(n2125), .B0(n1681), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n141 ) );
OAI221XL U2734 ( .A0(n2128), .A1(n1647), .B0(\BOOTH_instance/n307 ), .B1(
n2129), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n168 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ) );
AOI22XL U2735 ( .A0(n2130), .A1(N4721), .B0(n2190), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n168 ) );
OAI221XL U2736 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n159 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ) );
AOI22XL U2737 ( .A0(n1682), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1690), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n159 ) );
NAND2XL U2738 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n37 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n38 ), .Y(
\ALU_instance/SHIFTER_OUT[31] ) );
NAND2XL U2739 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N265 ), .B(n2134), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n37 ) );
AOI222XL U2740 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N233 ), .A1(n2131),
.B0(n1692), .B1(n1616), .C0(\ALU_instance/SHIFTER_GENERIC_I/N168 ),
.C1(n2133), .Y(\ALU_instance/SHIFTER_GENERIC_I/n38 ) );
OAI221XL U2741 ( .A0(n2127), .A1(n1608), .B0(n2129), .B1(n2180), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n143 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ) );
AOI22XL U2742 ( .A0(n2177), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1651), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n143 ) );
OAI221XL U2743 ( .A0(n2127), .A1(n2182), .B0(n2129), .B1(n2184), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n153 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ) );
AOI22XL U2744 ( .A0(n2179), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n2178), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n153 ) );
OAI221XL U2745 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n159 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ) );
AOI22XL U2746 ( .A0(n1682), .A1(n2125), .B0(n1690), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n159 ) );
OAI221XL U2747 ( .A0(n2127), .A1(n2184), .B0(n2129), .B1(n2186), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n165 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ) );
AOI22XL U2748 ( .A0(n2181), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n2179), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n165 ) );
OAI221XL U2749 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n160 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ) );
AOI22XL U2750 ( .A0(n1679), .A1(n2125), .B0(n1684), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n160 ) );
OAI221XL U2751 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n134 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ) );
AOI22XL U2752 ( .A0(n1685), .A1(n2125), .B0(n1678), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n134 ) );
OAI221XL U2753 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n160 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ) );
AOI22XL U2754 ( .A0(n1679), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1684), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n160 ) );
OAI221XL U2755 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ),
.B0(n2123), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n145 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ) );
AOI22XL U2756 ( .A0(n1678), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1687), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n145 )
);
OAI221XL U2757 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n138 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ) );
AOI22XL U2758 ( .A0(n1690), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1681), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n138 )
);
OAI221XL U2759 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n111 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ) );
AOI22XL U2760 ( .A0(n1680), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1677), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n111 ) );
OAI221XL U2761 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n144 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ) );
AOI22XL U2762 ( .A0(n1678), .A1(n2125), .B0(n1687), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n144 ) );
OAI221XL U2763 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n124 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ) );
AOI22XL U2764 ( .A0(n1687), .A1(n2125), .B0(n1686), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n124 ) );
OAI221XL U2765 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n127 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ) );
AOI22XL U2766 ( .A0(n1689), .A1(n2125), .B0(n1679), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n127 ) );
OAI221XL U2767 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .A1(n1644),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .B1(n1643), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n145 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ) );
AOI22XL U2768 ( .A0(n1683), .A1(n2124), .B0(n1686), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n145 ) );
OAI221XL U2769 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ),
.B0(n2123), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n107 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ) );
AOI22XL U2770 ( .A0(n1687), .A1(n2125), .B0(n1686), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n107 ) );
OAI221XL U2771 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n259 ),
.B0(\BOOTH_instance/n166 ), .B1(\BOOTH_instance/n260 ), .C0(
\BOOTH_instance/n261 ), .Y(\BOOTH_instance/n253 ) );
AOI22XL U2772 ( .A0(n2118), .A1(\BOOTH_instance/n168 ), .B0(n1596), .B1(
\BOOTH_instance/n150 ), .Y(\BOOTH_instance/n261 ) );
OAI221XL U2773 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n249 ),
.B0(\BOOTH_instance/n166 ), .B1(n1607), .C0(\BOOTH_instance/n251 ),
.Y(\BOOTH_instance/n243 ) );
AOI22XL U2774 ( .A0(n2120), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n252 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n251 ) );
OAI221XL U2775 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n219 ),
.B0(\BOOTH_instance/n166 ), .B1(n2184), .C0(\BOOTH_instance/n221 ),
.Y(\BOOTH_instance/n213 ) );
AOI22XL U2776 ( .A0(n2185), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n222 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n221 ) );
OAI221XL U2777 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n148 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ) );
AOI22XL U2778 ( .A0(n1681), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1680), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n148 )
);
OAI221XL U2779 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n158 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ) );
AOI22XL U2780 ( .A0(n1677), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1685), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n158 )
);
AOI22XL U2781 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .A1(n1691),
.B0(n2125), .B1(n1692), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n55 )
);
OAI221XL U2782 ( .A0(\BOOTH_instance/n186 ), .A1(\BOOTH_instance/n260 ),
.B0(n1606), .B1(\BOOTH_instance/n259 ), .C0(\BOOTH_instance/n278 ),
.Y(\BOOTH_instance/n274 ) );
AOI22XL U2783 ( .A0(N4723), .A1(\BOOTH_instance/n188 ), .B0(n1596), .B1(
\BOOTH_instance/n176 ), .Y(\BOOTH_instance/n278 ) );
OAI221XL U2784 ( .A0(\BOOTH_instance/n186 ), .A1(n1607), .B0(n1606), .B1(
\BOOTH_instance/n249 ), .C0(\BOOTH_instance/n268 ), .Y(
\BOOTH_instance/n264 ) );
AOI22XL U2785 ( .A0(N4724), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n252 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n268 ) );
OAI221XL U2786 ( .A0(\BOOTH_instance/n186 ), .A1(n2184), .B0(n1606), .B1(
\BOOTH_instance/n219 ), .C0(\BOOTH_instance/n238 ), .Y(
\BOOTH_instance/n234 ) );
AOI22XL U2787 ( .A0(n2185), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n222 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n238 ) );
OAI221XL U2788 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n158 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ) );
AOI22XL U2789 ( .A0(n1677), .A1(n2125), .B0(n1685), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n158 ) );
OAI221XL U2790 ( .A0(\BOOTH_instance/n155 ), .A1(n1647), .B0(n1721), .B1(
\BOOTH_instance/n290 ), .C0(\BOOTH_instance/n291 ), .Y(
\BOOTH_instance/n283 ) );
AOI22XL U2791 ( .A0(\BOOTH_instance/n292 ), .A1(\BOOTH_instance/n149 ), .B0(
N4721), .B1(\BOOTH_instance/n282 ), .Y(\BOOTH_instance/n291 ) );
AOI222XL U2792 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n150 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n149 ) );
OAI221XL U2793 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(n1647),
.B0(n2129), .B1(n2192), .C0(\ALU_instance/SHIFTER_GENERIC_I/C48/n155 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n150 ) );
AOI22XL U2794 ( .A0(N4719), .A1(n2125), .B0(n2111), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n155 ) );
OAI221XL U2795 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n92 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N106 ) );
AOI222XL U2796 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n93 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n92 ) );
OAI221XL U2797 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(n2192),
.B0(n2129), .B1(n2191), .C0(\ALU_instance/SHIFTER_GENERIC_I/C48/n96 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n93 ) );
AOI22XL U2798 ( .A0(n2193), .A1(n2125), .B0(N4719), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n96 ) );
OAI221XL U2799 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ), .B1(n2173), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n13 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N233 ) );
AOI222XL U2800 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n17 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n13 ) );
OAI221XL U2801 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n24 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n17 ) );
INVXL U2802 ( .A(n1682), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ) );
OAI221XL U2803 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N232 ) );
AOI222XL U2804 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n31 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n29 ) );
OAI221XL U2805 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n34 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n31 ) );
AOI22XL U2806 ( .A0(n1682), .A1(n2130), .B0(n1691), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n34 ) );
OAI221XL U2807 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n38 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N231 ) );
AOI222XL U2808 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n40 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n38 ) );
OAI221XL U2809 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n43 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n40 ) );
AOI22XL U2810 ( .A0(n1690), .A1(n2130), .B0(n1682), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n43 ) );
OAI221XL U2811 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n46 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N230 ) );
AOI222XL U2812 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n48 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n46 ) );
OAI221XL U2813 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n51 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n48 ) );
AOI22XL U2814 ( .A0(n1681), .A1(n2130), .B0(n1690), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n51 ) );
OAI221XL U2815 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ), .B1(n2172), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n80 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N138 ) );
AOI222XL U2816 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n80 ) );
OAI221XL U2817 ( .A0(n2122), .A1(n2191), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(n2192), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n86 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n81 ) );
AOI22XL U2818 ( .A0(n2193), .A1(n2125), .B0(N4719), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n86 ) );
OAI211XL U2819 ( .A0(n1540), .A1(n1539), .B0(n1537), .C0(n1544), .Y(n1553)
);
OAI221XL U2820 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .A1(n1644),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B1(n1643), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n135 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ) );
AOI22XL U2821 ( .A0(n1686), .A1(n2124), .B0(n1687), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n135 ) );
OAI221XL U2822 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n161 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ) );
AOI22XL U2823 ( .A0(n1686), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B1(n1683), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n161 ) );
OAI221XL U2824 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ) );
AOI22XL U2825 ( .A0(n1689), .A1(n2125), .B0(n1679), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n117 ) );
OAI221XL U2826 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n142 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ) );
AOI22XL U2827 ( .A0(n1685), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1678), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n142 )
);
OAI221XL U2828 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n2182),
.B0(n2123), .B1(n2184), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n152 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ) );
AOI22XL U2829 ( .A0(n2185), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2187), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n152 )
);
INVXL U2830 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n161 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ) );
AOI221XL U2831 ( .A0(n2124), .A1(n1687), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1678), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n162 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n161 ) );
OAI2B2XL U2832 ( .A1N(n1686), .A0(n1644), .B0(n1643), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n162 ) );
XOR2XL U2833 ( .A(n2136), .B(N4842), .Y(\ALU_instance/INTERNAL_B[15] ) );
XOR2XL U2834 ( .A(n2136), .B(N4848), .Y(\ALU_instance/INTERNAL_B[21] ) );
XOR2XL U2835 ( .A(n2136), .B(N4844), .Y(\ALU_instance/INTERNAL_B[17] ) );
XOR2XL U2836 ( .A(n2136), .B(N4849), .Y(\ALU_instance/INTERNAL_B[22] ) );
XOR2XL U2837 ( .A(n2136), .B(N4852), .Y(\ALU_instance/INTERNAL_B[25] ) );
XOR2XL U2838 ( .A(n2136), .B(N4845), .Y(\ALU_instance/INTERNAL_B[18] ) );
XOR2XL U2839 ( .A(n2135), .B(N4856), .Y(\ALU_instance/INTERNAL_B[29] ) );
XOR2XL U2840 ( .A(n2136), .B(N4850), .Y(\ALU_instance/INTERNAL_B[23] ) );
XOR2XL U2841 ( .A(n2136), .B(N4853), .Y(\ALU_instance/INTERNAL_B[26] ) );
XOR2XL U2842 ( .A(n2136), .B(N4846), .Y(\ALU_instance/INTERNAL_B[19] ) );
XOR2XL U2843 ( .A(n2135), .B(N4857), .Y(\ALU_instance/INTERNAL_B[30] ) );
XOR2XL U2844 ( .A(n2135), .B(N4854), .Y(\ALU_instance/INTERNAL_B[27] ) );
XOR2XL U2845 ( .A(n2135), .B(\EX_ALU_B[31] ), .Y(
\ALU_instance/INTERNAL_B[31] ) );
INVXL U2846 ( .A(n1561), .Y(n1588) );
AND2XL U2847 ( .A(\ALU_instance/INTERNAL_B[28] ), .B(n1690), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[1] ) );
AO22XL U2848 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[16] ) );
XNOR2XL U2849 ( .A(n1684), .B(\ALU_instance/INTERNAL_B[16] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[0] ) );
XOR2XL U2850 ( .A(\ALU_instance/INTERNAL_B[16] ), .B(n1684), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[0] ) );
AO22XL U2851 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[20] ) );
XNOR2XL U2852 ( .A(n1683), .B(\ALU_instance/INTERNAL_B[20] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[0] ) );
XOR2XL U2853 ( .A(\ALU_instance/INTERNAL_B[20] ), .B(n1683), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[0] ) );
INVXL U2854 ( .A(n1556), .Y(n1544) );
OR3XL U2855 ( .A(N4840), .B(N4841), .C(\BOOTH_instance/n315 ), .Y(n1721) );
INVXL U2856 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N202 ), .Y(n2114) );
OR2XL U2857 ( .A(\ALU_instance/INTERNAL_B[20] ), .B(n1683), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2858 ( .A(\ALU_instance/INTERNAL_B[16] ), .B(n1684), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2859 ( .A(\ALU_instance/INTERNAL_B[24] ), .B(n1685), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2860 ( .A(\ALU_instance/INTERNAL_B[28] ), .B(n1690), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[1] ) );
AND2XL U2861 ( .A(\ALU_instance/INTERNAL_B[20] ), .B(n1683), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[1] ) );
AND2XL U2862 ( .A(\ALU_instance/INTERNAL_B[16] ), .B(n1684), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[1] ) );
AND2XL U2863 ( .A(\ALU_instance/INTERNAL_B[24] ), .B(n1685), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[1] ) );
XOR2XL U2864 ( .A(n2137), .B(N4839), .Y(\ALU_instance/INTERNAL_B[12] ) );
AO22XL U2865 ( .A0(EX_MULT_OUT[5]), .A1(n2145), .B0(EX_ALU_OUT[5]), .B1(
n2144), .Y(N4865) );
OAI2BB1XL U2866 ( .A0N(\ALU_instance/ADDER_OUT[5] ), .A1N(n1599), .B0(
\ALU_instance/n16 ), .Y(EX_ALU_OUT[5]) );
AOI22XL U2867 ( .A0(\ALU_instance/SHIFTER_OUT[5] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[5] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n16 ) );
OAI2B2XL U2868 ( .A1N(N4832), .A0(\ALU_instance/LOGIC_GENERIC_I/n45 ), .B0(
N4832), .B1(\ALU_instance/LOGIC_GENERIC_I/n46 ), .Y(
\ALU_instance/LOGIC_OUT[5] ) );
XOR2XL U2869 ( .A(n2135), .B(N4835), .Y(\ALU_instance/INTERNAL_B[8] ) );
XOR2XL U2870 ( .A(n2136), .B(N4847), .Y(\ALU_instance/INTERNAL_B[20] ) );
XOR2XL U2871 ( .A(n2136), .B(N4843), .Y(\ALU_instance/INTERNAL_B[16] ) );
XOR2XL U2872 ( .A(n2136), .B(N4851), .Y(\ALU_instance/INTERNAL_B[24] ) );
XOR2XL U2873 ( .A(n2135), .B(N4855), .Y(\ALU_instance/INTERNAL_B[28] ) );
AO22XL U2874 ( .A0(EX_MULT_OUT[17]), .A1(n2145), .B0(EX_ALU_OUT[17]), .B1(
n2144), .Y(N4877) );
OAI2BB1XL U2875 ( .A0N(\ALU_instance/ADDER_OUT[17] ), .A1N(n1599), .B0(
\ALU_instance/n37 ), .Y(EX_ALU_OUT[17]) );
AOI22XL U2876 ( .A0(\ALU_instance/SHIFTER_OUT[17] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[17] ), .B1(n2139), .Y(\ALU_instance/n37 ) );
OAI2B2XL U2877 ( .A1N(N4844), .A0(\ALU_instance/LOGIC_GENERIC_I/n102 ), .B0(
N4844), .B1(\ALU_instance/LOGIC_GENERIC_I/n103 ), .Y(
\ALU_instance/LOGIC_OUT[17] ) );
AO22XL U2878 ( .A0(EX_MULT_OUT[16]), .A1(n2145), .B0(EX_ALU_OUT[16]), .B1(
n2144), .Y(N4876) );
OAI2BB1XL U2879 ( .A0N(\ALU_instance/ADDER_OUT[16] ), .A1N(n1599), .B0(
\ALU_instance/n38 ), .Y(EX_ALU_OUT[16]) );
AOI22XL U2880 ( .A0(\ALU_instance/SHIFTER_OUT[16] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[16] ), .B1(n2139), .Y(\ALU_instance/n38 ) );
OAI2B2XL U2881 ( .A1N(N4843), .A0(\ALU_instance/LOGIC_GENERIC_I/n105 ), .B0(
N4843), .B1(\ALU_instance/LOGIC_GENERIC_I/n106 ), .Y(
\ALU_instance/LOGIC_OUT[16] ) );
AO22XL U2882 ( .A0(EX_MULT_OUT[15]), .A1(n2145), .B0(EX_ALU_OUT[15]), .B1(
n2144), .Y(N4875) );
OAI2BB1XL U2883 ( .A0N(\ALU_instance/ADDER_OUT[15] ), .A1N(n1599), .B0(
\ALU_instance/n4 ), .Y(EX_ALU_OUT[15]) );
AOI22XL U2884 ( .A0(\ALU_instance/SHIFTER_OUT[15] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[15] ), .B1(n2139), .Y(\ALU_instance/n4 ) );
OAI2B2XL U2885 ( .A1N(N4842), .A0(\ALU_instance/LOGIC_GENERIC_I/n108 ), .B0(
N4842), .B1(\ALU_instance/LOGIC_GENERIC_I/n109 ), .Y(
\ALU_instance/LOGIC_OUT[15] ) );
AO22XL U2886 ( .A0(EX_MULT_OUT[14]), .A1(n2145), .B0(EX_ALU_OUT[14]), .B1(
n2144), .Y(N4874) );
OAI2BB1XL U2887 ( .A0N(\ALU_instance/ADDER_OUT[14] ), .A1N(n1599), .B0(
\ALU_instance/n7 ), .Y(EX_ALU_OUT[14]) );
AOI22XL U2888 ( .A0(\ALU_instance/SHIFTER_OUT[14] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[14] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n7 ) );
OAI2B2XL U2889 ( .A1N(N4841), .A0(\ALU_instance/LOGIC_GENERIC_I/n111 ), .B0(
N4841), .B1(\ALU_instance/LOGIC_GENERIC_I/n112 ), .Y(
\ALU_instance/LOGIC_OUT[14] ) );
AO22XL U2890 ( .A0(EX_MULT_OUT[13]), .A1(n2145), .B0(EX_ALU_OUT[13]), .B1(
n2144), .Y(N4873) );
OAI2BB1XL U2891 ( .A0N(\ALU_instance/ADDER_OUT[13] ), .A1N(n1599), .B0(
\ALU_instance/n8 ), .Y(EX_ALU_OUT[13]) );
AOI22XL U2892 ( .A0(\ALU_instance/SHIFTER_OUT[13] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[13] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n8 ) );
OAI2B2XL U2893 ( .A1N(N4840), .A0(\ALU_instance/LOGIC_GENERIC_I/n114 ), .B0(
N4840), .B1(\ALU_instance/LOGIC_GENERIC_I/n115 ), .Y(
\ALU_instance/LOGIC_OUT[13] ) );
AO22XL U2894 ( .A0(EX_MULT_OUT[12]), .A1(n2145), .B0(EX_ALU_OUT[12]), .B1(
n2144), .Y(N4872) );
OAI2BB1XL U2895 ( .A0N(\ALU_instance/ADDER_OUT[12] ), .A1N(n1599), .B0(
\ALU_instance/n9 ), .Y(EX_ALU_OUT[12]) );
AOI22XL U2896 ( .A0(\ALU_instance/SHIFTER_OUT[12] ), .A1(n2138), .B0(
\ALU_instance/LOGIC_OUT[12] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n9 ) );
OAI2B2XL U2897 ( .A1N(N4839), .A0(\ALU_instance/LOGIC_GENERIC_I/n117 ), .B0(
N4839), .B1(\ALU_instance/LOGIC_GENERIC_I/n118 ), .Y(
\ALU_instance/LOGIC_OUT[12] ) );
AO22XL U2898 ( .A0(EX_MULT_OUT[11]), .A1(n2145), .B0(EX_ALU_OUT[11]), .B1(
n2144), .Y(N4871) );
OAI2BB1XL U2899 ( .A0N(\ALU_instance/ADDER_OUT[11] ), .A1N(n1599), .B0(
\ALU_instance/n10 ), .Y(EX_ALU_OUT[11]) );
AOI22XL U2900 ( .A0(\ALU_instance/SHIFTER_OUT[11] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[11] ), .B1(n2139), .Y(\ALU_instance/n10 )
);
OAI2B2XL U2901 ( .A1N(n1648), .A0(\ALU_instance/LOGIC_GENERIC_I/n120 ), .B0(
n1648), .B1(\ALU_instance/LOGIC_GENERIC_I/n121 ), .Y(
\ALU_instance/LOGIC_OUT[11] ) );
AO22XL U2902 ( .A0(EX_MULT_OUT[10]), .A1(n2145), .B0(EX_ALU_OUT[10]), .B1(
n2144), .Y(N4870) );
OAI2BB1XL U2903 ( .A0N(\ALU_instance/ADDER_OUT[10] ), .A1N(n1599), .B0(
\ALU_instance/n11 ), .Y(EX_ALU_OUT[10]) );
AOI22XL U2904 ( .A0(\ALU_instance/SHIFTER_OUT[10] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[10] ), .B1(n2139), .Y(\ALU_instance/n11 )
);
OAI2B2XL U2905 ( .A1N(N4837), .A0(\ALU_instance/LOGIC_GENERIC_I/n123 ), .B0(
N4837), .B1(\ALU_instance/LOGIC_GENERIC_I/n124 ), .Y(
\ALU_instance/LOGIC_OUT[10] ) );
AO22XL U2906 ( .A0(EX_MULT_OUT[9]), .A1(n2145), .B0(EX_ALU_OUT[9]), .B1(
n2144), .Y(N4869) );
OAI2BB1XL U2907 ( .A0N(\ALU_instance/ADDER_OUT[9] ), .A1N(n1599), .B0(
\ALU_instance/n12 ), .Y(EX_ALU_OUT[9]) );
AOI22XL U2908 ( .A0(\ALU_instance/SHIFTER_OUT[9] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[9] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n12 ) );
OAI2B2XL U2909 ( .A1N(N4836), .A0(\ALU_instance/LOGIC_GENERIC_I/n33 ), .B0(
N4836), .B1(\ALU_instance/LOGIC_GENERIC_I/n34 ), .Y(
\ALU_instance/LOGIC_OUT[9] ) );
AO22XL U2910 ( .A0(EX_MULT_OUT[8]), .A1(n2145), .B0(EX_ALU_OUT[8]), .B1(
n2144), .Y(N4868) );
OAI2BB1XL U2911 ( .A0N(\ALU_instance/ADDER_OUT[8] ), .A1N(n1599), .B0(
\ALU_instance/n13 ), .Y(EX_ALU_OUT[8]) );
AOI22XL U2912 ( .A0(\ALU_instance/SHIFTER_OUT[8] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[8] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n13 ) );
OAI2B2XL U2913 ( .A1N(N4835), .A0(\ALU_instance/LOGIC_GENERIC_I/n36 ), .B0(
N4835), .B1(\ALU_instance/LOGIC_GENERIC_I/n37 ), .Y(
\ALU_instance/LOGIC_OUT[8] ) );
AO22XL U2914 ( .A0(EX_MULT_OUT[7]), .A1(n2145), .B0(EX_ALU_OUT[7]), .B1(
n2144), .Y(N4867) );
OAI2BB1XL U2915 ( .A0N(\ALU_instance/ADDER_OUT[7] ), .A1N(n1599), .B0(
\ALU_instance/n14 ), .Y(EX_ALU_OUT[7]) );
AOI22XL U2916 ( .A0(\ALU_instance/SHIFTER_OUT[7] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[7] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n14 ) );
OAI2B2XL U2917 ( .A1N(N4834), .A0(\ALU_instance/LOGIC_GENERIC_I/n39 ), .B0(
N4834), .B1(\ALU_instance/LOGIC_GENERIC_I/n40 ), .Y(
\ALU_instance/LOGIC_OUT[7] ) );
AO22XL U2918 ( .A0(EX_MULT_OUT[6]), .A1(n2145), .B0(EX_ALU_OUT[6]), .B1(
n2144), .Y(N4866) );
OAI2BB1XL U2919 ( .A0N(\ALU_instance/ADDER_OUT[6] ), .A1N(n1599), .B0(
\ALU_instance/n15 ), .Y(EX_ALU_OUT[6]) );
AOI22XL U2920 ( .A0(\ALU_instance/SHIFTER_OUT[6] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[6] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n15 ) );
OAI2B2XL U2921 ( .A1N(N4833), .A0(\ALU_instance/LOGIC_GENERIC_I/n42 ), .B0(
N4833), .B1(\ALU_instance/LOGIC_GENERIC_I/n43 ), .Y(
\ALU_instance/LOGIC_OUT[6] ) );
AOI32XL U2922 ( .A0(n1535), .A1(n1398), .A2(n1547), .B0(n1527), .B1(n1534),
.Y(n1531) );
OAI221XL U2923 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .B0(n2129), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n138 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ) );
AOI22XL U2924 ( .A0(n1684), .A1(n2125), .B0(n1651), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n138 ) );
OAI221XL U2925 ( .A0(n2127), .A1(n1670), .B0(n2129), .B1(n1608), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n137 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ) );
AOI22XL U2926 ( .A0(n1651), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1684), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n137 )
);
OAI221XL U2927 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n146 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ) );
AOI22XL U2928 ( .A0(n2125), .A1(n1688), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B1(n1689), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n146 ) );
OAI221XL U2929 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n134 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ) );
AOI22XL U2930 ( .A0(n2125), .A1(n1683), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B1(n1688), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n134 ) );
OAI221XL U2931 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n147 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ) );
AOI22XL U2932 ( .A0(n1681), .A1(n2125), .B0(n1680), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n147 ) );
OAI221XL U2933 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n121 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ) );
AOI22XL U2934 ( .A0(n1680), .A1(n2125), .B0(n1677), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n121 ) );
INVXL U2935 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n61 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ) );
OAI221XL U2936 ( .A0(n2122), .A1(n2186), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2188), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n63 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n61 ) );
AOI22XL U2937 ( .A0(n2189), .A1(n2125), .B0(n2119), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n63 ) );
INVXL U2938 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n87 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ) );
OAI221XL U2939 ( .A0(n2122), .A1(n2188), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(n1607), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n89 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n87 ) );
AOI22XL U2940 ( .A0(N4724), .A1(n2125), .B0(n2117), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n89 ) );
OAI2B2XL U2941 ( .A1N(n1525), .A0(n1708), .B0(n1530), .B1(n1374), .Y(
EX_SHIFTER_CW[0]) );
AOI221XL U2942 ( .A0(n2124), .A1(n2119), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2189), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n163 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ) );
OAI22XL U2943 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .A1(n1644),
.B0(n2191), .B1(n1643), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n163 )
);
OAI31XL U2944 ( .A0(n1544), .A1(n1549), .A2(n1536), .B0(n1557), .Y(
EX_COMPARATOR_CW[5]) );
OAI221XL U2945 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n2192),
.B0(n2123), .B1(n1647), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n155 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n151 ) );
AOI22XL U2946 ( .A0(n2115), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N202 ), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n155 ) );
NAND3XL U2947 ( .A(n1546), .B(n1551), .C(n1552), .Y(EX_ALU_SEL[0]) );
AOI211XL U2948 ( .A0(n1708), .A1(n1553), .B0(EX_COMPARATOR_CW[5]), .C0(
EX_COMPARATOR_CW[1]), .Y(n1552) );
MXI2XL U2949 ( .A(n1691), .B(n1692), .S0(n1643), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ) );
OAI2B2XL U2950 ( .A1N(n1601), .A0(\ALU_instance/LOGIC_GENERIC_I/n93 ), .B0(
n1601), .B1(\ALU_instance/LOGIC_GENERIC_I/n94 ), .Y(
\ALU_instance/LOGIC_OUT[1] ) );
NAND2XL U2951 ( .A(n2195), .B(N4719), .Y(\ALU_instance/LOGIC_GENERIC_I/n94 )
);
AOI22XL U2952 ( .A0(n2194), .A1(\BOOTH_instance/n307 ), .B0(n2115), .B1(
EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n93 ) );
OAI2B2XL U2953 ( .A1N(n2161), .A0(\ALU_instance/LOGIC_GENERIC_I/n60 ), .B0(
n1602), .B1(\ALU_instance/LOGIC_GENERIC_I/n61 ), .Y(
\ALU_instance/LOGIC_OUT[2] ) );
NAND2XL U2954 ( .A(n2195), .B(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n61 )
);
AOI22XL U2955 ( .A0(n2194), .A1(n1647), .B0(n2193), .B1(n2197), .Y(
\ALU_instance/LOGIC_GENERIC_I/n60 ) );
OAI2B2XL U2956 ( .A1N(\EX_ALU_B[31] ), .A0(
\ALU_instance/LOGIC_GENERIC_I/n54 ), .B0(\EX_ALU_B[31] ), .B1(
\ALU_instance/LOGIC_GENERIC_I/n55 ), .Y(\ALU_instance/LOGIC_OUT[31] )
);
NAND2XL U2957 ( .A(n2196), .B(n1692), .Y(\ALU_instance/LOGIC_GENERIC_I/n55 )
);
AOI22XL U2958 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ),
.B0(n1692), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n54 ) );
NOR3XL U2959 ( .A(n1542), .B(n1559), .C(n1560), .Y(n1530) );
AOI22XL U2960 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ),
.B0(n1691), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n57 ) );
AOI22XL U2961 ( .A0(n2196), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ),
.B0(n1682), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n63 ) );
AOI22XL U2962 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ),
.B0(n1690), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n66 ) );
AOI22XL U2963 ( .A0(n2196), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ),
.B0(n1681), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n69 ) );
AOI22XL U2964 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ),
.B0(n1680), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n72 ) );
AOI22XL U2965 ( .A0(n2196), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ),
.B0(n1677), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n75 ) );
AOI22XL U2966 ( .A0(n2196), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ),
.B0(n1685), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n78 ) );
AOI22XL U2967 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ),
.B0(n1678), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n81 ) );
AOI22XL U2968 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ),
.B0(n1687), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n84 ) );
AOI22XL U2969 ( .A0(n2196), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ),
.B0(n1686), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n87 ) );
AOI22XL U2970 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ),
.B0(n1683), .B1(n2197), .Y(\ALU_instance/LOGIC_GENERIC_I/n90 ) );
AOI22XL U2971 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ),
.B0(n1688), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n96 ) );
AOI22XL U2972 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ),
.B0(n1689), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n99 ) );
AOI22XL U2973 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ),
.B0(n1679), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n102 ) );
AOI22XL U2974 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ),
.B0(n1684), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n105 ) );
AOI22XL U2975 ( .A0(n2194), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ),
.B0(n1651), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n108 ) );
AOI22XL U2976 ( .A0(n2194), .A1(n2184), .B0(n2183), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n123 ) );
AOI22XL U2977 ( .A0(n2195), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ),
.B0(N4724), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n42 ) );
AOI22XL U2978 ( .A0(n2195), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ),
.B0(N4723), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n45 ) );
AOI22XL U2979 ( .A0(n1691), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1692), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n24 )
);
OAI221XL U2980 ( .A0(n2122), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n130 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ) );
AOI22XL U2981 ( .A0(n1684), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1651), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n130 )
);
OAI221XL U2982 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .B0(n2123), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n147 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ) );
AOI22XL U2983 ( .A0(n1651), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2177), .B1(n2126), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n147 )
);
NAND2XL U2984 ( .A(n2195), .B(N4723), .Y(\ALU_instance/LOGIC_GENERIC_I/n46 )
);
NAND2XL U2985 ( .A(n2195), .B(N4724), .Y(\ALU_instance/LOGIC_GENERIC_I/n43 )
);
AOI21XL U2986 ( .A0(n2160), .A1(n1692), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ) );
NAND2XL U2987 ( .A(n1708), .B(n1542), .Y(n1536) );
NAND2XL U2988 ( .A(n2196), .B(n1651), .Y(\ALU_instance/LOGIC_GENERIC_I/n109 ) );
NAND2XL U2989 ( .A(n2196), .B(n1678), .Y(\ALU_instance/LOGIC_GENERIC_I/n82 )
);
NAND2XL U2990 ( .A(n2196), .B(n1679), .Y(\ALU_instance/LOGIC_GENERIC_I/n103 ) );
NAND2XL U2991 ( .A(n2196), .B(n1682), .Y(\ALU_instance/LOGIC_GENERIC_I/n64 )
);
NAND2XL U2992 ( .A(n2196), .B(n1681), .Y(\ALU_instance/LOGIC_GENERIC_I/n70 )
);
NAND2XL U2993 ( .A(n2196), .B(n1680), .Y(\ALU_instance/LOGIC_GENERIC_I/n73 )
);
NAND2XL U2994 ( .A(n2196), .B(n1677), .Y(\ALU_instance/LOGIC_GENERIC_I/n76 )
);
NAND2XL U2995 ( .A(n2196), .B(n1689), .Y(\ALU_instance/LOGIC_GENERIC_I/n100 ) );
NAND2XL U2996 ( .A(n2196), .B(n1687), .Y(\ALU_instance/LOGIC_GENERIC_I/n85 )
);
NAND2XL U2997 ( .A(n2196), .B(n1686), .Y(\ALU_instance/LOGIC_GENERIC_I/n88 )
);
NAND2XL U2998 ( .A(n2196), .B(n1688), .Y(\ALU_instance/LOGIC_GENERIC_I/n97 )
);
NAND2XL U2999 ( .A(n2196), .B(n1691), .Y(\ALU_instance/LOGIC_GENERIC_I/n58 )
);
NAND2XL U3000 ( .A(n2196), .B(n1690), .Y(\ALU_instance/LOGIC_GENERIC_I/n67 )
);
NAND2XL U3001 ( .A(n2196), .B(n1685), .Y(\ALU_instance/LOGIC_GENERIC_I/n79 )
);
NAND2XL U3002 ( .A(n2196), .B(n1683), .Y(\ALU_instance/LOGIC_GENERIC_I/n91 )
);
NAND2XL U3003 ( .A(n2196), .B(n1684), .Y(\ALU_instance/LOGIC_GENERIC_I/n106 ) );
INVXL U3004 ( .A(n2117), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ) );
INVXL U3005 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n57 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ) );
OAI221XL U3006 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n59 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n57 ) );
AOI22XL U3007 ( .A0(n1680), .A1(n2130), .B0(n1681), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n59 ) );
INVXL U3008 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n63 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ) );
OAI221XL U3009 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n65 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n63 ) );
AOI22XL U3010 ( .A0(n1677), .A1(n2130), .B0(n1680), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n65 ) );
INVXL U3011 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n77 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ) );
OAI221XL U3012 ( .A0(n2127), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n79 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n77 ) );
AOI22XL U3013 ( .A0(n1685), .A1(n2130), .B0(n1677), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n79 ) );
INVXL U3014 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n85 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ) );
OAI221XL U3015 ( .A0(n2128), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ),
.B0(n2129), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n87 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n85 ) );
AOI22XL U3016 ( .A0(n1678), .A1(n2130), .B0(n1685), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n87 ) );
INVXL U3017 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ) );
OAI221XL U3018 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n2184),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2186), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n53 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n50 ) );
AOI22XL U3019 ( .A0(n2187), .A1(n2125), .B0(n2189), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n53 ) );
INVXL U3020 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n162 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ) );
OAI221XL U3021 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n1607),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\BOOTH_instance/n260 ), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n163 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n162 ) );
AOI22XL U3022 ( .A0(N4723), .A1(n2125), .B0(n2190), .B1(n2126), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n163 ) );
INVXL U3023 ( .A(n2119), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ) );
INVXL U3024 ( .A(n2118), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ) );
INVXL U3025 ( .A(N4723), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ) );
INVXL U3026 ( .A(N4724), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ) );
INVXL U3027 ( .A(n1559), .Y(n1523) );
CLKBUFX1 U3028 ( .A(EX_LOGIC_CW[2]), .Y(n2196) );
INVXL U3029 ( .A(n1688), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ) );
INVXL U3030 ( .A(EX_SHIFTER_CW[1]), .Y(\ALU_instance/SHIFTER_GENERIC_I/n89 )
);
AND2XL U3031 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ), .B(
n1593), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ) );
AND2XL U3032 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ), .B(
n1593), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ) );
INVXL U3033 ( .A(n1692), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ) );
INVXL U3034 ( .A(n1651), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ) );
INVXL U3035 ( .A(n1678), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ) );
INVXL U3036 ( .A(n1679), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ) );
INVXL U3037 ( .A(n1681), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ) );
INVXL U3038 ( .A(n1680), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ) );
INVXL U3039 ( .A(n1677), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ) );
INVXL U3040 ( .A(n1689), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ) );
INVXL U3041 ( .A(n1687), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ) );
INVXL U3042 ( .A(n1686), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ) );
INVXL U3043 ( .A(n1691), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ) );
INVXL U3044 ( .A(n1690), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ) );
INVXL U3045 ( .A(n1685), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ) );
INVXL U3046 ( .A(n1683), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ) );
INVXL U3047 ( .A(n1684), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ) );
NOR2XL U3048 ( .A(n1483), .B(n1293), .Y(n1195) );
AOI21XL U3049 ( .A0(n1290), .A1(n1291), .B0(n1227), .Y(n1225) );
OAI2BB2XL U3050 ( .B0(ID_REGA_ZERO), .B1(n1479), .A0N(n1194), .A1N(
ID_REGA_ZERO), .Y(n1517) );
NOR2XL U3051 ( .A(\zero_instance/n1 ), .B(\zero_instance/n2 ), .Y(
ID_REGA_ZERO) );
NAND4XL U3052 ( .A(\zero_instance/n7 ), .B(\zero_instance/n8 ), .C(
\zero_instance/n9 ), .D(\zero_instance/n10 ), .Y(\zero_instance/n1 )
);
NOR2XL U3053 ( .A(n1290), .B(n1518), .Y(n1485) );
NOR2XL U3054 ( .A(n1370), .B(n1190), .Y(n1498) );
INVXL U3055 ( .A(n1516), .Y(n1478) );
CLKBUFX1 U3056 ( .A(n1226), .Y(n2146) );
CLKBUFX3 U3057 ( .A(n697), .Y(n2156) );
CLKBUFX1 U3058 ( .A(n697), .Y(n2154) );
BUFX2 U3059 ( .A(n697), .Y(n2155) );
INVXL U3060 ( .A(n1291), .Y(n1293) );
INVXL U3061 ( .A(n1358), .Y(N4717) );
BUFX2 U3062 ( .A(n697), .Y(n2157) );
INVXL U3063 ( .A(n1520), .Y(n1197) );
NOR2XL U3064 ( .A(n1484), .B(n1618), .Y(ID_INSTR_AFTER_CU[27]) );
NOR2XL U3065 ( .A(n1481), .B(n1618), .Y(ID_INSTR_AFTER_CU[29]) );
NOR2XL U3066 ( .A(n1488), .B(n1618), .Y(ID_INSTR_AFTER_CU[31]) );
NOR2XL U3067 ( .A(n1205), .B(n1618), .Y(ID_INSTR_AFTER_CU[7]) );
NOR2XL U3068 ( .A(n1204), .B(n1618), .Y(ID_INSTR_AFTER_CU[9]) );
NOR2XL U3069 ( .A(n1203), .B(n1618), .Y(ID_INSTR_AFTER_CU[8]) );
NOR2XL U3070 ( .A(n1433), .B(n1618), .Y(ID_INSTR_AFTER_CU[17]) );
NOR2XL U3071 ( .A(n1432), .B(n1618), .Y(ID_INSTR_AFTER_CU[16]) );
NOR2XL U3072 ( .A(n1434), .B(n1618), .Y(ID_INSTR_AFTER_CU[19]) );
NAND2XL U3073 ( .A(n1522), .B(n1290), .Y(ID_INSTR_AFTER_CU[28]) );
NAND2XL U3074 ( .A(n1522), .B(n1483), .Y(ID_INSTR_AFTER_CU[30]) );
NAND2XL U3075 ( .A(n1522), .B(n1518), .Y(ID_INSTR_AFTER_CU[26]) );
AND2XL U3076 ( .A(n2109), .B(n1522), .Y(ID_INSTR_AFTER_CU[15]) );
OAI32XL U3077 ( .A0(n1373), .A1(n1374), .A2(n1375), .B0(n1376), .B1(n1377),
.Y(n1368) );
OR2XL U3078 ( .A(n1378), .B(n1379), .Y(n1375) );
OAI32XL U3079 ( .A0(n1441), .A1(n1422), .A2(n1442), .B0(n1443), .B1(n1216),
.Y(n1439) );
OR2XL U3080 ( .A(n1446), .B(n1447), .Y(n1442) );
INVXL U3081 ( .A(n1438), .Y(n1443) );
OAI32XL U3082 ( .A0(n1359), .A1(n1360), .A2(n1361), .B0(n1357), .B1(n1362),
.Y(N4712) );
NAND2XL U3083 ( .A(n1194), .B(n1195), .Y(n1359) );
AOI21XL U3084 ( .A0(n1190), .A1(n1363), .B0(n1364), .Y(n1362) );
AOI22XL U3085 ( .A0(n1365), .A1(n1366), .B0(n1367), .B1(n1361), .Y(n1364) );
OAI2B2XL U3086 ( .A1N(n1369), .A0(n1361), .B0(n1376), .B1(n1374), .Y(n1363)
);
XNOR2XL U3087 ( .A(RF_ADD_WR[2]), .B(n1427), .Y(n1474) );
XNOR2XL U3088 ( .A(RF_ADD_WR[1]), .B(n1433), .Y(n1490) );
XNOR2XL U3089 ( .A(RF_ADD_WR[4]), .B(n1407), .Y(n1475) );
OAI2B2XL U3090 ( .A1N(n1360), .A0(n1368), .B0(n1371), .B1(n1372), .Y(n1365)
);
NAND4XL U3091 ( .A(n1343), .B(n1344), .C(n1340), .D(n1348), .Y(n1493) );
NOR3XL U3092 ( .A(n1419), .B(n1435), .C(n1417), .Y(n1413) );
NAND3XL U3093 ( .A(n1344), .B(n1471), .C(n1339), .Y(n1338) );
OAI21XL U3094 ( .A0(n1369), .A1(n1368), .B0(n1370), .Y(n1366) );
INVXL U3095 ( .A(n1435), .Y(n1422) );
OAI211XL U3096 ( .A0(n1328), .A1(n1309), .B0(n1208), .C0(n1329), .Y(N6250)
);
NAND2XL U3097 ( .A(WB_DATA_EXT_16[7]), .B(n2149), .Y(n1329) );
NOR2XL U3098 ( .A(n1822), .B(n1328), .Y(WB_DATA_EXT_16[7]) );
OAI211XL U3099 ( .A0(n1326), .A1(n1309), .B0(n1208), .C0(n1327), .Y(N6251)
);
NAND2XL U3100 ( .A(WB_DATA_EXT_16[8]), .B(n2149), .Y(n1327) );
NOR2XL U3101 ( .A(n1822), .B(n1326), .Y(WB_DATA_EXT_16[8]) );
OAI211XL U3102 ( .A0(n1324), .A1(n1309), .B0(n1208), .C0(n1325), .Y(N6252)
);
NAND2XL U3103 ( .A(WB_DATA_EXT_16[9]), .B(n2149), .Y(n1325) );
NOR2XL U3104 ( .A(n1324), .B(n1822), .Y(WB_DATA_EXT_16[9]) );
OAI211XL U3105 ( .A0(n1322), .A1(n1309), .B0(n1208), .C0(n1323), .Y(N6253)
);
NAND2XL U3106 ( .A(WB_DATA_EXT_16[10]), .B(n2149), .Y(n1323) );
NOR2XL U3107 ( .A(n1822), .B(n1322), .Y(WB_DATA_EXT_16[10]) );
OAI211XL U3108 ( .A0(n1320), .A1(n1309), .B0(n1208), .C0(n1321), .Y(N6254)
);
NAND2XL U3109 ( .A(WB_DATA_EXT_16[11]), .B(n2149), .Y(n1321) );
NOR2XL U3110 ( .A(n1822), .B(n1320), .Y(WB_DATA_EXT_16[11]) );
OAI211XL U3111 ( .A0(n1318), .A1(n1309), .B0(n1208), .C0(n1319), .Y(N6255)
);
NAND2XL U3112 ( .A(WB_DATA_EXT_16[12]), .B(n2149), .Y(n1319) );
NOR2XL U3113 ( .A(n1822), .B(n1318), .Y(WB_DATA_EXT_16[12]) );
OAI211XL U3114 ( .A0(n1316), .A1(n1309), .B0(n1208), .C0(n1317), .Y(N6256)
);
NAND2XL U3115 ( .A(WB_DATA_EXT_16[13]), .B(n2149), .Y(n1317) );
NOR2XL U3116 ( .A(n1822), .B(n1316), .Y(WB_DATA_EXT_16[13]) );
OAI211XL U3117 ( .A0(n1314), .A1(n1309), .B0(n1208), .C0(n1315), .Y(N6257)
);
NAND2XL U3118 ( .A(WB_DATA_EXT_16[14]), .B(n2149), .Y(n1315) );
NOR2XL U3119 ( .A(n1822), .B(n1314), .Y(WB_DATA_EXT_16[14]) );
OAI211XL U3120 ( .A0(n1312), .A1(n1309), .B0(n1208), .C0(n1313), .Y(N6258)
);
NAND2XL U3121 ( .A(WB_DATA_EXT_16[15]), .B(n2149), .Y(n1313) );
INVXL U3122 ( .A(n2110), .Y(WB_DATA_EXT_16[15]) );
AOI31XL U3123 ( .A0(n1194), .A1(n1195), .A2(n1357), .B0(n1358), .Y(N4716) );
INVXL U3124 ( .A(n1328), .Y(WB_DATA_EXT_8[9]) );
INVXL U3125 ( .A(n1312), .Y(WB_DATA_EXT_16[31]) );
NAND2XL U3126 ( .A(WB_DATA_EXT_16[31]), .B(WB_SIGN_EXT_16_CONTROL), .Y(
\WB_SIGN_EXT_16_instance/n27 ) );
OR3XL U3127 ( .A(n1370), .B(n1371), .C(n1372), .Y(n1440) );
NAND3XL U3128 ( .A(n1203), .B(n1204), .C(n1205), .Y(n1202) );
INVXL U3129 ( .A(n1216), .Y(n1417) );
INVXL U3130 ( .A(n1341), .Y(n1330) );
NAND2BXL U3131 ( .AN(PORT_R_W), .B(n1216), .Y(PORT_EN) );
NAND2XL U3132 ( .A(n1445), .B(n1219), .Y(n1213) );
AND3XL U3133 ( .A(n1397), .B(n1398), .C(n1399), .Y(n1357) );
INVXL U3134 ( .A(n1215), .Y(n1212) );
NAND2XL U3135 ( .A(n1199), .B(n1191), .Y(RF_RD1) );
INVXL U3136 ( .A(WB_DATA_EXT_8[0]), .Y(\WB_SIGN_EXT_16_instance/n34 ) );
INVXL U3137 ( .A(WB_DATA_EXT_8[1]), .Y(\WB_SIGN_EXT_16_instance/n33 ) );
INVXL U3138 ( .A(WB_DATA_EXT_8[2]), .Y(\WB_SIGN_EXT_16_instance/n28 ) );
INVXL U3139 ( .A(WB_DATA_EXT_8[3]), .Y(\WB_SIGN_EXT_16_instance/n25 ) );
INVXL U3140 ( .A(WB_DATA_EXT_8[4]), .Y(\WB_SIGN_EXT_16_instance/n24 ) );
INVXL U3141 ( .A(WB_DATA_EXT_8[5]), .Y(\WB_SIGN_EXT_16_instance/n23 ) );
INVXL U3142 ( .A(WB_DATA_EXT_8[6]), .Y(\WB_SIGN_EXT_16_instance/n22 ) );
AND2XL U3143 ( .A(n1214), .B(n1215), .Y(PORT_SIZE[0]) );
OAI2BB1XL U3144 ( .A0N(WB_DATA_EXT_8[0]), .A1N(n1330), .B0(n1337), .Y(N6243)
);
AOI22XL U3145 ( .A0(n1619), .A1(WB_DATA_EXT_8[0]), .B0(WB_DATA_EXT_16[0]),
.B1(n2149), .Y(n1337) );
NOR2XL U3146 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n34 ), .Y(
WB_DATA_EXT_16[0]) );
OAI2BB1XL U3147 ( .A0N(WB_DATA_EXT_8[1]), .A1N(n1330), .B0(n1336), .Y(N6244)
);
AOI22XL U3148 ( .A0(n1619), .A1(WB_DATA_EXT_8[1]), .B0(WB_DATA_EXT_16[1]),
.B1(n1211), .Y(n1336) );
NOR2XL U3149 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n33 ), .Y(
WB_DATA_EXT_16[1]) );
OAI2BB1XL U3150 ( .A0N(WB_DATA_EXT_8[2]), .A1N(n1330), .B0(n1335), .Y(N6245)
);
AOI22XL U3151 ( .A0(n1619), .A1(WB_DATA_EXT_8[2]), .B0(WB_DATA_EXT_16[2]),
.B1(n1211), .Y(n1335) );
NOR2XL U3152 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n28 ), .Y(
WB_DATA_EXT_16[2]) );
OAI2BB1XL U3153 ( .A0N(WB_DATA_EXT_8[3]), .A1N(n1330), .B0(n1334), .Y(N6246)
);
AOI22XL U3154 ( .A0(n1619), .A1(WB_DATA_EXT_8[3]), .B0(WB_DATA_EXT_16[3]),
.B1(n1211), .Y(n1334) );
NOR2XL U3155 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n25 ), .Y(
WB_DATA_EXT_16[3]) );
OAI2BB1XL U3156 ( .A0N(WB_DATA_EXT_8[4]), .A1N(n1330), .B0(n1333), .Y(N6247)
);
AOI22XL U3157 ( .A0(n1619), .A1(WB_DATA_EXT_8[4]), .B0(WB_DATA_EXT_16[4]),
.B1(n1211), .Y(n1333) );
NOR2XL U3158 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n24 ), .Y(
WB_DATA_EXT_16[4]) );
OAI2BB1XL U3159 ( .A0N(WB_DATA_EXT_8[5]), .A1N(n1330), .B0(n1332), .Y(N6248)
);
AOI22XL U3160 ( .A0(n1619), .A1(WB_DATA_EXT_8[5]), .B0(WB_DATA_EXT_16[5]),
.B1(n1211), .Y(n1332) );
NOR2XL U3161 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n23 ), .Y(
WB_DATA_EXT_16[5]) );
OAI2BB1XL U3162 ( .A0N(WB_DATA_EXT_8[6]), .A1N(n1330), .B0(n1331), .Y(N6249)
);
AOI22XL U3163 ( .A0(n1619), .A1(WB_DATA_EXT_8[6]), .B0(WB_DATA_EXT_16[6]),
.B1(n1211), .Y(n1331) );
NOR2XL U3164 ( .A(n1822), .B(\WB_SIGN_EXT_16_instance/n22 ), .Y(
WB_DATA_EXT_16[6]) );
AOI222XL U3165 ( .A0(EX_COMPARATOR_CW[3]), .A1(\ALU_instance/OVERFLOW ),
.B0(EX_COMPARATOR_CW[0]), .B1(\ALU_instance/ZERO ), .C0(
EX_COMPARATOR_CW[4]), .C1(\ALU_instance/COMPARATOR_GENERIC_I/n9 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n4 ) );
OAI31XL U3166 ( .A0(n1539), .A1(n1374), .A2(n1540), .B0(n1541), .Y(
EX_COMPARATOR_CW[3]) );
OAI21XL U3167 ( .A0(n1536), .A1(n1537), .B0(n1538), .Y(EX_COMPARATOR_CW[4])
);
OAI31XL U3168 ( .A0(n1544), .A1(EX_INSTR[2]), .A2(n1536), .B0(n1545), .Y(
EX_COMPARATOR_CW[0]) );
OAI2B11XL U3169 ( .A1N(n1356), .A0(EX_INSTR[26]), .B0(n1374), .C0(n1351),
.Y(n1564) );
OAI22XL U3170 ( .A0(n1567), .A1(n1568), .B0(EX_INSTR[31]), .B1(n1400), .Y(
n1356) );
NOR3XL U3171 ( .A(EX_INSTR[29]), .B(EX_INSTR[30]), .C(n1567), .Y(n1569) );
OAI211XL U3172 ( .A0(n1584), .A1(n1585), .B0(n1581), .C0(EX_INSTR[29]), .Y(
n1543) );
AND2XL U3173 ( .A(n1573), .B(EX_INSTR[30]), .Y(n1585) );
NOR2XL U3174 ( .A(n1565), .B(EX_INSTR[26]), .Y(n1528) );
NAND4XL U3175 ( .A(EX_INSTR[30]), .B(n1577), .C(EX_INSTR[29]), .D(
EX_INSTR[27]), .Y(n1538) );
NAND3XL U3176 ( .A(EX_INSTR[30]), .B(n1580), .C(n1397), .Y(n1541) );
NAND2BXL U3177 ( .AN(n1578), .B(n1611), .Y(n1377) );
AOI33XL U3178 ( .A0(n1580), .A1(EX_INSTR[31]), .A2(n1577), .B0(EX_INSTR[29]),
.B1(n1573), .B2(n1581), .Y(n1578) );
OAI211XL U3179 ( .A0(n1547), .A1(n1577), .B0(EX_INSTR[31]), .C0(n1563), .Y(
n1571) );
AOI2B1XL U3180 ( .A1N(n2153), .A0(EX_REGB[3]), .B0(n1353), .Y(n1352) );
INVXL U3181 ( .A(N4831), .Y(n2168) );
NAND4XL U3182 ( .A(n1563), .B(EX_INSTR[26]), .C(n1565), .D(n1566), .Y(n1351)
);
NOR3XL U3183 ( .A(EX_INSTR[6]), .B(EX_INSTR[10]), .C(n1590), .Y(n1561) );
OR3XL U3184 ( .A(EX_INSTR[9]), .B(EX_INSTR[8]), .C(EX_INSTR[7]), .Y(n1590)
);
NOR3XL U3185 ( .A(n1550), .B(EX_INSTR[1]), .C(n1540), .Y(n1556) );
NAND3BXL U3186 ( .AN(EX_INSTR[4]), .B(EX_INSTR[5]), .C(n1561), .Y(n1550) );
OAI32XL U3187 ( .A0(n1553), .A1(n1582), .A2(n1374), .B0(n1574), .B1(n1583),
.Y(EX_ADD_SUB) );
OAI21XL U3188 ( .A0(n1567), .A1(n1570), .B0(n1374), .Y(n1583) );
NOR3XL U3189 ( .A(n1550), .B(EX_INSTR[2]), .C(n1560), .Y(n1582) );
NAND3XL U3190 ( .A(EX_INSTR[3]), .B(EX_INSTR[5]), .C(n1587), .Y(n1537) );
NOR3XL U3191 ( .A(n1560), .B(EX_INSTR[2]), .C(n1588), .Y(n1587) );
INVXL U3192 ( .A(EX_INSTR[2]), .Y(n1549) );
NAND3XL U3193 ( .A(EX_INSTR[5]), .B(EX_INSTR[0]), .C(n1589), .Y(n1539) );
NOR3XL U3194 ( .A(n1549), .B(EX_INSTR[1]), .C(n1588), .Y(n1589) );
INVXL U3195 ( .A(EX_INSTR[3]), .Y(n1540) );
NAND2XL U3196 ( .A(n1228), .B(n1229), .Y(N760) );
AOI22XL U3197 ( .A0(RF_OUT1[30]), .A1(n1646), .B0(IF_PC_INC[30]), .B1(n1225),
.Y(n1229) );
AOI22XL U3198 ( .A0(ID_PC[30]), .A1(n1226), .B0(ID_PC_SUM[30]), .B1(n1227),
.Y(n1228) );
XOR2XL U3199 ( .A(PORT_PC[30]), .B(\add_502/carry[30] ), .Y(IF_PC_INC[30])
);
NAND2XL U3200 ( .A(n1230), .B(n1231), .Y(N759) );
AOI22XL U3201 ( .A0(RF_OUT1[29]), .A1(n2148), .B0(IF_PC_INC[29]), .B1(n1225),
.Y(n1231) );
AOI22XL U3202 ( .A0(ID_PC[29]), .A1(n1226), .B0(ID_PC_SUM[29]), .B1(n1227),
.Y(n1230) );
XOR2XL U3203 ( .A(PORT_PC[29]), .B(\add_502/carry[29] ), .Y(IF_PC_INC[29])
);
NAND2XL U3204 ( .A(n1232), .B(n1233), .Y(N758) );
AOI22XL U3205 ( .A0(RF_OUT1[28]), .A1(n1646), .B0(IF_PC_INC[28]), .B1(n2147),
.Y(n1233) );
AOI22XL U3206 ( .A0(ID_PC[28]), .A1(n1226), .B0(ID_PC_SUM[28]), .B1(n1227),
.Y(n1232) );
XOR2XL U3207 ( .A(PORT_PC[28]), .B(\add_502/carry[28] ), .Y(IF_PC_INC[28])
);
NAND2XL U3208 ( .A(n1234), .B(n1235), .Y(N757) );
AOI22XL U3209 ( .A0(RF_OUT1[27]), .A1(n2148), .B0(IF_PC_INC[27]), .B1(n1225),
.Y(n1235) );
AOI22XL U3210 ( .A0(ID_PC[27]), .A1(n1226), .B0(ID_PC_SUM[27]), .B1(n1227),
.Y(n1234) );
XOR2XL U3211 ( .A(PORT_PC[27]), .B(\add_502/carry[27] ), .Y(IF_PC_INC[27])
);
NAND2XL U3212 ( .A(n1236), .B(n1237), .Y(N756) );
AOI22XL U3213 ( .A0(RF_OUT1[26]), .A1(n2148), .B0(IF_PC_INC[26]), .B1(n1225),
.Y(n1237) );
AOI22XL U3214 ( .A0(ID_PC[26]), .A1(n1226), .B0(ID_PC_SUM[26]), .B1(n1227),
.Y(n1236) );
XOR2XL U3215 ( .A(PORT_PC[26]), .B(\add_502/carry[26] ), .Y(IF_PC_INC[26])
);
NAND2XL U3216 ( .A(n1238), .B(n1239), .Y(N755) );
AOI22XL U3217 ( .A0(RF_OUT1[25]), .A1(n1646), .B0(IF_PC_INC[25]), .B1(n2147),
.Y(n1239) );
AOI22XL U3218 ( .A0(RF_ADD_RD1[4]), .A1(n1226), .B0(ID_PC_SUM[25]), .B1(
n1227), .Y(n1238) );
XOR2XL U3219 ( .A(PORT_PC[25]), .B(\add_502/carry[25] ), .Y(IF_PC_INC[25])
);
NAND2XL U3220 ( .A(n1222), .B(n1223), .Y(N761) );
AOI22XL U3221 ( .A0(RF_OUT1[31]), .A1(n2148), .B0(IF_PC_INC[31]), .B1(n1225),
.Y(n1223) );
AOI22XL U3222 ( .A0(ID_PC[31]), .A1(n2146), .B0(ID_PC_SUM[31]), .B1(n1227),
.Y(n1222) );
XOR2XL U3223 ( .A(PORT_PC[31]), .B(\add_502/carry[31] ), .Y(IF_PC_INC[31])
);
AND2XL U3224 ( .A(ID_PC[2]), .B(ID_IMM16_SHL2[2]), .Y(\add_545/carry[3] ) );
AOI33XL U3225 ( .A0(n1535), .A1(EX_INSTR[27]), .A2(n1528), .B0(n1548), .B1(
EX_INSTR[1]), .B2(n1534), .Y(n1533) );
OAI31XL U3226 ( .A0(n1554), .A1(EX_INSTR[2]), .A2(n1374), .B0(n1555), .Y(
EX_COMPARATOR_CW[1]) );
NAND2XL U3227 ( .A(n1556), .B(EX_INSTR[0]), .Y(n1554) );
NOR3XL U3228 ( .A(n1549), .B(EX_INSTR[3]), .C(n1550), .Y(n1534) );
OAI21XL U3229 ( .A0(n1523), .A1(n1374), .B0(n1524), .Y(EX_SHIFTER_CW[1]) );
AOI31XL U3230 ( .A0(n1525), .A1(n1374), .A2(n1526), .B0(n1527), .Y(n1524) );
NAND3XL U3231 ( .A(n1528), .B(EX_INSTR[27]), .C(n1399), .Y(n1526) );
AOI33XL U3232 ( .A0(n1527), .A1(EX_INSTR[0]), .A2(n1534), .B0(n1397), .B1(
n1398), .B2(n1535), .Y(n1532) );
NAND3XL U3233 ( .A(EX_INSTR[2]), .B(n1561), .C(n1562), .Y(n1559) );
NOR3XL U3234 ( .A(EX_INSTR[3]), .B(EX_INSTR[5]), .C(EX_INSTR[4]), .Y(n1562)
);
NOR2XL U3235 ( .A(n1374), .B(EX_INSTR[1]), .Y(n1527) );
INVXL U3236 ( .A(EX_INSTR[0]), .Y(n1542) );
NAND2XL U3237 ( .A(n1240), .B(n1241), .Y(N754) );
AOI22XL U3238 ( .A0(RF_OUT1[24]), .A1(n1646), .B0(IF_PC_INC[24]), .B1(n1225),
.Y(n1241) );
AOI22XL U3239 ( .A0(RF_ADD_RD1[3]), .A1(n2146), .B0(ID_PC_SUM[24]), .B1(
n1227), .Y(n1240) );
XOR2XL U3240 ( .A(PORT_PC[24]), .B(\add_502/carry[24] ), .Y(IF_PC_INC[24])
);
NAND2XL U3241 ( .A(n1242), .B(n1243), .Y(N753) );
AOI22XL U3242 ( .A0(RF_OUT1[23]), .A1(n2148), .B0(IF_PC_INC[23]), .B1(n2147),
.Y(n1243) );
AOI22XL U3243 ( .A0(RF_ADD_RD1[2]), .A1(n1226), .B0(ID_PC_SUM[23]), .B1(
n1227), .Y(n1242) );
XOR2XL U3244 ( .A(PORT_PC[23]), .B(\add_502/carry[23] ), .Y(IF_PC_INC[23])
);
NAND2XL U3245 ( .A(n1244), .B(n1245), .Y(N752) );
AOI22XL U3246 ( .A0(RF_OUT1[22]), .A1(n2148), .B0(IF_PC_INC[22]), .B1(n2147),
.Y(n1245) );
AOI22XL U3247 ( .A0(RF_ADD_RD1[1]), .A1(n2146), .B0(ID_PC_SUM[22]), .B1(
n1227), .Y(n1244) );
XOR2XL U3248 ( .A(PORT_PC[22]), .B(\add_502/carry[22] ), .Y(IF_PC_INC[22])
);
NAND2XL U3249 ( .A(n1246), .B(n1247), .Y(N751) );
AOI22XL U3250 ( .A0(RF_OUT1[21]), .A1(n2148), .B0(IF_PC_INC[21]), .B1(n2147),
.Y(n1247) );
AOI22XL U3251 ( .A0(RF_ADD_RD1[0]), .A1(n2146), .B0(ID_PC_SUM[21]), .B1(
n1227), .Y(n1246) );
XOR2XL U3252 ( .A(PORT_PC[21]), .B(\add_502/carry[21] ), .Y(IF_PC_INC[21])
);
NAND2XL U3253 ( .A(n1248), .B(n1249), .Y(N750) );
AOI22XL U3254 ( .A0(RF_OUT1[20]), .A1(n2148), .B0(IF_PC_INC[20]), .B1(n2147),
.Y(n1249) );
AOI22XL U3255 ( .A0(RF_ADD_RD2[4]), .A1(n2146), .B0(ID_PC_SUM[20]), .B1(
n1227), .Y(n1248) );
XOR2XL U3256 ( .A(PORT_PC[20]), .B(\add_502/carry[20] ), .Y(IF_PC_INC[20])
);
NAND2XL U3257 ( .A(n1250), .B(n1251), .Y(N749) );
AOI22XL U3258 ( .A0(RF_OUT1[19]), .A1(n2148), .B0(IF_PC_INC[19]), .B1(n2147),
.Y(n1251) );
AOI22XL U3259 ( .A0(RF_ADD_RD2[3]), .A1(n2146), .B0(ID_PC_SUM[19]), .B1(
n1227), .Y(n1250) );
XOR2XL U3260 ( .A(PORT_PC[19]), .B(\add_502/carry[19] ), .Y(IF_PC_INC[19])
);
NAND2XL U3261 ( .A(n1252), .B(n1253), .Y(N748) );
AOI22XL U3262 ( .A0(RF_OUT1[18]), .A1(n1646), .B0(IF_PC_INC[18]), .B1(n2147),
.Y(n1253) );
AOI22XL U3263 ( .A0(RF_ADD_RD2[2]), .A1(n2146), .B0(ID_PC_SUM[18]), .B1(
n1227), .Y(n1252) );
XOR2XL U3264 ( .A(PORT_PC[18]), .B(\add_502/carry[18] ), .Y(IF_PC_INC[18])
);
NAND2XL U3265 ( .A(n1254), .B(n1255), .Y(N747) );
AOI22XL U3266 ( .A0(RF_OUT1[17]), .A1(n1646), .B0(IF_PC_INC[17]), .B1(n2147),
.Y(n1255) );
AOI22XL U3267 ( .A0(RF_ADD_RD2[1]), .A1(n2146), .B0(ID_PC_SUM[17]), .B1(
n1227), .Y(n1254) );
XOR2XL U3268 ( .A(PORT_PC[17]), .B(\add_502/carry[17] ), .Y(IF_PC_INC[17])
);
NAND2XL U3269 ( .A(n1256), .B(n1257), .Y(N746) );
AOI22XL U3270 ( .A0(RF_OUT1[16]), .A1(n1646), .B0(IF_PC_INC[16]), .B1(n2147),
.Y(n1257) );
AOI22XL U3271 ( .A0(RF_ADD_RD2[0]), .A1(n2146), .B0(ID_PC_SUM[16]), .B1(
n1227), .Y(n1256) );
XOR2XL U3272 ( .A(PORT_PC[16]), .B(\add_502/carry[16] ), .Y(IF_PC_INC[16])
);
NAND2XL U3273 ( .A(n1258), .B(n1259), .Y(N745) );
AOI22XL U3274 ( .A0(RF_OUT1[15]), .A1(n2148), .B0(IF_PC_INC[15]), .B1(n2147),
.Y(n1259) );
AOI22XL U3275 ( .A0(n2109), .A1(n2146), .B0(ID_PC_SUM[15]), .B1(n1227), .Y(
n1258) );
XOR2XL U3276 ( .A(PORT_PC[15]), .B(\add_502/carry[15] ), .Y(IF_PC_INC[15])
);
NAND2XL U3277 ( .A(n1260), .B(n1261), .Y(N744) );
AOI22XL U3278 ( .A0(RF_OUT1[14]), .A1(n1646), .B0(IF_PC_INC[14]), .B1(n2147),
.Y(n1261) );
AOI22XL U3279 ( .A0(ID_IMM16_SHL2[16]), .A1(n2146), .B0(ID_PC_SUM[14]), .B1(
n1227), .Y(n1260) );
XOR2XL U3280 ( .A(PORT_PC[14]), .B(\add_502/carry[14] ), .Y(IF_PC_INC[14])
);
NAND2XL U3281 ( .A(n1262), .B(n1263), .Y(N743) );
AOI22XL U3282 ( .A0(RF_OUT1[13]), .A1(n1646), .B0(IF_PC_INC[13]), .B1(n2147),
.Y(n1263) );
AOI22XL U3283 ( .A0(ID_IMM16_SHL2[15]), .A1(n2146), .B0(ID_PC_SUM[13]), .B1(
n1227), .Y(n1262) );
XOR2XL U3284 ( .A(PORT_PC[13]), .B(\add_502/carry[13] ), .Y(IF_PC_INC[13])
);
NAND2XL U3285 ( .A(n1264), .B(n1265), .Y(N742) );
AOI22XL U3286 ( .A0(RF_OUT1[12]), .A1(n1646), .B0(IF_PC_INC[12]), .B1(n2147),
.Y(n1265) );
AOI22XL U3287 ( .A0(ID_IMM16_SHL2[14]), .A1(n2146), .B0(ID_PC_SUM[12]), .B1(
n1227), .Y(n1264) );
XOR2XL U3288 ( .A(PORT_PC[12]), .B(\add_502/carry[12] ), .Y(IF_PC_INC[12])
);
NAND2XL U3289 ( .A(n1266), .B(n1267), .Y(N741) );
AOI22XL U3290 ( .A0(RF_OUT1[11]), .A1(n1646), .B0(IF_PC_INC[11]), .B1(n2147),
.Y(n1267) );
AOI22XL U3291 ( .A0(ID_IMM16_SHL2[13]), .A1(n2146), .B0(ID_PC_SUM[11]), .B1(
n1227), .Y(n1266) );
XOR2XL U3292 ( .A(PORT_PC[11]), .B(\add_502/carry[11] ), .Y(IF_PC_INC[11])
);
NAND2XL U3293 ( .A(n1268), .B(n1269), .Y(N740) );
AOI22XL U3294 ( .A0(RF_OUT1[10]), .A1(n1646), .B0(IF_PC_INC[10]), .B1(n2147),
.Y(n1269) );
AOI22XL U3295 ( .A0(ID_IMM16_SHL2[12]), .A1(n2146), .B0(ID_PC_SUM[10]), .B1(
n1227), .Y(n1268) );
XOR2XL U3296 ( .A(PORT_PC[10]), .B(\add_502/carry[10] ), .Y(IF_PC_INC[10])
);
AND2XL U3297 ( .A(PORT_PC[2]), .B(PORT_PC[3]), .Y(\add_502/carry[4] ) );
AND2XL U3298 ( .A(\add_502/carry[29] ), .B(PORT_PC[29]), .Y(
\add_502/carry[30] ) );
AND2XL U3299 ( .A(\add_502/carry[28] ), .B(PORT_PC[28]), .Y(
\add_502/carry[29] ) );
AND2XL U3300 ( .A(\add_502/carry[27] ), .B(PORT_PC[27]), .Y(
\add_502/carry[28] ) );
AND2XL U3301 ( .A(\add_502/carry[26] ), .B(PORT_PC[26]), .Y(
\add_502/carry[27] ) );
AND2XL U3302 ( .A(\add_502/carry[25] ), .B(PORT_PC[25]), .Y(
\add_502/carry[26] ) );
AND2XL U3303 ( .A(\add_502/carry[24] ), .B(PORT_PC[24]), .Y(
\add_502/carry[25] ) );
AND2XL U3304 ( .A(\add_502/carry[23] ), .B(PORT_PC[23]), .Y(
\add_502/carry[24] ) );
AND2XL U3305 ( .A(\add_502/carry[22] ), .B(PORT_PC[22]), .Y(
\add_502/carry[23] ) );
AND2XL U3306 ( .A(\add_502/carry[21] ), .B(PORT_PC[21]), .Y(
\add_502/carry[22] ) );
AND2XL U3307 ( .A(\add_502/carry[20] ), .B(PORT_PC[20]), .Y(
\add_502/carry[21] ) );
AND2XL U3308 ( .A(\add_502/carry[19] ), .B(PORT_PC[19]), .Y(
\add_502/carry[20] ) );
AND2XL U3309 ( .A(\add_502/carry[18] ), .B(PORT_PC[18]), .Y(
\add_502/carry[19] ) );
AND2XL U3310 ( .A(\add_502/carry[17] ), .B(PORT_PC[17]), .Y(
\add_502/carry[18] ) );
AND2XL U3311 ( .A(\add_502/carry[16] ), .B(PORT_PC[16]), .Y(
\add_502/carry[17] ) );
AND2XL U3312 ( .A(\add_502/carry[15] ), .B(PORT_PC[15]), .Y(
\add_502/carry[16] ) );
AND2XL U3313 ( .A(\add_502/carry[14] ), .B(PORT_PC[14]), .Y(
\add_502/carry[15] ) );
AND2XL U3314 ( .A(\add_502/carry[13] ), .B(PORT_PC[13]), .Y(
\add_502/carry[14] ) );
AND2XL U3315 ( .A(\add_502/carry[12] ), .B(PORT_PC[12]), .Y(
\add_502/carry[13] ) );
AND2XL U3316 ( .A(\add_502/carry[11] ), .B(PORT_PC[11]), .Y(
\add_502/carry[12] ) );
AND2XL U3317 ( .A(\add_502/carry[10] ), .B(PORT_PC[10]), .Y(
\add_502/carry[11] ) );
AND2XL U3318 ( .A(\add_502/carry[9] ), .B(PORT_PC[9]), .Y(
\add_502/carry[10] ) );
AND2XL U3319 ( .A(\add_502/carry[8] ), .B(PORT_PC[8]), .Y(\add_502/carry[9] ) );
AND2XL U3320 ( .A(\add_502/carry[7] ), .B(PORT_PC[7]), .Y(\add_502/carry[8] ) );
AND2XL U3321 ( .A(\add_502/carry[6] ), .B(PORT_PC[6]), .Y(\add_502/carry[7] ) );
AND2XL U3322 ( .A(\add_502/carry[5] ), .B(PORT_PC[5]), .Y(\add_502/carry[6] ) );
AND2XL U3323 ( .A(\add_502/carry[4] ), .B(PORT_PC[4]), .Y(\add_502/carry[5] ) );
AND2XL U3324 ( .A(\add_502/carry[30] ), .B(PORT_PC[30]), .Y(
\add_502/carry[31] ) );
AOI21XL U3325 ( .A0(ID_INSTR_28), .A1(n1481), .B0(n1520), .Y(n1521) );
NOR3XL U3326 ( .A(n1478), .B(ID_INSTR_28), .C(n1518), .Y(n1358) );
NOR4XL U3327 ( .A(RF_OUT1[27]), .B(RF_OUT1[26]), .C(RF_OUT1[25]), .D(
RF_OUT1[24]), .Y(\zero_instance/n7 ) );
NOR4XL U3328 ( .A(RF_OUT1[23]), .B(RF_OUT1[22]), .C(RF_OUT1[21]), .D(
RF_OUT1[20]), .Y(\zero_instance/n6 ) );
NOR4XL U3329 ( .A(RF_OUT1[9]), .B(RF_OUT1[8]), .C(RF_OUT1[7]), .D(RF_OUT1[6]), .Y(\zero_instance/n10 ) );
NOR4XL U3330 ( .A(RF_OUT1[30]), .B(RF_OUT1[2]), .C(RF_OUT1[29]), .D(
RF_OUT1[28]), .Y(\zero_instance/n8 ) );
NOR4XL U3331 ( .A(RF_OUT1[5]), .B(RF_OUT1[4]), .C(RF_OUT1[3]), .D(
RF_OUT1[31]), .Y(\zero_instance/n9 ) );
NOR2XL U3332 ( .A(n1290), .B(ID_INSTR_26), .Y(n1194) );
NOR2XL U3333 ( .A(ID_INSTR_26), .B(ID_INSTR_28), .Y(n1520) );
NAND4XL U3334 ( .A(\zero_instance/n3 ), .B(\zero_instance/n4 ), .C(
\zero_instance/n5 ), .D(\zero_instance/n6 ), .Y(\zero_instance/n2 ) );
NOR4XL U3335 ( .A(RF_OUT1[12]), .B(RF_OUT1[11]), .C(RF_OUT1[10]), .D(
RF_OUT1[0]), .Y(\zero_instance/n3 ) );
NOR4XL U3336 ( .A(RF_OUT1[16]), .B(RF_OUT1[15]), .C(RF_OUT1[14]), .D(
RF_OUT1[13]), .Y(\zero_instance/n4 ) );
NOR4XL U3337 ( .A(RF_OUT1[1]), .B(RF_OUT1[19]), .C(RF_OUT1[18]), .D(
RF_OUT1[17]), .Y(\zero_instance/n5 ) );
NAND2XL U3338 ( .A(ID_INSTR_31), .B(n1483), .Y(n1196) );
INVXL U3339 ( .A(ID_INSTR_27), .Y(n1484) );
INVXL U3340 ( .A(ID_INSTR_29), .Y(n1481) );
INVXL U3341 ( .A(ID_INSTR_31), .Y(n1488) );
INVXL U3342 ( .A(ID_IMM16_SHL2[9]), .Y(n1205) );
INVXL U3343 ( .A(ID_IMM16_SHL2[11]), .Y(n1204) );
INVXL U3344 ( .A(ID_IMM16_SHL2[10]), .Y(n1203) );
INVXL U3345 ( .A(RF_ADD_RD2[1]), .Y(n1433) );
AND2XL U3346 ( .A(ID_SIGN_EXT_CONTROL), .B(n2109), .Y(\ID_IMM16_EXT[31] ) );
NAND4XL U3347 ( .A(n1498), .B(n1515), .C(N4717), .D(n1292), .Y(
ID_SIGN_EXT_CONTROL) );
OAI211XL U3348 ( .A0(n1519), .A1(n1520), .B0(n1488), .C0(ID_INSTR_29), .Y(
n1515) );
AOI21XL U3349 ( .A0(ID_INSTR_28), .A1(ID_INSTR_27), .B0(n1483), .Y(n1519) );
NAND2XL U3350 ( .A(n1286), .B(n1287), .Y(N731) );
AOI22XL U3351 ( .A0(n2146), .A1(ID_IMM16_SHL2[3]), .B0(ID_PC_SUM[1]), .B1(
n1227), .Y(n1286) );
AOI22XL U3352 ( .A0(RF_OUT1[1]), .A1(n2148), .B0(IF_PC_INC[1]), .B1(n2147),
.Y(n1287) );
NAND2XL U3353 ( .A(n1288), .B(n1289), .Y(N730) );
AOI22XL U3354 ( .A0(ID_IMM16_SHL2[2]), .A1(n2146), .B0(ID_PC_SUM[0]), .B1(
n1227), .Y(n1288) );
AOI22XL U3355 ( .A0(RF_OUT1[0]), .A1(n2148), .B0(IF_PC_INC[0]), .B1(n2147),
.Y(n1289) );
NAND2XL U3356 ( .A(n1270), .B(n1271), .Y(N739) );
AOI22XL U3357 ( .A0(RF_OUT1[9]), .A1(n1646), .B0(IF_PC_INC[9]), .B1(n2147),
.Y(n1271) );
AOI22XL U3358 ( .A0(ID_IMM16_SHL2[11]), .A1(n2146), .B0(ID_PC_SUM[9]), .B1(
n1227), .Y(n1270) );
XOR2XL U3359 ( .A(PORT_PC[9]), .B(\add_502/carry[9] ), .Y(IF_PC_INC[9]) );
NAND2XL U3360 ( .A(n1272), .B(n1273), .Y(N738) );
AOI22XL U3361 ( .A0(ID_IMM16_SHL2[10]), .A1(n2146), .B0(ID_PC_SUM[8]), .B1(
n1227), .Y(n1272) );
AOI22XL U3362 ( .A0(RF_OUT1[8]), .A1(n1646), .B0(IF_PC_INC[8]), .B1(n2147),
.Y(n1273) );
XOR2XL U3363 ( .A(PORT_PC[8]), .B(\add_502/carry[8] ), .Y(IF_PC_INC[8]) );
NAND2XL U3364 ( .A(n1274), .B(n1275), .Y(N737) );
AOI22XL U3365 ( .A0(ID_IMM16_SHL2[9]), .A1(n2146), .B0(ID_PC_SUM[7]), .B1(
n1227), .Y(n1274) );
AOI22XL U3366 ( .A0(RF_OUT1[7]), .A1(n1646), .B0(IF_PC_INC[7]), .B1(n2147),
.Y(n1275) );
XOR2XL U3367 ( .A(PORT_PC[7]), .B(\add_502/carry[7] ), .Y(IF_PC_INC[7]) );
NAND2XL U3368 ( .A(n1276), .B(n1277), .Y(N736) );
AOI22XL U3369 ( .A0(ID_IMM16_SHL2[8]), .A1(n2146), .B0(ID_PC_SUM[6]), .B1(
n1227), .Y(n1276) );
AOI22XL U3370 ( .A0(RF_OUT1[6]), .A1(n2148), .B0(IF_PC_INC[6]), .B1(n2147),
.Y(n1277) );
XOR2XL U3371 ( .A(PORT_PC[6]), .B(\add_502/carry[6] ), .Y(IF_PC_INC[6]) );
NAND2XL U3372 ( .A(n1278), .B(n1279), .Y(N735) );
AOI22XL U3373 ( .A0(ID_IMM16_SHL2[7]), .A1(n2146), .B0(ID_PC_SUM[5]), .B1(
n1227), .Y(n1278) );
AOI22XL U3374 ( .A0(RF_OUT1[5]), .A1(n2148), .B0(IF_PC_INC[5]), .B1(n2147),
.Y(n1279) );
XOR2XL U3375 ( .A(PORT_PC[5]), .B(\add_502/carry[5] ), .Y(IF_PC_INC[5]) );
NAND2XL U3376 ( .A(n1280), .B(n1281), .Y(N734) );
AOI22XL U3377 ( .A0(ID_IMM16_SHL2[6]), .A1(n2146), .B0(ID_PC_SUM[4]), .B1(
n1227), .Y(n1280) );
AOI22XL U3378 ( .A0(RF_OUT1[4]), .A1(n2148), .B0(IF_PC_INC[4]), .B1(n2147),
.Y(n1281) );
XOR2XL U3379 ( .A(PORT_PC[4]), .B(\add_502/carry[4] ), .Y(IF_PC_INC[4]) );
NAND2XL U3380 ( .A(n1282), .B(n1283), .Y(N733) );
AOI22XL U3381 ( .A0(n2146), .A1(ID_IMM16_SHL2[5]), .B0(ID_PC_SUM[3]), .B1(
n1227), .Y(n1282) );
AOI22XL U3382 ( .A0(RF_OUT1[3]), .A1(n2148), .B0(IF_PC_INC[3]), .B1(n2147),
.Y(n1283) );
XOR2XL U3383 ( .A(PORT_PC[3]), .B(PORT_PC[2]), .Y(IF_PC_INC[3]) );
NAND2XL U3384 ( .A(n1284), .B(n1285), .Y(N732) );
AOI22XL U3385 ( .A0(n2146), .A1(ID_IMM16_SHL2[4]), .B0(ID_PC_SUM[2]), .B1(
n1227), .Y(n1284) );
AOI22XL U3386 ( .A0(RF_OUT1[2]), .A1(n2148), .B0(IF_PC_INC[2]), .B1(n2147),
.Y(n1285) );
XOR2XL U3387 ( .A(ID_IMM16_SHL2[2]), .B(ID_PC[2]), .Y(ID_PC_SUM[2]) );
OR4XL U3388 ( .A(n1196), .B(n1484), .C(n1518), .D(ID_INSTR_28), .Y(n1198) );
INVXL U3389 ( .A(RF_ADD_RD2[3]), .Y(n1434) );
INVXL U3390 ( .A(RF_ADD_RD2[0]), .Y(n1432) );
NOR2BXL U3391 ( .AN(RF_ADD_RD2[2]), .B(n1618), .Y(ID_INSTR_AFTER_CU[18]) );
NOR2BXL U3392 ( .AN(RF_ADD_RD2[4]), .B(n1618), .Y(ID_INSTR_AFTER_CU[20]) );
INVXL U3393 ( .A(PORT_PC[2]), .Y(IF_PC_INC[2]) );
NAND2BXL U3394 ( .AN(PORT_INSTR_IRAM[26]), .B(n2154), .Y(N790) );
NAND2BXL U3395 ( .AN(PORT_INSTR_IRAM[30]), .B(n2154), .Y(N794) );
NAND2BXL U3396 ( .AN(PORT_INSTR_IRAM[28]), .B(n2154), .Y(N792) );
AND2XL U3397 ( .A(ID_IMM16_SHL2[5]), .B(n1522), .Y(ID_INSTR_AFTER_CU[3]) );
AND2XL U3398 ( .A(ID_IMM16_SHL2[3]), .B(n1522), .Y(ID_INSTR_AFTER_CU[1]) );
AND2XL U3399 ( .A(ID_IMM16_SHL2[12]), .B(n1522), .Y(ID_INSTR_AFTER_CU[10])
);
AND2XL U3400 ( .A(ID_IMM16_SHL2[8]), .B(n1522), .Y(ID_INSTR_AFTER_CU[6]) );
AND2XL U3401 ( .A(ID_IMM16_SHL2[6]), .B(n1522), .Y(ID_INSTR_AFTER_CU[4]) );
AND2XL U3402 ( .A(ID_IMM16_SHL2[7]), .B(n1522), .Y(ID_INSTR_AFTER_CU[5]) );
AND2XL U3403 ( .A(ID_IMM16_SHL2[4]), .B(n1522), .Y(ID_INSTR_AFTER_CU[2]) );
AND2XL U3404 ( .A(ID_IMM16_SHL2[2]), .B(n1522), .Y(ID_INSTR_AFTER_CU[0]) );
AND2XL U3405 ( .A(ID_IMM16_SHL2[15]), .B(n1522), .Y(ID_INSTR_AFTER_CU[13])
);
AND2XL U3406 ( .A(ID_IMM16_SHL2[14]), .B(n1522), .Y(ID_INSTR_AFTER_CU[12])
);
AND2XL U3407 ( .A(ID_IMM16_SHL2[13]), .B(n1522), .Y(ID_INSTR_AFTER_CU[11])
);
AND2XL U3408 ( .A(ID_IMM16_SHL2[16]), .B(n1522), .Y(ID_INSTR_AFTER_CU[14])
);
AND2XL U3409 ( .A(PORT_INSTR_IRAM[25]), .B(n2154), .Y(N789) );
AND2XL U3410 ( .A(PORT_INSTR_IRAM[16]), .B(n2154), .Y(N780) );
AND2XL U3411 ( .A(PORT_INSTR_IRAM[17]), .B(n2154), .Y(N781) );
AND2XL U3412 ( .A(PORT_INSTR_IRAM[31]), .B(n2154), .Y(N795) );
AND2XL U3413 ( .A(PORT_INSTR_IRAM[27]), .B(n2154), .Y(N791) );
AND2XL U3414 ( .A(PORT_INSTR_IRAM[0]), .B(n2155), .Y(N764) );
AND2XL U3415 ( .A(PORT_INSTR_IRAM[29]), .B(n2154), .Y(N793) );
AND2XL U3416 ( .A(PORT_INSTR_IRAM[20]), .B(n2154), .Y(N784) );
AND2XL U3417 ( .A(PORT_INSTR_IRAM[21]), .B(n2154), .Y(N785) );
AND2XL U3418 ( .A(PORT_INSTR_IRAM[24]), .B(n2154), .Y(N788) );
AND2XL U3419 ( .A(PORT_INSTR_IRAM[19]), .B(n2154), .Y(N783) );
AND2XL U3420 ( .A(PORT_INSTR_IRAM[23]), .B(n2154), .Y(N787) );
AND2XL U3421 ( .A(PORT_INSTR_IRAM[22]), .B(n2154), .Y(N786) );
AND2XL U3422 ( .A(PORT_INSTR_IRAM[18]), .B(n2154), .Y(N782) );
AND2XL U3423 ( .A(PORT_INSTR_IRAM[14]), .B(n2154), .Y(N778) );
AND2XL U3424 ( .A(PORT_INSTR_IRAM[13]), .B(n2154), .Y(N777) );
AND2XL U3425 ( .A(PORT_INSTR_IRAM[12]), .B(n2154), .Y(N776) );
AND2XL U3426 ( .A(PORT_INSTR_IRAM[11]), .B(n2154), .Y(N775) );
AND2XL U3427 ( .A(PORT_INSTR_IRAM[9]), .B(n2155), .Y(N773) );
AND2XL U3428 ( .A(PORT_INSTR_IRAM[8]), .B(n2155), .Y(N772) );
AND2XL U3429 ( .A(PORT_INSTR_IRAM[7]), .B(n2155), .Y(N771) );
AND2XL U3430 ( .A(PORT_INSTR_IRAM[3]), .B(n2155), .Y(N767) );
AND2XL U3431 ( .A(PORT_INSTR_IRAM[1]), .B(n2155), .Y(N765) );
AND2XL U3432 ( .A(PORT_INSTR_IRAM[2]), .B(n2155), .Y(N766) );
AND2XL U3433 ( .A(PORT_INSTR_IRAM[5]), .B(n2155), .Y(N769) );
AND2XL U3434 ( .A(PORT_INSTR_IRAM[4]), .B(n2155), .Y(N768) );
AND2XL U3435 ( .A(PORT_INSTR_IRAM[10]), .B(n2154), .Y(N774) );
AND2XL U3436 ( .A(PORT_INSTR_IRAM[6]), .B(n2155), .Y(N770) );
AND2XL U3437 ( .A(PORT_INSTR_IRAM[15]), .B(n2154), .Y(N779) );
CLKINVX1 U3438 ( .A(RESET), .Y(\ID_EX_IMM16_EXT_REG_instance/n34 ) );
CLKINVX1 U3439 ( .A(RESET), .Y(\ID_EX_REGA_REG_instance/n34 ) );
CLKINVX1 U3440 ( .A(RESET), .Y(\ID_EX_PC_REG_instance/n34 ) );
CLKINVX1 U3441 ( .A(RESET), .Y(\EX_MEM_REGB_REG_instance/n34 ) );
CLKINVX1 U3442 ( .A(RESET), .Y(\EX_MEM_OUT_REG_instance/n34 ) );
CLKINVX1 U3443 ( .A(RESET), .Y(\MEM_WB_ALU_REG_instance/n34 ) );
CLKINVX1 U3444 ( .A(RESET), .Y(\ID_EX_REGB_REG_instance/n34 ) );
CLKINVX1 U3445 ( .A(RESET), .Y(\PC_instance/n33 ) );
INVXL U3446 ( .A(RESET), .Y(\ID_EX_INSTR_REG_instance/n34 ) );
OAI32XL U3447 ( .A0(n1503), .A1(WB_INSTR_28), .A2(n1347), .B0(n1504), .B1(
n1505), .Y(n1468) );
OR3XL U3448 ( .A(WB_INSTR[6]), .B(WB_INSTR[10]), .C(n1514), .Y(n1504) );
NAND3XL U3449 ( .A(n1340), .B(n1348), .C(n1471), .Y(n1503) );
OAI211XL U3450 ( .A0(WB_INSTR[5]), .A1(n1506), .B0(n1507), .C0(n1508), .Y(
n1505) );
OAI33XL U3451 ( .A0(n1448), .A1(n1449), .A2(n1450), .B0(n1441), .B1(n1447),
.B2(n1446), .Y(n1438) );
XOR2XL U3452 ( .A(RF_ADD_RD2[2]), .B(MEM_INSTR[13]), .Y(n1449) );
XOR2XL U3453 ( .A(RF_ADD_RD2[4]), .B(MEM_INSTR[15]), .Y(n1450) );
NAND3XL U3454 ( .A(n1454), .B(n1455), .C(n1456), .Y(n1448) );
OAI221XL U3455 ( .A0(n1478), .A1(n1479), .B0(n1480), .B1(n1481), .C0(n1482),
.Y(n1372) );
INVXL U3456 ( .A(n1195), .Y(n1482) );
AOI32XL U3457 ( .A0(n1196), .A1(n1484), .A2(n1485), .B0(n1486), .B1(n1290),
.Y(n1480) );
OAI21XL U3458 ( .A0(n1484), .A1(n1483), .B0(ID_INSTR_31), .Y(n1486) );
AOI22XL U3459 ( .A0(WB_ALU[15]), .A1(n2121), .B0(WB_DATA_RAM[15]), .B1(n1310), .Y(n1312) );
AOI22XL U3460 ( .A0(WB_ALU[7]), .A1(n2121), .B0(WB_DATA_RAM[7]), .B1(n1310),
.Y(n1328) );
AOI22XL U3461 ( .A0(WB_ALU[8]), .A1(n2121), .B0(WB_DATA_RAM[8]), .B1(n1310),
.Y(n1326) );
AOI22XL U3462 ( .A0(WB_ALU[9]), .A1(n2121), .B0(WB_DATA_RAM[9]), .B1(n1310),
.Y(n1324) );
AOI22XL U3463 ( .A0(WB_ALU[10]), .A1(n2121), .B0(WB_DATA_RAM[10]), .B1(n1310), .Y(n1322) );
AOI22XL U3464 ( .A0(WB_ALU[11]), .A1(n2121), .B0(WB_DATA_RAM[11]), .B1(n1310), .Y(n1320) );
AOI22XL U3465 ( .A0(WB_ALU[12]), .A1(n2121), .B0(WB_DATA_RAM[12]), .B1(n1310), .Y(n1318) );
AOI22XL U3466 ( .A0(WB_ALU[13]), .A1(n2121), .B0(WB_DATA_RAM[13]), .B1(n1310), .Y(n1316) );
AOI22XL U3467 ( .A0(WB_ALU[14]), .A1(n2121), .B0(WB_DATA_RAM[14]), .B1(n1310), .Y(n1314) );
OAI31XL U3468 ( .A0(n1391), .A1(n1392), .A2(n1393), .B0(n1360), .Y(n1369) );
XOR2XL U3469 ( .A(RF_ADD_RD2[2]), .B(EX_INSTR[18]), .Y(n1392) );
XOR2XL U3470 ( .A(RF_ADD_RD2[4]), .B(EX_INSTR[20]), .Y(n1393) );
NAND3XL U3471 ( .A(n1394), .B(n1395), .C(n1396), .Y(n1391) );
OAI211XL U3472 ( .A0(EX_INSTR[31]), .A1(n1400), .B0(n1377), .C0(n1374), .Y(
n1361) );
NOR3XL U3473 ( .A(n1347), .B(WB_INSTR_31), .C(n1349), .Y(n1339) );
NOR4XL U3474 ( .A(n1445), .B(n1220), .C(MEM_INSTR[27]), .D(MEM_INSTR[29]),
.Y(n1214) );
XNOR2XL U3475 ( .A(EX_INSTR[17]), .B(RF_ADD_RD2[1]), .Y(n1396) );
XNOR2XL U3476 ( .A(MEM_INSTR[12]), .B(RF_ADD_RD2[1]), .Y(n1456) );
XNOR2XL U3477 ( .A(EX_INSTR[16]), .B(RF_ADD_RD2[0]), .Y(n1395) );
XNOR2XL U3478 ( .A(MEM_INSTR[11]), .B(RF_ADD_RD2[0]), .Y(n1455) );
XNOR2XL U3479 ( .A(EX_INSTR[19]), .B(RF_ADD_RD2[3]), .Y(n1394) );
XNOR2XL U3480 ( .A(MEM_INSTR[14]), .B(RF_ADD_RD2[3]), .Y(n1454) );
XNOR2XL U3481 ( .A(EX_INSTR[11]), .B(n1384), .Y(n1378) );
XNOR2XL U3482 ( .A(MEM_INSTR[11]), .B(n1384), .Y(n1446) );
XNOR2XL U3483 ( .A(n1407), .B(EX_INSTR[20]), .Y(n1406) );
XNOR2XL U3484 ( .A(n1427), .B(MEM_INSTR[18]), .Y(n1425) );
XNOR2XL U3485 ( .A(n1408), .B(EX_INSTR[19]), .Y(n1404) );
XNOR2XL U3486 ( .A(n1433), .B(MEM_INSTR[17]), .Y(n1429) );
NOR2XL U3487 ( .A(n1409), .B(MEM_INSTR[30]), .Y(n1215) );
AOI211XL U3488 ( .A0(WB_INSTR[0]), .A1(n1512), .B0(n1513), .C0(WB_INSTR[3]),
.Y(n1506) );
INVXL U3489 ( .A(WB_INSTR[2]), .Y(n1513) );
OAI31XL U3490 ( .A0(n1464), .A1(WB_INSTR_30), .A2(WB_INSTR_29), .B0(n1341),
.Y(n1463) );
AOI22XL U3491 ( .A0(n1466), .A1(WB_INSTR_26), .B0(n1467), .B1(WB_INSTR_31),
.Y(n1464) );
OAI21XL U3492 ( .A0(WB_INSTR_30), .A1(n1338), .B0(WB_SIGN_EXT_16_CONTROL),
.Y(n1211) );
OAI21XL U3493 ( .A0(n1445), .A1(n1219), .B0(n1213), .Y(n1444) );
NOR4XL U3494 ( .A(n1428), .B(n1429), .C(n1430), .D(n1431), .Y(n1414) );
XOR2XL U3495 ( .A(RF_ADD_RD2[2]), .B(MEM_INSTR[18]), .Y(n1430) );
XNOR2XL U3496 ( .A(n1432), .B(MEM_INSTR[16]), .Y(n1431) );
XNOR2XL U3497 ( .A(n1434), .B(MEM_INSTR[19]), .Y(n1428) );
NOR4XL U3498 ( .A(n1423), .B(n1424), .C(n1425), .D(n1426), .Y(n1415) );
XOR2XL U3499 ( .A(RF_ADD_RD1[1]), .B(MEM_INSTR[17]), .Y(n1424) );
XNOR2XL U3500 ( .A(n1384), .B(MEM_INSTR[16]), .Y(n1426) );
XNOR2XL U3501 ( .A(n1408), .B(MEM_INSTR[19]), .Y(n1423) );
NOR4XL U3502 ( .A(n1417), .B(n1418), .C(n1419), .D(n1420), .Y(n1416) );
NAND2XL U3503 ( .A(n1421), .B(n1422), .Y(n1418) );
XNOR2XL U3504 ( .A(n1407), .B(MEM_INSTR[20]), .Y(n1420) );
OAI2B2XL U3505 ( .A1N(n1467), .A0(WB_INSTR_26), .B0(WB_INSTR_29), .B1(n1349),
.Y(n1469) );
NOR2XL U3506 ( .A(WB_INSTR_29), .B(WB_INSTR_27), .Y(n1343) );
AOI32XL U3507 ( .A0(WB_INSTR[1]), .A1(n1509), .A2(WB_INSTR[2]), .B0(
WB_INSTR[4]), .B1(n1510), .Y(n1508) );
NAND2XL U3508 ( .A(WB_INSTR[3]), .B(n1511), .Y(n1510) );
AO21XL U3509 ( .A0(WB_INSTR[0]), .A1(WB_INSTR[5]), .B0(WB_INSTR[3]), .Y(
n1509) );
OAI2BB1XL U3510 ( .A0N(WB_INSTR[0]), .A1N(WB_INSTR[2]), .B0(n1512), .Y(n1511) );
AOI32XL U3511 ( .A0(n1214), .A1(n1409), .A2(MEM_INSTR[30]), .B0(n1410), .B1(
n1411), .Y(N4710) );
AOI32XL U3512 ( .A0(n1412), .A1(n1413), .A2(n1414), .B0(n1415), .B1(n1416),
.Y(n1411) );
AOI32XL U3513 ( .A0(n1190), .A1(n1438), .A2(n1435), .B0(n1439), .B1(n1440),
.Y(n1410) );
AOI2BB1XL U3514 ( .A0N(n1190), .A1N(n1370), .B0(n1437), .Y(n1412) );
NOR3XL U3515 ( .A(MEM_INSTR[29]), .B(MEM_INSTR[31]), .C(MEM_INSTR[30]), .Y(
n1436) );
NOR3BXL U3516 ( .AN(n1217), .B(n1212), .C(MEM_INSTR[29]), .Y(PORT_R_W) );
XNOR2XL U3517 ( .A(n1218), .B(n1219), .Y(n1217) );
NAND2XL U3518 ( .A(MEM_INSTR[26]), .B(n1220), .Y(n1218) );
OAI211XL U3519 ( .A0(WB_INSTR_31), .A1(n1459), .B0(n1460), .C0(n1461), .Y(
RF_WR) );
AOI31XL U3520 ( .A0(WB_INSTR_29), .A1(n1462), .A2(WB_INSTR_30), .B0(n1463),
.Y(n1461) );
INVXL U3521 ( .A(n1468), .Y(n1460) );
AOI211XL U3522 ( .A0(WB_INSTR_30), .A1(n1469), .B0(n1466), .C0(n1470), .Y(
n1459) );
AO22XL U3523 ( .A0(WB_ALU[0]), .A1(n2121), .B0(WB_DATA_RAM[0]), .B1(n1310),
.Y(WB_DATA_EXT_8[0]) );
AO22XL U3524 ( .A0(WB_ALU[1]), .A1(n2121), .B0(WB_DATA_RAM[1]), .B1(n1310),
.Y(WB_DATA_EXT_8[1]) );
AO22XL U3525 ( .A0(WB_ALU[2]), .A1(n2121), .B0(WB_DATA_RAM[2]), .B1(n1310),
.Y(WB_DATA_EXT_8[2]) );
AO22XL U3526 ( .A0(WB_ALU[3]), .A1(n2121), .B0(WB_DATA_RAM[3]), .B1(n1310),
.Y(WB_DATA_EXT_8[3]) );
AO22XL U3527 ( .A0(WB_ALU[4]), .A1(n2121), .B0(WB_DATA_RAM[4]), .B1(n1310),
.Y(WB_DATA_EXT_8[4]) );
AO22XL U3528 ( .A0(WB_ALU[5]), .A1(n2121), .B0(WB_DATA_RAM[5]), .B1(n1310),
.Y(WB_DATA_EXT_8[5]) );
AO22XL U3529 ( .A0(WB_ALU[6]), .A1(n2121), .B0(WB_DATA_RAM[6]), .B1(n1310),
.Y(WB_DATA_EXT_8[6]) );
AND4XL U3530 ( .A(WB_INSTR_29), .B(WB_INSTR_28), .C(n1339), .D(n1340), .Y(
n1822) );
AOI211XL U3531 ( .A0(MEM_INSTR[29]), .A1(MEM_INSTR[28]), .B0(n1212), .C0(
n1213), .Y(PORT_SIZE[1]) );
NAND3XL U3532 ( .A(WB_INSTR_31), .B(n1343), .C(n1465), .Y(n1341) );
NOR3XL U3533 ( .A(WB_INSTR_26), .B(WB_INSTR_30), .C(WB_INSTR_28), .Y(n1465)
);
OAI2B11XL U3534 ( .A1N(WB_DATA_RAM[16]), .A0(n1207), .B0(n1208), .C0(n1308),
.Y(N6259) );
AOI22XL U3535 ( .A0(WB_ALU[16]), .A1(n1617), .B0(WB_DATA_EXT_16[16]), .B1(
n2149), .Y(n1308) );
OAI21XL U3536 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n34 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[16]) );
OAI2B11XL U3537 ( .A1N(WB_DATA_RAM[17]), .A0(n1207), .B0(n1208), .C0(n1307),
.Y(N6260) );
AOI22XL U3538 ( .A0(WB_ALU[17]), .A1(n1617), .B0(WB_DATA_EXT_16[17]), .B1(
n2149), .Y(n1307) );
OAI21XL U3539 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n33 ), .B0(n2110), .Y(WB_DATA_EXT_16[17]) );
OAI2B11XL U3540 ( .A1N(WB_DATA_RAM[18]), .A0(n1207), .B0(n1208), .C0(n1306),
.Y(N6261) );
AOI22XL U3541 ( .A0(WB_ALU[18]), .A1(n1617), .B0(WB_DATA_EXT_16[18]), .B1(
n2149), .Y(n1306) );
OAI21XL U3542 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n28 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[18]) );
OAI2B11XL U3543 ( .A1N(WB_DATA_RAM[19]), .A0(n1207), .B0(n2150), .C0(n1305),
.Y(N6262) );
AOI22XL U3544 ( .A0(WB_ALU[19]), .A1(n1617), .B0(WB_DATA_EXT_16[19]), .B1(
n2149), .Y(n1305) );
OAI21XL U3545 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n25 ), .B0(n2110), .Y(WB_DATA_EXT_16[19]) );
OAI2B11XL U3546 ( .A1N(WB_DATA_RAM[20]), .A0(n1207), .B0(n2150), .C0(n1304),
.Y(N6263) );
AOI22XL U3547 ( .A0(WB_ALU[20]), .A1(n1617), .B0(WB_DATA_EXT_16[20]), .B1(
n2149), .Y(n1304) );
OAI21XL U3548 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n24 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[20]) );
OAI2B11XL U3549 ( .A1N(WB_DATA_RAM[21]), .A0(n1207), .B0(n2150), .C0(n1303),
.Y(N6264) );
AOI22XL U3550 ( .A0(WB_ALU[21]), .A1(n1617), .B0(WB_DATA_EXT_16[21]), .B1(
n2149), .Y(n1303) );
OAI21XL U3551 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n23 ), .B0(n2110), .Y(WB_DATA_EXT_16[21]) );
OAI2B11XL U3552 ( .A1N(WB_DATA_RAM[22]), .A0(n1207), .B0(n2150), .C0(n1302),
.Y(N6265) );
AOI22XL U3553 ( .A0(WB_ALU[22]), .A1(n1617), .B0(WB_DATA_EXT_16[22]), .B1(
n1211), .Y(n1302) );
OAI21XL U3554 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n22 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[22]) );
OAI2B11XL U3555 ( .A1N(WB_DATA_RAM[23]), .A0(n1207), .B0(n2150), .C0(n1301),
.Y(N6266) );
AOI22XL U3556 ( .A0(WB_ALU[23]), .A1(n1617), .B0(WB_DATA_EXT_16[23]), .B1(
n1211), .Y(n1301) );
OAI21XL U3557 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1328), .B0(n2110), .Y(
WB_DATA_EXT_16[23]) );
OAI2B11XL U3558 ( .A1N(WB_DATA_RAM[24]), .A0(n1207), .B0(n2150), .C0(n1300),
.Y(N6267) );
AOI22XL U3559 ( .A0(WB_ALU[24]), .A1(n1617), .B0(WB_DATA_EXT_16[24]), .B1(
n1211), .Y(n1300) );
OAI21XL U3560 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1326), .B0(
\WB_SIGN_EXT_16_instance/n27 ), .Y(WB_DATA_EXT_16[24]) );
OAI2B11XL U3561 ( .A1N(WB_DATA_RAM[25]), .A0(n1207), .B0(n2150), .C0(n1299),
.Y(N6268) );
AOI22XL U3562 ( .A0(WB_ALU[25]), .A1(n1617), .B0(WB_DATA_EXT_16[25]), .B1(
n1211), .Y(n1299) );
OAI21XL U3563 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1324), .B0(n2110), .Y(
WB_DATA_EXT_16[25]) );
OAI2B11XL U3564 ( .A1N(WB_DATA_RAM[26]), .A0(n1207), .B0(n2150), .C0(n1298),
.Y(N6269) );
AOI22XL U3565 ( .A0(WB_ALU[26]), .A1(n1617), .B0(WB_DATA_EXT_16[26]), .B1(
n1211), .Y(n1298) );
OAI21XL U3566 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1322), .B0(
\WB_SIGN_EXT_16_instance/n27 ), .Y(WB_DATA_EXT_16[26]) );
OAI2B11XL U3567 ( .A1N(WB_DATA_RAM[27]), .A0(n1207), .B0(n2150), .C0(n1297),
.Y(N6270) );
AOI22XL U3568 ( .A0(WB_ALU[27]), .A1(n1617), .B0(WB_DATA_EXT_16[27]), .B1(
n1211), .Y(n1297) );
OAI21XL U3569 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1320), .B0(n2110), .Y(
WB_DATA_EXT_16[27]) );
OAI2B11XL U3570 ( .A1N(WB_DATA_RAM[28]), .A0(n1207), .B0(n2150), .C0(n1296),
.Y(N6271) );
AOI22XL U3571 ( .A0(WB_ALU[28]), .A1(n1617), .B0(WB_DATA_EXT_16[28]), .B1(
n1211), .Y(n1296) );
OAI21XL U3572 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1318), .B0(
\WB_SIGN_EXT_16_instance/n27 ), .Y(WB_DATA_EXT_16[28]) );
OAI2B11XL U3573 ( .A1N(WB_DATA_RAM[29]), .A0(n1207), .B0(n2150), .C0(n1295),
.Y(N6272) );
AOI22XL U3574 ( .A0(WB_ALU[29]), .A1(n1617), .B0(WB_DATA_EXT_16[29]), .B1(
n1211), .Y(n1295) );
OAI21XL U3575 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1316), .B0(n2110), .Y(
WB_DATA_EXT_16[29]) );
OAI2B11XL U3576 ( .A1N(WB_DATA_RAM[30]), .A0(n1207), .B0(n2150), .C0(n1294),
.Y(N6273) );
AOI22XL U3577 ( .A0(WB_ALU[30]), .A1(n1617), .B0(WB_DATA_EXT_16[30]), .B1(
n1211), .Y(n1294) );
OAI21XL U3578 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1314), .B0(n2110), .Y(
WB_DATA_EXT_16[30]) );
OAI2B11XL U3579 ( .A1N(WB_DATA_RAM[31]), .A0(n1207), .B0(n2150), .C0(n1209),
.Y(RF_DATAIN[31]) );
AOI22XL U3580 ( .A0(WB_ALU[31]), .A1(n1617), .B0(WB_DATA_EXT_16[31]), .B1(
n1211), .Y(n1209) );
NOR2XL U3581 ( .A(n1349), .B(WB_INSTR_28), .Y(n1466) );
OAI2BB1XL U3582 ( .A0N(WB_INSTR[17]), .A1N(n1493), .B0(n1497), .Y(
RF_ADD_WR[1]) );
AOI21XL U3583 ( .A0(WB_INSTR[12]), .A1(n1468), .B0(n1495), .Y(n1497) );
OAI2BB1XL U3584 ( .A0N(WB_INSTR[18]), .A1N(n1493), .B0(n1496), .Y(
RF_ADD_WR[2]) );
AOI21XL U3585 ( .A0(WB_INSTR[13]), .A1(n1468), .B0(n1495), .Y(n1496) );
OAI2BB1XL U3586 ( .A0N(WB_INSTR[20]), .A1N(n1493), .B0(n1494), .Y(
RF_ADD_WR[4]) );
AOI21XL U3587 ( .A0(WB_INSTR[15]), .A1(n1468), .B0(n1495), .Y(n1494) );
NAND3BXL U3588 ( .AN(n1498), .B(n1499), .C(n1500), .Y(n1489) );
XNOR2XL U3589 ( .A(RF_ADD_RD2[0]), .B(RF_ADD_WR[0]), .Y(n1499) );
XNOR2XL U3590 ( .A(RF_ADD_RD2[3]), .B(RF_ADD_WR[3]), .Y(n1500) );
INVXL U3591 ( .A(WB_INSTR_28), .Y(n1344) );
INVXL U3592 ( .A(n1380), .Y(n1376) );
OAI33XL U3593 ( .A0(n1381), .A1(n1382), .A2(n1383), .B0(n1373), .B1(n1379),
.B2(n1378), .Y(n1380) );
XOR2XL U3594 ( .A(RF_ADD_RD2[2]), .B(EX_INSTR[13]), .Y(n1382) );
XOR2XL U3595 ( .A(RF_ADD_RD2[4]), .B(EX_INSTR[15]), .Y(n1383) );
NOR2XL U3596 ( .A(n1344), .B(WB_INSTR_27), .Y(n1467) );
NAND2XL U3597 ( .A(n1200), .B(n1201), .Y(n1191) );
NOR4XL U3598 ( .A(n1206), .B(N4717), .C(ID_IMM16_SHL2[12]), .D(
ID_IMM16_SHL2[2]), .Y(n1200) );
NOR4XL U3599 ( .A(n1202), .B(ID_IMM16_SHL2[6]), .C(ID_IMM16_SHL2[8]), .D(
ID_IMM16_SHL2[7]), .Y(n1201) );
NAND3XL U3600 ( .A(ID_IMM16_SHL2[4]), .B(ID_IMM16_SHL2[3]), .C(
ID_IMM16_SHL2[5]), .Y(n1206) );
OAI2BB1XL U3601 ( .A0N(WB_INSTR[16]), .A1N(n1493), .B0(n1502), .Y(
RF_ADD_WR[0]) );
AOI21XL U3602 ( .A0(WB_INSTR[11]), .A1(n1468), .B0(n1495), .Y(n1502) );
OAI2BB1XL U3603 ( .A0N(WB_INSTR[19]), .A1N(n1493), .B0(n1501), .Y(
RF_ADD_WR[3]) );
AOI21XL U3604 ( .A0(WB_INSTR[14]), .A1(n1468), .B0(n1495), .Y(n1501) );
INVXL U3605 ( .A(WB_INSTR_27), .Y(n1349) );
AOI21XL U3606 ( .A0(WB_INSTR_30), .A1(WB_INSTR_27), .B0(n1471), .Y(n1470) );
NAND3XL U3607 ( .A(n1401), .B(n1402), .C(n1403), .Y(n1360) );
NOR3XL U3608 ( .A(n1404), .B(n1405), .C(n1406), .Y(n1403) );
XNOR2XL U3609 ( .A(EX_INSTR[16]), .B(RF_ADD_RD1[0]), .Y(n1401) );
XNOR2XL U3610 ( .A(EX_INSTR[18]), .B(RF_ADD_RD1[2]), .Y(n1402) );
NAND3XL U3611 ( .A(n1385), .B(n1386), .C(n1387), .Y(n1373) );
XNOR2XL U3612 ( .A(EX_INSTR[14]), .B(RF_ADD_RD1[3]), .Y(n1385) );
XNOR2XL U3613 ( .A(EX_INSTR[15]), .B(RF_ADD_RD1[4]), .Y(n1386) );
XNOR2XL U3614 ( .A(EX_INSTR[13]), .B(RF_ADD_RD1[2]), .Y(n1387) );
NAND3XL U3615 ( .A(n1451), .B(n1452), .C(n1453), .Y(n1441) );
XNOR2XL U3616 ( .A(MEM_INSTR[15]), .B(RF_ADD_RD1[4]), .Y(n1451) );
XNOR2XL U3617 ( .A(MEM_INSTR[14]), .B(RF_ADD_RD1[3]), .Y(n1452) );
XNOR2XL U3618 ( .A(MEM_INSTR[13]), .B(RF_ADD_RD1[2]), .Y(n1453) );
NAND3XL U3619 ( .A(n1476), .B(n1421), .C(n1477), .Y(n1472) );
XNOR2XL U3620 ( .A(RF_ADD_RD1[3]), .B(RF_ADD_WR[3]), .Y(n1476) );
XNOR2XL U3621 ( .A(RF_ADD_RD1[0]), .B(RF_ADD_WR[0]), .Y(n1477) );
INVXL U3622 ( .A(WB_INSTR_31), .Y(n1348) );
INVXL U3623 ( .A(WB_INSTR_26), .Y(n1347) );
NAND3XL U3624 ( .A(n1388), .B(n1389), .C(n1390), .Y(n1381) );
XNOR2XL U3625 ( .A(EX_INSTR[14]), .B(RF_ADD_RD2[3]), .Y(n1388) );
XNOR2XL U3626 ( .A(EX_INSTR[11]), .B(RF_ADD_RD2[0]), .Y(n1389) );
XNOR2XL U3627 ( .A(EX_INSTR[12]), .B(RF_ADD_RD2[1]), .Y(n1390) );
AND3XL U3628 ( .A(n1436), .B(MEM_INSTR[27]), .C(n1220), .Y(n1419) );
INVXL U3629 ( .A(MEM_INSTR[27]), .Y(n1219) );
OAI211XL U3630 ( .A0(n1343), .A1(n1344), .B0(n1345), .C0(n1346), .Y(n1342)
);
AOI21XL U3631 ( .A0(WB_INSTR_27), .A1(n1347), .B0(n1348), .Y(n1346) );
AOI31XL U3632 ( .A0(n1349), .A1(n1344), .A2(WB_INSTR_26), .B0(WB_INSTR_30),
.Y(n1345) );
OA21XL U3633 ( .A0(n1457), .A1(n1458), .B0(RF_WR), .Y(N4708) );
NOR4XL U3634 ( .A(n1472), .B(n1473), .C(n1474), .D(n1475), .Y(n1458) );
NOR4XL U3635 ( .A(n1489), .B(n1490), .C(n1491), .D(n1492), .Y(n1457) );
XOR2XL U3636 ( .A(RF_ADD_WR[1]), .B(RF_ADD_RD1[1]), .Y(n1473) );
AND3XL U3637 ( .A(n1487), .B(n1488), .C(n1194), .Y(n1371) );
OAI21XL U3638 ( .A0(ID_INSTR_30), .A1(n1481), .B0(ID_INSTR_27), .Y(n1487) );
XOR2XL U3639 ( .A(EX_INSTR[12]), .B(RF_ADD_RD1[1]), .Y(n1379) );
XOR2XL U3640 ( .A(MEM_INSTR[12]), .B(RF_ADD_RD1[1]), .Y(n1447) );
XOR2XL U3641 ( .A(RF_ADD_WR[2]), .B(RF_ADD_RD2[2]), .Y(n1491) );
XOR2XL U3642 ( .A(RF_ADD_WR[4]), .B(RF_ADD_RD2[4]), .Y(n1492) );
XOR2XL U3643 ( .A(RF_ADD_RD1[1]), .B(EX_INSTR[17]), .Y(n1405) );
AO21XL U3644 ( .A0(WB_INSTR_26), .A1(n1467), .B0(n1466), .Y(n1462) );
NAND3BXL U3645 ( .AN(n1190), .B(n1191), .C(n1192), .Y(RF_RD2) );
AOI22XL U3646 ( .A0(ID_INSTR_29), .A1(n1193), .B0(n1194), .B1(n1195), .Y(
n1192) );
OAI31XL U3647 ( .A0(n1196), .A1(ID_INSTR_27), .A2(n1197), .B0(n1198), .Y(
n1193) );
INVXL U3648 ( .A(RF_ADD_RD1[0]), .Y(n1384) );
INVXL U3649 ( .A(RF_ADD_RD1[2]), .Y(n1427) );
INVXL U3650 ( .A(RF_ADD_RD1[4]), .Y(n1407) );
INVXL U3651 ( .A(RF_ADD_RD1[3]), .Y(n1408) );
XOR2XL U3652 ( .A(RF_ADD_RD2[4]), .B(MEM_INSTR[20]), .Y(n1437) );
OR3XL U3653 ( .A(WB_INSTR[9]), .B(WB_INSTR[8]), .C(WB_INSTR[7]), .Y(n1514)
);
INVXL U3654 ( .A(WB_INSTR[1]), .Y(n1512) );
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_rconst;
// Inputs
reg [23:0] i;
// Outputs
wire [63:0] rc;
// Instantiate the Unit Under Test (UUT)
rconst uut (
.i(i),
.rc(rc)
);
initial begin
// Initialize Inputs
i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i=0; i[0] = 1;
#(`P);
if(rc !== 64'h1) begin $display("E"); $finish; end
i=0; i[1] = 1;
#(`P);
if(rc !== 64'h8082) begin $display("E"); $finish; end
i=0; i[2] = 1;
#(`P);
if(rc !== 64'h800000000000808a) begin $display("E"); $finish; end
i=0; i[3] = 1;
#(`P);
if(rc !== 64'h8000000080008000) begin $display("E"); $finish; end
i=0; i[4] = 1;
#(`P);
if(rc !== 64'h808b) begin $display("E"); $finish; end
i=0; i[5] = 1;
#(`P);
if(rc !== 64'h80000001) begin $display("E"); $finish; end
i=0; i[6] = 1;
#(`P);
if(rc !== 64'h8000000080008081) begin $display("E"); $finish; end
i=0; i[7] = 1;
#(`P);
if(rc !== 64'h8000000000008009) begin $display("E"); $finish; end
i=0; i[8] = 1;
#(`P);
if(rc !== 64'h8a) begin $display("E"); $finish; end
i=0; i[9] = 1;
#(`P);
if(rc !== 64'h88) begin $display("E"); $finish; end
i=0; i[10] = 1;
#(`P);
if(rc !== 64'h80008009) begin $display("E"); $finish; end
i=0; i[11] = 1;
#(`P);
if(rc !== 64'h8000000a) begin $display("E"); $finish; end
i=0; i[12] = 1;
#(`P);
if(rc !== 64'h8000808b) begin $display("E"); $finish; end
i=0; i[13] = 1;
#(`P);
if(rc !== 64'h800000000000008b) begin $display("E"); $finish; end
i=0; i[14] = 1;
#(`P);
if(rc !== 64'h8000000000008089) begin $display("E"); $finish; end
i=0; i[15] = 1;
#(`P);
if(rc !== 64'h8000000000008003) begin $display("E"); $finish; end
i=0; i[16] = 1;
#(`P);
if(rc !== 64'h8000000000008002) begin $display("E"); $finish; end
i=0; i[17] = 1;
#(`P);
if(rc !== 64'h8000000000000080) begin $display("E"); $finish; end
i=0; i[18] = 1;
#(`P);
if(rc !== 64'h800a) begin $display("E"); $finish; end
i=0; i[19] = 1;
#(`P);
if(rc !== 64'h800000008000000a) begin $display("E"); $finish; end
i=0; i[20] = 1;
#(`P);
if(rc !== 64'h8000000080008081) begin $display("E"); $finish; end
i=0; i[21] = 1;
#(`P);
if(rc !== 64'h8000000000008080) begin $display("E"); $finish; end
i=0; i[22] = 1;
#(`P);
if(rc !== 64'h80000001) begin $display("E"); $finish; end
i=0; i[23] = 1;
#(`P);
if(rc !== 64'h8000000080008008) begin $display("E"); $finish; end
$display("Good!");
$finish;
end
endmodule
`undef P
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: rep_jbi_sc0_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module rep_jbi_sc0_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the select of a bit from a vector.
*/
module main;
reg [3:0] a = 4'b0110;
reg [1:0] s = 0;
wire b = a[s];
initial begin
#1 if (b !== 0) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 1;
#1 if (b !== 1) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 2;
#1 if (b !== 1) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 3;
#1 if (b !== 0) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 2'bxx;
#1 if (b !== 1'bx) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V |
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Interface outputs are synchronized using ordinary flops for improved timing.
//--------------------------------------------------------------------------
// Structure:
// axic_reg_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6
// \ \ Application: MIG
// / / Filename: axi4_wrapper.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Sept 16, 2009
// \___\/\___\
//
//Device: Virtex-6, Spartan-6 and 7series
//Design Name: DDR3 SDRAM
//Purpose:
// This module is wrapper for converting the reads and writes to transactions
// that follow the AXI4 protocol.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_axi4_wrapper #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
parameter CTL_SIG_WIDTH = 2, // Control signal width
parameter WR_STS_WIDTH = 16, // Write port status signal width
parameter RD_STS_WIDTH = 16, // Read port status signal width
parameter EN_UPSIZER = 0, // There is no upsizer code
parameter WDG_TIMER_WIDTH = 9
)
(
input aclk, // AXI input clock
input aresetn, // Active low AXI reset signal
// User interface command port
input cmd_en, // Asserted to indicate a valid command
// and address
input [2:0] cmd, // Write or read command
// 000 - READ with INCR bursts
// 001 - READ with WRAP bursts
// 01x - Reserved
// 100 - WRITE with INCR bursts
// 101 - WRITE with WRAP bursts
input [7:0] blen, // Burst length calculated as blen+1
input [31:0] addr, // Address for the read or the write
// transaction
input [CTL_SIG_WIDTH-1:0] ctl, // control command for read or write
// transaction
input wdog_mask, // Mask the watchdog timeouts
output cmd_ack,// Indicates the command has been accepted
// User interface write ports
input wrdata_vld, // Asserted to indicate a valid write
// data
input [C_AXI_DATA_WIDTH-1:0] wrdata, // Write data
input [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld, // Byte valids for the write data
input wrdata_cmptd,// Last data to be transferred
output reg wrdata_rdy, // Indicates that the write data is
// ready to be accepted
output reg wrdata_sts_vld, // Indicates a write status after
// completion of a write transfer
output [WR_STS_WIDTH-1:0] wrdata_sts, // Status of the write transaction
// User interface read ports
input rddata_rdy, // Data ready to be accepted
output reg rddata_vld, // Indicates a valid read data available
output reg [C_AXI_DATA_WIDTH-1:0] rddata, // Read data
output [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld, // Byte valids for read data
output reg rddata_cmptd, // Indicates last data present and
// valid status
output [RD_STS_WIDTH-1:0] rddata_sts, // Status of the read transaction
// AXI write address channel signals
input axi_wready, // Indicates slave is ready to accept a
// write address
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
output [7:0] axi_wlen, // Write Burst Length
output [2:0] axi_wsize, // Write Burst size
output [1:0] axi_wburst, // Write Burst type
output [1:0] axi_wlock, // Write lock type
output [3:0] axi_wcache, // Write Cache type
output [2:0] axi_wprot, // Write Protection type
output reg axi_wvalid, // Write address valid
// AXI write data channel signals
input axi_wd_wready, // Write data ready
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
output reg [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
output reg [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
output reg axi_wd_last, // Last write transaction
output axi_wd_valid, // Write valid
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
input [1:0] axi_wd_bresp, // Write response
input axi_wd_bvalid, // Write reponse valid
output reg axi_wd_bready, // Response ready
// AXI read address channel signals
input axi_rready, // Read address ready
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
output [7:0] axi_rlen, // Read Burst Length
output [2:0] axi_rsize, // Read Burst size
output [1:0] axi_rburst, // Read Burst type
output [1:0] axi_rlock, // Read lock type
output [3:0] axi_rcache, // Read Cache type
output [2:0] axi_rprot, // Read Protection type
output reg axi_rvalid, // Read address valid
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
input [1:0] axi_rd_rresp, // Read response
input axi_rd_rvalid, // Read reponse valid
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
input axi_rd_last, // Read last
output reg axi_rd_rready // Read Response ready
);
//*****************************************************************************
// Internal parameter declarations
//*****************************************************************************
parameter [8:0] AXI_WRIDLE = 9'd0,
AXI_WRCTL = 9'd1,
AXI_WRRDY = 9'd2,
AXI_WRDAT = 9'd3,
AXI_WRDAT_WT = 9'd4,
AXI_WRDAT_LST = 9'd5,
AXI_WRDAT_DMY = 9'd6,
AXI_WRRESP_WT = 9'd7,
AXI_WRTO = 9'd8;
parameter [5:0] AXI_RDIDLE = 6'd0,
AXI_RDCTL = 6'd1,
AXI_RDDAT = 6'd2,
AXI_RDDAT_LST = 6'd3,
AXI_RDDAT_WT = 6'd4,
AXI_RDTO = 6'd5;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg wrap_w;
reg [7:0] blen_w;
reg [7:0] blen_w_minus_1;
reg [C_AXI_ADDR_WIDTH-1:0] addr_w;
reg [CTL_SIG_WIDTH-1:0] ctl_w;
reg wrap_r;
reg [7:0] blen_r;
reg [C_AXI_ADDR_WIDTH-1:0] addr_r;
reg [CTL_SIG_WIDTH-1:0] ctl_r;
reg [8:0] wstate;
reg [8:0] next_wstate;
reg wr_cmd_start;
reg [WDG_TIMER_WIDTH-1:0] wr_wdog_cntr;
reg wrdata_vld_r;
reg wrdata_cmptd_r;
reg [7:0] wr_len_cntr;
reg [7:0] rd_len_cntr;
reg [7:0] blen_cntr;
reg [3:0] wr_cntr;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r1;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r2;
reg wrdata_mux_ctrl;
reg [2:0] wrdata_fsm_sts;
reg [3:0] brespid_r;
reg [1:0] bresp_r;
reg [5:0] rstate;
reg [5:0] next_rstate;
reg [WDG_TIMER_WIDTH-1:0] rd_wdog_cntr;
reg rd_cmd_start;
reg rlast;
reg [3:0] rd_cntr;
reg rddata_ppld;
reg [C_AXI_DATA_WIDTH-1:0] rddata_p1;
reg err_resp;
reg [1:0] rddata_fsm_sts;
reg rrid_err;
reg pending_one_trans;
reg axi_wready_l;
wire wr_cmd_timeout;
wire wr_done;
wire wr_last;
wire rd_cmd_timeout;
//*****************************************************************************
// Address and control register logic
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn) begin
wrap_w <= 1'b0;
blen_w <= 8'h0;
blen_w_minus_1 <= 8'h0;
addr_w <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_w <= {CTL_SIG_WIDTH{1'b0}};
end
else if (wstate[AXI_WRIDLE] & next_wstate[AXI_WRIDLE] &
cmd_en & cmd[2]) begin
wrap_w <= cmd[0];
blen_w <= blen;
blen_w_minus_1 <= blen - 8'h01;
addr_w <= addr;
ctl_w <= ctl;
end
end
always @(posedge aclk) begin
if (!aresetn) begin
wrap_r <= 1'b0;
blen_r <= 8'h0;
addr_r <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_r <= {CTL_SIG_WIDTH{1'b0}};
end
else if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDIDLE] &
cmd_en & !cmd[2]) begin
wrap_r <= cmd[0];
blen_r <= blen;
addr_r <= addr;
ctl_r <= ctl;
end
end
assign cmd_ack = (wstate[AXI_WRIDLE] & next_wstate[AXI_WRCTL]) |
(rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL]);
//*****************************************************************************
// Write data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cmd_start <= 1'b0;
else if (cmd_en & cmd[2] & wstate[AXI_WRIDLE])
wr_cmd_start <= 1'b1;
else if (wstate[AXI_WRCTL])
wr_cmd_start <= 1'b0;
always @(posedge aclk)
if (wstate[AXI_WRIDLE] |
(axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT] | wstate[AXI_WRDAT_LST] | wstate[AXI_WRDAT_DMY])) |
(axi_wd_bvalid & wstate[AXI_WRRESP_WT]))
wr_wdog_cntr <= 'h0;
else if (!wstate[AXI_WRTO] & !wdog_mask)
wr_wdog_cntr <= wr_wdog_cntr + 'h1;
always @(posedge aclk)
wrdata_vld_r <= wrdata_vld;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_cmptd_r <= 1'b0;
else if (wrdata_cmptd & wrdata_vld)
wrdata_cmptd_r <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
blen_cntr <= 8'h0;
else if (wrdata_vld & wrdata_rdy)
blen_cntr <= blen_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
pending_one_trans <= 1'b0;
else if (next_wstate[AXI_WRDAT] & wstate[AXI_WRDAT_WT])
pending_one_trans <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & wr_last & !axi_wd_wready)
pending_one_trans <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wr_len_cntr <= 8'h0;
else if ((wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) &
axi_wd_valid & axi_wd_wready)
wr_len_cntr <= wr_len_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wready_l <= 1'b0;
else if (axi_wready)
axi_wready_l <= 1'b1;
assign wr_cmd_timeout = wr_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
assign wr_last = (wr_len_cntr >= blen_w_minus_1);
assign wr_done = (blen_cntr >= blen_w);
//*****************************************************************************
// Write data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
wstate <= 9'h1;
else
wstate <= next_wstate;
end
always @(*) begin
next_wstate = 9'h0;
case (1'b1)
wstate[AXI_WRIDLE]: begin // 9'h001
if (wr_cmd_start)
next_wstate[AXI_WRCTL] = 1'b1;
else
next_wstate[AXI_WRIDLE] = 1'b1;
end
wstate[AXI_WRCTL]: begin // 9'h002
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wvalid)
next_wstate[AXI_WRRDY] = 1'b1;
else
next_wstate[AXI_WRCTL] = 1'b1;
end
wstate[AXI_WRRDY]: begin // 9'h004
if (wrdata_cmptd_r & wrdata_rdy)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (wrdata_vld_r & wrdata_rdy)
next_wstate[AXI_WRDAT] = 1'b1;
else
next_wstate[AXI_WRRDY] = 1'b1;
end
wstate[AXI_WRDAT]: begin // 9'h008
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else if (!axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
wstate[AXI_WRDAT_WT]: begin // 9'h010
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready) begin
if (pending_one_trans & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!pending_one_trans & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
else
next_wstate[AXI_WRDAT_WT] = 1'b1;
end
wstate[AXI_WRDAT_LST]: begin // 9'h020
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_valid & axi_wd_wready)
next_wstate[AXI_WRRESP_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_LST] = 1'b1;
end
wstate[AXI_WRDAT_DMY]: begin // 9'h040
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (wrdata_cmptd_r & wr_last)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!wr_last & !axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_DMY] = 1'b1;
end
wstate[AXI_WRRESP_WT]: begin // 9'h080
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_bvalid &
(EN_UPSIZER == 1 || (EN_UPSIZER == 0 & axi_wready_l)))
next_wstate[AXI_WRIDLE] = 1'b1;
else
next_wstate[AXI_WRRESP_WT] = 1'b1;
end
wstate[AXI_WRTO]: begin // 9'h100
next_wstate[AXI_WRIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Write channel control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cntr <= 4'h0;
else if (wstate[AXI_WRRESP_WT] & next_wstate[AXI_WRIDLE])
wr_cntr <= wr_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_wvalid <= 1'b0;
else if ((wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY] & axi_wready) ||
(axi_wready & !wstate[AXI_WRCTL]))
axi_wvalid <= 1'b0;
else if (wstate[AXI_WRCTL])
axi_wvalid <= 1'b1;
assign awid = wr_cntr;
assign axi_waddr = addr_w;
assign axi_wid = wr_cntr;
assign axi_wlen = blen_w;
assign axi_wburst = {1'b0, wrap_w} + 2'b01;
assign axi_wsize = ctl_w[2:0];
// Not supported and hence assigned zeros
assign axi_wlock = 2'b0;
assign axi_wcache = 4'b0;
assign axi_wprot = 3'b0;
//*****************************************************************************
// Write channel data signals
//*****************************************************************************
always @(posedge aclk) begin
if (wstate[AXI_WRIDLE]) begin
wrdata_r1 <= 'h0;
wrdata_r2 <= 'h0;
end
else if (wrdata_rdy & wrdata_vld & (wstate[AXI_WRDAT] | wstate[AXI_WRRDY] |
wstate[AXI_WRDAT_LST])) begin
wrdata_r1 <= wrdata;
wrdata_r2 <= wrdata_r1;
end
end
always @(posedge aclk)
if (!aresetn)
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT_LST] | (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT]))
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT] |
(wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY]) |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT]))
wrdata_rdy <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_sts_vld <= 1'b0;
else if (wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b0;
else if ((wstate[AXI_WRRESP_WT] | wstate[AXI_WRTO]) & next_wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_mux_ctrl <= 1'b0;
else if ((wstate[AXI_WRDAT_WT] & (next_wstate[AXI_WRDAT] | next_wstate[AXI_WRDAT_LST])) |
wstate[AXI_WRIDLE])
wrdata_mux_ctrl <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & !pending_one_trans)
wrdata_mux_ctrl <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_wd_last <= 1'b0;
else if (wstate[AXI_WRDAT_LST] & next_wstate[AXI_WRRESP_WT])
axi_wd_last <= 1'b0;
else if ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY] | wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT_LST])
axi_wd_last <= 1'b1;
generate
begin: data_axi_wr
if (C_AXI_NBURST_SUPPORT != 1) begin
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_data <= 'h0;
else if (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & wrdata_mux_ctrl &
~next_wstate[AXI_WRDAT_LST])
axi_wd_data <= wrdata_r2;
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT_LST]) |
(wstate[AXI_WRDAT_LST] & !next_wstate[AXI_WRRESP_WT]))) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]))
axi_wd_data <= wrdata_r1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(next_wstate[AXI_WRDAT_LST] & (wstate[AXI_WRRDY] | wstate[AXI_WRDAT])) |
((wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT]))) |
(next_wstate[AXI_WRDAT_LST] & !axi_wd_wready &
(wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT])) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]) |
((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY]) & next_wstate[AXI_WRDAT_WT]) |
(wstate[AXI_WRDAT_WT]))
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b1}};
else
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
end
end
endgenerate
assign axi_wd_wid = wr_cntr;
assign axi_wd_valid = wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT];
//*****************************************************************************
// Write response and status signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
axi_wd_bready <= 1'b0;
else if (next_wstate[AXI_WRIDLE] & wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b0;
else if (wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_fsm_sts <= 3'b000;
else begin
if (next_wstate[AXI_WRTO]) begin
if (wstate[AXI_WRDAT])
wrdata_fsm_sts <= 3'b001;
else if (wstate[AXI_WRDAT_WT])
wrdata_fsm_sts <= 3'b010;
else if (wstate[AXI_WRDAT_DMY])
wrdata_fsm_sts <= 3'b011;
else if (wstate[AXI_WRRESP_WT])
wrdata_fsm_sts <= 3'b100;
end
end
always @(posedge aclk)
if (wstate[AXI_WRIDLE]) begin
brespid_r <= 4'h0;
bresp_r <= 2'b00;
end
else if (wstate[AXI_WRRESP_WT] & axi_wd_bvalid) begin
brespid_r <= axi_wd_bid;
bresp_r <= axi_wd_bresp;
end
assign wrdata_sts = {{{WR_STS_WIDTH-8}{1'b0}},wrdata_fsm_sts,brespid_r[3:0],bresp_r};
//*****************************************************************************
// Read data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (rstate[AXI_RDIDLE] | axi_rready | axi_rd_rvalid)
rd_wdog_cntr <= 'h0;
else if (!rstate[AXI_RDTO])
rd_wdog_cntr <= rd_wdog_cntr + 'h1;
always @(posedge aclk)
if (!aresetn)
rd_cmd_start <= 1'b0;
else if (cmd_en & !cmd[2] & rstate[AXI_RDIDLE])
rd_cmd_start <= 1'b1;
else if (rstate[AXI_RDCTL])
rd_cmd_start <= 1'b0;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rlast <= 1'b0;
else if (axi_rd_last & axi_rd_rvalid)
rlast <= 1'b1;
assign rd_cmd_timeout = rd_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
//*****************************************************************************
// Read data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
rstate <= 6'h1;
else
rstate <= next_rstate;
end
always @(*) begin
next_rstate = 6'h0;
case (1'b1)
rstate[AXI_RDIDLE]: begin // 6'h01
if (rd_cmd_start)
next_rstate[AXI_RDCTL] = 1'b1;
else
next_rstate[AXI_RDIDLE] = 1'b1;
end
rstate[AXI_RDCTL]: begin // 6'h02
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (axi_rready & axi_rvalid) begin
if (rddata_rdy)
next_rstate[AXI_RDDAT] = 1'b1;
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
else
next_rstate[AXI_RDCTL] = 1'b1;
end
rstate[AXI_RDDAT]: begin // 6'h04
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDDAT_LST]: begin // 6'h08
if (rddata_cmptd & rddata_vld & rddata_rdy)
next_rstate[AXI_RDIDLE] = 1'b1;
else
next_rstate[AXI_RDDAT_LST] = 1'b1;
end
rstate[AXI_RDDAT_WT]: begin // 6'h10
if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDTO]: begin // 6'h20
next_rstate[AXI_RDIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Read Address control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rd_cntr <= 4'h0;
else if (rstate[AXI_RDDAT_LST] & next_rstate[AXI_RDIDLE])
rd_cntr <= rd_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDDAT])
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL])
axi_rvalid <= 1'b1;
assign axi_rid = rd_cntr;
generate
begin: addr_axi_rd
if (C_AXI_DATA_WIDTH == 256)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:5], 5'b0};
else if (C_AXI_DATA_WIDTH == 128)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:4], 4'b0};
else if (C_AXI_DATA_WIDTH == 64)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:3], 3'b0};
else
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:2], 2'b0};
end
endgenerate
assign axi_rlen = blen_r;
assign axi_rburst = {1'b0, wrap_r} + 2'b01;
assign axi_rsize = ctl_r[2:0];
// Not supported and hence assigned zeros
assign axi_rlock = 2'b0;
assign axi_rcache = 4'b0;
assign axi_rprot = 3'b0;
//*****************************************************************************
// Read channel data signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rddata_vld <= 1'b0;
else if ((rddata_vld & !axi_rd_rvalid & rstate[AXI_RDDAT]) |
(rddata_rdy & rstate[AXI_RDDAT_LST]) |
(rstate[AXI_RDDAT_WT] & next_rstate[AXI_RDDAT] & rddata_ppld) |
(rddata_rdy & axi_rd_rvalid & axi_rd_last) |
rstate[AXI_RDIDLE])
rddata_vld <= 1'b0;
else if ((rstate[AXI_RDDAT] & axi_rd_rvalid & !axi_rd_last) |
((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
rddata_ppld <= 1'b0;
else if (rddata_vld & rddata_rdy)
rddata_ppld <= 1'b0;
else if (!rddata_vld & axi_rd_rvalid & axi_rd_rready & rstate[AXI_RDDAT_WT])
rddata_ppld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_rd_rready <= 1'b0;
else if (rstate[AXI_RDIDLE] |
(rstate[AXI_RDDAT] & next_rstate[AXI_RDDAT_WT]) |
(rstate[AXI_RDDAT_WT] & !next_rstate[AXI_RDDAT] & rddata_ppld) |
(next_rstate[AXI_RDDAT_LST] & (rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT])))
axi_rd_rready <= 1'b0;
else if ((next_rstate[AXI_RDDAT] & (rstate[AXI_RDCTL] | rstate[AXI_RDDAT_WT])) |
(next_rstate[AXI_RDDAT_LST] & rstate[AXI_RDDAT_WT] & rddata_ppld) |
(rstate[AXI_RDDAT_WT] & !rddata_ppld) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last))
axi_rd_rready <= 1'b1;
always @(posedge aclk)
if (axi_rd_rvalid)
rddata_p1 <= axi_rd_data;
generate
begin: data_axi_rd
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (axi_rd_rvalid & !rddata_ppld)
rddata <= axi_rd_data;
else if (rddata_rdy & rddata_vld & rddata_ppld)
rddata <= rddata_p1;
assign rddata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
end
end
endgenerate
always @(posedge aclk)
if (!aresetn)
rddata_cmptd <= 1'b0;
else if ((next_rstate[AXI_RDIDLE] & rstate[AXI_RDDAT_LST]) |
rstate[AXI_RDIDLE])
rddata_cmptd <= 1'b0;
else if (((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_cmptd <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
err_resp <= 1'b0;
else if (axi_rd_rvalid & axi_rd_rresp[1])
err_resp <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rddata_fsm_sts <= 2'b00;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b01;
else if (rstate[AXI_RDDAT] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b10;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rrid_err <= 1'b0;
else if (axi_rd_rvalid & axi_rd_bid != rd_cntr)
rrid_err <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rd_len_cntr <= 8'h0;
else if (axi_rd_rvalid & axi_rd_rready)
rd_len_cntr <= rd_len_cntr + 8'h01;
assign rddata_sts = {{(RD_STS_WIDTH-12){1'b0}},rd_len_cntr,rddata_fsm_sts,rrid_err,err_resp};
// synthesis translate_off
always @(posedge aclk) begin
if (rd_cmd_timeout)
$display ("ERR: Read timeout occured at time %t", $time);
if (wr_cmd_timeout)
$display ("ERR: Write timeout occured at time %t", $time);
end
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_FUNCTIONAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM.v when simulating
// the core, BRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM(
clka,
dina,
addra,
wea,
clkb,
addrb,
doutb);
input clka;
input [31 : 0] dina;
input [6 : 0] addra;
input [0 : 0] wea;
input clkb;
input [6 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(7),
.C_ADDRB_WIDTH(7),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex2"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(100),
.C_READ_DEPTH_B(100),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(100),
.C_WRITE_DEPTH_B(100),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex2"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.DOUTA(),
.DINB(),
.ENB(),
.REGCEB(),
.WEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of BRAM is "black_box"
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iobuf32(
input [31:0] T,
input [31:0] I,
output [31:0] O,
inout [31:0] IO
);
IOBUF iobuf0(
.T(T[0]),
.I(I[0]),
.O(O[0]),
.IO(IO[0])
);
IOBUF iobuf1(
.T(T[1]),
.I(I[1]),
.O(O[1]),
.IO(IO[1])
);
IOBUF iobuf2(
.T(T[2]),
.I(I[2]),
.O(O[2]),
.IO(IO[2])
);
IOBUF iobuf3(
.T(T[3]),
.I(I[3]),
.O(O[3]),
.IO(IO[3])
);
IOBUF iobuf4(
.T(T[4]),
.I(I[4]),
.O(O[4]),
.IO(IO[4])
);
IOBUF iobuf5(
.T(T[5]),
.I(I[5]),
.O(O[5]),
.IO(IO[5])
);
IOBUF iobuf6(
.T(T[6]),
.I(I[6]),
.O(O[6]),
.IO(IO[6])
);
IOBUF iobuf7(
.T(T[7]),
.I(I[7]),
.O(O[7]),
.IO(IO[7])
);
IOBUF iobuf8(
.T(T[8]),
.I(I[8]),
.O(O[8]),
.IO(IO[8])
);
IOBUF iobuf9(
.T(T[9]),
.I(I[9]),
.O(O[9]),
.IO(IO[9])
);
IOBUF iobuf10(
.T(T[10]),
.I(I[10]),
.O(O[10]),
.IO(IO[10])
);
IOBUF iobuf11(
.T(T[11]),
.I(I[11]),
.O(O[11]),
.IO(IO[11])
);
IOBUF iobuf12(
.T(T[12]),
.I(I[12]),
.O(O[12]),
.IO(IO[12])
);
IOBUF iobuf13(
.T(T[13]),
.I(I[13]),
.O(O[13]),
.IO(IO[13])
);
IOBUF iobuf14(
.T(T[14]),
.I(I[14]),
.O(O[14]),
.IO(IO[14])
);
IOBUF iobuf15(
.T(T[15]),
.I(I[15]),
.O(O[15]),
.IO(IO[15])
);
IOBUF iobuf16(
.T(T[16]),
.I(I[16]),
.O(O[16]),
.IO(IO[16])
);
IOBUF iobuf17(
.T(T[17]),
.I(I[17]),
.O(O[17]),
.IO(IO[17])
);
IOBUF iobuf18(
.T(T[18]),
.I(I[18]),
.O(O[18]),
.IO(IO[18])
);
IOBUF iobuf19(
.T(T[19]),
.I(I[19]),
.O(O[19]),
.IO(IO[19])
);
IOBUF iobuf20(
.T(T[20]),
.I(I[20]),
.O(O[20]),
.IO(IO[20])
);
IOBUF iobuf21(
.T(T[21]),
.I(I[21]),
.O(O[21]),
.IO(IO[21])
);
IOBUF iobuf22(
.T(T[22]),
.I(I[22]),
.O(O[22]),
.IO(IO[22])
);
IOBUF iobuf23(
.T(T[23]),
.I(I[23]),
.O(O[23]),
.IO(IO[23])
);
IOBUF iobuf24(
.T(T[24]),
.I(I[24]),
.O(O[24]),
.IO(IO[24])
);
IOBUF iobuf25(
.T(T[25]),
.I(I[25]),
.O(O[25]),
.IO(IO[25])
);
IOBUF iobuf26(
.T(T[26]),
.I(I[26]),
.O(O[26]),
.IO(IO[26])
);
IOBUF iobuf27(
.T(T[27]),
.I(I[27]),
.O(O[27]),
.IO(IO[27])
);
IOBUF iobuf28(
.T(T[28]),
.I(I[28]),
.O(O[28]),
.IO(IO[28])
);
IOBUF iobuf29(
.T(T[29]),
.I(I[29]),
.O(O[29]),
.IO(IO[29])
);
IOBUF iobuf30(
.T(T[30]),
.I(I[30]),
.O(O[30]),
.IO(IO[30])
);
IOBUF iobuf31(
.T(T[31]),
.I(I[31]),
.O(O[31]),
.IO(IO[31])
);
endmodule
|
module nios_solo (
clk_clk,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
io_u2p_ack,
io_u2p_rdata,
io_u2p_read,
io_u2p_wdata,
io_u2p_write,
io_u2p_address,
io_u2p_irq,
mem_mem_req_address,
mem_mem_req_byte_en,
mem_mem_req_read_writen,
mem_mem_req_request,
mem_mem_req_tag,
mem_mem_req_wdata,
mem_mem_resp_dack_tag,
mem_mem_resp_data,
mem_mem_resp_rack_tag,
reset_reset_n,
dummy_export);
input clk_clk;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input io_u2p_ack;
input [7:0] io_u2p_rdata;
output io_u2p_read;
output [7:0] io_u2p_wdata;
output io_u2p_write;
output [19:0] io_u2p_address;
input io_u2p_irq;
output [25:0] mem_mem_req_address;
output [3:0] mem_mem_req_byte_en;
output mem_mem_req_read_writen;
output mem_mem_req_request;
output [7:0] mem_mem_req_tag;
output [31:0] mem_mem_req_wdata;
input [7:0] mem_mem_resp_dack_tag;
input [31:0] mem_mem_resp_data;
input [7:0] mem_mem_resp_rack_tag;
input reset_reset_n;
input dummy_export;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright (c) 2001 Philip Blundell
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
primitive p (Q, D);
input D;
output Q;
reg Q;
initial Q = 1'b0;
table
0 : ? : 0;
1 : ? : 1;
endtable
endprimitive
module m;
reg D;
wire Q;
reg A;
wire QQ;
p(Q, D);
buf(QQ, Q);
initial
begin
// The #1 is needed here to allow the initial values to
// settle. Without it, there is a time-0 race.
#1 $display(QQ, Q);
#10
D = 0;
#15
$display(QQ, Q);
#20
D = 1;
#25
$display(QQ, Q);
$finish(0);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter [31:0] TWENTY4 = 24;
parameter [31:0] PA = TWENTY4/8;
parameter [1:0] VALUE = 2'b10;
parameter [5:0] REPL = {PA{VALUE}};
parameter [7:0] CONC = {REPL,VALUE};
parameter DBITS = 32;
parameter INIT_BYTE = 8'h1F;
parameter DWORDS_LOG2 = 7;
parameter DWORDS = (1<<DWORDS_LOG2);
parameter DBYTES=DBITS/8;
reg [DBITS-1:0] mem [0:DWORDS-1];
integer i;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (REPL != {2'b10,2'b10,2'b10}) $stop;
if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop;
end
if (cyc==2) begin
for (i = 0; i < DWORDS; i = i + 1)
mem[i] = {DBYTES{INIT_BYTE}};
end
if (cyc==3) begin
for (i = 0; i < DWORDS; i = i + 1)
if (mem[i] != {DBYTES{INIT_BYTE}}) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//
// Designed by Qiang Wu
//
// 2048 bytes, 64bit interface
`timescale 1ns/1ps
module packet_memory(
clk,
input_mode,
addr64,
data_in64,
data_out64,
byte_we8,
addr32,
data_in32,
data_out32,
byte_we4
);
input clk;
input input_mode; //1 for 64, 0 for 32
input [10:3] addr64;
input [63:0] data_in64;
output [63:0] data_out64;
input [7:0] byte_we8;
input [10:2] addr32;
input [31:0] data_in32;
output [31:0] data_out32;
input [3:0] byte_we4;
reg [63:0] data_out64;
reg [31:0] data_out32;
reg wea0;
reg web0;
reg [8:0] addra0;
reg [8:0] addrb0;
reg [31:0] dia0;
reg [31:0] dib0;
wire [31:0] doa0;
wire [31:0] dob0;
always @(*) begin
wea0 = 0;
web0 = 0;
if(input_mode == 1) begin
addra0[8:0] = {addr64[10:3], 1'b0};
addrb0[8:0] = {addr64[10:3], 1'b1};
dia0 = data_in64[31:0];
dib0 = data_in64[63:32];
data_out64 = {dob0, doa0};
if(byte_we8) begin
wea0 = 1;
web0 = 1;
end else begin
wea0 = 0;
web0 = 0;
end
end else begin
addra0[8:0] = addr32[10:2];
dia0 = data_in32[31:0];
data_out32 = doa0;
if(byte_we4) begin
wea0 = 1;
end else begin
wea0 = 0;
end
end
end
wire [3:0] dipa;
wire [3:0] dipb;
RAMB16_S36_S36 pm0(
.DOA (doa0),
.DOB (dob0),
.DOPA (),
.DOPB (),
.ADDRA (addra0),
.ADDRB (addrb0),
.CLKA (clk),
.CLKB (clk),
.DIA (dia0),
.DIB (dib0),
.DIPA (dipa),
.DIPB (dipb),
.ENA (1'b1),
.ENB (1'b1),
.SSRA (reset),
.SSRB (reset),
.WEA (wea0),
.WEB (web0)
);
endmodule
|
(* techmap_celltype = "$_DFFE_[PN][PN][01][PN]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
EFX_FF #(
.CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
.CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
.SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
.D_POLARITY(1'b1),
.SR_SYNC(1'b0),
.SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
.SR_SYNC_PRIORITY(1'b1)
) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_SDFFE_[PN][PN][01][PN]_" *)
module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
EFX_FF #(
.CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
.CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
.SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
.D_POLARITY(1'b1),
.SR_SYNC(1'b1),
.SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
.SR_SYNC_PRIORITY(1'b1)
) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_SDFFCE_[PN][PN][01][PN]_" *)
module \$_SDFFCE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
EFX_FF #(
.CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
.CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
.SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
.D_POLARITY(1'b1),
.SR_SYNC(1'b1),
.SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
.SR_SYNC_PRIORITY(1'b0)
) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 2) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 3) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
end else
if (WIDTH == 4) begin
EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif
|
`timescale 1ns / 1ps
module MaquinaEstados(
clk, //Clock de la maquina de estados
reset, //Reset de la maquina de estados
state, //para la maquina de estados
accion, //00:reposo,01:llegado a destino,10:subir, 11:bajar
sensor_puerta, //Indicador de puerta atascada (1: atascado, 0 libre)
sensor_sobrepeso, //Indicador de sobrepeso (1: si hay, 0 no hay)
t_expired,
restart_timer, //reinicia el timer
start_timer, //inicia el timer
//Se;al que habilitan el verificador de movimiento
habilita_verificador,
inicia_Registro_Solicitudes,
//A continuacin los leds que se estrn activando y desactivando
subiendo_LED,
bajando_LED,
freno_act_LED,
motor_act_LED,
puerta_abierta_LED,
puerta_cerrada_LED,
sensor_puerta_LED,
sensor_sobrepeso_LED,
//Se;al de finalizaci'on
ready
);
input wire clk, reset;
input wire [1:0] accion;
input sensor_puerta, sensor_sobrepeso, t_expired;
output reg restart_timer, start_timer, ready, habilita_verificador, inicia_Registro_Solicitudes;
output reg subiendo_LED,
bajando_LED,
freno_act_LED,
motor_act_LED,
puerta_abierta_LED,
puerta_cerrada_LED,
sensor_puerta_LED,
sensor_sobrepeso_LED;
output [1:0] state;
reg[3:0] state, nextState;
parameter inicio=4'd0;
parameter reposo = 4'd1;
parameter movimiento = 4'd2;
parameter detener = 4'd3;
parameter abre_puerta = 4'd4;
parameter inicia_conteo = 4'd5;
parameter revisa_seguridad = 4'd6;
parameter dispara_alerta = 4'd7;
parameter reinicia_conteo = 4'd8;
parameter cierra_puerta = 4'd9;
//Asignacin sincrona del siguiente estado
always @(posedge clk or posedge reset)
if (reset)
state <= inicio;
else
state <= nextState;
always @(state or accion) begin
nextState=4'bxxxx;
case (state)
inicio:
begin
habilita_verificador=1'b1;
inicia_Registro_Solicitudes=1'b1;
nextState = reposo;
end
reposo:
begin
freno_act_LED = 1'b1;
puerta_abierta_LED = 1'b0;
puerta_cerrada_LED = 1'b1;
motor_act_LED = 1'b0;
if (accion == 2'b00) begin
nextState = reposo;
end
else if (accion == 2'b10 || accion == 2'b11) begin
nextState = movimiento;
end
else if (accion == 2'b01) begin
nextState = abre_puerta;
end
end
movimiento:
begin
freno_act_LED = 1'b0;
motor_act_LED = 1'b1;
if (accion == 2'b10) begin
subiendo_LED = 1'b1;
bajando_LED = 1'b0;
//Agregar se activa el 7seg subiendo
nextState = movimiento;
end
else if (accion == 2'b11) begin
subiendo_LED = 1'b0;
bajando_LED = 1'b1;
//Agregar se activa el 7 seg bajando
nextState = movimiento;
end
else if (accion == 2'b01)
begin
nextState = detener;
end
end
detener:
begin
freno_act_LED = 1'b1;
motor_act_LED = 1'b0;
nextState = abre_puerta;
end
abre_puerta:
begin
puerta_abierta_LED = 1'b1;
puerta_cerrada_LED = 1'b0;
ready= 1'b1;
if (accion == 2'b10 || accion == 2'b11)
begin
nextState = inicia_conteo;
end
else if (accion == 2'b00)
begin
nextState = reposo;
end
end
inicia_conteo:
begin
start_timer = 1'b1;
nextState = revisa_seguridad;
end
revisa_seguridad:
begin
if (!(sensor_puerta) & !(sensor_sobrepeso) & !(t_expired))
begin
nextState = revisa_seguridad;
end
else if (sensor_sobrepeso | sensor_puerta & !(t_expired))
begin
nextState = dispara_alerta;
end
else if (t_expired)
begin
nextState = cierra_puerta;
end
end
dispara_alerta:
begin
if (sensor_sobrepeso)
begin
sensor_sobrepeso_LED = 1'b1;
end
if (sensor_puerta)
begin
sensor_puerta_LED = 1'b1;
end
nextState = reinicia_conteo;
end
reinicia_conteo:
begin
restart_timer = 1'b1;
nextState = revisa_seguridad;
end
cierra_puerta:
begin
puerta_abierta_LED = 1'b0;
puerta_cerrada_LED = 1'b1;
nextState = movimiento;
end
default: nextState = reposo;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_4_V
`define SKY130_FD_SC_HS__A221O_4_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221o_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_4_V
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* sequential detector
*/
// Import the modules that will be tested for in this testbench
`include "seq_detector.v"
// IMPORTANT: To run this, try: ncverilog -f seq_detector.f +gui
module tb_seq_detect();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the seq_detector
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire error,match_op;
// Declare "reg" signals: inputs to the DUT
reg inp,clock,reset;
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
seq_detect sqd (
// instance_name(signal name),
// Signal name can be the same as the instance name
inp,clock,reset,error,match_op);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
inp = 1'd0;
reset = 1'd0;
// @ t=10,
#10
inp = 1'd0;
reset = 1'd1;
// @ t=20
#10
inp = 1'd0;
reset = 1'd0;
// @ t=30
#10
inp = 1'd1;
reset = 1'd0;
// @ t=40
#10
inp = 1'd1;
reset = 1'd0;
// @ t=50
#10
inp = 1'dx;
reset = 1'd0;
// @ t=60
#10
inp = 1'd0;
reset = 1'd0;
// @ t=70
#10
inp = 1'dz;
reset = 1'd0;
// @ t=80
#10
inp = 1'd0;
reset = 1'd0;
// @ t=90
#10
inp = 1'd1;
reset = 1'd0;
// @ t=100
#10
inp = 1'd1;
reset = 1'd0;
// @ t=110
#10
inp = 1'd0;
reset = 1'd0;
// @ t=120
#10
inp = 1'd1;
reset = 1'd0;
// @ t=130
#10
// Start of correct sequence
$display($time, " << Start of correct sequence >>");
inp = 1'd1;
reset = 1'd0;
// @ t=140
#10
inp = 1'd0;
reset = 1'd0;
// @ t=150
#10
inp = 1'd0;
reset = 1'd0;
// @ t=160
#10
inp = 1'd1;
reset = 1'd0;
// @ t=170
#10
inp = 1'd1;
reset = 1'd0;
// @ t=180
#10
inp = 1'd0;
reset = 1'd0;
// @ t=190
#10
inp = 1'd1;
reset = 1'd0;
// @ t=200
#10
inp = 1'd1;
reset = 1'd0;
// End of correct sequence
$display($time, " << End of correct sequence >>");
// @ t=210
#10
inp = 1'd1;
reset = 1'd0;
// @ t=220
#10
inp = 1'd1;
reset = 1'd0;
// @ t=230
#10
inp = 1'd0;
reset = 1'd0;
// @ t=240; reset the sequence detector
#10
inp = 1'd1;
reset = 1'd0;
// @ t=250
#10
inp = 1'd0;
reset = 1'd0;
// @ t=260
#10
inp = 1'd1;
reset = 1'd0;
// @ t=270
#10
inp = 1'd1;
reset = 1'd1;
// @ t=280
#10
inp = 1'd0;
reset = 1'd0;
// @ t=290
#10
inp = 1'd1;
reset = 1'd0;
// @ t=300
#10
inp = 1'dx;
reset = 1'd0;
// @ t=310
#10
inp = 1'd1;
reset = 1'd0;
// @ t=320
#10
inp = 1'd0;
reset = 1'd0;
// @ t=330
#10
inp = 1'd1;
reset = 1'd0;
// @ t=340
#10
inp = 1'dx;
reset = 1'd0;
// @ t=350
#10
inp = 1'dx;
reset = 1'd0;
// @ t=360
#10
inp = 1'dz;
reset = 1'd0;
// @ t=370
#10
inp = 1'd0;
reset = 1'd0;
// @ t=380
#10
inp = 1'd1;
reset = 1'd0;
// @ t=390
#10
inp = 1'd0;
reset = 1'd0;
// @ t=400
#10
inp = 1'd1;
reset = 1'd0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_barrier(clock, resetn, i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
i_datac, i_datac_valid, o_datac_stall, i_datad, i_datad_valid, o_datad_stall,
o_dataout, o_dataout_valid, i_dataout_stall, i_start, i_counter_value, i_settings);
parameter DATA_WIDTH = 1;
parameter CONFIG_WIDTH = 4;
parameter FIFO_DEPTH = 64;
parameter BARRIER_MAX_SIMULTANEOUS_WORKGROUPS = 4;
parameter BARRIER_WORKGROUP_SIZE_BITS = 10;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input [DATA_WIDTH-1:0] i_datac;
input [DATA_WIDTH-1:0] i_datad;
input i_dataa_valid, i_datab_valid, i_datac_valid, i_datad_valid;
output o_dataa_stall, o_datab_stall, o_datac_stall, o_datad_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
input i_start;
input [31:0] i_counter_value;
input [CONFIG_WIDTH-1:0] i_settings;
wire data_to_count_valid;
wire fifo_a_valid, fifo_b_valid, fifo_c_valid, fifo_d_valid;
wire is_fifo_a_valid, is_fifo_b_valid, is_fifo_c_valid, is_fifo_d_valid;
wire is_fifo_stalled;
vfabric_counter_fifo fifo_a( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_dataa_valid), .o_datain_stall(o_dataa_stall),
.o_dataout_valid(fifo_a_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_b( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datab_valid), .o_datain_stall(o_datab_stall),
.o_dataout_valid(fifo_b_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_c( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datac_valid), .o_datain_stall(o_datac_stall),
.o_dataout_valid(fifo_c_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_d( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datad_valid), .o_datain_stall(o_datad_stall),
.o_dataout_valid(fifo_d_valid), .i_dataout_stall(is_fifo_stalled));
assign is_fifo_a_valid = fifo_a_valid | ~i_settings[0];
assign is_fifo_b_valid = fifo_b_valid | ~i_settings[1];
assign is_fifo_c_valid = fifo_c_valid | ~i_settings[2];
assign is_fifo_d_valid = fifo_d_valid | ~i_settings[3];
assign is_fifo_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid
& is_fifo_d_valid);
assign data_to_count_valid = i_start &
is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid;
acl_barrier_simple barrier0(
.clock(clock),
.resetn(resetn),
.valid_entry(data_to_count_valid),
.data_entry(),
.stall_entry(1'b0),
.valid_exit(o_dataout_valid),
.data_exit(),
.stall_exit(i_dataout_stall),
.num_live_workitems(),
.workgroup_size(i_counter_value));
defparam barrier0.DATA_WIDTH = DATA_WIDTH;
defparam barrier0.MAX_SIMULTANEOUS_WORKGROUPS = BARRIER_MAX_SIMULTANEOUS_WORKGROUPS;
defparam barrier0.WORKGROUP_SIZE_BITS = BARRIER_WORKGROUP_SIZE_BITS;
endmodule
|
module acl_fp_dot_product_64(clock, resetn, enable, valid_in, valid_out,
datain_a_00,
datain_a_01,
datain_a_02,
datain_a_03,
datain_a_04,
datain_a_05,
datain_a_06,
datain_a_07,
datain_a_08,
datain_a_09,
datain_a_10,
datain_a_11,
datain_a_12,
datain_a_13,
datain_a_14,
datain_a_15,
datain_a_16,
datain_a_17,
datain_a_18,
datain_a_19,
datain_a_20,
datain_a_21,
datain_a_22,
datain_a_23,
datain_a_24,
datain_a_25,
datain_a_26,
datain_a_27,
datain_a_28,
datain_a_29,
datain_a_30,
datain_a_31,
datain_a_32,
datain_a_33,
datain_a_34,
datain_a_35,
datain_a_36,
datain_a_37,
datain_a_38,
datain_a_39,
datain_a_40,
datain_a_41,
datain_a_42,
datain_a_43,
datain_a_44,
datain_a_45,
datain_a_46,
datain_a_47,
datain_a_48,
datain_a_49,
datain_a_50,
datain_a_51,
datain_a_52,
datain_a_53,
datain_a_54,
datain_a_55,
datain_a_56,
datain_a_57,
datain_a_58,
datain_a_59,
datain_a_60,
datain_a_61,
datain_a_62,
datain_a_63,
datain_b_00,
datain_b_01,
datain_b_02,
datain_b_03,
datain_b_04,
datain_b_05,
datain_b_06,
datain_b_07,
datain_b_08,
datain_b_09,
datain_b_10,
datain_b_11,
datain_b_12,
datain_b_13,
datain_b_14,
datain_b_15,
datain_b_16,
datain_b_17,
datain_b_18,
datain_b_19,
datain_b_20,
datain_b_21,
datain_b_22,
datain_b_23,
datain_b_24,
datain_b_25,
datain_b_26,
datain_b_27,
datain_b_28,
datain_b_29,
datain_b_30,
datain_b_31,
datain_b_32,
datain_b_33,
datain_b_34,
datain_b_35,
datain_b_36,
datain_b_37,
datain_b_38,
datain_b_39,
datain_b_40,
datain_b_41,
datain_b_42,
datain_b_43,
datain_b_44,
datain_b_45,
datain_b_46,
datain_b_47,
datain_b_48,
datain_b_49,
datain_b_50,
datain_b_51,
datain_b_52,
datain_b_53,
datain_b_54,
datain_b_55,
datain_b_56,
datain_b_57,
datain_b_58,
datain_b_59,
datain_b_60,
datain_b_61,
datain_b_62,
datain_b_63,
result
);
input clock, resetn, enable, valid_in;
output valid_out;
input [31:0] datain_a_00,
datain_a_01,
datain_a_02,
datain_a_03,
datain_a_04,
datain_a_05,
datain_a_06,
datain_a_07,
datain_a_08,
datain_a_09,
datain_a_10,
datain_a_11,
datain_a_12,
datain_a_13,
datain_a_14,
datain_a_15,
datain_a_16,
datain_a_17,
datain_a_18,
datain_a_19,
datain_a_20,
datain_a_21,
datain_a_22,
datain_a_23,
datain_a_24,
datain_a_25,
datain_a_26,
datain_a_27,
datain_a_28,
datain_a_29,
datain_a_30,
datain_a_31,
datain_a_32,
datain_a_33,
datain_a_34,
datain_a_35,
datain_a_36,
datain_a_37,
datain_a_38,
datain_a_39,
datain_a_40,
datain_a_41,
datain_a_42,
datain_a_43,
datain_a_44,
datain_a_45,
datain_a_46,
datain_a_47,
datain_a_48,
datain_a_49,
datain_a_50,
datain_a_51,
datain_a_52,
datain_a_53,
datain_a_54,
datain_a_55,
datain_a_56,
datain_a_57,
datain_a_58,
datain_a_59,
datain_a_60,
datain_a_61,
datain_a_62,
datain_a_63,
datain_b_00,
datain_b_01,
datain_b_02,
datain_b_03,
datain_b_04,
datain_b_05,
datain_b_06,
datain_b_07,
datain_b_08,
datain_b_09,
datain_b_10,
datain_b_11,
datain_b_12,
datain_b_13,
datain_b_14,
datain_b_15,
datain_b_16,
datain_b_17,
datain_b_18,
datain_b_19,
datain_b_20,
datain_b_21,
datain_b_22,
datain_b_23,
datain_b_24,
datain_b_25,
datain_b_26,
datain_b_27,
datain_b_28,
datain_b_29,
datain_b_30,
datain_b_31,
datain_b_32,
datain_b_33,
datain_b_34,
datain_b_35,
datain_b_36,
datain_b_37,
datain_b_38,
datain_b_39,
datain_b_40,
datain_b_41,
datain_b_42,
datain_b_43,
datain_b_44,
datain_b_45,
datain_b_46,
datain_b_47,
datain_b_48,
datain_b_49,
datain_b_50,
datain_b_51,
datain_b_52,
datain_b_53,
datain_b_54,
datain_b_55,
datain_b_56,
datain_b_57,
datain_b_58,
datain_b_59,
datain_b_60,
datain_b_61,
datain_b_62,
datain_b_63;
output [31:0] result;
wire [31:0] inputs_a[0:63];
wire [31:0] inputs_b[0:63];
assign inputs_a[0] = datain_a_00;
assign inputs_a[1] = datain_a_01;
assign inputs_a[2] = datain_a_02;
assign inputs_a[3] = datain_a_03;
assign inputs_a[4] = datain_a_04;
assign inputs_a[5] = datain_a_05;
assign inputs_a[6] = datain_a_06;
assign inputs_a[7] = datain_a_07;
assign inputs_a[8] = datain_a_08;
assign inputs_a[9] = datain_a_09;
assign inputs_a[10] = datain_a_10;
assign inputs_a[11] = datain_a_11;
assign inputs_a[12] = datain_a_12;
assign inputs_a[13] = datain_a_13;
assign inputs_a[14] = datain_a_14;
assign inputs_a[15] = datain_a_15;
assign inputs_a[16] = datain_a_16;
assign inputs_a[17] = datain_a_17;
assign inputs_a[18] = datain_a_18;
assign inputs_a[19] = datain_a_19;
assign inputs_a[20] = datain_a_20;
assign inputs_a[21] = datain_a_21;
assign inputs_a[22] = datain_a_22;
assign inputs_a[23] = datain_a_23;
assign inputs_a[24] = datain_a_24;
assign inputs_a[25] = datain_a_25;
assign inputs_a[26] = datain_a_26;
assign inputs_a[27] = datain_a_27;
assign inputs_a[28] = datain_a_28;
assign inputs_a[29] = datain_a_29;
assign inputs_a[30] = datain_a_30;
assign inputs_a[31] = datain_a_31;
assign inputs_a[32] = datain_a_32;
assign inputs_a[33] = datain_a_33;
assign inputs_a[34] = datain_a_34;
assign inputs_a[35] = datain_a_35;
assign inputs_a[36] = datain_a_36;
assign inputs_a[37] = datain_a_37;
assign inputs_a[38] = datain_a_38;
assign inputs_a[39] = datain_a_39;
assign inputs_a[40] = datain_a_40;
assign inputs_a[41] = datain_a_41;
assign inputs_a[42] = datain_a_42;
assign inputs_a[43] = datain_a_43;
assign inputs_a[44] = datain_a_44;
assign inputs_a[45] = datain_a_45;
assign inputs_a[46] = datain_a_46;
assign inputs_a[47] = datain_a_47;
assign inputs_a[48] = datain_a_48;
assign inputs_a[49] = datain_a_49;
assign inputs_a[50] = datain_a_50;
assign inputs_a[51] = datain_a_51;
assign inputs_a[52] = datain_a_52;
assign inputs_a[53] = datain_a_53;
assign inputs_a[54] = datain_a_54;
assign inputs_a[55] = datain_a_55;
assign inputs_a[56] = datain_a_56;
assign inputs_a[57] = datain_a_57;
assign inputs_a[58] = datain_a_58;
assign inputs_a[59] = datain_a_59;
assign inputs_a[60] = datain_a_60;
assign inputs_a[61] = datain_a_61;
assign inputs_a[62] = datain_a_62;
assign inputs_a[63] = datain_a_63;
assign inputs_b[0] = datain_b_00;
assign inputs_b[1] = datain_b_01;
assign inputs_b[2] = datain_b_02;
assign inputs_b[3] = datain_b_03;
assign inputs_b[4] = datain_b_04;
assign inputs_b[5] = datain_b_05;
assign inputs_b[6] = datain_b_06;
assign inputs_b[7] = datain_b_07;
assign inputs_b[8] = datain_b_08;
assign inputs_b[9] = datain_b_09;
assign inputs_b[10] = datain_b_10;
assign inputs_b[11] = datain_b_11;
assign inputs_b[12] = datain_b_12;
assign inputs_b[13] = datain_b_13;
assign inputs_b[14] = datain_b_14;
assign inputs_b[15] = datain_b_15;
assign inputs_b[16] = datain_b_16;
assign inputs_b[17] = datain_b_17;
assign inputs_b[18] = datain_b_18;
assign inputs_b[19] = datain_b_19;
assign inputs_b[20] = datain_b_20;
assign inputs_b[21] = datain_b_21;
assign inputs_b[22] = datain_b_22;
assign inputs_b[23] = datain_b_23;
assign inputs_b[24] = datain_b_24;
assign inputs_b[25] = datain_b_25;
assign inputs_b[26] = datain_b_26;
assign inputs_b[27] = datain_b_27;
assign inputs_b[28] = datain_b_28;
assign inputs_b[29] = datain_b_29;
assign inputs_b[30] = datain_b_30;
assign inputs_b[31] = datain_b_31;
assign inputs_b[32] = datain_b_32;
assign inputs_b[33] = datain_b_33;
assign inputs_b[34] = datain_b_34;
assign inputs_b[35] = datain_b_35;
assign inputs_b[36] = datain_b_36;
assign inputs_b[37] = datain_b_37;
assign inputs_b[38] = datain_b_38;
assign inputs_b[39] = datain_b_39;
assign inputs_b[40] = datain_b_40;
assign inputs_b[41] = datain_b_41;
assign inputs_b[42] = datain_b_42;
assign inputs_b[43] = datain_b_43;
assign inputs_b[44] = datain_b_44;
assign inputs_b[45] = datain_b_45;
assign inputs_b[46] = datain_b_46;
assign inputs_b[47] = datain_b_47;
assign inputs_b[48] = datain_b_48;
assign inputs_b[49] = datain_b_49;
assign inputs_b[50] = datain_b_50;
assign inputs_b[51] = datain_b_51;
assign inputs_b[52] = datain_b_52;
assign inputs_b[53] = datain_b_53;
assign inputs_b[54] = datain_b_54;
assign inputs_b[55] = datain_b_55;
assign inputs_b[56] = datain_b_56;
assign inputs_b[57] = datain_b_57;
assign inputs_b[58] = datain_b_58;
assign inputs_b[59] = datain_b_59;
assign inputs_b[60] = datain_b_60;
assign inputs_b[61] = datain_b_61;
assign inputs_b[62] = datain_b_62;
assign inputs_b[63] = datain_b_63;
wire [36:0] mult_result [0:63];
wire [63:0] mult_valid_out;
wire [63:0] mult_stall_out;
wire [37:0] add_result_1 [0:31];
wire [31:0] add_valid_out_1;
wire [31:0] add_stall_out_1;
wire [37:0] add_result_2 [0:15];
wire [15:0] add_valid_out_2;
wire [15:0] add_stall_out_2;
wire [37:0] add_result_3 [0:7];
wire [7:0] add_valid_out_3;
wire [7:0] add_stall_out_3;
wire [37:0] add_result_4 [0:3];
wire [3:0] add_valid_out_4;
wire [3:0] add_stall_out_4;
wire [37:0] add_result_5 [0:1];
wire [1:0] add_valid_out_5;
wire [1:0] add_stall_out_5;
wire [37:0] add_result_6;
wire add_valid_out_6;
wire [0:0] add_stall_out_6;
// stage 0
genvar i;
generate
for(i=0; i < 64; i = i + 1)
begin: mult_stage
acl_fp_custom_mul_wrapper m0(
.clock(clock),
.resetn(resetn),
.dataa(inputs_a[i]),
.datab(inputs_b[i]),
.result(mult_result[i]),
.valid_in((i==0) ? valid_in : 1'b0),
.valid_out(mult_valid_out[i]),
.enable(enable));
end
endgenerate
// stage 1
generate
for(i=0; i < 32; i = i + 1)
begin: add_stage_1
acl_fp_custom_add_wrapper a1(
.clock(clock),
.resetn(resetn),
.dataa(mult_result[2*i]),
.datab(mult_result[2*i+1]),
.result(add_result_1[i]),
.valid_in((i==0) ? mult_valid_out[2*i] : 1'b0),
.valid_out(add_valid_out_1[i]),
.enable(enable));
end
endgenerate
// stage 2
generate
for(i=0; i < 16; i = i + 1)
begin: add_stage_2
acl_fp_custom_dynamic_align a2(
.clock(clock),
.resetn(resetn),
.dataa(add_result_1[2*i]),
.datab(add_result_1[2*i+1]),
.result(add_result_2[i]),
.valid_in((i==0) ? add_valid_out_1[2*i] : 1'b0),
.valid_out(add_valid_out_2[i]),
.enable(enable));
end
endgenerate
// stage 3
generate
for(i=0; i < 8; i = i + 1)
begin: add_stage_3
acl_fp_custom_dynamic_align a3(
.clock(clock),
.resetn(resetn),
.dataa(add_result_2[2*i]),
.datab(add_result_2[2*i+1]),
.result(add_result_3[i]),
.valid_in((i==0) ? add_valid_out_2[2*i] :1'b0),
.valid_out(add_valid_out_3[i]),
.enable(enable));
end
endgenerate
// stage 4
generate
for(i=0; i < 4; i = i + 1)
begin: add_stage_4
acl_fp_custom_dynamic_align a4(
.clock(clock),
.resetn(resetn),
.dataa(add_result_3[2*i]),
.datab(add_result_3[2*i+1]),
.result(add_result_4[i]),
.valid_in((i==0) ? add_valid_out_3[2*i] : 1'b0),
.valid_out(add_valid_out_4[i]),
.enable(enable));
end
endgenerate
// stage 5
generate
for(i=0; i < 2; i = i + 1)
begin: add_stage_5
acl_fp_custom_dynamic_align a5(
.clock(clock),
.resetn(resetn),
.dataa(add_result_4[2*i]),
.datab(add_result_4[2*i+1]),
.result(add_result_5[i]),
.valid_in((i==0) ? add_valid_out_4[2*i] : 1'b0),
.valid_out(add_valid_out_5[i]),
.enable(enable));
end
endgenerate
wire add_conv_stall_out;
acl_fp_custom_dynamic_align a6(
.clock(clock),
.resetn(resetn),
.dataa(add_result_5[0]),
.datab(add_result_5[1]),
.result(add_result_6),
.valid_in(add_valid_out_5[0]),
.valid_out(add_valid_out_6),
.enable(enable));
wire [26:0] norm_man;
wire [8:0] norm_exp;
wire norm_sign;
wire norm_valid;
acl_fp_custom_reduced_normalize norm(
.clock(clock),
.resetn(resetn),
.mantissa(add_result_6[27:0]), .exponent(add_result_6[36:28]), .sign(add_result_6[37]),
.valid_in(add_valid_out_6), .valid_out(norm_valid),
.enable(enable),
.mantissa_out(norm_man), .exponent_out(norm_exp), .sign_out(norm_sign));
defparam norm.HIGH_CAPACITY = 0;
defparam norm.FLUSH_DENORMS = 0;
defparam norm.HIGH_LATENCY = 1;
defparam norm.REMOVE_STICKY = 1;
defparam norm.FINITE_MATH_ONLY = 1;
acl_fp_convert_to_ieee cie(
.clock(clock),
.resetn(resetn),
.mantissa(norm_man),
.exponent(norm_exp),
.sign(norm_sign),
.result(result),
.valid_in(norm_valid),
.valid_out(valid_out),
.enable(enable));
defparam cie.FINITE_MATH_ONLY = 1;
endmodule
|
`default_nettype none
`define CLKFREQ 12000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
module ham_15_11_encoder ( d, c );
input [10:0] d;
output [14:0] c;
wire n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41;
assign c[14] = d[10];
assign c[13] = d[9];
assign c[12] = d[8];
assign c[11] = d[7];
assign c[10] = d[6];
assign c[9] = d[5];
assign c[8] = d[4];
assign c[6] = d[3];
assign c[5] = d[2];
assign c[4] = d[1];
assign c[2] = d[0];
XOR2X1 U25 ( .A(n28), .B(n29), .Y(c[7]) );
XOR2X1 U26 ( .A(d[7]), .B(n30), .Y(n29) );
XOR2X1 U27 ( .A(n31), .B(n32), .Y(c[3]) );
XOR2X1 U28 ( .A(n33), .B(n34), .Y(n32) );
XOR2X1 U29 ( .A(d[2]), .B(d[10]), .Y(n34) );
XOR2X1 U30 ( .A(d[7]), .B(n35), .Y(n31) );
XOR2X1 U31 ( .A(d[9]), .B(d[8]), .Y(n35) );
XOR2X1 U32 ( .A(n36), .B(n37), .Y(c[1]) );
XOR2X1 U33 ( .A(n30), .B(n38), .Y(n37) );
XOR2X1 U34 ( .A(d[9]), .B(d[5]), .Y(n30) );
XOR2X1 U35 ( .A(d[0]), .B(n39), .Y(n36) );
XOR2X1 U36 ( .A(d[3]), .B(d[2]), .Y(n39) );
XOR2X1 U37 ( .A(n33), .B(n40), .Y(c[0]) );
XOR2X1 U38 ( .A(d[0]), .B(n28), .Y(n40) );
XNOR2X1 U39 ( .A(n41), .B(n38), .Y(n28) );
XOR2X1 U40 ( .A(d[10]), .B(d[6]), .Y(n38) );
XNOR2X1 U41 ( .A(d[8]), .B(d[4]), .Y(n41) );
XOR2X1 U42 ( .A(d[3]), .B(d[1]), .Y(n33) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
module sfa_interconnect(
// Inputs
output wire sn_tready ,
input wire sn_tvalid ,
input wire [31 : 0] sn_tdata ,
output wire se_tready ,
input wire se_tvalid ,
input wire [31 : 0] se_tdata ,
output wire ss_tready ,
input wire ss_tvalid ,
input wire [31 : 0] ss_tdata ,
output wire sw_tready ,
input wire sw_tvalid ,
input wire [31 : 0] sw_tdata ,
// Outputs
input wire mn_tready ,
output wire mn_tvalid ,
output wire [31 : 0] mn_tdata ,
input wire me_tready ,
output wire me_tvalid ,
output wire [31 : 0] me_tdata ,
input wire ms_tready ,
output wire ms_tvalid ,
output wire [31 : 0] ms_tdata ,
input wire mw_tready ,
output wire mw_tvalid ,
output wire [31 : 0] mw_tdata ,
// PR Intrface
input wire macc1_tready ,
output wire macc1_tvalid ,
output wire [31 : 0] macc1_tdata ,
input wire macc2_tready ,
output wire macc2_tvalid ,
output wire [31 : 0] macc2_tdata ,
output wire sacc_tready ,
input wire sacc_tvalid ,
input wire [31 : 0] sacc_tdata ,
// Config Interface
input wire [ 3 : 0] IN1_CONF ,
input wire [ 3 : 0] IN2_CONF ,
input wire [ 3 : 0] N_CONF ,
input wire [ 3 : 0] E_CONF ,
input wire [ 3 : 0] S_CONF ,
input wire [ 3 : 0] W_CONF ,
input wire ACLK ,
input wire ARESETN
);
wire en_tmp_tready;
wire sn_tmp_tready;
wire wn_tmp_tready;
wire ne_tmp_tready;
wire se_tmp_tready;
wire we_tmp_tready;
wire ns_tmp_tready;
wire es_tmp_tready;
wire ws_tmp_tready;
wire nw_tmp_tready;
wire ew_tmp_tready;
wire sw_tmp_tready;
wire nacc1_tmp_tready;
wire eacc1_tmp_tready;
wire sacc1_tmp_tready;
wire wacc1_tmp_tready;
wire nacc2_tmp_tready;
wire eacc2_tmp_tready;
wire sacc2_tmp_tready;
wire wacc2_tmp_tready;
assign sn_tready = en_tmp_tready | sn_tmp_tready | wn_tmp_tready | nacc1_tmp_tready | nacc2_tmp_tready;
assign se_tready = ne_tmp_tready | se_tmp_tready | we_tmp_tready | eacc1_tmp_tready | eacc2_tmp_tready;
assign ss_tready = ns_tmp_tready | es_tmp_tready | ws_tmp_tready | sacc1_tmp_tready | sacc2_tmp_tready;
assign sw_tready = nw_tmp_tready | ew_tmp_tready | sw_tmp_tready | wacc1_tmp_tready | wacc2_tmp_tready;
assign sacc_tready = nout_tmp_tready | eout_tmp_tready | sout_tmp_tready | wout_tmp_tready;
sfa_5to1_mux N_OUT_MUX (
.s1_tready () ,
.s1_tvalid (1'b0 ) ,
.s1_tdata (32'b0) ,
.s2_tready (ne_tmp_tready) ,
.s2_tvalid (se_tvalid) ,
.s2_tdata (se_tdata ) ,
.s3_tready (ns_tmp_tready) ,
.s3_tvalid (ss_tvalid) ,
.s3_tdata (ss_tdata ) ,
.s4_tready (nw_tmp_tready) ,
.s4_tvalid (sw_tvalid) ,
.s4_tdata (sw_tdata ) ,
.s5_tready (nout_tmp_tready) ,
.s5_tvalid (sacc_tvalid) ,
.s5_tdata (sacc_tdata ) ,
.mO_tready (mn_tready) ,
.mO_tvalid (mn_tvalid) ,
.mO_tdata (mn_tdata ) ,
.CONF (N_CONF )
);
sfa_5to1_mux E_OUT_MUX (
.s1_tready (en_tmp_tready) ,
.s1_tvalid (sn_tvalid) ,
.s1_tdata (sn_tdata ) ,
.s2_tready () ,
.s2_tvalid (1'b0 ) ,
.s2_tdata (32'b0) ,
.s3_tready (es_tmp_tready) ,
.s3_tvalid (ss_tvalid) ,
.s3_tdata (ss_tdata ) ,
.s4_tready (ew_tmp_tready) ,
.s4_tvalid (sw_tvalid) ,
.s4_tdata (sw_tdata ) ,
.s5_tready (eout_tmp_tready) ,
.s5_tvalid (sacc_tvalid) ,
.s5_tdata (sacc_tdata ) ,
.mO_tready (me_tready) ,
.mO_tvalid (me_tvalid) ,
.mO_tdata (me_tdata ) ,
.CONF (E_CONF )
);
sfa_5to1_mux S_OUT_MUX (
.s1_tready (sn_tmp_tready) ,
.s1_tvalid (sn_tvalid) ,
.s1_tdata (sn_tdata ) ,
.s2_tready (se_tmp_tready) ,
.s2_tvalid (se_tvalid) ,
.s2_tdata (se_tdata ) ,
.s3_tready () ,
.s3_tvalid (1'b0 ) ,
.s3_tdata (32'b0) ,
.s4_tready (sw_tmp_tready) ,
.s4_tvalid (sw_tvalid) ,
.s4_tdata (sw_tdata ) ,
.s5_tready (sout_tmp_tready) ,
.s5_tvalid (sacc_tvalid) ,
.s5_tdata (sacc_tdata ) ,
.mO_tready (ms_tready) ,
.mO_tvalid (ms_tvalid) ,
.mO_tdata (ms_tdata ) ,
.CONF (S_CONF )
);
sfa_5to1_mux W_OUT_MUX (
.s1_tready (wn_tmp_tready) ,
.s1_tvalid (sn_tvalid) ,
.s1_tdata (sn_tdata ) ,
.s2_tready (we_tmp_tready) ,
.s2_tvalid (se_tvalid) ,
.s2_tdata (se_tdata ) ,
.s3_tready (ws_tmp_tready) ,
.s3_tvalid (ss_tvalid) ,
.s3_tdata (ss_tdata ) ,
.s4_tready () ,
.s4_tvalid (1'b0 ) ,
.s4_tdata (32'b0) ,
.s5_tready (wout_tmp_tready) ,
.s5_tvalid (sacc_tvalid) ,
.s5_tdata (sacc_tdata ) ,
.mO_tready (mw_tready) ,
.mO_tvalid (mw_tvalid) ,
.mO_tdata (mw_tdata ) ,
.CONF (W_CONF )
);
sfa_5to1_mux ACC_IN1_MUX (
.s1_tready (nacc1_tmp_tready) ,
.s1_tvalid (sn_tvalid) ,
.s1_tdata (sn_tdata ) ,
.s2_tready (eacc1_tmp_tready) ,
.s2_tvalid (se_tvalid) ,
.s2_tdata (se_tdata ) ,
.s3_tready (sacc1_tmp_tready) ,
.s3_tvalid (ss_tvalid) ,
.s3_tdata (ss_tdata ) ,
.s4_tready (wacc1_tmp_tready) ,
.s4_tvalid (sw_tvalid) ,
.s4_tdata (sw_tdata ) ,
.mO_tready (macc1_tready) ,
.mO_tvalid (macc1_tvalid) ,
.mO_tdata (macc1_tdata ) ,
.CONF (IN1_CONF )
);
sfa_5to1_mux ACC_IN2_MUX (
.s1_tready (nacc2_tmp_tready) ,
.s1_tvalid (sn_tvalid) ,
.s1_tdata (sn_tdata ) ,
.s2_tready (eacc2_tmp_tready) ,
.s2_tvalid (se_tvalid) ,
.s2_tdata (se_tdata ) ,
.s3_tready (sacc2_tmp_tready) ,
.s3_tvalid (ss_tvalid) ,
.s3_tdata (ss_tdata ) ,
.s4_tready (wacc2_tmp_tready) ,
.s4_tvalid (sw_tvalid) ,
.s4_tdata (sw_tdata ) ,
.mO_tready (macc2_tready) ,
.mO_tvalid (macc2_tvalid) ,
.mO_tdata (macc2_tdata ) ,
.CONF (IN2_CONF )
);
endmodule
|
`define ADDER_WIDTH 032
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_PP_SYMBOL_V
|
// system_acl_iface_hps_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.05.08:40:38
`timescale 1 ps / 1 ps
module system_acl_iface_hps_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
system_acl_iface_hps_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53) // .hps_io_gpio_inst_GPIO53
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module dyn_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKFX1_OUT,
CLKFX2_OUT,
CLKDV_OUT,
DCM_SP_LOCKED_OUT,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
input CLKIN_IN;
wire CLKIN_IBUFG_OUT;
wire CLK0_OUT;
output CLKFX1_OUT;
output CLKFX2_OUT;
output CLKDV_OUT;
output DCM_SP_LOCKED_OUT;
input dcm_progclk;
input dcm_progdata;
input dcm_progen;
input dcm_reset;
output dcm_progdone;
output dcm_locked;
output [2:1] dcm_status;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFX1_BUF;
wire CLKFX2_BUF;
wire CLKDV_BUF;
wire GND_BIT;
wire dcm_progclk_buf;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLKFX1_BUFG_INST (.I(CLKFX1_BUF),
.O(CLKFX1_OUT));
BUFG CLKFX2_BUFG_INST (.I(CLKFX2_BUF),
.O(CLKFX2_OUT));
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG DCMPROGCLK_BUFG_INST (.I(dcm_progclk),
.O(dcm_progclk_buf));
// 100 MHZ osc gives fixed 50MHz CLKFX1, 12.5MHZ CLKDV
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(8.0), .CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX1_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(DCM_SP_LOCKED_OUT),
.PSDONE(),
.STATUS());
DCM_CLKGEN #(
.CLKFX_DIVIDE(100), // 100Mhz osc so gives steps of 1MHz
.CLKFX_MULTIPLY(SPEED_MHZ),
.CLKFXDV_DIVIDE(2), // Unused
.CLKIN_PERIOD(10.0),
.CLKFX_MD_MAX(0.000),
.SPREAD_SPECTRUM("NONE"),
.STARTUP_WAIT("FALSE")
)
DCM_CLKGEN_INST (
.CLKIN(CLKIN_IBUFG),
.CLKFX(CLKFX2_BUF),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata),
.PROGEN(dcm_progen),
.PROGDONE(dcm_progdone),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(dcm_reset)
);
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_mux_2
*/
module test_wb_mux_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs0_dat_i = 0;
reg wbs0_ack_i = 0;
reg wbs0_err_i = 0;
reg wbs0_rty_i = 0;
reg [ADDR_WIDTH-1:0] wbs0_addr = 0;
reg [ADDR_WIDTH-1:0] wbs0_addr_msk = 0;
reg [DATA_WIDTH-1:0] wbs1_dat_i = 0;
reg wbs1_ack_i = 0;
reg wbs1_err_i = 0;
reg wbs1_rty_i = 0;
reg [ADDR_WIDTH-1:0] wbs1_addr = 0;
reg [ADDR_WIDTH-1:0] wbs1_addr_msk = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs0_adr_o;
wire [DATA_WIDTH-1:0] wbs0_dat_o;
wire wbs0_we_o;
wire [SELECT_WIDTH-1:0] wbs0_sel_o;
wire wbs0_stb_o;
wire wbs0_cyc_o;
wire [ADDR_WIDTH-1:0] wbs1_adr_o;
wire [DATA_WIDTH-1:0] wbs1_dat_o;
wire wbs1_we_o;
wire [SELECT_WIDTH-1:0] wbs1_sel_o;
wire wbs1_stb_o;
wire wbs1_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs0_dat_i,
wbs0_ack_i,
wbs0_err_i,
wbs0_rty_i,
wbs0_addr,
wbs0_addr_msk,
wbs1_dat_i,
wbs1_ack_i,
wbs1_err_i,
wbs1_rty_i,
wbs1_addr,
wbs1_addr_msk);
$to_myhdl(wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs0_adr_o,
wbs0_dat_o,
wbs0_we_o,
wbs0_sel_o,
wbs0_stb_o,
wbs0_cyc_o,
wbs1_adr_o,
wbs1_dat_o,
wbs1_we_o,
wbs1_sel_o,
wbs1_stb_o,
wbs1_cyc_o);
// dump file
$dumpfile("test_wb_mux_2.lxt");
$dumpvars(0, test_wb_mux_2);
end
wb_mux_2 #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs0_adr_o(wbs0_adr_o),
.wbs0_dat_i(wbs0_dat_i),
.wbs0_dat_o(wbs0_dat_o),
.wbs0_we_o(wbs0_we_o),
.wbs0_sel_o(wbs0_sel_o),
.wbs0_stb_o(wbs0_stb_o),
.wbs0_ack_i(wbs0_ack_i),
.wbs0_err_i(wbs0_err_i),
.wbs0_rty_i(wbs0_rty_i),
.wbs0_cyc_o(wbs0_cyc_o),
.wbs0_addr(wbs0_addr),
.wbs0_addr_msk(wbs0_addr_msk),
.wbs1_adr_o(wbs1_adr_o),
.wbs1_dat_i(wbs1_dat_i),
.wbs1_dat_o(wbs1_dat_o),
.wbs1_we_o(wbs1_we_o),
.wbs1_sel_o(wbs1_sel_o),
.wbs1_stb_o(wbs1_stb_o),
.wbs1_ack_i(wbs1_ack_i),
.wbs1_err_i(wbs1_err_i),
.wbs1_rty_i(wbs1_rty_i),
.wbs1_cyc_o(wbs1_cyc_o),
.wbs1_addr(wbs1_addr),
.wbs1_addr_msk(wbs1_addr_msk)
);
endmodule
|
//==========================================
// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
// Coder : Alex Claros F.
// Date : 15/May/2005.
// Notes : This implementation is based on the article
// 'Asynchronous FIFO in Virtex-II FPGAs'
// writen by Peter Alfke. This TechXclusive
// article can be downloaded from the
// Xilinx website. It has some minor modifications.
//=========================================
`timescale 1ns / 1ps
module vgafb_asfifo
#(parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH))
//Reading port
(output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
assign Data_out = Mem[pNextWordToRead];
// always @ (posedge RClk)
// if (!PresetEmpty)
// Data_out <= Mem[pNextWordToRead];
// if (ReadEn_in & !Empty_out)
//'Data_in' logic:
always @ (posedge WClk)
if (WriteEn_in & !Full_out)
Mem[pNextWordToWrite] <= Data_in;
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
vgafb_graycounter #(
.COUNTER_WIDTH( ADDRESS_WIDTH )
) GrayCounter_pWr (
.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
vgafb_graycounter #(
.COUNTER_WIDTH( ADDRESS_WIDTH )
) GrayCounter_pRd (
.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in)
Status = 0; //Going 'Empty'.
else if (Set_Status)
Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull)
Full_out <= 1;
else
Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty)
Empty_out <= 1;
else
Empty_out <= 0;
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
Require Import Eqdep List Omega.
Set Implicit Arguments.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite app_ass.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Abort to backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => try rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'.
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2010/01/07 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_multi_mac_pcs_pma_gige
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
input wire gxb_pwrdn_in_0, // Powerdown signal to GXB
output wire pcs_pwrdn_out_0, // Powerdown Enable from PCS
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_0, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
input wire gxb_pwrdn_in_1, // Powerdown signal to GXB
output wire pcs_pwrdn_out_1, // Powerdown Enable from PCS
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_1, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
input wire gxb_pwrdn_in_2, // Powerdown signal to GXB
output wire pcs_pwrdn_out_2, // Powerdown Enable from PCS
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_2, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
input wire gxb_pwrdn_in_3, // Powerdown signal to GXB
output wire pcs_pwrdn_out_3, // Powerdown Enable from PCS
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_3, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
input wire gxb_pwrdn_in_4, // Powerdown signal to GXB
output wire pcs_pwrdn_out_4, // Powerdown Enable from PCS
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_4, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
input wire gxb_pwrdn_in_5, // Powerdown signal to GXB
output wire pcs_pwrdn_out_5, // Powerdown Enable from PCS
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_5, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
input wire gxb_pwrdn_in_6, // Powerdown signal to GXB
output wire pcs_pwrdn_out_6, // Powerdown Enable from PCS
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_6, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
input wire gxb_pwrdn_in_7, // Powerdown signal to GXB
output wire pcs_pwrdn_out_7, // Powerdown Enable from PCS
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_7, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
input wire gxb_pwrdn_in_8, // Powerdown signal to GXB
output wire pcs_pwrdn_out_8, // Powerdown Enable from PCS
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_8, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
input wire gxb_pwrdn_in_9, // Powerdown signal to GXB
output wire pcs_pwrdn_out_9, // Powerdown Enable from PCS
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_9, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
input wire gxb_pwrdn_in_10, // Powerdown signal to GXB
output wire pcs_pwrdn_out_10, // Powerdown Enable from PCS
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_10, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
input wire gxb_pwrdn_in_11, // Powerdown signal to GXB
output wire pcs_pwrdn_out_11, // Powerdown Enable from PCS
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_11, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
input wire gxb_pwrdn_in_12, // Powerdown signal to GXB
output wire pcs_pwrdn_out_12, // Powerdown Enable from PCS
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_12, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
input wire gxb_pwrdn_in_13, // Powerdown signal to GXB
output wire pcs_pwrdn_out_13, // Powerdown Enable from PCS
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_13, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
input wire gxb_pwrdn_in_14, // Powerdown signal to GXB
output wire pcs_pwrdn_out_14, // Powerdown Enable from PCS
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_14, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
input wire gxb_pwrdn_in_15, // Powerdown signal to GXB
output wire pcs_pwrdn_out_15, // Powerdown Enable from PCS
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_15, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
input wire gxb_pwrdn_in_16, // Powerdown signal to GXB
output wire pcs_pwrdn_out_16, // Powerdown Enable from PCS
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_16, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
input wire gxb_pwrdn_in_17, // Powerdown signal to GXB
output wire pcs_pwrdn_out_17, // Powerdown Enable from PCS
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_17, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
input wire gxb_pwrdn_in_18, // Powerdown signal to GXB
output wire pcs_pwrdn_out_18, // Powerdown Enable from PCS
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_18, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
input wire gxb_pwrdn_in_19, // Powerdown signal to GXB
output wire pcs_pwrdn_out_19, // Powerdown Enable from PCS
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_19, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
input wire gxb_pwrdn_in_20, // Powerdown signal to GXB
output wire pcs_pwrdn_out_20, // Powerdown Enable from PCS
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_20, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
input wire gxb_pwrdn_in_21, // Powerdown signal to GXB
output wire pcs_pwrdn_out_21, // Powerdown Enable from PCS
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_21, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
input wire gxb_pwrdn_in_22, // Powerdown signal to GXB
output wire pcs_pwrdn_out_22, // Powerdown Enable from PCS
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_22, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
input wire gxb_pwrdn_in_23, // Powerdown signal to GXB
output wire pcs_pwrdn_out_23, // Powerdown Enable from PCS
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_23, // Clock for reconfiguration block
input wire [3:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_23); // Signals from the gxb block to the reconfig block
wire MAC_PCS_reset;
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire pcs_clk_c0;
wire pcs_clk_c1;
wire pcs_clk_c2;
wire pcs_clk_c3;
wire pcs_clk_c4;
wire pcs_clk_c5;
wire pcs_clk_c6;
wire pcs_clk_c7;
wire pcs_clk_c8;
wire pcs_clk_c9;
wire pcs_clk_c10;
wire pcs_clk_c11;
wire pcs_clk_c12;
wire pcs_clk_c13;
wire pcs_clk_c14;
wire pcs_clk_c15;
wire pcs_clk_c16;
wire pcs_clk_c17;
wire pcs_clk_c18;
wire pcs_clk_c19;
wire pcs_clk_c20;
wire pcs_clk_c21;
wire pcs_clk_c22;
wire pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset)
begin
if (reset == 1)
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= reset;
pma_digital_rst2 <= reset;
end
else
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = pma_digital_rst2;
// Assign pcs clock for all channels
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(MAC_PCS_reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 0)
begin
assign gxb_pwrdn_in_sig[0] = gxb_pwrdn_in_0;
assign pcs_pwrdn_out_0 = pcs_pwrdn_out_sig[0];
end
else
begin
assign gxb_pwrdn_in_sig[0] = pcs_pwrdn_out_sig[0];
assign pcs_pwrdn_out_0 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 0)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(pcs_clk_c0),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_0
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[0]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_0),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_0),
.rx_datain (rxp_0),
.rx_dataout (rx_frame_0),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[0]),
.rx_errdetect (rx_char_err_gx[0]),
.rx_patterndetect (rx_patterndetect[0]),
.rx_rlv (rx_runlengthviolation[0]),
.rx_seriallpbken (sd_loopback_0),
.rx_syncstatus (rx_syncstatus[0]),
.tx_clkout (pcs_clk_c0),
.tx_ctrlenable (tx_kchar_0),
.tx_datain (tx_frame_0),
.tx_dataout (txp_0),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.rx_runningdisp(rx_runningdisp[0])
);
defparam
the_altera_tse_gxb_gige_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_0.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {17{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
assign pcs_clk_c0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 1)
begin
assign gxb_pwrdn_in_sig[1] = gxb_pwrdn_in_1;
assign pcs_pwrdn_out_1 = pcs_pwrdn_out_sig[1];
end
else
begin
assign gxb_pwrdn_in_sig[1] = pcs_pwrdn_out_sig[1];
assign pcs_pwrdn_out_1 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 1)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(pcs_clk_c1),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_1
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[1]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_1),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_1),
.rx_datain (rxp_1),
.rx_dataout (rx_frame_1),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[1]),
.rx_errdetect (rx_char_err_gx[1]),
.rx_patterndetect (rx_patterndetect[1]),
.rx_rlv (rx_runlengthviolation[1]),
.rx_seriallpbken (sd_loopback_1),
.rx_syncstatus (rx_syncstatus[1]),
.tx_clkout (pcs_clk_c1),
.tx_ctrlenable (tx_kchar_1),
.tx_datain (tx_frame_1),
.tx_dataout (txp_1),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.rx_runningdisp(rx_runningdisp[1])
);
defparam
the_altera_tse_gxb_gige_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_1.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 4,
the_altera_tse_gxb_gige_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {17{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
assign pcs_clk_c1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
begin
assign gxb_pwrdn_in_sig[2] = gxb_pwrdn_in_2;
assign pcs_pwrdn_out_2 = pcs_pwrdn_out_sig[2];
end
else
begin
assign gxb_pwrdn_in_sig[2] = pcs_pwrdn_out_sig[2];
assign pcs_pwrdn_out_2 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 2)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(pcs_clk_c2),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_2
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[2]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_2),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_2),
.rx_datain (rxp_2),
.rx_dataout (rx_frame_2),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[2]),
.rx_errdetect (rx_char_err_gx[2]),
.rx_patterndetect (rx_patterndetect[2]),
.rx_rlv (rx_runlengthviolation[2]),
.rx_seriallpbken (sd_loopback_2),
.rx_syncstatus (rx_syncstatus[2]),
.tx_clkout (pcs_clk_c2),
.tx_ctrlenable (tx_kchar_2),
.tx_datain (tx_frame_2),
.tx_dataout (txp_2),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.rx_runningdisp(rx_runningdisp[2])
);
defparam
the_altera_tse_gxb_gige_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_2.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 8,
the_altera_tse_gxb_gige_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {17{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
assign pcs_clk_c2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 3)
begin
assign gxb_pwrdn_in_sig[3] = gxb_pwrdn_in_3;
assign pcs_pwrdn_out_3 = pcs_pwrdn_out_sig[3];
end
else
begin
assign gxb_pwrdn_in_sig[3] = pcs_pwrdn_out_sig[3];
assign pcs_pwrdn_out_3 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 3)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(pcs_clk_c3),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_3
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[3]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_3),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_3),
.rx_datain (rxp_3),
.rx_dataout (rx_frame_3),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[3]),
.rx_errdetect (rx_char_err_gx[3]),
.rx_patterndetect (rx_patterndetect[3]),
.rx_rlv (rx_runlengthviolation[3]),
.rx_seriallpbken (sd_loopback_3),
.rx_syncstatus (rx_syncstatus[3]),
.tx_clkout (pcs_clk_c3),
.tx_ctrlenable (tx_kchar_3),
.tx_datain (tx_frame_3),
.tx_dataout (txp_3),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.rx_runningdisp(rx_runningdisp[3])
);
defparam
the_altera_tse_gxb_gige_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_3.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 12,
the_altera_tse_gxb_gige_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {17{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
assign pcs_clk_c3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 4)
begin
assign gxb_pwrdn_in_sig[4] = gxb_pwrdn_in_4;
assign pcs_pwrdn_out_4 = pcs_pwrdn_out_sig[4];
end
else
begin
assign gxb_pwrdn_in_sig[4] = pcs_pwrdn_out_sig[4];
assign pcs_pwrdn_out_4 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 4)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(pcs_clk_c4),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_4
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[4]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_4),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_4),
.rx_datain (rxp_4),
.rx_dataout (rx_frame_4),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[4]),
.rx_errdetect (rx_char_err_gx[4]),
.rx_patterndetect (rx_patterndetect[4]),
.rx_rlv (rx_runlengthviolation[4]),
.rx_seriallpbken (sd_loopback_4),
.rx_syncstatus (rx_syncstatus[4]),
.tx_clkout (pcs_clk_c4),
.tx_ctrlenable (tx_kchar_4),
.tx_datain (tx_frame_4),
.tx_dataout (txp_4),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.rx_runningdisp(rx_runningdisp[4])
);
defparam
the_altera_tse_gxb_gige_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_4.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 16,
the_altera_tse_gxb_gige_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {17{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
assign pcs_clk_c4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 5)
begin
assign gxb_pwrdn_in_sig[5] = gxb_pwrdn_in_5;
assign pcs_pwrdn_out_5 = pcs_pwrdn_out_sig[5];
end
else
begin
assign gxb_pwrdn_in_sig[5] = pcs_pwrdn_out_sig[5];
assign pcs_pwrdn_out_5 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 5)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(pcs_clk_c5),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_5
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[5]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_5),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_5),
.rx_datain (rxp_5),
.rx_dataout (rx_frame_5),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[5]),
.rx_errdetect (rx_char_err_gx[5]),
.rx_patterndetect (rx_patterndetect[5]),
.rx_rlv (rx_runlengthviolation[5]),
.rx_seriallpbken (sd_loopback_5),
.rx_syncstatus (rx_syncstatus[5]),
.tx_clkout (pcs_clk_c5),
.tx_ctrlenable (tx_kchar_5),
.tx_datain (tx_frame_5),
.tx_dataout (txp_5),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.rx_runningdisp(rx_runningdisp[5])
);
defparam
the_altera_tse_gxb_gige_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_5.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 20,
the_altera_tse_gxb_gige_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {17{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
assign pcs_clk_c5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 6)
begin
assign gxb_pwrdn_in_sig[6] = gxb_pwrdn_in_6;
assign pcs_pwrdn_out_6 = pcs_pwrdn_out_sig[6];
end
else
begin
assign gxb_pwrdn_in_sig[6] = pcs_pwrdn_out_sig[6];
assign pcs_pwrdn_out_6 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 6)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(pcs_clk_c6),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_6
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[6]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_6),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_6),
.rx_datain (rxp_6),
.rx_dataout (rx_frame_6),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[6]),
.rx_errdetect (rx_char_err_gx[6]),
.rx_patterndetect (rx_patterndetect[6]),
.rx_rlv (rx_runlengthviolation[6]),
.rx_seriallpbken (sd_loopback_6),
.rx_syncstatus (rx_syncstatus[6]),
.tx_clkout (pcs_clk_c6),
.tx_ctrlenable (tx_kchar_6),
.tx_datain (tx_frame_6),
.tx_dataout (txp_6),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.rx_runningdisp(rx_runningdisp[6])
);
defparam
the_altera_tse_gxb_gige_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_6.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 24,
the_altera_tse_gxb_gige_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {17{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
assign pcs_clk_c6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 7)
begin
assign gxb_pwrdn_in_sig[7] = gxb_pwrdn_in_7;
assign pcs_pwrdn_out_7 = pcs_pwrdn_out_sig[7];
end
else
begin
assign gxb_pwrdn_in_sig[7] = pcs_pwrdn_out_sig[7];
assign pcs_pwrdn_out_7 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 7)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(pcs_clk_c7),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_7
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[7]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_7),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_7),
.rx_datain (rxp_7),
.rx_dataout (rx_frame_7),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[7]),
.rx_errdetect (rx_char_err_gx[7]),
.rx_patterndetect (rx_patterndetect[7]),
.rx_rlv (rx_runlengthviolation[7]),
.rx_seriallpbken (sd_loopback_7),
.rx_syncstatus (rx_syncstatus[7]),
.tx_clkout (pcs_clk_c7),
.tx_ctrlenable (tx_kchar_7),
.tx_datain (tx_frame_7),
.tx_dataout (txp_7),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.rx_runningdisp(rx_runningdisp[7])
);
defparam
the_altera_tse_gxb_gige_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_7.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 24,
the_altera_tse_gxb_gige_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {17{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
assign pcs_clk_c7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 8)
begin
assign gxb_pwrdn_in_sig[8] = gxb_pwrdn_in_8;
assign pcs_pwrdn_out_8 = pcs_pwrdn_out_sig[8];
end
else
begin
assign gxb_pwrdn_in_sig[8] = pcs_pwrdn_out_sig[8];
assign pcs_pwrdn_out_8 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 8)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(pcs_clk_c8),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_8
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[8]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_8),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_8),
.rx_datain (rxp_8),
.rx_dataout (rx_frame_8),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[8]),
.rx_errdetect (rx_char_err_gx[8]),
.rx_patterndetect (rx_patterndetect[8]),
.rx_rlv (rx_runlengthviolation[8]),
.rx_seriallpbken (sd_loopback_8),
.rx_syncstatus (rx_syncstatus[8]),
.tx_clkout (pcs_clk_c8),
.tx_ctrlenable (tx_kchar_8),
.tx_datain (tx_frame_8),
.tx_dataout (txp_8),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.rx_runningdisp(rx_runningdisp[8])
);
defparam
the_altera_tse_gxb_gige_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_8.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 32,
the_altera_tse_gxb_gige_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {17{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
assign pcs_clk_c8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 9)
begin
assign gxb_pwrdn_in_sig[9] = gxb_pwrdn_in_9;
assign pcs_pwrdn_out_9 = pcs_pwrdn_out_sig[9];
end
else
begin
assign gxb_pwrdn_in_sig[9] = pcs_pwrdn_out_sig[9];
assign pcs_pwrdn_out_9 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 9)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(pcs_clk_c9),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_9
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[9]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_9),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_9),
.rx_datain (rxp_9),
.rx_dataout (rx_frame_9),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[9]),
.rx_errdetect (rx_char_err_gx[9]),
.rx_patterndetect (rx_patterndetect[9]),
.rx_rlv (rx_runlengthviolation[9]),
.rx_seriallpbken (sd_loopback_9),
.rx_syncstatus (rx_syncstatus[9]),
.tx_clkout (pcs_clk_c9),
.tx_ctrlenable (tx_kchar_9),
.tx_datain (tx_frame_9),
.tx_dataout (txp_9),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.rx_runningdisp(rx_runningdisp[9])
);
defparam
the_altera_tse_gxb_gige_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_9.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 36,
the_altera_tse_gxb_gige_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {17{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
assign pcs_clk_c9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 10)
begin
assign gxb_pwrdn_in_sig[10] = gxb_pwrdn_in_10;
assign pcs_pwrdn_out_10 = pcs_pwrdn_out_sig[10];
end
else
begin
assign gxb_pwrdn_in_sig[10] = pcs_pwrdn_out_sig[10];
assign pcs_pwrdn_out_10 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 10)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(pcs_clk_c10),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_10
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[10]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_10),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_10),
.rx_datain (rxp_10),
.rx_dataout (rx_frame_10),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[10]),
.rx_errdetect (rx_char_err_gx[10]),
.rx_patterndetect (rx_patterndetect[10]),
.rx_rlv (rx_runlengthviolation[10]),
.rx_seriallpbken (sd_loopback_10),
.rx_syncstatus (rx_syncstatus[10]),
.tx_clkout (pcs_clk_c10),
.tx_ctrlenable (tx_kchar_10),
.tx_datain (tx_frame_10),
.tx_dataout (txp_10),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.rx_runningdisp(rx_runningdisp[10])
);
defparam
the_altera_tse_gxb_gige_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_10.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 40,
the_altera_tse_gxb_gige_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {17{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
assign pcs_clk_c10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 11)
begin
assign gxb_pwrdn_in_sig[11] = gxb_pwrdn_in_11;
assign pcs_pwrdn_out_11 = pcs_pwrdn_out_sig[11];
end
else
begin
assign gxb_pwrdn_in_sig[11] = pcs_pwrdn_out_sig[11];
assign pcs_pwrdn_out_11 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 11)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(pcs_clk_c11),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_11
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[11]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_11),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_11),
.rx_datain (rxp_11),
.rx_dataout (rx_frame_11),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[11]),
.rx_errdetect (rx_char_err_gx[11]),
.rx_patterndetect (rx_patterndetect[11]),
.rx_rlv (rx_runlengthviolation[11]),
.rx_seriallpbken (sd_loopback_11),
.rx_syncstatus (rx_syncstatus[11]),
.tx_clkout (pcs_clk_c11),
.tx_ctrlenable (tx_kchar_11),
.tx_datain (tx_frame_11),
.tx_dataout (txp_11),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.rx_runningdisp(rx_runningdisp[11])
);
defparam
the_altera_tse_gxb_gige_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_11.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 44,
the_altera_tse_gxb_gige_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {17{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
assign pcs_clk_c11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 12)
begin
assign gxb_pwrdn_in_sig[12] = gxb_pwrdn_in_12;
assign pcs_pwrdn_out_12 = pcs_pwrdn_out_sig[12];
end
else
begin
assign gxb_pwrdn_in_sig[12] = pcs_pwrdn_out_sig[12];
assign pcs_pwrdn_out_12 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 12)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(pcs_clk_c12),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_12
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[12]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_12),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_12),
.rx_datain (rxp_12),
.rx_dataout (rx_frame_12),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[12]),
.rx_errdetect (rx_char_err_gx[12]),
.rx_patterndetect (rx_patterndetect[12]),
.rx_rlv (rx_runlengthviolation[12]),
.rx_seriallpbken (sd_loopback_12),
.rx_syncstatus (rx_syncstatus[12]),
.tx_clkout (pcs_clk_c12),
.tx_ctrlenable (tx_kchar_12),
.tx_datain (tx_frame_12),
.tx_dataout (txp_12),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.rx_runningdisp(rx_runningdisp[12])
);
defparam
the_altera_tse_gxb_gige_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_12.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 48,
the_altera_tse_gxb_gige_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {17{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
assign pcs_clk_c12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 13)
begin
assign gxb_pwrdn_in_sig[13] = gxb_pwrdn_in_13;
assign pcs_pwrdn_out_13 = pcs_pwrdn_out_sig[13];
end
else
begin
assign gxb_pwrdn_in_sig[13] = pcs_pwrdn_out_sig[13];
assign pcs_pwrdn_out_13 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 13)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(pcs_clk_c13),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_13
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[13]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_13),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_13),
.rx_datain (rxp_13),
.rx_dataout (rx_frame_13),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[13]),
.rx_errdetect (rx_char_err_gx[13]),
.rx_patterndetect (rx_patterndetect[13]),
.rx_rlv (rx_runlengthviolation[13]),
.rx_seriallpbken (sd_loopback_13),
.rx_syncstatus (rx_syncstatus[13]),
.tx_clkout (pcs_clk_c13),
.tx_ctrlenable (tx_kchar_13),
.tx_datain (tx_frame_13),
.tx_dataout (txp_13),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.rx_runningdisp(rx_runningdisp[13])
);
defparam
the_altera_tse_gxb_gige_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_13.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 52,
the_altera_tse_gxb_gige_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {17{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
assign pcs_clk_c13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 14)
begin
assign gxb_pwrdn_in_sig[14] = gxb_pwrdn_in_14;
assign pcs_pwrdn_out_14 = pcs_pwrdn_out_sig[14];
end
else
begin
assign gxb_pwrdn_in_sig[14] = pcs_pwrdn_out_sig[14];
assign pcs_pwrdn_out_14 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 14)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(pcs_clk_c14),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_14
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[14]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_14),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_14),
.rx_datain (rxp_14),
.rx_dataout (rx_frame_14),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[14]),
.rx_errdetect (rx_char_err_gx[14]),
.rx_patterndetect (rx_patterndetect[14]),
.rx_rlv (rx_runlengthviolation[14]),
.rx_seriallpbken (sd_loopback_14),
.rx_syncstatus (rx_syncstatus[14]),
.tx_clkout (pcs_clk_c14),
.tx_ctrlenable (tx_kchar_14),
.tx_datain (tx_frame_14),
.tx_dataout (txp_14),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.rx_runningdisp(rx_runningdisp[14])
);
defparam
the_altera_tse_gxb_gige_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_14.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 56,
the_altera_tse_gxb_gige_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {17{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
assign pcs_clk_c14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 15)
begin
assign gxb_pwrdn_in_sig[15] = gxb_pwrdn_in_15;
assign pcs_pwrdn_out_15 = pcs_pwrdn_out_sig[15];
end
else
begin
assign gxb_pwrdn_in_sig[15] = pcs_pwrdn_out_sig[15];
assign pcs_pwrdn_out_15 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 15)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(pcs_clk_c15),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_15
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[15]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_15),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_15),
.rx_datain (rxp_15),
.rx_dataout (rx_frame_15),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[15]),
.rx_errdetect (rx_char_err_gx[15]),
.rx_patterndetect (rx_patterndetect[15]),
.rx_rlv (rx_runlengthviolation[15]),
.rx_seriallpbken (sd_loopback_15),
.rx_syncstatus (rx_syncstatus[15]),
.tx_clkout (pcs_clk_c15),
.tx_ctrlenable (tx_kchar_15),
.tx_datain (tx_frame_15),
.tx_dataout (txp_15),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.rx_runningdisp(rx_runningdisp[15])
);
defparam
the_altera_tse_gxb_gige_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_15.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 60,
the_altera_tse_gxb_gige_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {17{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
assign pcs_clk_c15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 16)
begin
assign gxb_pwrdn_in_sig[16] = gxb_pwrdn_in_16;
assign pcs_pwrdn_out_16 = pcs_pwrdn_out_sig[16];
end
else
begin
assign gxb_pwrdn_in_sig[16] = pcs_pwrdn_out_sig[16];
assign pcs_pwrdn_out_16 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 16)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(pcs_clk_c16),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_16
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[16]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_16),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_16),
.rx_datain (rxp_16),
.rx_dataout (rx_frame_16),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[16]),
.rx_errdetect (rx_char_err_gx[16]),
.rx_patterndetect (rx_patterndetect[16]),
.rx_rlv (rx_runlengthviolation[16]),
.rx_seriallpbken (sd_loopback_16),
.rx_syncstatus (rx_syncstatus[16]),
.tx_clkout (pcs_clk_c16),
.tx_ctrlenable (tx_kchar_16),
.tx_datain (tx_frame_16),
.tx_dataout (txp_16),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.rx_runningdisp(rx_runningdisp[16])
);
defparam
the_altera_tse_gxb_gige_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_16.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 64,
the_altera_tse_gxb_gige_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {17{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
assign pcs_clk_c16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 17)
begin
assign gxb_pwrdn_in_sig[17] = gxb_pwrdn_in_17;
assign pcs_pwrdn_out_17 = pcs_pwrdn_out_sig[17];
end
else
begin
assign gxb_pwrdn_in_sig[17] = pcs_pwrdn_out_sig[17];
assign pcs_pwrdn_out_17 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 17)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(pcs_clk_c17),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_17
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[17]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_17),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_17),
.rx_datain (rxp_17),
.rx_dataout (rx_frame_17),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[17]),
.rx_errdetect (rx_char_err_gx[17]),
.rx_patterndetect (rx_patterndetect[17]),
.rx_rlv (rx_runlengthviolation[17]),
.rx_seriallpbken (sd_loopback_17),
.rx_syncstatus (rx_syncstatus[17]),
.tx_clkout (pcs_clk_c17),
.tx_ctrlenable (tx_kchar_17),
.tx_datain (tx_frame_17),
.tx_dataout (txp_17),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.rx_runningdisp(rx_runningdisp[17])
);
defparam
the_altera_tse_gxb_gige_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_17.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 68,
the_altera_tse_gxb_gige_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {17{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
assign pcs_clk_c17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 18)
begin
assign gxb_pwrdn_in_sig[18] = gxb_pwrdn_in_18;
assign pcs_pwrdn_out_18 = pcs_pwrdn_out_sig[18];
end
else
begin
assign gxb_pwrdn_in_sig[18] = pcs_pwrdn_out_sig[18];
assign pcs_pwrdn_out_18 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 18)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(pcs_clk_c18),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_18
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[18]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_18),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_18),
.rx_datain (rxp_18),
.rx_dataout (rx_frame_18),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[18]),
.rx_errdetect (rx_char_err_gx[18]),
.rx_patterndetect (rx_patterndetect[18]),
.rx_rlv (rx_runlengthviolation[18]),
.rx_seriallpbken (sd_loopback_18),
.rx_syncstatus (rx_syncstatus[18]),
.tx_clkout (pcs_clk_c18),
.tx_ctrlenable (tx_kchar_18),
.tx_datain (tx_frame_18),
.tx_dataout (txp_18),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.rx_runningdisp(rx_runningdisp[18])
);
defparam
the_altera_tse_gxb_gige_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_18.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 72,
the_altera_tse_gxb_gige_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {17{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
assign pcs_clk_c18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 19)
begin
assign gxb_pwrdn_in_sig[19] = gxb_pwrdn_in_19;
assign pcs_pwrdn_out_19 = pcs_pwrdn_out_sig[19];
end
else
begin
assign gxb_pwrdn_in_sig[19] = pcs_pwrdn_out_sig[19];
assign pcs_pwrdn_out_19 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 19)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(pcs_clk_c19),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_19
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[19]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_19),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_19),
.rx_datain (rxp_19),
.rx_dataout (rx_frame_19),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[19]),
.rx_errdetect (rx_char_err_gx[19]),
.rx_patterndetect (rx_patterndetect[19]),
.rx_rlv (rx_runlengthviolation[19]),
.rx_seriallpbken (sd_loopback_19),
.rx_syncstatus (rx_syncstatus[19]),
.tx_clkout (pcs_clk_c19),
.tx_ctrlenable (tx_kchar_19),
.tx_datain (tx_frame_19),
.tx_dataout (txp_19),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.rx_runningdisp(rx_runningdisp[19])
);
defparam
the_altera_tse_gxb_gige_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_19.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 76,
the_altera_tse_gxb_gige_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {17{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
assign pcs_clk_c19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 20)
begin
assign gxb_pwrdn_in_sig[20] = gxb_pwrdn_in_20;
assign pcs_pwrdn_out_20 = pcs_pwrdn_out_sig[20];
end
else
begin
assign gxb_pwrdn_in_sig[20] = pcs_pwrdn_out_sig[20];
assign pcs_pwrdn_out_20 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 20)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(pcs_clk_c20),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_20
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[20]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_20),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_20),
.rx_datain (rxp_20),
.rx_dataout (rx_frame_20),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[20]),
.rx_errdetect (rx_char_err_gx[20]),
.rx_patterndetect (rx_patterndetect[20]),
.rx_rlv (rx_runlengthviolation[20]),
.rx_seriallpbken (sd_loopback_20),
.rx_syncstatus (rx_syncstatus[20]),
.tx_clkout (pcs_clk_c20),
.tx_ctrlenable (tx_kchar_20),
.tx_datain (tx_frame_20),
.tx_dataout (txp_20),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.rx_runningdisp(rx_runningdisp[20])
);
defparam
the_altera_tse_gxb_gige_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_20.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 80,
the_altera_tse_gxb_gige_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {17{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
assign pcs_clk_c20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 21)
begin
assign gxb_pwrdn_in_sig[21] = gxb_pwrdn_in_21;
assign pcs_pwrdn_out_21 = pcs_pwrdn_out_sig[21];
end
else
begin
assign gxb_pwrdn_in_sig[21] = pcs_pwrdn_out_sig[21];
assign pcs_pwrdn_out_21 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 21)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(pcs_clk_c21),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_21
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[21]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_21),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_21),
.rx_datain (rxp_21),
.rx_dataout (rx_frame_21),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[21]),
.rx_errdetect (rx_char_err_gx[21]),
.rx_patterndetect (rx_patterndetect[21]),
.rx_rlv (rx_runlengthviolation[21]),
.rx_seriallpbken (sd_loopback_21),
.rx_syncstatus (rx_syncstatus[21]),
.tx_clkout (pcs_clk_c21),
.tx_ctrlenable (tx_kchar_21),
.tx_datain (tx_frame_21),
.tx_dataout (txp_21),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.rx_runningdisp(rx_runningdisp[21])
);
defparam
the_altera_tse_gxb_gige_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_21.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 84,
the_altera_tse_gxb_gige_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {17{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
assign pcs_clk_c21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 22)
begin
assign gxb_pwrdn_in_sig[22] = gxb_pwrdn_in_22;
assign pcs_pwrdn_out_22 = pcs_pwrdn_out_sig[22];
end
else
begin
assign gxb_pwrdn_in_sig[22] = pcs_pwrdn_out_sig[22];
assign pcs_pwrdn_out_22 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 22)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(pcs_clk_c22),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_22
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[22]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_22),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_22),
.rx_datain (rxp_22),
.rx_dataout (rx_frame_22),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[22]),
.rx_errdetect (rx_char_err_gx[22]),
.rx_patterndetect (rx_patterndetect[22]),
.rx_rlv (rx_runlengthviolation[22]),
.rx_seriallpbken (sd_loopback_22),
.rx_syncstatus (rx_syncstatus[22]),
.tx_clkout (pcs_clk_c22),
.tx_ctrlenable (tx_kchar_22),
.tx_datain (tx_frame_22),
.tx_dataout (txp_22),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.rx_runningdisp(rx_runningdisp[22])
);
defparam
the_altera_tse_gxb_gige_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_22.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 88,
the_altera_tse_gxb_gige_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {17{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
assign pcs_clk_c22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 23)
begin
assign gxb_pwrdn_in_sig[23] = gxb_pwrdn_in_23;
assign pcs_pwrdn_out_23 = pcs_pwrdn_out_sig[23];
end
else
begin
assign gxb_pwrdn_in_sig[23] = pcs_pwrdn_out_sig[23];
assign pcs_pwrdn_out_23 = 1'b0;
end
endgenerate
generate if (MAX_CHANNELS > 23)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(pcs_clk_c23),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_23
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[23]),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk_23),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_23),
.rx_datain (rxp_23),
.rx_dataout (rx_frame_23),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err[23]),
.rx_errdetect (rx_char_err_gx[23]),
.rx_patterndetect (rx_patterndetect[23]),
.rx_rlv (rx_runlengthviolation[23]),
.rx_seriallpbken (sd_loopback_23),
.rx_syncstatus (rx_syncstatus[23]),
.tx_clkout (pcs_clk_c23),
.tx_ctrlenable (tx_kchar_23),
.tx_datain (tx_frame_23),
.tx_dataout (txp_23),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.rx_runningdisp(rx_runningdisp[23])
);
defparam
the_altera_tse_gxb_gige_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_23.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 92,
the_altera_tse_gxb_gige_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {17{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
assign pcs_clk_c23 = 1'b0;
end
endgenerate
endmodule // module altera_tse_multi_mac_pcs_pma_gige
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_dp_maca_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_dp_maca_r(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca, rclk,
scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_out_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
// ======================================================================
// BotPsoc.v generated from TopDesign.cysch
// 02/19/2014 at 09:42
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 4
`define CYDEV_CHIP_REV_EXPECT 0
`define CYDEV_CHIP_DIE_ACTUAL 4
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 3
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 4
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 3
`define CYDEV_CHIP_MEMBER_USED 4
`define CYDEV_CHIP_REVISION_USED 0
// Component: B_SPI_Slave_v2_60
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Slave_v2_60"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Slave_v2_60\B_SPI_Slave_v2_60.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Slave_v2_60"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Slave_v2_60\B_SPI_Slave_v2_60.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: not_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v"
`endif
// SPI_Slave_v2_60(BidirectMode=false, ClockInternal=false, ControlFileName=SPI_Slave_Default.ctl, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CyGetRegReplacementString_1=CY_GET_REG8, CyGetRegReplacementString_2=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, DesiredBitRate=1000000, FixedPlacementEnabled=false, InternalInterruptEnabled=0, InternalRxInterruptEnabled=0, InternalTxInterruptEnabled=0, InterruptOnByteComplete=false, InterruptOnDone=false, InterruptOnRXEmpty=false, InterruptOnRXFull=false, InterruptOnRXNotEmpty=true, InterruptOnRXOverrun=false, InterruptOnTXEmpty=true, InterruptOnTXFull=false, InterruptOnTXNotFull=false, IntOnByteComp=0, IntOnRXEmpty=0, IntOnRXFull=0, IntOnRXNotEmpty=1, IntOnRXOver=0, IntOnSPIDone=0, IntOnTXEmpty=1, IntOnTXFull=0, IntOnTXNotFull=0, Mode=0, ModeUseZero=1, MultiSlaveEnable=false, NumberOfDataBits=8, PSoC3_ES2_PSoC5_ES1=false, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, RxBufferSize=4, ShiftDir=0, SiliconRevisionReplacementString=es3, TxBufferSize=4, UseInternalInterrupt=false, UseRxInternalInterrupt=false, UseTxInternalInterrupt=false, VerilogSectionReplacementString=sR8, CY_COMPONENT_NAME=SPI_Slave_v2_60, CY_CONTROL_FILE=SPI_Slave_Default.ctl, CY_FITTER_NAME=PiComs, CY_INSTANCE_SHORT_NAME=PiComs, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=60, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=PiComs, )
module SPI_Slave_v2_60_0 (
ss,
mosi,
sclk,
miso,
clock,
tx_interrupt,
sdat,
rx_interrupt,
miso_oe,
reset);
input ss;
input mosi;
input sclk;
output miso;
input clock;
output tx_interrupt;
inout sdat;
output rx_interrupt;
output miso_oe;
input reset;
parameter NumberOfDataBits = 8;
parameter ShiftDir = 0;
wire Net_131;
wire Net_89;
wire Net_81;
wire Net_77;
wire Net_75;
wire miso_wire;
wire Net_146;
B_SPI_Slave_v2_60 BSPIS (
.mosi(Net_75),
.sclk(sclk),
.ss(ss),
.miso(miso_wire),
.reset(reset),
.clock(Net_81),
.tx_interpt(tx_interrupt),
.tx_enable(Net_146),
.rx_interpt(rx_interrupt));
defparam BSPIS.BidirectMode = 0;
defparam BSPIS.ModeCPHA = 0;
defparam BSPIS.ModePOL = 0;
defparam BSPIS.NumberOfDataBits = 8;
defparam BSPIS.ShiftDir = 0;
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_75 = mosi;
// VirtualMux_2 (cy_virtualmux_v1_0)
assign Net_81 = clock;
assign miso_oe = ~ss;
assign miso = miso_wire;
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// Component: LUT_v1_50
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\LUT_v1_50"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\LUT_v1_50\LUT_v1_50.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\LUT_v1_50"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\LUT_v1_50\LUT_v1_50.v"
`endif
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// PWM_v3_0(CaptureMode=0, Compare1_16=false, Compare1_8=false, Compare2_16=false, Compare2_8=false, CompareStatusEdgeSense=true, CompareType1=1, CompareType1Software=0, CompareType2=1, CompareType2Software=0, CompareValue1=0, CompareValue2=63, CONTROL3=1, ControlReg=false, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG16, CySetRegReplacementString=CY_SET_REG16, DeadBand=0, DeadBand2_4=0, DeadBand256=0, DeadBandUsed=0, DeadTime=1, DitherOffset=0, EnableMode=0, FF16=true, FF8=false, FixedFunction=true, FixedFunctionUsed=1, InterruptOnCMP1=false, InterruptOnCMP2=false, InterruptOnKill=false, InterruptOnTC=false, IntOnCMP1=0, IntOnCMP2=0, IntOnKill=0, IntOnTC=0, KillMode=1, KillModeMinTime=0, MinimumKillTime=1, OneCompare=true, Period=65535, PWMMode=0, PWMModeCenterAligned=0, RegDefReplacementString=reg16, RegSizeReplacementString=uint16, Resolution=16, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, Status=false, TriggerMode=0, UDB16=false, UDB8=false, UseControl=true, UseInterrupt=false, UseStatus=false, VerilogSectionReplacementString=sP16, CY_COMPONENT_NAME=PWM_v3_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LMotorPwm, CY_INSTANCE_SHORT_NAME=LMotorPwm, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LMotorPwm, )
module PWM_v3_0_1 (
pwm2,
tc,
clock,
reset,
pwm1,
interrupt,
capture,
kill,
enable,
trigger,
cmp_sel,
pwm,
ph1,
ph2);
output pwm2;
output tc;
input clock;
input reset;
output pwm1;
output interrupt;
input capture;
input kill;
input enable;
input trigger;
input cmp_sel;
output pwm;
output ph1;
output ph2;
parameter Resolution = 16;
wire Net_114;
wire Net_113;
wire Net_107;
wire Net_96;
wire Net_55;
wire Net_57;
wire Net_101;
wire Net_54;
wire Net_63;
cy_psoc3_timer_v1_0 PWMHW (
.timer_reset(reset),
.capture(capture),
.enable(Net_113),
.kill(Net_107),
.clock(clock),
.tc(Net_63),
.compare(Net_57),
.interrupt(Net_54));
// vmCompare (cy_virtualmux_v1_0)
assign pwm = Net_57;
// vmIRQ (cy_virtualmux_v1_0)
assign interrupt = Net_54;
// vmTC (cy_virtualmux_v1_0)
assign tc = Net_63;
OneTerminal OneTerminal_1 (
.o(Net_113));
// FFKillMux (cy_virtualmux_v1_0)
assign Net_107 = kill;
ZeroTerminal ZeroTerminal_1 (
.z(Net_114));
endmodule
// PWM_v3_0(CaptureMode=0, Compare1_16=false, Compare1_8=false, Compare2_16=false, Compare2_8=false, CompareStatusEdgeSense=true, CompareType1=1, CompareType1Software=0, CompareType2=1, CompareType2Software=0, CompareValue1=0, CompareValue2=63, CONTROL3=1, ControlReg=false, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG16, CySetRegReplacementString=CY_SET_REG16, DeadBand=0, DeadBand2_4=0, DeadBand256=0, DeadBandUsed=0, DeadTime=1, DitherOffset=0, EnableMode=0, FF16=true, FF8=false, FixedFunction=true, FixedFunctionUsed=1, InterruptOnCMP1=false, InterruptOnCMP2=false, InterruptOnKill=false, InterruptOnTC=false, IntOnCMP1=0, IntOnCMP2=0, IntOnKill=0, IntOnTC=0, KillMode=1, KillModeMinTime=0, MinimumKillTime=1, OneCompare=true, Period=65535, PWMMode=0, PWMModeCenterAligned=0, RegDefReplacementString=reg16, RegSizeReplacementString=uint16, Resolution=16, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, Status=false, TriggerMode=0, UDB16=false, UDB8=false, UseControl=true, UseInterrupt=false, UseStatus=false, VerilogSectionReplacementString=sP16, CY_COMPONENT_NAME=PWM_v3_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=RMotorPwm, CY_INSTANCE_SHORT_NAME=RMotorPwm, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=RMotorPwm, )
module PWM_v3_0_2 (
pwm2,
tc,
clock,
reset,
pwm1,
interrupt,
capture,
kill,
enable,
trigger,
cmp_sel,
pwm,
ph1,
ph2);
output pwm2;
output tc;
input clock;
input reset;
output pwm1;
output interrupt;
input capture;
input kill;
input enable;
input trigger;
input cmp_sel;
output pwm;
output ph1;
output ph2;
parameter Resolution = 16;
wire Net_114;
wire Net_113;
wire Net_107;
wire Net_96;
wire Net_55;
wire Net_57;
wire Net_101;
wire Net_54;
wire Net_63;
cy_psoc3_timer_v1_0 PWMHW (
.timer_reset(reset),
.capture(capture),
.enable(Net_113),
.kill(Net_107),
.clock(clock),
.tc(Net_63),
.compare(Net_57),
.interrupt(Net_54));
// vmCompare (cy_virtualmux_v1_0)
assign pwm = Net_57;
// vmIRQ (cy_virtualmux_v1_0)
assign interrupt = Net_54;
// vmTC (cy_virtualmux_v1_0)
assign tc = Net_63;
OneTerminal OneTerminal_1 (
.o(Net_113));
// FFKillMux (cy_virtualmux_v1_0)
assign Net_107 = kill;
ZeroTerminal ZeroTerminal_1 (
.z(Net_114));
endmodule
// Component: CyControlReg_v1_70
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v"
`endif
// top
module top ;
wire Net_510;
wire Net_508;
wire Net_488;
wire Net_486;
wire Net_469;
wire Net_468;
wire Net_467;
wire Net_466;
wire Net_465;
wire Net_464;
wire Net_463;
wire Net_462;
wire Net_461;
wire Net_460;
wire Net_459;
wire Net_427;
wire Net_458;
wire Net_457;
wire Net_456;
wire Net_455;
wire Net_454;
wire Net_420;
wire Net_419;
electrical Net_235;
electrical Net_472;
electrical Net_135;
electrical Net_473;
wire Net_412;
wire Net_411;
wire Net_409;
wire Net_408;
wire Net_407;
wire Net_405;
wire Net_404;
wire Net_403;
wire Net_402;
wire Net_401;
wire Net_406;
electrical Net_253;
electrical Net_476;
electrical Net_252;
wire Net_399;
electrical Net_477;
wire Net_336;
wire Net_335;
wire Net_334;
wire Net_333;
wire Net_332;
wire Net_331;
wire Net_330;
wire Net_356;
wire Net_355;
wire Net_354;
wire Net_353;
wire Net_352;
wire Net_351;
wire Net_350;
wire Net_88;
wire Net_87;
wire Net_58;
wire Net_82;
wire Net_81;
wire Net_55;
wire Net_74;
wire Net_72;
wire Net_50;
wire Net_509;
wire Net_506;
wire Net_49;
wire Net_46;
wire Net_47;
wire Net_48;
wire Net_444;
wire Net_328;
wire Net_329;
wire Net_447;
wire Net_431;
wire Net_418;
wire Net_327;
wire Net_474;
wire Net_475;
wire Net_151;
wire Net_150;
wire Net_470;
wire Net_471;
wire Net_234;
wire Net_146;
electrical Net_128;
electrical Net_109;
electrical Net_120;
electrical Net_119;
electrical Net_115;
electrical Net_112;
wire Net_482;
wire Net_484;
wire [0:0] tmpOE__Debug0_net;
wire [0:0] tmpFB_0__Debug0_net;
wire [0:0] tmpIO_0__Debug0_net;
wire [0:0] tmpINTERRUPT_0__Debug0_net;
electrical [0:0] tmpSIOVREF__Debug0_net;
cy_psoc3_pins_v1_10
#(.id("52f31aa9-2f0a-497d-9a1f-1424095e13e6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug0
(.oe(tmpOE__Debug0_net),
.y({1'b0}),
.fb({tmpFB_0__Debug0_net[0:0]}),
.io({tmpIO_0__Debug0_net[0:0]}),
.siovref(tmpSIOVREF__Debug0_net),
.interrupt({tmpINTERRUPT_0__Debug0_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug0_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Debug1_net;
wire [0:0] tmpFB_0__Debug1_net;
wire [0:0] tmpIO_0__Debug1_net;
wire [0:0] tmpINTERRUPT_0__Debug1_net;
electrical [0:0] tmpSIOVREF__Debug1_net;
cy_psoc3_pins_v1_10
#(.id("7f8ba9b1-e6f7-45c0-b01d-5f32ddc74dfe"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug1
(.oe(tmpOE__Debug1_net),
.y({1'b0}),
.fb({tmpFB_0__Debug1_net[0:0]}),
.io({tmpIO_0__Debug1_net[0:0]}),
.siovref(tmpSIOVREF__Debug1_net),
.interrupt({tmpINTERRUPT_0__Debug1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
SPI_Slave_v2_60_0 PiComs (
.mosi(Net_46),
.sclk(Net_47),
.ss(Net_48),
.miso(Net_49),
.clock(Net_50),
.tx_interrupt(Net_484),
.sdat(Net_72),
.rx_interrupt(Net_482),
.miso_oe(Net_74),
.reset(Net_55));
defparam PiComs.NumberOfDataBits = 8;
defparam PiComs.ShiftDir = 0;
cy_dma_v1_0
#(.drq_type(2'b00))
SpiXmitDma
(.drq(Net_484),
.trq(1'b0),
.nrq(Net_82));
wire [0:0] tmpOE__PiSPI_MOSI_net;
wire [0:0] tmpIO_0__PiSPI_MOSI_net;
wire [0:0] tmpINTERRUPT_0__PiSPI_MOSI_net;
electrical [0:0] tmpSIOVREF__PiSPI_MOSI_net;
cy_psoc3_pins_v1_10
#(.id("4c15b41e-e284-4978-99e7-5aaee19bd0ce"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
PiSPI_MOSI
(.oe(tmpOE__PiSPI_MOSI_net),
.y({1'b0}),
.fb({Net_46}),
.io({tmpIO_0__PiSPI_MOSI_net[0:0]}),
.siovref(tmpSIOVREF__PiSPI_MOSI_net),
.interrupt({tmpINTERRUPT_0__PiSPI_MOSI_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PiSPI_MOSI_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PiSPI_SCLK_net;
wire [0:0] tmpIO_0__PiSPI_SCLK_net;
wire [0:0] tmpINTERRUPT_0__PiSPI_SCLK_net;
electrical [0:0] tmpSIOVREF__PiSPI_SCLK_net;
cy_psoc3_pins_v1_10
#(.id("ba473d3a-49b3-4f06-8a28-0fcda8af6039"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
PiSPI_SCLK
(.oe(tmpOE__PiSPI_SCLK_net),
.y({1'b0}),
.fb({Net_47}),
.io({tmpIO_0__PiSPI_SCLK_net[0:0]}),
.siovref(tmpSIOVREF__PiSPI_SCLK_net),
.interrupt({tmpINTERRUPT_0__PiSPI_SCLK_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PiSPI_SCLK_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PiSPI_SS_net;
wire [0:0] tmpIO_0__PiSPI_SS_net;
wire [0:0] tmpINTERRUPT_0__PiSPI_SS_net;
electrical [0:0] tmpSIOVREF__PiSPI_SS_net;
cy_psoc3_pins_v1_10
#(.id("792a292b-6d33-426c-8811-0706c32bbec7"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
PiSPI_SS
(.oe(tmpOE__PiSPI_SS_net),
.y({1'b0}),
.fb({Net_48}),
.io({tmpIO_0__PiSPI_SS_net[0:0]}),
.siovref(tmpSIOVREF__PiSPI_SS_net),
.interrupt({tmpINTERRUPT_0__PiSPI_SS_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PiSPI_SS_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PiSPI_MISO_net;
wire [0:0] tmpFB_0__PiSPI_MISO_net;
wire [0:0] tmpIO_0__PiSPI_MISO_net;
wire [0:0] tmpINTERRUPT_0__PiSPI_MISO_net;
electrical [0:0] tmpSIOVREF__PiSPI_MISO_net;
cy_psoc3_pins_v1_10
#(.id("d8190f24-3d81-4c67-a2d7-769222f9f1c9"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
PiSPI_MISO
(.oe(tmpOE__PiSPI_MISO_net),
.y({Net_49}),
.fb({tmpFB_0__PiSPI_MISO_net[0:0]}),
.io({tmpIO_0__PiSPI_MISO_net[0:0]}),
.siovref(tmpSIOVREF__PiSPI_MISO_net),
.interrupt({tmpINTERRUPT_0__PiSPI_MISO_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PiSPI_MISO_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_clock_v1_0
#(.id("e0f7effe-c87d-4c77-863b-2d9a300816ea"),
.source_clock_id(""),
.divisor(0),
.period("62500000"),
.is_direct(0),
.is_digital(1))
PiSPI_CLK
(.clock_out(Net_50));
assign Net_55 = 1'h0;
wire [0:0] tmpOE__Debug2_net;
wire [0:0] tmpFB_0__Debug2_net;
wire [0:0] tmpIO_0__Debug2_net;
wire [0:0] tmpINTERRUPT_0__Debug2_net;
electrical [0:0] tmpSIOVREF__Debug2_net;
cy_psoc3_pins_v1_10
#(.id("552a2720-c5e1-40f0-bdcd-60f84ec0f68a"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug2
(.oe(tmpOE__Debug2_net),
.y({1'b0}),
.fb({tmpFB_0__Debug2_net[0:0]}),
.io({tmpIO_0__Debug2_net[0:0]}),
.siovref(tmpSIOVREF__Debug2_net),
.interrupt({tmpINTERRUPT_0__Debug2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Debug3_net;
wire [0:0] tmpFB_0__Debug3_net;
wire [0:0] tmpIO_0__Debug3_net;
wire [0:0] tmpINTERRUPT_0__Debug3_net;
electrical [0:0] tmpSIOVREF__Debug3_net;
cy_psoc3_pins_v1_10
#(.id("82a522ba-f5ef-4c0b-8a96-10c9f5905354"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug3
(.oe(tmpOE__Debug3_net),
.y({1'b0}),
.fb({tmpFB_0__Debug3_net[0:0]}),
.io({tmpIO_0__Debug3_net[0:0]}),
.siovref(tmpSIOVREF__Debug3_net),
.interrupt({tmpINTERRUPT_0__Debug3_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug3_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Debug4_net;
wire [0:0] tmpFB_0__Debug4_net;
wire [0:0] tmpIO_0__Debug4_net;
wire [0:0] tmpINTERRUPT_0__Debug4_net;
electrical [0:0] tmpSIOVREF__Debug4_net;
cy_psoc3_pins_v1_10
#(.id("bc4203ed-2165-4b05-b709-dd4cf62fe78f"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug4
(.oe(tmpOE__Debug4_net),
.y({1'b0}),
.fb({tmpFB_0__Debug4_net[0:0]}),
.io({tmpIO_0__Debug4_net[0:0]}),
.siovref(tmpSIOVREF__Debug4_net),
.interrupt({tmpINTERRUPT_0__Debug4_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug4_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Debug5_net;
wire [0:0] tmpFB_0__Debug5_net;
wire [0:0] tmpIO_0__Debug5_net;
wire [0:0] tmpINTERRUPT_0__Debug5_net;
electrical [0:0] tmpSIOVREF__Debug5_net;
cy_psoc3_pins_v1_10
#(.id("71d52255-be97-4fd2-90eb-2bb46ad1b34d"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug5
(.oe(tmpOE__Debug5_net),
.y({1'b0}),
.fb({tmpFB_0__Debug5_net[0:0]}),
.io({tmpIO_0__Debug5_net[0:0]}),
.siovref(tmpSIOVREF__Debug5_net),
.interrupt({tmpINTERRUPT_0__Debug5_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug5_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Debug6_net;
wire [0:0] tmpFB_0__Debug6_net;
wire [0:0] tmpIO_0__Debug6_net;
wire [0:0] tmpINTERRUPT_0__Debug6_net;
electrical [0:0] tmpSIOVREF__Debug6_net;
cy_psoc3_pins_v1_10
#(.id("7e2648e5-99fd-4fbb-a613-ee58cfe9ae1d"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug6
(.oe(tmpOE__Debug6_net),
.y({1'b0}),
.fb({tmpFB_0__Debug6_net[0:0]}),
.io({tmpIO_0__Debug6_net[0:0]}),
.siovref(tmpSIOVREF__Debug6_net),
.interrupt({tmpINTERRUPT_0__Debug6_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug6_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Debug7_net;
wire [0:0] tmpFB_0__Debug7_net;
wire [0:0] tmpIO_0__Debug7_net;
wire [0:0] tmpINTERRUPT_0__Debug7_net;
electrical [0:0] tmpSIOVREF__Debug7_net;
cy_psoc3_pins_v1_10
#(.id("56d2d614-d466-4668-8d81-444fbf026f5a"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Debug7
(.oe(tmpOE__Debug7_net),
.y({1'b0}),
.fb({tmpFB_0__Debug7_net[0:0]}),
.io({tmpIO_0__Debug7_net[0:0]}),
.siovref(tmpSIOVREF__Debug7_net),
.interrupt({tmpINTERRUPT_0__Debug7_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Debug7_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_dma_v1_0
#(.drq_type(2'b00))
SpiRcvDma
(.drq(Net_482),
.trq(1'b0),
.nrq(Net_88));
cy_isr_v1_0
#(.int_type(2'b10))
SpiXferDone
(.int_signal(Net_88));
// -- LUT RMotorControlLUT start --
if (1)
begin : RMotorControlLUT
reg [3:0] tmp__RMotorControlLUT_reg;
wire [2:0] tmp__RMotorControlLUT_ins;
assign tmp__RMotorControlLUT_ins = {Net_444,Net_447,Net_431};
always @(tmp__RMotorControlLUT_ins)
begin
case (tmp__RMotorControlLUT_ins)
3'b000 : tmp__RMotorControlLUT_reg = 4'b1000;
3'b001 : tmp__RMotorControlLUT_reg = 4'b1010;
3'b010 : tmp__RMotorControlLUT_reg = 4'b0001;
3'b011 : tmp__RMotorControlLUT_reg = 4'b0101;
3'b100 : tmp__RMotorControlLUT_reg = 4'b0110;
3'b101 : tmp__RMotorControlLUT_reg = 4'b0110;
3'b110 : tmp__RMotorControlLUT_reg = 4'b0110;
3'b111 : tmp__RMotorControlLUT_reg = 4'b0110;
endcase
end
assign {Net_474,Net_475,Net_150,Net_151} = tmp__RMotorControlLUT_reg;
end
// -- LUT RMotorControlLUT end --
// -- LUT LMotorControlLUT start --
if (1)
begin : LMotorControlLUT
reg [3:0] tmp__LMotorControlLUT_reg;
wire [2:0] tmp__LMotorControlLUT_ins;
assign tmp__LMotorControlLUT_ins = {Net_329,Net_328,Net_327};
always @(tmp__LMotorControlLUT_ins)
begin
case (tmp__LMotorControlLUT_ins)
3'b000 : tmp__LMotorControlLUT_reg = 4'b1000;
3'b001 : tmp__LMotorControlLUT_reg = 4'b1010;
3'b010 : tmp__LMotorControlLUT_reg = 4'b0001;
3'b011 : tmp__LMotorControlLUT_reg = 4'b0101;
3'b100 : tmp__LMotorControlLUT_reg = 4'b0110;
3'b101 : tmp__LMotorControlLUT_reg = 4'b0110;
3'b110 : tmp__LMotorControlLUT_reg = 4'b0110;
3'b111 : tmp__LMotorControlLUT_reg = 4'b0110;
endcase
end
assign {Net_470,Net_471,Net_234,Net_146} = tmp__LMotorControlLUT_reg;
end
// -- LUT LMotorControlLUT end --
wire [0:0] tmpOE__RDV2_net;
wire [0:0] tmpFB_0__RDV2_net;
wire [0:0] tmpIO_0__RDV2_net;
wire [0:0] tmpINTERRUPT_0__RDV2_net;
electrical [0:0] tmpSIOVREF__RDV2_net;
cy_psoc3_pins_v1_10
#(.id("eb6c27ab-fc51-4034-b315-213e9e3744bc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
RDV2
(.oe(tmpOE__RDV2_net),
.y({Net_151}),
.fb({tmpFB_0__RDV2_net[0:0]}),
.io({tmpIO_0__RDV2_net[0:0]}),
.siovref(tmpSIOVREF__RDV2_net),
.interrupt({tmpINTERRUPT_0__RDV2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RDV2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__RDG2_net;
wire [0:0] tmpFB_0__RDG2_net;
wire [0:0] tmpIO_0__RDG2_net;
wire [0:0] tmpINTERRUPT_0__RDG2_net;
electrical [0:0] tmpSIOVREF__RDG2_net;
cy_psoc3_pins_v1_10
#(.id("2dcbab4f-65ea-40f8-baad-ea98d42dc211"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
RDG2
(.oe(tmpOE__RDG2_net),
.y({Net_150}),
.fb({tmpFB_0__RDG2_net[0:0]}),
.io({tmpIO_0__RDG2_net[0:0]}),
.siovref(tmpSIOVREF__RDG2_net),
.interrupt({tmpINTERRUPT_0__RDG2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RDG2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__RDV1_net;
wire [0:0] tmpFB_0__RDV1_net;
wire [0:0] tmpIO_0__RDV1_net;
wire [0:0] tmpINTERRUPT_0__RDV1_net;
electrical [0:0] tmpSIOVREF__RDV1_net;
cy_psoc3_pins_v1_10
#(.id("d4b8a528-bfc4-48a3-9fd8-96314beacfb9"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
RDV1
(.oe(tmpOE__RDV1_net),
.y({Net_474}),
.fb({tmpFB_0__RDV1_net[0:0]}),
.io({tmpIO_0__RDV1_net[0:0]}),
.siovref(tmpSIOVREF__RDV1_net),
.interrupt({tmpINTERRUPT_0__RDV1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RDV1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_annotation_universal_v1_0 MotorPower (
.connect({
Net_109
})
);
defparam MotorPower.comp_name = "Power_v1_0";
defparam MotorPower.port_names = "T1";
defparam MotorPower.width = 1;
wire [0:0] tmpOE__RDG1_net;
wire [0:0] tmpFB_0__RDG1_net;
wire [0:0] tmpIO_0__RDG1_net;
wire [0:0] tmpINTERRUPT_0__RDG1_net;
electrical [0:0] tmpSIOVREF__RDG1_net;
cy_psoc3_pins_v1_10
#(.id("1e69f5d3-19e3-469b-92b1-f3a454c3faa9"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
RDG1
(.oe(tmpOE__RDG1_net),
.y({Net_475}),
.fb({tmpFB_0__RDG1_net[0:0]}),
.io({tmpIO_0__RDG1_net[0:0]}),
.siovref(tmpSIOVREF__RDG1_net),
.interrupt({tmpINTERRUPT_0__RDG1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RDG1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LDV2_net;
wire [0:0] tmpFB_0__LDV2_net;
wire [0:0] tmpIO_0__LDV2_net;
wire [0:0] tmpINTERRUPT_0__LDV2_net;
electrical [0:0] tmpSIOVREF__LDV2_net;
cy_psoc3_pins_v1_10
#(.id("59533667-4cfc-4544-baab-8b3bd52909f1"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
LDV2
(.oe(tmpOE__LDV2_net),
.y({Net_146}),
.fb({tmpFB_0__LDV2_net[0:0]}),
.io({tmpIO_0__LDV2_net[0:0]}),
.siovref(tmpSIOVREF__LDV2_net),
.interrupt({tmpINTERRUPT_0__LDV2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LDV2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LDV1_net;
wire [0:0] tmpFB_0__LDV1_net;
wire [0:0] tmpIO_0__LDV1_net;
wire [0:0] tmpINTERRUPT_0__LDV1_net;
electrical [0:0] tmpSIOVREF__LDV1_net;
cy_psoc3_pins_v1_10
#(.id("97923ef1-80ab-4780-9d4a-c8d7a967982d"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
LDV1
(.oe(tmpOE__LDV1_net),
.y({Net_470}),
.fb({tmpFB_0__LDV1_net[0:0]}),
.io({tmpIO_0__LDV1_net[0:0]}),
.siovref(tmpSIOVREF__LDV1_net),
.interrupt({tmpINTERRUPT_0__LDV1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LDV1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LDG2_net;
wire [0:0] tmpFB_0__LDG2_net;
wire [0:0] tmpIO_0__LDG2_net;
wire [0:0] tmpINTERRUPT_0__LDG2_net;
electrical [0:0] tmpSIOVREF__LDG2_net;
cy_psoc3_pins_v1_10
#(.id("287415af-de3f-4249-a327-fa46c98fd051"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
LDG2
(.oe(tmpOE__LDG2_net),
.y({Net_234}),
.fb({tmpFB_0__LDG2_net[0:0]}),
.io({tmpIO_0__LDG2_net[0:0]}),
.siovref(tmpSIOVREF__LDG2_net),
.interrupt({tmpINTERRUPT_0__LDG2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LDG2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LDG1_net;
wire [0:0] tmpFB_0__LDG1_net;
wire [0:0] tmpIO_0__LDG1_net;
wire [0:0] tmpINTERRUPT_0__LDG1_net;
electrical [0:0] tmpSIOVREF__LDG1_net;
cy_psoc3_pins_v1_10
#(.id("ad18c94c-1026-409d-8b2d-761861c9cd40"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
LDG1
(.oe(tmpOE__LDG1_net),
.y({Net_471}),
.fb({tmpFB_0__LDG1_net[0:0]}),
.io({tmpIO_0__LDG1_net[0:0]}),
.siovref(tmpSIOVREF__LDG1_net),
.interrupt({tmpINTERRUPT_0__LDG1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LDG1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_annotation_universal_v1_0 MotorGround (
.connect({
Net_128
})
);
defparam MotorGround.comp_name = "Gnd_v1_0";
defparam MotorGround.port_names = "T1";
defparam MotorGround.width = 1;
cy_annotation_universal_v1_0 Q_8 (
.connect({
Net_120,
Net_477,
Net_128
})
);
defparam Q_8.comp_name = "NFET_En_v1_0";
defparam Q_8.port_names = "D, G, S";
defparam Q_8.width = 3;
assign Net_399 = 1'h0;
cy_annotation_universal_v1_0 Q_7 (
.connect({
Net_119,
Net_252,
Net_128
})
);
defparam Q_7.comp_name = "NFET_En_v1_0";
defparam Q_7.port_names = "D, G, S";
defparam Q_7.width = 3;
cy_annotation_universal_v1_0 Q_6 (
.connect({
Net_120,
Net_476,
Net_109
})
);
defparam Q_6.comp_name = "PFET_En_v1_0";
defparam Q_6.port_names = "D, G, S";
defparam Q_6.width = 3;
cy_annotation_universal_v1_0 Q_5 (
.connect({
Net_119,
Net_253,
Net_109
})
);
defparam Q_5.comp_name = "PFET_En_v1_0";
defparam Q_5.port_names = "D, G, S";
defparam Q_5.width = 3;
assign Net_406 = 1'h0;
PWM_v3_0_1 LMotorPwm (
.reset(Net_399),
.clock(Net_418),
.tc(Net_401),
.pwm1(Net_402),
.pwm2(Net_403),
.interrupt(Net_404),
.capture(1'b0),
.kill(Net_406),
.enable(1'b1),
.trigger(1'b0),
.cmp_sel(1'b0),
.pwm(Net_327),
.ph1(Net_411),
.ph2(Net_412));
defparam LMotorPwm.Resolution = 16;
cy_annotation_universal_v1_0 RightDriveMotor (
.connect({
Net_119,
Net_120
})
);
defparam RightDriveMotor.comp_name = "Motor_v1_0";
defparam RightDriveMotor.port_names = "T1, T2";
defparam RightDriveMotor.width = 2;
cy_annotation_universal_v1_0 Q_4 (
.connect({
Net_115,
Net_473,
Net_128
})
);
defparam Q_4.comp_name = "NFET_En_v1_0";
defparam Q_4.port_names = "D, G, S";
defparam Q_4.width = 3;
cy_annotation_universal_v1_0 Q_3 (
.connect({
Net_112,
Net_135,
Net_128
})
);
defparam Q_3.comp_name = "NFET_En_v1_0";
defparam Q_3.port_names = "D, G, S";
defparam Q_3.width = 3;
cy_annotation_universal_v1_0 Q_2 (
.connect({
Net_115,
Net_472,
Net_109
})
);
defparam Q_2.comp_name = "PFET_En_v1_0";
defparam Q_2.port_names = "D, G, S";
defparam Q_2.width = 3;
cy_annotation_universal_v1_0 LeftDriveMotor (
.connect({
Net_112,
Net_115
})
);
defparam LeftDriveMotor.comp_name = "Motor_v1_0";
defparam LeftDriveMotor.port_names = "T1, T2";
defparam LeftDriveMotor.width = 2;
cy_annotation_universal_v1_0 Q_1 (
.connect({
Net_112,
Net_235,
Net_109
})
);
defparam Q_1.comp_name = "PFET_En_v1_0";
defparam Q_1.port_names = "D, G, S";
defparam Q_1.width = 3;
cy_clock_v1_0
#(.id("2307c094-7db2-4382-8854-4aa6ddf619ae"),
.source_clock_id(""),
.divisor(0),
.period("196078431.372549"),
.is_direct(0),
.is_digital(1))
MotorPwmClock
(.clock_out(Net_418));
PWM_v3_0_2 RMotorPwm (
.reset(Net_420),
.clock(Net_418),
.tc(Net_454),
.pwm1(Net_455),
.pwm2(Net_456),
.interrupt(Net_457),
.capture(1'b0),
.kill(Net_427),
.enable(1'b1),
.trigger(1'b0),
.cmp_sel(1'b0),
.pwm(Net_431),
.ph1(Net_462),
.ph2(Net_463));
defparam RMotorPwm.Resolution = 16;
assign Net_427 = 1'h0;
assign Net_420 = 1'h0;
CyControlReg_v1_70 MotorControlReg (
.control_1(Net_444),
.control_2(Net_328),
.control_3(Net_329),
.control_0(Net_447),
.control_4(Net_464),
.control_5(Net_465),
.control_6(Net_466),
.control_7(Net_467),
.clock(1'b0),
.reset(1'b0));
defparam MotorControlReg.Bit0Mode = 0;
defparam MotorControlReg.Bit1Mode = 0;
defparam MotorControlReg.Bit2Mode = 0;
defparam MotorControlReg.Bit3Mode = 0;
defparam MotorControlReg.Bit4Mode = 0;
defparam MotorControlReg.Bit5Mode = 0;
defparam MotorControlReg.Bit6Mode = 0;
defparam MotorControlReg.Bit7Mode = 0;
defparam MotorControlReg.BitValue = 0;
defparam MotorControlReg.BusDisplay = 0;
defparam MotorControlReg.ExtrReset = 0;
defparam MotorControlReg.NumOutputs = 4;
wire [0:0] tmpOE__SerDrv_485Sel_net;
wire [0:0] tmpFB_0__SerDrv_485Sel_net;
wire [0:0] tmpIO_0__SerDrv_485Sel_net;
wire [0:0] tmpINTERRUPT_0__SerDrv_485Sel_net;
electrical [0:0] tmpSIOVREF__SerDrv_485Sel_net;
cy_psoc3_pins_v1_10
#(.id("fd594dc3-3efb-4bd3-892c-7af0fc27189b"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
SerDrv_485Sel
(.oe(tmpOE__SerDrv_485Sel_net),
.y({Net_486}),
.fb({tmpFB_0__SerDrv_485Sel_net[0:0]}),
.io({tmpIO_0__SerDrv_485Sel_net[0:0]}),
.siovref(tmpSIOVREF__SerDrv_485Sel_net),
.interrupt({tmpINTERRUPT_0__SerDrv_485Sel_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SerDrv_485Sel_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
assign Net_486 = 1'h0;
wire [0:0] tmpOE__SerDrv_Enable_net;
wire [0:0] tmpFB_0__SerDrv_Enable_net;
wire [0:0] tmpIO_0__SerDrv_Enable_net;
wire [0:0] tmpINTERRUPT_0__SerDrv_Enable_net;
electrical [0:0] tmpSIOVREF__SerDrv_Enable_net;
cy_psoc3_pins_v1_10
#(.id("fccf07ce-94e8-4f8a-b8b3-0a687ca58a90"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
SerDrv_Enable
(.oe(tmpOE__SerDrv_Enable_net),
.y({Net_488}),
.fb({tmpFB_0__SerDrv_Enable_net[0:0]}),
.io({tmpIO_0__SerDrv_Enable_net[0:0]}),
.siovref(tmpSIOVREF__SerDrv_Enable_net),
.interrupt({tmpINTERRUPT_0__SerDrv_Enable_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SerDrv_Enable_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
assign Net_488 = 1'h1;
wire [0:0] tmpOE__SerDrv_RA_net;
wire [0:0] tmpIO_0__SerDrv_RA_net;
wire [0:0] tmpINTERRUPT_0__SerDrv_RA_net;
electrical [0:0] tmpSIOVREF__SerDrv_RA_net;
cy_psoc3_pins_v1_10
#(.id("19a0a241-daf3-4284-bddc-bbf25efc36c5"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
SerDrv_RA
(.oe(tmpOE__SerDrv_RA_net),
.y({1'b0}),
.fb({Net_506}),
.io({tmpIO_0__SerDrv_RA_net[0:0]}),
.siovref(tmpSIOVREF__SerDrv_RA_net),
.interrupt({tmpINTERRUPT_0__SerDrv_RA_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SerDrv_RA_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__SerDrv_RB_net;
wire [0:0] tmpIO_0__SerDrv_RB_net;
wire [0:0] tmpINTERRUPT_0__SerDrv_RB_net;
electrical [0:0] tmpSIOVREF__SerDrv_RB_net;
cy_psoc3_pins_v1_10
#(.id("9081c06c-a743-485f-b7ff-16e38257cb73"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
SerDrv_RB
(.oe(tmpOE__SerDrv_RB_net),
.y({1'b0}),
.fb({Net_508}),
.io({tmpIO_0__SerDrv_RB_net[0:0]}),
.siovref(tmpSIOVREF__SerDrv_RB_net),
.interrupt({tmpINTERRUPT_0__SerDrv_RB_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SerDrv_RB_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__SerDrv_DY_net;
wire [0:0] tmpFB_0__SerDrv_DY_net;
wire [0:0] tmpIO_0__SerDrv_DY_net;
wire [0:0] tmpINTERRUPT_0__SerDrv_DY_net;
electrical [0:0] tmpSIOVREF__SerDrv_DY_net;
cy_psoc3_pins_v1_10
#(.id("50c223ef-75a8-4158-80c6-a7fb78dfb997"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
SerDrv_DY
(.oe(tmpOE__SerDrv_DY_net),
.y({Net_509}),
.fb({tmpFB_0__SerDrv_DY_net[0:0]}),
.io({tmpIO_0__SerDrv_DY_net[0:0]}),
.siovref(tmpSIOVREF__SerDrv_DY_net),
.interrupt({tmpINTERRUPT_0__SerDrv_DY_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SerDrv_DY_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__SerDrv_DZ_net;
wire [0:0] tmpFB_0__SerDrv_DZ_net;
wire [0:0] tmpIO_0__SerDrv_DZ_net;
wire [0:0] tmpINTERRUPT_0__SerDrv_DZ_net;
electrical [0:0] tmpSIOVREF__SerDrv_DZ_net;
cy_psoc3_pins_v1_10
#(.id("900f815f-ee97-4b34-a221-6822ddb4f76f"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
SerDrv_DZ
(.oe(tmpOE__SerDrv_DZ_net),
.y({Net_510}),
.fb({tmpFB_0__SerDrv_DZ_net[0:0]}),
.io({tmpIO_0__SerDrv_DZ_net[0:0]}),
.siovref(tmpSIOVREF__SerDrv_DZ_net),
.interrupt({tmpINTERRUPT_0__SerDrv_DZ_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SerDrv_DZ_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PiUART_RXD_net;
wire [0:0] tmpFB_0__PiUART_RXD_net;
wire [0:0] tmpIO_0__PiUART_RXD_net;
wire [0:0] tmpINTERRUPT_0__PiUART_RXD_net;
electrical [0:0] tmpSIOVREF__PiUART_RXD_net;
cy_psoc3_pins_v1_10
#(.id("f1ea3e85-bd6b-4d5a-bfa3-3f153e6d198d"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
PiUART_RXD
(.oe(tmpOE__PiUART_RXD_net),
.y({Net_506}),
.fb({tmpFB_0__PiUART_RXD_net[0:0]}),
.io({tmpIO_0__PiUART_RXD_net[0:0]}),
.siovref(tmpSIOVREF__PiUART_RXD_net),
.interrupt({tmpINTERRUPT_0__PiUART_RXD_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PiUART_RXD_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PiUART_TXD_net;
wire [0:0] tmpIO_0__PiUART_TXD_net;
wire [0:0] tmpINTERRUPT_0__PiUART_TXD_net;
electrical [0:0] tmpSIOVREF__PiUART_TXD_net;
cy_psoc3_pins_v1_10
#(.id("1f75df3a-17d6-4a7e-9bcd-8c583ccfd06e"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
PiUART_TXD
(.oe(tmpOE__PiUART_TXD_net),
.y({1'b0}),
.fb({Net_509}),
.io({tmpIO_0__PiUART_TXD_net[0:0]}),
.siovref(tmpSIOVREF__PiUART_TXD_net),
.interrupt({tmpINTERRUPT_0__PiUART_TXD_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PiUART_TXD_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
assign Net_510 = 1'h0;
endmodule
|
// USED ONLY TO SELECT PL BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 4;
parameter WB = 4;
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
genvar i,j;
wire [WA*WB-1:0] selected;
generate
for (i=0; i<WA; i=i+1) begin:ol
for (j=0; j<WB; j=j+1) begin:il
assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
end
end
endgenerate
assign selected_bit=|selected;
endmodule // unary_select_pair
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:39 05/20/2014
// Design Name: program_counter
// Module Name: C:/Users/Deus/Windows Sync/Xilinx Workspace/Single/test_pc.v
// Project Name: Single
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: program_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_pc;
// Inputs
reg clk;
reg [31:0] pc_next;
// Outputs
wire [31:0] pc_now;
// Instantiate the Unit Under Test (UUT)
program_counter uut (
.clk(clk),
.pc_next(pc_next),
.pc_now(pc_now)
);
initial begin
// Initialize Inputs
clk = 0;
pc_next = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always @* pc_next <= pc_now + 4;
always #10 clk = ~clk;
endmodule
|
module top;
reg pass;
integer val;
initial begin
pass = 1'b1;
// Check ARS in a fully signed context.
// All operands are signed.
val = -1;
val = 7'sd10 + (val >>> 1);
if (val !== 9) begin
$display("Failed ARS in signed context, got %d", val);
pass = 1'b0;
end
// Check ARS in a cast signed context.
// This is fully signed as well because of the cast.
val = -1;
val = $signed(7'd10) + (val >>> 1);
if (val !== 9) begin
$display("Failed ARS in cast signed context, got %d", val);
pass = 1'b0;
end
// Check ARS in a self determined context.
// The system function is a primary and should create a self-determined
// context for the ARS. The addition is then done in an unsigned
// context, but this should still give the correct result.
//
// The bug is that Icarus is not sign padding the ARS since the
// addition is casting it to be unsigned. It should only be able to
// cast the sign of the result not the actual ARS! This casting is
// happening in suppress_binary_operand_sign_if_needed() defined in
// elab_expr.cc. It looks like $signed and $unsigned need some way
// to protect their argument self-determined context.
val = -1;
val = 7'd10 + $signed(val >>> 1);
if (val !== 9) begin
$display("Failed ARS in $signed context, got %d", val);
pass = 1'b0;
end
// Check ARS in a different self determined context.
// See comments above for $signed.
val = -1;
val = 7'd10 + $unsigned(val >>> 1);
if (val !== 9) begin
$display("Failed ARS in $unsigned context, got %d", val);
pass = 1'b0;
end
// Check ARS in a different self determined context.
val = -1;
val = 7'd10 + {val >>> 1};
if (val !== 9) begin
$display("Failed ARS in a concatenation context, got %d", val);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports.
//
//===----------------------------------------------------------------------===//
module acl_mlab_fifo (
clock,
resetn,
data_in,
data_out,
valid_in,
valid_out,
stall_in,
stall_out,
usedw,
empty,
full,
almost_full);
function integer my_local_log;
input [31:0] value;
for (my_local_log=0; value>0; my_local_log=my_local_log+1)
value = value>>1;
endfunction
parameter DATA_WIDTH = 32;
parameter DEPTH = 256;
parameter NUM_BITS_USED_WORDS = DEPTH == 1 ? 1 : my_local_log(DEPTH-1);
parameter ALMOST_FULL_VALUE = 0;
input clock, stall_in, valid_in, resetn;
output stall_out, valid_out;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output [NUM_BITS_USED_WORDS-1:0] usedw;
output empty, full, almost_full;
// add a register stage prior to the acl_fifo.
//reg [DATA_WIDTH-1:0] data_input /* synthesis preserve */;
//reg valid_input /* synthesis preserve */;
//always@(posedge clock or negedge resetn)
//begin
// if (~resetn)
// begin
// data_input <= {DATA_WIDTH{1'bx}};
// valid_input <= 1'b0;
// end
// else if (~valid_input | ~full)
// begin
// valid_input <= valid_in;
// data_input <= data_in;
// end
//end
scfifo scfifo_component (
.clock (clock),
.data (data_in),
.rdreq ((~stall_in) & (~empty)),
.sclr (),
.wrreq (valid_in & (~full)),
.empty (empty),
.full (full),
.q (data_out),
.aclr (~resetn),
.almost_empty (),
.almost_full (almost_full),
.usedw (usedw));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = DEPTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = NUM_BITS_USED_WORDS,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.almost_full_value = ALMOST_FULL_VALUE;
assign stall_out = full;
assign valid_out = ~empty;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:16:35 05/04/2014
// Design Name: CPU_top
// Module Name: D:/single_CPU/test.v
// Project Name: single_CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CPU_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg stp;
reg rst;
reg clk;
reg [1:0] dptype;
reg [4:0] regselect;
// Outputs
wire exec;
wire [5:0] initype;
wire [3:0] node;
wire [7:0] segment;
// Instantiate the Unit Under Test (UUT)
CPU_top uut (
.stp(stp),
.o_ins(o_ins),
.o_pc(o_pc),
.regselect(regselect),
.dpdata(dpdata)
);
initial begin
// Initialize Inputs
stp = 0;
regselect=5;
rst = 0;
clk = 0;
dptype = 0;
// Wait 100 ns for global reset to finish
forever begin #10; stp=~stp; end
// Add stimulus here
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:35:45 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
CountGenerator
:Function
For generating counts from xilinx.
Give the first output after 0 cycle while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-31
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module CountGenerator(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data,
count_x,
count_y);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Count for x.
*/
output reg[im_width_bits - 1 : 0] count_x;
/*
::description
Count for y.
*/
output reg[im_width_bits - 1 : 0] count_y;
assign out_ready = in_enable;
assign out_data = out_ready ? in_data : 0;
generate
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
count_x <= 0;
else if(count_x == im_width - 1)
count_x <= 0;
else
count_x <= count_x + 1;
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
count_y <= 0;
else if(count_x == im_width - 1 && count_y == im_height - 1)
count_y <= 0;
else if(count_x == im_width - 1)
count_y <= count_y + 1;
else
count_y <= count_y;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
count_x <= 0;
else if(count_x == im_width - 1)
count_x <= 0;
else
count_x <= count_x + 1;
end
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
count_y <= 0;
else if(count_x == im_width - 1 && count_y == im_height - 1)
count_y <= 0;
else if(count_x == im_width - 1)
count_y <= count_y + 1;
else
count_y <= count_y;
end
end
endgenerate
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_FUNCTIONAL_PP_V |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : chipscope.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 07 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR2/3 SDRAM
//Purpose : Chipscope cores declarations used if debug option is
// enabled in MIG when generating design. These are
// empty declarations to allow compilation to pass both in
// simulation and synthesis. The proper .ngc files must be
// referenced during the actual ISE build.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module icon5
(
inout [35:0] CONTROL0,
inout [35:0] CONTROL1,
inout [35:0] CONTROL2,
inout [35:0] CONTROL3,
inout [35:0] CONTROL4
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule // icon
module ila384_8
(
input CLK,
input [383:0] DATA,
input [7:0] TRIG0,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
module vio_async_in256
(
input [255:0] ASYNC_IN,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
module vio_sync_out32
(
output [31:0] SYNC_OUT,
input CLK,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c_split_1 <= 16'h0;
c_split_2 <= 16'h0;
c_split_3 <= 16'h0;
c_split_4 <= 0;
c_split_5 <= 0;
// End of automatics
end
else begin
c_split_1 <= m_din;
c_split_2 <= c_split_1;
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
if (cyc==1) begin
c_split_4 <= 16'h4;
c_split_5 <= 16'h5;
end
else begin
c_split_4 <= c_split_3;
c_split_5 <= c_split_4;
end
end
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
d_split_1 <= 16'h0;
d_split_2 <= 16'h0;
// End of automatics
end
else begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
end
// Not OK
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
// End of automatics
end
else begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
e_split_1 = 16'h0;
e_split_2 = 16'h0;
// End of automatics
end
else begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_split_1 = 16'h0;
f_split_2 = 16'h0;
// End of automatics
end
else begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
m_din <= 16'he44e;
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
end
if (cyc==8) begin
m_din <= 16'he55e;
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
(** * MoreStlc: More on the Simply Typed Lambda-Calculus *)
Require Export Stlc.
(* ###################################################################### *)
(** * Simple Extensions to STLC *)
(** The simply typed lambda-calculus has enough structure to make its
theoretical properties interesting, but it is not much of a
programming language. In this chapter, we begin to close the gap
with real-world languages by introducing a number of familiar
features that have straightforward treatments at the level of
typing. *)
(** ** Numbers *)
(** Adding types, constants, and primitive operations for numbers is
easy -- just a matter of combining the [Types] and [Stlc]
chapters. *)
(** ** [let]-bindings *)
(** When writing a complex expression, it is often useful to give
names to some of its subexpressions: this avoids repetition and
often increases readability. Most languages provide one or more
ways of doing this. In OCaml (and Coq), for example, we can write
[let x=t1 in t2] to mean ``evaluate the expression [t1] and bind
the name [x] to the resulting value while evaluating [t2].''
Our [let]-binder follows OCaml's in choosing a call-by-value
evaluation order, where the [let]-bound term must be fully
evaluated before evaluation of the [let]-body can begin. The
typing rule [T_Let] tells us that the type of a [let] can be
calculated by calculating the type of the [let]-bound term,
extending the context with a binding with this type, and in this
enriched context calculating the type of the body, which is then
the type of the whole [let] expression.
At this point in the course, it's probably easier simply to look
at the rules defining this new feature as to wade through a lot of
english text conveying the same information. Here they are: *)
(** Syntax:
<<
t ::= Terms
| ... (other terms same as before)
| let x=t in t let-binding
>>
*)
(**
Reduction:
t1 ==> t1'
---------------------------------- (ST_Let1)
let x=t1 in t2 ==> let x=t1' in t2
---------------------------- (ST_LetValue)
let x=v1 in t2 ==> [x:=v1]t2
Typing:
Gamma |- t1 : T1 Gamma , x:T1 |- t2 : T2
-------------------------------------------- (T_Let)
Gamma |- let x=t1 in t2 : T2
*)
(** ** Pairs *)
(** Our functional programming examples in Coq have made
frequent use of _pairs_ of values. The type of such pairs is
called a _product type_.
The formalization of pairs is almost too simple to be worth
discussing. However, let's look briefly at the various parts of
the definition to emphasize the common pattern. *)
(** In Coq, the primitive way of extracting the components of a pair
is _pattern matching_. An alternative style is to take [fst] and
[snd] -- the first- and second-projection operators -- as
primitives. Just for fun, let's do our products this way. For
example, here's how we'd write a function that takes a pair of
numbers and returns the pair of their sum and difference:
<<
\x:Nat*Nat.
let sum = x.fst + x.snd in
let diff = x.fst - x.snd in
(sum,diff)
>>
*)
(** Adding pairs to the simply typed lambda-calculus, then, involves
adding two new forms of term -- pairing, written [(t1,t2)], and
projection, written [t.fst] for the first projection from [t] and
[t.snd] for the second projection -- plus one new type constructor,
[T1*T2], called the _product_ of [T1] and [T2]. *)
(** Syntax:
<<
t ::= Terms
| ...
| (t,t) pair
| t.fst first projection
| t.snd second projection
v ::= Values
| ...
| (v,v) pair value
T ::= Types
| ...
| T * T product type
>>
*)
(** For evaluation, we need several new rules specifying how pairs and
projection behave.
t1 ==> t1'
-------------------- (ST_Pair1)
(t1,t2) ==> (t1',t2)
t2 ==> t2'
-------------------- (ST_Pair2)
(v1,t2) ==> (v1,t2')
t1 ==> t1'
------------------ (ST_Fst1)
t1.fst ==> t1'.fst
------------------ (ST_FstPair)
(v1,v2).fst ==> v1
t1 ==> t1'
------------------ (ST_Snd1)
t1.snd ==> t1'.snd
------------------ (ST_SndPair)
(v1,v2).snd ==> v2
*)
(**
Rules [ST_FstPair] and [ST_SndPair] specify that, when a fully
evaluated pair meets a first or second projection, the result is
the appropriate component. The congruence rules [ST_Fst1] and
[ST_Snd1] allow reduction to proceed under projections, when the
term being projected from has not yet been fully evaluated.
[ST_Pair1] and [ST_Pair2] evaluate the parts of pairs: first the
left part, and then -- when a value appears on the left -- the right
part. The ordering arising from the use of the metavariables [v]
and [t] in these rules enforces a left-to-right evaluation
strategy for pairs. (Note the implicit convention that
metavariables like [v] and [v1] can only denote values.) We've
also added a clause to the definition of values, above, specifying
that [(v1,v2)] is a value. The fact that the components of a pair
value must themselves be values ensures that a pair passed as an
argument to a function will be fully evaluated before the function
body starts executing. *)
(** The typing rules for pairs and projections are straightforward.
Gamma |- t1 : T1 Gamma |- t2 : T2
--------------------------------------- (T_Pair)
Gamma |- (t1,t2) : T1*T2
Gamma |- t1 : T11*T12
--------------------- (T_Fst)
Gamma |- t1.fst : T11
Gamma |- t1 : T11*T12
--------------------- (T_Snd)
Gamma |- t1.snd : T12
*)
(** The rule [T_Pair] says that [(t1,t2)] has type [T1*T2] if [t1] has
type [T1] and [t2] has type [T2]. Conversely, the rules [T_Fst]
and [T_Snd] tell us that, if [t1] has a product type
[T11*T12] (i.e., if it will evaluate to a pair), then the types of
the projections from this pair are [T11] and [T12]. *)
(** ** Unit *)
(** Another handy base type, found especially in languages in
the ML family, is the singleton type [Unit]. *)
(** It has a single element -- the term constant [unit] (with a small
[u]) -- and a typing rule making [unit] an element of [Unit]. We
also add [unit] to the set of possible result values of
computations -- indeed, [unit] is the _only_ possible result of
evaluating an expression of type [Unit]. *)
(** Syntax:
<<
t ::= Terms
| ...
| unit unit value
v ::= Values
| ...
| unit unit
T ::= Types
| ...
| Unit Unit type
>>
Typing:
-------------------- (T_Unit)
Gamma |- unit : Unit
*)
(** It may seem a little strange to bother defining a type that
has just one element -- after all, wouldn't every computation
living in such a type be trivial?
This is a fair question, and indeed in the STLC the [Unit] type is
not especially critical (though we'll see two uses for it below).
Where [Unit] really comes in handy is in richer languages with
various sorts of _side effects_ -- e.g., assignment statements
that mutate variables or pointers, exceptions and other sorts of
nonlocal control structures, etc. In such languages, it is
convenient to have a type for the (trivial) result of an
expression that is evaluated only for its effect. *)
(** ** Sums *)
(** Many programs need to deal with values that can take two distinct
forms. For example, we might identify employees in an accounting
application using using _either_ their name _or_ their id number.
A search function might return _either_ a matching value _or_ an
error code.
These are specific examples of a binary _sum type_,
which describes a set of values drawn from exactly two given types, e.g.
<<
Nat + Bool
>>
*)
(** We create elements of these types by _tagging_ elements of
the component types. For example, if [n] is a [Nat] then [inl v]
is an element of [Nat+Bool]; similarly, if [b] is a [Bool] then
[inr b] is a [Nat+Bool]. The names of the tags [inl] and [inr]
arise from thinking of them as functions
<<
inl : Nat -> Nat + Bool
inr : Bool -> Nat + Bool
>>
that "inject" elements of [Nat] or [Bool] into the left and right
components of the sum type [Nat+Bool]. (But note that we don't
actually treat them as functions in the way we formalize them:
[inl] and [inr] are keywords, and [inl t] and [inr t] are primitive
syntactic forms, not function applications. This allows us to give
them their own special typing rules.) *)
(** In general, the elements of a type [T1 + T2] consist of the
elements of [T1] tagged with the token [inl], plus the elements of
[T2] tagged with [inr]. *)
(** One important usage of sums is signaling errors:
<<
div : Nat -> Nat -> (Nat + Unit) =
div =
\x:Nat. \y:Nat.
if iszero y then
inr unit
else
inl ...
>>
The type [Nat + Unit] above is in fact isomorphic to [option nat]
in Coq, and we've already seen how to signal errors with options. *)
(** To _use_ elements of sum types, we introduce a [case]
construct (a very simplified form of Coq's [match]) to destruct
them. For example, the following procedure converts a [Nat+Bool]
into a [Nat]: *)
(**
<<
getNat =
\x:Nat+Bool.
case x of
inl n => n
| inr b => if b then 1 else 0
>>
*)
(** More formally... *)
(** Syntax:
<<
t ::= Terms
| ...
| inl T t tagging (left)
| inr T t tagging (right)
| case t of case
inl x => t
| inr x => t
v ::= Values
| ...
| inl T v tagged value (left)
| inr T v tagged value (right)
T ::= Types
| ...
| T + T sum type
>>
*)
(** Evaluation:
t1 ==> t1'
---------------------- (ST_Inl)
inl T t1 ==> inl T t1'
t1 ==> t1'
---------------------- (ST_Inr)
inr T t1 ==> inr T t1'
t0 ==> t0'
------------------------------------------- (ST_Case)
case t0 of inl x1 => t1 | inr x2 => t2 ==>
case t0' of inl x1 => t1 | inr x2 => t2
---------------------------------------------- (ST_CaseInl)
case (inl T v0) of inl x1 => t1 | inr x2 => t2
==> [x1:=v0]t1
---------------------------------------------- (ST_CaseInr)
case (inr T v0) of inl x1 => t1 | inr x2 => t2
==> [x2:=v0]t2
*)
(** Typing:
Gamma |- t1 : T1
---------------------------- (T_Inl)
Gamma |- inl T2 t1 : T1 + T2
Gamma |- t1 : T2
---------------------------- (T_Inr)
Gamma |- inr T1 t1 : T1 + T2
Gamma |- t0 : T1+T2
Gamma , x1:T1 |- t1 : T
Gamma , x2:T2 |- t2 : T
--------------------------------------------------- (T_Case)
Gamma |- case t0 of inl x1 => t1 | inr x2 => t2 : T
We use the type annotation in [inl] and [inr] to make the typing
simpler, similarly to what we did for functions. *)
(** Without this extra
information, the typing rule [T_Inl], for example, would have to
say that, once we have shown that [t1] is an element of type [T1],
we can derive that [inl t1] is an element of [T1 + T2] for _any_
type T2. For example, we could derive both [inl 5 : Nat + Nat]
and [inl 5 : Nat + Bool] (and infinitely many other types).
This failure of uniqueness of types would mean that we cannot
build a typechecking algorithm simply by "reading the rules from
bottom to top" as we could for all the other features seen so far.
There are various ways to deal with this difficulty. One simple
one -- which we've adopted here -- forces the programmer to
explicitly annotate the "other side" of a sum type when performing
an injection. This is rather heavyweight for programmers (and so
real languages adopt other solutions), but it is easy to
understand and formalize. *)
(** ** Lists *)
(** The typing features we have seen can be classified into _base
types_ like [Bool], and _type constructors_ like [->] and [*] that
build new types from old ones. Another useful type constructor is
[List]. For every type [T], the type [List T] describes
finite-length lists whose elements are drawn from [T].
In principle, we could encode lists using pairs, sums and
_recursive_ types. But giving semantics to recursive types is
non-trivial. Instead, we'll just discuss the special case of lists
directly.
Below we give the syntax, semantics, and typing rules for lists.
Except for the fact that explicit type annotations are mandatory
on [nil] and cannot appear on [cons], these lists are essentially
identical to those we built in Coq. We use [lcase] to destruct
lists, to avoid dealing with questions like "what is the [head] of
the empty list?" *)
(** For example, here is a function that calculates the sum of
the first two elements of a list of numbers:
<<
\x:List Nat.
lcase x of nil -> 0
| a::x' -> lcase x' of nil -> a
| b::x'' -> a+b
>>
*)
(**
Syntax:
<<
t ::= Terms
| ...
| nil T
| cons t t
| lcase t of nil -> t | x::x -> t
v ::= Values
| ...
| nil T nil value
| cons v v cons value
T ::= Types
| ...
| List T list of Ts
>>
*)
(** Reduction:
t1 ==> t1'
-------------------------- (ST_Cons1)
cons t1 t2 ==> cons t1' t2
t2 ==> t2'
-------------------------- (ST_Cons2)
cons v1 t2 ==> cons v1 t2'
t1 ==> t1'
---------------------------------------- (ST_Lcase1)
(lcase t1 of nil -> t2 | xh::xt -> t3) ==>
(lcase t1' of nil -> t2 | xh::xt -> t3)
----------------------------------------- (ST_LcaseNil)
(lcase nil T of nil -> t2 | xh::xt -> t3)
==> t2
----------------------------------------------- (ST_LcaseCons)
(lcase (cons vh vt) of nil -> t2 | xh::xt -> t3)
==> [xh:=vh,xt:=vt]t3
*)
(** Typing:
----------------------- (T_Nil)
Gamma |- nil T : List T
Gamma |- t1 : T Gamma |- t2 : List T
----------------------------------------- (T_Cons)
Gamma |- cons t1 t2: List T
Gamma |- t1 : List T1
Gamma |- t2 : T
Gamma , h:T1, t:List T1 |- t3 : T
------------------------------------------------- (T_Lcase)
Gamma |- (lcase t1 of nil -> t2 | h::t -> t3) : T
*)
(** ** General Recursion *)
(** Another facility found in most programming languages (including
Coq) is the ability to define recursive functions. For example,
we might like to be able to define the factorial function like
this:
<<
fact = \x:Nat.
if x=0 then 1 else x * (fact (pred x)))
>>
But this would require quite a bit of work to formalize: we'd have
to introduce a notion of "function definitions" and carry around an
"environment" of such definitions in the definition of the [step]
relation. *)
(** Here is another way that is straightforward to formalize: instead
of writing recursive definitions where the right-hand side can
contain the identifier being defined, we can define a _fixed-point
operator_ that performs the "unfolding" of the recursive definition
in the right-hand side lazily during reduction.
<<
fact =
fix
(\f:Nat->Nat.
\x:Nat.
if x=0 then 1 else x * (f (pred x)))
>>
*)
(** The intuition is that the higher-order function [f] passed
to [fix] is a _generator_ for the [fact] function: if [fact] is
applied to a function that approximates the desired behavior of
[fact] up to some number [n] (that is, a function that returns
correct results on inputs less than or equal to [n]), then it
returns a better approximation to [fact] -- a function that returns
correct results for inputs up to [n+1]. Applying [fix] to this
generator returns its _fixed point_ -- a function that gives the
desired behavior for all inputs [n].
(The term "fixed point" has exactly the same sense as in ordinary
mathematics, where a fixed point of a function [f] is an input [x]
such that [f(x) = x]. Here, a fixed point of a function [F] of
type (say) [(Nat->Nat)->(Nat->Nat)] is a function [f] such that [F
f] is behaviorally equivalent to [f].) *)
(** Syntax:
<<
t ::= Terms
| ...
| fix t fixed-point operator
>>
Reduction:
t1 ==> t1'
------------------ (ST_Fix1)
fix t1 ==> fix t1'
F = \xf:T1.t2
----------------------- (ST_FixAbs)
fix F ==> [xf:=fix F]t2
Typing:
Gamma |- t1 : T1->T1
-------------------- (T_Fix)
Gamma |- fix t1 : T1
*)
(** Let's see how [ST_FixAbs] works by reducing [fact 3 = fix F 3],
where [F = (\f. \x. if x=0 then 1 else x * (f (pred x)))] (we are
omitting type annotations for brevity here).
<<
fix F 3
>>
[==>] [ST_FixAbs]
<<
(\x. if x=0 then 1 else x * (fix F (pred x))) 3
>>
[==>] [ST_AppAbs]
<<
if 3=0 then 1 else 3 * (fix F (pred 3))
>>
[==>] [ST_If0_Nonzero]
<<
3 * (fix F (pred 3))
>>
[==>] [ST_FixAbs + ST_Mult2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 3))
>>
[==>] [ST_PredNat + ST_Mult2 + ST_App2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 2)
>>
[==>] [ST_AppAbs + ST_Mult2]
<<
3 * (if 2=0 then 1 else 2 * (fix F (pred 2)))
>>
[==>] [ST_If0_Nonzero + ST_Mult2]
<<
3 * (2 * (fix F (pred 2)))
>>
[==>] [ST_FixAbs + 2 x ST_Mult2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 2)))
>>
[==>] [ST_PredNat + 2 x ST_Mult2 + ST_App2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 1))
>>
[==>] [ST_AppAbs + 2 x ST_Mult2]
<<
3 * (2 * (if 1=0 then 1 else 1 * (fix F (pred 1))))
>>
[==>] [ST_If0_Nonzero + 2 x ST_Mult2]
<<
3 * (2 * (1 * (fix F (pred 1))))
>>
[==>] [ST_FixAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 1))))
>>
[==>] [ST_PredNat + 3 x ST_Mult2 + ST_App2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 0)))
>>
[==>] [ST_AppAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * (if 0=0 then 1 else 0 * (fix F (pred 0)))))
>>
[==>] [ST_If0Zero + 3 x ST_Mult2]
<<
3 * (2 * (1 * 1))
>>
[==>] [ST_MultNats + 2 x ST_Mult2]
<<
3 * (2 * 1)
>>
[==>] [ST_MultNats + ST_Mult2]
<<
3 * 2
>>
[==>] [ST_MultNats]
<<
6
>>
*)
(** **** Exercise: 1 star (halve_fix) *)
(** Translate this informal recursive definition into one using [fix]:
<<
halve =
\x:Nat.
if x=0 then 0
else if (pred x)=0 then 0
else 1 + (halve (pred (pred x))))
>>
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star (fact_steps) *)
(** Write down the sequence of steps that the term [fact 1] goes
through to reduce to a normal form (assuming the usual reduction
rules for arithmetic operations).
(* FILL IN HERE *)
[]
*)
(** The ability to form the fixed point of a function of type [T->T]
for any [T] has some surprising consequences. In particular, it
implies that _every_ type is inhabited by some term. To see this,
observe that, for every type [T], we can define the term
fix (\x:T.x)
By [T_Fix] and [T_Abs], this term has type [T]. By [ST_FixAbs]
it reduces to itself, over and over again. Thus it is an
_undefined element_ of [T].
More usefully, here's an example using [fix] to define a
two-argument recursive function:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
And finally, here is an example where [fix] is used to define a
_pair_ of recursive functions (illustrating the fact that the type
[T1] in the rule [T_Fix] need not be a function type):
<<
evenodd =
fix
(\eo: (Nat->Bool * Nat->Bool).
let e = \n:Nat. if n=0 then true else eo.snd (pred n) in
let o = \n:Nat. if n=0 then false else eo.fst (pred n) in
(e,o))
even = evenodd.fst
odd = evenodd.snd
>>
*)
(* ###################################################################### *)
(** ** Records *)
(** As a final example of a basic extension of the STLC, let's
look briefly at how to define _records_ and their types.
Intuitively, records can be obtained from pairs by two kinds of
generalization: they are n-ary products (rather than just binary)
and their fields are accessed by _label_ (rather than position).
Conceptually, this extension is a straightforward generalization
of pairs and product types, but notationally it becomes a little
heavier; for this reason, we postpone its formal treatment to a
separate chapter ([Records]). *)
(** Records are not included in the extended exercise below, but
they will be useful to motivate the [Sub] chapter. *)
(** Syntax:
<<
t ::= Terms
| ...
| {i1=t1, ..., in=tn} record
| t.i projection
v ::= Values
| ...
| {i1=v1, ..., in=vn} record value
T ::= Types
| ...
| {i1:T1, ..., in:Tn} record type
>>
Intuitively, the generalization is pretty obvious. But it's worth
noticing that what we've actually written is rather informal: in
particular, we've written "[...]" in several places to mean "any
number of these," and we've omitted explicit mention of the usual
side-condition that the labels of a record should not contain
repetitions. *)
(* It is possible to devise informal notations that are
more precise, but these tend to be quite heavy and to obscure the
main points of the definitions. So we'll leave these a bit loose
here (they are informal anyway, after all) and do the work of
tightening things up elsewhere (in chapter [Records]). *)
(**
Reduction:
ti ==> ti'
------------------------------------ (ST_Rcd)
{i1=v1, ..., im=vm, in=ti, ...}
==> {i1=v1, ..., im=vm, in=ti', ...}
t1 ==> t1'
-------------- (ST_Proj1)
t1.i ==> t1'.i
------------------------- (ST_ProjRcd)
{..., i=vi, ...}.i ==> vi
Again, these rules are a bit informal. For example, the first rule
is intended to be read "if [ti] is the leftmost field that is not a
value and if [ti] steps to [ti'], then the whole record steps..."
In the last rule, the intention is that there should only be one
field called i, and that all the other fields must contain values. *)
(**
Typing:
Gamma |- t1 : T1 ... Gamma |- tn : Tn
-------------------------------------------------- (T_Rcd)
Gamma |- {i1=t1, ..., in=tn} : {i1:T1, ..., in:Tn}
Gamma |- t : {..., i:Ti, ...}
----------------------------- (T_Proj)
Gamma |- t.i : Ti
*)
(* ###################################################################### *)
(** *** Encoding Records (Optional) *)
(** There are several ways to make the above definitions precise.
- We can directly formalize the syntactic forms and inference
rules, staying as close as possible to the form we've given
them above. This is conceptually straightforward, and it's
probably what we'd want to do if we were building a real
compiler -- in particular, it will allow is to print error
messages in the form that programmers will find easy to
understand. But the formal versions of the rules will not be
pretty at all!
- We could look for a smoother way of presenting records -- for
example, a binary presentation with one constructor for the
empty record and another constructor for adding a single field
to an existing record, instead of a single monolithic
constructor that builds a whole record at once. This is the
right way to go if we are primarily interested in studying the
metatheory of the calculi with records, since it leads to
clean and elegant definitions and proofs. Chapter [Records]
shows how this can be done.
- Alternatively, if we like, we can avoid formalizing records
altogether, by stipulating that record notations are just
informal shorthands for more complex expressions involving
pairs and product types. We sketch this approach here.
First, observe that we can encode arbitrary-size tuples using
nested pairs and the [unit] value. To avoid overloading the pair
notation [(t1,t2)], we'll use curly braces without labels to write
down tuples, so [{}] is the empty tuple, [{5}] is a singleton
tuple, [{5,6}] is a 2-tuple (morally the same as a pair),
[{5,6,7}] is a triple, etc.
<<
{} ----> unit
{t1, t2, ..., tn} ----> (t1, trest)
where {t2, ..., tn} ----> trest
>>
Similarly, we can encode tuple types using nested product types:
<<
{} ----> Unit
{T1, T2, ..., Tn} ----> T1 * TRest
where {T2, ..., Tn} ----> TRest
>>
The operation of projecting a field from a tuple can be encoded
using a sequence of second projections followed by a first projection:
<<
t.0 ----> t.fst
t.(n+1) ----> (t.snd).n
>>
Next, suppose that there is some total ordering on record labels,
so that we can associate each label with a unique natural number.
This number is called the _position_ of the label. For example,
we might assign positions like this:
<<
LABEL POSITION
a 0
b 1
c 2
... ...
foo 1004
... ...
bar 10562
... ...
>>
We use these positions to encode record values as tuples (i.e., as
nested pairs) by sorting the fields according to their positions.
For example:
<<
{a=5, b=6} ----> {5,6}
{a=5, c=7} ----> {5,unit,7}
{c=7, a=5} ----> {5,unit,7}
{c=5, b=3} ----> {unit,3,5}
{f=8,c=5,a=7} ----> {7,unit,5,unit,unit,8}
{f=8,c=5} ----> {unit,unit,5,unit,unit,8}
>>
Note that each field appears in the position associated with its
label, that the size of the tuple is determined by the label with
the highest position, and that we fill in unused positions with
[unit].
We do exactly the same thing with record types:
<<
{a:Nat, b:Nat} ----> {Nat,Nat}
{c:Nat, a:Nat} ----> {Nat,Unit,Nat}
{f:Nat,c:Nat} ----> {Unit,Unit,Nat,Unit,Unit,Nat}
>>
Finally, record projection is encoded as a tuple projection from
the appropriate position:
<<
t.l ----> t.(position of l)
>>
It is not hard to check that all the typing rules for the original
"direct" presentation of records are validated by this
encoding. (The reduction rules are "almost validated" -- not
quite, because the encoding reorders fields.) *)
(** Of course, this encoding will not be very efficient if we
happen to use a record with label [bar]! But things are not
actually as bad as they might seem: for example, if we assume that
our compiler can see the whole program at the same time, we can
_choose_ the numbering of labels so that we assign small positions
to the most frequently used labels. Indeed, there are industrial
compilers that essentially do this! *)
(** *** Variants (Optional Reading) *)
(** Just as products can be generalized to records, sums can be
generalized to n-ary labeled types called _variants_. Instead of
[T1+T2], we can write something like [<l1:T1,l2:T2,...ln:Tn>]
where [l1],[l2],... are field labels which are used both to build
instances and as case arm labels.
These n-ary variants give us almost enough mechanism to build
arbitrary inductive data types like lists and trees from
scratch -- the only thing missing is a way to allow _recursion_ in
type definitions. We won't cover this here, but detailed
treatments can be found in many textbooks -- e.g., Types and
Programming Languages. *)
(* ###################################################################### *)
(** * Exercise: Formalizing the Extensions *)
(** **** Exercise: 4 stars, advanced (STLC_extensions) *)
(** In this problem you will formalize a couple of the extensions
described above. We've provided the necessary additions to the
syntax of terms and types, and we've included a few examples that
you can test your definitions with to make sure they are working
as expected. You'll fill in the rest of the definitions and
extend all the proofs accordingly.
To get you started, we've provided implementations for:
- numbers
- pairs and units
- sums
- lists
You need to complete the implementations for:
- let (which involves binding)
- [fix]
A good strategy is to work on the extensions one at a time, in
multiple passes, rather than trying to work through the file from
start to finish in a single pass. For each definition or proof,
begin by reading carefully through the parts that are provided for
you, referring to the text in the [Stlc] chapter for high-level
intuitions and the embedded comments for detailed mechanics.
*)
Module STLCExtended.
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty
| TUnit : ty
| TProd : ty -> ty -> ty
| TSum : ty -> ty -> ty
| TList : ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TArrow" | Case_aux c "TNat"
| Case_aux c "TProd" | Case_aux c "TUnit"
| Case_aux c "TSum" | Case_aux c "TList" ].
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* numbers *)
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* units *)
| tunit : tm
(* let *)
| tlet : id -> tm -> tm -> tm
(* i.e., [let x = t1 in t2] *)
(* sums *)
| tinl : ty -> tm -> tm
| tinr : ty -> tm -> tm
| tcase : tm -> id -> tm -> id -> tm -> tm
(* i.e., [case t0 of inl x1 => t1 | inr x2 => t2] *)
(* lists *)
| tnil : ty -> tm
| tcons : tm -> tm -> tm
| tlcase : tm -> tm -> id -> id -> tm -> tm
(* i.e., [lcase t1 of | nil -> t2 | x::y -> t3] *)
(* fix *)
| tfix : tm -> tm.
(** Note that, for brevity, we've omitted booleans and instead
provided a single [if0] form combining a zero test and a
conditional. That is, instead of writing
<<
if x = 0 then ... else ...
>>
we'll write this:
<<
if0 x then ... else ...
>>
*)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tnat" | Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tpair" | Case_aux c "tfst" | Case_aux c "tsnd"
| Case_aux c "tunit" | Case_aux c "tlet"
| Case_aux c "tinl" | Case_aux c "tinr" | Case_aux c "tcase"
| Case_aux c "tnil" | Case_aux c "tcons" | Case_aux c "tlcase"
| Case_aux c "tfix" ].
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if eq_id_dec x y then s else t
| tabs y T t1 =>
tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tpair t1 t2 =>
tpair (subst x s t1) (subst x s t2)
| tfst t1 =>
tfst (subst x s t1)
| tsnd t1 =>
tsnd (subst x s t1)
| tunit => tunit
(* FILL IN HERE *)
| tinl T t1 =>
tinl T (subst x s t1)
| tinr T t1 =>
tinr T (subst x s t1)
| tcase t0 y1 t1 y2 t2 =>
tcase (subst x s t0)
y1 (if eq_id_dec x y1 then t1 else (subst x s t1))
y2 (if eq_id_dec x y2 then t2 else (subst x s t2))
| tnil T =>
tnil T
| tcons t1 t2 =>
tcons (subst x s t1) (subst x s t2)
| tlcase t1 t2 y1 y2 t3 =>
tlcase (subst x s t1) (subst x s t2) y1 y2
(if eq_id_dec x y1 then
t3
else if eq_id_dec x y2 then t3
else (subst x s t3))
(* FILL IN HERE *)
| _ => t (* ... and delete this line *)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
(** Next we define the values of our language. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
(* Numbers are values: *)
| v_nat : forall n1,
value (tnat n1)
(* A pair is a value if both components are: *)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
(* A unit is always a value *)
| v_unit : value tunit
(* A tagged value is a value: *)
| v_inl : forall v T,
value v ->
value (tinl T v)
| v_inr : forall v T,
value v ->
value (tinr T v)
(* A list is a value iff its head and tail are values: *)
| v_lnil : forall T, value (tnil T)
| v_lcons : forall v1 vl,
value v1 ->
value vl ->
value (tcons v1 vl)
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* nats *)
| ST_Succ1 : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_SuccNat : forall n1,
(tsucc (tnat n1)) ==> (tnat (S n1))
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_PredNat : forall n1,
(tpred (tnat n1)) ==> (tnat (pred n1))
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
(tmult t1 t2) ==> (tmult t1' t2)
| ST_Mult2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tmult v1 t2) ==> (tmult v1 t2')
| ST_MultNats : forall n1 n2,
(tmult (tnat n1) (tnat n2)) ==> (tnat (mult n1 n2))
| ST_If01 : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_If0Zero : forall t2 t3,
(tif0 (tnat 0) t2 t3) ==> t2
| ST_If0Nonzero : forall n t2 t3,
(tif0 (tnat (S n)) t2 t3) ==> t3
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst1 : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd1 : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* let *)
(* FILL IN HERE *)
(* sums *)
| ST_Inl : forall t1 t1' T,
t1 ==> t1' ->
(tinl T t1) ==> (tinl T t1')
| ST_Inr : forall t1 t1' T,
t1 ==> t1' ->
(tinr T t1) ==> (tinr T t1')
| ST_Case : forall t0 t0' x1 t1 x2 t2,
t0 ==> t0' ->
(tcase t0 x1 t1 x2 t2) ==> (tcase t0' x1 t1 x2 t2)
| ST_CaseInl : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinl T v0) x1 t1 x2 t2) ==> [x1:=v0]t1
| ST_CaseInr : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinr T v0) x1 t1 x2 t2) ==> [x2:=v0]t2
(* lists *)
| ST_Cons1 : forall t1 t1' t2,
t1 ==> t1' ->
(tcons t1 t2) ==> (tcons t1' t2)
| ST_Cons2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tcons v1 t2) ==> (tcons v1 t2')
| ST_Lcase1 : forall t1 t1' t2 x1 x2 t3,
t1 ==> t1' ->
(tlcase t1 t2 x1 x2 t3) ==> (tlcase t1' t2 x1 x2 t3)
| ST_LcaseNil : forall T t2 x1 x2 t3,
(tlcase (tnil T) t2 x1 x2 t3) ==> t2
| ST_LcaseCons : forall v1 vl t2 x1 x2 t3,
value v1 ->
value vl ->
(tlcase (tcons v1 vl) t2 x1 x2 t3) ==> (subst x2 vl (subst x1 v1 t3))
(* fix *)
(* FILL IN HERE *)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Succ1" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Pred1" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_MultNats" | Case_aux c "ST_If01"
| Case_aux c "ST_If0Zero" | Case_aux c "ST_If0Nonzero"
| Case_aux c "ST_Pair1" | Case_aux c "ST_Pair2"
| Case_aux c "ST_Fst1" | Case_aux c "ST_FstPair"
| Case_aux c "ST_Snd1" | Case_aux c "ST_SndPair"
(* FILL IN HERE *)
| Case_aux c "ST_Inl" | Case_aux c "ST_Inr" | Case_aux c "ST_Case"
| Case_aux c "ST_CaseInl" | Case_aux c "ST_CaseInr"
| Case_aux c "ST_Cons1" | Case_aux c "ST_Cons2" | Case_aux c "ST_Lcase1"
| Case_aux c "ST_LcaseNil" | Case_aux c "ST_LcaseCons"
(* FILL IN HERE *)
].
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
(** Next we define the typing rules. These are nearly direct
transcriptions of the inference rules shown above. *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(extend Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
(* nats *)
| T_Nat : forall Gamma n1,
Gamma |- (tnat n1) \in TNat
| T_Succ : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tsucc t1) \in TNat
| T_Pred : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tpred t1) \in TNat
| T_Mult : forall Gamma t1 t2,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in TNat ->
Gamma |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma t1 t2 t3 T1,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- (tif0 t1 t2 t3) \in T1
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in T2 ->
Gamma |- (tpair t1 t2) \in (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tfst t) \in T1
| T_Snd : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tsnd t) \in T2
(* unit *)
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* let *)
(* FILL IN HERE *)
(* sums *)
| T_Inl : forall Gamma t1 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- (tinl T2 t1) \in (TSum T1 T2)
| T_Inr : forall Gamma t2 T1 T2,
Gamma |- t2 \in T2 ->
Gamma |- (tinr T1 t2) \in (TSum T1 T2)
| T_Case : forall Gamma t0 x1 T1 t1 x2 T2 t2 T,
Gamma |- t0 \in (TSum T1 T2) ->
(extend Gamma x1 T1) |- t1 \in T ->
(extend Gamma x2 T2) |- t2 \in T ->
Gamma |- (tcase t0 x1 t1 x2 t2) \in T
(* lists *)
| T_Nil : forall Gamma T,
Gamma |- (tnil T) \in (TList T)
| T_Cons : forall Gamma t1 t2 T1,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in (TList T1) ->
Gamma |- (tcons t1 t2) \in (TList T1)
| T_Lcase : forall Gamma t1 T1 t2 x1 x2 t3 T2,
Gamma |- t1 \in (TList T1) ->
Gamma |- t2 \in T2 ->
(extend (extend Gamma x2 (TList T1)) x1 T1) |- t3 \in T2 ->
Gamma |- (tlcase t1 t2 x1 x2 t3) \in T2
(* fix *)
(* FILL IN HERE *)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Pair" | Case_aux c "T_Fst" | Case_aux c "T_Snd"
| Case_aux c "T_Unit"
(* let *)
(* FILL IN HERE *)
| Case_aux c "T_Inl" | Case_aux c "T_Inr" | Case_aux c "T_Case"
| Case_aux c "T_Nil" | Case_aux c "T_Cons" | Case_aux c "T_Lcase"
(* fix *)
(* FILL IN HERE *)
].
(* ###################################################################### *)
(** ** Examples *)
(** This section presents formalized versions of the examples from
above (plus several more). The ones at the beginning focus on
specific features; you can use these to make sure your definition
of a given feature is reasonable before moving on to extending the
proofs later in the file with the cases relating to this feature.
The later examples require all the features together, so you'll
need to come back to these when you've got all the definitions
filled in. *)
Module Examples.
(** *** Preliminaries *)
(** First, let's define a few variable names: *)
Notation a := (Id 0).
Notation f := (Id 1).
Notation g := (Id 2).
Notation l := (Id 3).
Notation k := (Id 6).
Notation i1 := (Id 7).
Notation i2 := (Id 8).
Notation x := (Id 9).
Notation y := (Id 10).
Notation processSum := (Id 11).
Notation n := (Id 12).
Notation eq := (Id 13).
Notation m := (Id 14).
Notation evenodd := (Id 15).
Notation even := (Id 16).
Notation odd := (Id 17).
Notation eo := (Id 18).
(** Next, a bit of Coq hackery to automate searching for typing
derivations. You don't need to understand this bit in detail --
just have a look over it so that you'll know what to look for if
you ever find yourself needing to make custom extensions to
[auto].
The following [Hint] declarations say that, whenever [auto]
arrives at a goal of the form [(Gamma |- (tapp e1 e1) \in T)], it
should consider [eapply T_App], leaving an existential variable
for the middle type T1, and similar for [lcase]. That variable
will then be filled in during the search for type derivations for
[e1] and [e2]. We also include a hint to "try harder" when
solving equality goals; this is useful to automate uses of
[T_Var] (which includes an equality as a precondition). *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
(* You'll want to uncomment the following line once
you've defined the [T_Lcase] constructor for the typing
relation: *)
(*
Hint Extern 2 (has_type _ (tlcase _ _ _ _ _) _) =>
eapply T_Lcase; auto.
*)
Hint Extern 2 (_ = _) => compute; reflexivity.
(** *** Numbers *)
Module Numtest.
(* if0 (pred (succ (pred (2 * 0))) then 5 else 6 *)
Definition test :=
tif0
(tpred
(tsucc
(tpred
(tmult
(tnat 2)
(tnat 0)))))
(tnat 5)
(tnat 6).
(** Remove the comment braces once you've implemented enough of the
definitions that you think this should work. *)
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof.
unfold test.
(* This typing derivation is quite deep, so we need to increase the
max search depth of [auto] from the default 5 to 10. *)
auto 10.
Qed.
Example numtest_reduces :
test ==>* tnat 5.
Proof.
unfold test. normalize.
Qed.
*)
End Numtest.
(** *** Products *)
Module Prodtest.
(* ((5,6),7).fst.snd *)
Definition test :=
tsnd
(tfst
(tpair
(tpair
(tnat 5)
(tnat 6))
(tnat 7))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End Prodtest.
(** *** [let] *)
Module LetTest.
(* let x = pred 6 in succ x *)
Definition test :=
tlet
x
(tpred (tnat 6))
(tsucc (tvar x)).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End LetTest.
(** *** Sums *)
Module Sumtest1.
(* case (inl Nat 5) of
inl x => x
| inr y => y *)
Definition test :=
tcase (tinl TNat (tnat 5))
x (tvar x)
y (tvar y).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tnat 5).
Proof. unfold test. normalize. Qed.
*)
End Sumtest1.
Module Sumtest2.
(* let processSum =
\x:Nat+Nat.
case x of
inl n => n
inr n => if0 n then 1 else 0 in
(processSum (inl Nat 5), processSum (inr Nat 5)) *)
Definition test :=
tlet
processSum
(tabs x (TSum TNat TNat)
(tcase (tvar x)
n (tvar n)
n (tif0 (tvar n) (tnat 1) (tnat 0))))
(tpair
(tapp (tvar processSum) (tinl TNat (tnat 5)))
(tapp (tvar processSum) (tinr TNat (tnat 5)))).
(*
Example typechecks :
(@empty ty) |- test \in (TProd TNat TNat).
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tpair (tnat 5) (tnat 0)).
Proof. unfold test. normalize. Qed.
*)
End Sumtest2.
(** *** Lists *)
Module ListTest.
(* let l = cons 5 (cons 6 (nil Nat)) in
lcase l of
nil => 0
| x::y => x*x *)
Definition test :=
tlet l
(tcons (tnat 5) (tcons (tnat 6) (tnil TNat)))
(tlcase (tvar l)
(tnat 0)
x y (tmult (tvar x) (tvar x))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 20. Qed.
Example reduces :
test ==>* (tnat 25).
Proof. unfold test. normalize. Qed.
*)
End ListTest.
(** *** [fix] *)
Module FixTest1.
(* fact := fix
(\f:nat->nat.
\a:nat.
if a=0 then 1 else a * (f (pred a))) *)
Definition fact :=
tfix
(tabs f (TArrow TNat TNat)
(tabs a TNat
(tif0
(tvar a)
(tnat 1)
(tmult
(tvar a)
(tapp (tvar f) (tpred (tvar a))))))).
(** (Warning: you may be able to typecheck [fact] but still have some
rules wrong!) *)
(*
Example fact_typechecks :
(@empty ty) |- fact \in (TArrow TNat TNat).
Proof. unfold fact. auto 10.
Qed.
*)
(*
Example fact_example:
(tapp fact (tnat 4)) ==>* (tnat 24).
Proof. unfold fact. normalize. Qed.
*)
End FixTest1.
Module FixTest2.
(* map :=
\g:nat->nat.
fix
(\f:[nat]->[nat].
\l:[nat].
case l of
| [] -> []
| x::l -> (g x)::(f l)) *)
Definition map :=
tabs g (TArrow TNat TNat)
(tfix
(tabs f (TArrow (TList TNat) (TList TNat))
(tabs l (TList TNat)
(tlcase (tvar l)
(tnil TNat)
a l (tcons (tapp (tvar g) (tvar a))
(tapp (tvar f) (tvar l))))))).
(*
(* Make sure you've uncommented the last [Hint Extern] above... *)
Example map_typechecks :
empty |- map \in
(TArrow (TArrow TNat TNat)
(TArrow (TList TNat)
(TList TNat))).
Proof. unfold map. auto 10. Qed.
Example map_example :
tapp (tapp map (tabs a TNat (tsucc (tvar a))))
(tcons (tnat 1) (tcons (tnat 2) (tnil TNat)))
==>* (tcons (tnat 2) (tcons (tnat 3) (tnil TNat))).
Proof. unfold map. normalize. Qed.
*)
End FixTest2.
Module FixTest3.
(* equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if0 m then (if0 n then 1 else 0)
else if0 n then 0
else eq (pred m) (pred n)) *)
Definition equal :=
tfix
(tabs eq (TArrow TNat (TArrow TNat TNat))
(tabs m TNat
(tabs n TNat
(tif0 (tvar m)
(tif0 (tvar n) (tnat 1) (tnat 0))
(tif0 (tvar n)
(tnat 0)
(tapp (tapp (tvar eq)
(tpred (tvar m)))
(tpred (tvar n)))))))).
(*
Example equal_typechecks :
(@empty ty) |- equal \in (TArrow TNat (TArrow TNat TNat)).
Proof. unfold equal. auto 10.
Qed.
*)
(*
Example equal_example1:
(tapp (tapp equal (tnat 4)) (tnat 4)) ==>* (tnat 1).
Proof. unfold equal. normalize. Qed.
*)
(*
Example equal_example2:
(tapp (tapp equal (tnat 4)) (tnat 5)) ==>* (tnat 0).
Proof. unfold equal. normalize. Qed.
*)
End FixTest3.
Module FixTest4.
(* let evenodd =
fix
(\eo: (Nat->Nat * Nat->Nat).
let e = \n:Nat. if0 n then 1 else eo.snd (pred n) in
let o = \n:Nat. if0 n then 0 else eo.fst (pred n) in
(e,o)) in
let even = evenodd.fst in
let odd = evenodd.snd in
(even 3, even 4)
*)
Definition eotest :=
tlet evenodd
(tfix
(tabs eo (TProd (TArrow TNat TNat) (TArrow TNat TNat))
(tpair
(tabs n TNat
(tif0 (tvar n)
(tnat 1)
(tapp (tsnd (tvar eo)) (tpred (tvar n)))))
(tabs n TNat
(tif0 (tvar n)
(tnat 0)
(tapp (tfst (tvar eo)) (tpred (tvar n))))))))
(tlet even (tfst (tvar evenodd))
(tlet odd (tsnd (tvar evenodd))
(tpair
(tapp (tvar even) (tnat 3))
(tapp (tvar even) (tnat 4))))).
(*
Example eotest_typechecks :
(@empty ty) |- eotest \in (TProd TNat TNat).
Proof. unfold eotest. eauto 30.
Qed.
*)
(*
Example eotest_example1:
eotest ==>* (tpair (tnat 0) (tnat 1)).
Proof. unfold eotest. normalize. Qed.
*)
End FixTest4.
End Examples.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** The proofs of progress and preservation for this system are
essentially the same (though of course somewhat longer) as for the
pure simply typed lambda-calculus. *)
(* ###################################################################### *)
(** *** Progress *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
(* Theorem: Suppose empty |- t : T. Then either
1. t is a value, or
2. t ==> t' for some t'.
Proof: By induction on the given typing derivation. *)
intros t T Ht.
remember (@empty ty) as Gamma.
generalize dependent HeqGamma.
has_type_cases (induction Ht) Case; intros HeqGamma; subst.
Case "T_Var".
(* The final rule in the given typing derivation cannot be [T_Var],
since it can never be the case that [empty |- x : T] (since the
context is empty). *)
inversion H.
Case "T_Abs".
(* If the [T_Abs] rule was the last used, then [t = tabs x T11 t12],
which is a value. *)
left...
Case "T_App".
(* If the last rule applied was T_App, then [t = t1 t2], and we know
from the form of the rule that
[empty |- t1 : T1 -> T2]
[empty |- t2 : T1]
By the induction hypothesis, each of t1 and t2 either is a value
or can take a step. *)
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
(* If both [t1] and [t2] are values, then we know that
[t1 = tabs x T11 t12], since abstractions are the only values
that can have an arrow type. But
[(tabs x T11 t12) t2 ==> [x:=t2]t12] by [ST_AppAbs]. *)
inversion H; subst; try (solve by inversion).
exists (subst x t2 t12)...
SSCase "t2 steps".
(* If [t1] is a value and [t2 ==> t2'], then [t1 t2 ==> t1 t2']
by [ST_App2]. *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
(* Finally, If [t1 ==> t1'], then [t1 t2 ==> t1' t2] by [ST_App1]. *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Nat".
left...
Case "T_Succ".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (S n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsucc t1')...
Case "T_Pred".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (pred n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tpred t1')...
Case "T_Mult".
right.
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
inversion H0; subst; try solve by inversion.
exists (tnat (mult n1 n0))...
SSCase "t2 steps".
inversion H0 as [t2' Hstp].
exists (tmult t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tmult t1' t2)...
Case "T_If0".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
destruct n1 as [|n1'].
SSCase "n1=0".
exists t2...
SSCase "n1<>0".
exists t3...
SCase "t1 steps".
inversion H as [t1' H0].
exists (tif0 t1' t2 t3)...
Case "T_Pair".
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 steps".
right. inversion H0 as [t2' Hstp].
exists (tpair t1 t2')...
SCase "t1 steps".
right. inversion H as [t1' Hstp].
exists (tpair t1' t2)...
Case "T_Fst".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v1...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tfst t1')...
Case "T_Snd".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v2...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsnd t1')...
Case "T_Unit".
left...
(* let *)
(* FILL IN HERE *)
Case "T_Inl".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinl _ t1')... *)
Case "T_Inr".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinr _ t1')... *)
Case "T_Case".
right.
destruct IHHt1...
SCase "t0 is a value".
inversion H; subst; try solve by inversion.
SSCase "t0 is inl".
exists ([x1:=v]t1)...
SSCase "t0 is inr".
exists ([x2:=v]t2)...
SCase "t0 steps".
inversion H as [t0' Hstp].
exists (tcase t0' x1 t1 x2 t2)...
Case "T_Nil".
left...
Case "T_Cons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. inversion H0 as [t2' Hstp].
exists (tcons t1 t2')...
SCase "head steps".
right. inversion H as [t1' Hstp].
exists (tcons t1' t2)...
Case "T_Lcase".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
SSCase "t1=tnil".
exists t2...
SSCase "t1=tcons v1 vl".
exists ([x2:=vl]([x1:=v1]t3))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tlcase t1' t2 x1 x2 t3)...
(* fix *)
(* FILL IN HERE *)
Qed.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* nats *)
| afi_succ : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_pred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if01 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if02 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if03 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* let *)
(* FILL IN HERE *)
(* sums *)
| afi_inl : forall x t T,
appears_free_in x t ->
appears_free_in x (tinl T t)
| afi_inr : forall x t T,
appears_free_in x t ->
appears_free_in x (tinr T t)
| afi_case0 : forall x t0 x1 t1 x2 t2,
appears_free_in x t0 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case1 : forall x t0 x1 t1 x2 t2,
x1 <> x ->
appears_free_in x t1 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case2 : forall x t0 x1 t1 x2 t2,
x2 <> x ->
appears_free_in x t2 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
(* lists *)
| afi_cons1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tcons t1 t2)
| afi_cons2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tcons t1 t2)
| afi_lcase1 : forall x t1 t2 y1 y2 t3,
appears_free_in x t1 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase2 : forall x t1 t2 y1 y2 t3,
appears_free_in x t2 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase3 : forall x t1 t2 y1 y2 t3,
y1 <> x ->
y2 <> x ->
appears_free_in x t3 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
(* fix *)
(* FILL IN HERE *)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend.
destruct (eq_id_dec x y)...
Case "T_Mult".
apply T_Mult...
Case "T_If0".
apply T_If0...
Case "T_Pair".
apply T_Pair...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
eapply T_Case...
apply IHhas_type2. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x2 y)...
Case "T_Cons".
apply T_Cons...
Case "T_Lcase".
eapply T_Lcase... apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
destruct (eq_id_dec x2 y)...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; inversion Hafi; subst...
Case "T_Abs".
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
SCase "left".
destruct IHHtyp2 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
SCase "right".
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Case "T_Lcase".
clear Htyp1 IHHtyp1 Htyp2 IHHtyp2.
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx... rewrite neq_id in Hctx...
Qed.
(* ###################################################################### *)
(** *** Substitution *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(extend Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- [x:=v]t : S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
t_cases (induction t) Case;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
Case "tvar".
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
Case "tabs".
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 : S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
(* let *)
(* FILL IN HERE *)
Case "tcase".
rename i into x1. rename i0 into x2.
eapply T_Case...
SCase "left arm".
destruct (eq_id_dec x x1).
SSCase "x = x1".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
SSCase "x <> x1".
apply IHt2. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
subst. rewrite neq_id...
SCase "right arm".
destruct (eq_id_dec x x2).
SSCase "x = x2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
SSCase "x <> x2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
subst. rewrite neq_id...
Case "tlcase".
rename i into y1. rename i0 into y2.
eapply T_Lcase...
destruct (eq_id_dec x y1).
SCase "x=y1".
simpl.
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
SCase "x<>y1".
destruct (eq_id_dec x y2).
SSCase "x=y2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y2 z)...
SSCase "x<>y2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
subst. rewrite neq_id...
destruct (eq_id_dec y2 z)...
subst. rewrite neq_id...
Qed.
(* ###################################################################### *)
(** *** Preservation *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
SCase "ST_AppAbs".
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
Case "T_Fst".
inversion HT...
Case "T_Snd".
inversion HT...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
SCase "ST_CaseInl".
inversion HT1; subst.
eapply substitution_preserves_typing...
SCase "ST_CaseInr".
inversion HT1; subst.
eapply substitution_preserves_typing...
Case "T_Lcase".
SCase "ST_LcaseCons".
inversion HT1; subst.
apply substitution_preserves_typing with (TList T1)...
apply substitution_preserves_typing with T1...
(* fix *)
(* FILL IN HERE *)
Qed.
(** [] *)
End STLCExtended.
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EBUFN_PP_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_ELU_sMINodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_ELU_sMINodr
// File Name: d_KES_PE_ELU_sMINodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Error Locator Update module, minimum order + 1 (semi-)
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_ELU_sMINodr // error locate update module: minimum order + 1 (semi-)
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_ELU,
input wire [`D_KES_GF_ORDER-1:0] i_v_2i_Xm1,
input wire [`D_KES_GF_ORDER-1:0] i_k_2i_Xm1,
input wire [`D_KES_GF_ORDER-1:0] i_d_2i,
input wire [`D_KES_GF_ORDER-1:0] i_delta_2im2,
input wire i_condition_2i,
output reg [`D_KES_GF_ORDER-1:0] o_v_2i_X,
output reg o_v_2i_X_deg_chk_bit,
output reg [`D_KES_GF_ORDER-1:0] o_k_2i_X
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_ELU_RST = 2'b01; // reset
parameter PE_ELU_OUT = 2'b10; // output buffer update
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_A;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_B;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X;
wire [`D_KES_GF_ORDER-1:0] w_k_2ip2_X;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_ELU_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_ELU_RST: begin
r_nxt_state <= (i_EXECUTE_PE_ELU)? (PE_ELU_OUT):(PE_ELU_RST);
end
PE_ELU_OUT: begin
r_nxt_state <= PE_ELU_RST;
end
default: begin
r_nxt_state <= PE_ELU_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 0;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
end
else begin
case (r_nxt_state)
PE_ELU_RST: begin // hold original data
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
PE_ELU_OUT: begin // output update only
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= w_v_2ip2_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= |(w_v_2ip2_X[`D_KES_GF_ORDER-1:0]);
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= w_k_2ip2_X[`D_KES_GF_ORDER-1:0];
end
default: begin
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_delta_2im2_FFM_v_2i_X (
.i_poly_form_A (i_delta_2im2[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (o_v_2i_X[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0]));
d_parallel_FFM_gate_GF12 d_d_2i_FFM_k_2i_Xm1 (
.i_poly_form_A (i_d_2i[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (i_k_2i_Xm1[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_B[`D_KES_GF_ORDER-1:0]));
assign w_v_2ip2_X[`D_KES_GF_ORDER-1:0] = w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0] ^ w_v_2ip2_X_term_B[`D_KES_GF_ORDER-1:0];
assign w_k_2ip2_X[`D_KES_GF_ORDER-1:0] = (i_condition_2i)? (i_v_2i_Xm1[`D_KES_GF_ORDER-1:0]):(D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0]);
endmodule
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// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
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