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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_SYMBOL_V
`define SKY130_FD_SC_MS__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_SYMBOL_V
|
// Used for 32 bit data axi ports like GP0/GP1
module axi_master32_stub(
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [31:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [31:0] M2S_AXI_WDATA,
output [3:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read Transaction
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 32'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 32'b0;
assign M2S_AXI_WSTRB = 4'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule : axi_master32_stub
/*
axi_master_stub axi_master_XXX_stub (
.M2S_AXI_ACLK(M2S_XXX_AXI_ACLK),
//Read Transaction
.M2S_AXI_ARVALID(M2S_XXX_AXI_ARVALID),
.M2S_AXI_ARREADY(M2S_XXX_AXI_ARREADY),
.M2S_AXI_ARADDR(M2S_XXX_AXI_ARADDR[31:0]),
.M2S_AXI_ARBURST(M2S_XXX_AXI_ARBURST[1:0]),
.M2S_AXI_ARLEN(M2S_XXX_AXI_ARLEN[3:0]),
.M2S_AXI_ARSIZE(M2S_XXX_AXI_ARSIZE[1:0]),
//
.M2S_AXI_RVALID(M2S_XXX_AXI_RVALID),
.M2S_AXI_RREADY(M2S_XXX_AXI_RREADY),
.M2S_AXI_RLAST(M2S_XXX_AXI_RLAST),
.M2S_AXI_RDATA(M2S_XXX_AXI_RDATA[63:0]),
//
.M2S_AXI_RRESP(M2S_XXX_AXI_RRESP[1:0]),
// Write Transaction
.M2S_AXI_AWVALID(M2S_XXX_AXI_AWVALID),
.M2S_AXI_AWREADY(M2S_XXX_AXI_AWREADY),
.M2S_AXI_AWADDR(M2S_XXX_AXI_AWADDR[31:0]),
.M2S_AXI_AWBURST(M2S_XXX_AXI_AWBURST[1:0]),
.M2S_AXI_AWLEN(M2S_XXX_AXI_AWLEN[3:0]),
.M2S_AXI_AWSIZE(M2S_XXX_AXI_AWSIZE[1:0]),
//
.M2S_AXI_WVALID(M2S_XXX_AXI_WVALID),
.M2S_AXI_WREADY(M2S_XXX_AXI_WREADY),
.M2S_AXI_WLAST(M2S_XXX_AXI_WLAST),
.M2S_AXI_WDATA(M2S_XXX_AXI_WDATA[63:0]),
.M2S_AXI_WSTRB(M2S_XXX_AXI_WSTRB[7:0]),
//
.M2S_AXI_BVALID(M2S_XXX_AXI_BVALID),
.M2S_AXI_BREADY(M2S_XXX_AXI_BREADY),
.M2S_AXI_BRESP(M2S_XXX_AXI_BRESP[1:0])
);
*/
|
module simf_tb;
//wires
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
reg [5:0] issue_wfid;
reg [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
reg [15:0] issue_imm_value0;
reg [31:0] issue_imm_value1, issue_opcode, sgpr_rd_data, exec_rd_m0_value,
issue_instr_pc;
reg [63:0] exec_rd_exec_value, exec_rd_vcc_value;
reg [2047:0] vgpr_source1_data, vgpr_source2_data, vgpr_source3_data;
wire vgpr_source1_rd_en, vgpr_source2_rd_en, vgpr_source3_rd_en, vgpr_wr_en,
exec_rd_en, exec_wr_vcc_en, sgpr_rd_en, sgpr_wr_en, issue_alu_ready,
vgpr_instr_done, rfa_queue_entry_valid;
wire [5:0] exec_rd_wfid, exec_wr_vcc_wfid, vgpr_instr_done_wfid;
wire [8:0] sgpr_rd_addr, sgpr_wr_addr;
wire [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_source3_addr,
vgpr_dest_addr;
wire [31:0] tracemon_retire_pc;
wire [63:0] vgpr_wr_mask, exec_wr_vcc_value, sgpr_wr_data;
wire [2047:0] vgpr_dest_data;
//instantiation of dut
simf simf(
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3), //TODO implement this.
.issue_dest_reg1(issue_dest_reg1),
.issue_dest_reg2(issue_dest_reg2), //TODO implement this
.issue_imm_value0(issue_imm_value0),
.issue_imm_value1(issue_imm_value1),
.issue_opcode(issue_opcode),
.issue_wfid(issue_wfid),
.issue_alu_select(issue_alu_select),
.vgpr_source1_data(vgpr_source1_data),
.vgpr_source2_data(vgpr_source2_data),
.vgpr_source3_data(vgpr_source3_data), //TODO implement this
.sgpr_rd_data(sgpr_rd_data),
.exec_rd_exec_value(exec_rd_exec_value),
.exec_rd_vcc_value(exec_rd_vcc_value),
.exec_rd_m0_value(exec_rd_m0_value), //TODO implement this
.exec_rd_scc_value(exec_rd_scc_value),
.issue_instr_pc(issue_instr_pc),
.rfa_queue_entry_serviced(rfa_queue_entry_serviced),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source3_rd_en(vgpr_source3_rd_en), //TODO
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.vgpr_source3_addr(vgpr_source3_addr), //TODO implement
.vgpr_dest_addr(vgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_wr_en(vgpr_wr_en),
.vgpr_wr_mask(vgpr_wr_mask),
.exec_rd_wfid(exec_rd_wfid),
.exec_rd_en(exec_rd_en),
.exec_wr_vcc_wfid(exec_wr_vcc_wfid),
.exec_wr_vcc_en(exec_wr_vcc_en),
.exec_wr_vcc_value(exec_wr_vcc_value),
.sgpr_rd_en(sgpr_rd_en),
.sgpr_rd_addr(sgpr_rd_addr),
.sgpr_wr_addr(sgpr_wr_addr), //TODO
.sgpr_wr_en(sgpr_wr_en), //TODO
.sgpr_wr_data(sgpr_wr_data), //TODO
.issue_alu_ready(issue_alu_ready),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.vgpr_instr_done(vgpr_instr_done),
.rfa_queue_entry_valid(rfa_queue_entry_valid),
.tracemon_retire_pc(tracemon_retire_pc),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
issue_alu_select = 1'b0;
rfa_queue_entry_serviced = 1'b0;
#10 rst = 1'b0;
#10000;
$finish;
end
initial begin
#31;
$display("ISSUING FLOAT ADD\n");
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_source_reg3 = {32{1'bx}};
issue_dest_reg1 = {2'b10,10'd31};
issue_dest_reg2 = {12{1'bx}};
issue_imm_value0 = {16{1'bx}};
issue_imm_value1 = {32{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h003}; //V_ADD_F32
issue_wfid = 6'd15;
issue_alu_select = 1'b1;
sgpr_rd_data = {32{1'bx}};
exec_rd_exec_value = 64'hf0ff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
exec_rd_m0_value = {32{1'bx}};
exec_rd_scc_value = 1'bx;
issue_instr_pc = 32'hdead_f00d;
rfa_queue_entry_serviced = 1'b0;
vgpr_source1_data = {64{32'h4205_9999}}; //33.4
vgpr_source2_data = {64{32'h41B7_3333}}; //22.9
vgpr_source3_data = {64{32'hx}};
#10;
issue_alu_select = 1'b0;
#1000;
$display("ISSUING FLOAT SUB\n");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h004}; //V_SUB_F32
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h4205_9999}}; //33.4
vgpr_source2_data = {64{32'h41B7_3333}}; //22.9
#10;
issue_alu_select = 1'b0;
#10;
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#1000;
$display("ISSUING FLOAT MUL");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h008}; //V_MUL_F32
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h4205_9999}}; //33.4
vgpr_source2_data = {64{32'h41B7_3333}}; //22.9
#10;
issue_alu_select = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor($time, ": issue_alu_select = %b, issue_alu_ready = %b \n \
rfa_queue_entry_serviced = %h, rfa_queue_entry_valid = %h \n \
vgpr_dest_data = %h",
issue_alu_select, issue_alu_ready,
rfa_queue_entry_serviced, rfa_queue_entry_valid,
vgpr_dest_data[31:0]
);
// $monitor("$time: vgpr_dest_data = %h", vgpr_dest_data);
//$monitor("$time: rfa_queue_entry_serviced = %b", rfa_queue_entry_serviced);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,simf_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_RX_ENGINE.v
// Version : 1.11
//--
//-- Description: Local-Link Receive Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_RX_ENGINE #(
parameter TCQ = 1,
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
input clk,
input rst_n,
// AXI-S
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output reg m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Memory Read data handshake with Completion
// transmit unit. Transmit unit reponds to
// req_compl assertion and responds with compl_done
// assertion when a Completion w/ data is transmitted.
output reg req_compl,
output reg req_compl_wd,
input compl_done,
output reg [2:0] req_tc, // Memory Read TC
output reg req_td, // Memory Read TD
output reg req_ep, // Memory Read EP
output reg [1:0] req_attr, // Memory Read Attribute
output reg [9:0] req_len, // Memory Read Length (1DW)
output reg [15:0] req_rid, // Memory Read Requestor ID
output reg [7:0] req_tag, // Memory Read Tag
output reg [7:0] req_be, // Memory Read Byte Enables
output reg [12:0] req_addr, // Memory Read Address
// Memory interface used to save 1 DW data received
// on Memory Write 32 TLP. Data extracted from
// inbound TLP is presented to the Endpoint memory
// unit. Endpoint memory unit reacts to wr_en
// assertion and asserts wr_busy when it is
// processing written information.
output reg [10:0] wr_addr, // Memory Write Address
output reg [7:0] wr_be, // Memory Write Byte Enable
output reg [31:0] wr_data, // Memory Write Data
output reg wr_en, // Memory Write Enable
input wr_busy // Memory Write Busy
);
localparam PIO_RX_MEM_RD32_FMT_TYPE = 7'b00_00000;
localparam PIO_RX_MEM_WR32_FMT_TYPE = 7'b10_00000;
localparam PIO_RX_MEM_RD64_FMT_TYPE = 7'b01_00000;
localparam PIO_RX_MEM_WR64_FMT_TYPE = 7'b11_00000;
localparam PIO_RX_IO_RD32_FMT_TYPE = 7'b00_00010;
localparam PIO_RX_IO_WR32_FMT_TYPE = 7'b10_00010;
localparam PIO_RX_RST_STATE = 8'b00000000;
localparam PIO_RX_MEM_RD32_DW1DW2 = 8'b00000001;
localparam PIO_RX_MEM_WR32_DW1DW2 = 8'b00000010;
localparam PIO_RX_MEM_RD64_DW1DW2 = 8'b00000100;
localparam PIO_RX_MEM_WR64_DW1DW2 = 8'b00001000;
localparam PIO_RX_MEM_WR64_DW3 = 8'b00010000;
localparam PIO_RX_WAIT_STATE = 8'b00100000;
localparam PIO_RX_IO_WR_DW1DW2 = 8'b01000000;
localparam PIO_RX_IO_MEM_WR_WAIT_STATE = 8'b10000000;
// Local Registers
reg [7:0] state;
reg [7:0] tlp_type;
wire io_bar_hit_n;
wire mem32_bar_hit_n;
wire mem64_bar_hit_n;
wire erom_bar_hit_n;
reg [1:0] region_select;
generate
if (C_DATA_WIDTH == 64) begin : pio_rx_sm_64
wire sop; // Start of packet
reg in_packet_q;
// Generate a signal that indicates if we are currently receiving a packet.
// This value is one clock cycle delayed from what is actually on the AXIS
// data bus.
always@(posedge clk)
begin
if(!rst_n)
in_packet_q <= # TCQ 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready && m_axis_rx_tlast)
in_packet_q <= # TCQ 1'b0;
else if (sop && m_axis_rx_tready)
in_packet_q <= # TCQ 1'b1;
end
assign sop = !in_packet_q && m_axis_rx_tvalid;
always @ ( posedge clk ) begin
if (!rst_n )
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
req_compl_wd <= #TCQ 1'b1;
req_tc <= #TCQ 3'b0;
req_td <= #TCQ 1'b0;
req_ep <= #TCQ 1'b0;
req_attr <= #TCQ 2'b0;
req_len <= #TCQ 10'b0;
req_rid <= #TCQ 16'b0;
req_tag <= #TCQ 8'b0;
req_be <= #TCQ 8'b0;
req_addr <= #TCQ 13'b0;
wr_be <= #TCQ 8'b0;
wr_addr <= #TCQ 11'b0;
wr_data <= #TCQ 32'b0;
wr_en <= #TCQ 1'b0;
state <= #TCQ PIO_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end
else
begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
case (state)
PIO_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
if (sop)
begin
case (m_axis_rx_tdata[30:24])
PIO_RX_MEM_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_IO_WR_DW1DW2;
end //if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end //if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
default : begin // other TLPs
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end // if (sop)
else
state <= #TCQ PIO_RX_RST_STATE;
end // PIO_RX_RST_STATE
PIO_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // PIO_RX_MEM_RD32_DW1DW2
PIO_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // PIO_RX_MEM_WR32_DW1DW2
PIO_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
req_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // PIO_RX_MEM_RD64_DW1DW2
PIO_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34]};
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // PIO_RX_MEM_WR64_DW1DW2
PIO_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[31:0];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // PIO_RX_MEM_WR64_DW3
PIO_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_IO_WR_DW1DW2;
end // PIO_RX_IO_WR_DW1DW2
PIO_RX_WAIT_STATE : begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
else
state <= #TCQ PIO_RX_WAIT_STATE;
end // PIO_RX_WAIT_STATE
default : begin
// default case stmt
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end
end
end
else if (C_DATA_WIDTH == 128) begin : pio_rx_sm_128
// Define where the start of packet happens. Remember that PCIe dwords
// start on the right and get filled in to the left of the 128-bit data
// bus.
// Start of packet can only happen on byte 0 (right most byte) or on
// byte 8 (middle byte).
wire sof_present = m_axis_rx_tuser[14];
wire sof_right = !m_axis_rx_tuser[13] && sof_present;
wire sof_mid = m_axis_rx_tuser[13] && sof_present;
always @ ( posedge clk ) begin
if (!rst_n )
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
req_compl_wd <= #TCQ 1'b1;
req_tc <= #TCQ 3'b0;
req_td <= #TCQ 1'b0;
req_ep <= #TCQ 1'b0;
req_attr <= #TCQ 2'b0;
req_len <= #TCQ 10'b0;
req_rid <= #TCQ 16'b0;
req_tag <= #TCQ 8'b0;
req_be <= #TCQ 8'b0;
req_addr <= #TCQ 13'b0;
wr_be <= #TCQ 8'b0;
wr_addr <= #TCQ 11'b0;
wr_data <= #TCQ 32'b0;
wr_en <= #TCQ 1'b0;
state <= #TCQ PIO_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end // if (!rst_n )
else
begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
case (state)
PIO_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
req_compl_wd <= #TCQ 1'b1;
// Packet starts in the middle of the 128-bit bus.
if ((m_axis_rx_tvalid) && (m_axis_rx_tready))
begin
if (sof_mid)
begin
tlp_type <= #TCQ m_axis_rx_tdata[95:88];
req_len <= #TCQ m_axis_rx_tdata[73:64];
m_axis_rx_tready <= #TCQ 1'b0;
// Evaluate packet type
case (m_axis_rx_tdata[94:88])
PIO_RX_MEM_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
default : begin // other TLPs
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase // case (m_axis_rx_tdata[94:88])
// Packet starts on the right of the data bus. Remember, packets start
// on the right and are filled to the left. The data-bus is filled 32-bits
// (one Dword) at time.
end
else if (sof_right)
begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
case (m_axis_rx_tdata[30:24])
PIO_RX_MEM_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_addr <= #TCQ {region_select[1:0],
m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
wr_data <= #TCQ m_axis_rx_tdata[127:96];
wr_en <= #TCQ 1'b1;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
// Upper 32-bits of 64-bit address not used, but would be captured
// in this state if used. Upper 32 address bits are on
//m_axis_rx_tdata[127:96]
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
// lower qw
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_WAIT_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
wr_data <= #TCQ m_axis_rx_tdata[127:96];
wr_en <= #TCQ 1'b1;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
wr_en <= #TCQ 1'b1;
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
endcase // case (m_axis_rx_tdata[30:24])
end // if (sof_right)
end
else // not a start of packet
state <= #TCQ PIO_RX_RST_STATE;
end //PIO_RX_RST_STATE
PIO_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[31:0];
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_WR64_DW3
PIO_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_RD32_DW1DW2
PIO_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_WR32_DW1DW2
PIO_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_IO_WR_DW1DW2
PIO_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_RD64_DW1DW2
PIO_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
// lower QW
wr_data <= #TCQ m_axis_rx_tdata[95:64];
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tvalid)
end // PIO_RX_MEM_WR64_DW1DW2
PIO_RX_WAIT_STATE : begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) &&(!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) &&(!wr_busy))
else if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!compl_done))
else if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
else
begin
state <= #TCQ PIO_RX_WAIT_STATE;
end
end // PIO_RX_WAIT_STATE
default : begin
// default case stmt
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end // if rst_n
end // always
end // pio_rx_sm_128
endgenerate
assign mem64_bar_hit_n = 1'b1;
assign io_bar_hit_n = 1'b1;
assign mem32_bar_hit_n = ~(m_axis_rx_tuser[2]);
assign erom_bar_hit_n = ~(m_axis_rx_tuser[8]);
always @*
begin
case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
4'b0111 : begin
region_select <= #TCQ 2'b00; // Select IO region
end // 4'b0111
4'b1011 : begin
region_select <= #TCQ 2'b01; // Select Mem32 region
end // 4'b1011
4'b1101 : begin
region_select <= #TCQ 2'b10; // Select Mem64 region
end // 4'b1101
4'b1110 : begin
region_select <= #TCQ 2'b11; // Select EROM region
end // 4'b1110
default : begin
region_select <= #TCQ 2'b00; // Error selection will select IO region
end // default
endcase // case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(state)
begin
case (state)
PIO_RX_RST_STATE : state_ascii <= #TCQ "RX_RST_STATE";
PIO_RX_MEM_RD32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD32_DW1DW2";
PIO_RX_MEM_WR32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR32_DW1DW2";
PIO_RX_MEM_RD64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD64_DW1DW2";
PIO_RX_MEM_WR64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR64_DW1DW2";
PIO_RX_MEM_WR64_DW3 : state_ascii <= #TCQ "RX_MEM_WR64_DW3";
PIO_RX_WAIT_STATE : state_ascii <= #TCQ "RX_WAIT_STATE";
PIO_RX_IO_WR_DW1DW2 : state_ascii <= #TCQ "RX_IO_WR_DW1DW2";
PIO_RX_IO_MEM_WR_WAIT_STATE : state_ascii <= #TCQ "RX_IO_MEM_WR_WAIT_STATE";
default : state_ascii <= #TCQ "PIO 128 STATE ERR";
endcase
end
// synthesis translate_on
endmodule // PIO_RX_ENGINE
|
module axis_control_if
#(
parameter C_s_axis_TDATA_WIDTH = 32,
parameter C_m_axis_TDATA_WIDTH = 32,
parameter C_m_axis_START_COUNT = 32,
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter C_m_axis_txc_START_COUNT = 32,
parameter ENABLE_LEN = 1
)
(
// Ports of Axi Master Bus Interface m_axis
input m_axis_txd_tvalid,
input m_axis_txd_tlast,
input m_axis_txd_tready,
input [11:0] tx_pkt_byte_cnt,
input tx_pkt_byte_cnt_vld,
input s_axis_rxs_aclk,
input s_axis_rxs_aresetn,
output s_axis_rxs_tready,
input [C_S_AXIS_RXS_TDATA_WIDTH-1 : 0] s_axis_rxs_tdata,
input [(C_S_AXIS_RXS_TDATA_WIDTH/8)-1 : 0] s_axis_rxs_tkeep,
input s_axis_rxs_tlast,
input s_axis_rxs_tvalid,
input m_axis_txc_aclk,
input m_axis_txc_aresetn,
output reg m_axis_txc_tvalid,
output reg [C_M_AXIS_TXC_TDATA_WIDTH-1 : 0] m_axis_txc_tdata,
output reg [(C_M_AXIS_TXC_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep,
output reg m_axis_txc_tlast,
input m_axis_txc_tready
);
reg [2:0] tx_ctrl_state;
localparam WAIT_FOR_REQ = 1,
SEND_CTRL_PKTS = 2,
WAIT_FOR_NXT = 4;
reg [7:0] send_ctrl_words;
localparam WORD0 = 1,
WORD1 = 2,
WORD2 = 4,
WORD3 = 8,
WORD4 = 16,
WORD5 = 32;
assign s_axis_rxs_tready = 1'b1;
reg len_fifo_rd_en;
wire [11:0] len_fifo_dout;
generate
if(ENABLE_LEN)begin
small_fifo
#( .WIDTH(12),
.MAX_DEPTH_BITS(5))
pkt_len_fifo
(
.clk(m_axis_txc_aclk),
.reset(!m_axis_txc_aresetn),
.din(tx_pkt_byte_cnt),
.wr_en(tx_pkt_byte_cnt_vld),
.rd_en(len_fifo_rd_en),
.dout(len_fifo_dout),
.full( ),
.prog_full(),
.nearly_full(),
.empty( )
);
end
else begin
assign len_fifo_dout = 12'hFFF;
end
endgenerate
always@(posedge m_axis_txc_aclk)
if(!m_axis_txc_aresetn)
len_fifo_rd_en <= 1'b0;
else if(tx_pkt_byte_cnt_vld)
len_fifo_rd_en <= 1'b1;
else len_fifo_rd_en<=0;
always @(posedge m_axis_txc_aclk)
if(!m_axis_txc_aresetn)begin
tx_ctrl_state <= WAIT_FOR_REQ;
send_ctrl_words <= WORD0;
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= 32'hFF_FF_FF_FF;
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
end
else begin
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= {24'h50000,len_fifo_dout};
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
case (tx_ctrl_state)
WAIT_FOR_REQ: begin
if(m_axis_txd_tvalid) begin
m_axis_txc_tvalid <= 1'b1;
tx_ctrl_state <= SEND_CTRL_PKTS;
end
end
SEND_CTRL_PKTS: begin
m_axis_txc_tvalid <= 1'b1;
if(m_axis_txc_tready) begin
case (send_ctrl_words)
WORD0: send_ctrl_words <= WORD1;
WORD1: send_ctrl_words <= WORD2;
WORD2: send_ctrl_words <= WORD3;
WORD3: send_ctrl_words <= WORD4;
WORD4: begin
send_ctrl_words <= WORD0;
m_axis_txc_tlast <= 1'b1;
tx_ctrl_state <= WAIT_FOR_NXT;
end
endcase
end
end
WAIT_FOR_NXT: begin
if(m_axis_txd_tready && m_axis_txd_tlast)tx_ctrl_state <= WAIT_FOR_REQ;
end
default:
tx_ctrl_state<=WAIT_FOR_REQ;
endcase
end
endmodule |
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Graying
:Function
Covert RGB images to gray-scale images.
Users can configure the multipliers by themselves.
Give the first output after mul_delay + 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module Graying(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data
);
/*
::description
This module's working mode.
::range
0 for Pipeline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
Color's bit width.
::range
1 - 12
*/
parameter color_width = 8;
/*
::description
Delay for multiplier.
::range
Depend your multilpliers' configurations
*/
parameter mul_delay = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [3 * color_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[color_width - 1 : 0] out_data;
reg[color_width - 1 : 0] reg_out_data;
reg[color_width - 1 : 0] r, g, b;
wire[10 : 0] mul_r;
wire[11 : 0] mul_g;
wire[8 : 0] mul_b;
reg[2 : 0] con_enable;
genvar i;
generate
if(work_mode == 0) begin
always @(*) begin
r = in_data[3 * color_width - 1 : 2 * color_width];
g = in_data[2 * color_width - 1 : 1 * color_width];
b = in_data[1 * color_width - 1 : 0 * color_width];
end
end else begin
always @(posedge in_enable) begin
r = in_data[3 * color_width - 1 : 2 * color_width];
g = in_data[2 * color_width - 1 : 1 * color_width];
b = in_data[1 * color_width - 1 : 0 * color_width];
end
end
/*
::description
Multiplier for Unsigned 12bits x 0.299, used for red channel.
You can configure the multiplier by yourself, then change the "mul_delay".
All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
*/
MultiplierRedx0d299 MulRed(.CLK (clk), .A({{12 - color_width{1'b0}} ,r}), .SCLR(~rst_n), .P(mul_r));
/*
::description
Multiplier for Unsigned 12bits x 0.587, used for green channel.
You can configure the multiplier by yourself, then change the "mul_delay".
All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
*/
MultiplierGreenx0d587 MulGreen(.CLK (clk), .A({{12 - color_width{1'b0}} ,g}), .SCLR(~rst_n), .P(mul_g));
/*
::description
Multiplier for Unsigned 12bits x 0.114, used for blue channel.
You can configure the multiplier by yourself, then change the "mul_delay".
All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
*/
MultiplierBluex0d114 MulBlue(.CLK (clk), .A({{12 - color_width{1'b0}} ,b}), .SCLR(~rst_n), .P(mul_b));
reg[11 : 0] mul_g_buffer;
reg[color_width - 1 : 0] sum_tmp;
always @(posedge clk) begin
mul_g_buffer <= mul_g;
sum_tmp <= mul_r + mul_b;
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
reg_out_data <= 0;
end else begin
reg_out_data <= sum_tmp + mul_g_buffer;
end
end
assign out_data = out_ready ? reg_out_data : 0;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == mul_delay + 2)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_ready = con_enable == mul_delay + 2 ? 1 : 0;
endgenerate
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode=0;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] mode_d1r;
reg [7:0] mode_d2r;
reg [7:0] mode_d3r;
// surefire lint_off ITENST
// surefire lint_off STMINI
// surefire lint_off NBAJAM
always @ (posedge clk) begin // filp-flops with asynchronous reset
if (0) begin
_mode <= 0;
end
else begin
_mode <= _mode + 1;
if (_mode==0) begin
$write("[%0t] t_blocking: Running\n", $time);
a <= 8'd0;
b <= 8'd0;
c <= 8'd0;
end
else if (_mode==1) begin
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd1;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==2) begin
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd2;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==3) begin
if (a !== 8'd1) $stop;
if (b !== 8'd2) $stop;
if (c !== 8'd1) $stop;
end
else if (_mode==4) begin
if (mode_d3r != 8'd1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
always @ (posedge clk) begin
mode_d3r <= mode_d2r;
mode_d2r <= mode_d1r;
mode_d1r <= _mode[7:0];
end
reg [14:10] bits;
// surefire lint_off SEQASS
always @ (posedge clk) begin
if (_mode==1) begin
bits[14:13] <= 2'b11;
bits[12] <= 1'b1;
end
if (_mode==2) begin
bits[11:10] <= 2'b10;
bits[13] <= 0;
end
if (_mode==3) begin
if (bits !== 5'b10110) $stop;
end
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_stat_counter;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] monitor_axis_tdata = 8'd0;
reg [7:0] monitor_axis_tkeep = 8'd0;
reg monitor_axis_tvalid = 1'b0;
reg monitor_axis_tready = 1'b0;
reg monitor_axis_tlast = 1'b0;
reg monitor_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
reg trigger = 0;
// Outputs
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tready,
tag,
trigger);
$to_myhdl(output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_stat_counter.lxt");
$dumpvars(0, test_axis_stat_counter);
end
axis_stat_counter #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// axi monitor input
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// configuration
.tag(tag),
.trigger(trigger),
// status
.busy(busy)
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_data_in (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. The only thing to
notice is that we are _not_ using the [asnum]/[aslist] trick that
we used in chapter [HoareList] to make all the operations total by
forcibly coercing the arguments to [+] (for example) into numbers.
Instead, we simply let terms get stuck if they try to use an
operator with the wrong kind of operands: the [step] relation
doesn't relate them to anything. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
Hint Unfold extend.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Theorem step_deterministic:
deterministic step.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true \in Bool
----------------- (T_False)
|- false \in Bool
|- t1 \in Bool |- t2 \in T |- t3 \in T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 \in T
------------ (T_Zero)
|- 0 \in Nat
|- t1 \in Nat
------------------ (T_Succ)
|- succ t1 \in Nat
|- t1 \in Nat
------------------ (T_Pred)
|- pred t1 \in Nat
|- t1 \in Nat
--------------------- (T_IsZero)
|- iszero t1 \in Bool
*)
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) \in TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue \in TBool).
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
|- tsucc t \in TNat ->
|- t \in TNat.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value". inversion H; clear H.
SSCase "t1 is a bvalue". inversion H0; clear H0.
SSSCase "t1 is ttrue".
exists t2...
SSSCase "t1 is tfalse".
exists t3...
SSCase "t1 is an nvalue".
solve by inversion 2. (* on H and HT1 *)
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t \in T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then it is either an [nvalue] or a
[bvalue]. But it cannot be an [nvalue], because we know
[|- t1 \in Bool] and there are no rules assigning type
[Bool] to any term that could be an [nvalue]. So [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* FILL IN HERE *)
[]
*)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
- Every value is a normal form.
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
- The single-step evaluation relation is a _total_ function.
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 \in T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 \in T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so,
by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 \in T], as required.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
|- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' \in T], then [|- t \in T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[]
*)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
(* FILL IN HERE *)
[] *)
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[]
*)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : arb_mux.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ns / 1 ps
module arb_mux #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
parameter nCS_PER_RANK = 1,
parameter nCNFG2WR = 2,
parameter nSLOTS = 2,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(/*AUTOARG*/
// Outputs
sent_row, sent_col, sending_row, io_config_valid_r, io_config,
dfi_we_n1, dfi_we_n0, dfi_ras_n1, dfi_ras_n0, dfi_odt_wr1,
dfi_odt_wr0, dfi_odt_nom1, dfi_odt_nom0, dfi_cs_n1, dfi_cs_n0,
dfi_cas_n1, dfi_cas_n0, dfi_bank1, dfi_bank0, dfi_address1,
dfi_address0, col_wr_data_buf_addr, col_size, col_row, col_rmw,
col_ra, col_periodic_rd, col_data_buf_addr, col_ba, col_a,
sending_col, io_config_strobe, insert_maint_r1,
// Inputs
slot_1_present, slot_0_present, rts_row, rts_col, rtc, row_cmd_wr,
row_addr, req_wr_r, req_size_r, req_row_r, req_ras, req_rank_r,
req_periodic_rd_r, req_data_buf_addr_r, req_cas, req_bank_r,
rd_wr_r, maint_zq_r, maint_rank_r, insert_maint_r,
force_io_config_rd_r, col_rdy_wr, col_addr, clk, rst
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [ROW_VECT_INDX:0] col_addr; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] col_rdy_wr; // To arb_row_col0 of arb_row_col.v
input force_io_config_rd_r; // To arb_row_col0 of arb_row_col.v
input insert_maint_r; // To arb_row_col0 of arb_row_col.v
input [RANK_WIDTH-1:0] maint_rank_r; // To arb_select0 of arb_select.v
input maint_zq_r; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rd_wr_r; // To arb_select0 of arb_select.v
input [BANK_VECT_INDX:0] req_bank_r; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_cas; // To arb_select0 of arb_select.v
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;// To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_periodic_rd_r; // To arb_select0 of arb_select.v
input [RANK_VECT_INDX:0] req_rank_r; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_ras; // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] req_row_r; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_size_r; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_wr_r; // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] row_addr; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] row_cmd_wr; // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rtc; // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_col; // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_row; // To arb_row_col0 of arb_row_col.v
input [7:0] slot_0_present; // To arb_select0 of arb_select.v
input [7:0] slot_1_present; // To arb_select0 of arb_select.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [ROW_WIDTH-1:0] col_a; // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] col_ba; // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;// From arb_select0 of arb_select.v
output col_periodic_rd; // From arb_select0 of arb_select.v
output [RANK_WIDTH-1:0] col_ra; // From arb_select0 of arb_select.v
output col_rmw; // From arb_select0 of arb_select.v
output [ROW_WIDTH-1:0] col_row; // From arb_select0 of arb_select.v
output col_size; // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;// From arb_select0 of arb_select.v
output [ROW_WIDTH-1:0] dfi_address0; // From arb_select0 of arb_select.v
output [ROW_WIDTH-1:0] dfi_address1; // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] dfi_bank0; // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] dfi_bank1; // From arb_select0 of arb_select.v
output dfi_cas_n0; // From arb_select0 of arb_select.v
output dfi_cas_n1; // From arb_select0 of arb_select.v
output [(CS_WIDTH*nCS_PER_RANK)-1:0] dfi_cs_n0;// From arb_select0 of arb_select.v
output [(CS_WIDTH*nCS_PER_RANK)-1:0] dfi_cs_n1;// From arb_select0 of arb_select.v
output [(nSLOTS*nCS_PER_RANK)-1:0] dfi_odt_nom0;// From arb_select0 of arb_select.v
output [(nSLOTS*nCS_PER_RANK)-1:0] dfi_odt_nom1;// From arb_select0 of arb_select.v
output [(nSLOTS*nCS_PER_RANK)-1:0] dfi_odt_wr0;// From arb_select0 of arb_select.v
output [(nSLOTS*nCS_PER_RANK)-1:0] dfi_odt_wr1;// From arb_select0 of arb_select.v
output dfi_ras_n0; // From arb_select0 of arb_select.v
output dfi_ras_n1; // From arb_select0 of arb_select.v
output dfi_we_n0; // From arb_select0 of arb_select.v
output dfi_we_n1; // From arb_select0 of arb_select.v
output [RANK_WIDTH:0] io_config; // From arb_select0 of arb_select.v
output io_config_valid_r; // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_row; // From arb_row_col0 of arb_row_col.v
output sent_col; // From arb_row_col0 of arb_row_col.v
output sent_row; // From arb_row_col0 of arb_row_col.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cs_en0; // From arb_row_col0 of arb_row_col.v
wire cs_en1; // From arb_row_col0 of arb_row_col.v
wire force_io_config_rd_r1; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
// End of automatics
input clk;
input rst;
output [nBANK_MACHS-1:0] sending_col;
output io_config_strobe;
output insert_maint_r1;
arb_row_col #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2WR (nCNFG2WR))
arb_row_col0
(/*AUTOINST*/
// Outputs
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.sent_row (sent_row),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.io_config_strobe (io_config_strobe),
.force_io_config_rd_r1 (force_io_config_rd_r1),
.io_config_valid_r (io_config_valid_r),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.clk (clk),
.rst (rst),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.rts_col (rts_col[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.force_io_config_rd_r (force_io_config_rd_r),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
arb_select #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nSLOTS (nSLOTS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_select0
(/*AUTOINST*/
// Outputs
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_size (col_size),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.dfi_bank0 (dfi_bank0[BANK_WIDTH-1:0]),
.dfi_address0 (dfi_address0[ROW_WIDTH-1:0]),
.dfi_ras_n0 (dfi_ras_n0),
.dfi_cas_n0 (dfi_cas_n0),
.dfi_we_n0 (dfi_we_n0),
.dfi_bank1 (dfi_bank1[BANK_WIDTH-1:0]),
.dfi_address1 (dfi_address1[ROW_WIDTH-1:0]),
.dfi_ras_n1 (dfi_ras_n1),
.dfi_cas_n1 (dfi_cas_n1),
.dfi_we_n1 (dfi_we_n1),
.dfi_cs_n0 (dfi_cs_n0[(CS_WIDTH*nCS_PER_RANK)-1:0]),
.dfi_cs_n1 (dfi_cs_n1[(CS_WIDTH*nCS_PER_RANK)-1:0]),
.io_config (io_config[RANK_WIDTH:0]),
.dfi_odt_nom0 (dfi_odt_nom0[(nSLOTS*nCS_PER_RANK)-1:0]),
.dfi_odt_wr0 (dfi_odt_wr0[(nSLOTS*nCS_PER_RANK)-1:0]),
.dfi_odt_nom1 (dfi_odt_nom1[(nSLOTS*nCS_PER_RANK)-1:0]),
.dfi_odt_wr1 (dfi_odt_wr1[(nSLOTS*nCS_PER_RANK)-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.force_io_config_rd_r1 (force_io_config_rd_r1),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.io_config_strobe (io_config_strobe),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD2_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYGATE4SD2_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD2_BLACKBOX_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
state = 0;
invalid_rd = 0;
end else begin
case (state)
0 : begin
state = 0;
invalid_rd = 0;
if(req)begin
state = 1;
invalid_rd = invalid_rd_req;
end
end
1 : begin
state = 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
state = 0;
invalid_rd = 0;
end
end
endcase
end
end
endmodule
|
module test1(
input wire clk,
input wire reset,
input wire enabled,
input wire in,
input wire Start,
input wire Stop,
output wire sda
);
reg start, done, data;
always@( negedge Start or reset )
begin
if(~reset)
begin
start <= 1'b0;
end
else
begin
if( enabled == 1 )
begin
start <= 1'b1;
end
else
begin
start <= 1'b0;
end
end
end
always@( posedge Stop or reset )
begin
if(~reset)
begin
done <= 1'b0;
end
else
begin
if( enabled == 1 )
begin
done <= 1'b1;
end
else
begin
done <= 1'b0;
end
end
end
always@( posedge clk )
begin
data <= in;
end
assign sda = ( enabled == 1 ) ? ( start == 1) ? (done== 0) ? data : 1'bz : 1'bz : 1'bz;
endmodule
module testbench1();
reg reset, clk, enable, in, Start, Stop;
wire sda;
test1 u1 ( clk, reset, enable, in, Start, Stop, sda );
always
begin
#5 clk = ~clk;
end
initial
begin
reset = 0;
clk = 1;
enable = 0;
in = 0;
Start = 0;
Stop = 0;
#20
reset = 1;
#40
Start = 1;
#20;
Start = 0;
#20
enable = 1;
#20
enable = 0;
#20
enable = 1;
Start = 1;
#20
Start = 0;
in = 0;
#20
in = 1;
#10
in = 0;
#10
in = 1;
#10
in = 0;
#10
in = 1;
#10
in = 0;
#10
in = 1;
#10
in = 0;
#10
in = 1;
Stop = 1;
#2
Stop = 0;
#50
$finish;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.1 Build 216 11/01/2011
///////////////////////////////////////////////////////////////////////////////
//
// MAX IO Atom
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module max_asynch_io (datain, oe, padio, dataout);
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter weak_pull_up = "false";
input datain, oe;
output dataout;
inout padio;
reg prev_value;
reg tmp_padio, tmp_dataout;
reg buf_control;
wire datain_in;
wire oe_in;
buf(datain_in, datain);
buf(oe_in, oe);
tri padio_tmp;
specify
(padio => dataout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
endspecify
initial
begin
prev_value = 'b1;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if (operation_mode == "input")
begin
prev_value = padio;
tmp_dataout = padio;
end
else if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in == 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // 'Z'
begin
if ( padio != 1'bz)
begin
prev_value = padio;
end
end
end // end open_drain_output , true
else
begin
tmp_padio = datain_in;
prev_value = datain_in;
end // end open_drain_output false
end // end oe_in == 1
else if ( oe_in == 0 )
begin
if ( padio !== 1'bz)
begin
prev_value = padio;
if ((padio === 1'bx) && (operation_mode == "output") && (padio_tmp === 1'bx) && (prev_value === 1'bx))
begin
prev_value = 'b0;
end
end
tmp_padio = 'bz;
end
else
begin
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end
if ( operation_mode == "bidir")
tmp_dataout = padio;
else
tmp_dataout = 1'bz;
if ( $realtime <= 1 )
prev_value = 0;
end
end
else // bus hold is false
if (bus_hold == "false")
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_dataout = padio;
if (weak_pull_up == "true")
begin
if (tmp_dataout === 1'bz)
tmp_dataout = 1'b1;
end
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
begin
tmp_dataout = padio;
if (weak_pull_up == "true")
begin
if (tmp_dataout === 1'bz)
tmp_dataout = 1'b1;
end
end
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in == 1'bx)
tmp_padio = 1'bx;
else
begin
tmp_padio = 1'bz;
if (weak_pull_up == "true")
begin
if (tmp_padio === 1'bz)
buf_control = 1;
end
end
end
else
begin
if ((datain_in !== 1'b1)&&(datain_in !== 1'b0)&&(datain_in !== 'bx))
tmp_padio = 'bz;
else
tmp_padio = datain_in;
if (weak_pull_up == "true")
begin
if (tmp_padio === 1'bz)
buf_control = 1;
end
end
end
else if ( oe_in == 0 )
begin
tmp_padio = 1'bz;
if (weak_pull_up == "true")
begin
if (tmp_padio === 1'bz)
begin
buf_control = 1;
end
end
end
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in max io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
end
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (dataout, tmp_dataout, 'b0);
pmos (padio, padio_tmp, 'b0);
endmodule
module max_io (datain, oe, padio, dataout);
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter weak_pull_up = "false";
inout padio;
input datain, oe;
output dataout;
max_asynch_io asynch_inst (datain, oe, padio, dataout);
defparam
asynch_inst.operation_mode = operation_mode,
asynch_inst.bus_hold = bus_hold,
asynch_inst.open_drain_output = open_drain_output,
asynch_inst.weak_pull_up = weak_pull_up;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// MAX MCELL ATOM
//
//////////////////////////////////////////////////////////////////////////////
// MAX MCELL ASYNCH
`timescale 1 ps/1 ps
module max_asynch_mcell (pterm0, pterm1, pterm2, pterm3, pterm4,
pterm5, fpin, pxor, pexpin, fbkin,
combout, pexpout, regin);
parameter operation_mode = "normal";
parameter pexp_mode = "off";
parameter register_mode = "dff";
input [51:0] pterm0, pterm1, pterm2, pterm3, pterm4, pterm5, pxor;
input pexpin, fbkin, fpin;
output combout, pexpout, regin;
reg icomb, ipexpout, tmp_comb, tmp_fpin;
reg tmp_pterm0, tmp_pterm1, tmp_pterm2;
reg tmp_pterm3, tmp_pterm4, tmp_pexpin;
wire [51:0] ipterm0, ipterm1, ipterm2, ipterm3, ipterm4, ipterm5, ipxor;
wire ipexpin;
wire ifpin;
buf (ipexpin, pexpin);
buf (ifpin, fpin);
buf (ipterm0[0], pterm0[0]);
buf (ipterm0[1], pterm0[1]);
buf (ipterm0[2], pterm0[2]);
buf (ipterm0[3], pterm0[3]);
buf (ipterm0[4], pterm0[4]);
buf (ipterm0[5], pterm0[5]);
buf (ipterm0[6], pterm0[6]);
buf (ipterm0[7], pterm0[7]);
buf (ipterm0[8], pterm0[8]);
buf (ipterm0[9], pterm0[9]);
buf (ipterm0[10], pterm0[10]);
buf (ipterm0[11], pterm0[11]);
buf (ipterm0[12], pterm0[12]);
buf (ipterm0[13], pterm0[13]);
buf (ipterm0[14], pterm0[14]);
buf (ipterm0[15], pterm0[15]);
buf (ipterm0[16], pterm0[16]);
buf (ipterm0[17], pterm0[17]);
buf (ipterm0[18], pterm0[18]);
buf (ipterm0[19], pterm0[19]);
buf (ipterm0[20], pterm0[20]);
buf (ipterm0[21], pterm0[21]);
buf (ipterm0[22], pterm0[22]);
buf (ipterm0[23], pterm0[23]);
buf (ipterm0[24], pterm0[24]);
buf (ipterm0[25], pterm0[25]);
buf (ipterm0[26], pterm0[26]);
buf (ipterm0[27], pterm0[27]);
buf (ipterm0[28], pterm0[28]);
buf (ipterm0[29], pterm0[29]);
buf (ipterm0[30], pterm0[30]);
buf (ipterm0[31], pterm0[31]);
buf (ipterm0[32], pterm0[32]);
buf (ipterm0[33], pterm0[33]);
buf (ipterm0[34], pterm0[34]);
buf (ipterm0[35], pterm0[35]);
buf (ipterm0[36], pterm0[36]);
buf (ipterm0[37], pterm0[37]);
buf (ipterm0[38], pterm0[38]);
buf (ipterm0[39], pterm0[39]);
buf (ipterm0[40], pterm0[40]);
buf (ipterm0[41], pterm0[41]);
buf (ipterm0[42], pterm0[42]);
buf (ipterm0[43], pterm0[43]);
buf (ipterm0[44], pterm0[44]);
buf (ipterm0[45], pterm0[45]);
buf (ipterm0[46], pterm0[46]);
buf (ipterm0[47], pterm0[47]);
buf (ipterm0[48], pterm0[48]);
buf (ipterm0[49], pterm0[49]);
buf (ipterm0[50], pterm0[50]);
buf (ipterm0[51], pterm0[51]);
buf (ipterm1[0], pterm1[0]);
buf (ipterm1[1], pterm1[1]);
buf (ipterm1[2], pterm1[2]);
buf (ipterm1[3], pterm1[3]);
buf (ipterm1[4], pterm1[4]);
buf (ipterm1[5], pterm1[5]);
buf (ipterm1[6], pterm1[6]);
buf (ipterm1[7], pterm1[7]);
buf (ipterm1[8], pterm1[8]);
buf (ipterm1[9], pterm1[9]);
buf (ipterm1[10], pterm1[10]);
buf (ipterm1[11], pterm1[11]);
buf (ipterm1[12], pterm1[12]);
buf (ipterm1[13], pterm1[13]);
buf (ipterm1[14], pterm1[14]);
buf (ipterm1[15], pterm1[15]);
buf (ipterm1[16], pterm1[16]);
buf (ipterm1[17], pterm1[17]);
buf (ipterm1[18], pterm1[18]);
buf (ipterm1[19], pterm1[19]);
buf (ipterm1[20], pterm1[20]);
buf (ipterm1[21], pterm1[21]);
buf (ipterm1[22], pterm1[22]);
buf (ipterm1[23], pterm1[23]);
buf (ipterm1[24], pterm1[24]);
buf (ipterm1[25], pterm1[25]);
buf (ipterm1[26], pterm1[26]);
buf (ipterm1[27], pterm1[27]);
buf (ipterm1[28], pterm1[28]);
buf (ipterm1[29], pterm1[29]);
buf (ipterm1[30], pterm1[30]);
buf (ipterm1[31], pterm1[31]);
buf (ipterm1[32], pterm1[32]);
buf (ipterm1[33], pterm1[33]);
buf (ipterm1[34], pterm1[34]);
buf (ipterm1[35], pterm1[35]);
buf (ipterm1[36], pterm1[36]);
buf (ipterm1[37], pterm1[37]);
buf (ipterm1[38], pterm1[38]);
buf (ipterm1[39], pterm1[39]);
buf (ipterm1[40], pterm1[40]);
buf (ipterm1[41], pterm1[41]);
buf (ipterm1[42], pterm1[42]);
buf (ipterm1[43], pterm1[43]);
buf (ipterm1[44], pterm1[44]);
buf (ipterm1[45], pterm1[45]);
buf (ipterm1[46], pterm1[46]);
buf (ipterm1[47], pterm1[47]);
buf (ipterm1[48], pterm1[48]);
buf (ipterm1[49], pterm1[49]);
buf (ipterm1[50], pterm1[50]);
buf (ipterm1[51], pterm1[51]);
buf (ipterm2[0], pterm2[0]);
buf (ipterm2[1], pterm2[1]);
buf (ipterm2[2], pterm2[2]);
buf (ipterm2[3], pterm2[3]);
buf (ipterm2[4], pterm2[4]);
buf (ipterm2[5], pterm2[5]);
buf (ipterm2[6], pterm2[6]);
buf (ipterm2[7], pterm2[7]);
buf (ipterm2[8], pterm2[8]);
buf (ipterm2[9], pterm2[9]);
buf (ipterm2[10], pterm2[10]);
buf (ipterm2[11], pterm2[11]);
buf (ipterm2[12], pterm2[12]);
buf (ipterm2[13], pterm2[13]);
buf (ipterm2[14], pterm2[14]);
buf (ipterm2[15], pterm2[15]);
buf (ipterm2[16], pterm2[16]);
buf (ipterm2[17], pterm2[17]);
buf (ipterm2[18], pterm2[18]);
buf (ipterm2[19], pterm2[19]);
buf (ipterm2[20], pterm2[20]);
buf (ipterm2[21], pterm2[21]);
buf (ipterm2[22], pterm2[22]);
buf (ipterm2[23], pterm2[23]);
buf (ipterm2[24], pterm2[24]);
buf (ipterm2[25], pterm2[25]);
buf (ipterm2[26], pterm2[26]);
buf (ipterm2[27], pterm2[27]);
buf (ipterm2[28], pterm2[28]);
buf (ipterm2[29], pterm2[29]);
buf (ipterm2[30], pterm2[30]);
buf (ipterm2[31], pterm2[31]);
buf (ipterm2[32], pterm2[32]);
buf (ipterm2[33], pterm2[33]);
buf (ipterm2[34], pterm2[34]);
buf (ipterm2[35], pterm2[35]);
buf (ipterm2[36], pterm2[36]);
buf (ipterm2[37], pterm2[37]);
buf (ipterm2[38], pterm2[38]);
buf (ipterm2[39], pterm2[39]);
buf (ipterm2[40], pterm2[40]);
buf (ipterm2[41], pterm2[41]);
buf (ipterm2[42], pterm2[42]);
buf (ipterm2[43], pterm2[43]);
buf (ipterm2[44], pterm2[44]);
buf (ipterm2[45], pterm2[45]);
buf (ipterm2[46], pterm2[46]);
buf (ipterm2[47], pterm2[47]);
buf (ipterm2[48], pterm2[48]);
buf (ipterm2[49], pterm2[49]);
buf (ipterm2[50], pterm2[50]);
buf (ipterm2[51], pterm2[51]);
buf (ipterm3[0], pterm3[0]);
buf (ipterm3[1], pterm3[1]);
buf (ipterm3[2], pterm3[2]);
buf (ipterm3[3], pterm3[3]);
buf (ipterm3[4], pterm3[4]);
buf (ipterm3[5], pterm3[5]);
buf (ipterm3[6], pterm3[6]);
buf (ipterm3[7], pterm3[7]);
buf (ipterm3[8], pterm3[8]);
buf (ipterm3[9], pterm3[9]);
buf (ipterm3[10], pterm3[10]);
buf (ipterm3[11], pterm3[11]);
buf (ipterm3[12], pterm3[12]);
buf (ipterm3[13], pterm3[13]);
buf (ipterm3[14], pterm3[14]);
buf (ipterm3[15], pterm3[15]);
buf (ipterm3[16], pterm3[16]);
buf (ipterm3[17], pterm3[17]);
buf (ipterm3[18], pterm3[18]);
buf (ipterm3[19], pterm3[19]);
buf (ipterm3[20], pterm3[20]);
buf (ipterm3[21], pterm3[21]);
buf (ipterm3[22], pterm3[22]);
buf (ipterm3[23], pterm3[23]);
buf (ipterm3[24], pterm3[24]);
buf (ipterm3[25], pterm3[25]);
buf (ipterm3[26], pterm3[26]);
buf (ipterm3[27], pterm3[27]);
buf (ipterm3[28], pterm3[28]);
buf (ipterm3[29], pterm3[29]);
buf (ipterm3[30], pterm3[30]);
buf (ipterm3[31], pterm3[31]);
buf (ipterm3[32], pterm3[32]);
buf (ipterm3[33], pterm3[33]);
buf (ipterm3[34], pterm3[34]);
buf (ipterm3[35], pterm3[35]);
buf (ipterm3[36], pterm3[36]);
buf (ipterm3[37], pterm3[37]);
buf (ipterm3[38], pterm3[38]);
buf (ipterm3[39], pterm3[39]);
buf (ipterm3[40], pterm3[40]);
buf (ipterm3[41], pterm3[41]);
buf (ipterm3[42], pterm3[42]);
buf (ipterm3[43], pterm3[43]);
buf (ipterm3[44], pterm3[44]);
buf (ipterm3[45], pterm3[45]);
buf (ipterm3[46], pterm3[46]);
buf (ipterm3[47], pterm3[47]);
buf (ipterm3[48], pterm3[48]);
buf (ipterm3[49], pterm3[49]);
buf (ipterm3[50], pterm3[50]);
buf (ipterm3[51], pterm3[51]);
buf (ipterm4[0], pterm4[0]);
buf (ipterm4[1], pterm4[1]);
buf (ipterm4[2], pterm4[2]);
buf (ipterm4[3], pterm4[3]);
buf (ipterm4[4], pterm4[4]);
buf (ipterm4[5], pterm4[5]);
buf (ipterm4[6], pterm4[6]);
buf (ipterm4[7], pterm4[7]);
buf (ipterm4[8], pterm4[8]);
buf (ipterm4[9], pterm4[9]);
buf (ipterm4[10], pterm4[10]);
buf (ipterm4[11], pterm4[11]);
buf (ipterm4[12], pterm4[12]);
buf (ipterm4[13], pterm4[13]);
buf (ipterm4[14], pterm4[14]);
buf (ipterm4[15], pterm4[15]);
buf (ipterm4[16], pterm4[16]);
buf (ipterm4[17], pterm4[17]);
buf (ipterm4[18], pterm4[18]);
buf (ipterm4[19], pterm4[19]);
buf (ipterm4[20], pterm4[20]);
buf (ipterm4[21], pterm4[21]);
buf (ipterm4[22], pterm4[22]);
buf (ipterm4[23], pterm4[23]);
buf (ipterm4[24], pterm4[24]);
buf (ipterm4[25], pterm4[25]);
buf (ipterm4[26], pterm4[26]);
buf (ipterm4[27], pterm4[27]);
buf (ipterm4[28], pterm4[28]);
buf (ipterm4[29], pterm4[29]);
buf (ipterm4[30], pterm4[30]);
buf (ipterm4[31], pterm4[31]);
buf (ipterm4[32], pterm4[32]);
buf (ipterm4[33], pterm4[33]);
buf (ipterm4[34], pterm4[34]);
buf (ipterm4[35], pterm4[35]);
buf (ipterm4[36], pterm4[36]);
buf (ipterm4[37], pterm4[37]);
buf (ipterm4[38], pterm4[38]);
buf (ipterm4[39], pterm4[39]);
buf (ipterm4[40], pterm4[40]);
buf (ipterm4[41], pterm4[41]);
buf (ipterm4[42], pterm4[42]);
buf (ipterm4[43], pterm4[43]);
buf (ipterm4[44], pterm4[44]);
buf (ipterm4[45], pterm4[45]);
buf (ipterm4[46], pterm4[46]);
buf (ipterm4[47], pterm4[47]);
buf (ipterm4[48], pterm4[48]);
buf (ipterm4[49], pterm4[49]);
buf (ipterm4[50], pterm4[50]);
buf (ipterm4[51], pterm4[51]);
buf (ipterm5[0], pterm5[0]);
buf (ipterm5[1], pterm5[1]);
buf (ipterm5[2], pterm5[2]);
buf (ipterm5[3], pterm5[3]);
buf (ipterm5[4], pterm5[4]);
buf (ipterm5[5], pterm5[5]);
buf (ipterm5[6], pterm5[6]);
buf (ipterm5[7], pterm5[7]);
buf (ipterm5[8], pterm5[8]);
buf (ipterm5[9], pterm5[9]);
buf (ipterm5[10], pterm5[10]);
buf (ipterm5[11], pterm5[11]);
buf (ipterm5[12], pterm5[12]);
buf (ipterm5[13], pterm5[13]);
buf (ipterm5[14], pterm5[14]);
buf (ipterm5[15], pterm5[15]);
buf (ipterm5[16], pterm5[16]);
buf (ipterm5[17], pterm5[17]);
buf (ipterm5[18], pterm5[18]);
buf (ipterm5[19], pterm5[19]);
buf (ipterm5[20], pterm5[20]);
buf (ipterm5[21], pterm5[21]);
buf (ipterm5[22], pterm5[22]);
buf (ipterm5[23], pterm5[23]);
buf (ipterm5[24], pterm5[24]);
buf (ipterm5[25], pterm5[25]);
buf (ipterm5[26], pterm5[26]);
buf (ipterm5[27], pterm5[27]);
buf (ipterm5[28], pterm5[28]);
buf (ipterm5[29], pterm5[29]);
buf (ipterm5[30], pterm5[30]);
buf (ipterm5[31], pterm5[31]);
buf (ipterm5[32], pterm5[32]);
buf (ipterm5[33], pterm5[33]);
buf (ipterm5[34], pterm5[34]);
buf (ipterm5[35], pterm5[35]);
buf (ipterm5[36], pterm5[36]);
buf (ipterm5[37], pterm5[37]);
buf (ipterm5[38], pterm5[38]);
buf (ipterm5[39], pterm5[39]);
buf (ipterm5[40], pterm5[40]);
buf (ipterm5[41], pterm5[41]);
buf (ipterm5[42], pterm5[42]);
buf (ipterm5[43], pterm5[43]);
buf (ipterm5[44], pterm5[44]);
buf (ipterm5[45], pterm5[45]);
buf (ipterm5[46], pterm5[46]);
buf (ipterm5[47], pterm5[47]);
buf (ipterm5[48], pterm5[48]);
buf (ipterm5[49], pterm5[49]);
buf (ipterm5[50], pterm5[50]);
buf (ipterm5[51], pterm5[51]);
buf (ipxor[0], pxor[0]);
buf (ipxor[1], pxor[1]);
buf (ipxor[2], pxor[2]);
buf (ipxor[3], pxor[3]);
buf (ipxor[4], pxor[4]);
buf (ipxor[5], pxor[5]);
buf (ipxor[6], pxor[6]);
buf (ipxor[7], pxor[7]);
buf (ipxor[8], pxor[8]);
buf (ipxor[9], pxor[9]);
buf (ipxor[10], pxor[10]);
buf (ipxor[11], pxor[11]);
buf (ipxor[12], pxor[12]);
buf (ipxor[13], pxor[13]);
buf (ipxor[14], pxor[14]);
buf (ipxor[15], pxor[15]);
buf (ipxor[16], pxor[16]);
buf (ipxor[17], pxor[17]);
buf (ipxor[18], pxor[18]);
buf (ipxor[19], pxor[19]);
buf (ipxor[20], pxor[20]);
buf (ipxor[21], pxor[21]);
buf (ipxor[22], pxor[22]);
buf (ipxor[23], pxor[23]);
buf (ipxor[24], pxor[24]);
buf (ipxor[25], pxor[25]);
buf (ipxor[26], pxor[26]);
buf (ipxor[27], pxor[27]);
buf (ipxor[28], pxor[28]);
buf (ipxor[29], pxor[29]);
buf (ipxor[30], pxor[30]);
buf (ipxor[31], pxor[31]);
buf (ipxor[32], pxor[32]);
buf (ipxor[33], pxor[33]);
buf (ipxor[34], pxor[34]);
buf (ipxor[35], pxor[35]);
buf (ipxor[36], pxor[36]);
buf (ipxor[37], pxor[37]);
buf (ipxor[38], pxor[38]);
buf (ipxor[39], pxor[39]);
buf (ipxor[40], pxor[40]);
buf (ipxor[41], pxor[41]);
buf (ipxor[42], pxor[42]);
buf (ipxor[43], pxor[43]);
buf (ipxor[44], pxor[44]);
buf (ipxor[45], pxor[45]);
buf (ipxor[46], pxor[46]);
buf (ipxor[47], pxor[47]);
buf (ipxor[48], pxor[48]);
buf (ipxor[49], pxor[49]);
buf (ipxor[50], pxor[50]);
buf (ipxor[51], pxor[51]);
specify
(pterm0[0] => combout) = (0, 0) ;
(pterm0[1] => combout) = (0, 0) ;
(pterm0[2] => combout) = (0, 0) ;
(pterm0[3] => combout) = (0, 0) ;
(pterm0[4] => combout) = (0, 0) ;
(pterm0[5] => combout) = (0, 0) ;
(pterm0[6] => combout) = (0, 0) ;
(pterm0[7] => combout) = (0, 0) ;
(pterm0[8] => combout) = (0, 0) ;
(pterm0[9] => combout) = (0, 0) ;
(pterm0[10] => combout) = (0, 0) ;
(pterm0[11] => combout) = (0, 0) ;
(pterm0[12] => combout) = (0, 0) ;
(pterm0[13] => combout) = (0, 0) ;
(pterm0[14] => combout) = (0, 0) ;
(pterm0[15] => combout) = (0, 0) ;
(pterm0[16] => combout) = (0, 0) ;
(pterm0[17] => combout) = (0, 0) ;
(pterm0[18] => combout) = (0, 0) ;
(pterm0[19] => combout) = (0, 0) ;
(pterm0[20] => combout) = (0, 0) ;
(pterm0[21] => combout) = (0, 0) ;
(pterm0[22] => combout) = (0, 0) ;
(pterm0[23] => combout) = (0, 0) ;
(pterm0[24] => combout) = (0, 0) ;
(pterm0[25] => combout) = (0, 0) ;
(pterm0[26] => combout) = (0, 0) ;
(pterm0[27] => combout) = (0, 0) ;
(pterm0[28] => combout) = (0, 0) ;
(pterm0[29] => combout) = (0, 0) ;
(pterm0[30] => combout) = (0, 0) ;
(pterm0[31] => combout) = (0, 0) ;
(pterm0[32] => combout) = (0, 0) ;
(pterm0[33] => combout) = (0, 0) ;
(pterm0[34] => combout) = (0, 0) ;
(pterm0[35] => combout) = (0, 0) ;
(pterm0[36] => combout) = (0, 0) ;
(pterm0[37] => combout) = (0, 0) ;
(pterm0[38] => combout) = (0, 0) ;
(pterm0[39] => combout) = (0, 0) ;
(pterm0[40] => combout) = (0, 0) ;
(pterm0[41] => combout) = (0, 0) ;
(pterm0[42] => combout) = (0, 0) ;
(pterm0[43] => combout) = (0, 0) ;
(pterm0[44] => combout) = (0, 0) ;
(pterm0[45] => combout) = (0, 0) ;
(pterm0[46] => combout) = (0, 0) ;
(pterm0[47] => combout) = (0, 0) ;
(pterm0[48] => combout) = (0, 0) ;
(pterm0[49] => combout) = (0, 0) ;
(pterm0[50] => combout) = (0, 0) ;
(pterm0[51] => combout) = (0, 0) ;
(pterm1[0] => combout) = (0, 0) ;
(pterm1[1] => combout) = (0, 0) ;
(pterm1[2] => combout) = (0, 0) ;
(pterm1[3] => combout) = (0, 0) ;
(pterm1[4] => combout) = (0, 0) ;
(pterm1[5] => combout) = (0, 0) ;
(pterm1[6] => combout) = (0, 0) ;
(pterm1[7] => combout) = (0, 0) ;
(pterm1[8] => combout) = (0, 0) ;
(pterm1[9] => combout) = (0, 0) ;
(pterm1[10] => combout) = (0, 0) ;
(pterm1[11] => combout) = (0, 0) ;
(pterm1[12] => combout) = (0, 0) ;
(pterm1[13] => combout) = (0, 0) ;
(pterm1[14] => combout) = (0, 0) ;
(pterm1[15] => combout) = (0, 0) ;
(pterm1[16] => combout) = (0, 0) ;
(pterm1[17] => combout) = (0, 0) ;
(pterm1[18] => combout) = (0, 0) ;
(pterm1[19] => combout) = (0, 0) ;
(pterm1[20] => combout) = (0, 0) ;
(pterm1[21] => combout) = (0, 0) ;
(pterm1[22] => combout) = (0, 0) ;
(pterm1[23] => combout) = (0, 0) ;
(pterm1[24] => combout) = (0, 0) ;
(pterm1[25] => combout) = (0, 0) ;
(pterm1[26] => combout) = (0, 0) ;
(pterm1[27] => combout) = (0, 0) ;
(pterm1[28] => combout) = (0, 0) ;
(pterm1[29] => combout) = (0, 0) ;
(pterm1[30] => combout) = (0, 0) ;
(pterm1[31] => combout) = (0, 0) ;
(pterm1[32] => combout) = (0, 0) ;
(pterm1[33] => combout) = (0, 0) ;
(pterm1[34] => combout) = (0, 0) ;
(pterm1[35] => combout) = (0, 0) ;
(pterm1[36] => combout) = (0, 0) ;
(pterm1[37] => combout) = (0, 0) ;
(pterm1[38] => combout) = (0, 0) ;
(pterm1[39] => combout) = (0, 0) ;
(pterm1[40] => combout) = (0, 0) ;
(pterm1[41] => combout) = (0, 0) ;
(pterm1[42] => combout) = (0, 0) ;
(pterm1[43] => combout) = (0, 0) ;
(pterm1[44] => combout) = (0, 0) ;
(pterm1[45] => combout) = (0, 0) ;
(pterm1[46] => combout) = (0, 0) ;
(pterm1[47] => combout) = (0, 0) ;
(pterm1[48] => combout) = (0, 0) ;
(pterm1[49] => combout) = (0, 0) ;
(pterm1[50] => combout) = (0, 0) ;
(pterm1[51] => combout) = (0, 0) ;
(pterm2[0] => combout) = (0, 0) ;
(pterm2[1] => combout) = (0, 0) ;
(pterm2[2] => combout) = (0, 0) ;
(pterm2[3] => combout) = (0, 0) ;
(pterm2[4] => combout) = (0, 0) ;
(pterm2[5] => combout) = (0, 0) ;
(pterm2[6] => combout) = (0, 0) ;
(pterm2[7] => combout) = (0, 0) ;
(pterm2[8] => combout) = (0, 0) ;
(pterm2[9] => combout) = (0, 0) ;
(pterm2[10] => combout) = (0, 0) ;
(pterm2[11] => combout) = (0, 0) ;
(pterm2[12] => combout) = (0, 0) ;
(pterm2[13] => combout) = (0, 0) ;
(pterm2[14] => combout) = (0, 0) ;
(pterm2[15] => combout) = (0, 0) ;
(pterm2[16] => combout) = (0, 0) ;
(pterm2[17] => combout) = (0, 0) ;
(pterm2[18] => combout) = (0, 0) ;
(pterm2[19] => combout) = (0, 0) ;
(pterm2[20] => combout) = (0, 0) ;
(pterm2[21] => combout) = (0, 0) ;
(pterm2[22] => combout) = (0, 0) ;
(pterm2[23] => combout) = (0, 0) ;
(pterm2[24] => combout) = (0, 0) ;
(pterm2[25] => combout) = (0, 0) ;
(pterm2[26] => combout) = (0, 0) ;
(pterm2[27] => combout) = (0, 0) ;
(pterm2[28] => combout) = (0, 0) ;
(pterm2[29] => combout) = (0, 0) ;
(pterm2[30] => combout) = (0, 0) ;
(pterm2[31] => combout) = (0, 0) ;
(pterm2[32] => combout) = (0, 0) ;
(pterm2[33] => combout) = (0, 0) ;
(pterm2[34] => combout) = (0, 0) ;
(pterm2[35] => combout) = (0, 0) ;
(pterm2[36] => combout) = (0, 0) ;
(pterm2[37] => combout) = (0, 0) ;
(pterm2[38] => combout) = (0, 0) ;
(pterm2[39] => combout) = (0, 0) ;
(pterm2[40] => combout) = (0, 0) ;
(pterm2[41] => combout) = (0, 0) ;
(pterm2[42] => combout) = (0, 0) ;
(pterm2[43] => combout) = (0, 0) ;
(pterm2[44] => combout) = (0, 0) ;
(pterm2[45] => combout) = (0, 0) ;
(pterm2[46] => combout) = (0, 0) ;
(pterm2[47] => combout) = (0, 0) ;
(pterm2[48] => combout) = (0, 0) ;
(pterm2[49] => combout) = (0, 0) ;
(pterm2[50] => combout) = (0, 0) ;
(pterm2[51] => combout) = (0, 0) ;
(pterm3[0] => combout) = (0, 0) ;
(pterm3[1] => combout) = (0, 0) ;
(pterm3[2] => combout) = (0, 0) ;
(pterm3[3] => combout) = (0, 0) ;
(pterm3[4] => combout) = (0, 0) ;
(pterm3[5] => combout) = (0, 0) ;
(pterm3[6] => combout) = (0, 0) ;
(pterm3[7] => combout) = (0, 0) ;
(pterm3[8] => combout) = (0, 0) ;
(pterm3[9] => combout) = (0, 0) ;
(pterm3[10] => combout) = (0, 0) ;
(pterm3[11] => combout) = (0, 0) ;
(pterm3[12] => combout) = (0, 0) ;
(pterm3[13] => combout) = (0, 0) ;
(pterm3[14] => combout) = (0, 0) ;
(pterm3[15] => combout) = (0, 0) ;
(pterm3[16] => combout) = (0, 0) ;
(pterm3[17] => combout) = (0, 0) ;
(pterm3[18] => combout) = (0, 0) ;
(pterm3[19] => combout) = (0, 0) ;
(pterm3[20] => combout) = (0, 0) ;
(pterm3[21] => combout) = (0, 0) ;
(pterm3[22] => combout) = (0, 0) ;
(pterm3[23] => combout) = (0, 0) ;
(pterm3[24] => combout) = (0, 0) ;
(pterm3[25] => combout) = (0, 0) ;
(pterm3[26] => combout) = (0, 0) ;
(pterm3[27] => combout) = (0, 0) ;
(pterm3[28] => combout) = (0, 0) ;
(pterm3[29] => combout) = (0, 0) ;
(pterm3[30] => combout) = (0, 0) ;
(pterm3[31] => combout) = (0, 0) ;
(pterm3[32] => combout) = (0, 0) ;
(pterm3[33] => combout) = (0, 0) ;
(pterm3[34] => combout) = (0, 0) ;
(pterm3[35] => combout) = (0, 0) ;
(pterm3[36] => combout) = (0, 0) ;
(pterm3[37] => combout) = (0, 0) ;
(pterm3[38] => combout) = (0, 0) ;
(pterm3[39] => combout) = (0, 0) ;
(pterm3[40] => combout) = (0, 0) ;
(pterm3[41] => combout) = (0, 0) ;
(pterm3[42] => combout) = (0, 0) ;
(pterm3[43] => combout) = (0, 0) ;
(pterm3[44] => combout) = (0, 0) ;
(pterm3[45] => combout) = (0, 0) ;
(pterm3[46] => combout) = (0, 0) ;
(pterm3[47] => combout) = (0, 0) ;
(pterm3[48] => combout) = (0, 0) ;
(pterm3[49] => combout) = (0, 0) ;
(pterm3[50] => combout) = (0, 0) ;
(pterm3[51] => combout) = (0, 0) ;
(pterm4[0] => combout) = (0, 0) ;
(pterm4[1] => combout) = (0, 0) ;
(pterm4[2] => combout) = (0, 0) ;
(pterm4[3] => combout) = (0, 0) ;
(pterm4[4] => combout) = (0, 0) ;
(pterm4[5] => combout) = (0, 0) ;
(pterm4[6] => combout) = (0, 0) ;
(pterm4[7] => combout) = (0, 0) ;
(pterm4[8] => combout) = (0, 0) ;
(pterm4[9] => combout) = (0, 0) ;
(pterm4[10] => combout) = (0, 0) ;
(pterm4[11] => combout) = (0, 0) ;
(pterm4[12] => combout) = (0, 0) ;
(pterm4[13] => combout) = (0, 0) ;
(pterm4[14] => combout) = (0, 0) ;
(pterm4[15] => combout) = (0, 0) ;
(pterm4[16] => combout) = (0, 0) ;
(pterm4[17] => combout) = (0, 0) ;
(pterm4[18] => combout) = (0, 0) ;
(pterm4[19] => combout) = (0, 0) ;
(pterm4[20] => combout) = (0, 0) ;
(pterm4[21] => combout) = (0, 0) ;
(pterm4[22] => combout) = (0, 0) ;
(pterm4[23] => combout) = (0, 0) ;
(pterm4[24] => combout) = (0, 0) ;
(pterm4[25] => combout) = (0, 0) ;
(pterm4[26] => combout) = (0, 0) ;
(pterm4[27] => combout) = (0, 0) ;
(pterm4[28] => combout) = (0, 0) ;
(pterm4[29] => combout) = (0, 0) ;
(pterm4[30] => combout) = (0, 0) ;
(pterm4[31] => combout) = (0, 0) ;
(pterm4[32] => combout) = (0, 0) ;
(pterm4[33] => combout) = (0, 0) ;
(pterm4[34] => combout) = (0, 0) ;
(pterm4[35] => combout) = (0, 0) ;
(pterm4[36] => combout) = (0, 0) ;
(pterm4[37] => combout) = (0, 0) ;
(pterm4[38] => combout) = (0, 0) ;
(pterm4[39] => combout) = (0, 0) ;
(pterm4[40] => combout) = (0, 0) ;
(pterm4[41] => combout) = (0, 0) ;
(pterm4[42] => combout) = (0, 0) ;
(pterm4[43] => combout) = (0, 0) ;
(pterm4[44] => combout) = (0, 0) ;
(pterm4[45] => combout) = (0, 0) ;
(pterm4[46] => combout) = (0, 0) ;
(pterm4[47] => combout) = (0, 0) ;
(pterm4[48] => combout) = (0, 0) ;
(pterm4[49] => combout) = (0, 0) ;
(pterm4[50] => combout) = (0, 0) ;
(pterm4[51] => combout) = (0, 0) ;
(pterm5[0] => combout) = (0, 0) ;
(pterm5[1] => combout) = (0, 0) ;
(pterm5[2] => combout) = (0, 0) ;
(pterm5[3] => combout) = (0, 0) ;
(pterm5[4] => combout) = (0, 0) ;
(pterm5[5] => combout) = (0, 0) ;
(pterm5[6] => combout) = (0, 0) ;
(pterm5[7] => combout) = (0, 0) ;
(pterm5[8] => combout) = (0, 0) ;
(pterm5[9] => combout) = (0, 0) ;
(pterm5[10] => combout) = (0, 0) ;
(pterm5[11] => combout) = (0, 0) ;
(pterm5[12] => combout) = (0, 0) ;
(pterm5[13] => combout) = (0, 0) ;
(pterm5[14] => combout) = (0, 0) ;
(pterm5[15] => combout) = (0, 0) ;
(pterm5[16] => combout) = (0, 0) ;
(pterm5[17] => combout) = (0, 0) ;
(pterm5[18] => combout) = (0, 0) ;
(pterm5[19] => combout) = (0, 0) ;
(pterm5[20] => combout) = (0, 0) ;
(pterm5[21] => combout) = (0, 0) ;
(pterm5[22] => combout) = (0, 0) ;
(pterm5[23] => combout) = (0, 0) ;
(pterm5[24] => combout) = (0, 0) ;
(pterm5[25] => combout) = (0, 0) ;
(pterm5[26] => combout) = (0, 0) ;
(pterm5[27] => combout) = (0, 0) ;
(pterm5[28] => combout) = (0, 0) ;
(pterm5[29] => combout) = (0, 0) ;
(pterm5[30] => combout) = (0, 0) ;
(pterm5[31] => combout) = (0, 0) ;
(pterm5[32] => combout) = (0, 0) ;
(pterm5[33] => combout) = (0, 0) ;
(pterm5[34] => combout) = (0, 0) ;
(pterm5[35] => combout) = (0, 0) ;
(pterm5[36] => combout) = (0, 0) ;
(pterm5[37] => combout) = (0, 0) ;
(pterm5[38] => combout) = (0, 0) ;
(pterm5[39] => combout) = (0, 0) ;
(pterm5[40] => combout) = (0, 0) ;
(pterm5[41] => combout) = (0, 0) ;
(pterm5[42] => combout) = (0, 0) ;
(pterm5[43] => combout) = (0, 0) ;
(pterm5[44] => combout) = (0, 0) ;
(pterm5[45] => combout) = (0, 0) ;
(pterm5[46] => combout) = (0, 0) ;
(pterm5[47] => combout) = (0, 0) ;
(pterm5[48] => combout) = (0, 0) ;
(pterm5[49] => combout) = (0, 0) ;
(pterm5[50] => combout) = (0, 0) ;
(pterm5[51] => combout) = (0, 0) ;
(pxor[0] => combout) = (0, 0) ;
(pxor[1] => combout) = (0, 0) ;
(pxor[2] => combout) = (0, 0) ;
(pxor[3] => combout) = (0, 0) ;
(pxor[4] => combout) = (0, 0) ;
(pxor[5] => combout) = (0, 0) ;
(pxor[6] => combout) = (0, 0) ;
(pxor[7] => combout) = (0, 0) ;
(pxor[8] => combout) = (0, 0) ;
(pxor[9] => combout) = (0, 0) ;
(pxor[10] => combout) = (0, 0) ;
(pxor[11] => combout) = (0, 0) ;
(pxor[12] => combout) = (0, 0) ;
(pxor[13] => combout) = (0, 0) ;
(pxor[14] => combout) = (0, 0) ;
(pxor[15] => combout) = (0, 0) ;
(pxor[16] => combout) = (0, 0) ;
(pxor[17] => combout) = (0, 0) ;
(pxor[18] => combout) = (0, 0) ;
(pxor[19] => combout) = (0, 0) ;
(pxor[20] => combout) = (0, 0) ;
(pxor[21] => combout) = (0, 0) ;
(pxor[22] => combout) = (0, 0) ;
(pxor[23] => combout) = (0, 0) ;
(pxor[24] => combout) = (0, 0) ;
(pxor[25] => combout) = (0, 0) ;
(pxor[26] => combout) = (0, 0) ;
(pxor[27] => combout) = (0, 0) ;
(pxor[28] => combout) = (0, 0) ;
(pxor[29] => combout) = (0, 0) ;
(pxor[30] => combout) = (0, 0) ;
(pxor[31] => combout) = (0, 0) ;
(pxor[32] => combout) = (0, 0) ;
(pxor[33] => combout) = (0, 0) ;
(pxor[34] => combout) = (0, 0) ;
(pxor[35] => combout) = (0, 0) ;
(pxor[36] => combout) = (0, 0) ;
(pxor[37] => combout) = (0, 0) ;
(pxor[38] => combout) = (0, 0) ;
(pxor[39] => combout) = (0, 0) ;
(pxor[40] => combout) = (0, 0) ;
(pxor[41] => combout) = (0, 0) ;
(pxor[42] => combout) = (0, 0) ;
(pxor[43] => combout) = (0, 0) ;
(pxor[44] => combout) = (0, 0) ;
(pxor[45] => combout) = (0, 0) ;
(pxor[46] => combout) = (0, 0) ;
(pxor[47] => combout) = (0, 0) ;
(pxor[48] => combout) = (0, 0) ;
(pxor[49] => combout) = (0, 0) ;
(pxor[50] => combout) = (0, 0) ;
(pxor[51] => combout) = (0, 0) ;
(pexpin => combout) = (0, 0) ;
(pterm0[0] => pexpout) = (0, 0) ;
(pterm0[1] => pexpout) = (0, 0) ;
(pterm0[2] => pexpout) = (0, 0) ;
(pterm0[3] => pexpout) = (0, 0) ;
(pterm0[4] => pexpout) = (0, 0) ;
(pterm0[5] => pexpout) = (0, 0) ;
(pterm0[6] => pexpout) = (0, 0) ;
(pterm0[7] => pexpout) = (0, 0) ;
(pterm0[8] => pexpout) = (0, 0) ;
(pterm0[9] => pexpout) = (0, 0) ;
(pterm0[10] => pexpout) = (0, 0) ;
(pterm0[11] => pexpout) = (0, 0) ;
(pterm0[12] => pexpout) = (0, 0) ;
(pterm0[13] => pexpout) = (0, 0) ;
(pterm0[14] => pexpout) = (0, 0) ;
(pterm0[15] => pexpout) = (0, 0) ;
(pterm0[16] => pexpout) = (0, 0) ;
(pterm0[17] => pexpout) = (0, 0) ;
(pterm0[18] => pexpout) = (0, 0) ;
(pterm0[19] => pexpout) = (0, 0) ;
(pterm0[20] => pexpout) = (0, 0) ;
(pterm0[21] => pexpout) = (0, 0) ;
(pterm0[22] => pexpout) = (0, 0) ;
(pterm0[23] => pexpout) = (0, 0) ;
(pterm0[24] => pexpout) = (0, 0) ;
(pterm0[25] => pexpout) = (0, 0) ;
(pterm0[26] => pexpout) = (0, 0) ;
(pterm0[27] => pexpout) = (0, 0) ;
(pterm0[28] => pexpout) = (0, 0) ;
(pterm0[29] => pexpout) = (0, 0) ;
(pterm0[30] => pexpout) = (0, 0) ;
(pterm0[31] => pexpout) = (0, 0) ;
(pterm0[32] => pexpout) = (0, 0) ;
(pterm0[33] => pexpout) = (0, 0) ;
(pterm0[34] => pexpout) = (0, 0) ;
(pterm0[35] => pexpout) = (0, 0) ;
(pterm0[36] => pexpout) = (0, 0) ;
(pterm0[37] => pexpout) = (0, 0) ;
(pterm0[38] => pexpout) = (0, 0) ;
(pterm0[39] => pexpout) = (0, 0) ;
(pterm0[40] => pexpout) = (0, 0) ;
(pterm0[41] => pexpout) = (0, 0) ;
(pterm0[42] => pexpout) = (0, 0) ;
(pterm0[43] => pexpout) = (0, 0) ;
(pterm0[44] => pexpout) = (0, 0) ;
(pterm0[45] => pexpout) = (0, 0) ;
(pterm0[46] => pexpout) = (0, 0) ;
(pterm0[47] => pexpout) = (0, 0) ;
(pterm0[48] => pexpout) = (0, 0) ;
(pterm0[49] => pexpout) = (0, 0) ;
(pterm0[50] => pexpout) = (0, 0) ;
(pterm0[51] => pexpout) = (0, 0) ;
(pterm1[0] => pexpout) = (0, 0) ;
(pterm1[1] => pexpout) = (0, 0) ;
(pterm1[2] => pexpout) = (0, 0) ;
(pterm1[3] => pexpout) = (0, 0) ;
(pterm1[4] => pexpout) = (0, 0) ;
(pterm1[5] => pexpout) = (0, 0) ;
(pterm1[6] => pexpout) = (0, 0) ;
(pterm1[7] => pexpout) = (0, 0) ;
(pterm1[8] => pexpout) = (0, 0) ;
(pterm1[9] => pexpout) = (0, 0) ;
(pterm1[10] => pexpout) = (0, 0) ;
(pterm1[11] => pexpout) = (0, 0) ;
(pterm1[12] => pexpout) = (0, 0) ;
(pterm1[13] => pexpout) = (0, 0) ;
(pterm1[14] => pexpout) = (0, 0) ;
(pterm1[15] => pexpout) = (0, 0) ;
(pterm1[16] => pexpout) = (0, 0) ;
(pterm1[17] => pexpout) = (0, 0) ;
(pterm1[18] => pexpout) = (0, 0) ;
(pterm1[19] => pexpout) = (0, 0) ;
(pterm1[20] => pexpout) = (0, 0) ;
(pterm1[21] => pexpout) = (0, 0) ;
(pterm1[22] => pexpout) = (0, 0) ;
(pterm1[23] => pexpout) = (0, 0) ;
(pterm1[24] => pexpout) = (0, 0) ;
(pterm1[25] => pexpout) = (0, 0) ;
(pterm1[26] => pexpout) = (0, 0) ;
(pterm1[27] => pexpout) = (0, 0) ;
(pterm1[28] => pexpout) = (0, 0) ;
(pterm1[29] => pexpout) = (0, 0) ;
(pterm1[30] => pexpout) = (0, 0) ;
(pterm1[31] => pexpout) = (0, 0) ;
(pterm1[32] => pexpout) = (0, 0) ;
(pterm1[33] => pexpout) = (0, 0) ;
(pterm1[34] => pexpout) = (0, 0) ;
(pterm1[35] => pexpout) = (0, 0) ;
(pterm1[36] => pexpout) = (0, 0) ;
(pterm1[37] => pexpout) = (0, 0) ;
(pterm1[38] => pexpout) = (0, 0) ;
(pterm1[39] => pexpout) = (0, 0) ;
(pterm1[40] => pexpout) = (0, 0) ;
(pterm1[41] => pexpout) = (0, 0) ;
(pterm1[42] => pexpout) = (0, 0) ;
(pterm1[43] => pexpout) = (0, 0) ;
(pterm1[44] => pexpout) = (0, 0) ;
(pterm1[45] => pexpout) = (0, 0) ;
(pterm1[46] => pexpout) = (0, 0) ;
(pterm1[47] => pexpout) = (0, 0) ;
(pterm1[48] => pexpout) = (0, 0) ;
(pterm1[49] => pexpout) = (0, 0) ;
(pterm1[50] => pexpout) = (0, 0) ;
(pterm1[51] => pexpout) = (0, 0) ;
(pterm2[0] => pexpout) = (0, 0) ;
(pterm2[1] => pexpout) = (0, 0) ;
(pterm2[2] => pexpout) = (0, 0) ;
(pterm2[3] => pexpout) = (0, 0) ;
(pterm2[4] => pexpout) = (0, 0) ;
(pterm2[5] => pexpout) = (0, 0) ;
(pterm2[6] => pexpout) = (0, 0) ;
(pterm2[7] => pexpout) = (0, 0) ;
(pterm2[8] => pexpout) = (0, 0) ;
(pterm2[9] => pexpout) = (0, 0) ;
(pterm2[10] => pexpout) = (0, 0) ;
(pterm2[11] => pexpout) = (0, 0) ;
(pterm2[12] => pexpout) = (0, 0) ;
(pterm2[13] => pexpout) = (0, 0) ;
(pterm2[14] => pexpout) = (0, 0) ;
(pterm2[15] => pexpout) = (0, 0) ;
(pterm2[16] => pexpout) = (0, 0) ;
(pterm2[17] => pexpout) = (0, 0) ;
(pterm2[18] => pexpout) = (0, 0) ;
(pterm2[19] => pexpout) = (0, 0) ;
(pterm2[20] => pexpout) = (0, 0) ;
(pterm2[21] => pexpout) = (0, 0) ;
(pterm2[22] => pexpout) = (0, 0) ;
(pterm2[23] => pexpout) = (0, 0) ;
(pterm2[24] => pexpout) = (0, 0) ;
(pterm2[25] => pexpout) = (0, 0) ;
(pterm2[26] => pexpout) = (0, 0) ;
(pterm2[27] => pexpout) = (0, 0) ;
(pterm2[28] => pexpout) = (0, 0) ;
(pterm2[29] => pexpout) = (0, 0) ;
(pterm2[30] => pexpout) = (0, 0) ;
(pterm2[31] => pexpout) = (0, 0) ;
(pterm2[32] => pexpout) = (0, 0) ;
(pterm2[33] => pexpout) = (0, 0) ;
(pterm2[34] => pexpout) = (0, 0) ;
(pterm2[35] => pexpout) = (0, 0) ;
(pterm2[36] => pexpout) = (0, 0) ;
(pterm2[37] => pexpout) = (0, 0) ;
(pterm2[38] => pexpout) = (0, 0) ;
(pterm2[39] => pexpout) = (0, 0) ;
(pterm2[40] => pexpout) = (0, 0) ;
(pterm2[41] => pexpout) = (0, 0) ;
(pterm2[42] => pexpout) = (0, 0) ;
(pterm2[43] => pexpout) = (0, 0) ;
(pterm2[44] => pexpout) = (0, 0) ;
(pterm2[45] => pexpout) = (0, 0) ;
(pterm2[46] => pexpout) = (0, 0) ;
(pterm2[47] => pexpout) = (0, 0) ;
(pterm2[48] => pexpout) = (0, 0) ;
(pterm2[49] => pexpout) = (0, 0) ;
(pterm2[50] => pexpout) = (0, 0) ;
(pterm2[51] => pexpout) = (0, 0) ;
(pterm3[0] => pexpout) = (0, 0) ;
(pterm3[1] => pexpout) = (0, 0) ;
(pterm3[2] => pexpout) = (0, 0) ;
(pterm3[3] => pexpout) = (0, 0) ;
(pterm3[4] => pexpout) = (0, 0) ;
(pterm3[5] => pexpout) = (0, 0) ;
(pterm3[6] => pexpout) = (0, 0) ;
(pterm3[7] => pexpout) = (0, 0) ;
(pterm3[8] => pexpout) = (0, 0) ;
(pterm3[9] => pexpout) = (0, 0) ;
(pterm3[10] => pexpout) = (0, 0) ;
(pterm3[11] => pexpout) = (0, 0) ;
(pterm3[12] => pexpout) = (0, 0) ;
(pterm3[13] => pexpout) = (0, 0) ;
(pterm3[14] => pexpout) = (0, 0) ;
(pterm3[15] => pexpout) = (0, 0) ;
(pterm3[16] => pexpout) = (0, 0) ;
(pterm3[17] => pexpout) = (0, 0) ;
(pterm3[18] => pexpout) = (0, 0) ;
(pterm3[19] => pexpout) = (0, 0) ;
(pterm3[20] => pexpout) = (0, 0) ;
(pterm3[21] => pexpout) = (0, 0) ;
(pterm3[22] => pexpout) = (0, 0) ;
(pterm3[23] => pexpout) = (0, 0) ;
(pterm3[24] => pexpout) = (0, 0) ;
(pterm3[25] => pexpout) = (0, 0) ;
(pterm3[26] => pexpout) = (0, 0) ;
(pterm3[27] => pexpout) = (0, 0) ;
(pterm3[28] => pexpout) = (0, 0) ;
(pterm3[29] => pexpout) = (0, 0) ;
(pterm3[30] => pexpout) = (0, 0) ;
(pterm3[31] => pexpout) = (0, 0) ;
(pterm3[32] => pexpout) = (0, 0) ;
(pterm3[33] => pexpout) = (0, 0) ;
(pterm3[34] => pexpout) = (0, 0) ;
(pterm3[35] => pexpout) = (0, 0) ;
(pterm3[36] => pexpout) = (0, 0) ;
(pterm3[37] => pexpout) = (0, 0) ;
(pterm3[38] => pexpout) = (0, 0) ;
(pterm3[39] => pexpout) = (0, 0) ;
(pterm3[40] => pexpout) = (0, 0) ;
(pterm3[41] => pexpout) = (0, 0) ;
(pterm3[42] => pexpout) = (0, 0) ;
(pterm3[43] => pexpout) = (0, 0) ;
(pterm3[44] => pexpout) = (0, 0) ;
(pterm3[45] => pexpout) = (0, 0) ;
(pterm3[46] => pexpout) = (0, 0) ;
(pterm3[47] => pexpout) = (0, 0) ;
(pterm3[48] => pexpout) = (0, 0) ;
(pterm3[49] => pexpout) = (0, 0) ;
(pterm3[50] => pexpout) = (0, 0) ;
(pterm3[51] => pexpout) = (0, 0) ;
(pterm4[0] => pexpout) = (0, 0) ;
(pterm4[1] => pexpout) = (0, 0) ;
(pterm4[2] => pexpout) = (0, 0) ;
(pterm4[3] => pexpout) = (0, 0) ;
(pterm4[4] => pexpout) = (0, 0) ;
(pterm4[5] => pexpout) = (0, 0) ;
(pterm4[6] => pexpout) = (0, 0) ;
(pterm4[7] => pexpout) = (0, 0) ;
(pterm4[8] => pexpout) = (0, 0) ;
(pterm4[9] => pexpout) = (0, 0) ;
(pterm4[10] => pexpout) = (0, 0) ;
(pterm4[11] => pexpout) = (0, 0) ;
(pterm4[12] => pexpout) = (0, 0) ;
(pterm4[13] => pexpout) = (0, 0) ;
(pterm4[14] => pexpout) = (0, 0) ;
(pterm4[15] => pexpout) = (0, 0) ;
(pterm4[16] => pexpout) = (0, 0) ;
(pterm4[17] => pexpout) = (0, 0) ;
(pterm4[18] => pexpout) = (0, 0) ;
(pterm4[19] => pexpout) = (0, 0) ;
(pterm4[20] => pexpout) = (0, 0) ;
(pterm4[21] => pexpout) = (0, 0) ;
(pterm4[22] => pexpout) = (0, 0) ;
(pterm4[23] => pexpout) = (0, 0) ;
(pterm4[24] => pexpout) = (0, 0) ;
(pterm4[25] => pexpout) = (0, 0) ;
(pterm4[26] => pexpout) = (0, 0) ;
(pterm4[27] => pexpout) = (0, 0) ;
(pterm4[28] => pexpout) = (0, 0) ;
(pterm4[29] => pexpout) = (0, 0) ;
(pterm4[30] => pexpout) = (0, 0) ;
(pterm4[31] => pexpout) = (0, 0) ;
(pterm4[32] => pexpout) = (0, 0) ;
(pterm4[33] => pexpout) = (0, 0) ;
(pterm4[34] => pexpout) = (0, 0) ;
(pterm4[35] => pexpout) = (0, 0) ;
(pterm4[36] => pexpout) = (0, 0) ;
(pterm4[37] => pexpout) = (0, 0) ;
(pterm4[38] => pexpout) = (0, 0) ;
(pterm4[39] => pexpout) = (0, 0) ;
(pterm4[40] => pexpout) = (0, 0) ;
(pterm4[41] => pexpout) = (0, 0) ;
(pterm4[42] => pexpout) = (0, 0) ;
(pterm4[43] => pexpout) = (0, 0) ;
(pterm4[44] => pexpout) = (0, 0) ;
(pterm4[45] => pexpout) = (0, 0) ;
(pterm4[46] => pexpout) = (0, 0) ;
(pterm4[47] => pexpout) = (0, 0) ;
(pterm4[48] => pexpout) = (0, 0) ;
(pterm4[49] => pexpout) = (0, 0) ;
(pterm4[50] => pexpout) = (0, 0) ;
(pterm4[51] => pexpout) = (0, 0) ;
(pterm5[0] => pexpout) = (0, 0) ;
(pterm5[1] => pexpout) = (0, 0) ;
(pterm5[2] => pexpout) = (0, 0) ;
(pterm5[3] => pexpout) = (0, 0) ;
(pterm5[4] => pexpout) = (0, 0) ;
(pterm5[5] => pexpout) = (0, 0) ;
(pterm5[6] => pexpout) = (0, 0) ;
(pterm5[7] => pexpout) = (0, 0) ;
(pterm5[8] => pexpout) = (0, 0) ;
(pterm5[9] => pexpout) = (0, 0) ;
(pterm5[10] => pexpout) = (0, 0) ;
(pterm5[11] => pexpout) = (0, 0) ;
(pterm5[12] => pexpout) = (0, 0) ;
(pterm5[13] => pexpout) = (0, 0) ;
(pterm5[14] => pexpout) = (0, 0) ;
(pterm5[15] => pexpout) = (0, 0) ;
(pterm5[16] => pexpout) = (0, 0) ;
(pterm5[17] => pexpout) = (0, 0) ;
(pterm5[18] => pexpout) = (0, 0) ;
(pterm5[19] => pexpout) = (0, 0) ;
(pterm5[20] => pexpout) = (0, 0) ;
(pterm5[21] => pexpout) = (0, 0) ;
(pterm5[22] => pexpout) = (0, 0) ;
(pterm5[23] => pexpout) = (0, 0) ;
(pterm5[24] => pexpout) = (0, 0) ;
(pterm5[25] => pexpout) = (0, 0) ;
(pterm5[26] => pexpout) = (0, 0) ;
(pterm5[27] => pexpout) = (0, 0) ;
(pterm5[28] => pexpout) = (0, 0) ;
(pterm5[29] => pexpout) = (0, 0) ;
(pterm5[30] => pexpout) = (0, 0) ;
(pterm5[31] => pexpout) = (0, 0) ;
(pterm5[32] => pexpout) = (0, 0) ;
(pterm5[33] => pexpout) = (0, 0) ;
(pterm5[34] => pexpout) = (0, 0) ;
(pterm5[35] => pexpout) = (0, 0) ;
(pterm5[36] => pexpout) = (0, 0) ;
(pterm5[37] => pexpout) = (0, 0) ;
(pterm5[38] => pexpout) = (0, 0) ;
(pterm5[39] => pexpout) = (0, 0) ;
(pterm5[40] => pexpout) = (0, 0) ;
(pterm5[41] => pexpout) = (0, 0) ;
(pterm5[42] => pexpout) = (0, 0) ;
(pterm5[43] => pexpout) = (0, 0) ;
(pterm5[44] => pexpout) = (0, 0) ;
(pterm5[45] => pexpout) = (0, 0) ;
(pterm5[46] => pexpout) = (0, 0) ;
(pterm5[47] => pexpout) = (0, 0) ;
(pterm5[48] => pexpout) = (0, 0) ;
(pterm5[49] => pexpout) = (0, 0) ;
(pterm5[50] => pexpout) = (0, 0) ;
(pterm5[51] => pexpout) = (0, 0) ;
(pexpin => pexpout) = (0, 0) ;
(pterm0[0] => regin) = (0, 0) ;
(pterm0[1] => regin) = (0, 0) ;
(pterm0[2] => regin) = (0, 0) ;
(pterm0[3] => regin) = (0, 0) ;
(pterm0[4] => regin) = (0, 0) ;
(pterm0[5] => regin) = (0, 0) ;
(pterm0[6] => regin) = (0, 0) ;
(pterm0[7] => regin) = (0, 0) ;
(pterm0[8] => regin) = (0, 0) ;
(pterm0[9] => regin) = (0, 0) ;
(pterm0[10] => regin) = (0, 0) ;
(pterm0[11] => regin) = (0, 0) ;
(pterm0[12] => regin) = (0, 0) ;
(pterm0[13] => regin) = (0, 0) ;
(pterm0[14] => regin) = (0, 0) ;
(pterm0[15] => regin) = (0, 0) ;
(pterm0[16] => regin) = (0, 0) ;
(pterm0[17] => regin) = (0, 0) ;
(pterm0[18] => regin) = (0, 0) ;
(pterm0[19] => regin) = (0, 0) ;
(pterm0[20] => regin) = (0, 0) ;
(pterm0[21] => regin) = (0, 0) ;
(pterm0[22] => regin) = (0, 0) ;
(pterm0[23] => regin) = (0, 0) ;
(pterm0[24] => regin) = (0, 0) ;
(pterm0[25] => regin) = (0, 0) ;
(pterm0[26] => regin) = (0, 0) ;
(pterm0[27] => regin) = (0, 0) ;
(pterm0[28] => regin) = (0, 0) ;
(pterm0[29] => regin) = (0, 0) ;
(pterm0[30] => regin) = (0, 0) ;
(pterm0[31] => regin) = (0, 0) ;
(pterm0[32] => regin) = (0, 0) ;
(pterm0[33] => regin) = (0, 0) ;
(pterm0[34] => regin) = (0, 0) ;
(pterm0[35] => regin) = (0, 0) ;
(pterm0[36] => regin) = (0, 0) ;
(pterm0[37] => regin) = (0, 0) ;
(pterm0[38] => regin) = (0, 0) ;
(pterm0[39] => regin) = (0, 0) ;
(pterm0[40] => regin) = (0, 0) ;
(pterm0[41] => regin) = (0, 0) ;
(pterm0[42] => regin) = (0, 0) ;
(pterm0[43] => regin) = (0, 0) ;
(pterm0[44] => regin) = (0, 0) ;
(pterm0[45] => regin) = (0, 0) ;
(pterm0[46] => regin) = (0, 0) ;
(pterm0[47] => regin) = (0, 0) ;
(pterm0[48] => regin) = (0, 0) ;
(pterm0[49] => regin) = (0, 0) ;
(pterm0[50] => regin) = (0, 0) ;
(pterm0[51] => regin) = (0, 0) ;
(pterm1[0] => regin) = (0, 0) ;
(pterm1[1] => regin) = (0, 0) ;
(pterm1[2] => regin) = (0, 0) ;
(pterm1[3] => regin) = (0, 0) ;
(pterm1[4] => regin) = (0, 0) ;
(pterm1[5] => regin) = (0, 0) ;
(pterm1[6] => regin) = (0, 0) ;
(pterm1[7] => regin) = (0, 0) ;
(pterm1[8] => regin) = (0, 0) ;
(pterm1[9] => regin) = (0, 0) ;
(pterm1[10] => regin) = (0, 0) ;
(pterm1[11] => regin) = (0, 0) ;
(pterm1[12] => regin) = (0, 0) ;
(pterm1[13] => regin) = (0, 0) ;
(pterm1[14] => regin) = (0, 0) ;
(pterm1[15] => regin) = (0, 0) ;
(pterm1[16] => regin) = (0, 0) ;
(pterm1[17] => regin) = (0, 0) ;
(pterm1[18] => regin) = (0, 0) ;
(pterm1[19] => regin) = (0, 0) ;
(pterm1[20] => regin) = (0, 0) ;
(pterm1[21] => regin) = (0, 0) ;
(pterm1[22] => regin) = (0, 0) ;
(pterm1[23] => regin) = (0, 0) ;
(pterm1[24] => regin) = (0, 0) ;
(pterm1[25] => regin) = (0, 0) ;
(pterm1[26] => regin) = (0, 0) ;
(pterm1[27] => regin) = (0, 0) ;
(pterm1[28] => regin) = (0, 0) ;
(pterm1[29] => regin) = (0, 0) ;
(pterm1[30] => regin) = (0, 0) ;
(pterm1[31] => regin) = (0, 0) ;
(pterm1[32] => regin) = (0, 0) ;
(pterm1[33] => regin) = (0, 0) ;
(pterm1[34] => regin) = (0, 0) ;
(pterm1[35] => regin) = (0, 0) ;
(pterm1[36] => regin) = (0, 0) ;
(pterm1[37] => regin) = (0, 0) ;
(pterm1[38] => regin) = (0, 0) ;
(pterm1[39] => regin) = (0, 0) ;
(pterm1[40] => regin) = (0, 0) ;
(pterm1[41] => regin) = (0, 0) ;
(pterm1[42] => regin) = (0, 0) ;
(pterm1[43] => regin) = (0, 0) ;
(pterm1[44] => regin) = (0, 0) ;
(pterm1[45] => regin) = (0, 0) ;
(pterm1[46] => regin) = (0, 0) ;
(pterm1[47] => regin) = (0, 0) ;
(pterm1[48] => regin) = (0, 0) ;
(pterm1[49] => regin) = (0, 0) ;
(pterm1[50] => regin) = (0, 0) ;
(pterm1[51] => regin) = (0, 0) ;
(pterm2[0] => regin) = (0, 0) ;
(pterm2[1] => regin) = (0, 0) ;
(pterm2[2] => regin) = (0, 0) ;
(pterm2[3] => regin) = (0, 0) ;
(pterm2[4] => regin) = (0, 0) ;
(pterm2[5] => regin) = (0, 0) ;
(pterm2[6] => regin) = (0, 0) ;
(pterm2[7] => regin) = (0, 0) ;
(pterm2[8] => regin) = (0, 0) ;
(pterm2[9] => regin) = (0, 0) ;
(pterm2[10] => regin) = (0, 0) ;
(pterm2[11] => regin) = (0, 0) ;
(pterm2[12] => regin) = (0, 0) ;
(pterm2[13] => regin) = (0, 0) ;
(pterm2[14] => regin) = (0, 0) ;
(pterm2[15] => regin) = (0, 0) ;
(pterm2[16] => regin) = (0, 0) ;
(pterm2[17] => regin) = (0, 0) ;
(pterm2[18] => regin) = (0, 0) ;
(pterm2[19] => regin) = (0, 0) ;
(pterm2[20] => regin) = (0, 0) ;
(pterm2[21] => regin) = (0, 0) ;
(pterm2[22] => regin) = (0, 0) ;
(pterm2[23] => regin) = (0, 0) ;
(pterm2[24] => regin) = (0, 0) ;
(pterm2[25] => regin) = (0, 0) ;
(pterm2[26] => regin) = (0, 0) ;
(pterm2[27] => regin) = (0, 0) ;
(pterm2[28] => regin) = (0, 0) ;
(pterm2[29] => regin) = (0, 0) ;
(pterm2[30] => regin) = (0, 0) ;
(pterm2[31] => regin) = (0, 0) ;
(pterm2[32] => regin) = (0, 0) ;
(pterm2[33] => regin) = (0, 0) ;
(pterm2[34] => regin) = (0, 0) ;
(pterm2[35] => regin) = (0, 0) ;
(pterm2[36] => regin) = (0, 0) ;
(pterm2[37] => regin) = (0, 0) ;
(pterm2[38] => regin) = (0, 0) ;
(pterm2[39] => regin) = (0, 0) ;
(pterm2[40] => regin) = (0, 0) ;
(pterm2[41] => regin) = (0, 0) ;
(pterm2[42] => regin) = (0, 0) ;
(pterm2[43] => regin) = (0, 0) ;
(pterm2[44] => regin) = (0, 0) ;
(pterm2[45] => regin) = (0, 0) ;
(pterm2[46] => regin) = (0, 0) ;
(pterm2[47] => regin) = (0, 0) ;
(pterm2[48] => regin) = (0, 0) ;
(pterm2[49] => regin) = (0, 0) ;
(pterm2[50] => regin) = (0, 0) ;
(pterm2[51] => regin) = (0, 0) ;
(pterm3[0] => regin) = (0, 0) ;
(pterm3[1] => regin) = (0, 0) ;
(pterm3[2] => regin) = (0, 0) ;
(pterm3[3] => regin) = (0, 0) ;
(pterm3[4] => regin) = (0, 0) ;
(pterm3[5] => regin) = (0, 0) ;
(pterm3[6] => regin) = (0, 0) ;
(pterm3[7] => regin) = (0, 0) ;
(pterm3[8] => regin) = (0, 0) ;
(pterm3[9] => regin) = (0, 0) ;
(pterm3[10] => regin) = (0, 0) ;
(pterm3[11] => regin) = (0, 0) ;
(pterm3[12] => regin) = (0, 0) ;
(pterm3[13] => regin) = (0, 0) ;
(pterm3[14] => regin) = (0, 0) ;
(pterm3[15] => regin) = (0, 0) ;
(pterm3[16] => regin) = (0, 0) ;
(pterm3[17] => regin) = (0, 0) ;
(pterm3[18] => regin) = (0, 0) ;
(pterm3[19] => regin) = (0, 0) ;
(pterm3[20] => regin) = (0, 0) ;
(pterm3[21] => regin) = (0, 0) ;
(pterm3[22] => regin) = (0, 0) ;
(pterm3[23] => regin) = (0, 0) ;
(pterm3[24] => regin) = (0, 0) ;
(pterm3[25] => regin) = (0, 0) ;
(pterm3[26] => regin) = (0, 0) ;
(pterm3[27] => regin) = (0, 0) ;
(pterm3[28] => regin) = (0, 0) ;
(pterm3[29] => regin) = (0, 0) ;
(pterm3[30] => regin) = (0, 0) ;
(pterm3[31] => regin) = (0, 0) ;
(pterm3[32] => regin) = (0, 0) ;
(pterm3[33] => regin) = (0, 0) ;
(pterm3[34] => regin) = (0, 0) ;
(pterm3[35] => regin) = (0, 0) ;
(pterm3[36] => regin) = (0, 0) ;
(pterm3[37] => regin) = (0, 0) ;
(pterm3[38] => regin) = (0, 0) ;
(pterm3[39] => regin) = (0, 0) ;
(pterm3[40] => regin) = (0, 0) ;
(pterm3[41] => regin) = (0, 0) ;
(pterm3[42] => regin) = (0, 0) ;
(pterm3[43] => regin) = (0, 0) ;
(pterm3[44] => regin) = (0, 0) ;
(pterm3[45] => regin) = (0, 0) ;
(pterm3[46] => regin) = (0, 0) ;
(pterm3[47] => regin) = (0, 0) ;
(pterm3[48] => regin) = (0, 0) ;
(pterm3[49] => regin) = (0, 0) ;
(pterm3[50] => regin) = (0, 0) ;
(pterm3[51] => regin) = (0, 0) ;
(pterm4[0] => regin) = (0, 0) ;
(pterm4[1] => regin) = (0, 0) ;
(pterm4[2] => regin) = (0, 0) ;
(pterm4[3] => regin) = (0, 0) ;
(pterm4[4] => regin) = (0, 0) ;
(pterm4[5] => regin) = (0, 0) ;
(pterm4[6] => regin) = (0, 0) ;
(pterm4[7] => regin) = (0, 0) ;
(pterm4[8] => regin) = (0, 0) ;
(pterm4[9] => regin) = (0, 0) ;
(pterm4[10] => regin) = (0, 0) ;
(pterm4[11] => regin) = (0, 0) ;
(pterm4[12] => regin) = (0, 0) ;
(pterm4[13] => regin) = (0, 0) ;
(pterm4[14] => regin) = (0, 0) ;
(pterm4[15] => regin) = (0, 0) ;
(pterm4[16] => regin) = (0, 0) ;
(pterm4[17] => regin) = (0, 0) ;
(pterm4[18] => regin) = (0, 0) ;
(pterm4[19] => regin) = (0, 0) ;
(pterm4[20] => regin) = (0, 0) ;
(pterm4[21] => regin) = (0, 0) ;
(pterm4[22] => regin) = (0, 0) ;
(pterm4[23] => regin) = (0, 0) ;
(pterm4[24] => regin) = (0, 0) ;
(pterm4[25] => regin) = (0, 0) ;
(pterm4[26] => regin) = (0, 0) ;
(pterm4[27] => regin) = (0, 0) ;
(pterm4[28] => regin) = (0, 0) ;
(pterm4[29] => regin) = (0, 0) ;
(pterm4[30] => regin) = (0, 0) ;
(pterm4[31] => regin) = (0, 0) ;
(pterm4[32] => regin) = (0, 0) ;
(pterm4[33] => regin) = (0, 0) ;
(pterm4[34] => regin) = (0, 0) ;
(pterm4[35] => regin) = (0, 0) ;
(pterm4[36] => regin) = (0, 0) ;
(pterm4[37] => regin) = (0, 0) ;
(pterm4[38] => regin) = (0, 0) ;
(pterm4[39] => regin) = (0, 0) ;
(pterm4[40] => regin) = (0, 0) ;
(pterm4[41] => regin) = (0, 0) ;
(pterm4[42] => regin) = (0, 0) ;
(pterm4[43] => regin) = (0, 0) ;
(pterm4[44] => regin) = (0, 0) ;
(pterm4[45] => regin) = (0, 0) ;
(pterm4[46] => regin) = (0, 0) ;
(pterm4[47] => regin) = (0, 0) ;
(pterm4[48] => regin) = (0, 0) ;
(pterm4[49] => regin) = (0, 0) ;
(pterm4[50] => regin) = (0, 0) ;
(pterm4[51] => regin) = (0, 0) ;
(pterm5[0] => regin) = (0, 0) ;
(pterm5[1] => regin) = (0, 0) ;
(pterm5[2] => regin) = (0, 0) ;
(pterm5[3] => regin) = (0, 0) ;
(pterm5[4] => regin) = (0, 0) ;
(pterm5[5] => regin) = (0, 0) ;
(pterm5[6] => regin) = (0, 0) ;
(pterm5[7] => regin) = (0, 0) ;
(pterm5[8] => regin) = (0, 0) ;
(pterm5[9] => regin) = (0, 0) ;
(pterm5[10] => regin) = (0, 0) ;
(pterm5[11] => regin) = (0, 0) ;
(pterm5[12] => regin) = (0, 0) ;
(pterm5[13] => regin) = (0, 0) ;
(pterm5[14] => regin) = (0, 0) ;
(pterm5[15] => regin) = (0, 0) ;
(pterm5[16] => regin) = (0, 0) ;
(pterm5[17] => regin) = (0, 0) ;
(pterm5[18] => regin) = (0, 0) ;
(pterm5[19] => regin) = (0, 0) ;
(pterm5[20] => regin) = (0, 0) ;
(pterm5[21] => regin) = (0, 0) ;
(pterm5[22] => regin) = (0, 0) ;
(pterm5[23] => regin) = (0, 0) ;
(pterm5[24] => regin) = (0, 0) ;
(pterm5[25] => regin) = (0, 0) ;
(pterm5[26] => regin) = (0, 0) ;
(pterm5[27] => regin) = (0, 0) ;
(pterm5[28] => regin) = (0, 0) ;
(pterm5[29] => regin) = (0, 0) ;
(pterm5[30] => regin) = (0, 0) ;
(pterm5[31] => regin) = (0, 0) ;
(pterm5[32] => regin) = (0, 0) ;
(pterm5[33] => regin) = (0, 0) ;
(pterm5[34] => regin) = (0, 0) ;
(pterm5[35] => regin) = (0, 0) ;
(pterm5[36] => regin) = (0, 0) ;
(pterm5[37] => regin) = (0, 0) ;
(pterm5[38] => regin) = (0, 0) ;
(pterm5[39] => regin) = (0, 0) ;
(pterm5[40] => regin) = (0, 0) ;
(pterm5[41] => regin) = (0, 0) ;
(pterm5[42] => regin) = (0, 0) ;
(pterm5[43] => regin) = (0, 0) ;
(pterm5[44] => regin) = (0, 0) ;
(pterm5[45] => regin) = (0, 0) ;
(pterm5[46] => regin) = (0, 0) ;
(pterm5[47] => regin) = (0, 0) ;
(pterm5[48] => regin) = (0, 0) ;
(pterm5[49] => regin) = (0, 0) ;
(pterm5[50] => regin) = (0, 0) ;
(pterm5[51] => regin) = (0, 0) ;
(pxor[0] => regin) = (0, 0) ;
(pxor[1] => regin) = (0, 0) ;
(pxor[2] => regin) = (0, 0) ;
(pxor[3] => regin) = (0, 0) ;
(pxor[4] => regin) = (0, 0) ;
(pxor[5] => regin) = (0, 0) ;
(pxor[6] => regin) = (0, 0) ;
(pxor[7] => regin) = (0, 0) ;
(pxor[8] => regin) = (0, 0) ;
(pxor[9] => regin) = (0, 0) ;
(pxor[10] => regin) = (0, 0) ;
(pxor[11] => regin) = (0, 0) ;
(pxor[12] => regin) = (0, 0) ;
(pxor[13] => regin) = (0, 0) ;
(pxor[14] => regin) = (0, 0) ;
(pxor[15] => regin) = (0, 0) ;
(pxor[16] => regin) = (0, 0) ;
(pxor[17] => regin) = (0, 0) ;
(pxor[18] => regin) = (0, 0) ;
(pxor[19] => regin) = (0, 0) ;
(pxor[20] => regin) = (0, 0) ;
(pxor[21] => regin) = (0, 0) ;
(pxor[22] => regin) = (0, 0) ;
(pxor[23] => regin) = (0, 0) ;
(pxor[24] => regin) = (0, 0) ;
(pxor[25] => regin) = (0, 0) ;
(pxor[26] => regin) = (0, 0) ;
(pxor[27] => regin) = (0, 0) ;
(pxor[28] => regin) = (0, 0) ;
(pxor[29] => regin) = (0, 0) ;
(pxor[30] => regin) = (0, 0) ;
(pxor[31] => regin) = (0, 0) ;
(pxor[32] => regin) = (0, 0) ;
(pxor[33] => regin) = (0, 0) ;
(pxor[34] => regin) = (0, 0) ;
(pxor[35] => regin) = (0, 0) ;
(pxor[36] => regin) = (0, 0) ;
(pxor[37] => regin) = (0, 0) ;
(pxor[38] => regin) = (0, 0) ;
(pxor[39] => regin) = (0, 0) ;
(pxor[40] => regin) = (0, 0) ;
(pxor[41] => regin) = (0, 0) ;
(pxor[42] => regin) = (0, 0) ;
(pxor[43] => regin) = (0, 0) ;
(pxor[44] => regin) = (0, 0) ;
(pxor[45] => regin) = (0, 0) ;
(pxor[46] => regin) = (0, 0) ;
(pxor[47] => regin) = (0, 0) ;
(pxor[48] => regin) = (0, 0) ;
(pxor[49] => regin) = (0, 0) ;
(pxor[50] => regin) = (0, 0) ;
(pxor[51] => regin) = (0, 0) ;
(pexpin => regin) = (0, 0) ;
(fpin => regin) = (0, 0);
(fbkin => regin) = (0, 0) ;
(fbkin => pexpout) = (0, 0) ;
(fbkin => combout) = (0, 0) ;
endspecify
always @ (ipterm0 or ipterm1 or ipterm2 or ipterm3
or ipterm4 or ipterm5 or ipxor or ipexpin or fbkin or ifpin)
begin
if (ifpin !== 'b0)
tmp_fpin = 'b1;
else
tmp_fpin = 'b0;
if (ipexpin !== 'b1)
tmp_pexpin = 'b0;
else
tmp_pexpin = 'b1;
if (&ipterm0 !== 'b1)
tmp_pterm0 = 'b0;
else
tmp_pterm0 = 'b1;
if (&ipterm1 !== 'b1)
tmp_pterm1 = 'b0;
else
tmp_pterm1 = 'b1;
if (&ipterm2 !== 'b1)
tmp_pterm2 = 'b0;
else
tmp_pterm2 = 'b1;
if (&ipterm3 !== 'b1)
tmp_pterm3 = 'b0;
else
tmp_pterm3 = 'b1;
if (&ipterm4 !== 'b1)
tmp_pterm4 = 'b0;
else
tmp_pterm4 = 'b1;
if (pexp_mode == "off")
begin
if (operation_mode == "normal")
begin
if (register_mode == "tff")
icomb = ((tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4) | tmp_pexpin) ^ fbkin;
else
icomb = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else if (operation_mode == "invert")
begin
if (register_mode == "tff")
icomb = ((tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin) ^ (~fbkin));
else
icomb = (tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin) ^ 'b1;
end
else if (operation_mode == "xor")
icomb = (tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin) ^ &ipxor;
else if (operation_mode == "vcc")
begin
if (register_mode == "tff")
icomb = 1'b1 ^ fbkin;
else
icomb = tmp_fpin;
end
else
icomb = 'bz;
end
else //pexp_mode = on
begin
if (operation_mode == "normal")
begin
if (register_mode == "tff")
icomb = &ipterm5 ^ fbkin;
else
icomb = &ipterm5;
ipexpout = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else if (operation_mode == "invert")
begin
if (register_mode == "tff")
icomb = &ipterm5 ^ (~fbkin);
else
icomb = &ipterm5 ^ 'b1;
ipexpout = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else if (operation_mode == "xor")
begin
ipexpout = (tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin);
icomb = &ipterm5 ^ &ipxor;
end
else if (operation_mode == "vcc")
begin
if (register_mode == "tff")
icomb = 1'b1 ^ fbkin;
else
icomb = tmp_fpin;
ipexpout = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else
begin
icomb = 'bz;
ipexpout = 'bz;
end
end
end
and (pexpout, ipexpout, 'b1);
and (combout, icomb, 'b1);
and (regin, icomb, 'b1);
endmodule
// MAX MCELL REG
`timescale 1 ps/1 ps
module max_mcell_register (datain, clk, aclr, pclk, pena, paclr,
papre, regout, fbkout);
parameter operation_mode = "normal";
parameter power_up = "low";
parameter register_mode = "dff";
input datain, clk, aclr;
input [51:0] pclk, pena, paclr, papre;
output regout, fbkout;
reg iregout, oldclk1, oldclk2;
reg pena_viol, clk_per_viol, datain_viol, pclk_per_viol;
reg pterm_aclr, pterm_preset, ptermclk, penable;
wire reset;
wire [51:0] ipclk, ipena, ipaclr, ipapre;
reg violation;
wire clk_in;
wire iclr;
buf (clk_in, clk);
buf (iclr, aclr);
buf (ipclk[0], pclk[0]);
buf (ipclk[1], pclk[1]);
buf (ipclk[2], pclk[2]);
buf (ipclk[3], pclk[3]);
buf (ipclk[4], pclk[4]);
buf (ipclk[5], pclk[5]);
buf (ipclk[6], pclk[6]);
buf (ipclk[7], pclk[7]);
buf (ipclk[8], pclk[8]);
buf (ipclk[9], pclk[9]);
buf (ipclk[10], pclk[10]);
buf (ipclk[11], pclk[11]);
buf (ipclk[12], pclk[12]);
buf (ipclk[13], pclk[13]);
buf (ipclk[14], pclk[14]);
buf (ipclk[15], pclk[15]);
buf (ipclk[16], pclk[16]);
buf (ipclk[17], pclk[17]);
buf (ipclk[18], pclk[18]);
buf (ipclk[19], pclk[19]);
buf (ipclk[20], pclk[20]);
buf (ipclk[21], pclk[21]);
buf (ipclk[22], pclk[22]);
buf (ipclk[23], pclk[23]);
buf (ipclk[24], pclk[24]);
buf (ipclk[25], pclk[25]);
buf (ipclk[26], pclk[26]);
buf (ipclk[27], pclk[27]);
buf (ipclk[28], pclk[28]);
buf (ipclk[29], pclk[29]);
buf (ipclk[30], pclk[30]);
buf (ipclk[31], pclk[31]);
buf (ipclk[32], pclk[32]);
buf (ipclk[33], pclk[33]);
buf (ipclk[34], pclk[34]);
buf (ipclk[35], pclk[35]);
buf (ipclk[36], pclk[36]);
buf (ipclk[37], pclk[37]);
buf (ipclk[38], pclk[38]);
buf (ipclk[39], pclk[39]);
buf (ipclk[40], pclk[40]);
buf (ipclk[41], pclk[41]);
buf (ipclk[42], pclk[42]);
buf (ipclk[43], pclk[43]);
buf (ipclk[44], pclk[44]);
buf (ipclk[45], pclk[45]);
buf (ipclk[46], pclk[46]);
buf (ipclk[47], pclk[47]);
buf (ipclk[48], pclk[48]);
buf (ipclk[49], pclk[49]);
buf (ipclk[50], pclk[50]);
buf (ipclk[51], pclk[51]);
buf (ipena[0], pena[0]);
buf (ipena[1], pena[1]);
buf (ipena[2], pena[2]);
buf (ipena[3], pena[3]);
buf (ipena[4], pena[4]);
buf (ipena[5], pena[5]);
buf (ipena[6], pena[6]);
buf (ipena[7], pena[7]);
buf (ipena[8], pena[8]);
buf (ipena[9], pena[9]);
buf (ipena[10], pena[10]);
buf (ipena[11], pena[11]);
buf (ipena[12], pena[12]);
buf (ipena[13], pena[13]);
buf (ipena[14], pena[14]);
buf (ipena[15], pena[15]);
buf (ipena[16], pena[16]);
buf (ipena[17], pena[17]);
buf (ipena[18], pena[18]);
buf (ipena[19], pena[19]);
buf (ipena[20], pena[20]);
buf (ipena[21], pena[21]);
buf (ipena[22], pena[22]);
buf (ipena[23], pena[23]);
buf (ipena[24], pena[24]);
buf (ipena[25], pena[25]);
buf (ipena[26], pena[26]);
buf (ipena[27], pena[27]);
buf (ipena[28], pena[28]);
buf (ipena[29], pena[29]);
buf (ipena[30], pena[30]);
buf (ipena[31], pena[31]);
buf (ipena[32], pena[32]);
buf (ipena[33], pena[33]);
buf (ipena[34], pena[34]);
buf (ipena[35], pena[35]);
buf (ipena[36], pena[36]);
buf (ipena[37], pena[37]);
buf (ipena[38], pena[38]);
buf (ipena[39], pena[39]);
buf (ipena[40], pena[40]);
buf (ipena[41], pena[41]);
buf (ipena[42], pena[42]);
buf (ipena[43], pena[43]);
buf (ipena[44], pena[44]);
buf (ipena[45], pena[45]);
buf (ipena[46], pena[46]);
buf (ipena[47], pena[47]);
buf (ipena[48], pena[48]);
buf (ipena[49], pena[49]);
buf (ipena[50], pena[50]);
buf (ipena[51], pena[51]);
buf (ipaclr[0], paclr[0]);
buf (ipaclr[1], paclr[1]);
buf (ipaclr[2], paclr[2]);
buf (ipaclr[3], paclr[3]);
buf (ipaclr[4], paclr[4]);
buf (ipaclr[5], paclr[5]);
buf (ipaclr[6], paclr[6]);
buf (ipaclr[7], paclr[7]);
buf (ipaclr[8], paclr[8]);
buf (ipaclr[9], paclr[9]);
buf (ipaclr[10], paclr[10]);
buf (ipaclr[11], paclr[11]);
buf (ipaclr[12], paclr[12]);
buf (ipaclr[13], paclr[13]);
buf (ipaclr[14], paclr[14]);
buf (ipaclr[15], paclr[15]);
buf (ipaclr[16], paclr[16]);
buf (ipaclr[17], paclr[17]);
buf (ipaclr[18], paclr[18]);
buf (ipaclr[19], paclr[19]);
buf (ipaclr[20], paclr[20]);
buf (ipaclr[21], paclr[21]);
buf (ipaclr[22], paclr[22]);
buf (ipaclr[23], paclr[23]);
buf (ipaclr[24], paclr[24]);
buf (ipaclr[25], paclr[25]);
buf (ipaclr[26], paclr[26]);
buf (ipaclr[27], paclr[27]);
buf (ipaclr[28], paclr[28]);
buf (ipaclr[29], paclr[29]);
buf (ipaclr[30], paclr[30]);
buf (ipaclr[31], paclr[31]);
buf (ipaclr[32], paclr[32]);
buf (ipaclr[33], paclr[33]);
buf (ipaclr[34], paclr[34]);
buf (ipaclr[35], paclr[35]);
buf (ipaclr[36], paclr[36]);
buf (ipaclr[37], paclr[37]);
buf (ipaclr[38], paclr[38]);
buf (ipaclr[39], paclr[39]);
buf (ipaclr[40], paclr[40]);
buf (ipaclr[41], paclr[41]);
buf (ipaclr[42], paclr[42]);
buf (ipaclr[43], paclr[43]);
buf (ipaclr[44], paclr[44]);
buf (ipaclr[45], paclr[45]);
buf (ipaclr[46], paclr[46]);
buf (ipaclr[47], paclr[47]);
buf (ipaclr[48], paclr[48]);
buf (ipaclr[49], paclr[49]);
buf (ipaclr[50], paclr[50]);
buf (ipaclr[51], paclr[51]);
buf (ipapre[0], papre[0]);
buf (ipapre[1], papre[1]);
buf (ipapre[2], papre[2]);
buf (ipapre[3], papre[3]);
buf (ipapre[4], papre[4]);
buf (ipapre[5], papre[5]);
buf (ipapre[6], papre[6]);
buf (ipapre[7], papre[7]);
buf (ipapre[8], papre[8]);
buf (ipapre[9], papre[9]);
buf (ipapre[10], papre[10]);
buf (ipapre[11], papre[11]);
buf (ipapre[12], papre[12]);
buf (ipapre[13], papre[13]);
buf (ipapre[14], papre[14]);
buf (ipapre[15], papre[15]);
buf (ipapre[16], papre[16]);
buf (ipapre[17], papre[17]);
buf (ipapre[18], papre[18]);
buf (ipapre[19], papre[19]);
buf (ipapre[20], papre[20]);
buf (ipapre[21], papre[21]);
buf (ipapre[22], papre[22]);
buf (ipapre[23], papre[23]);
buf (ipapre[24], papre[24]);
buf (ipapre[25], papre[25]);
buf (ipapre[26], papre[26]);
buf (ipapre[27], papre[27]);
buf (ipapre[28], papre[28]);
buf (ipapre[29], papre[29]);
buf (ipapre[30], papre[30]);
buf (ipapre[31], papre[31]);
buf (ipapre[32], papre[32]);
buf (ipapre[33], papre[33]);
buf (ipapre[34], papre[34]);
buf (ipapre[35], papre[35]);
buf (ipapre[36], papre[36]);
buf (ipapre[37], papre[37]);
buf (ipapre[38], papre[38]);
buf (ipapre[39], papre[39]);
buf (ipapre[40], papre[40]);
buf (ipapre[41], papre[41]);
buf (ipapre[42], papre[42]);
buf (ipapre[43], papre[43]);
buf (ipapre[44], papre[44]);
buf (ipapre[45], papre[45]);
buf (ipapre[46], papre[46]);
buf (ipapre[47], papre[47]);
buf (ipapre[48], papre[48]);
buf (ipapre[49], papre[49]);
buf (ipapre[50], papre[50]);
buf (ipapre[51], papre[51]);
assign reset = (!iclr) && (&ipena);
specify
$period (posedge clk &&& reset, 0, clk_per_viol);
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, pena[0], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[1], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[2], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[3], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[4], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[5], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[6], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[7], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[8], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[9], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[10], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[11], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[12], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[13], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[14], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[15], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[16], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[17], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[18], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[19], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[20], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[21], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[22], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[23], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[24], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[25], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[26], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[27], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[28], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[29], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[30], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[31], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[32], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[33], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[34], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[35], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[36], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[37], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[38], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[39], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[40], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[41], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[42], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[43], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[44], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[45], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[46], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[47], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[48], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[49], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[50], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[51], 0, 0, pena_viol) ;
$setuphold (posedge pclk[0] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[1] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[2] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[3] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[4] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[5] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[6] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[7] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[8] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[9] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[10] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[11] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[12] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[13] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[14] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[15] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[16] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[17] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[18] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[19] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[20] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[21] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[22] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[23] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[24] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[25] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[26] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[27] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[28] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[29] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[30] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[31] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[32] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[33] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[34] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[35] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[36] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[37] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[38] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[39] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[40] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[41] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[42] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[43] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[44] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[45] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[46] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[47] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[48] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[49] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[50] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[51] &&& reset, datain, 0, 0, datain_viol) ;
(posedge clk => (regout +: datain)) = 0 ;
(posedge pclk[0] => (regout +: datain)) = (0, 0) ;
(posedge pclk[1] => (regout +: datain)) = (0, 0) ;
(posedge pclk[2] => (regout +: datain)) = (0, 0) ;
(posedge pclk[3] => (regout +: datain)) = (0, 0) ;
(posedge pclk[4] => (regout +: datain)) = (0, 0) ;
(posedge pclk[5] => (regout +: datain)) = (0, 0) ;
(posedge pclk[6] => (regout +: datain)) = (0, 0) ;
(posedge pclk[7] => (regout +: datain)) = (0, 0) ;
(posedge pclk[8] => (regout +: datain)) = (0, 0) ;
(posedge pclk[9] => (regout +: datain)) = (0, 0) ;
(posedge pclk[10] => (regout +: datain)) = (0, 0) ;
(posedge pclk[11] => (regout +: datain)) = (0, 0) ;
(posedge pclk[12] => (regout +: datain)) = (0, 0) ;
(posedge pclk[13] => (regout +: datain)) = (0, 0) ;
(posedge pclk[14] => (regout +: datain)) = (0, 0) ;
(posedge pclk[15] => (regout +: datain)) = (0, 0) ;
(posedge pclk[16] => (regout +: datain)) = (0, 0) ;
(posedge pclk[17] => (regout +: datain)) = (0, 0) ;
(posedge pclk[18] => (regout +: datain)) = (0, 0) ;
(posedge pclk[19] => (regout +: datain)) = (0, 0) ;
(posedge pclk[20] => (regout +: datain)) = (0, 0) ;
(posedge pclk[21] => (regout +: datain)) = (0, 0) ;
(posedge pclk[22] => (regout +: datain)) = (0, 0) ;
(posedge pclk[23] => (regout +: datain)) = (0, 0) ;
(posedge pclk[24] => (regout +: datain)) = (0, 0) ;
(posedge pclk[25] => (regout +: datain)) = (0, 0) ;
(posedge pclk[26] => (regout +: datain)) = (0, 0) ;
(posedge pclk[27] => (regout +: datain)) = (0, 0) ;
(posedge pclk[28] => (regout +: datain)) = (0, 0) ;
(posedge pclk[29] => (regout +: datain)) = (0, 0) ;
(posedge pclk[30] => (regout +: datain)) = (0, 0) ;
(posedge pclk[31] => (regout +: datain)) = (0, 0) ;
(posedge pclk[32] => (regout +: datain)) = (0, 0) ;
(posedge pclk[33] => (regout +: datain)) = (0, 0) ;
(posedge pclk[34] => (regout +: datain)) = (0, 0) ;
(posedge pclk[35] => (regout +: datain)) = (0, 0) ;
(posedge pclk[36] => (regout +: datain)) = (0, 0) ;
(posedge pclk[37] => (regout +: datain)) = (0, 0) ;
(posedge pclk[38] => (regout +: datain)) = (0, 0) ;
(posedge pclk[39] => (regout +: datain)) = (0, 0) ;
(posedge pclk[40] => (regout +: datain)) = (0, 0) ;
(posedge pclk[41] => (regout +: datain)) = (0, 0) ;
(posedge pclk[42] => (regout +: datain)) = (0, 0) ;
(posedge pclk[43] => (regout +: datain)) = (0, 0) ;
(posedge pclk[44] => (regout +: datain)) = (0, 0) ;
(posedge pclk[45] => (regout +: datain)) = (0, 0) ;
(posedge pclk[46] => (regout +: datain)) = (0, 0) ;
(posedge pclk[47] => (regout +: datain)) = (0, 0) ;
(posedge pclk[48] => (regout +: datain)) = (0, 0) ;
(posedge pclk[49] => (regout +: datain)) = (0, 0) ;
(posedge pclk[50] => (regout +: datain)) = (0, 0) ;
(posedge pclk[51] => (regout +: datain)) = (0, 0) ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[0] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[1] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[2] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[3] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[4] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[5] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[6] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[7] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[8] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[9] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[10] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[11] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[12] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[13] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[14] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[15] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[16] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[17] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[18] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[19] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[20] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[21] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[22] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[23] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[24] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[25] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[26] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[27] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[28] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[29] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[30] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[31] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[32] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[33] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[34] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[35] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[36] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[37] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[38] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[39] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[40] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[41] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[42] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[43] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[44] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[45] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[46] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[47] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[48] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[49] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[50] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[51] => (regout +: 1'b0)) = (0, 0) ;
(posedge papre[0] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[1] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[2] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[3] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[4] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[5] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[6] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[7] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[8] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[9] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[10] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[11] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[12] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[13] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[14] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[15] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[16] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[17] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[18] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[19] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[20] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[21] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[22] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[23] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[24] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[25] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[26] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[27] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[28] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[29] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[30] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[31] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[32] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[33] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[34] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[35] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[36] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[37] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[38] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[39] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[40] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[41] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[42] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[43] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[44] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[45] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[46] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[47] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[48] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[49] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[50] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[51] => (regout +: 1'b1)) = (0, 0) ;
(posedge clk => (fbkout +: datain)) = 0 ;
(posedge pclk[0] => (fbkout +: datain)) = 0 ;
(posedge pclk[1] => (fbkout +: datain)) = 0 ;
(posedge pclk[2] => (fbkout +: datain)) = 0 ;
(posedge pclk[3] => (fbkout +: datain)) = 0 ;
(posedge pclk[4] => (fbkout +: datain)) = 0 ;
(posedge pclk[5] => (fbkout +: datain)) = 0 ;
(posedge pclk[6] => (fbkout +: datain)) = 0 ;
(posedge pclk[7] => (fbkout +: datain)) = 0 ;
(posedge pclk[8] => (fbkout +: datain)) = 0 ;
(posedge pclk[9] => (fbkout +: datain)) = 0 ;
(posedge pclk[10] => (fbkout +: datain)) = 0 ;
(posedge pclk[11] => (fbkout +: datain)) = 0 ;
(posedge pclk[12] => (fbkout +: datain)) = 0 ;
(posedge pclk[13] => (fbkout +: datain)) = 0 ;
(posedge pclk[14] => (fbkout +: datain)) = 0 ;
(posedge pclk[15] => (fbkout +: datain)) = 0 ;
(posedge pclk[16] => (fbkout +: datain)) = 0 ;
(posedge pclk[17] => (fbkout +: datain)) = 0 ;
(posedge pclk[18] => (fbkout +: datain)) = 0 ;
(posedge pclk[19] => (fbkout +: datain)) = 0 ;
(posedge pclk[20] => (fbkout +: datain)) = 0 ;
(posedge pclk[21] => (fbkout +: datain)) = 0 ;
(posedge pclk[22] => (fbkout +: datain)) = 0 ;
(posedge pclk[23] => (fbkout +: datain)) = 0 ;
(posedge pclk[24] => (fbkout +: datain)) = 0 ;
(posedge pclk[25] => (fbkout +: datain)) = 0 ;
(posedge pclk[26] => (fbkout +: datain)) = 0 ;
(posedge pclk[27] => (fbkout +: datain)) = 0 ;
(posedge pclk[28] => (fbkout +: datain)) = 0 ;
(posedge pclk[29] => (fbkout +: datain)) = 0 ;
(posedge pclk[30] => (fbkout +: datain)) = 0 ;
(posedge pclk[31] => (fbkout +: datain)) = 0 ;
(posedge pclk[32] => (fbkout +: datain)) = 0 ;
(posedge pclk[33] => (fbkout +: datain)) = 0 ;
(posedge pclk[34] => (fbkout +: datain)) = 0 ;
(posedge pclk[35] => (fbkout +: datain)) = 0 ;
(posedge pclk[36] => (fbkout +: datain)) = 0 ;
(posedge pclk[37] => (fbkout +: datain)) = 0 ;
(posedge pclk[38] => (fbkout +: datain)) = 0 ;
(posedge pclk[39] => (fbkout +: datain)) = 0 ;
(posedge pclk[40] => (fbkout +: datain)) = 0 ;
(posedge pclk[41] => (fbkout +: datain)) = 0 ;
(posedge pclk[42] => (fbkout +: datain)) = 0 ;
(posedge pclk[43] => (fbkout +: datain)) = 0 ;
(posedge pclk[44] => (fbkout +: datain)) = 0 ;
(posedge pclk[45] => (fbkout +: datain)) = 0 ;
(posedge pclk[46] => (fbkout +: datain)) = 0 ;
(posedge pclk[47] => (fbkout +: datain)) = 0 ;
(posedge pclk[48] => (fbkout +: datain)) = 0 ;
(posedge pclk[49] => (fbkout +: datain)) = 0 ;
(posedge pclk[50] => (fbkout +: datain)) = 0 ;
(posedge pclk[51] => (fbkout +: datain)) = 0 ;
(posedge aclr => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[0] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[1] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[2] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[3] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[4] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[5] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[6] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[7] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[8] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[9] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[10] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[11] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[12] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[13] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[14] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[15] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[16] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[17] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[18] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[19] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[20] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[21] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[22] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[23] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[24] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[25] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[26] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[27] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[28] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[29] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[30] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[31] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[32] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[33] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[34] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[35] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[36] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[37] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[38] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[39] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[40] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[41] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[42] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[43] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[44] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[45] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[46] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[47] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[48] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[49] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[50] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[51] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge papre[0] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[1] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[2] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[3] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[4] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[5] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[6] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[7] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[8] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[9] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[10] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[11] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[12] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[13] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[14] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[15] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[16] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[17] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[18] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[19] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[20] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[21] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[22] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[23] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[24] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[25] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[26] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[27] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[28] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[29] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[30] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[31] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[32] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[33] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[34] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[35] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[36] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[37] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[38] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[39] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[40] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[41] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[42] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[43] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[44] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[45] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[46] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[47] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[48] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[49] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[50] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[51] => (fbkout +: 1'b1)) = (0, 0) ;
endspecify
initial
begin
penable = 'b1;
pterm_aclr = 'b0;
pterm_preset = 'b0;
ptermclk = 'b0;
oldclk1 = 'b0;
oldclk2 = 'b0;
violation = 0;
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
always @(datain_viol or clk_per_viol or pclk_per_viol or pena_viol)
begin
violation = 1;
end
always @ (clk_in or iclr or ipaclr or ipapre or ipena or posedge violation
or ipclk)
begin
if (&ipclk !== 'b1)
ptermclk = 'b0;
else
ptermclk = 'b1;
if (&ipena == 'b0)
penable = 'b0;
else
penable = 'b1;
if ((&ipaclr) == 'b1)
pterm_aclr = 'b1;
else
pterm_aclr = 'b0;
if (&ipapre == 'b1)
pterm_preset = 'b1;
else
pterm_preset = 'b0;
if ((iclr == 'b1) || (pterm_aclr === 'b1))
iregout = 'b0;
else if (pterm_preset == 'b1)
iregout = 'b1;
else if (violation == 1'b1)
begin
violation = 0;
iregout = 'bx;
end
else if (penable == 'b1)
begin
if (((clk_in == 'b1) && (oldclk1 == 'b0)) || ((ptermclk == 'b1) && (oldclk2 == 'b0)))
begin
iregout = datain;
end
end
oldclk1 = clk_in;
oldclk2 = ptermclk;
end
and (regout, iregout, 'b1);
and (fbkout, iregout, 'b1);
endmodule
//
// MAX MCELL ATOM
//
`timescale 1 ps/1 ps
module max_mcell (pterm0, pterm1, pterm2, pterm3, pterm4, pterm5, pxor,
pexpin, clk, aclr, fpin, pclk, pena, paclr, papre,
dataout, pexpout);
parameter operation_mode = "normal";
parameter output_mode = "comb";
parameter register_mode = "dff";
parameter pexp_mode = "off";
parameter power_up = "low";
input [51:0] pterm0, pterm1, pterm2, pterm3, pterm4, pterm5;
input [51:0] pxor, pclk, pena, paclr, papre;
input pexpin, clk, aclr, fpin;
output dataout, pexpout;
wire fbk, dffin, combo, dffo;
max_asynch_mcell pcom (pterm0, pterm1, pterm2, pterm3, pterm4,
pterm5, fpin, pxor, pexpin, fbk, combo,
pexpout, dffin);
max_mcell_register preg (dffin, clk, aclr, pclk, pena, paclr,
papre, dffo, fbk);
defparam
pcom.operation_mode = operation_mode,
pcom.pexp_mode = pexp_mode,
pcom.register_mode = register_mode,
preg.operation_mode = operation_mode,
preg.power_up = power_up,
preg.register_mode = register_mode;
assign dataout = (output_mode == "comb") ? combo : dffo;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// MAX SEXP ATOM
//
//////////////////////////////////////////////////////////////////////////////
// MAX SEXP ASYNCH
`timescale 1 ps/1 ps
module max_asynch_sexp (datain, dataout);
input [51:0] datain;
output dataout;
reg tmp_dataout;
wire [51:0] idatain;
buf (idatain[0], datain[0]);
buf (idatain[1], datain[1]);
buf (idatain[2], datain[2]);
buf (idatain[3], datain[3]);
buf (idatain[4], datain[4]);
buf (idatain[5], datain[5]);
buf (idatain[6], datain[6]);
buf (idatain[7], datain[7]);
buf (idatain[8], datain[8]);
buf (idatain[9], datain[9]);
buf (idatain[10], datain[10]);
buf (idatain[11], datain[11]);
buf (idatain[12], datain[12]);
buf (idatain[13], datain[13]);
buf (idatain[14], datain[14]);
buf (idatain[15], datain[15]);
buf (idatain[16], datain[16]);
buf (idatain[17], datain[17]);
buf (idatain[18], datain[18]);
buf (idatain[19], datain[19]);
buf (idatain[20], datain[20]);
buf (idatain[21], datain[21]);
buf (idatain[22], datain[22]);
buf (idatain[23], datain[23]);
buf (idatain[24], datain[24]);
buf (idatain[25], datain[25]);
buf (idatain[26], datain[26]);
buf (idatain[27], datain[27]);
buf (idatain[28], datain[28]);
buf (idatain[29], datain[29]);
buf (idatain[30], datain[30]);
buf (idatain[31], datain[31]);
buf (idatain[32], datain[32]);
buf (idatain[33], datain[33]);
buf (idatain[34], datain[34]);
buf (idatain[35], datain[35]);
buf (idatain[36], datain[36]);
buf (idatain[37], datain[37]);
buf (idatain[38], datain[38]);
buf (idatain[39], datain[39]);
buf (idatain[40], datain[40]);
buf (idatain[41], datain[41]);
buf (idatain[42], datain[42]);
buf (idatain[43], datain[43]);
buf (idatain[44], datain[44]);
buf (idatain[45], datain[45]);
buf (idatain[46], datain[46]);
buf (idatain[47], datain[47]);
buf (idatain[48], datain[48]);
buf (idatain[49], datain[49]);
buf (idatain[50], datain[50]);
buf (idatain[51], datain[51]);
specify
(datain[0] => dataout) = (0, 0) ;
(datain[1] => dataout) = (0, 0) ;
(datain[2] => dataout) = (0, 0) ;
(datain[3] => dataout) = (0, 0) ;
(datain[4] => dataout) = (0, 0) ;
(datain[5] => dataout) = (0, 0) ;
(datain[6] => dataout) = (0, 0) ;
(datain[7] => dataout) = (0, 0) ;
(datain[8] => dataout) = (0, 0) ;
(datain[9] => dataout) = (0, 0) ;
(datain[10] => dataout) = (0, 0) ;
(datain[11] => dataout) = (0, 0) ;
(datain[12] => dataout) = (0, 0) ;
(datain[13] => dataout) = (0, 0) ;
(datain[14] => dataout) = (0, 0) ;
(datain[15] => dataout) = (0, 0) ;
(datain[16] => dataout) = (0, 0) ;
(datain[17] => dataout) = (0, 0) ;
(datain[18] => dataout) = (0, 0) ;
(datain[19] => dataout) = (0, 0) ;
(datain[20] => dataout) = (0, 0) ;
(datain[21] => dataout) = (0, 0) ;
(datain[22] => dataout) = (0, 0) ;
(datain[23] => dataout) = (0, 0) ;
(datain[24] => dataout) = (0, 0) ;
(datain[25] => dataout) = (0, 0) ;
(datain[26] => dataout) = (0, 0) ;
(datain[27] => dataout) = (0, 0) ;
(datain[28] => dataout) = (0, 0) ;
(datain[29] => dataout) = (0, 0) ;
(datain[30] => dataout) = (0, 0) ;
(datain[31] => dataout) = (0, 0) ;
(datain[32] => dataout) = (0, 0) ;
(datain[33] => dataout) = (0, 0) ;
(datain[34] => dataout) = (0, 0) ;
(datain[35] => dataout) = (0, 0) ;
(datain[36] => dataout) = (0, 0) ;
(datain[37] => dataout) = (0, 0) ;
(datain[38] => dataout) = (0, 0) ;
(datain[39] => dataout) = (0, 0) ;
(datain[40] => dataout) = (0, 0) ;
(datain[41] => dataout) = (0, 0) ;
(datain[42] => dataout) = (0, 0) ;
(datain[43] => dataout) = (0, 0) ;
(datain[44] => dataout) = (0, 0) ;
(datain[45] => dataout) = (0, 0) ;
(datain[46] => dataout) = (0, 0) ;
(datain[47] => dataout) = (0, 0) ;
(datain[48] => dataout) = (0, 0) ;
(datain[49] => dataout) = (0, 0) ;
(datain[50] => dataout) = (0, 0) ;
(datain[51] => dataout) = (0, 0) ;
endspecify
always @ (idatain)
begin
tmp_dataout = ~(&idatain);
end
and (dataout, tmp_dataout, 'b1);
endmodule
//
// MAX SEXP ATOM
//
`timescale 1 ps/1 ps
module max_sexp (datain, dataout);
input [51:0] datain;
output dataout;
max_asynch_sexp pcom (datain, dataout);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_state.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Primary bank state machine. All bank specific timing is generated here.
//
// Conceptually, when a bank machine is assigned a request, conflicts are
// checked. If there is a conflict, then the new request is added
// to the queue for that rank-bank.
//
// Eventually, that request will find itself at the head of the queue for
// its rank-bank. Forthwith, the bank machine will begin arbitration to send an
// activate command to the DRAM. Once arbitration is successful and the
// activate is sent, the row state machine waits the RCD delay. The RAS
// counter is also started when the activate is sent.
//
// Upon completion of the RCD delay, the bank state machine will begin
// arbitration for sending out the column command. Once the column
// command has been sent, the bank state machine waits the RTP latency, and
// if the command is a write, the RAS counter is loaded with the WR latency.
//
// When the RTP counter reaches zero, the pre charge wait state is entered.
// Once the RAS timer reaches zero, arbitration to send a precharge command
// begins.
//
// Upon successful transmission of the precharge command, the bank state
// machine waits the precharge period and then rejoins the idle list.
//
// For an open rank-bank hit, a bank machine passes management of the rank-bank to
// a bank machine that is managing the subsequent request to the same page. A bank
// machine can either be a "passer" or a "passee" in this handoff. There
// are two conditions that have to occur before an open bank can be passed.
// A spatial condition, ie same rank-bank and row address. And a temporal condition,
// ie the passee has completed it work with the bank, but has not issued a precharge.
//
// The spatial condition is signalled by pass_open_bank_ns. The temporal condition
// is when the column command is issued, or when the bank_wait_in_progress
// signal is true. Bank_wait_in_progress is true when the RTP timer is not
// zero, or when the RAS/WR timer is not zero and the state machine is waiting
// to send out a precharge command.
//
// On an open bank pass, the passer transitions from the temporal condition
// noted above and performs the end of request processing and eventually lands
// in the act_wait_r state.
//
// On an open bank pass, the passee lands in the col_wait_r state and waits
// for its chance to send out a column command.
//
// Since there is a single data bus shared by all columns in all ranks, there
// is a single column machine. The column machine is primarily in charge of
// managing the timing on the DQ data bus. It reserves states for data transfer,
// driver turnaround states, and preambles. It also has the ability to add
// additional programmable delay for read to write changeovers. This read to write
// delay is generated in the column machine which inhibits writes via the
// inhbt_wr signal.
//
// There is a rank machine for every rank. The rank machines are responsible
// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
// in the bank machine since it is closely coupled to the operation of the
// bank machine and is timing critical.
//
// Since a bank machine can be working on a request for any rank, all rank machines
// inhibits are input to all bank machines. Based on the rank of the current
// request, each bank machine selects the rank information corresponding
// to the rank of its current request.
//
// Since driver turnaround states and WTR delays are so severe with DDRIII, the
// memory interface has the ability to promote requests that use the same
// driver as the most recent request. There is logic in this block that
// detects when the driver for its request is the same as the driver for
// the most recent request. In such a case, this block will send out special
// "same" request early enough to eliminate dead states when there is no
// driver changeover.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v2_3_bank_state #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRP = 10,
parameter nRTP = 4,
parameter nRCD = 5,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANKS = 4,
parameter RANK_WIDTH = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,
bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,
allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,
act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,
rd_this_rank_r, rts_pre, rtc,
// Inputs
clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,
sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,
phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,
passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,
auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,
start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,
demand_act_priority_in, order_q_zero, sent_col, q_has_rd,
q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,
inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,
rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Activate wait state machine.
input bm_end;
reg bm_end_r1;
always @(posedge clk) bm_end_r1 <= #TCQ bm_end;
reg col_wait_r;
input pass_open_bank_r;
input sending_row;
reg act_wait_r_lcl;
input rcv_open_bank;
wire start_rcd_lcl = act_wait_r_lcl && sending_row;
output wire start_rcd;
assign start_rcd = start_rcd_lcl;
wire act_wait_ns = rst ||
((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||
bm_end_r1 || (pass_open_bank_r && bm_end));
always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;
output wire act_wait_r;
assign act_wait_r = act_wait_r_lcl;
// RCD timer
//
// When CWL is even, CAS commands are issued on slot 0 and RAS commands are
// issued on slot 1. This implies that the RCD can never expire in the same
// cycle as the RAS (otherwise the CAS for a given transaction would precede
// the RAS). Similarly, this can also cause premature expiration for longer
// RCD. An offset must be added to RCD before translating it to the FPGA clock
// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to
// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to
// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.
//
// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are
// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS
// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the
// RAS command. In 2:1 mode, there are only 2 slots so direct translation
// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,
// there are two slots after CAS, so 2 is added to shift the timer into the
// next FPGA cycle for cases that can't expire in the current cycle.
//
// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,
// It is sufficient to translate to the half-rate domain and add the remainder.
// In 4:1 mode, we must translate to the quarter-rate domain and add an
// additional fabric cycle only if the remainder exceeds the fixed offset of 2
localparam nRCD_CLKS =
nCK_PER_CLK == 1 ?
nRCD :
nCK_PER_CLK == 2 ?
ADDR_CMD_MODE == "2T" ?
(nRCD/2) + (nRCD%2) :
CWL % 2 ?
(nRCD/2) :
(nRCD+2) / 2 :
// (nCK_PER_CLK == 4)
ADDR_CMD_MODE == "2T" ?
(nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :
CWL % 2 ?
(nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :
nRCD/4 + 1;
localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;
localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);
localparam ZERO = 0;
localparam ONE = 1;
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};
reg end_rcd;
reg rcd_active_r = 1'b0;
generate
if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2
always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;
end
else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;
always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin
if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];
else begin
rcd_timer_ns = rcd_timer_r;
if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];
else if (|rcd_timer_r) rcd_timer_ns =
rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;
wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);
always @(posedge clk) end_rcd = end_rcd_ns;
wire rcd_active_ns = |rcd_timer_ns;
always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;
end
endgenerate
// Figure out if the read that's completing is for an RMW for
// this bank machine. Delay by a state if CWL != 8 since the
// data is not ready in the RMW buffer for the early write
// data fetch that happens with ECC and CWL != 8.
// Create a state bit indicating we're waiting for the read
// half of the rmw to complete.
input sending_col;
input rd_wr_r;
input req_wr_r;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
input phy_rddata_valid;
input rd_rmw;
reg rmw_rd_done = 1'b0;
reg rd_half_rmw_lcl = 1'b0;
output wire rd_half_rmw;
assign rd_half_rmw = rd_half_rmw_lcl;
reg rmw_wait_r = 1'b0;
generate
if (ECC != "OFF") begin : rmw_on
// Delay phy_rddata_valid and rd_rmw by one cycle to align them
// to req_data_buf_addr_r so that rmw_wait_r clears properly
reg phy_rddata_valid_r;
reg rd_rmw_r;
always @(posedge clk) begin
phy_rddata_valid_r <= #TCQ phy_rddata_valid;
rd_rmw_r <= #TCQ rd_rmw;
end
wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r &&
(rd_data_addr == req_data_buf_addr_r);
if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;
else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;
always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;
wire rmw_wait_ns = ~rst &&
((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));
always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;
end
endgenerate
// column wait state machine.
wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd
|| rcv_open_bank || (rmw_rd_done && rmw_wait_r));
always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;
// Set up various RAS timer parameters, wires, etc.
localparam TWO = 2;
output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;
reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;
input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;
// On a bank pass, select the RAS timer from the passing bank machine.
reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;
integer i;
always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin
passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};
for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)
if (rb_hit_busies_r[i])
passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];
end
// RAS and (reused for) WTP timer. When an open bank is passed, this
// timer is passed to the new owner. The existing RAS prevents
// an activate from occuring too early.
wire start_wtp_timer = sending_col && ~rd_wr_r;
input idle_r;
always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl
or start_wtp_timer) begin
if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];
else begin
ras_timer_ns = ras_timer_r;
if (start_rcd_lcl) ras_timer_ns =
nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];
if (start_wtp_timer) ras_timer_ns =
// As the timer is being reused, it is essential to compare
// before new value is loaded.
(ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]
: ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =
ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
end
end // always @ (...
wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank
? passed_ras_timer
: ras_timer_ns;
always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;
wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);
reg ras_timer_zero_r;
always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;
// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nRTP_CLKS = (nCK_PER_CLK == 1)
? nRTP :
(nCK_PER_CLK == 2)
? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) :
(nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2);
localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;
localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;
wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;
always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r
or sending_col_not_rmw_rd) begin
rtp_timer_ns = rtp_timer_r;
if (rst || pass_open_bank_r)
rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];
else begin
if (sending_col_not_rmw_rd)
rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];
if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;
wire end_rtp_lcl = ~pass_open_bank_r &&
((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||
((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));
output wire end_rtp;
assign end_rtp = end_rtp_lcl;
// Optionally implement open page mode timer.
localparam OP_WIDTH = clogb2(nOP_WAIT + 1);
output wire bank_wait_in_progress;
output wire start_pre_wait;
input passing_open_bank;
input low_idle_cnt_r;
output wire op_exit_req;
input op_exit_grant;
input tail_r;
output reg pre_wait_r;
generate
if (nOP_WAIT == 0) begin : op_mode_disabled
assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r);
assign start_pre_wait = end_rtp_lcl;
assign op_exit_req = 1'b0;
end
else begin : op_mode_enabled
reg op_wait_r;
assign bank_wait_in_progress = sending_col || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r) ||
op_wait_r;
wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)
|| op_wait_r);
wire op_wait_ns = ~op_exit_grant && op_active;
always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;
assign start_pre_wait = op_exit_grant ||
(end_rtp_lcl && ~tail_r && ~passing_open_bank);
if (nOP_WAIT == -1)
assign op_exit_req = (low_idle_cnt_r && op_active);
else begin : op_cnt
reg [OP_WIDTH-1:0] op_cnt_r;
wire [OP_WIDTH-1:0] op_cnt_ns =
(passing_open_bank || op_exit_grant || rst)
? ZERO[OP_WIDTH-1:0]
: end_rtp_lcl
? nOP_WAIT[OP_WIDTH-1:0]
: |op_cnt_r
? op_cnt_r - ONE[OP_WIDTH-1:0]
: op_cnt_r;
always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;
assign op_exit_req = (low_idle_cnt_r && op_active) ||
(op_wait_r && ~|op_cnt_r);
end
end
endgenerate
output allow_auto_pre;
wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||
(col_wait_r && ~sending_col);
// precharge wait state machine.
input auto_pre_r;
wire start_pre;
input pass_open_bank_ns;
wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&
(start_pre_wait || (pre_wait_r && ~start_pre)));
always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;
wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;
// precharge timer.
localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP :
(nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) :
/*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));
// Subtract two because there are a minimum of two fabric states from
// end of RP timer until earliest possible arb to send act.
localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;
localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);
input sending_pre;
output rts_pre;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_pre || auto_pre_r);
assign rts_pre = ~sending_pre && pre_request;
end
else begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_row || auto_pre_r);
assign rts_pre = 1'b0;
end
endgenerate
reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];
generate
if (nRP_CLKS_M2 > ZERO) begin : rp_timer
reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;
always @(/*AS*/rp_timer_r or rst or start_pre)
if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];
else begin
rp_timer_ns = rp_timer_r;
if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];
else if (|rp_timer_r) rp_timer_ns =
rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];
end
always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;
end // block: rp_timer
endgenerate
output wire precharge_bm_end;
assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||
(start_pre && (nRP_CLKS_M2 == ZERO));
// Compute RRD related activate inhibit.
// Compare this bank machine's rank with others, then
// select result based on grant. An alternative is to
// select the just issued rank with the grant and simply
// compare against this bank machine's rank. However, this
// serializes the selection of the rank and the compare processes.
// As implemented below, the compare occurs first, then the
// selection based on grant. This is faster.
input [RANK_WIDTH-1:0] req_rank_r;
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;
reg inhbt_act_rrd;
input [(nBANK_MACHS*2)-1:0] start_rcd_in;
generate
integer j;
if (RANKS == 1)
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];
end
else begin
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd ||
(start_rcd_in[j] &&
(req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));
end
end
endgenerate
// Extract the activate command inhibit for the rank associated
// with this request. FAW and RRD are computed separately so that
// gate level timing can be carefully managed.
input [RANKS-1:0] inhbt_act_faw_r;
wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];
input wait_for_maint_r;
input head_r;
wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&
~wait_for_maint_r;
// Implement simple starvation avoidance for act requests. Precharge
// requests don't need this because they are never gated off by
// timing events such as inhbt_act_rrd. Priority request timeout
// is fixed at a single trip around the round robin arbiter.
input sent_row;
wire rts_act_denied = act_req && sent_row && ~sending_row;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;
generate
if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2
begin :BM_MORE_THAN_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{{BM_CNT_WIDTH-1{1'b0}}, 1'b1};
end
end
else // Number of Bank Machs == 2
begin :BM_EQUAL_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{1'b1};
end
end
endgenerate
always @(posedge clk) act_starve_limit_cntr_r <=
#TCQ act_starve_limit_cntr_ns;
reg demand_act_priority_r;
wire demand_act_priority_ns = act_req &&
(demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));
always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;
`ifdef MC_SVA
cover_demand_act_priority:
cover property (@(posedge clk) (~rst && demand_act_priority_r));
`endif
output wire demand_act_priority;
assign demand_act_priority = demand_act_priority_r && ~sending_row;
// compute act_demanded from other demand_act_priorities
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;
reg act_demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_act_demanded
always @(demand_act_priority_in[`BM_SHARED_BV])
act_demanded = |demand_act_priority_in[`BM_SHARED_BV];
end
endgenerate
wire row_demand_ok = demand_act_priority_r || ~act_demanded;
// Generate the Request To Send row arbitation signal.
output wire rts_row;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T"))
assign rts_row = ~sending_row && row_demand_ok &&
(act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);
else
assign rts_row = ~sending_row && row_demand_ok &&
((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||
pre_request);
endgenerate
`ifdef MC_SVA
four_activate_window_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && my_inhbt_act_faw));
ras_ras_delay_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && inhbt_act_rrd));
`endif
// Provide rank machines early knowledge that this bank machine is
// going to send an activate to the rank. In this way, the rank
// machines just need to use the sending_row wire to figure out if
// they need to keep track of the activate.
output reg [RANKS-1:0] act_this_rank_r;
reg [RANKS-1:0] act_this_rank_ns;
always @(/*AS*/act_wait_r or req_rank_r) begin
act_this_rank_ns = {RANKS{1'b0}};
for (i = 0; i < RANKS; i = i + 1)
act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;
// Generate request to send column command signal.
input order_q_zero;
wire req_bank_rdy_ns = order_q_zero && col_wait_r;
reg req_bank_rdy_r;
always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;
// Determine is we have been denied a column command request.
input sent_col;
wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;
// Implement a starvation limit counter. Count the number of times a
// request to send a column command has been denied.
localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;
localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;
always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)
if (~col_wait_r)
starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};
else
if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))
starve_limit_cntr_ns = starve_limit_cntr_r +
{{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};
else starve_limit_cntr_ns = starve_limit_cntr_r;
always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;
input q_has_rd;
input q_has_priority;
// Decide if this bank machine should demand priority. Priority is demanded
// when starvation limit counter is reached, or a bit in the request.
wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&
rts_col_denied);
input req_priority_r;
input idle_ns;
reg demand_priority_r;
wire demand_priority_ns = ~idle_ns && col_wait_ns &&
(demand_priority_r ||
(order_q_zero &&
(req_priority_r || q_has_priority)) ||
(starved && (q_has_rd || ~req_wr_r)));
always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;
`ifdef MC_SVA
wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&
col_wait_ns;
req_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));
q_priority_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));
wire not_req_or_q_rdy_for_priority =
rdy_for_priority && ~req_priority_r && ~q_has_priority;
starved_req_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));
starved_q_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));
`endif
// compute demanded from other demand_priorities
input [(nBANK_MACHS*2)-1:0] demand_priority_in;
reg demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_demanded
always @(demand_priority_in[`BM_SHARED_BV]) demanded =
|demand_priority_in[`BM_SHARED_BV];
end
endgenerate
// In order to make sure that there is no starvation amongst a possibly
// unlimited stream of priority requests, add a second stage to the demand
// priority signal. If there are no other requests demanding priority, then
// go ahead and assert demand_priority. If any other requests are asserting
// demand_priority, hold off asserting demand_priority until these clear, then
// assert demand priority. Its possible to get multiple requests asserting
// demand priority simultaneously, but that's OK. Those requests will be
// serviced, demanded will fall, and another group of requests will be
// allowed to assert demand_priority.
reg demanded_prior_r;
wire demanded_prior_ns = demanded &&
(demanded_prior_r || ~demand_priority_r);
always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;
output wire demand_priority;
assign demand_priority = demand_priority_r && ~demanded_prior_r &&
~sending_col;
`ifdef MC_SVA
demand_priority_gated:
cover property (@(posedge clk) (demand_priority_r && ~demand_priority));
generate
if (nBANK_MACHS >1) multiple_demand_priority:
cover property (@(posedge clk)
($countones(demand_priority_in[`BM_SHARED_BV]) > 1));
endgenerate
`endif
wire demand_ok = demand_priority_r || ~demanded;
// Figure out if the request in this bank machine matches the current rank
// configuration.
input rnk_config_strobe;
input rnk_config_kill_rts_col;
input rnk_config_valid_r;
input [RANK_WIDTH-1:0] rnk_config;
output wire rtc;
wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);
assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;
// Using rank state provided by the rank machines, figure out if
// a read requests should wait for WTR or RTW.
input [RANKS-1:0] inhbt_rd;
wire my_inhbt_rd = inhbt_rd[req_rank_r];
input [RANKS-1:0] inhbt_wr;
wire my_inhbt_wr = inhbt_wr[req_rank_r];
wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;
// DQ bus timing constraints.
input dq_busy_data;
// Column command is ready to arbitrate, except for databus restrictions.
wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||
(rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") ||
(rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) &&
order_q_zero;
// Column command is ready to arbitrate for sending a write. Used
// to generate early wr_data_addr for ECC mode.
output wire col_rdy_wr;
assign col_rdy_wr = col_rdy && ~rd_wr_r;
// Figure out if we're ready to send a column command based on all timing
// constraints.
// if timing is an issue.
wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;
`ifdef MC_SVA
col_wait_for_order_q: cover property
(@(posedge clk)
(~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&
allow_rw));
col_wait_for_dq_busy: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && dq_busy_data &&
allow_rw));
col_wait_for_allow_rw: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && ~dq_busy_data &&
~allow_rw));
`endif
// Implement flow control for the command and control FIFOs and for the data
// FIFO during writes
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
// Register ctl_full and cmd_full
reg phy_mc_ctl_full_r = 1'b0;
reg phy_mc_cmd_full_r = 1'b0;
always @(posedge clk)
if(rst) begin
phy_mc_ctl_full_r <= #TCQ 1'b0;
phy_mc_cmd_full_r <= #TCQ 1'b0;
end else begin
phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;
phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;
end
// register output data pre-fifo almost full condition and fold in WR status
reg ofs_rdy_r = 1'b0;
always @(posedge clk)
if(rst)
ofs_rdy_r <= #TCQ 1'b0;
else
ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);
// Disable priority feature for one state after a config to insure
// forward progress on the just installed io config.
reg override_demand_r;
wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;
always @(posedge clk) override_demand_r <= override_demand_ns;
output wire rts_col;
assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&
col_cmd_rts && ofs_rdy_r;
// As in act_this_rank, wr/rd_this_rank informs rank machines
// that this bank machine is doing a write/rd. Removes logic
// after the grant.
reg [RANKS-1:0] wr_this_rank_ns;
reg [RANKS-1:0] rd_this_rank_ns;
always @(/*AS*/rd_wr_r or req_rank_r) begin
wr_this_rank_ns = {RANKS{1'b0}};
rd_this_rank_ns = {RANKS{1'b0}};
for (i=0; i<RANKS; i=i+1) begin
wr_this_rank_ns[i] = ~rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
rd_this_rank_ns[i] = rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
end
output reg [RANKS-1:0] wr_this_rank_r;
always @(posedge clk) wr_this_rank_r <= #TCQ wr_this_rank_ns;
output reg [RANKS-1:0] rd_this_rank_r;
always @(posedge clk) rd_this_rank_r <= #TCQ rd_this_rank_ns;
endmodule // bank_state
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
module test_tiny;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [`WIDTH_D0:0] data;
// Outputs
wire [`WIDTH_D0:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1; // keep FSM silent
// init x, y
write(3, 1186'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
write(5, 1186'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
write(6, 1186'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
write(7, 1186'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(9);
check(1186'h20115a6958895a08585a412698a58250900a651a859448a4848125164545598a426119a09885802424154a08855a0042a168516099228606222540582026aa0a6029a88805a1888628856a2a64504120aa290491925284508921140a24a0a8641548a521512698985a610861a401208644612a4a52625119000006004518844899810191a056aaa680889958996508954685a0920);
read(10);
check(1186'h228a9556506501a0258028a8856851a5466a205a2544849a12a10a018a40aaa461959859a4408245094969a44565a160a98229805169491120568121008a04918050a9022854868440662591221116889a9668a82aa84182a59025424469164015a56698a95989555601618402286696055608a82508125aaa5882000aaa96114998660a684582889a5a5190058a0411426145250);
read(11);
check(1186'h001224a468a9154205488585aaa9a0a9882056194952001a88424522191052a96a21102915181a845a5509844985196696160900a0515956a2a10a100a12566408a14450049a586951896442400a8620148582958a8a51869990a161412406860012a61a66214a4461a86895640a48284528201852615921952aaaaa40802586168a929582128a985929990826a9110186891489a);
read(12);
check(1186'h019618a9624a522a280a06a0654418906998059625a892054996a0560a941a842589189984190884426125114000aa60a0a568285221026662226a626a8600605095054405486561a95059449282969a5a10819101a620902609052a1294182962a020512196945a2aa42598a41842096596551544969262a12a86685214a952494a956166a199682a649249a990088296422051a);
read(13);
check(1186'h1a6999a0105054aaa2145298116480601695482119a0619155a4414a8a82840918a512a5680a8000889a4905016868480211289860a8a5699a250245161a042846096a9866025094a189860a9829465281646040866a26959a61a18621848689101a9a95685016a9581224968461a0a108958a91205a0220a18865105928298299a642a906900289a95095845649aa41591069866);
read(14);
check(1186'h15a4208a19a0405005900212505098a881a49445242619a12a12491844110169529a422046a684668819599891a411954196961160591865590a699a04908a6196928965a1686a664210420908115a5816919169662656a855099464680902514586265602510840a566a94a506961a615420a908aa91959610a1a0899589600902a10962460a664104126056a82551462459169a);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [6:0] adr;
input [`WIDTH_D0:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask
task check;
input [`WIDTH_D0:0] wish;
begin
if (out !== wish)
begin $display("Error! %h %h", out, wish); end
end
endtask
endmodule
|
`default_nettype none
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH:0] ALM_CARRY;
// Start of carry chain
generate
if (_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 1'b0) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
) alm_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.CO(ALM_CARRY[0])
);
end
endgenerate
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
) alm_i (
.A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),
.CI(ALM_CARRY[i]),
.SO(Y[i]),
.CO(ALM_CARRY[i+1])
);
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
module bram1 #(
parameter ABITS = 8, DBITS = 8, TRANSP = 0
) (
input clk,
input [ABITS-1:0] WR_ADDR,
input [DBITS-1:0] WR_DATA,
input WR_EN,
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [ABITS-1:0] RD_ADDR_BUF;
reg [DBITS-1:0] RD_DATA_BUF;
initial begin
memory[INIT_ADDR_0] <= INIT_DATA_0;
memory[INIT_ADDR_1] <= INIT_DATA_1;
memory[INIT_ADDR_2] <= INIT_DATA_2;
memory[INIT_ADDR_3] <= INIT_DATA_3;
end
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_ADDR_BUF <= RD_ADDR;
RD_DATA_BUF <= memory[RD_ADDR];
end
assign RD_DATA = TRANSP ? memory[RD_ADDR_BUF] : RD_DATA_BUF;
endmodule
|
/*
File: axi_slave.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_slave (/*AUTOARG*/
// Outputs
csysack, cactive, awready, wready, bid, bresp, bvalid, arready,
rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
emesh_wr_wait_inb, emesh_rd_wait_inb,
// Inputs
aclk, eclk, reset, csysreq, awid, awaddr, awlen, awsize, awburst,
awlock, awcache, awprot, awvalid, wid, wdata, wstrb, wlast, wvalid,
bready, arid, araddr, arlen, arsize, arburst, arlock, arcache,
arprot, arvalid, rready, emesh_access_outb, emesh_write_outb,
emesh_datamode_outb, emesh_ctrlmode_outb, emesh_dstaddr_outb,
emesh_srcaddr_outb, emesh_data_outb, emesh_wr_wait_outb,
emesh_rd_wait_outb, awqos, arqos
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
input csysreq;// system exit low-power state request
//########################
//# Write address channel
//########################
input [SIDW-1:0] awid; //write address ID
input [SAW-1:0] awaddr; //write address
input [3:0] awlen; //burst lenght (the number of data transfers)
input [2:0] awsize; //burst size (the size of each transfer)
input [1:0] awburst; //burst type
input [1:0] awlock; //lock type (atomic characteristics)
input [3:0] awcache; //memory type
input [2:0] awprot; //protection type
input awvalid; //write address valid
//########################
//# Write data channel
//########################
input [SIDW-1:0] wid; //write ID tag (supported only in AXI3)
input [SDW-1:0] wdata; //write data
input [3:0] wstrb; //write strobes
input wlast; //write last. Indicates the last transfer in burst
input wvalid;//write valid
//########################
// Write response channel
//########################
input bready;//response ready
//########################
//# Read address channel
//########################
input [SIDW-1:0] arid; //read address ID
input [SAW-1:0] araddr; //read address
input [3:0] arlen; //burst lenght (the number of data transfers)
input [2:0] arsize; //burst size (the size of each transfer)
input [1:0] arburst; //burst type
input [1:0] arlock; //lock type (atomic characteristics)
input [3:0] arcache; //memory type
input [2:0] arprot; //protection type
input arvalid; //write address valid
//########################
//# Read data channel
//########################
input rready; //read ready
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_wr_wait_outb;
input emesh_rd_wait_outb;
//##########
//# Outputs
//##########
// global signals
output csysack;//exit low-power state acknowledgement
output cactive;//clock active
//########################
//# Write address channel
//########################
output awready; //write address ready
//########################
//# Write data channel
//########################
output wready; //write ready
//########################
// Write response channel
//########################
output [SIDW-1:0] bid; //response ID tag
output [1:0] bresp; //write response
output bvalid;//write response valid
//########################
//# Read address channel
//########################
output arready;//read address ready
//########################
//# Read data channel
//########################
output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
output [SDW-1:0] rdata; //read data
output [1:0] rresp; //read response
output rlast; //read last, indicates the last transfer in burst
output rvalid;//read valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
output emesh_rd_wait_inb;
//#######################################################################
//# The following feature are not supported (AXI4 only)
//# If un-commented, those signals have to be driven with default values
//#######################################################################
input [3:0] awqos; //Quality of Service (AXI4 only) default 4'b0000
// input [3:0] awregion;//region identifier (AXI4 only)
// input awuser; //user signal (AXI4 only)
// input wuser; //user signal (AXI4 only)
input [3:0] arqos; //quality of service (AXI4 only) default 4'b0000
// input [3:0] arregion;//region identifier (AXI4 only)
// input aruser; //user signal (AXI4 only)
// output buser; //user signal (AXI4 only)
// output ruser; //user signal (AXI4 only)
//#########
//# Regs
//#########
reg csysack;
//#########
//# Wires
//#########
wire emesh_wr_access_inb;
wire emesh_wr_write_inb;
wire [1:0] emesh_wr_datamode_inb;
wire [3:0] emesh_wr_ctrlmode_inb;
wire [31:0] emesh_wr_dstaddr_inb;
wire [31:0] emesh_wr_srcaddr_inb;
wire [31:0] emesh_wr_data_inb;
wire emesh_rd_access_inb;
wire emesh_rd_write_inb;
wire [1:0] emesh_rd_datamode_inb;
wire [3:0] emesh_rd_ctrlmode_inb;
wire [31:0] emesh_rd_dstaddr_inb;
wire [31:0] emesh_rd_srcaddr_inb;
wire [31:0] emesh_rd_data_inb;
wire emesh_rd_wait;
/*AUTOINPUT*/
/*AUTOWIRE*/
//##################################################
//# This block doesn't accept read transactions
//# from emesh.
//##################################################
assign emesh_rd_wait_inb = 1'b0;
//##################################################
//# Low Power State
//# We don't support low power state
//##################################################
assign cactive = 1'b1;
always @ (posedge eclk or posedge reset)
if(reset)
csysack <= 1'b1;
else
csysack <= csysreq;
//##################################################
//# RD/WR transaction selection
//# *Write transactions are of the higher priority
//##################################################
assign emesh_rd_wait = emesh_rd_wait_outb | emesh_wr_access_inb;
assign emesh_access_inb = emesh_wr_access_inb | emesh_rd_access_inb;
assign emesh_write_inb = emesh_wr_access_inb ? emesh_wr_write_inb :
emesh_rd_write_inb;
assign emesh_datamode_inb[1:0] = emesh_wr_access_inb ?
emesh_wr_datamode_inb[1:0] :
emesh_rd_datamode_inb[1:0];
assign emesh_ctrlmode_inb[3:0] = emesh_wr_access_inb ?
emesh_wr_ctrlmode_inb[3:0] :
emesh_rd_ctrlmode_inb[3:0];
assign emesh_dstaddr_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_dstaddr_inb[31:0] :
emesh_rd_dstaddr_inb[31:0];
assign emesh_srcaddr_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_srcaddr_inb[31:0] :
emesh_rd_srcaddr_inb[31:0];
assign emesh_data_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_data_inb[31:0] :
emesh_rd_data_inb[31:0];
//##################################
//# Slave Write Port Instantiation
//##################################
/*axi_slave_wr AUTO_TEMPLATE(.emesh_wr_wait_outb (emesh_wr_wait_outb),
.emesh_\(.*\)_inb (emesh_wr_\1_inb[]),
);
*/
axi_slave_wr axi_slave_wr(/*AUTOINST*/
// Outputs
.awready (awready),
.wready (wready),
.bid (bid[SIDW-1:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.emesh_access_inb (emesh_wr_access_inb), // Templated
.emesh_write_inb (emesh_wr_write_inb), // Templated
.emesh_datamode_inb(emesh_wr_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(emesh_wr_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.awid (awid[SIDW-1:0]),
.awaddr (awaddr[SAW-1:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[SIDW-1:0]),
.wdata (wdata[SDW-1:0]),
.wstrb (wstrb[3:0]),
.wlast (wlast),
.wvalid (wvalid),
.bready (bready),
.emesh_wr_wait_outb(emesh_wr_wait_outb)); // Templated
//##################################
//# Slave Read Port Instantiation
//##################################
/*axi_slave_rd AUTO_TEMPLATE(.emesh_rd_wait_outb (emesh_rd_wait),
.emesh_wr_wait_inb (emesh_wr_wait_inb),
.emesh_\(.*\)_inb (emesh_rd_\1_inb[]),
);
*/
axi_slave_rd axi_slave_rd(/*AUTOINST*/
// Outputs
.arready (arready),
.rid (rid[SIDW-1:0]),
.rdata (rdata[SDW-1:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid),
.emesh_access_inb (emesh_rd_access_inb), // Templated
.emesh_write_inb (emesh_rd_write_inb), // Templated
.emesh_datamode_inb(emesh_rd_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(emesh_rd_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (emesh_wr_wait_inb), // Templated
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.arid (arid[SIDW-1:0]),
.araddr (araddr[SAW-1:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arburst (arburst[1:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready),
.emesh_access_outb (emesh_access_outb),
.emesh_write_outb (emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]),
.emesh_rd_wait_outb(emesh_rd_wait)); // Templated
endmodule // axi_slave
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:13:20 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84,
n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98,
n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161;
NAND2X1TS U75 ( .A(n105), .B(n104), .Y(n107) );
CMPR32X2TS U76 ( .A(in1[2]), .B(n161), .C(n160), .CO(n142), .S(res[2]) );
AOI21X1TS U77 ( .A0(n145), .A1(n151), .B0(n131), .Y(n152) );
NAND2BX1TS U78 ( .AN(n143), .B(n138), .Y(n161) );
AND2X2TS U79 ( .A(n140), .B(in1[3]), .Y(n145) );
OR2X2TS U80 ( .A(n90), .B(in1[12]), .Y(n87) );
OAI21X1TS U81 ( .A0(n95), .A1(in2[14]), .B0(n58), .Y(n96) );
NAND2X1TS U82 ( .A(n95), .B(n58), .Y(n81) );
NOR2XLTS U83 ( .A(n83), .B(n82), .Y(n84) );
NAND2BX1TS U84 ( .AN(in2[13]), .B(n83), .Y(n95) );
NAND2X1TS U85 ( .A(n85), .B(n58), .Y(n86) );
NOR2X1TS U86 ( .A(n66), .B(n82), .Y(n67) );
NAND2BX2TS U87 ( .AN(in2[11]), .B(n80), .Y(n85) );
BUFX3TS U88 ( .A(add_sub), .Y(n58) );
INVX2TS U89 ( .A(add_sub), .Y(n82) );
NOR2X4TS U90 ( .A(n74), .B(in2[4]), .Y(n76) );
CLKINVX6TS U91 ( .A(in2[0]), .Y(n62) );
INVX8TS U92 ( .A(in2[2]), .Y(n60) );
CLKINVX6TS U93 ( .A(in2[1]), .Y(n61) );
NOR2XLTS U94 ( .A(n80), .B(n82), .Y(n63) );
AND2X2TS U95 ( .A(in1[0]), .B(in2[0]), .Y(n136) );
OAI21XLTS U96 ( .A0(n145), .A1(n154), .B0(n142), .Y(n141) );
INVX2TS U97 ( .A(n113), .Y(n91) );
NAND2X2TS U98 ( .A(n110), .B(n109), .Y(n112) );
OR2X4TS U99 ( .A(n97), .B(in1[15]), .Y(n57) );
NAND2X2TS U100 ( .A(n90), .B(in1[12]), .Y(n113) );
XNOR2X2TS U101 ( .A(n86), .B(in2[12]), .Y(n90) );
NOR2X4TS U102 ( .A(n68), .B(in2[8]), .Y(n66) );
NOR2X4TS U103 ( .A(n72), .B(in2[6]), .Y(n70) );
NAND2X2TS U104 ( .A(n57), .B(n100), .Y(n102) );
NAND2X2TS U105 ( .A(n94), .B(in1[14]), .Y(n104) );
NAND2X2TS U106 ( .A(n97), .B(in1[15]), .Y(n100) );
NOR2X4TS U107 ( .A(n94), .B(in1[14]), .Y(n103) );
NAND2X2TS U108 ( .A(n92), .B(in1[13]), .Y(n109) );
XNOR2X2TS U109 ( .A(n96), .B(in2[15]), .Y(n97) );
NOR2X4TS U110 ( .A(n64), .B(in2[10]), .Y(n80) );
XOR2X1TS U111 ( .A(n135), .B(n134), .Y(res[6]) );
XOR2X2TS U112 ( .A(n67), .B(in2[9]), .Y(n119) );
AOI2BB2X1TS U113 ( .B0(n152), .B1(n132), .A0N(n157), .A1N(in1[5]), .Y(n135)
);
OAI21X1TS U114 ( .A0(n147), .A1(n154), .B0(n146), .Y(n150) );
XNOR2X2TS U115 ( .A(n69), .B(in2[8]), .Y(n121) );
NAND2X2TS U116 ( .A(n68), .B(n58), .Y(n69) );
OAI21XLTS U117 ( .A0(n137), .A1(n127), .B0(n126), .Y(res[1]) );
XOR2X1TS U118 ( .A(n133), .B(in1[6]), .Y(n134) );
OAI21X1TS U119 ( .A0(n160), .A1(in1[2]), .B0(n144), .Y(n147) );
NAND2BX1TS U120 ( .AN(n143), .B(n155), .Y(n144) );
INVX1TS U121 ( .A(n151), .Y(n153) );
AOI2BB1XLTS U122 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n136), .Y(res[0]) );
INVX12TS U123 ( .A(in2[3]), .Y(n59) );
XNOR2X2TS U124 ( .A(n102), .B(n101), .Y(res[15]) );
NOR2X2TS U125 ( .A(n76), .B(n82), .Y(n77) );
AFHCONX4TS U126 ( .A(in1[10]), .B(n117), .CI(n116), .CON(n88), .S(res[10])
);
NAND2BX4TS U127 ( .AN(in2[5]), .B(n76), .Y(n72) );
NAND2BX4TS U128 ( .AN(in2[9]), .B(n66), .Y(n64) );
NAND2BX4TS U129 ( .AN(in2[7]), .B(n70), .Y(n68) );
OAI21X4TS U130 ( .A0(n103), .A1(n106), .B0(n104), .Y(n101) );
OR2X1TS U131 ( .A(n130), .B(in1[4]), .Y(n151) );
INVX2TS U132 ( .A(n148), .Y(n131) );
NAND2X2TS U133 ( .A(n72), .B(add_sub), .Y(n73) );
NOR2X2TS U134 ( .A(n92), .B(in1[13]), .Y(n108) );
CLKXOR2X2TS U135 ( .A(n84), .B(in2[13]), .Y(n92) );
AND2X4TS U136 ( .A(in1[4]), .B(n130), .Y(n78) );
NAND2X1TS U137 ( .A(n151), .B(n148), .Y(n149) );
NAND2X1TS U138 ( .A(n87), .B(n113), .Y(n115) );
XOR2XLTS U139 ( .A(n112), .B(n111), .Y(res[13]) );
INVX2TS U140 ( .A(n108), .Y(n110) );
INVX2TS U141 ( .A(n103), .Y(n105) );
OAI2BB1X2TS U142 ( .A0N(n101), .A1N(n57), .B0(n100), .Y(res[16]) );
NAND2X1TS U143 ( .A(n160), .B(in1[2]), .Y(n155) );
XNOR2X2TS U144 ( .A(n139), .B(in2[2]), .Y(n160) );
NAND4X8TS U145 ( .A(n62), .B(n61), .C(n60), .D(n59), .Y(n74) );
XOR2X2TS U146 ( .A(n63), .B(in2[11]), .Y(n89) );
AFHCINX4TS U147 ( .CIN(n118), .B(n119), .A(in1[9]), .S(res[9]), .CO(n116) );
XNOR2X2TS U148 ( .A(n65), .B(in2[10]), .Y(n117) );
ADDFHX4TS U149 ( .A(n99), .B(in1[7]), .CI(n98), .CO(n120), .S(res[7]) );
ADDFHX4TS U150 ( .A(n133), .B(in1[6]), .CI(n79), .CO(n98) );
XOR2X1TS U151 ( .A(n107), .B(n106), .Y(res[14]) );
XOR2X4TS U152 ( .A(n71), .B(in2[7]), .Y(n99) );
AFHCONX4TS U153 ( .A(in1[8]), .B(n121), .CI(n120), .CON(n118), .S(res[8]) );
NAND2XLTS U154 ( .A(n130), .B(in1[4]), .Y(n148) );
XNOR2X4TS U155 ( .A(n73), .B(in2[6]), .Y(n133) );
XOR2X4TS U156 ( .A(n77), .B(in2[5]), .Y(n157) );
XNOR2X4TS U157 ( .A(n75), .B(in2[4]), .Y(n130) );
NAND2X4TS U158 ( .A(n74), .B(add_sub), .Y(n75) );
NAND2X1TS U159 ( .A(n64), .B(n58), .Y(n65) );
NOR2X1TS U160 ( .A(n70), .B(n82), .Y(n71) );
ADDFHX4TS U161 ( .A(n78), .B(in1[5]), .CI(n157), .CO(n79) );
NOR2X4TS U162 ( .A(n85), .B(in2[12]), .Y(n83) );
XNOR2X4TS U163 ( .A(n81), .B(in2[14]), .Y(n94) );
AFHCINX4TS U164 ( .CIN(n88), .B(n89), .A(in1[11]), .S(res[11]), .CO(n114) );
AOI21X4TS U165 ( .A0(n87), .A1(n114), .B0(n91), .Y(n111) );
INVX2TS U166 ( .A(n109), .Y(n93) );
AOI2BB1X4TS U167 ( .A0N(n108), .A1N(n111), .B0(n93), .Y(n106) );
XNOR2X1TS U168 ( .A(n115), .B(n114), .Y(res[12]) );
NAND2X1TS U169 ( .A(n58), .B(in2[0]), .Y(n122) );
CLKXOR2X2TS U170 ( .A(n122), .B(in2[1]), .Y(n124) );
INVX2TS U171 ( .A(n124), .Y(n137) );
XNOR2X1TS U172 ( .A(n136), .B(in1[1]), .Y(n127) );
INVX2TS U173 ( .A(in1[1]), .Y(n123) );
NOR2X2TS U174 ( .A(n124), .B(n123), .Y(n143) );
NOR3X1TS U175 ( .A(n136), .B(in1[1]), .C(n124), .Y(n125) );
AOI21X1TS U176 ( .A0(n136), .A1(n143), .B0(n125), .Y(n126) );
OR3X1TS U177 ( .A(in2[2]), .B(in2[0]), .C(in2[1]), .Y(n128) );
NAND2X1TS U178 ( .A(n58), .B(n128), .Y(n129) );
XNOR2X1TS U179 ( .A(n129), .B(in2[3]), .Y(n140) );
NAND2X1TS U180 ( .A(n157), .B(in1[5]), .Y(n132) );
OAI21X1TS U181 ( .A0(n137), .A1(in1[1]), .B0(n136), .Y(n138) );
OAI21X1TS U182 ( .A0(in2[0]), .A1(in2[1]), .B0(n58), .Y(n139) );
NOR2X2TS U183 ( .A(n140), .B(in1[3]), .Y(n154) );
OAI31X1TS U184 ( .A0(n145), .A1(n142), .A2(n154), .B0(n141), .Y(res[3]) );
INVX2TS U185 ( .A(n145), .Y(n146) );
XNOR2X1TS U186 ( .A(n150), .B(n149), .Y(res[4]) );
OAI31X1TS U187 ( .A0(n155), .A1(n154), .A2(n153), .B0(n152), .Y(n159) );
INVX2TS U188 ( .A(in1[5]), .Y(n156) );
XOR2X1TS U189 ( .A(n157), .B(n156), .Y(n158) );
XNOR2X1TS U190 ( .A(n159), .B(n158), .Y(res[5]) );
initial $sdf_annotate("Approx_adder_GeArN8R1P3_syn.sdf");
endmodule
|
// File: UpDown_CounterTBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 14 06:51:27 2018
`timescale 1ns/10ps
module UpDown_CounterTBV (
);
// myHDL -> Verilog Testbench for `Down_Counter` module
reg clk = 0;
reg rst = 0;
reg Trig = 0;
wire [4:0] count;
reg [0:0] Dir = 1'b0;
reg [4:0] Down_Counter0_0_1_count_i = 17;
always @(posedge clk, negedge rst) begin: UPDOWN_COUNTERTBV_DOWN_COUNTER0_0_1_LOGIC
if (rst) begin
Down_Counter0_0_1_count_i <= 17;
Trig <= 0;
end
else if ((Down_Counter0_0_1_count_i == 0)) begin
Trig <= 1;
Down_Counter0_0_1_count_i <= 17;
end
else begin
Down_Counter0_0_1_count_i <= (Down_Counter0_0_1_count_i - 1);
end
end
assign count = Down_Counter0_0_1_count_i;
always @(rst, clk, Trig, count) begin: UPDOWN_COUNTERTBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write(" ");
$write("%h", Trig);
$write(" ");
$write("%h", count);
$write("\n");
end
initial begin: UPDOWN_COUNTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: UPDOWN_COUNTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h19: begin
Dir <= 1'b1;
end
'h2a: begin
rst <= 1;
end
(-'h1): begin
rst <= 0;
end
default: begin
// pass
end
endcase
if ((i == 59)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B,
input LVPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(50.0),
.C_FCLK_CLK3_FREQ(50.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
`timescale 1ns/10ps
module PLL108_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("108.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
// Copyright (c) 2009 Bluespec, Inc. ALL RIGHTS RESERVED
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module xilinx_v5_pcie_wrapper
(
// Outputs
refclkout, cfg_to_turnoff_n, trn_tdst_dsc_n, trn_tdst_rdy_n,
trn_reof_n, cfg_interrupt_rdy_n, trn_reset_n, trn_rsrc_dsc_n,
trn_clk, trn2_clk, trn_rerrfwd_n, trn_lnk_up_n,
cfg_interrupt_msienable, trn_rsof_n, cfg_rd_wr_done_n,
trn_rsrc_rdy_n, cfg_err_cpl_rdy_n, cfg_interrupt_do,
trn_rfc_ph_av, trn_rd, trn_rbar_hit_n, cfg_dstatus, cfg_lcommand,
trn_rrem_n, cfg_status, cfg_interrupt_mmenable, pci_exp_txn,
cfg_command, pci_exp_txp, cfg_do, cfg_bus_number,
cfg_device_number, trn_rfc_npd_av, cfg_dcommand, trn_rfc_nph_av,
cfg_pcie_link_state_n, cfg_function_number, cfg_lstatus,
trn_rfc_pd_av, trn_tbuf_av,
// Inputs
trn_rcpl_streaming_n, trn_rdst_rdy_n, cfg_err_posted_n,
cfg_trn_pending_n, cfg_err_cpl_timeout_n, trn_terrfwd_n,
trn_rnp_ok_n, cfg_interrupt_n, cfg_rd_en_n, cfg_err_ur_n,
cfg_err_ecrc_n, cfg_err_cpl_abort_n, cfg_err_locked_n,
cfg_interrupt_assert_n, cfg_wr_en_n, trn_teof_n, trn_tsrc_dsc_n,
fast_train_simulation_only, cfg_err_cor_n, sys_reset_n,
trn_tsrc_rdy_n, sys_clk, cfg_err_cpl_unexpect_n, trn_tsof_n,
cfg_pm_wake_n, cfg_byte_en_n, trn_td, cfg_err_tlp_cpl_header,
cfg_dsn, trn_trem_n, cfg_di, cfg_dwaddr, pci_exp_rxn, pci_exp_rxp,
cfg_interrupt_di
);
// synthesis attribute keep of trn_rdst_rdy_n is "true";
// synthesis attribute keep of trn_tdst_dsc_n is "true";
// synthesis attribute keep of trn_tdst_rdy_n is "true";
// synthesis attribute keep of trn_terrfwd_n is "true";
// synthesis attribute keep of trn_reof_n is "true";
// synthesis attribute keep of trn_rnp_ok_n is "true";
// synthesis attribute keep of trn_reset_n is "true";
// synthesis attribute keep of trn_rsrc_dsc_n is "true";
// synthesis attribute keep of trn_rerrfwd_n is "true";
// synthesis attribute keep of trn_lnk_up_n is "true";
// synthesis attribute keep of trn_teof_n is "true";
// synthesis attribute keep of trn_rsof_n is "true";
// synthesis attribute keep of trn_tsrc_dsc_n is "true";
// synthesis attribute keep of trn_rsrc_rdy_n is "true";
// synthesis attribute keep of trn_tsrc_rdy_n is "true";
// synthesis attribute keep of trn_tsof_n is "true";
// synthesis attribute keep of trn_rfc_ph_av is "true";
// synthesis attribute keep of trn_rd is "true";
// synthesis attribute keep of trn_td is "true";
// synthesis attribute keep of trn_rbar_hit_n is "true";
// synthesis attribute keep of trn_rrem_n is "true";
// synthesis attribute keep of trn_trem_n is "true";
// synthesis attribute keep of trn_rfc_npd_av is "true";
// synthesis attribute keep of trn_rfc_nph_av is "true";
// synthesis attribute keep of trn_rfc_pd_av is "true";
// synthesis attribute keep of trn_tbuf_av is "true";
output refclkout;
input trn_rcpl_streaming_n;
output cfg_to_turnoff_n;
input trn_rdst_rdy_n;
output trn_tdst_dsc_n;
input cfg_err_posted_n;
output trn_tdst_rdy_n;
input cfg_trn_pending_n;
input cfg_err_cpl_timeout_n;
input trn_terrfwd_n;
output trn_reof_n;
input trn_rnp_ok_n;
input cfg_interrupt_n;
output cfg_interrupt_rdy_n;
input cfg_rd_en_n;
input cfg_err_ur_n;
output trn_reset_n;
input cfg_err_ecrc_n;
input cfg_err_cpl_abort_n;
output trn_rsrc_dsc_n;
output trn_clk;
output trn2_clk;
input cfg_err_locked_n;
input cfg_interrupt_assert_n;
output trn_rerrfwd_n;
input cfg_wr_en_n;
output trn_lnk_up_n;
output cfg_interrupt_msienable;
input trn_teof_n;
output trn_rsof_n;
output cfg_rd_wr_done_n;
input trn_tsrc_dsc_n;
output trn_rsrc_rdy_n;
input fast_train_simulation_only;
input cfg_err_cor_n;
input sys_reset_n;
output cfg_err_cpl_rdy_n;
input trn_tsrc_rdy_n;
input sys_clk;
input cfg_err_cpl_unexpect_n;
input trn_tsof_n;
input cfg_pm_wake_n;
input [3 : 0] cfg_byte_en_n;
output [7 : 0] cfg_interrupt_do;
output [7 : 0] trn_rfc_ph_av;
output [63 : 0] trn_rd;
input [63 : 0] trn_td;
input [47 : 0] cfg_err_tlp_cpl_header;
output [6 : 0] trn_rbar_hit_n;
output [15 : 0] cfg_dstatus;
output [15 : 0] cfg_lcommand;
input [63 : 0] cfg_dsn;
output [7 : 0] trn_rrem_n;
output [15 : 0] cfg_status;
output [2 : 0] cfg_interrupt_mmenable;
output [7 : 0] pci_exp_txn;
output [15 : 0] cfg_command;
output [7 : 0] pci_exp_txp;
input [7 : 0] trn_trem_n;
input [31 : 0] cfg_di;
output [31 : 0] cfg_do;
output [7 : 0] cfg_bus_number;
output [4 : 0] cfg_device_number;
input [9 : 0] cfg_dwaddr;
output [11 : 0] trn_rfc_npd_av;
output [15 : 0] cfg_dcommand;
output [7 : 0] trn_rfc_nph_av;
output [2 : 0] cfg_pcie_link_state_n;
output [2 : 0] cfg_function_number;
output [15 : 0] cfg_lstatus;
input [7 : 0] pci_exp_rxn;
input [7 : 0] pci_exp_rxp;
output [11 : 0] trn_rfc_pd_av;
output [3 : 0] trn_tbuf_av;
input [7 : 0] cfg_interrupt_di;
wire trn_clk_i;
// endpoint instance
endpoint_blk_plus_v1_12 ep
//pcie_endpoint endpoint
(
// Outputs
.refclkout (refclkout),
.cfg_to_turnoff_n (cfg_to_turnoff_n),
.trn_tdst_dsc_n (trn_tdst_dsc_n),
.trn_tdst_rdy_n (trn_tdst_rdy_n),
.trn_reof_n (trn_reof_n),
.cfg_interrupt_rdy_n (cfg_interrupt_rdy_n),
.trn_reset_n (trn_reset_n),
.trn_rsrc_dsc_n (trn_rsrc_dsc_n),
.trn_clk (trn_clk_i),
.trn_rerrfwd_n (trn_rerrfwd_n),
.trn_lnk_up_n (trn_lnk_up_n),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.trn_rsof_n (trn_rsof_n),
.cfg_rd_wr_done_n (cfg_rd_wr_done_n),
.trn_rsrc_rdy_n (trn_rsrc_rdy_n),
.cfg_err_cpl_rdy_n (cfg_err_cpl_rdy_n),
.cfg_interrupt_do (cfg_interrupt_do[7:0]),
.trn_rfc_ph_av (trn_rfc_ph_av[7:0]),
.trn_rd (trn_rd[63:0]),
.trn_rbar_hit_n (trn_rbar_hit_n[6:0]),
.cfg_dstatus (cfg_dstatus[15:0]),
.cfg_lcommand (cfg_lcommand[15:0]),
.trn_rrem_n (trn_rrem_n[7:0]),
.cfg_status (cfg_status[15:0]),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable[2:0]),
.pci_exp_txn (pci_exp_txn[7:0]),
.cfg_command (cfg_command[15:0]),
.pci_exp_txp (pci_exp_txp[7:0]),
.cfg_do (cfg_do[31:0]),
.cfg_bus_number (cfg_bus_number[7:0]),
.cfg_device_number (cfg_device_number[4:0]),
.trn_rfc_npd_av (trn_rfc_npd_av[11:0]),
.cfg_dcommand (cfg_dcommand[15:0]),
.trn_rfc_nph_av (trn_rfc_nph_av[7:0]),
.cfg_pcie_link_state_n (cfg_pcie_link_state_n[2:0]),
.cfg_function_number (cfg_function_number[2:0]),
.cfg_lstatus (cfg_lstatus[15:0]),
.trn_rfc_pd_av (trn_rfc_pd_av[11:0]),
.trn_tbuf_av (trn_tbuf_av[3:0]),
// Inputs
.trn_rcpl_streaming_n (trn_rcpl_streaming_n),
.trn_rdst_rdy_n (trn_rdst_rdy_n),
.cfg_err_posted_n (cfg_err_posted_n),
.cfg_trn_pending_n (cfg_trn_pending_n),
.cfg_err_cpl_timeout_n (cfg_err_cpl_timeout_n),
.trn_terrfwd_n (trn_terrfwd_n),
.trn_rnp_ok_n (trn_rnp_ok_n),
.cfg_interrupt_n (cfg_interrupt_n),
.cfg_rd_en_n (cfg_rd_en_n),
.cfg_err_ur_n (cfg_err_ur_n),
.cfg_err_ecrc_n (cfg_err_ecrc_n),
.cfg_err_cpl_abort_n (cfg_err_cpl_abort_n),
.cfg_err_locked_n (cfg_err_locked_n),
.cfg_interrupt_assert_n (cfg_interrupt_assert_n),
.cfg_wr_en_n (cfg_wr_en_n),
.trn_teof_n (trn_teof_n),
.trn_tsrc_dsc_n (trn_tsrc_dsc_n),
.fast_train_simulation_only (fast_train_simulation_only),
.cfg_err_cor_n (cfg_err_cor_n),
.sys_reset_n (sys_reset_n),
.trn_tsrc_rdy_n (trn_tsrc_rdy_n),
.sys_clk (sys_clk),
.cfg_err_cpl_unexpect_n (cfg_err_cpl_unexpect_n),
.trn_tsof_n (trn_tsof_n),
.cfg_pm_wake_n (cfg_pm_wake_n),
.cfg_byte_en_n (cfg_byte_en_n[3:0]),
.trn_td (trn_td[63:0]),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header[47:0]),
.cfg_dsn (cfg_dsn[63:0]),
.trn_trem_n (trn_trem_n[7:0]),
.cfg_di (cfg_di[31:0]),
.cfg_dwaddr (cfg_dwaddr[9:0]),
.pci_exp_rxn (pci_exp_rxn[7:0]),
.pci_exp_rxp (pci_exp_rxp[7:0]),
.cfg_interrupt_di (cfg_interrupt_di[7:0]));
// clock divider instance
DCM_ADV #(
.CLKDV_DIVIDE(2.0),
.CLKIN_PERIOD(4.0),
.DFS_FREQUENCY_MODE("HIGH"),
.DLL_FREQUENCY_MODE("HIGH"),
.SIM_DEVICE("VIRTEX5")
) divider
(
// Outputs
.CLK0 (trn_clk),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (),
.CLK90 (),
.CLKDV (trn2_clk),
.CLKFX180 (),
.CLKFX (),
.DRDY (),
.LOCKED (),
.PSDONE (),
.DO (),
// Inputs
.CLKFB (trn_clk),
.CLKIN (trn_clk_i),
.DCLK (1'b0),
.DEN (1'b0),
.DWE (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (!sys_reset_n),
.DI (16'h0000),
.DADDR (7'h0));
endmodule // xilinx_v5_pcie_wrapper
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef enum logic [4:0]
{
BIT0 = 5'd0,
BIT1 = 5'd1,
BIT2 = 5'd2
} three_t;
module t (/*AUTOARG*/);
localparam FIVE = 5;
enum { e0,
e1,
e3=3,
e5=FIVE,
e10_[2] = 10,
e20_[5:7] = 25,
e20_z,
e30_[7:5] = 30,
e30_z
} EN;
enum {
z5 = e5
} ZN;
typedef enum [2:0] { ONES=~0 } three_t;
three_t three = ONES;
var logic [ONES:0] sized_based_on_enum;
initial begin
if (e0 !== 0) $stop;
if (e1 !== 1) $stop;
if (e3 !== 3) $stop;
if (e5 !== 5) $stop;
if (e10_0 !== 10) $stop;
if (e10_1 !== 11) $stop;
if (e20_5 !== 25) $stop;
if (e20_6 !== 26) $stop;
if (e20_7 !== 27) $stop;
if (e20_z !== 28) $stop;
if (e30_7 !== 30) $stop;
if (e30_6 !== 31) $stop;
if (e30_5 !== 32) $stop;
if (e30_z !== 33) $stop;
if (z5 !== 5) $stop;
if (three != 3'b111) $stop;
if ($bits(sized_based_on_enum) != 8) $stop;
if ($bits(three_t) != 3) $stop;
if (FIVE[BIT0] != 1'b1) $stop;
if (FIVE[BIT1] != 1'b0) $stop;
if (FIVE[BIT2] != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clock, enable, and reset controls for whole system
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
//the following output is for register reads only
output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
output wire [3:0] debug_en,
output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
);
// FIXME need a separate reset for all control settings
// Master Controls assignments
//wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
assign tx_dsp_reset = master_controls[2];
assign rx_dsp_reset = master_controls[3];
// Unused - 4-7
// Strobe Generators
setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
strobe_gen da_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
strobe_gen tx_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
assign rx_sample_strobe = 1'b1;
strobe_gen decim_strobe_gen
( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
.rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
// Reset syncs for bus (usbclk) side
// The RX bus side reset isn't used, the TX bus side one may not be needed
reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
always @(posedge usbclk)
begin
tx_reset_bus_sync1 <= #1 tx_dsp_reset;
rx_reset_bus_sync1 <= #1 rx_dsp_reset;
tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
end
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
//wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
//wire [3:0] debug_en;
wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
// Upper 16 bits are mask for lower 16
always @(posedge master_clk)
if(serial_strobe)
case(serial_addr)
`FR_IO_0 : io_0_reg
<= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_1 : io_1_reg
<= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_2 : io_2_reg
<= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_3 : io_3_reg
<= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
wire transmit_now;
wire atr_ctl;
//wire [11:0] atr_tx_delay, atr_rx_delay;
//wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
//setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
assign atr_ctl = 1'b1;
atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
endmodule // master_control
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_4_V
`define SKY130_FD_SC_MS__A221O_4_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_4_V
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $
//
// $Revision: #1 $
// $Date: 2010/01/07 $
// Check in by : $Author: max $
// Author : Siew Kong NG
//
// Project : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description :
//
// RX_SYNC alignment for Alt2gxb, Alt4gxb
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
module altera_tse_gxb_aligned_rxsync (
input clk,
input reset,
input [7:0] alt_dataout,
input alt_sync,
input alt_disperr,
input alt_ctrldetect,
input alt_errdetect,
input alt_rmfifodatadeleted,
input alt_rmfifodatainserted,
input alt_runlengthviolation,
input alt_patterndetect,
input alt_runningdisp,
output reg [7:0] altpcs_dataout,
output altpcs_sync,
output reg altpcs_disperr,
output reg altpcs_ctrldetect,
output reg altpcs_errdetect,
output reg altpcs_rmfifodatadeleted,
output reg altpcs_rmfifodatainserted,
output reg altpcs_carrierdetect) ;
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
//-------------------------------------------------------------------------------
// intermediate wires
//reg altpcs_dataout
// pipelined 1
reg [7:0] alt_dataout_reg1;
reg alt_sync_reg1;
reg alt_sync_reg2;
reg alt_disperr_reg1;
reg alt_ctrldetect_reg1;
reg alt_errdetect_reg1;
reg alt_rmfifodatadeleted_reg1;
reg alt_rmfifodatainserted_reg1;
reg alt_patterndetect_reg1;
reg alt_runningdisp_reg1;
reg alt_runlengthviolation_latched;
//-------------------------------------------------------------------------------
always @(posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
// pipelined 1
alt_dataout_reg1 <= 8'h0;
alt_sync_reg1 <= 1'b0;
alt_disperr_reg1 <= 1'b0;
alt_ctrldetect_reg1 <= 1'b0;
alt_errdetect_reg1 <= 1'b0;
alt_rmfifodatadeleted_reg1 <= 1'b0;
alt_rmfifodatainserted_reg1 <= 1'b0;
alt_patterndetect_reg1 <= 1'b0;
alt_runningdisp_reg1 <= 1'b0;
end
else
begin
// pipelined 1
alt_dataout_reg1 <= alt_dataout;
alt_sync_reg1 <= alt_sync;
alt_disperr_reg1 <= alt_disperr;
alt_ctrldetect_reg1 <= alt_ctrldetect;
alt_errdetect_reg1 <= alt_errdetect;
alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;
alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
alt_patterndetect_reg1 <= alt_patterndetect;
alt_runningdisp_reg1 <= alt_runningdisp;
end
end
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX")
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
else
begin
if (alt_sync == 1'b1 )
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
end
else
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
end
end
assign altpcs_sync = alt_sync_reg1;
end
else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX")
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
alt_sync_reg2 <= 1'b0;
end
else
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
alt_sync_reg2 <= alt_sync_reg1 ;
end
end
assign altpcs_sync = alt_sync_reg2;
end
endgenerate
//latched runlength violation assertion for "carrier_detect" signal generation block
//reset the latch value after carrier_detect goes de-asserted
// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
// begin
// if (altpcs_carrierdetect == 1'b0)
// begin
// alt_runlengthviolation_latched <= 1'b0;
// end
// else
// begin
// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
// begin
// alt_runlengthviolation_latched <= 1'b1;
// end
// end
// end
// always @ (posedge reset or posedge clk)
// begin
// if (reset == 1'b1)
// begin
// alt_runlengthviolation_latched_reg <= 1'b0;
// end
// else
// begin
// alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
// end
// end
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
begin
alt_runlengthviolation_latched <= 1'b1;
end
end
end
end
// carrier_detect signal generation
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_carrierdetect <= 1'b1;
end
else
begin
if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
& alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 )) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
)
begin
altpcs_carrierdetect <= 1'b0;
end
else
begin
altpcs_carrierdetect <= 1'b1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_V |
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test checks that the upwards search for a name stops at a
* module boundary. In this example, the q variable in the instance
* "inst" of the test module should be an implicit wire, even though
* it is placed into the containing main scope that has a wire q in it.
*/
module test(p);
output p;
wire q = 1;
assign p = q;
endmodule // test
module main;
wire q = 0;
wire sig;
test inst(sig);
initial begin
#1 if (q !== 1'b0) begin
$display("FAILED -- main.q == %b", q);
$finish;
end
if (sig !== 1'b1) begin
$display("FAILED -- main.test.q == %b", sig);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module adc_interface
(input clock, input reset, input enable,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input wire [11:0] rx_a_b, input wire [11:0] rx_b_b,
output wire [31:0] rssi_0, output wire [31:0] rssi_1, output wire [31:0] rssi_2, output wire [31:0] rssi_3,
output reg [15:0] ddc0_in_i, output reg [15:0] ddc0_in_q,
output reg [15:0] ddc1_in_i, output reg [15:0] ddc1_in_q,
output reg [15:0] ddc2_in_i, output reg [15:0] ddc2_in_q,
output reg [15:0] ddc3_in_i, output reg [15:0] ddc3_in_q,
output wire [3:0] rx_numchan);
// Buffer at input to chip
reg [11:0] adc0,adc1,adc2,adc3;
always @(posedge clock)
begin
adc0 <= #1 rx_a_a;
adc1 <= #1 rx_b_a;
adc2 <= #1 rx_a_b;
adc3 <= #1 rx_b_b;
end
// then scale and subtract dc offset
wire [3:0] dco_en;
wire [15:0] adc0_corr,adc1_corr,adc2_corr,adc3_corr;
setting_reg #(`FR_DC_OFFSET_CL_EN) sr_dco_en(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(dco_en));
rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_in({adc1[11],adc1,3'b0}),.adc_out(adc1_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_in({adc2[11],adc2,3'b0}),.adc_out(adc2_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_in({adc3[11],adc3,3'b0}),.adc_out(adc3_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
// Level sensing for AGC
rssi rssi_block_0 (.clock(clock),.reset(reset),.enable(enable),.adc(adc0),.rssi(rssi_0[15:0]),.over_count(rssi_0[31:16]));
rssi rssi_block_1 (.clock(clock),.reset(reset),.enable(enable),.adc(adc1),.rssi(rssi_1[15:0]),.over_count(rssi_1[31:16]));
rssi rssi_block_2 (.clock(clock),.reset(reset),.enable(enable),.adc(adc2),.rssi(rssi_2[15:0]),.over_count(rssi_2[31:16]));
rssi rssi_block_3 (.clock(clock),.reset(reset),.enable(enable),.adc(adc3),.rssi(rssi_3[15:0]),.over_count(rssi_3[31:16]));
// And mux to the appropriate outputs
wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux;
wire rx_realsignals;
setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
.in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
assign rx_numchan[0] = 1'b0;
always @(posedge clock)
begin
ddc0_in_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? adc3_corr : adc2_corr) : (ddc0mux[0] ? adc1_corr : adc0_corr);
ddc0_in_q <= #1 rx_realsignals ? 16'd0 : ddc0mux[3] ? (ddc0mux[2] ? adc3_corr : adc2_corr) : (ddc0mux[2] ? adc1_corr : adc0_corr);
ddc1_in_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? adc3_corr : adc2_corr) : (ddc1mux[0] ? adc1_corr : adc0_corr);
ddc1_in_q <= #1 rx_realsignals ? 16'd0 : ddc1mux[3] ? (ddc1mux[2] ? adc3_corr : adc2_corr) : (ddc1mux[2] ? adc1_corr : adc0_corr);
ddc2_in_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? adc3_corr : adc2_corr) : (ddc2mux[0] ? adc1_corr : adc0_corr);
ddc2_in_q <= #1 rx_realsignals ? 16'd0 : ddc2mux[3] ? (ddc2mux[2] ? adc3_corr : adc2_corr) : (ddc2mux[2] ? adc1_corr : adc0_corr);
ddc3_in_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? adc3_corr : adc2_corr) : (ddc3mux[0] ? adc1_corr : adc0_corr);
ddc3_in_q <= #1 rx_realsignals ? 16'd0 : ddc3mux[3] ? (ddc3mux[2] ? adc3_corr : adc2_corr) : (ddc3mux[2] ? adc1_corr : adc0_corr);
end
endmodule // adc_interface
|
// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: coincidence_counter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module coincidence_counter (
aclr,
clock,
cnt_en,
q);
input aclr;
input clock;
input cnt_en;
output [21:0] q;
wire [21:0] sub_wire0;
wire [21:0] q = sub_wire0[21:0];
lpm_counter LPM_COUNTER_component (
.aclr (aclr),
.clock (clock),
.cnt_en (cnt_en),
.q (sub_wire0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.clk_en (1'b1),
.cout (),
.data ({22{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 22;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "22"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "22"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: q 0 0 22 0 OUTPUT NODEFVAL "q[21..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: q 0 0 22 0 @q 0 0 22 0
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: x^16 + x^15 + x^2 + 1
// * data width: 72
//
// Info : [email protected]
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module CRC16_D72(
nextCRC16_D72,
Data,
crc
);
output reg [15:0] nextCRC16_D72;
input wire [71:0] Data;
input wire [15:0] crc;
reg [71:0] d;
reg [15:0] c;
reg [15:0] newcrc;
always @ (*)
begin
d = Data;
c = crc;
newcrc[0] = d[71] ^ d[69] ^ d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[43] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[12] ^ c[13] ^ c[15];
newcrc[1] = d[70] ^ d[69] ^ d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[44] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[12] ^ c[13] ^ c[14];
newcrc[2] = d[70] ^ d[61] ^ d[60] ^ d[57] ^ d[56] ^ d[46] ^ d[42] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[16] ^ d[14] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[4] ^ c[5] ^ c[14];
newcrc[3] = d[71] ^ d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[47] ^ d[43] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[17] ^ d[15] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[5] ^ c[6] ^ c[15];
newcrc[4] = d[63] ^ d[62] ^ d[59] ^ d[58] ^ d[48] ^ d[44] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[18] ^ d[16] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[6] ^ c[7];
newcrc[5] = d[64] ^ d[63] ^ d[60] ^ d[59] ^ d[49] ^ d[45] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[19] ^ d[17] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[7] ^ c[8];
newcrc[6] = d[65] ^ d[64] ^ d[61] ^ d[60] ^ d[50] ^ d[46] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[20] ^ d[18] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[8] ^ c[9];
newcrc[7] = d[66] ^ d[65] ^ d[62] ^ d[61] ^ d[51] ^ d[47] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[21] ^ d[19] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[9] ^ c[10];
newcrc[8] = d[67] ^ d[66] ^ d[63] ^ d[62] ^ d[52] ^ d[48] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[22] ^ d[20] ^ d[7] ^ d[6] ^ c[6] ^ c[7] ^ c[10] ^ c[11];
newcrc[9] = d[68] ^ d[67] ^ d[64] ^ d[63] ^ d[53] ^ d[49] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[23] ^ d[21] ^ d[8] ^ d[7] ^ c[7] ^ c[8] ^ c[11] ^ c[12];
newcrc[10] = d[69] ^ d[68] ^ d[65] ^ d[64] ^ d[54] ^ d[50] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[24] ^ d[22] ^ d[9] ^ d[8] ^ c[8] ^ c[9] ^ c[12] ^ c[13];
newcrc[11] = d[70] ^ d[69] ^ d[66] ^ d[65] ^ d[55] ^ d[51] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[25] ^ d[23] ^ d[10] ^ d[9] ^ c[9] ^ c[10] ^ c[13] ^ c[14];
newcrc[12] = d[71] ^ d[70] ^ d[67] ^ d[66] ^ d[56] ^ d[52] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[26] ^ d[24] ^ d[11] ^ d[10] ^ c[0] ^ c[10] ^ c[11] ^ c[14] ^ c[15];
newcrc[13] = d[71] ^ d[68] ^ d[67] ^ d[57] ^ d[53] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[27] ^ d[25] ^ d[12] ^ d[11] ^ c[1] ^ c[11] ^ c[12] ^ c[15];
newcrc[14] = d[69] ^ d[68] ^ d[58] ^ d[54] ^ d[43] ^ d[42] ^ d[41] ^ d[40] ^ d[28] ^ d[26] ^ d[13] ^ d[12] ^ c[2] ^ c[12] ^ c[13];
newcrc[15] = d[71] ^ d[70] ^ d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[44] ^ d[42] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[12] ^ c[14] ^ c[15];
nextCRC16_D72 = newcrc;
end
endmodule
|
//======================================================================
//
// hc.v
// ----
// Top level wrapper for the HC stream cipher.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2017, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module hc(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_CONFIG = 8'h0a;
localparam CTRL_KEYLEN_BIT = 0;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_IV0 = 8'h20;
localparam ADDR_IV7 = 8'h27;
localparam ADDR_RESULT = 8'h40;
localparam CORE_NAME0 = 32'h68632020; // "hc "
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h302e3031; // "0.01"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg keylen_reg;
reg config_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [31 : 0] iv_reg [0 : 7];
reg iv_we;
reg [31 : 0] result_reg;
reg valid_reg;
reg ready_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_init;
wire core_next;
wire core_ready;
wire [255 : 0] core_key;
wire [255 : 0] core_iv;
wire core_keylen;
wire [31 : 0] core_result;
wire core_valid;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_iv = {iv_reg[0], iv_reg[1], iv_reg[2], iv_reg[3],
iv_reg[4], iv_reg[5], iv_reg[6], iv_reg[7]};
assign core_init = init_reg;
assign core_next = next_reg;
assign core_keylen = keylen_reg;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
hc_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.ready(core_ready),
.iv(core_iv),
.key(core_key),
.keylen(keylen_reg),
.result(core_result),
.result_valid(core_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 8 ; i = i + 1)
begin
key_reg[i] <= 32'h0;
iv_reg[i] <= 32'h0;
end
init_reg <= 0;
next_reg <= 0;
keylen_reg <= 0;
result_reg <= 32'h0;
valid_reg <= 0;
ready_reg <= 0;
end
else
begin
ready_reg <= core_ready;
valid_reg <= core_valid;
result_reg <= core_result;
init_reg <= init_new;
next_reg <= next_new;
if (config_we)
keylen_reg <= write_data[CTRL_KEYLEN_BIT];
if (key_we)
key_reg[address[2 : 0]] <= write_data;
if (iv_we)
iv_reg[address[2 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 0;
next_new = 0;
config_we = 0;
key_we = 0;
iv_we = 0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
if (address == ADDR_CONFIG)
config_we = 1;
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1;
if ((address >= ADDR_IV0) && (address <= ADDR_IV7))
iv_we = 1;
end // if (we)
else
begin
case (address)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {30'h0, next_reg, init_reg};
ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
ADDR_CONFIG: tmp_read_data = {31'h0, keylen_reg};
ADDR_RESULT: tmp_read_data = result_reg;
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // hc
//======================================================================
// EOF hc.v
//======================================================================
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Packets to MM Master Transaction Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
// --------------------------------------------------------------------------------
//| Fast Transaction Master
// --------------------------------------------------------------------------------
module altera_avalon_packets_to_master (
// Interface: clk
input wire clk,
input wire reset_n,
// Interface: ST in
output wire in_ready,
input wire in_valid,
input wire [ 7: 0] in_data,
input wire in_startofpacket,
input wire in_endofpacket,
// Interface: ST out
input wire out_ready,
output wire out_valid,
output wire [ 7: 0] out_data,
output wire out_startofpacket,
output wire out_endofpacket,
// Interface: MM out
output wire [31: 0] address,
input wire [31: 0] readdata,
output wire read,
output wire write,
output wire [ 3: 0] byteenable,
output wire [31: 0] writedata,
input wire waitrequest,
input wire readdatavalid
);
wire [ 35: 0] fifo_readdata;
wire fifo_read;
wire fifo_empty;
wire [ 35: 0] fifo_writedata;
wire fifo_write;
wire fifo_write_waitrequest;
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
parameter FAST_VER = 0;
generate
if (FAST_VER) begin
packets_to_fifo p2f (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.fifo_writedata (fifo_writedata),
.fifo_write (fifo_write),
.fifo_write_waitrequest (fifo_write_waitrequest)
);
fifo_to_packet f2p (
.clk (clk),
.reset_n (reset_n),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket),
.fifo_readdata (fifo_readdata),
.fifo_read (fifo_read),
.fifo_empty (fifo_empty)
);
fifo_buffer #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) fb (
.wrclock (clk),
.reset_n (reset_n),
.avalonmm_write_slave_writedata (fifo_writedata),
.avalonmm_write_slave_write (fifo_write),
.avalonmm_write_slave_waitrequest (fifo_write_waitrequest),
.avalonmm_read_slave_readdata (fifo_readdata),
.avalonmm_read_slave_read (fifo_read),
.avalonmm_read_slave_waitrequest (fifo_empty)
);
end else begin
packets_to_master p2m (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket)
);
end
endgenerate
endmodule
module packets_to_fifo (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid,
// Interface: FIFO
// FIFO data format:
// | sop, eop, [1:0]valid, [31:0]data |
output reg [ 35: 0] fifo_writedata,
output reg fifo_write,
input wire fifo_write_waitrequest
);
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte, byte_avail;
reg [ 15: 0] counter;
reg [ 31: 0] read_data_buffer;
reg [ 31: 0] fifo_data_buffer;
reg in_ready_0;
reg first_trans, last_trans, fifo_sop;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
READ_ASSERT = 4'b1010,
READ_CMD_WAIT = 4'b1011,
READ_DATA_WAIT = 4'b1100,
PUSH_FIFO = 4'b1101,
PUSH_FIFO_WAIT = 4'b1110,
FIFO_CMD_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @* begin
in_ready = in_ready_0;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
fifo_writedata <= 'b0;
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
byte_avail <= 'b0;
fifo_data_buffer <= 'b0;
end else begin
address[1:0] <= 'b0;
in_ready_0 <= 1'b0;
if (counter > 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
in_ready_0 <= !fifo_write_waitrequest;
fifo_write <= 1'b0;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1'b1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 1'b0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1'b1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1'b1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1'b1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1'b1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 1'b0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
read <= 1'b1;
fifo_write <= 1'b0;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
// number of valid byte
case (byteenable)
4'b0000 : byte_avail <= 1'b0;
4'b0001 : byte_avail <= 1'b0;
4'b0010 : byte_avail <= 1'b0;
4'b0100 : byte_avail <= 1'b0;
4'b1000 : byte_avail <= 1'b0;
4'b0011 : byte_avail <= 1'b1;
4'b0110 : byte_avail <= 1'b1;
4'b1100 : byte_avail <= 1'b1;
4'b0111 : byte_avail <= 2'h2;
4'b1110 : byte_avail <= 2'h2;
default : byte_avail <= 2'h3;
endcase
read_data_buffer <= readdata;
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= PUSH_FIFO;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata;
if (readdatavalid) begin
state <= PUSH_FIFO;
end
end
PUSH_FIFO : begin
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
if (first_trans) begin
first_trans <= 1'b0;
fifo_sop <= 1'b1;
end
case (current_byte)
3 : begin
fifo_data_buffer <= read_data_buffer >> 24;
counter <= counter - 1'b1;
end
2 : begin
fifo_data_buffer <= read_data_buffer >> 16;
if (counter == 1) counter <= 0;
else counter <= counter - 2'h2;
end
1 : begin
fifo_data_buffer <= read_data_buffer >> 8;
if (counter < 3) counter <= 0;
else counter <= counter - 2'h3;
end
default : begin
fifo_data_buffer <= read_data_buffer;
if (counter < 4) counter <= 0;
else counter <= counter - 3'h4;
end
endcase
current_byte <= 0;
state <= PUSH_FIFO_WAIT;
end
PUSH_FIFO_WAIT : begin
// pushd return packet with data
fifo_write <= 1'b1;
fifo_writedata <= {fifo_sop,(counter == 0)?1'b1:1'b0,byte_avail,fifo_data_buffer};
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 0) begin
state <= FIFO_CMD_WAIT;
end else if (command[2]== 1'b1) begin
//increment address, but word-align it
state <= FIFO_CMD_WAIT;
address[31:2] <= (address[31:2] + 1'b1);
end
end
FIFO_CMD_WAIT : begin
// back pressure if fifo_write_waitrequest
if (!fifo_write_waitrequest) begin
if (counter == 0) begin
state <= READY;
end else begin
state <= READ_ASSERT;
end
fifo_write <= 1'b0;
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= !fifo_write_waitrequest;
end
end // end else
end // end always block
endmodule
// --------------------------------------------------------------------------------
// FIFO buffer
// --------------------------------------------------------------------------------
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input aclr;
input clock;
input [ 35: 0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.lpm_numwords = FIFO_DEPTHS,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 36,
single_clock_fifo.lpm_widthu = FIFO_WIDTHU,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "OFF";
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input clock;
input [ 35: 0] data;
input rdreq;
input reset_n;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
wire wrreq_valid;
//the_scfifo, which is an e_instance
fifo_buffer_single_clock_fifo #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo (
.aclr (~reset_n),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq_valid)
);
assign wrreq_valid = wrreq & ~full;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer (
// inputs:
avalonmm_read_slave_read,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
reset_n,
wrclock,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonmm_write_slave_waitrequest
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output [ 35: 0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonmm_write_slave_waitrequest;
input avalonmm_read_slave_read;
input avalonmm_write_slave_write;
input [ 35: 0] avalonmm_write_slave_writedata;
input reset_n;
input wrclock;
wire [ 35: 0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire avalonmm_write_slave_waitrequest;
wire clock;
wire [ 35: 0] data;
wire empty;
wire full;
wire [ 35: 0] q;
wire rdreq;
wire wrreq;
//the_scfifo_with_controls, which is an e_instance
fifo_buffer_scfifo_with_controls #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo_with_controls
(
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n (reset_n),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
//out, which is an e_avalon_slave
assign data = avalonmm_write_slave_writedata;
assign wrreq = avalonmm_write_slave_write;
assign avalonmm_read_slave_readdata = q;
assign rdreq = avalonmm_read_slave_read;
assign clock = wrclock;
assign avalonmm_write_slave_waitrequest = full;
assign avalonmm_read_slave_waitrequest = empty;
endmodule
// --------------------------------------------------------------------------------
// fifo_buffer to Avalon-ST interface
// --------------------------------------------------------------------------------
module fifo_to_packet (
// Interface: clk
input clk,
input reset_n,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: FIFO in
input [ 35: 0] fifo_readdata,
output reg fifo_read,
input fifo_empty
);
reg [ 1: 0] state;
reg enable, sent_all;
reg [ 1: 0] current_byte, byte_end;
reg first_trans, last_trans;
reg [ 23:0] fifo_data_buffer;
localparam POP_FIFO = 2'b00,
POP_FIFO_WAIT = 2'b01,
FIFO_DATA_WAIT = 2'b10,
READ_SEND_ISSUE = 2'b11;
always @* begin
enable = (!fifo_empty & sent_all);
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
fifo_data_buffer <= 'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
state <= 'b0;
fifo_read <= 1'b0;
current_byte <= 'b0;
byte_end <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
sent_all <= 1'b1;
end else begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
end
case (state)
POP_FIFO : begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
byte_end <= 'b0;
fifo_read <= 1'b0;
sent_all <= 1'b1;
end
// start poping fifo after all data sent and data available
if (enable) begin
fifo_read <= 1'b1;
out_valid <= 1'b0;
state <= POP_FIFO_WAIT;
end
end
POP_FIFO_WAIT : begin
//fifo latency of 1
fifo_read <= 1'b0;
state <= FIFO_DATA_WAIT;
end
FIFO_DATA_WAIT : begin
sent_all <= 1'b0;
first_trans <= fifo_readdata[35];
last_trans <= fifo_readdata[34];
out_data <= fifo_readdata[7:0];
fifo_data_buffer <= fifo_readdata[31:8];
byte_end <= fifo_readdata[33:32];
current_byte <= 1'b1;
out_valid <= 1'b1;
// first byte sop eop handling
if (fifo_readdata[35] & fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
last_trans <= 1'b0;
out_startofpacket <= 1'b1;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35]) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= READ_SEND_ISSUE;
end else if (fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
sent_all <= 1'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
// last byte
if (last_trans & (current_byte == byte_end)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end
case (current_byte)
3: begin
out_data <= fifo_data_buffer[23:16];
end
2: begin
out_data <= fifo_data_buffer[15:8];
end
1: begin
out_data <= fifo_data_buffer[7:0];
end
default: begin
//out_data <= fifo_readdata[7:0];
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == byte_end) begin
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
end
endcase
end
end
endmodule
// --------------------------------------------------------------------------------
//| Economy Transaction Master
// --------------------------------------------------------------------------------
module packets_to_master (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid
);
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte; //, result_byte;
reg [ 15: 0] counter;
reg [ 23: 0] read_data_buffer;
reg in_ready_0;
reg first_trans, last_trans;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
RETURN_PACKET = 4'b1010,
READ_ASSERT = 4'b1011,
READ_CMD_WAIT = 4'b1100,
READ_DATA_WAIT = 4'b1101,
READ_SEND_ISSUE= 4'b1110,
READ_SEND_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @*
// in_ready = in_ready_0 & out_ready;
in_ready = in_ready_0;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
// result_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
end else begin
address[1:0] <= 'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
end
in_ready_0 <= 1'b0;
if (counter >= 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
out_valid <= 1'b0;
in_ready_0 <= 1'b1;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
RETURN_PACKET : begin
out_valid <= 1'b1;
if (out_ready) begin
case (current_byte)
// 0: begin
// out_startofpacket <= 1'b1;
// out_data <= (8'h80 | command);
// end
0: begin
out_data <= 8'b0;
end
1: begin
out_data <= counter[15:8];
end
2: begin
out_endofpacket <= 1'b1;
out_data <= counter[7:0];
end
default: begin
// out_data <= 8'b0;
// out_startofpacket <= 1'b0;
// out_endofpacket <= 1'b0;
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == 3) begin
state <= READY;
out_valid <= 1'b0;
end
else state <= RETURN_PACKET;
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
// byteenable <= unshifted_byteenable << current_byte;
read <= 1;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
out_startofpacket <= 'h0;
out_endofpacket <= 'h0;
if (counter == 1) begin
out_endofpacket <= 1'b1;
end
if (first_trans) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
end
case (current_byte)
3: begin
out_data <= read_data_buffer[23:16];
end
2: begin
out_data <= read_data_buffer[15:8];
end
1: begin
out_data <= read_data_buffer[7:0];
end
default: begin
out_data <= out_data;
end
endcase
state <= READ_SEND_WAIT;
end
READ_SEND_WAIT : begin
out_valid <= 1'b1;
if (out_ready) begin
counter <= counter - 1'b1;
current_byte <= current_byte + 1'b1;
out_valid <= 1'b0;
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 1) begin
state <= READY;
// end of current word, but we have more bytes to
// read - go back to READ_ASSERT
end else if (current_byte == 3) begin
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
state <= READ_ASSERT;
// continue sending current word
end else begin
state <= READ_SEND_ISSUE;
end
//maybe add in_ready_0 here so we are ready to go
//right away
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= 1'b1;
end
end // end else
end // end always block
endmodule
|
/* note for avalon interface
bus type: nagtive
read legacy = 0 (to consistent to FIFO)
*/
module adc_ltc2308_fifo(
// avalon slave port
slave_clk,
slave_reset_n,
slave_chipselect_n,
slave_addr,
slave_read_n,
slave_wrtie_n,
slave_readdata,
slave_wriredata,
adc_clk, // max 40mhz
// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);
// avalon slave port
input slave_clk;
input slave_reset_n;
input slave_chipselect_n;
input slave_addr;
input slave_read_n;
input slave_wrtie_n;
output reg [15:0] slave_readdata;
input [15:0] slave_wriredata;
input adc_clk;
output ADC_CONVST;
output ADC_SCK;
output ADC_SDI;
input ADC_SDO;
////////////////////////////////////
// avalon slave port
`define WRITE_REG_START_CH 0
`define WRITE_REG_MEASURE_NUM 1
// write for control
reg measure_fifo_start;
reg [11:0] measure_fifo_num;
reg [2:0] measure_fifo_ch;
always @ (posedge slave_clk or negedge slave_reset_n)
begin
if (~slave_reset_n)
measure_fifo_start <= 1'b0;
else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_START_CH)
{measure_fifo_ch, measure_fifo_start} <= slave_wriredata[3:0];
else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_MEASURE_NUM)
measure_fifo_num <= slave_wriredata;
end
///////////////////////
// read
`define READ_REG_MEASURE_DONE 0
`define READ_REG_ADC_VALUE 1
wire slave_read_status;
wire slave_read_data;
assign slave_read_status = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_MEASURE_DONE) ?1'b1:1'b0;
assign slave_read_data = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_ADC_VALUE) ?1'b1:1'b0;
reg measure_fifo_done;
always @ (posedge slave_clk)
begin
if (slave_read_status)
slave_readdata <= {11'b0, measure_fifo_done};
else if (slave_read_data)
slave_readdata <= fifo_q;
end
reg pre_slave_read_data;
always @ (posedge slave_clk or negedge slave_reset_n)
begin
if (~slave_reset_n)
pre_slave_read_data <= 1'b0;
else
pre_slave_read_data <= slave_read_data;
end
// read ack for adc data. (note. Slave_read_data is read lency=2, so slave_read_data is assert two clock)
assign fifo_rdreq = (pre_slave_read_data & slave_read_data)?1'b1:1'b0;
////////////////////////////////////
// create triggle message: adc_reset_n
reg pre_measure_fifo_start;
always @ (posedge adc_clk)
begin
pre_measure_fifo_start <= measure_fifo_start;
end
wire adc_reset_n;
assign adc_reset_n = (~pre_measure_fifo_start & measure_fifo_start)?1'b0:1'b1;
////////////////////////////////////
// control measure_start
reg [11:0] measure_count;
reg config_first;
reg wait_measure_done;
reg measure_start;
wire measure_done;
wire [11:0] measure_dataread;
always @ (posedge adc_clk or negedge adc_reset_n)
begin
if (~adc_reset_n)
begin
measure_start <= 1'b0;
config_first <= 1'b1;
measure_count <= 0;
measure_fifo_done <= 1'b0;
wait_measure_done <= 1'b0;
end
else if (~measure_fifo_done & ~measure_start & ~wait_measure_done)
begin
measure_start <= 1'b1;
wait_measure_done <= 1'b1;
end
else if (wait_measure_done) // && measure_start)
begin
measure_start <= 1'b0;
if (measure_done)
begin
if (config_first)
config_first <= 1'b0;
else
begin // read data and save into fifo
if (measure_count < measure_fifo_num) // && ~fifo_wrfull)
begin
measure_count <= measure_count + 1;
wait_measure_done <= 1'b0;
end
else
measure_fifo_done <= 1'b1;
end
end
end
end
// write data into fifo
reg pre_measure_done;
always @ (posedge adc_clk or negedge adc_reset_n)
begin
if (~adc_reset_n)
pre_measure_done <= 1'b0;
else
pre_measure_done <= measure_done;
end
assign fifo_wrreq = (~pre_measure_done & measure_done & ~config_first)?1'b1:1'b0;
///////////////////////////////////////
// SPI
adc_ltc2308 adc_ltc2308_inst(
.clk(adc_clk), // max 40mhz
// start measure
.measure_start(measure_start), // posedge triggle
.measure_done(measure_done),
.measure_ch(measure_fifo_ch),
.measure_dataread(measure_dataread),
// adc interface
.ADC_CONVST(ADC_CONVST),
.ADC_SCK(ADC_SCK),
.ADC_SDI(ADC_SDI),
.ADC_SDO(ADC_SDO)
);
///////////////////////////////////////
// FIFO
wire fifo_wrfull;
wire fifo_rdempty;
wire fifo_wrreq;
wire [11:0] fifo_q;
wire fifo_rdreq;
adc_data_fifo adc_data_fifo_inst(
.aclr(~adc_reset_n),
.data(measure_dataread),
.rdclk(slave_clk),
.rdreq(fifo_rdreq),
.wrclk(adc_clk),
.wrreq(fifo_wrreq),
.q(fifo_q),
.rdempty(fifo_rdempty),
.wrfull(fifo_wrfull)
);
endmodule
|
(** * References: Typing Mutable References *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
Require Export Smallstep.
(** So far, we have considered a variety of _pure_ language features,
including functional abstraction, basic types such as numbers and
booleans, and structured types such as records and variants. These
features form the backbone of most programming languages -- including
purely functional languages such as Haskell, "mostly functional"
languages such as ML, imperative languages such as C, and
object-oriented languages such as Java.
Most practical programming languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, evaluation of terms in these languages may assign to
mutable variables (reference cells, arrays, mutable record fields,
etc.), perform input and output to files, displays, or network
connections, make non-local transfers of control via exceptions,
jumps, or continuations, engage in inter-process synchronization
and communication, and so on. In the literature on programming
languages, such "side effects" of computation are more generally
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational
effect -- mutable references -- can be added to the calculi we have
studied. The main extension will be dealing explicitly with a
_store_ (or _heap_). This extension is straightforward to define;
the most interesting part is the refinement we need to make to the
statement of the type preservation theorem. *)
(* ###################################################################### *)
(** * Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language is a rare
exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] directly to assign a new
value to the cell that it points to (by writing [y:=84]), but we
cannot use it directly as an argument to an operation like [+].
Instead, we must explicitly _dereference_ it, writing [!y] to
obtain its current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a mutable
cell, and the operation of dereferencing a variable to obtain its
current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit.
In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
(* ###################################################################### *)
(** * Syntax *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and evaluates to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] evaluates
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. However, [r := 7]
evaluates to the trivial value [unit]; it exists only to have
the _side effect_ of modifying the contents of a cell. *)
(* ################################### *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. To the base natural number type and arrow types
we need to add two more types to deal with references. First, we
need the _unit type_, which we will use as the result type of an
assignment operation. We then add _reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references which
point to a cell holding values of type [T].
T ::= Nat
| Unit
| T -> T
| Ref T
*)
Inductive ty : Type :=
| TNat : ty
| TUnit : ty
| TArrow : ty -> ty -> ty
| TRef : ty -> ty.
(* ################################### *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
<<
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
>>
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* New terms: *)
| tunit : tm
| tref : tm -> tm
| tderef : tm -> tm
| tassign : tm -> tm -> tm
| tloc : nat -> tm.
(** Intuitively...
- [ref t] (formally, [tref t]) allocates a new reference cell
with the value [t] and evaluates to the location of the newly
allocated cell;
- [!t] (formally, [tderef t]) evaluates to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [tassign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [tloc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. It
would be easy to do so, since there are no very interesting
interactions between those features and references. *)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tzero"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tunit" | Case_aux c "tref"
| Case_aux c "tderef" | Case_aux c "tassign"
| Case_aux c "tloc" ].
Module ExampleVariables.
Definition x := Id 0.
Definition y := Id 1.
Definition r := Id 2.
Definition s := Id 3.
End ExampleVariables.
(* ################################### *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T11
--------------------- (T_Deref)
Gamma |- !t1 : T11
Gamma |- t1 : Ref T11
Gamma |- t2 : T11
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ################################### *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall n,
value (tnat n)
| v_unit :
value tunit
| v_loc : forall l,
value (tloc l).
Hint Constructors value.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tabs x' T t1 =>
if eq_id_dec x x' then t else tabs x' T (subst x s t1)
| tnat n =>
t
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
t
| tref t1 =>
tref (subst x s t1)
| tderef t1 =>
tderef (subst x s t1)
| tassign t1 t2 =>
tassign (subst x s t1) (subst x s t2)
| tloc _ =>
t
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** * Pragmatics *)
(* ################################### *)
(** ** Side Effects and Sequencing *)
(** The fact that the result of an assignment expression is the
trivial value [unit] allows us to use a nice abbreviation for
_sequencing_. For example, we can write
<<
r:=succ(!r); !r
>>
as an abbreviation for
<<
(\x:Unit. !r) (r := succ(!r)).
>>
This has the effect of evaluating two expressions in order and
returning the value of the second. Restricting the type of the first
expression to [Unit] helps the typechecker to catch some silly
errors by permitting us to throw away the first value only if it
is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
<<
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
>>
*)
(** Formally, we introduce sequencing as a "derived form"
[tseq] that expands into an abstraction and an application. *)
Definition tseq t1 t2 :=
tapp (tabs (Id 0) TUnit t2) t1.
(* ################################### *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to [r] and the _cell_ in the store that
is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after evaluating
<<
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
>>
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
<<
r := 5; r := !s
>>
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
<<
r := !s
>>
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ################################### *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
<<
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
>>
*)
(** Note that, since their argument types are [Unit], the
abstractions in the definitions of [incc] and [decc] are not
providing any useful information to the bodies of the
functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose is to
"slow down" the execution of the function bodies: since function
abstractions are values, the two [let]s are executed simply by
binding these functions to the names [incc] and [decc], rather
than by actually incrementing or decrementing [c]. Later, each
call to one of these functions results in its body being executed
once and performing the appropriate mutation on [c]. Such
functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
<<
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
>>
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
<<
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
>>
*)
(** **** Exercise: 1 star (store_draw) *)
(** Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(* c1.c = ref 0 / c2.c = ref 0 *)
(* ################################### *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give a (not very efficient) implementation of arrays
of numbers, as follows. Write [NatArray] for the type
[Ref (Nat->Nat)].
Recall the [equal] function from the [MoreStlc] chapter:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
Now, to build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
<<
newarray = \_:Unit. ref (\n:Nat.0)
>>
To look up an element of an array, we simply apply
the function to the desired index.
<<
lookup = \a:NatArray. \n:Nat. (!a) n
>>
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], and on all other indices passes the
lookup to the function that was previously stored in the reference.
<<
update = \a:NatArray. \m:Nat. \v:Nat.
let oldf = !a in
a := (\n:Nat. if equal m n then v else oldf n);
>>
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars (compact_update) *)
(** If we defined [update] more compactly like this
<<
update = \a:NatArray. \m:Nat. \v:Nat.
a := (\n:Nat. if equal m n then v else (!a) n)
>>
would it behave the same? *)
(* I think so! *)
(** [] *)
(* ################################### *)
(** ** Null References *)
(** There is one more difference between our references and C-style
mutable variables: in C-like languages, variables holding pointers
into the heap may sometimes have the value [NULL]. Dereferencing
such a "null pointer" is an error, and results in an
exception (Java) or in termination of the program (C).
Null pointers cause significant trouble in C-like languages: the
fact that any pointer might be null means that any dereference
operation in the program can potentially fail. However, even in
ML-like languages, there are occasionally situations where we may
or may not have a valid pointer in our hands. Fortunately, there
is no need to extend the basic mechanisms of references to achieve
this: the sum types introduced in the [MoreStlc] chapter already
give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter. Define [Option T] to be an
abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ################################### *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, collecting and reusing cells that can no longer be
reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. The reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Nat] and the
other with type [Ref Bool]. *)
(** **** Exercise: 1 star (type_safety_violation) *)
(** Show how this can lead to a violation of type safety. *)
(* Above example itself... *)
(** [] *)
(* ###################################################################### *)
(** * Operational Semantics *)
(* ################################### *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that evaluating a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming language implementations is
essentially just a big array of bytes. The run-time system keeps track
of which parts of this array are currently in use; when we need to
allocate a new reference cell, we allocate a large enough segment from
the free region of the store (4 bytes for integer cells, 8 bytes for
cells storing [Float]s, etc.), mark it as being used, and return the
index (typically, a 32- or 64-bit integer) of the start of the newly
allocated region. These indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is a bit more convenient
to use numbers.) We'll use the word _location_ instead of
_reference_ or _pointer_ from now on to emphasize this abstract
quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type safety violations. *)
(* ################################### *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
IMP, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in IMP, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we couldn't use this representation
before is that, in IMP, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [tref t1], which puts the value of [t1]
in a new reference cell and evaluates to the location of the newly
created reference cell. When evaluating such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
it will of course require some work!) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st tunit.
(** To add a new reference cell to the store, we use [snoc]. *)
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
(** We will need some boring lemmas about [snoc]. The proofs are
routine inductions. *)
Lemma length_snoc : forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ]. Qed.
(* The "solve by inversion" tactic is explained in Stlc.v. *)
Lemma nth_lt_snoc : forall A (l:list A) x d n,
n < length l ->
nth n l d = nth n (snoc l x) d.
Proof.
induction l as [|a l']; intros; try solve by inversion.
Case "l = a :: l'".
destruct n; auto.
simpl. apply IHl'.
simpl in H. apply lt_S_n in H. assumption.
Qed.
Lemma nth_eq_snoc : forall A (l:list A) x d,
nth (length l) (snoc l x) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** Of course, we also need some boring lemmas about [replace], which
are also fairly straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x nil = nil.
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
Case "st = []".
inversion Hlen.
Case "st = t' :: st'".
destruct l; simpl...
apply IHst'. simpl in Hlen. omega.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
Case "l1 = 0".
destruct st.
SCase "st = []". rewrite replace_nil...
SCase "st = _ :: _". destruct l2... contradict Hneq...
Case "l1 = S l1'".
destruct st as [|t2 st2].
SCase "st = []". destruct l2...
SCase "st = t2 :: st2".
destruct l2...
simpl; apply IHl1'...
Qed.
(* ################################### *)
(** ** Reduction *)
(** Next, we need to extend our operational semantics to take stores
into account. Since the result of evaluating an expression will
in general depend on the contents of the store in which it is
evaluated, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the evaluation of a
term may cause side effects on the store that may affect the
evaluation of other terms in the future, the evaluation rules need
to return a new store. Thus, the shape of the single-step
evaluation relation changes from [t ==> t'] to [t / st ==> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing evaluation rules with stores:
value v2
-------------------------------------- (ST_AppAbs)
(\x:T.t12) v2 / st ==> [x:=v2]t12 / st
t1 / st ==> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st ==> t1' t2 / st'
value v1 t2 / st ==> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st ==> v1 t2' / st'
Note that the first rule here returns the store unchanged:
function application, in itself, has no side effects. The other two
rules simply propagate side effects from premise to conclusion.
Now, the result of evaluating a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values.
It is crucial to note that making this extension to the syntax of
terms does not mean that we intend _programmers_ to write terms
involving explicit, concrete locations: such terms will arise only
as intermediate results of evaluation. This may initially seem
odd, but really it follows naturally from our design decision to
represent the result of every evaluation step by a modified
term. If we had chosen a more "machine-like" model for evaluation,
e.g. with an explicit stack to contain values of bound
identifiers, then the idea of adding locations to the set of
allowed values would probably seem more obvious.
In terms of this expanded syntax, we can state evaluation rules for
the new constructs that manipulate locations and the store. First, to
evaluate a dereferencing expression [!t1], we must first reduce [t1]
until it becomes a value:
t1 / st ==> t1' / st'
----------------------- (ST_Deref)
!t1 / st ==> !t1' / st'
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to derefence a
location that is larger than the size [|st|] of the currently
allocated store; the evaluation rules simply get stuck in this
case. The type safety properties that we'll establish below
assure us that well-typed terms will never misbehave in this way.)
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st ==> lookup l st / st
Next, to evaluate an assignment expression [t1:=t2], we must first
evaluate [t1] until it becomes a value (a location), and then
evaluate [t2] until it becomes a value (of any sort):
t1 / st ==> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st ==> t1' := t2 / st'
t2 / st ==> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st ==> v1 := t2' / st'
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v2], which we execute by updating the store to make
location [l] contain [v2]:
l < |st|
------------------------------------- (ST_Assign)
loc l := v2 / st ==> unit / [l:=v2]st
The notation [[l:=v2]st] means "the store that maps [l] to [v2]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this evaluation step is just [unit];
the interesting result is the updated store.)
Finally, to evaluate an expression of the form [ref t1], we first
evaluate [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------------- (ST_Ref)
ref t1 / st ==> ref t1' / st'
Then, to evaluate the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v1].
-------------------------------- (ST_RefValue)
ref v1 / st ==> loc |st| / st,v1
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v1] means [snoc st v1].)
Note that these evaluation rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as evaluation proceeds. This does not affect the
correctness of the results of evaluation (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
evaluation), but it means that a naive implementation of our
evaluator might sometimes run out of memory where a more
sophisticated evaluator would be able to continue by reusing
locations whose contents have become garbage.
Formally... *)
Reserved Notation "t1 '/' st1 '==>' t2 '/' st2"
(at level 40, st1 at level 39, t2 at level 39).
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T t12 v2 st,
value v2 ->
tapp (tabs x T t12) v2 / st ==> [x:=v2]t12 / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tapp t1 t2 / st ==> tapp t1' t2 / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tapp v1 t2 / st ==> tapp v1 t2'/ st'
| ST_SuccNat : forall n st,
tsucc (tnat n) / st ==> tnat (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tsucc t1 / st ==> tsucc t1' / st'
| ST_PredNat : forall n st,
tpred (tnat n) / st ==> tnat (pred n) / st
| ST_Pred : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tpred t1 / st ==> tpred t1' / st'
| ST_MultNats : forall n1 n2 st,
tmult (tnat n1) (tnat n2) / st ==> tnat (mult n1 n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st ==> t1' / st' ->
tmult t1 t2 / st ==> tmult t1' t2 / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tmult v1 t2 / st ==> tmult v1 t2' / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st ==> t1' / st' ->
tif0 t1 t2 t3 / st ==> tif0 t1' t2 t3 / st'
| ST_If0_Zero : forall t2 t3 st,
tif0 (tnat 0) t2 t3 / st ==> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
tif0 (tnat (S n)) t2 t3 / st ==> t3 / st
| ST_RefValue : forall v1 st,
value v1 ->
tref v1 / st ==> tloc (length st) / snoc st v1
| ST_Ref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tref t1 / st ==> tref t1' / st'
| ST_DerefLoc : forall st l,
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
| ST_Deref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tderef t1 / st ==> tderef t1' / st'
| ST_Assign : forall v2 l st,
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tassign t1 t2 / st ==> tassign t1' t2 / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tassign v1 t2 / st ==> tassign v1 t2' / st'
where "t1 '/' st1 '==>' t2 '/' st2" := (step (t1,st1) (t2,st2)).
(* no need to define ST_NatPredSucc or ST_NatPredZero *)
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Pred" | Case_aux c "ST_MultNats"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_If0" | Case_aux c "ST_If0_Zero"
| Case_aux c "ST_If0_Nonzero" | Case_aux c "ST_RefValue"
| Case_aux c "ST_Ref" | Case_aux c "ST_DerefLoc"
| Case_aux c "ST_Deref" | Case_aux c "ST_Assign"
| Case_aux c "ST_Assign1" | Case_aux c "ST_Assign2" ].
Hint Constructors step.
Definition multistep := (multi step).
Notation "t1 '/' st '==>*' t2 '/' st'" := (multistep (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(* ################################### *)
(** * Typing *)
(** Our contexts for free variables will be exactly the same as for
the STLC, partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ################################### *)
(** ** Store typings *)
(** Having extended our syntax and evaluation rules to accommodate
references, our last job is to write down typing rules for the new
constructs -- and, of course, to check that they are sound.
Naturally, the key question is, "What is the type of a location?"
First of all, notice that we do _not_ need to answer this question
for purposes of typechecking the terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of evaluation; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of an evaluation
sequence, e.g. trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we evaluate a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we evaluate the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we evaluate the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
and all the rest of the typing rules in the system are extended
similarly with stores. The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.
However, there are two problems with this rule. First, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear.
Second, the proposed typing rule for locations may not allow us to
derive anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
<<
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
>>
*)
(** **** Exercise: 2 stars (cyclic_store) *)
(** Can you find a term whose evaluation will create this particular
cyclic store? *)
Module cyclic_store.
Definition cyclic_store_program : tm :=
(tabs ExampleVariables.r TUnit (tnat 42)).
Definition cyclic_store_fst : tm :=
(tref (tabs (Id 5) TNat (tapp (tderef (tloc 1)) (tvar (Id 5))))).
Definition cyclic_store_snd : tm :=
(tref (tabs (Id 5) TNat (tapp (tderef (tloc 0)) (tvar (Id 5))))).
Definition cyclic_store : tm :=
(tapp (tapp cyclic_store_program cyclic_store_fst)
cyclic_store_snd).
End cyclic_store.
(* Now, consider l < length st *)
Definition cs_init_data : tm :=
(tref (tnat 0)).
Definition cs_program : tm :=
(tabs ExampleVariables.r TUnit (tnat 42)).
Definition cs_fst : tm :=
(tassign (tloc 0) (tabs (Id 5) TNat (tapp (tderef (tloc 1)) (tvar (Id 5))))).
Definition cs_snd : tm :=
(tassign (tloc 0) (tabs (Id 5) TNat (tapp (tderef (tloc 1)) (tvar (Id 5))))).
Definition cyclic_store : tm :=
(tseq cs_init_data (tseq cs_init_data
(tseq cs_fst
(tseq cs_snd
(tseq cs_init_data cs_program))))).
(* (tapp (tapp (tapp (tapp cs_init_program cs_init_data)
cs_init_data)
cs_fst)
cs_snd).
*)
(*
| ST_RefValue : forall (v1 : tm) (st : store),
value v1 -> tref v1 / st ==> tloc (length st) / snoc st v1
| ST_Assign : forall (v2 : tm) (l : nat) (st : list tm),
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_DerefLoc : forall (st : list tm) (l : nat),
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
Inductive value : tm -> Prop :=
v_abs : forall (x : id) (T : ty) (t : tm), value (tabs x T t)
| v_nat : forall n : nat, value (tnat n)
| v_unit : value tunit
| v_loc : forall l : nat, value (tloc l)
r:=succ(!r); !r
>>
as an abbreviation for
<<
(\x:Unit. !r) (r := succ(!r)).
*)
(*
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
(tref \x:Nat. (!(loc 1)))
(tref \x:Nat. (!(loc 0)))
*)
(** Both of these problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ ---a finite function
mapping locations to types.
As usual, this _conservative_ typing restriction on allowed
updates means that we will rule out as ill-typed some programs
that could evaluate perfectly well without getting stuck.
*)
(** Just like we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
value stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_Tlookup] function retrieves the type at a particular
index. *)
Definition store_Tlookup (n:nat) (ST:store_ty) :=
nth n ST TUnit.
(** Suppose we are _given_ a store typing [ST] describing the store
[st] in which some term [t] will be evaluated. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we may immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
That is, as long as [l] is a valid location (it is less than the
length of [ST]), we can compute the type of [l] just by looking it
up in [ST]. Typing is again a four-place relation, but it is
parameterized on a store _typing_ rather than a concrete store.
The rest of the typing rules are analogously augmented with store
typings. *)
(* ################################### *)
(** ** The Typing Relation *)
(** We can now give the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T11
------------------------- (T_Deref)
Gamma; ST |- !t1 : T11
Gamma; ST |- t1 : Ref T11
Gamma; ST |- t2 : T11
----------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
*)
Reserved Notation "Gamma ';' ST '|-' t '\in' T" (at level 40).
Inductive has_type : context -> store_ty -> tm -> ty -> Prop :=
| T_Var : forall Gamma ST x T,
Gamma x = Some T ->
Gamma; ST |- (tvar x) \in T
| T_Abs : forall Gamma ST x T11 T12 t12,
(extend Gamma x T11); ST |- t12 \in T12 ->
Gamma; ST |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma ST t1 t2,
Gamma; ST |- t1 \in (TArrow T1 T2) ->
Gamma; ST |- t2 \in T1 ->
Gamma; ST |- (tapp t1 t2) \in T2
| T_Nat : forall Gamma ST n,
Gamma; ST |- (tnat n) \in TNat
| T_Succ : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tsucc t1) \in TNat
| T_Pred : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tpred t1) \in TNat
| T_Mult : forall Gamma ST t1 t2,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in TNat ->
Gamma; ST |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma ST t1 t2 t3 T,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in T ->
Gamma; ST |- t3 \in T ->
Gamma; ST |- (tif0 t1 t2 t3) \in T
| T_Unit : forall Gamma ST,
Gamma; ST |- tunit \in TUnit
| T_Loc : forall Gamma ST l,
l < length ST ->
Gamma; ST |- (tloc l) \in (TRef (store_Tlookup l ST))
| T_Ref : forall Gamma ST t1 T1,
Gamma; ST |- t1 \in T1 ->
Gamma; ST |- (tref t1) \in (TRef T1)
| T_Deref : forall Gamma ST t1 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- (tderef t1) \in T11
| T_Assign : forall Gamma ST t1 t2 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- t2 \in T11 ->
Gamma; ST |- (tassign t1 t2) \in TUnit
where "Gamma ';' ST '|-' t '\in' T" := (has_type Gamma ST t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Unit" | Case_aux c "T_Loc"
| Case_aux c "T_Ref" | Case_aux c "T_Deref"
| Case_aux c "T_Assign" ].
(** Of course, these typing rules will accurately predict the results
of evaluation only if the concrete store used during evaluation
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the STLC: the substitution lemma promises
us that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will evaluate to a final result of type [T] if it yields
any result at all. (We will see later how to formalize an
analogous intuition for stores and store typings.)
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Recall that concrete location
constants arise only in terms that are the intermediate results of
evaluation; they are not in the language that programmers write.
Thus, we can simply typecheck the programmer's terms with respect
to the _empty_ store typing. As evaluation proceeds and new
locations are created, we will always be able to see how to extend
the store typing by looking at the type of the initial values
being placed in newly allocated cells; this intuition is
formalized in the statement of the type preservation theorem
below. *)
(* ################################### *)
(** * Properties *)
(** Our final task is to check that standard type safety properties
continue to hold for the STLC with references. The progress
theorem ("well-typed terms are not stuck") can be stated and
proved almost as for the STLC; we just need to add a few
straightforward cases to the proof, dealing with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ################################### *)
(** ** Well-Typed Stores *)
(** Since we have extended both the evaluation relation (with initial
and final stores) and the typing relation (with a store typing),
we need to change the statement of preservation to include these
parameters. Clearly, though, we cannot just add stores and store
typings without saying anything about how they are related: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
empty; ST |- t' \in T.
Abort.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then evaluate with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
empty; ST |- (store_lookup l st) \in (store_Tlookup l ST)).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. (The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation! This allows us to type circular
stores.) *)
(** **** Exercise: 2 stars (store_not_unique) *)
(** Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
(* Different gamma value? *)
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Lemma modusponens: forall (P Q: Prop), P -> (P -> Q) -> Q.
Proof. auto. Qed.
Ltac exploit x :=
refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _) _)
|| refine (modusponens _ _ (x _ _) _)
|| refine (modusponens _ _ (x _) _).
(*
Theorem preservation_wrong2 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
empty; ST |- t' \in T.
Abort.
*)
Ltac inv H := inversion H; subst; clear H.
Theorem preservation_wrong2 : ~(forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
empty; ST |- t' \in T).
Proof with eauto.
unfold not; intros.
generalize (H [TUnit] TUnit
(tseq
(tassign (tref (tnat 5)) (tnat 0))
(tderef (tloc 0)))
[tunit]
); intro T; exploit T; unfold tseq; eauto.
eapply T_App. constructor. constructor. constructor. constructor.
eapply T_Assign. constructor. constructor.
constructor.
constructor. auto.
intros. unfold store_lookup. simpl. destruct l; auto. destruct l; auto.
intro. inv H0. inv H5. inv H3. inv H4. inv H3. inv H7. inv H4. inv H6. inv H1. inv H1.
Qed.
(*
| T_Loc : forall Gamma ST l,
l < length ST ->
Gamma; ST |- (tloc l) \in (TRef (store_Tlookup l ST))
| T_Ref : forall Gamma ST t1 T1,
Gamma; ST |- t1 \in T1 ->
Gamma; ST |- (tref t1) \in (TRef T1)
| T_Deref : forall Gamma ST t1 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- (tderef t1) \in T11
| T_Assign : forall Gamma ST t1 t2 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- t2 \in T11 ->
Gamma; ST |- (tassign t1 t2) \in TUnit
| ST_RefValue : forall (v1 : tm) (st : store),
value v1 -> tref v1 / st ==> tloc (length st) / snoc st v1
| ST_Ref : forall (t1 t1' : tm) (st st' : store),
t1 / st ==> t1' / st' -> tref t1 / st ==> tref t1' / st'
| ST_DerefLoc : forall (st : list tm) (l : nat),
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
| ST_Deref : forall (t1 t1' : tm) (st st' : store),
t1 / st ==> t1' / st' -> tderef t1 / st ==> tderef t1' / st'
| ST_Assign : forall (v2 : tm) (l : nat) (st : list tm),
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_Assign1 : forall (t1 t1' t2 : tm) (st st' : store),
t1 / st ==> t1' / st' ->
tassign t1 t2 / st ==> tassign t1' t2 / st'
| ST_Assign2 : forall (v1 t2 t2' : tm) (st st' : store),
value v1 ->
t2 / st ==> t2' / st' ->
tassign v1 t2 / st ==> tassign v1 t2' / st' *)
(** This statement is fine for all of the evaluation rules except the
allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st']
includes a binding for a fresh location [l], then [l] cannot be in
the domain of [ST], and it will not be the case that [t']
(which definitely mentions [l]) is typable under [ST]. *)
(* ############################################ *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during evaluation,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_Tlookup l ST' = store_Tlookup l ST.
Proof with auto.
intros l ST ST' Hlen H.
generalize dependent ST'. generalize dependent l.
induction ST as [|a ST2]; intros l Hlen ST' HST'.
Case "nil". inversion Hlen.
Case "cons". unfold store_Tlookup in *.
destruct ST'.
SCase "ST' = nil". inversion HST'.
SCase "ST' = a' :: ST'2".
inversion HST'; subst.
destruct l as [|l'].
SSCase "l = 0"...
SSCase "l = S l'". simpl. apply IHST2...
simpl in Hlen; omega.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
inversion Hlen.
simpl in *.
destruct l; try omega.
apply lt_n_S. apply IHextends. omega.
Qed.
(** Finally, [snoc ST T] extends [ST], and [extends] is reflexive. *)
Lemma extends_snoc : forall ST T,
extends (snoc ST T) ST.
Proof with auto.
induction ST; intros T...
simpl...
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ################################### *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else it is exactly [snoc ST T1], where
[T1] is the type of the value [v1] in the extended store [snoc st
v1], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of evaluation steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ################################### *)
(** ** Substitution lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_succ : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tsucc t1)
| afi_pred : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tpred t1)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_ref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tref t1)
| afi_deref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tderef t1)
| afi_assign1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tassign t1 t2)
| afi_assign2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tassign t1 t2).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2" | Case_aux c "afi_abs"
| Case_aux c "afi_succ" | Case_aux c "afi_pred"
| Case_aux c "afi_mult1" | Case_aux c "afi_mult2"
| Case_aux c "afi_if0_1" | Case_aux c "afi_if0_2" | Case_aux c "afi_if0_3"
| Case_aux c "afi_ref" | Case_aux c "afi_deref"
| Case_aux c "afi_assign1" | Case_aux c "afi_assign2" ].
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma ST,
appears_free_in x t ->
Gamma; ST |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros. generalize dependent Gamma. generalize dependent T.
afi_cases (induction H) Case;
intros; (try solve [ inversion H0; subst; eauto ]).
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H8.
rewrite extend_neq in H8; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' ST t T,
Gamma; ST |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma'; ST |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros...
Case "T_Var".
apply T_Var. symmetry. rewrite <- H...
Case "T_Abs".
apply T_Abs. apply IHhas_type; intros.
unfold extend.
destruct (eq_id_dec x x0)...
Case "T_App".
eapply T_App.
apply IHhas_type1...
apply IHhas_type2...
Case "T_Mult".
eapply T_Mult.
apply IHhas_type1...
apply IHhas_type2...
Case "T_If0".
eapply T_If0.
apply IHhas_type1...
apply IHhas_type2...
apply IHhas_type3...
Case "T_Assign".
eapply T_Assign.
apply IHhas_type1...
apply IHhas_type2...
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x s S t T,
empty; ST |- s \in S ->
(extend Gamma x S); ST |- t \in T ->
Gamma; ST |- ([x:=s]t) \in T.
Proof with eauto.
intros Gamma ST x s S t T Hs Ht.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
inversion H; subst; simpl...
Case "tvar".
rename i into y.
destruct (eq_id_dec x y).
SCase "x = y".
subst.
rewrite extend_eq in H3.
inversion H3; subst.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ _ _ _ Hcontra Hs) as [T' HT'].
inversion HT'.
SCase "x <> y".
apply T_Var.
rewrite extend_neq in H3...
Case "tabs". subst.
rename i into y.
destruct (eq_id_dec x y).
SCase "x = y".
subst.
apply T_Abs. eapply context_invariance...
intros. apply extend_shadow.
SCase "x <> x0".
apply T_Abs. apply IHt.
eapply context_invariance...
intros. unfold extend.
destruct (eq_id_dec y x0)...
subst.
rewrite neq_id...
Qed.
(* ################################### *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
empty; ST |- t \in (store_Tlookup l ST) ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
destruct (beq_nat l' l) eqn: Heqll'.
Case "l' = l".
apply beq_nat_true in Heqll'; subst.
rewrite lookup_replace_eq...
Case "l' <> l".
apply beq_nat_false in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ######################################## *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
Gamma; ST |- t \in T ->
Gamma; ST' |- t \in T.
Proof with eauto.
intros. has_type_cases (induction H0) Case; eauto.
Case "T_Loc".
erewrite <- extends_lookup...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well typed with respect to a store typing, then the store extended
with a new term [t] will still be well typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_snoc : forall ST st t1 T1,
store_well_typed ST st ->
empty; ST |- t1 \in T1 ->
store_well_typed (snoc ST T1) (snoc st t1).
Proof with auto.
intros.
unfold store_well_typed in *.
inversion H as [Hlen Hmatch]; clear H.
rewrite !length_snoc.
split...
Case "types match.".
intros l Hl.
unfold store_lookup, store_Tlookup.
apply le_lt_eq_dec in Hl; inversion Hl as [Hlt | Heq].
SCase "l < length st".
apply lt_S_n in Hlt.
rewrite <- !nth_lt_snoc...
apply store_weakening with ST. apply extends_snoc.
apply Hmatch...
rewrite Hlen...
SCase "l = length st".
inversion Heq.
rewrite nth_eq_snoc.
rewrite <- Hlen. rewrite nth_eq_snoc...
apply store_weakening with ST... apply extends_snoc.
Qed.
(* ################################### *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
Theorem preservation :
preservation_theorem.
(*
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').*)
Proof with eauto using store_weakening, extends_refl.
unfold preservation_theorem.
remember (@empty ty) as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
has_type_cases (induction Ht) Case; intros t' HST Hstep;
subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
Case "T_App".
SCase "ST_AppAbs". exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
SCase "ST_App1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_App2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Succ".
SCase "ST_Succ".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Pred".
SCase "ST_Pred".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Mult".
SCase "ST_Mult1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Mult2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_If0".
SCase "ST_If0_1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... split...
Case "T_Ref".
SCase "ST_RefValue".
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption.
SCase "ST_Ref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Deref".
SCase "ST_DerefLoc".
exists ST. split; try split...
inversion HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst...
SCase "ST_Deref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Assign".
SCase "ST_Assign".
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
SCase "ST_Assign1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Assign2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
Theorem preservation_ :
preservation_theorem.
Proof with eauto using store_weakening, extends_refl.
unfold preservation_theorem. remember empty as Gamma.
intros.
generalize dependent t'.
generalize dependent H0.
has_type_cases (induction H) Case;
intros HST t' Hstep; try (solve by inversion);
inv Hstep; eauto using store_weakening, extends_refl.
Case "T_App".
eexists... split... split...
eapply substitution_preserves_typing...
inv H...
eapply IHhas_type1 in HST... inv HST. inv H1. inv H4.
eexists; eauto using store_weakening, extends_refl.
eapply IHhas_type2 in HST... inv HST. inv H1. inv H4.
eexists...
Case "T_Succ".
eapply IHhas_type in H1...
inv H1. inv H0. inv H2.
eexists...
Case "T_Pred".
eapply IHhas_type in H1...
inv H1. inv H0. inv H2.
eexists...
Case "T_Mult".
apply IHhas_type1 with (t1') in HST...
inv HST. inv H1. inv H4.
eexists...
apply IHhas_type2 with (t2') in H7...
inv H7. inv H1. inv H4.
eexists...
Case "T_If0".
eapply IHhas_type1 in HST...
inv HST. inv H2. inv H5.
eexists...
split...
Case "T_Ref".
generalize HST; intro.
unfold store_well_typed in HST0. inv HST0...
(*
eapply IHhas_type in HST.
inv HST. inv H3. inv H5.
*)
exists (snoc ST T1). split... apply extends_snoc.
split...
replace (TRef T1) with (TRef (store_Tlookup (length st) (snoc ST T1)))...
constructor...
rewrite length_snoc. rewrite H0. omega.
unfold store_Tlookup. rewrite <- H0.
rewrite nth_eq_snoc...
apply store_well_typed_snoc...
apply IHhas_type in H1. inv H1. inv H0. inv H2.
exists x... split... auto.
Case "T_Deref".
exists ST. split... split...
replace T11 with (store_Tlookup l ST)...
inv HST. apply H2...
unfold store_Tlookup. inv H...
apply IHhas_type in H1... inv H1. inv H0. inv H2.
unfold store_well_typed in HST...
Case "T_Assign".
exists ST... split... split...
apply assign_pres_store_typing...
replace (store_Tlookup l ST) with T11...
inv H...
apply IHhas_type1 in H2... inv H2. inv H1. inv H3.
exists x...
apply IHhas_type2 in H7... inv H7. inv H1. inv H4.
exists x...
Qed.
(** **** Exercise: 3 stars (preservation_informal) *)
(** Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
(H)empty; ST |- t \in T ->
(HST)store_well_typed ST st ->
(Hstep)t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
Keep store_weakening and extends_refl lemma in mind.
Induction on H : "empty; ST |- t \in T".
It has "has_type" inductive type.
Consider every case that H can occur, each with its own premises.
Many cases are solved just by looking simpl reasoning,
in specific, considering each possible cases of Hstep.
(*
has_type_cases (induction H) Case;
intros HST t' Hstep; try (solve by inversion);
inv Hstep; eauto using store_weakening, extends_refl.
*)
Now, focus on more interesting cases.
"T_Ref".
Gamma; ST |- t1 \in T1 ->
(H) Gamma; ST |- tref t1 \in TRef T1
where, original H was in form of
(H)empty; ST |- t \in T, means t := tref t1 for some t1.
Look at Hstep. Only possible cases with (t := tref t1) is
ST_RefValue and ST_Ref, stated below.
| ST_RefValue : forall (v1 : tm) (st : store),
value v1 -> tref v1 / st ==> tloc (length st) / snoc st v1
| ST_Ref : t1 / st ==> t1' / st' -> tref t1 / st ==> tref t1' / st'
For each case, now goal is to prove this.
exists ST' : store_ty,
extends ST' ST /\ \empty; ST' |- t' \in T /\ store_well_typed ST' st'
: Prop
| ST_RefValue -> exists (snoc ST T1)
| ST_Ref -> exists ST
Similary...
[] *)
(* ################################### *)
(** ** Progress *)
(** Fortunately, progress for this system is pretty easy to prove; the
proof is very similar to the proof of progress for the STLC, with
a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
empty; ST |- t \in T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst; try solve by inversion...
Case "T_App".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tapp (tabs x T t) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tapp t1' t2). exists st'...
Case "T_Succ".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [ inversion Ht ].
SSCase "t1 is a tnat".
exists (tnat (S n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tsucc t1'). exists st'...
Case "T_Pred".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht ].
SSCase "t1 is a tnat".
exists (tnat (pred n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tpred t1'). exists st'...
Case "T_Mult".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 is a value".
inversion Ht2p; subst; try solve [inversion Ht2].
exists (tnat (mult n n0)). exists st...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tmult (tnat n) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tmult t1' t2). exists st'...
Case "T_If0".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
SSCase "n = 0". exists t2. exists st...
SSCase "n = S n'". exists t3. exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tif0 t1' t2 t3). exists st'...
Case "T_Ref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tref t1'). exists st'...
Case "T_Deref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tderef t1'). exists st'...
Case "T_Assign".
right. destruct IHHt1 as [Ht1p|Ht1p]...
SCase "t1 is a value".
destruct IHHt2 as [Ht2p|Ht2p]...
SSCase "t2 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H5...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tassign t1 t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tassign t1' t2). exists st'...
Qed.
(* ################################### *)
(** * References and Nontermination *)
Section RefsAndNontermination.
Import ExampleVariables.
(** We know that the simply typed lambda calculus is _normalizing_,
that is, every well-typed term can be reduced to a value in a
finite number of steps. What about STLC + references?
Surprisingly, adding references causes us to lose the
normalization property: there exist well-typed terms in the STLC +
references which can continue to reduce forever, without ever
reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
<<
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
>>
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function (\x:Unit.(!r) unit) -- that is, the function which
ignores its argument and calls the function stored in [r] on the
argument [unit]; but of course, that function is itself! To get
the ball rolling we finally execute this function with [(!r)
unit].
*)
Definition loop_fun :=
tabs x TUnit (tapp (tderef (tvar r)) tunit).
Definition loop :=
tapp
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit)))
(tref (tabs x TUnit tunit)).
Definition loop' :=
tseq (tref (tabs x TUnit tunit))
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit))).
(** This term is well typed: *)
Lemma loop_typeable : exists T, empty; nil |- loop \in T.
Proof with eauto.
exists TUnit. (* eexists *)
unfold loop. unfold loop_fun.
(* repeat econstructor *)
apply T_App with (TRef (TArrow TUnit TUnit)).
repeat econstructor.
apply T_Ref. apply T_Abs. apply T_Unit.
(*
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
unfold extend. simpl. reflexivity. auto.
eapply T_Assign.
eapply T_Var. unfold extend. simpl. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
*)
Qed.
Lemma loop'_not_typeable : ~(exists T, empty; nil |- loop' \in T).
Proof with eauto.
unfold not; intro.
inv H. inv H0. inv H6. inv H2. inv H7. inv H4.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[==>+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [==>*]), except
that it is not reflexive: [t ==>+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition multistep1 := (step_closure step).
Notation "t1 '/' st '==>+' t2 '/' st'" := (multistep1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store [ [r:=(loc 0)]
loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[multi_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply multi_refl]).
Lemma loop_steps_to_loop_fun :
loop / nil ==>*
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop.
reduce.
Qed.
(** Finally, the latter expression reduces in two steps to itself! *)
Lemma loop_fun_step_self :
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil ==>+
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
Lemma cyclic_store_not_typeable : forall T, ~(empty; nil |- cyclic_store \in T).
Proof with eauto.
intros.
unfold cyclic_store. unfold cs_init_data, cs_fst, cs_snd, cs_program, not.
intros.
inv H. inv H4. inv H2. inv H7. inv H2. inv H6.
Qed.
(** **** Exercise: 4 stars (factorial_ref) *)
(** Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just use the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition five_to_six : tm :=
tapp
(tabs r (TRef TNat) (tsucc (tderef (tvar r))))
(tref (tnat 5)).
Lemma five_to_six_test : exists st,
five_to_six / nil ==>* tnat 6 / st.
Proof. eexists. unfold five_to_six. reduce. Qed.
Lemma five_to_six_type :
empty; nil |- five_to_six \in TNat.
Proof. repeat econstructor. Qed.
Definition minus_one : tm :=
(tabs r (TNat) (tpred (tvar r))).
Lemma minus_one_test :
(exists st,
(tapp minus_one (tnat 5)) / nil ==>* tnat 4 / st) /\
(exists st,
(tapp minus_one (tnat 0)) / nil ==>* tnat 0 / st) /\
(exists st,
(tseq
(tref minus_one)
(tnat 0)
) / nil ==>* tnat 0 / st) /\
(exists st,
(tseq
(tref minus_one)
(tapp (tderef (tloc 0)) (tnat 5))
) / nil ==>* tnat 4 / st)
.
Proof. repeat split; eexists; unfold minus_one, tseq, not; reduce.
Qed.
Lemma minus_one_type :
empty; nil |- minus_one \in (TArrow TNat TNat).
Proof. repeat econstructor. Qed.
(*
Definition loop_fun :=
tabs x TUnit (tapp (tderef (tvar r)) tunit).
Definition loop :=
tapp
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit)))
(tref (tabs x TUnit tunit)).
*)
Definition minus_one_without_program_arg :=
(*
(tseq
(* (tassign (tvar t) minus_one) *)
(tref minus_one)
(tapp (tderef (tvar (Id 0))) (tnat 10))).
*)
(* tseq : t1 should be TUnit, but tref is not TUnit *)
tapp
(tabs r (TRef (TArrow TNat TNat))
(tapp (tderef (tvar (Id 2))) (tnat 10)))
(tref minus_one).
Lemma minus_one_without_program_arg_type :
empty; nil |- minus_one_without_program_arg \in TNat.
Proof.
repeat econstructor.
(*
unfold minus_one_without_param, tseq.
apply T_App with (TRef (TArrow TNat TNat)).
repeat econstructor.
apply preservation_theorem.
apply T_Assign.
repeat econstructor; unfold t, extend; simpl.
Qed.
*)
Qed.
(*
x : tseq
?
y : param for program,4 -> 24
TNat
r : factorial_fun
TArrow TNat TNat
s : param for factorial_fun
TNat
*)
Definition program_arg := Id 14.
Definition function_address := Id 13.
Definition function_arg := Id 12.
(* Definition not_used := Id 11. (* for sequencing *) *)
Definition tseq_var := Id 10.
Definition function_param := Id 9.
Definition tseq' t1 t2 :=
tapp (tabs tseq_var TUnit t2) t1.
Definition factorial_fun : tm :=
(* minus_one. *)
(* tabs function_param TNat (tpred (tvar function_param)). *)
tabs function_param TNat
(tif0 (tvar function_param)
(tnat 1)
(tmult
(tvar function_param)
(* (tapp (tderef (tvar function_address)) (tpred (tvar function_param))) *)
(tapp (tderef (tvar function_address)) (tpred (tvar function_param)))
)
).
Definition factorial_without_program_arg : tm :=
tapp
(tabs function_address (TRef (TArrow TNat TNat))
(tseq' (tassign (tvar function_address) factorial_fun)
(tapp (tderef (tvar function_address)) (tnat 10))))
(tref (tabs function_arg TNat (tnat 42)))
(* initialize loc 0's type with, TRef Nat -> Nat *)
.
(* tseq uses (Id 0), which is ExampleVariables.x
tseq = fun t1 t2 : tm => tapp (tabs (Id 0) TUnit t2) t1
: tm -> tm -> tm
*)
Lemma factorial_without_param_type :
empty; nil |- factorial_without_program_arg \in TNat.
Proof with eauto.
unfold factorial_without_program_arg, tseq, x, y, r, s.
repeat econstructor; try reduce; try eauto; try unfold extend; try simpl.
Qed.
Definition factorial : tm :=
(tabs program_arg TNat
(tapp
(tabs function_address (TRef (TArrow TNat TNat))
(tseq (tassign (tvar function_address) factorial_fun)
(tapp (tderef (tvar function_address)) (tvar program_arg))))
(tref (tabs function_param TNat (tnat 42)))))
.
Lemma factorial_type : empty; nil |- factorial \in (TArrow TNat TNat).
Proof with eauto.
unfold factorial, tseq, x, y, r, s; reduce...
repeat try (econstructor); unfold extend;
unfold x; unfold y; unfold r; unfold s;
simpl; eauto.
Qed.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
Lemma factorial_6 : exists st,
tapp factorial (tnat 6) / nil ==>* tnat 720 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
Lemma factorial_4 : exists st,
tapp factorial (tnat 4) / nil ==>* tnat 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
(** [] *)
(* ################################### *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, optional (garabage_collector) *)
(** Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(** [] *)
End RefsAndNontermination.
End STLCRef.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/14/2015 05:20:43 PM
// Design Name:
// Module Name: Problem4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem4(
input A,
input B,
input C,
input D,
input E,
output X
);
assign X = (~A & ~B & ~C & D & ~E) | (~A & ~B & ~C & D & E) | (~A & ~B & C & ~D & E) | (~A & ~B & C & D & E) | (~A & B & ~C & ~D & E) | (~A & B & ~C & D & E) | (~A & B & C & ~D & E) | (A & ~B & ~C & ~D & E) |(A & ~B & ~C & D & E) | (A & ~B & C & D & E) | (A & B & C & ~D & E) | (A & B & C & D & E);
// 00010 00011 00101 00111 01001 01011 01101 10001 10011 10111 11101 11111
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430.v
//
// *Module Description:
// openMSP430 Top level file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module openMSP430 (
// OUTPUTs
aclk, // ASIC ONLY: ACLK
aclk_en, // FPGA ONLY: ACLK enable
dbg_freeze, // Freeze peripherals
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_uart_txd, // Debug interface: UART TXD
dco_enable, // ASIC ONLY: Fast oscillator enable
dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write byte enable (low active)
irq_acc, // Interrupt request accepted (one-hot signal)
lfxt_enable, // ASIC ONLY: Low frequency oscillator enable
lfxt_wkup, // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
mclk, // Main system clock
dma_dout, // Direct Memory Access data output
dma_ready, // Direct Memory Access is complete
dma_resp, // Direct Memory Access response (0:Okay / 1:Error)
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write byte enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write byte enable (low active) (optional)
puc_rst, // Main system reset
smclk, // ASIC ONLY: SMCLK
smclk_en, // FPGA ONLY: SMCLK enable
// INPUTs
cpu_en, // Enable CPU code execution (asynchronous and non-glitchy)
dbg_en, // Debug interface enable (asynchronous and non-glitchy)
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
dco_clk, // Fast oscillator (fast clock)
dmem_dout, // Data Memory data output
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
dma_addr, // Direct Memory Access address
dma_din, // Direct Memory Access data input
dma_en, // Direct Memory Access enable (high active)
dma_priority, // Direct Memory Access priority (0:low / 1:high)
dma_we, // Direct Memory Access write byte enable (high active)
dma_wkup, // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
scan_mode, // ASIC ONLY: Scan mode
wkup // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
// PARAMETERs
//============
parameter INST_NR = 8'h00; // Current oMSP instance number (for multicore systems)
parameter TOTAL_NR = 8'h00; // Total number of oMSP instances-1 (for multicore systems)
// OUTPUTs
//============
output aclk; // ASIC ONLY: ACLK
output aclk_en; // FPGA ONLY: ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output dbg_uart_txd; // Debug interface: UART TXD
output dco_enable; // ASIC ONLY: Fast oscillator enable
output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write byte enable (low active)
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
output mclk; // Main system clock
output [15:0] dma_dout; // Direct Memory Access data output
output dma_ready; // Direct Memory Access is complete
output dma_resp; // Direct Memory Access response (0:Okay / 1:Error)
output [13:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output per_en; // Peripheral enable (high active)
output [1:0] per_we; // Peripheral write byte enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
output puc_rst; // Main system reset
output smclk; // ASIC ONLY: SMCLK
output smclk_en; // FPGA ONLY: SMCLK enable
// INPUTs
//============
input cpu_en; // Enable CPU code execution (asynchronous and non-glitchy)
input dbg_en; // Debug interface enable (asynchronous and non-glitchy)
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [`IRQ_NR-3:0] irq; // Maskable interrupts (14, 30 or 62)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input [15:1] dma_addr; // Direct Memory Access address
input [15:0] dma_din; // Direct Memory Access data input
input dma_en; // Direct Memory Access enable (high active)
input dma_priority; // Direct Memory Access priority (0:low / 1:high)
input [1:0] dma_we; // Direct Memory Access write byte enable (high active)
input dma_wkup; // ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy)
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input reset_n; // Reset Pin (active low, asynchronous and non-glitchy)
input scan_enable; // ASIC ONLY: Scan enable (active during scan shifting)
input scan_mode; // ASIC ONLY: Scan mode
input wkup; // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
wire [7:0] inst_ad;
wire [7:0] inst_as;
wire [11:0] inst_alu;
wire inst_bw;
wire inst_irq_rst;
wire inst_mov;
wire [15:0] inst_dest;
wire [15:0] inst_dext;
wire [15:0] inst_sext;
wire [7:0] inst_so;
wire [15:0] inst_src;
wire [2:0] inst_type;
wire [7:0] inst_jmp;
wire [3:0] e_state;
wire exec_done;
wire decode_noirq;
wire cpu_en_s;
wire cpuoff;
wire oscoff;
wire scg0;
wire scg1;
wire por;
wire gie;
wire cpu_mclk;
wire dma_mclk;
wire mclk_dma_enable;
wire mclk_dma_wkup;
wire mclk_enable;
wire mclk_wkup;
wire [31:0] cpu_id;
wire [7:0] cpu_nr_inst = INST_NR;
wire [7:0] cpu_nr_total = TOTAL_NR;
wire [15:0] eu_mab;
wire [15:0] eu_mdb_in;
wire [15:0] eu_mdb_out;
wire [1:0] eu_mb_wr;
wire eu_mb_en;
wire [15:0] fe_mab;
wire [15:0] fe_mdb_in;
wire fe_mb_en;
wire fe_pmem_wait;
wire pc_sw_wr;
wire [15:0] pc_sw;
wire [15:0] pc;
wire [15:0] pc_nxt;
wire nmi_acc;
wire nmi_pnd;
wire nmi_wkup;
wire wdtie;
wire wdtnmies;
wire wdtifg;
wire wdt_irq;
wire wdt_wkup;
wire wdt_reset;
wire wdtifg_sw_clr;
wire wdtifg_sw_set;
wire dbg_clk;
wire dbg_rst;
wire dbg_en_s;
wire dbg_halt_cmd;
wire dbg_mem_en;
wire dbg_reg_wr;
wire dbg_cpu_reset;
wire [15:0] dbg_mem_addr;
wire [15:0] dbg_mem_dout;
wire [15:0] dbg_mem_din;
wire [15:0] dbg_reg_din;
wire [1:0] dbg_mem_wr;
wire cpu_halt_st;
wire cpu_halt_cmd;
wire puc_pnd_set;
wire [15:0] per_dout_or;
wire [15:0] per_dout_sfr;
wire [15:0] per_dout_wdog;
wire [15:0] per_dout_mpy;
wire [15:0] per_dout_clk;
//=============================================================================
// 2) GLOBAL CLOCK & RESET MANAGEMENT
//=============================================================================
omsp_clock_module clock_module_0 (
// OUTPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enablex
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_mclk (cpu_mclk), // Main system CPU only clock
.dma_mclk (dma_mclk), // Main system DMA and/or CPU clock
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_rst (dbg_rst), // Debug unit reset
.dco_enable (dco_enable), // Fast oscillator enable
.dco_wkup (dco_wkup), // Fast oscillator wake-up (asynchronous)
.lfxt_enable (lfxt_enable), // Low frequency oscillator enable
.lfxt_wkup (lfxt_wkup), // Low frequency oscillator wake-up (asynchronous)
.per_dout (per_dout_clk), // Peripheral data output
.por (por), // Power-on reset
.puc_pnd_set (puc_pnd_set), // PUC pending set for the serial debug interface
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.cpuoff (cpuoff), // Turns off the CPU
.dbg_cpu_reset (dbg_cpu_reset), // Reset CPU from debug interface
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.mclk_dma_enable (mclk_dma_enable), // DMA Sub-System Clock enable
.mclk_dma_wkup (mclk_dma_wkup), // DMA Sub-System Clock wake-up (asynchronous)
.mclk_enable (mclk_enable), // Main System Clock enable
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
.oscoff (oscoff), // Turns off LFXT1 clock input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
.wdt_reset (wdt_reset) // Watchdog-timer reset
);
assign mclk = dma_mclk;
//=============================================================================
// 3) FRONTEND (<=> FETCH & DECODE)
//=============================================================================
omsp_frontend frontend_0 (
// OUTPUTs
.cpu_halt_st (cpu_halt_st), // Halt/Run status from CPU
.decode_noirq (decode_noirq), // Frontend decode instruction
.e_state (e_state), // Execution state
.exec_done (exec_done), // Execution completed
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
.inst_as (inst_as), // Decoded Inst: source addressing mode
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_mov (inst_mov), // Decoded Inst: mov instruction
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
.inst_src (inst_src), // Decoded Inst: source (one hot)
.inst_type (inst_type), // Decoded Instruction type
.irq_acc (irq_acc), // Interrupt request accepted
.mab (fe_mab), // Frontend Memory address bus
.mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk_dma_enable (mclk_dma_enable), // DMA Sub-System Clock enable
.mclk_dma_wkup (mclk_dma_wkup), // DMA Sub-System Clock wake-up (asynchronous)
.mclk_enable (mclk_enable), // Main System Clock enable
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_halt_cmd (cpu_halt_cmd), // Halt CPU command
.cpuoff (cpuoff), // Turns off the CPU
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
.dma_en (dma_en), // Direct Memory Access enable (high active)
.dma_wkup (dma_wkup), // DMA Sub-System Wake-up (asynchronous and non-glitchy)
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.gie (gie), // General interrupt enable
.irq (irq), // Maskable interrupts
.mclk (cpu_mclk), // Main system clock
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
.nmi_pnd (nmi_pnd), // Non-maskable interrupt pending
.nmi_wkup (nmi_wkup), // NMI Wakeup
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wkup (wkup) // System Wake-up (asynchronous)
);
//=============================================================================
// 4) EXECUTION UNIT
//=============================================================================
omsp_execution_unit execution_unit_0 (
// OUTPUTs
.cpuoff (cpuoff), // Turns off the CPU
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.mab (eu_mab), // Memory address bus
.mb_en (eu_mb_en), // Memory bus enable
.mb_wr (eu_mb_wr), // Memory bus write transfer
.mdb_out (eu_mdb_out), // Memory data bus output
.oscoff (oscoff), // Turns off LFXT1 clock input
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
// INPUTs
.dbg_halt_st (cpu_halt_st), // Halt/Run status from CPU
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.e_state (e_state), // Execution state
.exec_done (exec_done), // Execution completed
.gie (gie), // General interrupt enable
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
.inst_as (inst_as), // Decoded Inst: source addressing mode
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_mov (inst_mov), // Decoded Inst: mov instruction
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
.inst_src (inst_src), // Decoded Inst: source (one hot)
.inst_type (inst_type), // Decoded Instruction type
.mclk (cpu_mclk), // Main system clock
.mdb_in (eu_mdb_in), // Memory data bus input
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
//=============================================================================
// 5) MEMORY BACKBONE
//=============================================================================
omsp_mem_backbone mem_backbone_0 (
// OUTPUTs
.cpu_halt_cmd (cpu_halt_cmd), // Halt CPU command
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.dma_dout (dma_dout), // Direct Memory Access data output
.dma_ready (dma_ready), // Direct Memory Access is complete
.dma_resp (dma_resp), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
// INPUTs
.cpu_halt_st (cpu_halt_st), // Halt/Run status from CPU
.dbg_halt_cmd (dbg_halt_cmd), // Debug interface Halt CPU command
.dbg_mem_addr (dbg_mem_addr[15:1]), // Debug address for rd/wr access
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dmem_dout (dmem_dout), // Data Memory data output
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (dma_mclk), // Main system clock
.dma_addr (dma_addr), // Direct Memory Access address
.dma_din (dma_din), // Direct Memory Access data input
.dma_en (dma_en), // Direct Memory Access enable (high active)
.dma_priority (dma_priority), // Direct Memory Access priority (0:low / 1:high)
.dma_we (dma_we), // Direct Memory Access write byte enable (high active)
.per_dout (per_dout_or), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
wire UNUSED_fe_mab_0 = fe_mab[0];
//=============================================================================
// 6) SPECIAL FUNCTION REGISTERS
//=============================================================================
omsp_sfr sfr_0 (
// OUTPUTs
.cpu_id (cpu_id), // CPU ID
.nmi_pnd (nmi_pnd), // NMI Pending
.nmi_wkup (nmi_wkup), // NMI Wakeup
.per_dout (per_dout_sfr), // Peripheral data output
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set), // Watchdog-timer interrupt flag software set
// INPUTs
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
.mclk (dma_mclk), // Main system clock
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.scan_mode (scan_mode), // Scan mode
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies) // Watchdog-timer NMI edge selection
);
//=============================================================================
// 7) WATCHDOG TIMER
//=============================================================================
`ifdef WATCHDOG
omsp_watchdog watchdog_0 (
// OUTPUTs
.per_dout (per_dout_wdog), // Peripheral data output
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_reset (wdt_reset), // Watchdog-timer reset
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies), // Watchdog-timer NMI edge selection
// INPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
.mclk (dma_mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_irq_clr (irq_acc[`IRQ_NR-6]), // Clear Watchdog-timer interrupt flag
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set) // Watchdog-timer interrupt flag software set
);
`else
assign per_dout_wdog = 16'h0000;
assign wdt_irq = 1'b0;
assign wdt_reset = 1'b0;
assign wdt_wkup = 1'b0;
assign wdtifg = 1'b0;
assign wdtnmies = 1'b0;
wire UNUSED_por = por;
wire UNUSED_wdtie = wdtie;
wire UNUSED_wdtifg_sw_clr = wdtifg_sw_clr;
wire UNUSED_wdtifg_sw_set = wdtifg_sw_set;
`endif
//=============================================================================
// 8) HARDWARE MULTIPLIER
//=============================================================================
`ifdef MULTIPLIER
omsp_multiplier multiplier_0 (
// OUTPUTs
.per_dout (per_dout_mpy), // Peripheral data output
// INPUTs
.mclk (dma_mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
`else
assign per_dout_mpy = 16'h0000;
`endif
//=============================================================================
// 9) PERIPHERALS' OUTPUT BUS
//=============================================================================
assign per_dout_or = per_dout |
per_dout_clk |
per_dout_sfr |
per_dout_wdog |
per_dout_mpy;
//=============================================================================
// 10) DEBUG INTERFACE
//=============================================================================
`ifdef DBG_EN
omsp_dbg dbg_0 (
// OUTPUTs
.dbg_cpu_reset (dbg_cpu_reset), // Reset CPU from debug interface
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_id (cpu_id), // CPU ID
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_halt_st (cpu_halt_st), // Halt/Run status from CPU
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.pc (pc), // Program counter
.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface
);
`else
assign dbg_cpu_reset = 1'b0;
assign dbg_freeze = ~cpu_en_s;
assign dbg_halt_cmd = 1'b0;
assign dbg_i2c_sda_out = 1'b1;
assign dbg_mem_addr = 16'h0000;
assign dbg_mem_dout = 16'h0000;
assign dbg_mem_en = 1'b0;
assign dbg_mem_wr = 2'b00;
assign dbg_reg_wr = 1'b0;
assign dbg_uart_txd = 1'b1;
wire UNUSED_decode_noirq = decode_noirq;
wire [31:0] UNUSED_cpu_id = cpu_id;
wire UNUSED_eu_mab_0 = eu_mab[0];
wire UNUSED_dbg_clk = dbg_clk;
wire UNUSED_dbg_rst = dbg_rst;
wire UNUSED_dbg_en_s = dbg_en_s;
wire [15:0] UNUSED_dbg_mem_din = dbg_mem_din;
wire [15:0] UNUSED_dbg_reg_din = dbg_reg_din;
wire UNUSED_puc_pnd_set = puc_pnd_set;
wire [6:0] UNUSED_dbg_i2c_addr = dbg_i2c_addr;
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
wire UNUSED_dbg_i2c_scl = dbg_i2c_scl;
wire UNUSED_dbg_i2c_sda_in = dbg_i2c_sda_in;
wire UNUSED_dbg_uart_rxd = dbg_uart_rxd;
`endif
endmodule // openMSP430
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_TB_V
`define SKY130_FD_SC_LP__INPUTISO0P_TB_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso0p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__inputiso0p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_TB_V
|
/*
* Decode WJX1 Wide Opcode
*/
`include "CoreDefs.v"
`include "DecWOp1.v"
module DecWOp(
/* verilator lint_off UNUSED */
clock, istrWord, opStep,
idRegN1, idRegS1, idRegT1, idImm1, idUCmd1,
idRegN2, idRegS2, idRegT2, idImm2, idUCmd2,
idRegN3, idRegS3, idRegT3, idImm3, idUCmd3,
idRegN4, idRegS4, idRegT4, idImm4, idUCmd4,
idRegN5, idRegS5, idRegT5, idImm5, idUCmd5
);
input clock;
input[127:0] istrWord; //source instruction word
output opStep;
output[6:0] idRegN1;
output[6:0] idRegS1;
output[6:0] idRegT1;
output[31:0] idImm1;
output[7:0] idUCmd1;
output[6:0] idRegN2;
output[6:0] idRegS2;
output[6:0] idRegT2;
output[31:0] idImm2;
output[7:0] idUCmd2;
output[6:0] idRegN3;
output[6:0] idRegS3;
output[6:0] idRegT3;
output[31:0] idImm3;
output[7:0] idUCmd3;
output[6:0] idRegN4;
output[6:0] idRegS4;
output[6:0] idRegT4;
output[31:0] idImm4;
output[7:0] idUCmd4;
output[6:0] idRegN5;
output[6:0] idRegS5;
output[6:0] idRegT5;
output[31:0] idImm5;
output[7:0] idUCmd5;
reg[6:0] opRegN1;
reg[6:0] opRegS1;
reg[6:0] opRegT1; //Index for mem ops
reg[31:0] opImm1; //Disp for mem ops
reg[7:0] opUCmd1;
reg[6:0] opRegN2;
reg[6:0] opRegS2;
reg[6:0] opRegT2; //Index for mem ops
reg[31:0] opImm2; //Disp for mem ops
reg[7:0] opUCmd2;
reg[6:0] opRegN3;
reg[6:0] opRegS3;
reg[6:0] opRegT3; //Index for mem ops
reg[31:0] opImm3; //Disp for mem ops
reg[7:0] opUCmd3;
reg[6:0] opRegN4;
reg[6:0] opRegS4;
reg[6:0] opRegT4; //Index for mem ops
reg[31:0] opImm4; //Disp for mem ops
reg[7:0] opUCmd4;
reg[6:0] opRegN5;
reg[6:0] opRegS5;
reg[6:0] opRegT5; //Index for mem ops
reg[31:0] opImm5; //Disp for mem ops
reg[7:0] opUCmd5;
assign idRegN1 = opRegN1;
assign idRegS1 = opRegS1;
assign idRegT1 = opRegT1;
assign idImm1 = opImm1;
assign idUCmd1 = opUCmd1;
assign idRegN2 = opRegN2;
assign idRegS2 = opRegS2;
assign idRegT2 = opRegT2;
assign idImm2 = opImm2;
assign idUCmd2 = opUCmd2;
assign idRegN3 = opRegN3;
assign idRegS3 = opRegS3;
assign idRegT3 = opRegT3;
assign idImm3 = opImm3;
assign idUCmd3 = opUCmd3;
assign idRegN4 = opRegN4;
assign idRegS4 = opRegS4;
assign idRegT4 = opRegT4;
assign idImm4 = opImm4;
assign idUCmd4 = opUCmd4;
assign idRegN5 = opRegN5;
assign idRegS5 = opRegS5;
assign idRegT5 = opRegT5;
assign idImm5 = opImm5;
assign idUCmd5 = opUCmd5;
reg isWide128;
assign opStep = isWide128;
wire[6:0] wop1RegN;
wire[6:0] wop1RegS;
wire[6:0] wop1RegT; //Index for mem ops
wire[31:0] wop1Imm; //Disp for mem ops
wire[7:0] wop1UCmd;
wire[6:0] wop2RegN;
wire[6:0] wop2RegS;
wire[6:0] wop2RegT; //Index for mem ops
wire[31:0] wop2Imm; //Disp for mem ops
wire[7:0] wop2UCmd;
DecWOp1 dwop1(clock, istrWord[23:0],
wop1RegN, wop1RegS, wop1RegT,
wop1Imm, wop1UCmd);
DecWOp1 dwop2(clock, istrWord[47:24],
wop2RegN, wop2RegS, wop2RegT,
wop2Imm, wop2UCmd);
wire[6:0] wop3RegN;
wire[6:0] wop3RegS;
wire[6:0] wop3RegT; //Index for mem ops
wire[31:0] wop3Imm; //Disp for mem ops
wire[7:0] wop3UCmd;
wire[6:0] wop4RegN;
wire[6:0] wop4RegS;
wire[6:0] wop4RegT; //Index for mem ops
wire[31:0] wop4Imm; //Disp for mem ops
wire[7:0] wop4UCmd;
DecWOp1 dwop3(clock, istrWord[87:64],
wop3RegN, wop3RegS, wop3RegT,
wop3Imm, wop3UCmd);
DecWOp1 dwop4(clock, istrWord[111:88],
wop4RegN, wop4RegS, wop4RegT,
wop4Imm, wop4UCmd);
wire[6:0] wop5RegN;
wire[6:0] wop5RegS;
wire[6:0] wop5RegT; //Index for mem ops
wire[31:0] wop5Imm; //Disp for mem ops
wire[7:0] wop5UCmd;
DecWOp1 dwop5(clock, { istrWord[123:112], istrWord[59:48] },
wop5RegN, wop5RegS, wop5RegT,
wop5Imm, wop5UCmd);
always @*
begin
isWide128 = istrWord[63];
opRegN1 = wop1RegN;
opRegS1 = wop1RegS;
opRegT1 = wop1RegT;
opImm1 = wop1Imm;
opUCmd1 = wop1UCmd;
opRegN2 = wop2RegN;
opRegS2 = wop2RegS;
opRegT2 = wop2RegT;
opImm2 = wop2Imm;
opUCmd2 = wop2UCmd;
if(isWide128)
begin
opRegN3 = wop3RegN;
opRegS3 = wop3RegS;
opRegT3 = wop3RegT;
opImm3 = wop3Imm;
opUCmd3 = wop3UCmd;
opRegN4 = wop4RegN;
opRegS4 = wop4RegS;
opRegT4 = wop4RegT;
opImm4 = wop4Imm;
opUCmd4 = wop4UCmd;
opRegN5 = wop5RegN;
opRegS5 = wop5RegS;
opRegT5 = wop5RegT;
opImm5 = wop5Imm;
opUCmd5 = wop5UCmd;
end
else
begin
opRegN3 = UREG_ZZR;
opRegS3 = UREG_ZZR;
opRegT3 = UREG_ZZR;
opImm3 = UV32_XX;
opUCmd3 = UCMD_NONE;
opRegN4 = UREG_ZZR;
opRegS4 = UREG_ZZR;
opRegT4 = UREG_ZZR;
opImm4 = UV32_XX;
opUCmd4 = UCMD_NONE;
opRegN5 = UREG_ZZR;
opRegS5 = UREG_ZZR;
opRegT5 = UREG_ZZR;
opImm5 = UV32_XX;
opUCmd5 = UCMD_NONE;
end
end
endmodule
|
(** * StlcProp: Properties of STLC *)
Require Export Stlc.
Module STLCProp.
Import STLC.
(** in this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * Canonical Forms *)
Lemma canonical_forms_bool : forall t,
empty ⊢ t ∈ TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof. repeat inversion 1; crush. Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty ⊢ t ∈ (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof. introv Ht HVal; inverts HVal; inverts Ht; eauto. Qed.
(* ###################################################################### *)
(** * Progress *)
(** As before, the _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take an evaluation step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. *)
Theorem progress : forall t T,
empty ⊢ t ∈ T ->
value t \/ exists t', t ==> t'.
(** _Proof_: by induction on the derivation of [⊢ t ∈ T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we know immediately that [t] is a value.
- If the last rule of the derivation was [T_App], then [t = t1
t2], and we know that [t1] and [t2] are also well typed in the
empty context; in particular, there exists a type [T2] such that
[⊢ t1 ∈ T2 -> T] and [⊢ t2 ∈ T2]. By the induction
hypothesis, either [t1] is a value or it can take an evaluation
step.
- If [t1] is a value, we now consider [t2], which by the other
induction hypothesis must also either be a value or take an
evaluation step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation was [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]).
*)
Proof.
introv Ht.
remember (@empty ty) as Gamma;
has_type_cases (induction Ht) Case; subst; eauto; eauto;
firstorder; try solve by inversion;
repeat match goal with
[p1 : value ?t, p2 : _ ⊢ ?t ∈ _ |- _] => inverts p1; inverts p2
end; eauto.
Qed.
(** **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty ⊢ t ∈ T ->
value t \/ exists t', t ==> t'.
Proof.
t_cases (induction t) Case; introv Ht; auto; inverts Ht as Ht1 Ht2 Ht3;
try solve by inversion; right;
repeat match goal with
[ IH : forall T, empty ⊢ ?t ∈ T → value ?t1 \/ exists t', ?t ==> t',
p : empty ⊢ ?t ∈ ?T |- _] => extend (IH T p)
end; destr_sums; destr_prods;
repeat match goal with
[ p1 : value ?t, p2 : _ ⊢ ?t ∈ _ |- _ ] => inverts p1; inverts p2 end; eauto.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Preservation *)
(** The other half of the type soundness property is the preservation
of types during reduction. For this, we need to develop some
technical machinery for reasoning about variables and
substitution. Working from top to bottom (the high-level property
we are actually interested in to the lowest-level technical lemmas
that are needed by various cases of the more interesting proofs),
the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter. The
one case that is significantly different is the one for the
[ST_AppAbs] rule, which is defined using the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both cases, we
discover that we need to take a term [s] that has been shown
to be well-typed in some context [Gamma] and consider the same
term [s] in a slightly different context [Gamma']. For this
we prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. For this, we need a careful definition
of
- the _free variables_ of a term -- i.e., the variables occuring
in the term that are not in the scope of a function
abstraction that binds them.
*)
(* ###################################################################### *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y] *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2"
| Case_aux c "afi_abs"
| Case_aux c "afi_if1" | Case_aux c "afi_if2"
| Case_aux c "afi_if3" ].
Hint Constructors appears_free_in.
(** A term in which no variables appear free is said to be _closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(* ###################################################################### *)
(** ** Substitution *)
(** We first need a technical lemma connecting free variables and
typing contexts. If a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it must
be the case that [Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma ⊢ t ∈ T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [extend_neq], noting
that [x] and [y] are different variables. *)
Proof. introv Hafi Ht.
generalize dependent Gamma; generalize dependent T;
afi_cases (induction Hafi) Case; inversion 1; eauto;
match goal with
| [ IH : forall T Gamma, Gamma ⊢ ?t ∈ T ->
exists T', Gamma ?x = Some T',
H : ?Gamma ⊢ ?t ∈ ?T |- _ ]
=> destruct (IH T Gamma H)
end; erewrite <- extend_neq; eauto.
Qed.
Hint Resolve free_in_context.
(** Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed -- that is, it has no free variables. *)
Lemma neg_lift : forall X Y : Prop, (X -> Y) -> ~ Y -> ~ X. eauto. Qed.
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty ⊢ t ∈ T ->
closed t.
intros; intros c Hc; eapply free_in_context in Hc; eauto; solve by inversion 2. Qed.
(** [] *)
(** Sometimes, when we have a proof [Gamma ⊢ t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma ⊢ t ∈ T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' ⊢ t ∈ T.
(** _Proof_: By induction on the derivation of [Gamma ⊢ t ∈ T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' ⊢ t ∈ T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 ⊢ t12 ∈ T12]. The induction
hypothesis is that for any context [Gamma''], if [Gamma,
y:T11] and [Gamma''] assign the same types to all the free
variables in [t12], then [t12] has type [T12] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the
free variables in [t]; we must show [Gamma' ⊢ \y:T11. t12 ∈
T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 ⊢ t12 ∈
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must either be [y], or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, we note that any variable
other than [y] which occurs free in [t12] also occurs free in
[t = \y:T11. t12], and by assumption [Gamma] and [Gamma']
agree on all such variables, and hence so do [Gamma, y:T11]
and [Gamma', y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma ⊢
t1 ∈ T2 -> T] and [Gamma ⊢ t2 ∈ T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. However, we note that all
free variables in [t1] are also free in [t1 t2], and similarly
for free variables in [t2]; hence the desired result follows
by the two IHs.
*)
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U ⊢ t ∈ T] and [⊢ v ∈ U], then [Gamma ⊢
[x:=v]t ∈ T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U ⊢ t ∈ T ->
empty ⊢ v ∈ U ->
Gamma ⊢ [x:=v]t ∈ T.
(** One technical subtlety in the statement of the lemma is that we
assign [v] the type [U] in the _empty_ context -- in other words,
we assume [v] is closed. This assumption considerably simplifies
the [T_Abs] case of the proof (compared to assuming [Gamma ⊢ v ∈
U], which would be the other reasonable assumption at this point)
because the context invariance lemma then tells us that [v] has
type [U] in any context at all -- we don't have to worry about
free variables in [v] clashing with the variable being introduced
into the context by [T_Abs].
_Proof_: We prove, by induction on [t], that, for all [T] and
[Gamma], if [Gamma,x:U ⊢ t ∈ T] and [⊢ v ∈ U], then [Gamma ⊢
[x:=v]t ∈ T].
- If [t] is a variable, there are two cases to consider, depending
on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U ⊢ x ∈ T] we
conclude that [U = T]. We must show that [[x:=v]x = v] has
type [T] under [Gamma], given the assumption that [v] has
type [U = T] under the empty context. This follows from
context invariance: if a closed term has type [T] in the
empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U ⊢ t12 ∈ T']
and [⊢ v ∈ U], then [Gamma' ⊢ [x:=v]t12 ∈ T'].
The substitution in the conclusion behaves differently,
depending on whether [x] and [y] are the same variable name.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma ⊢
t ∈ T]. But we know [Gamma,x:U ⊢ t : T], and since the
variable [y] does not appear free in [\y:T11. t12], the
context invariance lemma yields [Gamma ⊢ t ∈ T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 ⊢ t12 ∈
T12] by inversion of the typing relation, and [Gamma,y:T11,x:U
⊢ t12 ∈ T12] follows from this by the context invariance
lemma, so the IH applies, giving us [Gamma,y:T11 ⊢ [x:=v]t12 ∈
T12]. By [T_Abs], [Gamma ⊢ \y:T11. [x:=v]t12 ∈ T11->T12], and
by the definition of substitution (noting that [x <> y]),
[Gamma ⊢ \y:T11. [x:=v]t12 ∈ T11->T12] as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
Another technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[extend Gamma x U ⊢ t ∈ T] is not completely generic, in
the sense that one of the "slots" in the typing relation -- namely
the context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
(** The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way. *)
(* ###################################################################### *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T], and takes an evaluation step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
evaluation relation preserves types.
*)
Theorem preservation : forall t t' T,
empty ⊢ t ∈ T ->
t ==> t' ->
empty ⊢ t' ∈ T.
(** _Proof_: by induction on the derivation of [⊢ t ∈ T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis.
*)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
Lemma multipreservation : forall t t' T,
empty ⊢ t ∈ T -> t ==>* t' -> empty ⊢ t' ∈ T.
Proof. intros. induction H0; intros; auto.
apply IHmulti. eapply preservation with (t := x0); assumption.
Qed.
(** **** Exercise: 2 stars (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty ⊢ t ∈ T]? If so, prove it. If not, give a
counter-example not involving conditionals.
[]
*)
(* Conditionals make it trivially false, and there has to be another counterexample *)
(* (\ x : T -> \ i : T -> i) (\ y : T -> any untyped term here) *)
(* ###################################################################### *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Hint Resolve multipreservation.
Corollary soundness : forall t t' T,
empty ⊢ t ∈ T ->
t ==>* t' ->
~(stuck t').
Proof with eauto.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti; crush.
- assert (value x0 \/ exists t', x0 ==> t'); [eapply progress | crush]...
- assert (value z0 \/ exists t', z0 ==> t'); [eapply progress | crush]...
Qed.
(* ###################################################################### *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars (types_unique) *)
(** Another pleasant property of the STLC is that types are
unique: a given term (in a given context) has at most one
type. *)
(** Formalize this statement and prove it. *)
Theorem unique : forall t Gamma T T', Gamma ⊢ t ∈ T -> Gamma ⊢ t ∈ T' -> T = T'.
Proof with eauto.
introv Ht1 Ht2; generalize dependent T'.
has_type_cases (induction Ht1) Case; intros; inverts Ht2; crush...
- Case "T_Abs". apply (f_equal (TArrow T11)). apply IHHt1...
- Case "T_App". apply IHHt1_1 in H2. inverts H2...
Qed.
(** [] *)
(* ###################################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 1 star (progress_preservation_statement) *)
(** Without peeking, write down the progress and preservation
theorems for the simply typed lambda-calculus. *)
(** [] *)
Definition app : forall {A} (a : A) {P : A -> Type}, (forall a, P a) -> P a. auto. Defined.
Theorem progress'' : forall t T, empty ⊢ t ∈ T -> value t \/ exists t', t ==> t'.
Proof with eauto.
introv Ht; remember (@empty ty); symmetry in Heqp;
has_type_cases (induction Ht) Case; induction Heqp;
try apply (app eq_refl) in IHHt1; try apply (app eq_refl) in IHHt2;
try apply (app eq_refl) in IHHt3; simpl in *...
- Case "T_Var". inverts H.
- Case "T_App". right.
inverts IHHt1.
+ inverts IHHt2.
* inverts H; inverts Ht1. exists ([x0 := t2] t)...
* inverts H0. exists (tapp t1 x0)...
+ inverts H. exists (tapp x0 t2)...
- Case "T_If". right. simpl in *.
inverts IHHt1; inverts H; inverts Ht1...
Qed.
Theorem preservation'' : forall t t' T, empty ⊢ t ∈ T -> t ==> t' -> empty ⊢ t' ∈ T.
Proof with eauto.
introv Ht eval; generalize dependent t'; remember (@empty ty); symmetry in Heqp;
has_type_cases (induction Ht) Case; intros; subst; inverts eval; inverts Ht1...
- Case "T_App". eapply (substitution_preserves_typing). apply H1. apply Ht2.
Qed.
(** **** Exercise: 2 stars (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule:
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma ⊢ zap : T
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
False, forall t1 t2, tapp t1 t2 ==> zap
- Progress
Trivially true, forall t, exists t', t ==> t'
Proof: just take zap to be t', ST_Zap : t ==> zap
- Preservation
False, forall t : T1, forall T2, t : T1 ==> zap : T2
[]
*)
(** **** Exercise: 2 stars (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
true, same proof, but \x : A. x isn't a value anymore
- Progress
true
- Preservation
false, (\x : A. x) : A -> A ==> foo ==> true : TBool
[]
*)
(** **** Exercise: 2 stars (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
true
- Progress
false, but could be made true if you removed the value requirement on ST_App2
Example:
t1 t2 t3 : tm
tapp (tapp t1 t2) t3 no longer evaluates
- Preservation
true
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
false, if true then false else false ==> true and if true then false else false ==> false
- Progress
true
- Preservation
false, if true then (\a : A. A) else false : A -> A ==> true : Bool
*)
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma ⊢ t1 ∈ Bool->Bool->Bool
Gamma ⊢ t2 ∈ Bool
------------------------------ (T_FunnyApp)
Gamma ⊢ t1 t2 ∈ Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma ⊢ t1 ∈ Bool
Gamma ⊢ t2 ∈ Bool
--------------------- (T_FunnyApp')
Gamma ⊢ t1 t2 ∈ Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing
relation of the STLC:
------------------- (T_FunnyAbs)
⊢ \x:Bool.t ∈ Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(* ###################################################################### *)
(* ###################################################################### *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity) *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing... *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tnat"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0" ].
(** **** Exercise: 4 stars (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Progress theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties (up to [soundness]) of
the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
(* I could do all of these if it had originally been defined that way,
but this messiness with modules was giving me way too many scoping errors with notation,
not worth the trouble *)
End STLCArith.
End STLCProp.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_FUNCTIONAL_PP_V |
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//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// PART OF THIS FILE AT ALL TIMES.
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// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_register_slice_v2_1_7_axi_register_slice,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_m00_regslice_1,axi_register_slice_v2_1_7_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "zc702_m00_regslice_1,axi_register_slice_v2_1_7_axi_register_slice,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_m00_regslice_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [0 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* PS2 Mouse without FIFO buffer
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_nofifo (
input clk,
input reset,
input [7:0] writedata, // data to send
input write, // signal to send it
output [7:0] readdata, // data read
output irq, // signal data has arrived
output command_was_sent,
output error_sending_command,
output buffer_overrun_error,
inout ps2_clk,
inout ps2_dat
);
// Unused outputs
wire start_receiving_data;
wire wait_for_incoming_data;
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse mouse (
.clk (clk),
.reset (reset),
.the_command (writedata),
.send_command (write),
.received_data (readdata),
.received_data_en (irq),
.command_was_sent (command_was_sent),
.error_communication_timed_out (error_sending_command),
.start_receiving_data (start_receiving_data),
.wait_for_incoming_data (wait_for_incoming_data),
.ps2_clk (ps2_clk),
.ps2_dat (ps2_dat)
);
// Continous assignments
assign buffer_overrun_error = error_sending_command;
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: addr_arbiter_sasd.v
//
// Description:
// Hybrid priority + round-robin arbiter.
// Read & write requests combined (read preferred) at each slot
// Muxes AR and AW channel payload inputs based on arbitration results.
//-----------------------------------------------------------------------------
//
// Structure:
// addr_arbiter_sasd
// mux_enc
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_addr_arbiter_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 1,
parameter integer C_NUM_S_LOG = 1,
parameter integer C_AMESG_WIDTH = 1,
parameter C_GRANT_ENC = 0,
parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}}
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 'h0-'hF.
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_AWMESG,
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_ARMESG,
input wire [C_NUM_S-1:0] S_AWVALID,
output wire [C_NUM_S-1:0] S_AWREADY,
input wire [C_NUM_S-1:0] S_ARVALID,
output wire [C_NUM_S-1:0] S_ARREADY,
// Master Ports
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC,
output wire [C_NUM_S-1:0] M_GRANT_HOT,
output wire M_GRANT_RNW,
output wire M_GRANT_ANY,
output wire M_AWVALID,
input wire M_AWREADY,
output wire M_ARVALID,
input wire M_ARREADY
);
// Generates a mask for all input slots that are priority based
function [C_NUM_S-1:0] f_prio_mask
(
input integer null_arg
);
reg [C_NUM_S-1:0] mask;
integer i;
begin
mask = 0;
for (i=0; i < C_NUM_S; i=i+1) begin
mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
end
f_prio_mask = mask;
end
endfunction
// Convert 16-bit one-hot to 4-bit binary
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
reg m_valid_i = 1'b0;
reg [C_NUM_S-1:0] s_ready_i = 0;
reg [C_NUM_S-1:0] s_awvalid_reg = 0;
reg [C_NUM_S-1:0] s_arvalid_reg = 0;
wire [15:0] s_avalid;
wire m_aready;
wire [C_NUM_S-1:0] rnw;
reg grant_rnw;
reg [C_NUM_S_LOG-1:0] m_grant_enc_i;
reg [C_NUM_S-1:0] m_grant_hot_i;
reg [C_NUM_S-1:0] last_rr_hot;
reg any_grant;
reg any_prio;
reg [C_NUM_S-1:0] which_prio_hot;
reg [C_NUM_S_LOG-1:0] which_prio_enc;
reg [4:0] current_highest;
reg [15:0] next_prio_hot;
reg [C_NUM_S_LOG-1:0] next_prio_enc;
reg found_prio;
wire [C_NUM_S-1:0] valid_rr;
reg [15:0] next_rr_hot;
reg [C_NUM_S_LOG-1:0] next_rr_enc;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
reg found_rr;
wire [C_NUM_S-1:0] next_hot;
wire [C_NUM_S_LOG-1:0] next_enc;
integer i;
wire [C_AMESG_WIDTH-1:0] amesg_mux;
reg [C_AMESG_WIDTH-1:0] m_amesg_i;
wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;
genvar gen_si;
always @(posedge ACLK) begin
if (ARESET) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else if (|s_ready_i) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else begin
s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;
s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);
end
end
assign s_avalid = S_AWVALID | S_ARVALID;
assign M_AWVALID = m_valid_i & ~grant_rnw;
assign M_ARVALID = m_valid_i & grant_rnw;
assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};
assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};
assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;
assign M_GRANT_HOT = m_grant_hot_i;
assign M_GRANT_RNW = grant_rnw;
assign rnw = S_ARVALID & ~s_awvalid_reg;
assign M_AMESG = m_amesg_i;
assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;
generate
for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux
assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];
end // gen_mesg_mux
if (C_NUM_S>1) begin : gen_arbiter
/////////////////////////////////////////////////////////////////////////////
// Grant a new request when there is none still pending.
// If no qualified requests found, de-assert M_VALID.
/////////////////////////////////////////////////////////////////////////////
assign M_GRANT_ANY = any_grant;
assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
always @(posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 0;
s_ready_i <= 0;
m_grant_hot_i <= 0;
m_grant_enc_i <= 0;
any_grant <= 1'b0;
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 0;
if (m_valid_i) begin
// Stall 1 cycle after each master-side completion.
if (m_aready) begin // Master-side completion
m_valid_i <= 1'b0;
m_grant_hot_i <= 0;
any_grant <= 1'b0;
end
end else if (any_grant) begin
m_valid_i <= 1'b1;
s_ready_i <= m_grant_hot_i; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else begin
if (found_prio | found_rr) begin
m_grant_hot_i <= next_hot;
m_grant_enc_i <= next_enc;
any_grant <= 1'b1;
grant_rnw <= |(rnw & next_hot);
if (~found_prio) begin
last_rr_hot <= next_rr_hot;
end
end
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Fixed Priority arbiter
// Selects next request to grant from among inputs with PRIO > 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin : ALG_PRIO
integer ip;
any_prio = 1'b0;
which_prio_hot = 0;
which_prio_enc = 0;
current_highest = 0;
for (ip=0; ip < C_NUM_S; ip=ip+1) begin
if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin
if (s_avalid[ip]) begin
current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
any_prio = 1'b1;
which_prio_hot = 1'b1 << ip;
which_prio_enc = ip;
end
end
end
found_prio = any_prio;
next_prio_hot = which_prio_hot;
next_prio_enc = which_prio_enc;
end
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
assign valid_rr = ~P_PRIO_MASK & s_avalid;
always @ * begin : ALG_RR
integer ir, jr, nr;
next_rr_hot = 0;
for (ir=0;ir<C_NUM_S;ir=ir+1) begin
nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
for (jr=1;jr<C_NUM_S;jr=jr+1) begin
nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
if (jr < C_NUM_S-1) begin
mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
end
end
next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
end
next_rr_enc = f_hot2enc(next_rr_hot);
found_rr = |(next_rr_hot);
end
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_AMESG_WIDTH)
) si_amesg_mux_inst
(
.S (next_enc),
.A (s_amesg),
.O (amesg_mux),
.OE (1'b1)
);
always @(posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~any_grant) begin
m_amesg_i <= amesg_mux;
end
end
end else begin : gen_no_arbiter
assign M_GRANT_ANY = m_grant_hot_i;
always @ (posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 1'b0;
s_ready_i <= 1'b0;
m_grant_enc_i <= 0;
m_grant_hot_i <= 1'b0;
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 1'b0;
if (m_valid_i) begin
if (m_aready) begin
m_valid_i <= 1'b0;
m_grant_hot_i <= 1'b0;
end
end else if (m_grant_hot_i) begin
m_valid_i <= 1'b1;
s_ready_i[0] <= 1'b1; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else if (s_avalid[0]) begin
m_grant_hot_i <= 1'b1;
grant_rnw <= rnw[0];
end
end
end
always @ (posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~m_grant_hot_i) begin
m_amesg_i <= s_amesg;
end
end
end // gen_arbiter
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: addr_arbiter.v
//
// Description:
// Instantiates generic priority encoder.
// Each request is qualified if its target has not reached its issuing limit.
// Muxes mesg and target inputs based on arbitration results.
//-----------------------------------------------------------------------------
//
// Structure:
// addr_arbiter
// mux_enc
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_addr_arbiter #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 1,
parameter integer C_NUM_S_LOG = 1,
parameter integer C_NUM_M = 1,
parameter integer C_MESG_WIDTH = 1,
parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}}
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 'h0-'hF.
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S*C_MESG_WIDTH-1:0] S_MESG,
input wire [C_NUM_S*C_NUM_M-1:0] S_TARGET_HOT,
input wire [C_NUM_S-1:0] S_VALID,
input wire [C_NUM_S-1:0] S_VALID_QUAL,
output wire [C_NUM_S-1:0] S_READY,
// Master Ports
output wire [C_MESG_WIDTH-1:0] M_MESG,
output wire [C_NUM_M-1:0] M_TARGET_HOT,
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC,
output wire M_VALID,
input wire M_READY,
// Sideband input
input wire [C_NUM_M-1:0] ISSUING_LIMIT
);
// Generates a mask for all input slots that are priority based
function [C_NUM_S-1:0] f_prio_mask
(
input integer null_arg
);
reg [C_NUM_S-1:0] mask;
integer i;
begin
mask = 0;
for (i=0; i < C_NUM_S; i=i+1) begin
mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
end
f_prio_mask = mask;
end
endfunction
// Convert 16-bit one-hot to 4-bit binary
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
reg m_valid_i = 1'b0;
reg [C_NUM_S-1:0] s_ready_i = 0;
reg [C_NUM_S-1:0] qual_reg;
reg [C_NUM_S-1:0] grant_hot;
reg [C_NUM_S-1:0] last_rr_hot;
reg any_grant;
reg any_prio;
reg found_prio;
reg [C_NUM_S-1:0] which_prio_hot;
reg [C_NUM_S-1:0] next_prio_hot;
reg [C_NUM_S_LOG-1:0] which_prio_enc;
reg [C_NUM_S_LOG-1:0] next_prio_enc;
reg [4:0] current_highest;
wire [C_NUM_S-1:0] valid_rr;
reg [15:0] next_rr_hot;
reg [C_NUM_S_LOG-1:0] next_rr_enc;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
reg found_rr;
wire [C_NUM_S-1:0] next_hot;
wire [C_NUM_S_LOG-1:0] next_enc;
reg prio_stall;
integer i;
wire [C_NUM_S-1:0] valid_qual_i;
reg [C_NUM_S_LOG-1:0] m_grant_enc_i;
reg [C_NUM_M-1:0] m_target_hot_i;
wire [C_NUM_M-1:0] m_target_hot_mux;
reg [C_MESG_WIDTH-1:0] m_mesg_i;
wire [C_MESG_WIDTH-1:0] m_mesg_mux;
genvar gen_si;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
assign M_GRANT_ENC = m_grant_enc_i;
assign M_MESG = m_mesg_i;
assign M_TARGET_HOT = m_target_hot_i;
generate
if (C_NUM_S>1) begin : gen_arbiter
always @(posedge ACLK) begin
if (ARESET) begin
qual_reg <= 0;
end else begin
qual_reg <= valid_qual_i | ~S_VALID; // Don't disqualify when bus not VALID (valid_qual_i would be garbage)
end
end
for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual
assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT));
end
/////////////////////////////////////////////////////////////////////////////
// Grant a new request when there is none still pending.
// If no qualified requests found, de-assert M_VALID.
/////////////////////////////////////////////////////////////////////////////
assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
always @(posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 0;
s_ready_i <= 0;
grant_hot <= 0;
any_grant <= 1'b0;
m_grant_enc_i <= 0;
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
m_target_hot_i <= 0;
end else begin
s_ready_i <= 0;
if (m_valid_i) begin
// Stall 1 cycle after each master-side completion.
if (M_READY) begin // Master-side completion
m_valid_i <= 1'b0;
grant_hot <= 0;
any_grant <= 1'b0;
end
end else if (any_grant) begin
m_valid_i <= 1'b1;
s_ready_i <= grant_hot; // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY)
end else begin
if ((found_prio | found_rr) & ~prio_stall) begin
// Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i).
if (|(next_hot & valid_qual_i)) begin
grant_hot <= next_hot;
m_grant_enc_i <= next_enc;
any_grant <= 1'b1;
if (~found_prio) begin
last_rr_hot <= next_rr_hot;
end
m_target_hot_i <= m_target_hot_mux;
end
end
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Fixed Priority arbiter
// Selects next request to grant from among inputs with PRIO > 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin : ALG_PRIO
integer ip;
any_prio = 1'b0;
prio_stall = 1'b0;
which_prio_hot = 0;
which_prio_enc = 0;
current_highest = 0;
for (ip=0; ip < C_NUM_S; ip=ip+1) begin
// Disqualify slot if target hit issuing limit (pass to lower prio slot).
if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin
if ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin
current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
// Stall 1 cycle when highest prio is recovering from SI-side handshake.
// (Do not allow lower-prio slot to win arbitration.)
if (s_ready_i[ip]) begin
any_prio = 1'b0;
prio_stall = 1'b1;
which_prio_hot = 0;
which_prio_enc = 0;
end else begin
any_prio = 1'b1;
which_prio_hot = 1'b1 << ip;
which_prio_enc = ip;
end
end
end
end
found_prio = any_prio;
next_prio_hot = which_prio_hot;
next_prio_enc = which_prio_enc;
end
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
// Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot).
// Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i),
// and allow arbitration to pass to any other RR requester.
assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg;
always @ * begin : ALG_RR
integer ir, jr, nr;
next_rr_hot = 0;
for (ir=0;ir<C_NUM_S;ir=ir+1) begin
nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
for (jr=1;jr<C_NUM_S;jr=jr+1) begin
nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
if (jr < C_NUM_S-1) begin
mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
end
end
next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
end
next_rr_enc = f_hot2enc(next_rr_hot);
found_rr = |(next_rr_hot);
end
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_MESG_WIDTH)
) mux_mesg
(
.S (m_grant_enc_i),
.A (S_MESG),
.O (m_mesg_mux),
.OE (1'b1)
);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_NUM_M)
) si_amesg_mux_inst
(
.S (next_enc),
.A (S_TARGET_HOT),
.O (m_target_hot_mux),
.OE (1'b1)
);
always @(posedge ACLK) begin
if (ARESET) begin
m_mesg_i <= 0;
end else if (~m_valid_i) begin
m_mesg_i <= m_mesg_mux;
end
end
end else begin : gen_no_arbiter
assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT);
always @ (posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 1'b0;
s_ready_i <= 1'b0;
m_grant_enc_i <= 0;
end else begin
s_ready_i <= 1'b0;
if (m_valid_i) begin
if (M_READY) begin
m_valid_i <= 1'b0;
end
end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin
m_valid_i <= 1'b1;
s_ready_i <= 1'b1;
m_target_hot_i <= S_TARGET_HOT;
end
end
end
always @(posedge ACLK) begin
if (ARESET) begin
m_mesg_i <= 0;
end else if (~m_valid_i) begin
m_mesg_i <= S_MESG;
end
end
end // gen_arbiter
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_0_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region_or
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen = 0;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: crossbar_sasd.v
//
// Description:
// This module is a M-master to N-slave AXI axi_crossbar_v2_1_15_crossbar switch.
// Single transaction issuing, single arbiter (both W&R), single data pathways.
// The interface of this module consists of a vectored slave and master interface
// in which all slots are sized and synchronized to the native width and clock
// of the interconnect, and are all AXI4 protocol.
// All width, clock and protocol conversions are done outside this block, as are
// any pipeline registers or data FIFOs.
// This module contains all arbitration, decoders and channel multiplexing logic.
// It also contains the diagnostic registers and control interface.
//
//--------------------------------------------------------------------------
//
// Structure:
// crossbar_sasd
// addr_arbiter_sasd
// mux_enc
// addr_decoder
// comparator_static
// splitter
// mux_enc
// axic_register_slice
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_crossbar_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 1,
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0,
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter integer C_R_REGISTER = 0,
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE = 0,
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY
);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;
localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;
localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;
localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;
localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;
localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;
localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_BYPASS = 0;
localparam integer P_LIGHTWT = 7;
localparam integer P_FULLY_REG = 1;
localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice
(C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux
C_R_REGISTER;
localparam P_DECERR = 2'b11;
//---------------------------------------------------------------------------
// Functions
//---------------------------------------------------------------------------
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID
(
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer slot
);
begin
f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi
(input [C_NUM_MASTER_SLOTS*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
// AxiLite error-checking mask (on MI)
function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
genvar gen_si_slot;
genvar gen_mi_slot;
wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_armesg ;
wire [P_AMESG_WIDTH-1:0] aa_amesg ;
wire [C_AXI_ID_WIDTH-1:0] mi_aid ;
wire [C_AXI_ADDR_WIDTH-1:0] mi_aaddr ;
wire [8-1:0] mi_alen ;
wire [3-1:0] mi_asize ;
wire [2-1:0] mi_alock ;
wire [3-1:0] mi_aprot ;
wire [2-1:0] mi_aburst ;
wire [4-1:0] mi_acache ;
wire [4-1:0] mi_aregion ;
wire [4-1:0] mi_aqos ;
wire [P_AXI_AUSER_WIDTH-1:0] mi_auser ;
wire [4-1:0] target_region ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] aa_grant_hot ;
wire [P_NUM_SLAVE_SLOTS_LOG-1:0] aa_grant_enc ;
wire aa_grant_rnw ;
wire aa_grant_any ;
wire [C_NUM_MASTER_SLOTS-1:0] target_mi_hot ;
wire [P_NUM_MASTER_SLOTS_LOG-1:0] target_mi_enc ;
reg [P_NUM_MASTER_SLOTS_DE-1:0] m_atarget_hot = 0 ;
reg [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc = 0 ;
wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc_comb ;
wire match;
wire any_error ;
wire [7:0] m_aerror_i ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awready ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arready ;
wire aa_awvalid ;
wire aa_awready ;
wire aa_arvalid ;
wire aa_arready ;
wire mi_awvalid_en;
wire mi_awready_mux;
wire mi_arvalid_en;
wire mi_arready_mux;
wire w_transfer_en;
wire w_complete_mux;
wire b_transfer_en;
wire b_complete_mux;
wire r_transfer_en;
wire r_complete_mux;
wire target_secure;
wire target_write;
wire target_read;
wire target_axilite;
wire [P_BMESG_WIDTH-1:0] si_bmesg ;
wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0] mi_bmesg ;
wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_bresp ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0] mi_buser ;
wire [2-1:0] si_bresp ;
wire [C_AXI_BUSER_WIDTH-1:0] si_buser ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bready ;
wire aa_bvalid ;
wire aa_bready ;
wire si_bready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_bvalid;
wire [P_RMESG_WIDTH-1:0] aa_rmesg ;
wire [P_RMESG_WIDTH-1:0] sr_rmesg ;
wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0] mi_rmesg ;
wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_rresp ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0] mi_ruser ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0] mi_rdata ;
wire [P_NUM_MASTER_SLOTS_DE*1-1:0] mi_rlast ;
wire [2-1:0] si_rresp ;
wire [C_AXI_RUSER_WIDTH-1:0] si_ruser ;
wire [C_AXI_DATA_WIDTH-1:0] si_rdata ;
wire si_rlast ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rready ;
wire aa_rvalid ;
wire aa_rready ;
wire sr_rvalid ;
wire si_rready ;
wire sr_rready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_rvalid;
wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0] si_wmesg ;
wire [P_WMESG_WIDTH-1:0] mi_wmesg ;
wire [C_AXI_ID_WIDTH-1:0] mi_wid ;
wire [C_AXI_DATA_WIDTH-1:0] mi_wdata ;
wire [C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ;
wire [C_AXI_WUSER_WIDTH-1:0] mi_wuser ;
wire [1-1:0] mi_wlast ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wready ;
wire aa_wvalid ;
wire aa_wready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_wready;
reg [7:0] debug_r_beat_cnt_i;
reg [7:0] debug_w_beat_cnt_i;
reg [7:0] debug_aw_trans_seq_i;
reg [7:0] debug_ar_trans_seq_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (~ARESETN) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ARESETN;
end
end
wire reset;
assign reset = ~aresetn_d;
generate
axi_crossbar_v2_1_15_addr_arbiter_sasd #
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_AMESG_WIDTH (P_AMESG_WIDTH),
.C_GRANT_ENC (1),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_inst
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AW command request inputs
.S_AWMESG (si_awmesg),
.S_ARMESG (si_armesg),
.S_AWVALID (S_AXI_AWVALID),
.S_AWREADY (S_AXI_AWREADY),
.S_ARVALID (S_AXI_ARVALID),
.S_ARREADY (S_AXI_ARREADY),
.M_GRANT_ENC (aa_grant_enc),
.M_GRANT_HOT (aa_grant_hot), // SI-slot 1-hot mask of granted command
.M_GRANT_ANY (aa_grant_any),
.M_GRANT_RNW (aa_grant_rnw),
.M_AMESG (aa_amesg), // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.
.M_AWVALID (aa_awvalid),
.M_AWREADY (aa_awready),
.M_ARVALID (aa_arvalid),
.M_ARREADY (aa_arready)
);
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_15_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_MASTER_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL ({C_NUM_MASTER_SLOTS{1'b1}}),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (mi_aaddr),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign match = 1'b1;
assign target_region = 4'b0000;
end // gen_addr_decoder
// AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.
axi_crossbar_v2_1_15_splitter #
(
.C_NUM_M (3)
)
splitter_aw
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_awvalid),
.S_READY (aa_awready),
.M_VALID ({mi_awvalid_en, w_transfer_en, b_transfer_en}),
.M_READY ({mi_awready_mux, w_complete_mux, b_complete_mux})
);
// AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.
axi_crossbar_v2_1_15_splitter #
(
.C_NUM_M (2)
)
splitter_ar
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_arvalid),
.S_READY (aa_arready),
.M_VALID ({mi_arvalid_en, r_transfer_en}),
.M_READY ({mi_arready_mux, r_complete_mux})
);
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);
assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);
assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) ||
(mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||
(aa_grant_rnw && ~target_read); // R/W direction unsupported by target
assign m_aerror_i[7:4] = 4'b0000; // Reserved
assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc; // Select MI slot or decerr_slave
always @(posedge ACLK) begin
if (reset) begin
m_atarget_hot <= 0;
m_atarget_enc <= 0;
end else begin
m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot}); // Select MI slot or decerr_slave
m_atarget_enc <= m_atarget_enc_comb;
end
end
// Receive AWREADY from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_awready_mux_inst
(
.S (m_atarget_enc),
.A (mi_awready),
.O (mi_awready_mux),
.OE (mi_awvalid_en)
);
// Receive ARREADY from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_arready_mux_inst
(
.S (m_atarget_enc),
.A (mi_arready),
.O (mi_arready_mux),
.OE (mi_arvalid_en)
);
assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}}; // Assert AWVALID on targeted MI.
assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}}; // Assert ARVALID on targeted MI.
assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots.
assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots.
assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; // Copy from MI slots.
assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // Copy from MI slots.
// Receive WREADY from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_wready_mux_inst
(
.S (m_atarget_enc),
.A (mi_wready),
.O (aa_wready),
.OE (w_transfer_en)
);
assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}}; // Assert WVALID on targeted MI.
assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}}; // Assert WREADY on granted SI.
assign S_AXI_WREADY = si_wready;
assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast; // W burst complete on on designated SI/MI.
// Receive RREADY from granted SI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_rready_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_RREADY),
.O (si_rready),
.OE (r_transfer_en)
);
assign sr_rready = si_rready & r_transfer_en;
assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}}; // Assert RREADY on targeted MI.
assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}}; // Assert RVALID on granted SI.
assign S_AXI_RVALID = si_rvalid;
assign r_complete_mux = sr_rready & sr_rvalid & si_rlast; // R burst complete on on designated SI/MI.
// Receive BREADY from granted SI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_bready_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_BREADY),
.O (si_bready),
.OE (b_transfer_en)
);
assign aa_bready = si_bready & b_transfer_en;
assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}}; // Assert BREADY on targeted MI.
assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}}; // Assert BVALID on granted SI.
assign S_AXI_BVALID = si_bvalid;
assign b_complete_mux = aa_bready & aa_bvalid; // B transfer complete on on designated SI/MI.
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg
assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB
4'b0000,
// S_AXI_ARREGION[gen_si_slot*4+:4],
S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],
S_AXI_ARQOS[gen_si_slot*4+:4],
S_AXI_ARCACHE[gen_si_slot*4+:4],
S_AXI_ARBURST[gen_si_slot*2+:2],
S_AXI_ARPROT[gen_si_slot*3+:3],
S_AXI_ARLOCK[gen_si_slot*2+:2],
S_AXI_ARSIZE[gen_si_slot*3+:3],
S_AXI_ARLEN[gen_si_slot*8+:8],
S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)
};
assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB
4'b0000,
// S_AXI_AWREGION[gen_si_slot*4+:4],
S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],
S_AXI_AWQOS[gen_si_slot*4+:4],
S_AXI_AWCACHE[gen_si_slot*4+:4],
S_AXI_AWBURST[gen_si_slot*2+:2],
S_AXI_AWPROT[gen_si_slot*3+:3],
S_AXI_AWLOCK[gen_si_slot*2+:2],
S_AXI_AWSIZE[gen_si_slot*3+:3],
S_AXI_AWLEN[gen_si_slot*8+:8],
S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)
};
end // gen_si_amesg
assign mi_aid = aa_amesg[0 +: C_AXI_ID_WIDTH];
assign mi_aaddr = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];
assign mi_alen = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];
assign mi_asize = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];
assign mi_alock = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];
assign mi_aprot = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];
assign mi_aburst = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];
assign mi_acache = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];
assign mi_aqos = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];
assign mi_auser = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];
assign mi_aregion = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];
// Broadcast AW transfer payload to all MI-slots
assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{mi_aid}};
assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}};
assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{mi_alen }};
assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{mi_asize}};
assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{mi_alock}};
assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{mi_aprot}};
assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{mi_aregion}};
assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{mi_aburst}};
assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{mi_acache}};
assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{mi_aqos }};
assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};
// Broadcast AR transfer payload to all MI-slots
assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{mi_aid}};
assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}};
assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{mi_alen }};
assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{mi_asize}};
assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{mi_alock}};
assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{mi_aprot}};
assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{mi_aregion}};
assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{mi_aburst}};
assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{mi_acache}};
assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{mi_aqos }};
assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};
// W-channel MI handshakes
assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
// Broadcast W transfer payload to all MI-slots
assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};
assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};
assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};
assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};
assign M_AXI_WID = {C_NUM_MASTER_SLOTS{mi_wid}};
// Broadcast R transfer payload to all SI-slots
assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};
assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};
assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};
assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};
assign S_AXI_RID = {C_NUM_SLAVE_SLOTS{mi_aid}};
// Broadcast B transfer payload to all SI-slots
assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};
assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};
assign S_AXI_BID = {C_NUM_SLAVE_SLOTS{mi_aid}};
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI WVALID mux.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_w_valid_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_WVALID),
.O (aa_wvalid),
.OE (w_transfer_en)
);
// SI W-channel payload mux
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (P_WMESG_WIDTH)
) si_w_payload_mux_inst
(
.S (aa_grant_enc),
.A (si_wmesg),
.O (mi_wmesg),
.OE (1'b1)
);
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg
assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = { // Concatenate from MSB to LSB
((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),
S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
S_AXI_WLAST[gen_si_slot*1+:1]
};
end // gen_wmesg
assign mi_wlast = mi_wmesg[0];
assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];
assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
assign mi_wid = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
end else begin : gen_no_wmux
assign aa_wvalid = w_transfer_en & S_AXI_WVALID;
assign mi_wlast = S_AXI_WLAST;
assign mi_wdata = S_AXI_WDATA;
assign mi_wstrb = S_AXI_WSTRB;
assign mi_wuser = S_AXI_WUSER;
assign mi_wid = S_AXI_WID;
end // gen_wmux
// Receive RVALID from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_rvalid_mux_inst
(
.S (m_atarget_enc),
.A (mi_rvalid),
.O (aa_rvalid),
.OE (r_transfer_en)
);
// MI R-channel payload mux
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (P_RMESG_WIDTH)
) mi_rmesg_mux_inst
(
.S (m_atarget_enc),
.A (mi_rmesg),
.O (aa_rmesg),
.OE (1'b1)
);
axi_register_slice_v2_1_14_axic_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (P_RMESG_WIDTH),
.C_REG_CONFIG (P_R_REG_CONFIG)
)
reg_slice_r
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(aa_rmesg),
.S_VALID(aa_rvalid),
.S_READY(aa_rready),
// Master side
.M_PAYLOAD_DATA(sr_rmesg),
.M_VALID(sr_rvalid),
.M_READY(sr_rready)
);
assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID;
assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST;
assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg
assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = { // Concatenate from MSB to LSB
mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
mi_rresp[gen_mi_slot*2+:2],
mi_rlast[gen_mi_slot*1+:1]
};
end // gen_rmesg
assign si_rlast = sr_rmesg[0];
assign si_rresp = sr_rmesg[1 +: 2];
assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];
assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];
// Receive BVALID from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_bvalid_mux_inst
(
.S (m_atarget_enc),
.A (mi_bvalid),
.O (aa_bvalid),
.OE (b_transfer_en)
);
// MI B-channel payload mux
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (P_BMESG_WIDTH)
) mi_bmesg_mux_inst
(
.S (m_atarget_enc),
.A (mi_bmesg),
.O (si_bmesg),
.OE (1'b1)
);
assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID;
assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg
assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = { // Concatenate from MSB to LSB
mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
mi_bresp[gen_mi_slot*2+:2]
};
end // gen_bmesg
assign si_bresp = si_bmesg[0 +: 2];
assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];
if (C_DEBUG) begin : gen_debug_trans_seq
// DEBUG WRITE TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_aw_trans_seq_i <= 1;
end else begin
if (aa_awvalid && aa_awready) begin
debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
end
end
end
// DEBUG READ TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_ar_trans_seq_i <= 1;
end else begin
if (aa_arvalid && aa_arready) begin
debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
end
end
end
// DEBUG WRITE BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_w_beat_cnt_i <= 0;
end else if (aa_wready & aa_wvalid) begin
if (mi_wlast) begin
debug_w_beat_cnt_i <= 0;
end else begin
debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;
end
end
end // Clocked process
// DEBUG READ BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_r_beat_cnt_i <= 0;
end else if (sr_rready & sr_rvalid) begin
if (si_rlast) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end // Clocked process
end // gen_debug_trans_seq
if (C_RANGE_CHECK) begin : gen_decerr
// Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler
axi_crossbar_v2_1_15_decerr_slave #
(
.C_AXI_ID_WIDTH (1),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_RESP (P_DECERR)
)
decerr_slave_inst
(
.S_AXI_ACLK (ACLK),
.S_AXI_ARESET (reset),
.S_AXI_AWID (1'b0),
.S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
.S_AXI_WLAST (mi_wlast),
.S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
.S_AXI_BID (),
.S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
.S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
.S_AXI_ARID (1'b0),
.S_AXI_ARLEN (mi_alen),
.S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
.S_AXI_RID (),
.S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
.S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
.S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
);
end // gen_decerr
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: crossbar.v
//
// Description:
// This module is a M-master to N-slave AXI axi_crossbar_v2_1_15_crossbar switch.
// The interface of this module consists of a vectored slave and master interface
// in which all slots are sized and synchronized to the native width and clock
// of the interconnect.
// The SAMD axi_crossbar_v2_1_15_crossbar supports only AXI4 and AXI3 protocols.
// All width, clock and protocol conversions are done outside this block, as are
// any pipeline registers or data FIFOs.
// This module contains all arbitration, decoders and channel multiplexing logic.
// It also contains the diagnostic registers and control interface.
//
//-----------------------------------------------------------------------------
//
// Structure:
// crossbar
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
// splitter
// wdata_router
// axic_reg_srl_fifo
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
// addr_decoder
// comparator_static
// axic_srl_fifo
// axi_register_slice
// addr_arbiter
// mux_enc
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_crossbar #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 1,
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0,
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE = 0,
parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}},
parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY
);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);
localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);
localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;
localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;
localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;
localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;
localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;
localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
localparam [31:0] P_BYPASS = 32'h00000000;
localparam [31:0] P_FWD_REV = 32'h00000001;
localparam [31:0] P_SIMPLE = 32'h00000007;
localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};
localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);
localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
localparam P_DECERR = 2'b11;
//---------------------------------------------------------------------------
// Functions
//---------------------------------------------------------------------------
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID
(
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer slot
);
begin
f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
end
endfunction
// Write connectivity array transposed
function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity
(
input integer null_arg
);
integer si_slot;
integer mi_slot;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS*32{1'b1}};
for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];
end
end
f_si_write_connectivity = result;
end
endfunction
// Read connectivity array transposed
function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity
(
input integer null_arg
);
integer si_slot;
integer mi_slot;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS*32{1'b1}};
for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];
end
end
f_si_read_connectivity = result;
end
endfunction
genvar gen_si_slot;
genvar gen_mi_slot;
wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] si_st_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] st_tmp_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0] tmp_aa_awmesg ;
wire [P_AA_AWMESG_WIDTH-1:0] aa_mi_awmesg ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_awlock ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awprot ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_awregion ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awerror ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_awtarget_hot ;
wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_awtarget_enc ;
wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_wm_awgrant_enc ;
wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_awtarget_hot ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_awvalid_qual ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awready ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awready ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awready ;
wire aa_sa_awvalid ;
wire aa_sa_awready ;
wire aa_mi_arready ;
wire mi_awvalid_en ;
wire sa_wm_awvalid_en ;
wire sa_wm_awready_mux ;
wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] si_st_armesg ;
wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] st_tmp_armesg ;
wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0] tmp_aa_armesg ;
wire [P_AA_ARMESG_WIDTH-1:0] aa_mi_armesg ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_arlock ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arprot ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_arregion ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arerror ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_artarget_hot ;
wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_artarget_enc ;
wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_artarget_hot ;
wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_mi_argrant_enc ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid_qual ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arready ;
wire aa_mi_arvalid ;
wire mi_awready_mux ;
wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0] st_si_bmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0] st_mr_bmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_bid ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_bresp ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] st_mr_buser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_bid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_bid_target_i ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] bid_match ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_bid ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_bresp ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] mi_buser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] bready_carry ;
wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0] st_si_rmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0] st_mr_rmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_rid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] st_mr_rdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] st_mr_ruser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rlast ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_rresp ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_rid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_rid_target_i ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] rid_match ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_rid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_rdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] mi_ruser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rlast ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_rresp ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] rready_carry ;
wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] si_wr_wmesg ;
wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] wr_wm_wmesg ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] wr_wm_wlast ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wvalid ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0] wm_mr_wmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] wm_mr_wdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] wm_mr_wstrb ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] wm_mr_wid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] wm_mr_wuser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wlast ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_wdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] mi_wuser ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_wid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wlast ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_push ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_pop ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_push ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_pop ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awmaxissuing ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_armaxissuing ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] w_issuing_cnt ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] r_issuing_cnt ;
reg [8-1:0] debug_aw_trans_seq_i ;
reg [8-1:0] debug_ar_trans_seq_i ;
wire [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_trans_seq_i ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_beat_cnt_i ;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (~ARESETN) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ARESETN;
end
end
wire reset;
assign reset = ~aresetn_d;
generate
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots
if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read
axi_crossbar_v2_1_15_si_transactor # // "ST": SI Transactor (read channel)
(
.C_FAMILY (C_FAMILY),
.C_SI (gen_si_slot),
.C_DIR (P_READ),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_NUM_M (C_NUM_MASTER_SLOTS),
.C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),
.C_ACCEPTANCE_LOG (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),
.C_ID_WIDTH (C_AXI_ID_WIDTH),
.C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AMESG_WIDTH (P_ST_ARMESG_WIDTH),
.C_RMESG_WIDTH (P_ST_RMESG_WIDTH),
.C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (C_RANGE_CHECK),
.C_ADDR_DECODE (C_ADDR_DECODE),
.C_ERR_MODE (C_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
si_transactor_ar
(
.ACLK (ACLK),
.ARESET (reset),
.S_AID (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
.S_AADDR (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.S_ALEN (S_AXI_ARLEN[gen_si_slot*8+:8]),
.S_ASIZE (S_AXI_ARSIZE[gen_si_slot*3+:3]),
.S_ABURST (S_AXI_ARBURST[gen_si_slot*2+:2]),
.S_ALOCK (S_AXI_ARLOCK[gen_si_slot*2+:2]),
.S_APROT (S_AXI_ARPROT[gen_si_slot*3+:3]),
// .S_AREGION (S_AXI_ARREGION[gen_si_slot*4+:4]),
.S_AMESG (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
.S_AVALID (S_AXI_ARVALID[gen_si_slot]),
.S_AREADY (S_AXI_ARREADY[gen_si_slot]),
.M_AID (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.M_AADDR (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.M_ALEN (st_aa_arlen[gen_si_slot*8+:8]),
.M_ASIZE (st_aa_arsize[gen_si_slot*3+:3]),
.M_ALOCK (st_aa_arlock[gen_si_slot*2+:2]),
.M_APROT (st_aa_arprot[gen_si_slot*3+:3]),
.M_AREGION (st_aa_arregion[gen_si_slot*4+:4]),
.M_AMESG (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
.M_ATARGET_HOT (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_ATARGET_ENC (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
.M_AERROR (st_aa_arerror[gen_si_slot*8+:8]),
.M_AVALID_QUAL (st_aa_arvalid_qual[gen_si_slot]),
.M_AVALID (st_aa_arvalid[gen_si_slot]),
.M_AREADY (st_aa_arready[gen_si_slot]),
.S_RID (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_RMESG (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),
.S_RLAST (S_AXI_RLAST[gen_si_slot]),
.S_RVALID (S_AXI_RVALID[gen_si_slot]),
.S_RREADY (S_AXI_RREADY[gen_si_slot]),
.M_RID (st_mr_rid),
.M_RLAST (st_mr_rlast),
.M_RMESG (st_mr_rmesg),
.M_RVALID (st_mr_rvalid),
.M_RREADY (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_RTARGET (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_ar_trans_seq_i : 8'h0)
);
assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {
S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],
S_AXI_ARQOS[gen_si_slot*4+:4],
S_AXI_ARCACHE[gen_si_slot*4+:4],
S_AXI_ARBURST[gen_si_slot*2+:2]
};
assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {
st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],
st_aa_arregion[gen_si_slot*4+:4],
st_aa_arprot[gen_si_slot*3+:3],
st_aa_arlock[gen_si_slot*2+:2],
st_aa_arsize[gen_si_slot*3+:3],
st_aa_arlen[gen_si_slot*8+:8],
st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
};
assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];
assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];
assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];
end else begin : gen_no_si_read
assign S_AXI_ARREADY[gen_si_slot] = 1'b0;
assign st_aa_arvalid[gen_si_slot] = 1'b0;
assign st_aa_arvalid_qual[gen_si_slot] = 1'b1;
assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;
assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;
assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign S_AXI_RVALID[gen_si_slot] = 1'b0;
assign S_AXI_RLAST[gen_si_slot] = 1'b0;
assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
end // gen_si_read
if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write
axi_crossbar_v2_1_15_si_transactor # // "ST": SI Transactor (write channel)
(
.C_FAMILY (C_FAMILY),
.C_SI (gen_si_slot),
.C_DIR (P_WRITE),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_NUM_M (C_NUM_MASTER_SLOTS),
.C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),
.C_ACCEPTANCE_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),
.C_ID_WIDTH (C_AXI_ID_WIDTH),
.C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AMESG_WIDTH (P_ST_AWMESG_WIDTH),
.C_RMESG_WIDTH (P_ST_BMESG_WIDTH),
.C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (C_RANGE_CHECK),
.C_ADDR_DECODE (C_ADDR_DECODE),
.C_ERR_MODE (C_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
si_transactor_aw
(
.ACLK (ACLK),
.ARESET (reset),
.S_AID (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
.S_AADDR (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.S_ALEN (S_AXI_AWLEN[gen_si_slot*8+:8]),
.S_ASIZE (S_AXI_AWSIZE[gen_si_slot*3+:3]),
.S_ABURST (S_AXI_AWBURST[gen_si_slot*2+:2]),
.S_ALOCK (S_AXI_AWLOCK[gen_si_slot*2+:2]),
.S_APROT (S_AXI_AWPROT[gen_si_slot*3+:3]),
// .S_AREGION (S_AXI_AWREGION[gen_si_slot*4+:4]),
.S_AMESG (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
.S_AVALID (S_AXI_AWVALID[gen_si_slot]),
.S_AREADY (S_AXI_AWREADY[gen_si_slot]),
.M_AID (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.M_AADDR (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.M_ALEN (st_aa_awlen[gen_si_slot*8+:8]),
.M_ASIZE (st_aa_awsize[gen_si_slot*3+:3]),
.M_ALOCK (st_aa_awlock[gen_si_slot*2+:2]),
.M_APROT (st_aa_awprot[gen_si_slot*3+:3]),
.M_AREGION (st_aa_awregion[gen_si_slot*4+:4]),
.M_AMESG (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
.M_ATARGET_HOT (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_ATARGET_ENC (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
.M_AERROR (st_aa_awerror[gen_si_slot*8+:8]),
.M_AVALID_QUAL (st_aa_awvalid_qual[gen_si_slot]),
.M_AVALID (st_ss_awvalid[gen_si_slot]),
.M_AREADY (st_ss_awready[gen_si_slot]),
.S_RID (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_RMESG (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),
.S_RLAST (),
.S_RVALID (S_AXI_BVALID[gen_si_slot]),
.S_RREADY (S_AXI_BREADY[gen_si_slot]),
.M_RID (st_mr_bid),
.M_RLAST ({(C_NUM_MASTER_SLOTS+1){1'b1}}),
.M_RMESG (st_mr_bmesg),
.M_RVALID (st_mr_bvalid),
.M_RREADY (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_RTARGET (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_aw_trans_seq_i : 8'h0)
);
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {
S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],
S_AXI_AWQOS[gen_si_slot*4+:4],
S_AXI_AWCACHE[gen_si_slot*4+:4],
S_AXI_AWBURST[gen_si_slot*2+:2]
};
assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {
st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],
st_aa_awregion[gen_si_slot*4+:4],
st_aa_awprot[gen_si_slot*3+:3],
st_aa_awlock[gen_si_slot*2+:2],
st_aa_awsize[gen_si_slot*3+:3],
st_aa_awlen[gen_si_slot*8+:8],
st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
};
assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];
assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];
// AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration
axi_crossbar_v2_1_15_splitter # // "SS": Splitter from SI-Transactor (write channel)
(
.C_NUM_M (2)
)
splitter_aw_si
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (st_ss_awvalid[gen_si_slot]),
.S_READY (st_ss_awready[gen_si_slot]),
.M_VALID ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),
.M_READY ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})
);
axi_crossbar_v2_1_15_wdata_router # // "WR": Write data Router
(
.C_FAMILY (C_FAMILY),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS+1),
.C_SELECT_WIDTH (P_NUM_MASTER_SLOTS_LOG+1),
.C_WMESG_WIDTH (P_WR_WMESG_WIDTH),
.C_FIFO_DEPTH_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])
)
wdata_router_w
(
.ACLK (ACLK),
.ARESET (reset),
// Write transfer input from the current SI-slot
.S_WMESG (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
.S_WLAST (S_AXI_WLAST[gen_si_slot]),
.S_WVALID (S_AXI_WVALID[gen_si_slot]),
.S_WREADY (S_AXI_WREADY[gen_si_slot]),
// Vector of write transfer outputs to each MI-slot's W-mux
.M_WMESG (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),
.M_WLAST (wr_wm_wlast[gen_si_slot]),
.M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
// AW command push from local SI-slot
.S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), // Target MI-slot
.S_AVALID (ss_wr_awvalid[gen_si_slot]),
.S_AREADY (ss_wr_awready[gen_si_slot])
);
assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {
((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),
S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]
};
end else begin : gen_no_si_write
assign S_AXI_AWREADY[gen_si_slot] = 1'b0;
assign ss_aa_awvalid[gen_si_slot] = 1'b0;
assign st_aa_awvalid_qual[gen_si_slot] = 1'b1;
assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;
assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;
assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
assign S_AXI_BVALID[gen_si_slot] = 1'b0;
assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign S_AXI_WREADY[gen_si_slot] = 1'b0;
assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;
assign wr_wm_wlast[gen_si_slot] = 1'b0;
assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
end // gen_si_write
end // gen_slave_slots
for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots
if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read
if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder
axi_crossbar_v2_1_15_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_SLAVE_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_NUM_RANGES (1),
.C_ADDR_WIDTH (C_AXI_ID_WIDTH),
.C_TARGET_ENC (C_DEBUG),
.C_TARGET_HOT (1),
.C_REGION_ENC (0),
.C_BASE_ADDR (C_S_AXI_BASE_ID),
.C_HIGH_ADDR (C_S_AXI_HIGH_ID),
.C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
.C_RESOLUTION (0)
)
rid_decoder_inst
(
.ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),
.MATCH (rid_match[gen_mi_slot]),
.REGION ()
);
end else begin : gen_no_rid_decoder
assign tmp_mr_rid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot.
assign rid_match[gen_mi_slot] = 1'b1;
end
assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {
st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
st_mr_rresp[gen_mi_slot*2+:2]
};
end else begin : gen_no_mi_read
assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign rid_match[gen_mi_slot] = 1'b0;
assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;
end // gen_mi_read
if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write
if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder
axi_crossbar_v2_1_15_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_SLAVE_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_NUM_RANGES (1),
.C_ADDR_WIDTH (C_AXI_ID_WIDTH),
.C_TARGET_ENC (C_DEBUG),
.C_TARGET_HOT (1),
.C_REGION_ENC (0),
.C_BASE_ADDR (C_S_AXI_BASE_ID),
.C_HIGH_ADDR (C_S_AXI_HIGH_ID),
.C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
.C_RESOLUTION (0)
)
bid_decoder_inst
(
.ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),
.MATCH (bid_match[gen_mi_slot]),
.REGION ()
);
end else begin : gen_no_bid_decoder
assign tmp_mr_bid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot.
assign bid_match[gen_mi_slot] = 1'b1;
end
axi_crossbar_v2_1_15_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler)
(
.C_FAMILY (C_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_WMESG_WIDTH (P_WR_WMESG_WIDTH),
.C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])
)
wdata_mux_w
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of write transfer inputs from each SI-slot's W-router
.S_WMESG (wr_wm_wmesg),
.S_WLAST (wr_wm_wlast),
.S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
// Write transfer output to the current MI-slot
.M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
.M_WLAST (wm_mr_wlast[gen_mi_slot]),
.M_WVALID (wm_mr_wvalid[gen_mi_slot]),
.M_WREADY (wm_mr_wready[gen_mi_slot]),
// AW command push from AW arbiter output
.S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter
.S_AVALID (sa_wm_awvalid[gen_mi_slot]),
.S_AREADY (sa_wm_awready[gen_mi_slot])
);
if (C_DEBUG) begin : gen_debug_w
// DEBUG WRITE BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
end else begin
if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin
if (mi_wlast[gen_mi_slot]) begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
end else begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;
end
end
end
end // clocked process
// DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE
axi_data_fifo_v2_1_13_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),
.C_USE_FULL (0)
)
debug_w_seq_fifo
(
.ACLK (ACLK),
.ARESET (reset),
.S_MESG (debug_aw_trans_seq_i),
.S_VALID (sa_wm_awvalid[gen_mi_slot]),
.S_READY (),
.M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]),
.M_VALID (),
.M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])
);
end // gen_debug_w
assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];
assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {
st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
st_mr_bresp[gen_mi_slot*2+:2]
};
end else begin : gen_no_mi_write
assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign bid_match[gen_mi_slot] = 1'b0;
assign wm_mr_wvalid[gen_mi_slot] = 0;
assign wm_mr_wlast[gen_mi_slot] = 0;
assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;
assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;
assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;
assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign sa_wm_awready[gen_mi_slot] = 0;
end // gen_mi_write
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si
// Transpose handshakes from W-router (SxM) to W-mux (MxS).
assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];
assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
// Transpose response enables from ID decoders (MxS) to si_transactors (SxM).
assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
end // gen_trans_si
assign bready_carry[gen_mi_slot] = st_tmp_bready[gen_mi_slot];
assign rready_carry[gen_mi_slot] = st_tmp_rready[gen_mi_slot];
for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si
assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_BREADY if ...
bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ...
st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates BREADY for that MI-slot.
assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_RREADY if ...
rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ...
st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates RREADY for that MI-slot.
end // gen_resp_carry_si
assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
// Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.
assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] ==
P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];
assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] ==
P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];
always @(posedge ACLK) begin
if (reset) begin
w_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0
r_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0
end else begin
if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin
w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
end
if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin
r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
end
end
end // Clocked process
// Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.
// (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)
// Reg-slice incurs +1 latency, but no bubble-cycles.
axi_register_slice_v2_1_14_axi_register_slice # // "MR": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (1),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (1),
.C_AXI_ARUSER_WIDTH (1),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_REG_CONFIG_AW (P_BYPASS),
.C_REG_CONFIG_AR (P_BYPASS),
.C_REG_CONFIG_W (P_BYPASS),
.C_REG_CONFIG_R (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),
.C_REG_CONFIG_B (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)
)
reg_slice_mi
(
.aresetn (ARESETN),
.aclk (ACLK),
.s_axi_awid ({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_awaddr ({1{1'b0}}),
.s_axi_awlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),
.s_axi_awsize ({3{1'b0}}),
.s_axi_awburst ({2{1'b0}}),
.s_axi_awlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),
.s_axi_awcache ({4{1'b0}}),
.s_axi_awprot ({3{1'b0}}),
.s_axi_awregion ({4{1'b0}}),
.s_axi_awqos ({4{1'b0}}),
.s_axi_awuser ({1{1'b0}}),
.s_axi_awvalid ({1{1'b0}}),
.s_axi_awready (),
.s_axi_wid (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.s_axi_wdata (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.s_axi_wstrb (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
.s_axi_wlast (wm_mr_wlast[gen_mi_slot]),
.s_axi_wuser (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
.s_axi_wvalid (wm_mr_wvalid[gen_mi_slot]),
.s_axi_wready (wm_mr_wready[gen_mi_slot]),
.s_axi_bid (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.s_axi_bresp (st_mr_bresp[gen_mi_slot*2+:2] ),
.s_axi_buser (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
.s_axi_bvalid (st_mr_bvalid[gen_mi_slot*1+:1] ),
.s_axi_bready (st_mr_bready[gen_mi_slot*1+:1] ),
.s_axi_arid ({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_araddr ({1{1'b0}}),
.s_axi_arlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),
.s_axi_arsize ({3{1'b0}}),
.s_axi_arburst ({2{1'b0}}),
.s_axi_arlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),
.s_axi_arcache ({4{1'b0}}),
.s_axi_arprot ({3{1'b0}}),
.s_axi_arregion ({4{1'b0}}),
.s_axi_arqos ({4{1'b0}}),
.s_axi_aruser ({1{1'b0}}),
.s_axi_arvalid ({1{1'b0}}),
.s_axi_arready (),
.s_axi_rid (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.s_axi_rdata (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ),
.s_axi_rresp (st_mr_rresp[gen_mi_slot*2+:2] ),
.s_axi_rlast (st_mr_rlast[gen_mi_slot*1+:1] ),
.s_axi_ruser (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ),
.s_axi_rvalid (st_mr_rvalid[gen_mi_slot*1+:1] ),
.s_axi_rready (st_mr_rready[gen_mi_slot*1+:1] ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready ({1{1'b0}}),
.m_axi_wid (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.m_axi_wdata (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.m_axi_wstrb (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
.m_axi_wlast (mi_wlast[gen_mi_slot]),
.m_axi_wuser (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
.m_axi_wvalid (mi_wvalid[gen_mi_slot]),
.m_axi_wready (mi_wready[gen_mi_slot]),
.m_axi_bid (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.m_axi_bresp (mi_bresp[gen_mi_slot*2+:2] ),
.m_axi_buser (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
.m_axi_bvalid (mi_bvalid[gen_mi_slot*1+:1] ),
.m_axi_bready (mi_bready[gen_mi_slot*1+:1] ),
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready ({1{1'b0}}),
.m_axi_rid (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.m_axi_rdata (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ),
.m_axi_rresp (mi_rresp[gen_mi_slot*2+:2] ),
.m_axi_rlast (mi_rlast[gen_mi_slot*1+:1] ),
.m_axi_ruser (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ),
.m_axi_rvalid (mi_rvalid[gen_mi_slot*1+:1] ),
.m_axi_rready (mi_rready[gen_mi_slot*1+:1] )
);
end // gen_master_slots (Next gen_mi_slot)
// Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.
assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1];
assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1];
// Assign MI-side B, R and W channel ports (exclude error handler signals).
assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;
assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID;
assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;
assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST;
assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID;
assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];
assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;
assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];
assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];
assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
axi_crossbar_v2_1_15_addr_arbiter # // "AA": Addr Arbiter (AW channel)
(
.C_FAMILY (C_FAMILY),
.C_NUM_M (C_NUM_MASTER_SLOTS+1),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_MESG_WIDTH (P_AA_AWMESG_WIDTH),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_aw
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AW command request inputs
.S_MESG (tmp_aa_awmesg),
.S_TARGET_HOT (st_aa_awtarget_hot),
.S_VALID (ss_aa_awvalid),
.S_VALID_QUAL (st_aa_awvalid_qual),
.S_READY (ss_aa_awready),
// Granted AW command output
.M_MESG (aa_mi_awmesg),
.M_TARGET_HOT (aa_mi_awtarget_hot), // MI-slot targeted by granted command
.M_GRANT_ENC (aa_wm_awgrant_enc), // SI-slot index of granted command
.M_VALID (aa_sa_awvalid),
.M_READY (aa_sa_awready),
.ISSUING_LIMIT (mi_awmaxissuing)
);
// Broadcast AW transfer payload to all MI-slots
assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};
assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};
axi_crossbar_v2_1_15_addr_arbiter # // "AA": Addr Arbiter (AR channel)
(
.C_FAMILY (C_FAMILY),
.C_NUM_M (C_NUM_MASTER_SLOTS+1),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_MESG_WIDTH (P_AA_ARMESG_WIDTH),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_ar
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AR command request inputs
.S_MESG (tmp_aa_armesg),
.S_TARGET_HOT (st_aa_artarget_hot),
.S_VALID_QUAL (st_aa_arvalid_qual),
.S_VALID (st_aa_arvalid),
.S_READY (st_aa_arready),
// Granted AR command output
.M_MESG (aa_mi_armesg),
.M_TARGET_HOT (aa_mi_artarget_hot), // MI-slot targeted by granted command
.M_GRANT_ENC (aa_mi_argrant_enc),
.M_VALID (aa_mi_arvalid), // SI-slot index of granted command
.M_READY (aa_mi_arready),
.ISSUING_LIMIT (mi_armaxissuing)
);
if (C_DEBUG) begin : gen_debug_trans_seq
// DEBUG WRITE TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_aw_trans_seq_i <= 1;
end else begin
if (aa_sa_awvalid && aa_sa_awready) begin
debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
end
end
end
// DEBUG READ TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_ar_trans_seq_i <= 1;
end else begin
if (aa_mi_arvalid && aa_mi_arready) begin
debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
end
end
end
end // gen_debug_trans_seq
// Broadcast AR transfer payload to all MI-slots
assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};
assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};
// AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).
axi_crossbar_v2_1_15_splitter # // "SA": Splitter for Write Addr Arbiter
(
.C_NUM_M (2)
)
splitter_aw_mi
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_sa_awvalid),
.S_READY (aa_sa_awready),
.M_VALID ({mi_awvalid_en, sa_wm_awvalid_en}),
.M_READY ({mi_awready_mux, sa_wm_awready_mux})
);
assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};
assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);
assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler
assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;
assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};
assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);
assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};
assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);
assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler
assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;
// MI-slot # C_NUM_MASTER_SLOTS is the error handler
if (C_RANGE_CHECK) begin : gen_decerr_slave
axi_crossbar_v2_1_15_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_RESP (P_DECERR)
)
decerr_slave_inst
(
.S_AXI_ACLK (ACLK),
.S_AXI_ARESET (reset),
.S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),
.S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
.S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),
.S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
.S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
.S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
.S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),
.S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),
.S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
.S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
.S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
.S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
);
end else begin : gen_no_decerr_slave
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2] = 0;
assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
assign mi_bvalid[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2] = 0;
assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
assign mi_rlast[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_rvalid[C_NUM_MASTER_SLOTS] = 1'b0;
end // gen_decerr_slave
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11
)
(
input wire S_AXI_ACLK,
input wire S_AXI_ARESET,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [7:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i = 1'b0;
reg s_axi_wready_i = 1'b0;
reg s_axi_bvalid_i = 1'b0;
reg s_axi_arready_i = 1'b0;
reg s_axi_rvalid_i = 1'b0;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 1'b0;
localparam P_READ_DATA = 1'b1;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
end
end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
s_axi_wready_i <= 1'b1;
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
end
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [7:0] read_cnt;
reg [1:0] write_cs;
reg [0:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = s_axi_bid_i;
assign S_AXI_RID = s_axi_rid_i;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rvalid_i <= 1'b1;
if (S_AXI_ARLEN == 0) begin
s_axi_rlast_i <= 1'b1;
end else begin
s_axi_rlast_i <= 1'b0;
end
read_cs <= P_READ_DATA;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_15_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot = 0;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;
reg accept_cnt = 1'b0;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_13_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot = 0;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_13_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt = 0;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_15_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_13_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI Splitter
// Each transfer received on the AXI handshake slave port is replicated onto
// each of the master ports, and is completed back to the slave (S_READY)
// once all master ports have completed.
//
// M_VALID is asserted combinatorially from S_VALID assertion.
// Each M_VALID is masked off beginning the cycle after each M_READY is
// received (if S_READY remains low) until the cycle after both S_VALID
// and S_READY are asserted.
// S_READY is asserted combinatorially when the last (or all) of the M_READY
// inputs have been received.
// If all M_READYs are asserted when S_VALID is asserted, back-to-back
// handshakes can occur without bubble cycles.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// splitter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_splitter #
(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d = 0;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_13_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_13_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
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// -- systems, Class III medical devices, nuclear facilities,
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// -- (individually and collectively, "Critical
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// --
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// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_15_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl";
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_15_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_15_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_15_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_15_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_15_crossbar_sasd #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_15_crossbar #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
/*******************************************************************************
* *
* Copyright (C) 2009 Altera Corporation *
* *
* Altera products are protected under numerous U.S. and foreign patents, *
* maskwork rights, copyrights and other intellectual property laws. *
* *
* This reference design file, and your use thereof, is subject to and *
* governed by the terms and conditions of the applicable Altera Reference *
* Design License Agreement (either as signed by you, agreed by you upon *
* download or as a "click-through" agreement upon installation andor found *
* at www.altera.com). By using this reference design file, you indicate your *
* acceptance of such terms and conditions between you and Altera Corporation. *
* In the event that you do not agree with such terms and conditions, you may *
* not use the reference design file and please promptly destroy any copies *
* you have made. *
* *
* This reference design file is being provided on an "as-is" basis and as an *
* accommodation and therefore all warranties, representations or guarantees *
* of any kind (whether express, implied or statutory) including, without *
* limitation, warranties of merchantability, non-infringement, or fitness for *
* a particular purpose, are specifically disclaimed. By making this refer- *
* ence design file available, Altera expressly does not recommend, suggest *
* or require that this reference design file be used in combination with any *
* other product not provided by Altera. *
* *
* Module Name: erase_ram File Name: erase_ram.v *
* *
* Module Function: This module implements the SP RAM for storing keys the *
* basic CAM section. When storing a key location, the key *
* is written into the Erase RAM so that it can be erased *
* at a later time. *
* *
* Modules Used: *
* altsyncram Stratix IV Memory ATOM *
* *
* Parameters and Defines Used: *
* FAMILY Cyclone III/IV, or Stratix III/IV *
* S_KEY Section KEY *
* ENTRIES Total Entries in CAM *
* INDEX log 2 (ENTRIES) *
* CEIL_ENTRY 2**INDEX *
* *
* Created by: Jim Schwalbe Created on: 10/05/2009 *
* *
* REVISION HISTORY: *
* * Revision 1.0 10/05/2009 Jim Schwalbe *
* - Initial Revision *
* *
******************************************************************************/
module erase_ram (
address,
clock,
data,
wren,
q
);
// Target FPGA Family
parameter FAMILY = "Stratix IV";
// Section KEY
parameter S_KEY = 8; // Default (8)
// CAM ENTRIES
parameter ENTRIES = 416;
localparam INDEX = log2(ENTRIES); // Default (9)
localparam CEIL_ENTRY = 2**INDEX; // Default (512)
input [INDEX-1:0] address;
input clock;
input [S_KEY-1:0] data;
input wren;
output [S_KEY-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [S_KEY-1:0] sub_wire0;
wire [S_KEY-1:0] q = sub_wire0;
altsyncram altsyncram_component (
.wren_a ( wren ),
.clock0 ( clock ),
.address_a ( address ),
.data_a ( data ),
.q_a ( sub_wire0 ),
.aclr0 ( 1'b0 ),
.aclr1 ( 1'b0 ),
.address_b ( 1'b1 ),
.addressstall_a ( 1'b0 ),
.addressstall_b ( 1'b0 ),
.byteena_a ( 1'b1 ),
.byteena_b ( 1'b1 ),
.clock1 ( 1'b1 ),
.clocken0 ( 1'b1 ),
.clocken1 ( 1'b1 ),
.clocken2 ( 1'b1 ),
.clocken3 ( 1'b1 ),
.data_b ( 1'b1 ),
.eccstatus ( ),
.q_b ( ),
.rden_a ( 1'b1 ),
.rden_b ( 1'b1 ),
.wren_b ( 1'b0 )
);
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "erase_ram.rif"
`else
altsyncram_component.init_file = "erase_ram.hex"
`endif
,
altsyncram_component.intended_device_family = FAMILY,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = CEIL_ENTRY,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = INDEX,
altsyncram_component.width_a = S_KEY,
altsyncram_component.width_byteena_a = 1;
function integer log2;
input [32:0] bits;
integer k;
begin
log2 = 1;
for (k=0; 2**k < bits; k=k+1)
log2 = k + 1;
end
endfunction // log2
endmodule // erase_ram
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_8_V
`define SKY130_FD_SC_LP__MUX2_8_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_8 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_8 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// SA1 data (debug)
output [11:0] sa1_addr_out,
input [7:0] sa1_data,
// REG (generic)
// data inputs
input [7:0] sa1_config_data_in,
// data output
output [7:0] reg_group_out,
output [7:0] reg_index_out,
output [7:0] reg_value_out,
output [7:0] reg_invmask_out,
output reg_we_out,
output [7:0] reg_read_out,
// feature enable
output reg [15:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
//`define DEBUG
//`define MSU
initial begin
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [11:0] SA1_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [7:0] group_out_buf; initial group_out_buf = 8'hFF;
reg [7:0] index_out_buf; initial index_out_buf = 8'hFF;
reg [7:0] value_out_buf; initial value_out_buf = 8'hFF;
reg [7:0] invmask_out_buf; initial invmask_out_buf = 8'hFF;
reg [7:0] group_read_buf; initial group_read_buf = 8'hFF;
reg [7:0] index_read_buf; initial index_read_buf = 8'hFF;
reg [7:0] temp_read_buf; initial temp_read_buf = 8'hFF;
reg reg_we_buf; initial reg_we_buf = 0;
reg [55:0] rtc_data_out_buf;
reg rtc_pgm_we_buf;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg [7:0] dsp_feat_tmp;
reg [7:0] feat_tmp;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SA1_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
`ifdef MSU
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
`endif
8'hed:
case (spi_byte_cnt)
32'h2: feat_tmp <= param_data;
32'h3: featurebits_out <= {feat_tmp, param_data};
endcase
8'hee:
region_out <= param_data[0];
`ifdef DEBUG
8'hfa: // handles all group, index, value, invmask writes. unit is responsible for decoding group for match
case (spi_byte_cnt)
32'h2: begin
group_out_buf <= param_data;
end
32'h3: begin
index_out_buf <= param_data;
end
32'h4: begin
value_out_buf <= param_data;
end
32'h5: begin
invmask_out_buf <= param_data;
reg_we_buf <= 1;
end
32'h6: begin
reg_we_buf <= 0;
group_out_buf <= 8'hFF;
index_out_buf <= 8'hFF;
value_out_buf <= 8'hFF;
invmask_out_buf <= 8'hFF;
end
endcase
`endif
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
`ifdef MSU
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
`endif
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
`ifdef MSU
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
`endif
SA1_ADDR_OUT_BUF[11:8] <= param_data[3:0];
SA1_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3: begin
`ifdef MSU
MSU_ADDR_OUT_BUF[7:0] <= param_data;
`endif
SA1_ADDR_OUT_BUF[7:0] <= param_data;
end
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
// overload MSU read interface with SA1 buffer
end
else if ((cmd_ready | param_ready) && cmd_data == 8'hF5) begin
SA1_ADDR_OUT_BUF <= SA1_ADDR_OUT_BUF + 1;
end
else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
`ifdef MSU
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
`endif
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hF5)
MCU_DATA_IN_BUF <= sa1_data;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
`ifdef DEBUG
else if (cmd_data[7:0] == 8'hF9)
case (spi_byte_cnt)
32'h2: begin
group_read_buf <= param_data;
end
32'h3: begin
index_read_buf <= param_data;
end
32'h4: begin
if (group_read_buf == 8'h03) MCU_DATA_IN_BUF <= sa1_config_data_in;
else MCU_DATA_IN_BUF <= 0;
end
endcase
`endif
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign sa1_addr_out = SA1_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
//assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
//assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
//assign bsx_regs_set_out = bsx_regs_set_out_buf;
//
//assign rtc_data_out = rtc_data_out_buf;
//assign rtc_pgm_we = rtc_pgm_we_buf;
//
//assign srtc_reset = srtc_reset_buf;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign reg_group_out = group_out_buf;
assign reg_index_out = index_out_buf;
assign reg_value_out = value_out_buf;
assign reg_invmask_out = invmask_out_buf;
assign reg_we_out = reg_we_buf;
assign reg_read_out = index_read_buf;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_ar_channel.v
//
// Description:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_mc_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of AXI xDATA and MC xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// DRAM clock to AXI clock ratio
// supported values 2, 4
parameter integer C_MC_nCK_PER_CLK = 2,
// Static value of axsize
// Range: 2-4
parameter integer C_AXSIZE = 2
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] araddr ,
input wire [7:0] arlen ,
input wire [2:0] arsize ,
input wire [1:0] arburst ,
input wire [1:0] arlock ,
input wire [3:0] arcache ,
input wire [2:0] arprot ,
input wire [3:0] arqos ,
input wire arvalid ,
output wire arready ,
// MC Master Interface
//CMD PORT
output wire cmd_en ,
output wire cmd_en_last ,
output wire [2:0] cmd_instr ,
output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr ,
input wire cmd_full ,
// Connections to/from axi_mc_r_channel module
input wire r_data_rdy ,
output reg r_push ,
output wire[C_ID_WIDTH-1:0] r_arid ,
output reg r_rlast ,
output wire r_ignore_begin ,
output wire r_ignore_end ,
output wire arvalid_int ,
output wire [3:0] arqos_int
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_CMD_WRITE = 3'b000;
localparam P_CMD_READ = 3'b001;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
reg [C_ID_WIDTH-1:0] axid ;
reg [C_AXI_ADDR_WIDTH-1:0] axaddr ;
reg [7:0] axlen ;
reg [3:0] axqos ;
reg [1:0] axburst ;
reg axvalid ;
wire [C_ID_WIDTH-1:0] axid_int ;
wire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ;
wire [7:0] axlen_int ;
wire [3:0] axqos_int ;
wire [1:0] axburst_int ;
wire axvalid_int ;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign arvalid_int = axvalid_int;
assign arqos_int = axqos_int;
assign axid_int = arready ? arid : axid;
assign axlen_int = arready ? arlen : axlen;
assign axqos_int = arready ? arqos : axqos;
assign axaddr_int = arready ? araddr : axaddr;
assign axburst_int = arready ? arburst : axburst;
assign axvalid_int = arready ? arvalid : axvalid;
always @(posedge clk) begin
if(reset)
axvalid <= 1'b0;
else
axvalid <= axvalid_int;
end
always @(posedge clk) begin
axid <= axid_int;
axlen <= axlen_int;
axqos <= axqos_int;
axaddr <= axaddr_int;
axburst <= axburst_int;
end
// Translate the AXI transaction to the MC transaction(s)
mig_7series_v4_0_axi_mc_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,
.C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) ,
.C_AXSIZE ( C_AXSIZE ) ,
.C_MC_RD_INST ( 1 )
)
axi_mc_cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr_int ) ,
.axlen ( axlen_int ) ,
.axsize ( arsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations.
.axburst ( axburst_int ) ,
.axvalid ( axvalid_int ) ,
.axready ( arready ) ,
.cmd_byte_addr ( cmd_byte_addr ) ,
.ignore_begin ( r_ignore_begin ) ,
.ignore_end ( r_ignore_end ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
mig_7series_v4_0_axi_mc_cmd_fsm #
(
.C_MC_BURST_LEN (C_MC_BURST_LEN ),
.C_MC_RD_INST (1 )
)
ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axready ( arready ) ,
.axvalid ( axvalid_int ) ,
.cmd_en ( cmd_en ) ,
.cmd_full ( cmd_full ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_rdy ( r_data_rdy ) ,
.cmd_en_last ( cmd_en_last )
);
assign cmd_instr = P_CMD_READ;
// these signals can be moved out of this block to the top level.
assign r_arid = axid;
always @(posedge clk) begin
r_push <= next;
r_rlast <= ~next_pending;
end
endmodule
`default_nettype wire
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_pcie.vh"
module pcie_tx_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] pcie_dev_id,
input tx_cpld_gnt,
input tx_mrd_gnt,
input tx_mwr_gnt,
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_arb_valid,
output [5:0] tx_arb_gnt,
output [2:0] tx_arb_type,
output [11:2] tx_pcie_len,
output [127:0] tx_pcie_head,
output [31:0] tx_cpld_udata,
input tx_arb_rdy
);
reg [5:0] r_tx_req;
reg [5:0] r_tx_req_en;
wire [5:0] w_tx_req_en;
wire [5:0] w_tx_req_gnt;
reg [5:0] r_tx_req_ack;
wire [5:0] w_tx_req_ack;
reg [2:0] r_tx_type;
reg [5:0] r_tx_arb;
reg [5:0] r_tx_arb_cur;
reg [2:0] r_tx_arb_type;
reg [31:0] r_tx_pcie_head0;
reg [31:0] r_tx_pcie_head1;
reg [31:0] r_tx_pcie_head2;
reg [31:0] r_tx_pcie_head3;
assign tx_arb_valid = (r_tx_arb_cur[5] | r_tx_arb_cur[4]) | (r_tx_arb_cur[3] | r_tx_arb_cur[2]) | (r_tx_arb_cur[1] | r_tx_arb_cur[0]);
assign tx_arb_gnt = r_tx_arb_cur;
assign tx_arb_type = r_tx_arb_type;
assign tx_pcie_len = r_tx_pcie_head0[9:0];
assign tx_pcie_head = {r_tx_pcie_head3, r_tx_pcie_head2, r_tx_pcie_head1, r_tx_pcie_head0};
assign tx_cpld_udata = tx_cpld_data[63:32];
assign tx_cpld_req_ack = r_tx_req_ack[0];
assign tx_mrd0_req_ack = r_tx_req_ack[1];
assign tx_mrd1_req_ack = r_tx_req_ack[2];
assign tx_mrd2_req_ack = r_tx_req_ack[3];
assign tx_mwr0_req_ack = r_tx_req_ack[4];
assign tx_mwr1_req_ack = r_tx_req_ack[5];
assign w_tx_req_ack[0] = tx_arb_rdy & r_tx_arb_cur[0];
assign w_tx_req_ack[1] = tx_arb_rdy & r_tx_arb_cur[1];
assign w_tx_req_ack[2] = tx_arb_rdy & r_tx_arb_cur[2];
assign w_tx_req_ack[3] = tx_arb_rdy & r_tx_arb_cur[3];
assign w_tx_req_ack[4] = tx_arb_rdy & r_tx_arb_cur[4];
assign w_tx_req_ack[5] = tx_arb_rdy & r_tx_arb_cur[5];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_req <= 0;
end
else begin
if(tx_cpld_req == 1)
r_tx_req[0] <= 1;
else if(w_tx_req_ack[0] == 1)
r_tx_req[0] <= 0;
if(tx_mrd0_req == 1)
r_tx_req[1] <= 1;
else if(w_tx_req_ack[1] == 1)
r_tx_req[1] <= 0;
if(tx_mrd1_req == 1)
r_tx_req[2] <= 1;
else if(w_tx_req_ack[2] == 1)
r_tx_req[2] <= 0;
if(tx_mrd2_req == 1)
r_tx_req[3] <= 1;
else if(w_tx_req_ack[3] == 1)
r_tx_req[3] <= 0;
if(tx_mwr0_req == 1)
r_tx_req[4] <= 1;
else if(w_tx_req_ack[4] == 1)
r_tx_req[4] <= 0;
if(tx_mwr1_req == 1)
r_tx_req[5] <= 1;
else if(w_tx_req_ack[5] == 1)
r_tx_req[5] <= 0;
end
end
always @ (*)
begin
if(tx_arb_rdy == 1)
r_tx_req_en <= r_tx_req & ~r_tx_arb_cur;
else
r_tx_req_en <= r_tx_req;
end
assign w_tx_req_gnt[0] = tx_cpld_gnt;
assign w_tx_req_gnt[1] = tx_mrd_gnt;
assign w_tx_req_gnt[2] = tx_mrd_gnt;
assign w_tx_req_gnt[3] = tx_mrd_gnt;
assign w_tx_req_gnt[4] = tx_mwr_gnt;
assign w_tx_req_gnt[5] = tx_mwr_gnt;
assign w_tx_req_en = r_tx_req_en & w_tx_req_gnt;
always @ (*)
begin
if(w_tx_req_en[0] == 1) begin
r_tx_type <= 3'b001;
r_tx_arb <= 6'b000001;
end
else if(w_tx_req_en[1] == 1) begin
r_tx_type <= 3'b010;
r_tx_arb <= 6'b000010;
end
else if(w_tx_req_en[2] == 1) begin
r_tx_type <= 3'b010;
r_tx_arb <= 6'b000100;
end
else if(w_tx_req_en[4] == 1) begin
r_tx_type <= 3'b100;
r_tx_arb <= 6'b010000;
end
else if(w_tx_req_en[3] == 1) begin
r_tx_type <= 3'b010;
r_tx_arb <= 6'b001000;
end
else if(w_tx_req_en[5] == 1) begin
r_tx_type <= 3'b100;
r_tx_arb <= 6'b100000;
end
else begin
r_tx_type <= 3'b000;
r_tx_arb <= 6'b000000;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
r_tx_arb_cur <= 0;
else
r_tx_arb_cur <= r_tx_arb;
end
always @ (posedge pcie_user_clk)
begin
r_tx_arb_type <= r_tx_type;
r_tx_req_ack <= w_tx_req_ack;
end
always @ (*)
begin
case(r_tx_arb_cur) // synthesis parallel_case full_case
6'b000001: begin
r_tx_pcie_head0 <= {`D_CPLD_FMT, `D_CPLD_TYPE, 1'b0, `D_CPLD_TC, 1'b0, `D_CPLD_ATTR1, 1'b0, `D_CPLD_TH, `D_CPLD_TD, `D_CPLD_EP, `D_CPLD_ATTR2, `D_CPLD_AT, tx_cpld_len};
r_tx_pcie_head1 <= {pcie_dev_id, `D_CPLD_CS, `D_CPLD_BCM, tx_cpld_bc};
r_tx_pcie_head2 <= {tx_cpld_req_id, tx_cpld_tag, 1'b0, tx_cpld_laddr};
r_tx_pcie_head3 <= tx_cpld_data[31:0];
end
6'b000010: begin
r_tx_pcie_head0 <= {`D_MRD_FMT, `D_MRD_TYPE, 1'b0, `D_MRD_TC, 1'b0, `D_MRD_ATTR1, 1'b0, `D_MRD_TH, `D_MRD_TD, `D_MRD_EP, `D_MRD_ATTR2, `D_MRD_AT, tx_mrd0_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mrd0_tag, `D_MRD_LAST_BE, `D_MRD_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mrd0_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mrd0_addr[31:2], 2'b0};
end
6'b000100: begin
r_tx_pcie_head0 <= {`D_MRD_FMT, `D_MRD_TYPE, 1'b0, `D_MRD_TC, 1'b0, `D_MRD_ATTR1, 1'b0, `D_MRD_TH, `D_MRD_TD, `D_MRD_EP, `D_MRD_ATTR2, `D_MRD_AT, tx_mrd1_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mrd1_tag, `D_MRD_LAST_BE, `D_MRD_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mrd1_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mrd1_addr[31:2], 2'b0};
end
6'b001000: begin
r_tx_pcie_head0 <= {`D_MRD_FMT, `D_MRD_TYPE, 1'b0, `D_MRD_TC, 1'b0, `D_MRD_ATTR1, 1'b0, `D_MRD_TH, `D_MRD_TD, `D_MRD_EP, `D_MRD_ATTR2, `D_MRD_AT, tx_mrd2_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mrd2_tag, `D_MRD_LAST_BE, `D_MRD_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mrd2_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mrd2_addr[31:2], 2'b0};
end
6'b010000: begin
r_tx_pcie_head0 <= {`D_MWR_FMT, `D_MWR_TYPE, 1'b0, `D_MWR_TC, 1'b0, `D_MWR_ATTR1, 1'b0, `D_MWR_TH, `D_MWR_TD, `D_MWR_EP, `D_MWR_ATTR2, `D_MWR_AT, tx_mwr0_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mwr0_tag, `D_MWR_LAST_BE, `D_MWR_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mwr0_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mwr0_addr[31:2], 2'b0};
end
6'b100000: begin
r_tx_pcie_head0 <= {`D_MWR_FMT, `D_MWR_TYPE, 1'b0, `D_MWR_TC, 1'b0, `D_MWR_ATTR1, 1'b0, `D_MWR_TH, `D_MWR_TD, `D_MWR_EP, `D_MWR_ATTR2, `D_MWR_AT, tx_mwr1_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mwr1_tag, `D_MWR_LAST_BE, `D_MWR_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mwr1_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mwr1_addr[31:2], 2'b0};
end
endcase
end
endmodule |
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
/*
*******************************************************************************
* File Name : ada_bram.v
* Project : ADA processor
* Version : 0.1
* Date : Sept 1st, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright (c) 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Block RAM used for the Internal Memory
*******************************************************************************
*/
module ada_bram #(
parameter DATA = 32,
parameter ADDR = 8
)(
// Port A
input a_clk,
input a_wr,
input [ADDR-1:0] a_addr,
input [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input b_clk,
input b_wr,
input [ADDR-1:0] b_addr,
input [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
//--------------------------------------------------------------------------
// Shared memory
//--------------------------------------------------------------------------
reg [DATA-1:0] mem [(2**ADDR)-1:0];
// initiate the memory to zeros. For testing.
// TODO: Add interface to modify this memory using a debug interface
integer i;
initial begin
for (i=0; i < 256; i=i+1)
mem[i] = 32'b0;
end
//--------------------------------------------------------------------------
// Port A
//--------------------------------------------------------------------------
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
//--------------------------------------------------------------------------
// Port B
//--------------------------------------------------------------------------
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Decoder for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Decoder
// Module Name: Decoder
// File Name: Decoder.v
//
// Version: v1.0.0
//
// Description: General purpose decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module Decoder
#
(
parameter OutputWidth = 4
)
(
I,
O
);
input [$clog2(OutputWidth) - 1:0] I;
output [OutputWidth - 1:0] O;
reg [OutputWidth - 1:0] rO;
genvar c;
generate
for (c = 0; c < OutputWidth; c = c + 1)
begin: DecodeBits
always @ (*)
begin
if (I == c)
rO[c] <= 1'b1;
else
rO[c] <= 1'b0;
end
end
endgenerate
assign O = rO;
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2021 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module testbench(
/*AUTOARG*/
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
logic third_clk; // Additional dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
other_clk = val;
endfunction;
export "DPI-C" function set_third_clk;
function void set_third_clk(bit val);
third_clk = val;
endfunction;
bit even_other = 1;
import "DPI-C" context function void toggle_other_clk(bit val);
always @(posedge clk) begin
even_other <= ~even_other;
toggle_other_clk(even_other);
end
bit even_third = 1;
import "DPI-C" context function void toggle_third_clk(bit val);
always @(posedge other_clk) begin
even_third <= ~even_third;
toggle_third_clk(even_third);
end
int n = 0;
always @(posedge third_clk) begin
$display("t=%d n=%d", $time, n);
if ($time != (8*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");
$finish;
end
n += 1;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.28 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.27 2001/12/30 20:39:13 mohor
// More than one character was stored in case of break. End of the break
// was not detected correctly.
//
// Revision 1.26 2001/12/20 13:28:27 mohor
// Missing declaration of rf_push_q fixed.
//
// Revision 1.25 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.24 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.23 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.22 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.21 2001/12/13 10:31:16 mohor
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
// timeout counter).
//
// Revision 1.20 2001/12/10 19:52:05 gorban
// Igor fixed break condition bugs
//
// Revision 1.19 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.18 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.16 2001/11/27 22:17:09 gorban
// Fixed bug that prevented synthesis in uart_receiver.v
//
// Revision 1.15 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.14 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift; // receiver shift register
reg rparity; // received parity
reg rparity_error;
reg rframing_error; // framing error flag
reg rbit_in;
reg rparity_xor;
reg [7:0] counter_b; // counts the 0 (low) signals
reg rf_push_q;
// RX FIFO signals
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire break_error = (counter_b == 0);
// RX FIFO instance
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( rf_data_in ),
.data_out( rf_data_out ),
.push( rf_push_pulse ),
.pop( rf_pop ),
.overrun( rf_overrun ),
.count( rf_count ),
.error_bit( rf_error_bit ),
.fifo_reset( rx_reset ),
.reset_status(lsr_mask)
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
rstate <= #1 sr_idle;
rbit_in <= #1 1'b0;
rcounter16 <= #1 0;
rbit_counter <= #1 0;
rparity_xor <= #1 1'b0;
rframing_error <= #1 1'b0;
rparity_error <= #1 1'b0;
rparity <= #1 1'b0;
rshift <= #1 0;
rf_push <= #1 1'b0;
rf_data_in <= #1 0;
end
else
if (enable)
begin
case (rstate)
sr_idle : begin
rf_push <= #1 1'b0;
rf_data_in <= #1 0;
rcounter16 <= #1 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
begin
rstate <= #1 sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= #1 1'b0;
if (rcounter16_eq_7) // check the pulse
if (srx_pad_i==1'b1) // no start bit
rstate <= #1 sr_idle;
else // start bit detected
rstate <= #1 sr_rec_prepare;
rcounter16 <= #1 rcounter16_minus_1;
end
sr_rec_prepare:begin
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rbit_counter <= #1 3'b100;
2'b01 : rbit_counter <= #1 3'b101;
2'b10 : rbit_counter <= #1 3'b110;
2'b11 : rbit_counter <= #1 3'b111;
endcase
if (rcounter16_eq_0)
begin
rstate <= #1 sr_rec_bit;
rcounter16 <= #1 4'b1110;
rshift <= #1 0;
end
else
rstate <= #1 sr_rec_prepare;
rcounter16 <= #1 rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0)
rstate <= #1 sr_end_bit;
if (rcounter16_eq_7) // read the bit
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= #1 rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0) // no more bits in word
if (lcr[`UART_LC_PE]) // choose state based on parity
rstate <= #1 sr_rec_parity;
else
begin
rstate <= #1 sr_rec_stop;
rparity_error <= #1 1'b0; // no parity - no error :)
end
else // else we have more bits to read
begin
rstate <= #1 sr_rec_bit;
rbit_counter <= #1 rbit_counter - 1'b1;
end
rcounter16 <= #1 4'b1110;
end
sr_rec_parity: begin
if (rcounter16_eq_7) // read the parity
begin
rparity <= #1 srx_pad_i;
rstate <= #1 sr_ca_lc_parity;
end
rcounter16 <= #1 rcounter16_minus_1;
end
sr_ca_lc_parity : begin // rcounter equals 6
rcounter16 <= #1 rcounter16_minus_1;
rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
rstate <= #1 sr_check_parity;
end
sr_check_parity: begin // rcounter equals 5
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1
2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1
2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd
2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0
endcase
rcounter16 <= #1 rcounter16_minus_1;
rstate <= #1 sr_wait1;
end
sr_wait1 : if (rcounter16_eq_0)
begin
rstate <= #1 sr_rec_stop;
rcounter16 <= #1 4'b1110;
end
else
rcounter16 <= #1 rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) // read the parity
begin
rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit)
rstate <= #1 sr_push;
end
rcounter16 <= #1 rcounter16_minus_1;
end
sr_push : begin
///////////////////////////////////////
// $display($time, ": received: %b", rf_data_in);
if(srx_pad_i | break_error)
begin
if(break_error)
rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
else
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= #1 1'b1;
rstate <= #1 sr_idle;
end
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
begin
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= #1 1'b1;
rcounter16 <= #1 4'b1110;
rstate <= #1 sr_rec_start;
end
end
default : rstate <= #1 sr_idle;
endcase
end // if (enable)
end // always of receiver
always @ (posedge clk or posedge wb_rst_i)
begin
if(wb_rst_i)
rf_push_q <= 0;
else
rf_push_q <= #1 rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
//
// Break condition detection.
// Works in conjuction with the receiver state machine
reg [9:0] toc_value; // value to be set to timeout counter
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447; // 7 bits
4'b0100 : toc_value = 479; // 7.5 bits
4'b0001, 4'b1000 : toc_value = 511; // 8 bits
4'b1100 : toc_value = 543; // 8.5 bits
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
4'b1111 : toc_value = 767; // 12 bits
endcase // case(lcr[3:0])
wire [7:0] brc_value; // value to be set to break counter
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_b <= #1 8'd159;
else
if (srx_pad_i)
counter_b <= #1 brc_value; // character time length - 1
else
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
counter_b <= #1 counter_b - 1; // decrement break counter
end // always of break condition detection
///
/// Timeout condition detection
reg [9:0] counter_t; // counts the timeout condition clocks
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_t <= #1 10'd639; // 10 bits for the default 8N1
else
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
counter_t <= #1 toc_value;
else
if (enable && counter_t != 10'b0) // we don't want to underflow
counter_t <= #1 counter_t - 1;
end
endmodule
|
module test_mem_dev #(
parameter READ_FIFO_SIZE = 8,
parameter WRITE_FIFO_SIZE = 8,
parameter ADDRESS_WIDTH = 8,
parameter ENABLE_ERROR_CHECK = 1,
parameter INITIALIZE_MEM = 1
)(
input clk,
input rst,
//BRAM Style Interface
input bram_en,
input bram_we,
input [(ADDRESS_WIDTH - 1):0] bram_address,
input [31:0] bram_data_in,
output [31:0] bram_data_out,
output initializing,
//Write Side
input write_enable,
input [63:0] write_addr,
input write_addr_inc,
input write_addr_dec,
output write_finished,
input [23:0] write_count,
input write_flush,
output [1:0] write_ready,
input [1:0] write_activate,
output [23:0] write_size,
input write_strobe,
input [31:0] write_data,
//Read Side
input read_enable,
input [63:0] read_addr,
input read_addr_inc,
input read_addr_dec,
output read_busy,
output read_error,
input [23:0] read_count,
input read_flush,
output read_ready,
input read_activate,
output [23:0] read_size,
output [31:0] read_data,
input read_strobe
);
//Local Parameters
//Registers/Wires
reg [ADDRESS_WIDTH - 1:0] mem_addr_in;
reg [ADDRESS_WIDTH - 1:0] mem_addr_out;
reg [23:0] mem_write_count;
wire mem_write_overflow;
reg [23:0] local_read_size;
reg [23:0] mem_read_count;
reg mem_read_strobe;
reg mem_write_strobe;
reg prev_write_enable;
wire posedge_write_enable;
reg prev_read_enable;
wire posedge_read_enable;
reg [31:0] prev_f2m_data;
reg f2m_data_error;
reg [31:0] prev_m2f_data;
reg m2f_data_error;
reg f2m_strobe;
wire f2m_ready;
reg f2m_activate;
wire [23:0] f2m_size;
wire [31:0] f2m_data;
reg [23:0] f2m_count;
wire [1:0] m2f_ready;
reg [1:0] m2f_activate;
wire [23:0] m2f_size;
reg m2f_strobe;
wire [31:0] m2f_data;
reg [23:0] m2f_count;
reg first_write;
wire [31:0] din;
wire wea;
reg fill_mem;
reg [31:0] fill_mem_data;
reg fill_mem_wea;
wire write_fifo_empty;
wire blk_mem_we;
wire blk_mem_en;
wire [(ADDRESS_WIDTH - 1):0] blk_mem_wr_addr;
wire [(ADDRESS_WIDTH - 1):0] blk_mem_rd_addr;
wire [31:0] blk_mem_data_in;
wire enable_error_check;
//Submodules
blk_mem #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (ADDRESS_WIDTH )
) mem (
.clka (clk ),
.wea (blk_mem_we ),
.dina (blk_mem_data_in),
.addra (blk_mem_wr_addr),
.clkb (clk ),
.doutb (m2f_data ),
.addrb (blk_mem_rd_addr)
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (WRITE_FIFO_SIZE)
)fifo_to_mem (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (write_ready ),
.write_activate (write_activate ),
.write_fifo_size (write_size ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.starved (write_fifo_empty),
//Read
.read_clock (clk ),
.read_strobe (f2m_strobe ),
.read_ready (f2m_ready ),
.read_activate (f2m_activate ),
.read_count (f2m_size ),
.read_data (f2m_data )
//.inactive ( )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (READ_FIFO_SIZE )
)mem_to_fifo (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (m2f_ready ),
.write_activate (m2f_activate ),
.write_fifo_size (m2f_size ),
.write_strobe (m2f_strobe ),
.write_data (m2f_data ),
//.starved ( ),
//Read
.read_clock (clk ),
.read_strobe (read_strobe ),
.read_ready (read_ready ),
.read_activate (read_activate ),
.read_count (read_size ),
.read_data (read_data )
//.inactive ( )
);
//Asynchronous Logic
assign posedge_write_enable = !prev_write_enable && write_enable;
assign posedge_read_enable = !prev_read_enable && read_enable;
assign mem_write_overflow = ((write_count > 0) && (mem_write_count > write_count));
assign write_finished = ((write_count > 0) && (mem_write_count >= write_count) && write_fifo_empty);
assign mem_read_overflow = ((local_read_size > 0) && (mem_read_count > local_read_size));
assign read_finished = ((local_read_size > 0) && (mem_read_count >= local_read_size));
assign din = fill_mem ? fill_mem_data: f2m_data;
assign wea = fill_mem ? fill_mem_wea: f2m_strobe;
assign read_error = m2f_data_error;
assign blk_mem_we = bram_en ? bram_we : wea;
assign blk_mem_wr_addr = bram_en ? bram_address : mem_addr_in;
assign blk_mem_rd_addr = bram_en ? bram_address : mem_addr_out;
assign blk_mem_data_in = bram_en ? bram_data_in : din;
assign bram_data_out = m2f_data;
assign initializing = fill_mem_wea;
assign enable_error_check = ENABLE_ERROR_CHECK;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
mem_addr_in <= 0;
mem_addr_out <= 0;
f2m_strobe <= 0;
f2m_activate <= 0;
f2m_count <= 0;
m2f_activate <= 0;
m2f_strobe <= 0;
m2f_count <= 0;
prev_write_enable <= 0;
prev_read_enable <= 0;
local_read_size <= 0;
mem_write_count <= 0;
mem_read_count <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
m2f_data_error <= 0;
prev_f2m_data <= 0;
first_write <= 0;
fill_mem <= INITIALIZE_MEM;
fill_mem_data <= 0;
fill_mem_wea <= INITIALIZE_MEM;
prev_m2f_data <= 0;
end
//Fill Memory Device
else if (fill_mem) begin
fill_mem_wea <= 1;
if (mem_addr_in < (2 ** ADDRESS_WIDTH - 1)) begin
fill_mem_data <= mem_addr_in + 1;
mem_addr_in <= mem_addr_in + 1;
end
else begin
fill_mem <= 0;
fill_mem_wea <= 0;
end
end
else begin
//Strobes
f2m_strobe <= 0;
m2f_strobe <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
first_write <= 0;
m2f_data_error <= 0;
//Errors (Incomming)
if ((f2m_count > 0) && mem_write_strobe && !write_flush) begin
if ((prev_f2m_data == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
//if ((mem_addr_in == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
f2m_data_error <= 1;
if (enable_error_check) begin
$display ("Write: Wrap Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
else if ((prev_f2m_data + 1) != f2m_data) begin
if (first_write) begin
if (prev_f2m_data != f2m_data) begin
f2m_data_error <= 1;
if (enable_error_check) begin
$display ("Write: First Write Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
end
else begin
f2m_data_error <= 1;
if (enable_error_check) begin
$display ("Write: Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
end
end
//Error (Outgoing)
//if ((m2f_count > 0) && mem_read_strobe && !read_flush) begin
if ((m2f_count > 0) && m2f_strobe && !read_flush && ((m2f_activate & m2f_ready) == 0)) begin
if (((prev_m2f_data + 1)== (2 ** ADDRESS_WIDTH)) && (m2f_data != 0))begin
m2f_data_error <= 1;
if (enable_error_check) begin
$display ("Read: Wrap Error @ 0x%h should be 0", prev_m2f_data);
end
end
else if ((prev_m2f_data + 1) != m2f_data) begin
m2f_data_error <= 1;
if (enable_error_check) begin
$display ("Read: Error @ 0x%h: 0x%h != 0x%h", mem_addr_out, m2f_data, (prev_m2f_data + 1));
end
end
end
//Store Memory Address
if (posedge_write_enable) begin
mem_addr_in <= write_addr[ADDRESS_WIDTH - 1: 0];
mem_write_count <= 0;
end
if (posedge_read_enable) begin
mem_addr_out <= read_addr[ADDRESS_WIDTH - 1: 0];
local_read_size <= read_count;
mem_read_count <= 0;
end
if (!read_enable) begin
local_read_size <= 0;
end
//If available get a peice of the FIFO that I can write data to the memory
if (!f2m_activate && f2m_ready) begin
f2m_activate <= 1;
f2m_count <= 0;
end
//If there is an available FIFO to write to grab it
if ((m2f_activate == 0) && (m2f_ready > 0)) begin
m2f_count <= 0;
if (m2f_ready[0]) begin
m2f_activate[0] <= 1;
end
else begin
m2f_activate[1] <= 1;
end
end
if (mem_read_strobe) begin
if (read_addr_inc) begin
mem_addr_out <= mem_addr_out + 1;
end
else if (read_addr_dec) begin
mem_addr_out <= mem_addr_out - 1;
end
m2f_strobe <= 1;
end
if (!m2f_strobe &&
!mem_read_strobe && (m2f_activate > 0) &&
((m2f_count >= m2f_size) ||
(mem_read_count > 0 &&
mem_read_count >= local_read_size))) begin
m2f_activate <= 0;
end
if (mem_write_strobe) begin
mem_write_count <= mem_write_count + 1;
if (write_addr_inc) begin
mem_addr_in <= mem_addr_in + 1;
end
else if (write_addr_dec) begin
mem_addr_in <= mem_addr_in - 1;
end
end
//if (write_enable) begin
if (f2m_count < f2m_size) begin
if (f2m_activate) begin
f2m_strobe <= 1;
mem_write_strobe <= 1;
f2m_count <= f2m_count + 1;
if (f2m_count == 0) begin
first_write <= 1;
end
end
end
else begin
f2m_activate <= 0;
end
//end
if (mem_read_count < local_read_size) begin
if (read_enable) begin
if ((m2f_activate > 0) && (m2f_count < m2f_size)) begin
m2f_count <= m2f_count + 1;
mem_read_strobe <= 1;
mem_read_count <= mem_read_count + 1;
end
end
end
if (m2f_strobe) begin
prev_m2f_data <= m2f_data;
end
prev_f2m_data <= f2m_data;
prev_write_enable <= write_enable;
prev_read_enable <= read_enable;
end
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that the code generator properly handles
* ocncatenation expressions as parameters to system tasks.
*/
module main;
reg [3:0] a, b;
initial begin
a = 0;
b = 0;
for (a = 0 ; a < 4'd15 ; a = a + 1)
for (b = 0 ; b < 4'd15 ; b = b + 1)
$display("{a, b} == %b", {a, b});
end
endmodule // main
|
//wishbone_arbiter.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module arbiter_2_masters (
//control signals
input clk,
input rst,
//wishbone master ports
input i_m0_we,
input i_m0_cyc,
input i_m0_stb,
input [3:0] i_m0_sel,
output o_m0_ack,
input [31:0] i_m0_dat,
output [31:0] o_m0_dat,
input [31:0] i_m0_adr,
output o_m0_int,
input i_m1_we,
input i_m1_cyc,
input i_m1_stb,
input [3:0] i_m1_sel,
output o_m1_ack,
input [31:0] i_m1_dat,
output [31:0] o_m1_dat,
input [31:0] i_m1_adr,
output o_m1_int,
//wishbone slave signals
output o_s_we,
output o_s_stb,
output o_s_cyc,
output [3:0] o_s_sel,
output [31:0] o_s_adr,
output [31:0] o_s_dat,
input [31:0] i_s_dat,
input i_s_ack,
input i_s_int
);
localparam MASTER_COUNT = 2;
//registers/wires
//this should be parameterized
reg [7:0] master_select;
reg [7:0] priority_select;
wire o_master_we [MASTER_COUNT - 1:0];
wire o_master_stb [MASTER_COUNT - 1:0];
wire o_master_cyc [MASTER_COUNT - 1:0];
wire [3:0] o_master_sel [MASTER_COUNT - 1:0];
wire [31:0] o_master_adr [MASTER_COUNT - 1:0];
wire [31:0] o_master_dat [MASTER_COUNT - 1:0];
//master select block
localparam MASTER_NO_SEL = 8'hFF;
localparam MASTER_0 = 0;
localparam MASTER_1 = 1;
always @ (posedge clk) begin
if (rst) begin
master_select <= MASTER_NO_SEL;
end
else begin
case (master_select)
MASTER_0: begin
if (~i_m0_cyc && ~i_s_ack) begin
master_select <= MASTER_NO_SEL;
end
end
MASTER_1: begin
if (~i_m1_cyc && ~i_s_ack) begin
master_select <= MASTER_NO_SEL;
end
end
default: begin
//nothing selected
if (i_m0_cyc) begin
master_select <= MASTER_0;
end
else if (i_m1_cyc) begin
master_select <= MASTER_1;
end
end
endcase
if ((master_select != MASTER_NO_SEL) && (priority_select < master_select) && (!o_s_stb && !i_s_ack))begin
master_select <= MASTER_NO_SEL;
end
end
end
//priority select
always @ (posedge clk) begin
if (rst) begin
priority_select <= MASTER_NO_SEL;
end
else begin
//find the highest priority
if (i_m0_cyc) begin
priority_select <= MASTER_0;
end
else if (i_m1_cyc) begin
priority_select <= MASTER_1;
end
else begin
priority_select <= MASTER_NO_SEL;
end
end
end
//slave assignments
assign o_s_we = (master_select != MASTER_NO_SEL) ? o_master_we[master_select] : 0;
assign o_s_stb = (master_select != MASTER_NO_SEL) ? o_master_stb[master_select] : 0;
assign o_s_cyc = (master_select != MASTER_NO_SEL) ? o_master_cyc[master_select] : 0;
assign o_s_sel = (master_select != MASTER_NO_SEL) ? o_master_sel[master_select] : 0;
assign o_s_adr = (master_select != MASTER_NO_SEL) ? o_master_adr[master_select] : 0;
assign o_s_dat = (master_select != MASTER_NO_SEL) ? o_master_dat[master_select] : 0;
//write select block
assign o_master_we[MASTER_0] = i_m0_we;
assign o_master_we[MASTER_1] = i_m1_we;
//strobe select block
assign o_master_stb[MASTER_0] = i_m0_stb;
assign o_master_stb[MASTER_1] = i_m1_stb;
//cycle select block
assign o_master_cyc[MASTER_0] = i_m0_cyc;
assign o_master_cyc[MASTER_1] = i_m1_cyc;
//select select block
assign o_master_sel[MASTER_0] = i_m0_sel;
assign o_master_sel[MASTER_1] = i_m1_sel;
//address seelct block
assign o_master_adr[MASTER_0] = i_m0_adr;
assign o_master_adr[MASTER_1] = i_m1_adr;
//data select block
assign o_master_dat[MASTER_0] = i_m0_dat;
assign o_master_dat[MASTER_1] = i_m1_dat;
//assign block
assign o_m0_ack = (master_select == MASTER_0) ? i_s_ack : 0;
assign o_m0_dat = i_s_dat;
assign o_m0_int = (master_select == MASTER_0) ? i_s_int : 0;
assign o_m1_ack = (master_select == MASTER_1) ? i_s_ack : 0;
assign o_m1_dat = i_s_dat;
assign o_m1_int = (master_select == MASTER_1) ? i_s_int : 0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// issue2895
module t (/*AUTOARG*/);
localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0",
"t1", "t2", "s0/fp", "s1", "a0", "a1",
"a2", "a3", "a4", "a5", "a6", "a7", "s2",
"s3", "s4", "s5", "s6", "s7", "s8", "s9",
"s10", "s11", "t3", "t4", "t5", "t6"};
function string reg_x (logic [4:0] r, bit abi=1'b0);
reg_x = abi ? REG_X[r] : $sformatf("x%0d", r);
endfunction
// the issue is triggered by a second function containing a case statement
function string f2 (logic [4:0] r, bit abi=0);
case (r)
5'd0: f2 = $sformatf("nop");
5'd1: f2 = $sformatf("reg %s", reg_x(r[4:0], abi));
default: f2 = $sformatf("ILLEGAL");
endcase
endfunction
initial begin
for (int unsigned i = 0; i < 32; ++i) begin
$display("REGX: %s", reg_x(i[4:0], 1'b1));
end
$display("OP: %s", f2(5'd7));
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
//
// This module implements a 16 bit SPI slave.
// The main module name is spi.
//
// A parallel output shift register clocked on rising edge
module spirdshft(
output [7:0] dout,
input din,
input clk,
input en);
reg [7:0] doutregister = 8'h00;
assign dout = doutregister;
always @(posedge clk) begin
if(en) begin
doutregister[7:1] <= doutregister[6:0];
doutregister[0] <= din; // Clocked into LSB first
end
end
endmodule
// A parallel input shift register clocked on falling edge
module spiwrshft(
output out,
input [7:0] parallelin,
input rdld,
input clk);
reg [7:0] dinregister = 8'h00;
assign out = dinregister[7];
always @(negedge clk) begin
if(rdld)
dinregister <= parallelin;
else begin
dinregister[7:1] <= dinregister[6:0];
end
end
endmodule
// Clock counter
module spiclkcounter(
output [3:0] clkcount,
input clk,
input en);
reg [3:0] countreg = 0;
assign clkcount = countreg;
// en is async
always @(posedge clk, negedge en) begin
if(en)
countreg <= countreg + 1;
else
countreg <= 4'h0;
end
endmodule
// Address register
module addrregister(
output [3:0] addr,
input clk,
input din,
input en);
reg [3:0] addrreg = 0;
assign addr = addrreg;
always @(posedge clk) begin
if(en) begin
addrreg[3:1] <= addrreg[2:0];
addrreg[0] <= din; // Clocked into MSB first
end
end
endmodule
// Mode register (Stores first bit shifted out as read/~write in a 16 bit transaction)
module moderegister(
output mode,
input clk,
input modet,
input in);
reg modereg = 0;
assign mode = modereg;
always@(posedge clk) begin
if(modet)
modereg = in; // Save the state of the input bit
end
endmodule
// Decode SPI counter counts into transactions
module spiseq(
input [3:0] spiclkcounter,
input spien,
input mode,
output addrt,
output spioe,
output rdt,
output rdld,
output wrt,
output modet);
reg modetreg;
reg addrtreg;
reg rdtreg;
reg wrtreg;
reg rdldreg;
reg spioereg;
assign modet = modetreg;
assign addrt = addrtreg;
assign rdt = rdtreg;
assign wrt = wrtreg;
assign rdld = rdldreg;
assign spioe = spioereg;
always @(*) begin
modetreg = 0;
rdtreg = 0;
addrtreg = 0;
wrtreg = 0;
rdldreg = 0;
spioereg = spien & mode;
case(spiclkcounter)
4'h0:
modetreg <= 1; // Signal to load mode register
4'h1, 4'h2, 4'h3, 4'h4:
addrtreg <= spien; // Signal to load address register
4'h5, 4'h6, 4'h7:
rdtreg <= (mode & spien); // Signal to indicate read transaction
4'h8:
begin
rdtreg <= (mode & spien); // Signal to indicate read transaction
rdldreg <= (mode & spien); // Load shift register
wrtreg <= (~mode & spien); // Signal to indicate write transaction
end
4'h9, 4'ha, 4'hb,
4'hc, 4'hd, 4'he, 4'hf:
wrtreg <= (~mode & spien); // Signal to indicate write transaction
default:
begin
rdtreg <= 1'bx;
wrtreg <= 1'bx;
addrtreg <= 1'bx;
modetreg <= 1'bx;
rdldreg <= 1'bx;
end
endcase
end
endmodule
// Main interface
module spi(
output spidout, // Data to master (MISO)
output rdt, // Indicates a read transaction
output wrt, // Indicates a write transaction
output spioe, // MISO 3 state enable
output [7:0] wrtdata, // Parallel write data out
output [3:0] addr, // Parallel address out
input spien, // SPI enable (SS)
input spiclk, // SPI clock (SCLK)
input spidin, // SPIDIN (MOSI)
input [7:0] rddata); // Parallel read data in
wire mode;
wire rdld;
wire modet;
wire addrt;
wire [3:0] clkcount;
spiclkcounter scc (
.clk(spiclk),
.en(spien),
.clkcount(clkcount));
moderegister mreg (
.clk(spiclk),
.modet(modet),
.in(spidin),
.mode(mode));
addrregister areg (
.clk(spiclk),
.en(addrt),
.din(spidin),
.addr(addr));
spirdshft srs (
.clk(spiclk),
.din(spidin),
.en(wrt),
.dout(wrtdata));
spiwrshft sws (
.clk(spiclk),
.parallelin(rddata),
.rdld(rdld),
.out(spidout));
spiseq ssq (
.spiclkcounter(clkcount),
.spien(spien),
.mode(mode),
.modet(modet),
.spioe(spioe),
.addrt(addrt),
.rdt(rdt),
.rdld(rdld),
.wrt(wrt));
endmodule
|
(** * Norm: Normalization of STLC *)
(* $Date: 2014-04-23 07:36:43 -0400 (Wed, 23 Apr 2014) $ *)
(* Chapter maintained by Andrew Tolmach *)
(* (Based on TAPL Ch. 12.) *)
Require Export Smallstep.
Hint Constructors multi.
(**
(This chapter is optional.)
In this chapter, we consider another fundamental theoretical property
of the simply typed lambda-calculus: the fact that the evaluation of a
well-typed program is guaranteed to halt in a finite number of
steps---i.e., every well-typed term is _normalizable_.
Unlike the type-safety properties we have considered so far, the
normalization property does not extend to full-blown programming
languages, because these languages nearly always extend the simply
typed lambda-calculus with constructs, such as general recursion
(as we discussed in the MoreStlc chapter) or recursive types, that can
be used to write nonterminating programs. However, the issue of
normalization reappears at the level of _types_ when we consider the
metatheory of polymorphic versions of the lambda calculus such as
F_omega: in this system, the language of types effectively contains a
copy of the simply typed lambda-calculus, and the termination of the
typechecking algorithm will hinge on the fact that a ``normalization''
operation on type expressions is guaranteed to terminate.
Another reason for studying normalization proofs is that they are some
of the most beautiful---and mind-blowing---mathematics to be found in
the type theory literature, often (as here) involving the fundamental
proof technique of _logical relations_.
The calculus we shall consider here is the simply typed
lambda-calculus over a single base type [bool] and with pairs. We'll
give full details of the development for the basic lambda-calculus
terms treating [bool] as an uninterpreted base type, and leave the
extension to the boolean operators and pairs to the reader. Even for
the base calculus, normalization is not entirely trivial to prove,
since each reduction of a term can duplicate redexes in subterms. *)
(** **** Exercise: 1 star *)
(** Where do we fail if we attempt to prove normalization by a
straightforward induction on the size of a well-typed term? *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Language *)
(** We begin by repeating the relevant language definition, which is
similar to those in the MoreStlc chapter, and supporting results
including type preservation and step determinism. (We won't need
progress.) You may just wish to skip down to the Normalization
section... *)
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty
| TProd : ty -> ty -> ty
.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TBool" | Case_aux c "TArrow" | Case_aux c "TProd" ].
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* booleans *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(* i.e., [if t0 then t1 else t2] *)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tpair" | Case_aux c "tfst" | Case_aux c "tsnd"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tpair t1 t2 => tpair (subst x s t1) (subst x s t2)
| tfst t1 => tfst (subst x s t1)
| tsnd t1 => tsnd (subst x s t1)
| ttrue => ttrue
| tfalse => tfalse
| tif t0 t1 t2 => tif (subst x s t0) (subst x s t1) (subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
| v_true : value ttrue
| v_false : value tfalse
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* booleans *)
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t0 t0' t1 t2,
t0 ==> t0' ->
(tif t0 t1 t2) ==> (tif t0' t1 t2)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Pair1" | Case_aux c "ST_Pair2"
| Case_aux c "ST_Fst" | Case_aux c "ST_FstPair"
| Case_aux c "ST_Snd" | Case_aux c "ST_SndPair"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
Notation step_normal_form := (normal_form step).
Lemma value__normal : forall t, value t -> step_normal_form t.
Proof with eauto.
intros t H; induction H; intros [t' ST]; inversion ST...
Qed.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
has_type Gamma t1 T1 ->
has_type Gamma t2 T2 ->
has_type Gamma (tpair t1 t2) (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tfst t) T1
| T_Snd : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tsnd t) T2
(* booleans *)
| T_True : forall Gamma,
has_type Gamma ttrue TBool
| T_False : forall Gamma,
has_type Gamma tfalse TBool
| T_If : forall Gamma t0 t1 t2 T,
has_type Gamma t0 TBool ->
has_type Gamma t1 T ->
has_type Gamma t2 T ->
has_type Gamma (tif t0 t1 t2) T
.
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Pair" | Case_aux c "T_Fst" | Case_aux c "T_Snd"
| Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Extern 2 (has_type _ (tapp _ _) _) => eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* booleans *)
| afi_if0 : forall x t0 t1 t2,
appears_free_in x t0 ->
appears_free_in x (tif t0 t1 t2)
| afi_if1 : forall x t0 t1 t2,
appears_free_in x t1 ->
appears_free_in x (tif t0 t1 t2)
| afi_if2 : forall x t0 t1 t2,
appears_free_in x t2 ->
appears_free_in x (tif t0 t1 t2)
.
Hint Constructors appears_free_in.
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend. destruct (eq_id_dec x y)...
Case "T_Pair".
apply T_Pair...
Case "T_If".
eapply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; inversion Hafi; subst...
Case "T_Abs".
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Qed.
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
intros. unfold closed. intros x H1.
destruct (free_in_context _ _ _ _ H1 H) as [T' C].
inversion C. Qed.
(* ###################################################################### *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- ([x:=v]t) S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
t_cases (induction t) Case;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
Case "tvar".
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
Case "tabs".
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
SCase "ST_AppAbs".
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
Case "T_Fst".
inversion HT...
Case "T_Snd".
inversion HT...
Qed.
(** [] *)
(* ###################################################################### *)
(** *** Determinism *)
Lemma step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Normalization *)
(** Now for the actual normalization proof.
Our goal is to prove that every well-typed term evaluates to a
normal form. In fact, it turns out to be convenient to prove
something slightly stronger, namely that every well-typed term
evaluates to a _value_. This follows from the weaker property
anyway via the Progress lemma (why?) but otherwise we don't need
Progress, and we didn't bother re-proving it above.
Here's the key definition: *)
Definition halts (t:tm) : Prop := exists t', t ==>* t' /\ value t'.
(** A trivial fact: *)
Lemma value_halts : forall v, value v -> halts v.
Proof.
intros v H. unfold halts.
exists v. split.
apply multi_refl.
assumption.
Qed.
(** The key issue in the normalization proof (as in many proofs by
induction) is finding a strong enough induction hypothesis. To this
end, we begin by defining, for each type [T], a set [R_T] of closed
terms of type [T]. We will specify these sets using a relation [R]
and write [R T t] when [t] is in [R_T]. (The sets [R_T] are sometimes
called _saturated sets_ or _reducibility candidates_.)
Here is the definition of [R] for the base language:
- [R bool t] iff [t] is a closed term of type [bool] and [t] halts in a value
- [R (T1 -> T2) t] iff [t] is a closed term of type [T1 -> T2] and [t] halts
in a value _and_ for any term [s] such that [R T1 s], we have [R
T2 (t s)]. *)
(** This definition gives us the strengthened induction hypothesis that we
need. Our primary goal is to show that all _programs_ ---i.e., all
closed terms of base type---halt. But closed terms of base type can
contain subterms of functional type, so we need to know something
about these as well. Moreover, it is not enough to know that these
subterms halt, because the application of a normalized function to a
normalized argument involves a substitution, which may enable more
evaluation steps. So we need a stronger condition for terms of
functional type: not only should they halt themselves, but, when
applied to halting arguments, they should yield halting results.
The form of [R] is characteristic of the _logical relations_ proof
technique. (Since we are just dealing with unary relations here, we
could perhaps more properly say _logical predicates_.) If we want to
prove some property [P] of all closed terms of type [A], we proceed by
proving, by induction on types, that all terms of type [A] _possess_
property [P], all terms of type [A->A] _preserve_ property [P], all
terms of type [(A->A)->(A->A)] _preserve the property of preserving_
property [P], and so on. We do this by defining a family of
predicates, indexed by types. For the base type [A], the predicate is
just [P]. For functional types, it says that the function should map
values satisfying the predicate at the input type to values satisfying
the predicate at the output type.
When we come to formalize the definition of [R] in Coq, we hit a
problem. The most obvious formulation would be as a parameterized
Inductive proposition like this:
Inductive R : ty -> tm -> Prop :=
| R_bool : forall b t, has_type empty t TBool ->
halts t ->
R TBool t
| R_arrow : forall T1 T2 t, has_type empty t (TArrow T1 T2) ->
halts t ->
(forall s, R T1 s -> R T2 (tapp t s)) ->
R (TArrow T1 T2) t.
Unfortunately, Coq rejects this definition because it violates the
_strict positivity requirement_ for inductive definitions, which says
that the type being defined must not occur to the left of an arrow in
the type of a constructor argument. Here, it is the third argument to
[R_arrow], namely [(forall s, R T1 s -> R TS (tapp t s))], and
specifically the [R T1 s] part, that violates this rule. (The
outermost arrows separating the constructor arguments don't count when
applying this rule; otherwise we could never have genuinely inductive
predicates at all!) The reason for the rule is that types defined
with non-positive recursion can be used to build non-terminating
functions, which as we know would be a disaster for Coq's logical
soundness. Even though the relation we want in this case might be
perfectly innocent, Coq still rejects it because it fails the
positivity test.
Fortunately, it turns out that we _can_ define [R] using a
[Fixpoint]: *)
Fixpoint R (T:ty) (t:tm) {struct T} : Prop :=
has_type empty t T /\ halts t /\
(match T with
| TBool => True
| TArrow T1 T2 => (forall s, R T1 s -> R T2 (tapp t s))
(* FILL IN HERE *)
| TProd T1 T2 => False (* ... and delete this line *)
end).
(** As immediate consequences of this definition, we have that every
element of every set [R_T] halts in a value and is closed with type
[t] :*)
Lemma R_halts : forall {T} {t}, R T t -> halts t.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
Lemma R_typable_empty : forall {T} {t}, R T t -> has_type empty t T.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
(** Now we proceed to show the main result, which is that every
well-typed term of type [T] is an element of [R_T]. Together with
[R_halts], that will show that every well-typed term halts in a
value. *)
(* ###################################################################### *)
(** ** Membership in [R_T] is invariant under evaluation *)
(** We start with a preliminary lemma that shows a kind of strong
preservation property, namely that membership in [R_T] is _invariant_
under evaluation. We will need this property in both directions,
i.e. both to show that a term in [R_T] stays in [R_T] when it takes a
forward step, and to show that any term that ends up in [R_T] after a
step must have been in [R_T] to begin with.
First of all, an easy preliminary lemma. Note that in the forward
direction the proof depends on the fact that our language is
determinstic. This lemma might still be true for non-deterministic
languages, but the proof would be harder! *)
Lemma step_preserves_halting : forall t t', (t ==> t') -> (halts t <-> halts t').
Proof.
intros t t' ST. unfold halts.
split.
Case "->".
intros [t'' [STM V]].
inversion STM; subst.
apply ex_falso_quodlibet. apply value__normal in V. unfold normal_form in V. apply V. exists t'. auto.
rewrite (step_deterministic _ _ _ ST H). exists t''. split; assumption.
Case "<-".
intros [t'0 [STM V]].
exists t'0. split; eauto.
Qed.
(** Now the main lemma, which comes in two parts, one for each
direction. Each proceeds by induction on the structure of the type
[T]. In fact, this is where we make fundamental use of the
structure of types.
One requirement for staying in [R_T] is to stay in type [T]. In the
forward direction, we get this from ordinary type Preservation. *)
Lemma step_preserves_R : forall T t t', (t ==> t') -> R T t -> R T t'.
Proof.
induction T; intros t t' E Rt; unfold R; fold R; unfold R in Rt; fold R in Rt;
destruct Rt as [typable_empty_t [halts_t RRt]].
(* TBool *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
auto.
(* TArrow *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
intros.
eapply IHT2.
apply ST_App1. apply E.
apply RRt; auto.
(* FILL IN HERE *) Admitted.
(** The generalization to multiple steps is trivial: *)
Lemma multistep_preserves_R : forall T t t',
(t ==>* t') -> R T t -> R T t'.
Proof.
intros T t t' STM; induction STM; intros.
assumption.
apply IHSTM. eapply step_preserves_R. apply H. assumption.
Qed.
(** In the reverse direction, we must add the fact that [t] has type
[T] before stepping as an additional hypothesis. *)
Lemma step_preserves_R' : forall T t t',
has_type empty t T -> (t ==> t') -> R T t' -> R T t.
Proof.
(* FILL IN HERE *) Admitted.
Lemma multistep_preserves_R' : forall T t t',
has_type empty t T -> (t ==>* t') -> R T t' -> R T t.
Proof.
intros T t t' HT STM.
induction STM; intros.
assumption.
eapply step_preserves_R'. assumption. apply H. apply IHSTM.
eapply preservation; eauto. auto.
Qed.
(* ###################################################################### *)
(** ** Closed instances of terms of type [T] belong to [R_T] *)
(** Now we proceed to show that every term of type [T] belongs to
[R_T]. Here, the induction will be on typing derivations (it would be
surprising to see a proof about well-typed terms that did not
somewhere involve induction on typing derivations!). The only
technical difficulty here is in dealing with the abstraction case.
Since we are arguing by induction, the demonstration that a term
[tabs x T1 t2] belongs to [R_(T1->T2)] should involve applying the
induction hypothesis to show that [t2] belongs to [R_(T2)]. But
[R_(T2)] is defined to be a set of _closed_ terms, while [t2] may
contain [x] free, so this does not make sense.
This problem is resolved by using a standard trick to suitably
generalize the induction hypothesis: instead of proving a statement
involving a closed term, we generalize it to cover all closed
_instances_ of an open term [t]. Informally, the statement of the
lemma will look like this:
If [x1:T1,..xn:Tn |- t : T] and [v1,...,vn] are values such that
[R T1 v1], [R T2 v2], ..., [R Tn vn], then
[R T ([x1:=v1][x2:=v2]...[xn:=vn]t)].
The proof will proceed by induction on the typing derivation
[x1:T1,..xn:Tn |- t : T]; the most interesting case will be the one
for abstraction. *)
(* ###################################################################### *)
(** *** Multisubstitutions, multi-extensions, and instantiations *)
(** However, before we can proceed to formalize the statement and
proof of the lemma, we'll need to build some (rather tedious)
machinery to deal with the fact that we are performing _multiple_
substitutions on term [t] and _multiple_ extensions of the typing
context. In particular, we must be precise about the order in which
the substitutions occur and how they act on each other. Often these
details are simply elided in informal paper proofs, but of course Coq
won't let us do that. Since here we are substituting closed terms, we
don't need to worry about how one substitution might affect the term
put in place by another. But we still do need to worry about the
_order_ of substitutions, because it is quite possible for the same
identifier to appear multiple times among the [x1,...xn] with
different associated [vi] and [Ti].
To make everything precise, we will assume that environments are
extended from left to right, and multiple substitutions are performed
from right to left. To see that this is consistent, suppose we have
an environment written as [...,y:bool,...,y:nat,...] and a
corresponding term substitution written as [...[y:=(tbool
true)]...[y:=(tnat 3)]...t]. Since environments are extended from
left to right, the binding [y:nat] hides the binding [y:bool]; since
substitutions are performed right to left, we do the substitution
[y:=(tnat 3)] first, so that the substitution [y:=(tbool true)] has
no effect. Substitution thus correctly preserves the type of the term.
With these points in mind, the following definitions should make sense.
A _multisubstitution_ is the result of applying a list of
substitutions, which we call an _environment_. *)
Definition env := list (id * tm).
Fixpoint msubst (ss:env) (t:tm) {struct ss} : tm :=
match ss with
| nil => t
| ((x,s)::ss') => msubst ss' ([x:=s]t)
end.
(** We need similar machinery to talk about repeated extension of a
typing context using a list of (identifier, type) pairs, which we
call a _type assignment_. *)
Definition tass := list (id * ty).
Fixpoint mextend (Gamma : context) (xts : tass) :=
match xts with
| nil => Gamma
| ((x,v)::xts') => extend (mextend Gamma xts') x v
end.
(** We will need some simple operations that work uniformly on
environments and type assigments *)
Fixpoint lookup {X:Set} (k : id) (l : list (id * X)) {struct l} : option X :=
match l with
| nil => None
| (j,x) :: l' =>
if eq_id_dec j k then Some x else lookup k l'
end.
Fixpoint drop {X:Set} (n:id) (nxs:list (id * X)) {struct nxs} : list (id * X) :=
match nxs with
| nil => nil
| ((n',x)::nxs') => if eq_id_dec n' n then drop n nxs' else (n',x)::(drop n nxs')
end.
(** An _instantiation_ combines a type assignment and a value
environment with the same domains, where corresponding elements are
in R *)
Inductive instantiation : tass -> env -> Prop :=
| V_nil : instantiation nil nil
| V_cons : forall x T v c e, value v -> R T v -> instantiation c e -> instantiation ((x,T)::c) ((x,v)::e).
(** We now proceed to prove various properties of these definitions. *)
(* ###################################################################### *)
(** *** More Substitution Facts *)
(** First we need some additional lemmas on (ordinary) substitution. *)
Lemma vacuous_substitution : forall t x,
~ appears_free_in x t ->
forall t', [x:=t']t = t.
Proof with eauto.
(* FILL IN HERE *) Admitted.
Lemma subst_closed: forall t,
closed t ->
forall x t', [x:=t']t = t.
Proof.
intros. apply vacuous_substitution. apply H. Qed.
Lemma subst_not_afi : forall t x v, closed v -> ~ appears_free_in x ([x:=v]t).
Proof with eauto. (* rather slow this way *)
unfold closed, not.
t_cases (induction t) Case; intros x v P A; simpl in A.
Case "tvar".
destruct (eq_id_dec x i)...
inversion A; subst. auto.
Case "tapp".
inversion A; subst...
Case "tabs".
destruct (eq_id_dec x i)...
inversion A; subst...
inversion A; subst...
Case "tpair".
inversion A; subst...
Case "tfst".
inversion A; subst...
Case "tsnd".
inversion A; subst...
Case "ttrue".
inversion A.
Case "tfalse".
inversion A.
Case "tif".
inversion A; subst...
Qed.
Lemma duplicate_subst : forall t' x t v,
closed v -> [x:=t]([x:=v]t') = [x:=v]t'.
Proof.
intros. eapply vacuous_substitution. apply subst_not_afi. auto.
Qed.
Lemma swap_subst : forall t x x1 v v1, x <> x1 -> closed v -> closed v1 ->
[x1:=v1]([x:=v]t) = [x:=v]([x1:=v1]t).
Proof with eauto.
t_cases (induction t) Case; intros; simpl.
Case "tvar".
destruct (eq_id_dec x i); destruct (eq_id_dec x1 i).
subst. apply ex_falso_quodlibet...
subst. simpl. rewrite eq_id. apply subst_closed...
subst. simpl. rewrite eq_id. rewrite subst_closed...
simpl. rewrite neq_id... rewrite neq_id...
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Properties of multi-substitutions *)
Lemma msubst_closed: forall t, closed t -> forall ss, msubst ss t = t.
Proof.
induction ss.
reflexivity.
destruct a. simpl. rewrite subst_closed; assumption.
Qed.
(** Closed environments are those that contain only closed terms. *)
Fixpoint closed_env (env:env) {struct env} :=
match env with
| nil => True
| (x,t)::env' => closed t /\ closed_env env'
end.
(** Next come a series of lemmas charcterizing how [msubst] of closed terms
distributes over [subst] and over each term form *)
Lemma subst_msubst: forall env x v t, closed v -> closed_env env ->
msubst env ([x:=v]t) = [x:=v](msubst (drop x env) t).
Proof.
induction env0; intros.
auto.
destruct a. simpl.
inversion H0. fold closed_env in H2.
destruct (eq_id_dec i x).
subst. rewrite duplicate_subst; auto.
simpl. rewrite swap_subst; eauto.
Qed.
Lemma msubst_var: forall ss x, closed_env ss ->
msubst ss (tvar x) =
match lookup x ss with
| Some t => t
| None => tvar x
end.
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (eq_id_dec i x).
apply msubst_closed. inversion H; auto.
apply IHss. inversion H; auto.
Qed.
Lemma msubst_abs: forall ss x T t,
msubst ss (tabs x T t) = tabs x T (msubst (drop x ss) t).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (eq_id_dec i x); simpl; auto.
Qed.
Lemma msubst_app : forall ss t1 t2, msubst ss (tapp t1 t2) = tapp (msubst ss t1) (msubst ss t2).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. rewrite <- IHss. auto.
Qed.
(** You'll need similar functions for the other term constructors. *)
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** Properties of multi-extensions *)
(** We need to connect the behavior of type assignments with that of their
corresponding contexts. *)
Lemma mextend_lookup : forall (c : tass) (x:id), lookup x c = (mextend empty c) x.
Proof.
induction c; intros.
auto.
destruct a. unfold lookup, mextend, extend. destruct (eq_id_dec i x); auto.
Qed.
Lemma mextend_drop : forall (c: tass) Gamma x x',
mextend Gamma (drop x c) x' = if eq_id_dec x x' then Gamma x' else mextend Gamma c x'.
induction c; intros.
destruct (eq_id_dec x x'); auto.
destruct a. simpl.
destruct (eq_id_dec i x).
subst. rewrite IHc.
destruct (eq_id_dec x x'). auto. unfold extend. rewrite neq_id; auto.
simpl. unfold extend. destruct (eq_id_dec i x').
subst.
destruct (eq_id_dec x x').
subst. exfalso. auto.
auto.
auto.
Qed.
(* ###################################################################### *)
(** *** Properties of Instantiations *)
(** These are strightforward. *)
Lemma instantiation_domains_match: forall {c} {e},
instantiation c e -> forall {x} {T}, lookup x c = Some T -> exists t, lookup x e = Some t.
Proof.
intros c e V. induction V; intros x0 T0 C.
solve by inversion .
simpl in *.
destruct (eq_id_dec x x0); eauto.
Qed.
Lemma instantiation_env_closed : forall c e, instantiation c e -> closed_env e.
Proof.
intros c e V; induction V; intros.
econstructor.
unfold closed_env. fold closed_env.
split. eapply typable_empty__closed. eapply R_typable_empty. eauto.
auto.
Qed.
Lemma instantiation_R : forall c e, instantiation c e ->
forall x t T, lookup x c = Some T ->
lookup x e = Some t -> R T t.
Proof.
intros c e V. induction V; intros x' t' T' G E.
solve by inversion.
unfold lookup in *. destruct (eq_id_dec x x').
inversion G; inversion E; subst. auto.
eauto.
Qed.
Lemma instantiation_drop : forall c env,
instantiation c env -> forall x, instantiation (drop x c) (drop x env).
Proof.
intros c e V. induction V.
intros. simpl. constructor.
intros. unfold drop. destruct (eq_id_dec x x0); auto. constructor; eauto.
Qed.
(* ###################################################################### *)
(** *** Congruence lemmas on multistep *)
(** We'll need just a few of these; add them as the demand arises. *)
Lemma multistep_App2 : forall v t t',
value v -> (t ==>* t') -> (tapp v t) ==>* (tapp v t').
Proof.
intros v t t' V STM. induction STM.
apply multi_refl.
eapply multi_step.
apply ST_App2; eauto. auto.
Qed.
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** The R Lemma. *)
(** We finally put everything together.
The key lemma about preservation of typing under substitution can
be lifted to multi-substitutions: *)
Lemma msubst_preserves_typing : forall c e,
instantiation c e ->
forall Gamma t S, has_type (mextend Gamma c) t S ->
has_type Gamma (msubst e t) S.
Proof.
induction 1; intros.
simpl in H. simpl. auto.
simpl in H2. simpl.
apply IHinstantiation.
eapply substitution_preserves_typing; eauto.
apply (R_typable_empty H0).
Qed.
(** And at long last, the main lemma. *)
Lemma msubst_R : forall c env t T,
has_type (mextend empty c) t T -> instantiation c env -> R T (msubst env t).
Proof.
intros c env0 t T HT V.
generalize dependent env0.
(* We need to generalize the hypothesis a bit before setting up the induction. *)
remember (mextend empty c) as Gamma.
assert (forall x, Gamma x = lookup x c).
intros. rewrite HeqGamma. rewrite mextend_lookup. auto.
clear HeqGamma.
generalize dependent c.
has_type_cases (induction HT) Case; intros.
Case "T_Var".
rewrite H0 in H. destruct (instantiation_domains_match V H) as [t P].
eapply instantiation_R; eauto.
rewrite msubst_var. rewrite P. auto. eapply instantiation_env_closed; eauto.
Case "T_Abs".
rewrite msubst_abs.
(* We'll need variants of the following fact several times, so its simplest to
establish it just once. *)
assert (WT: has_type empty (tabs x T11 (msubst (drop x env0) t12)) (TArrow T11 T12)).
eapply T_Abs. eapply msubst_preserves_typing. eapply instantiation_drop; eauto.
eapply context_invariance. apply HT.
intros.
unfold extend. rewrite mextend_drop. destruct (eq_id_dec x x0). auto.
rewrite H.
clear - c n. induction c.
simpl. rewrite neq_id; auto.
simpl. destruct a. unfold extend. destruct (eq_id_dec i x0); auto.
unfold R. fold R. split.
auto.
split. apply value_halts. apply v_abs.
intros.
destruct (R_halts H0) as [v [P Q]].
pose proof (multistep_preserves_R _ _ _ P H0).
apply multistep_preserves_R' with (msubst ((x,v)::env0) t12).
eapply T_App. eauto.
apply R_typable_empty; auto.
eapply multi_trans. eapply multistep_App2; eauto.
eapply multi_R.
simpl. rewrite subst_msubst.
eapply ST_AppAbs; eauto.
eapply typable_empty__closed.
apply (R_typable_empty H1).
eapply instantiation_env_closed; eauto.
eapply (IHHT ((x,T11)::c)).
intros. unfold extend, lookup. destruct (eq_id_dec x x0); auto.
constructor; auto.
Case "T_App".
rewrite msubst_app.
destruct (IHHT1 c H env0 V) as [_ [_ P1]].
pose proof (IHHT2 c H env0 V) as P2. fold R in P1. auto.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Normalization Theorem *)
Theorem normalization : forall t T, has_type empty t T -> halts t.
Proof.
intros.
replace t with (msubst nil t) by reflexivity.
apply (@R_halts T).
apply (msubst_R nil); eauto.
eapply V_nil.
Qed.
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
assign dsp_sel[0] = i;
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF3(
.Q(a), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(d), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF2(
.Q(b), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(a), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF1(
.Q(c), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(b), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF0(
.Q(d), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(c), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF7(
.Q(e), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(h), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF6(
.Q(f), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(e), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF5(
.Q(g), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(f), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF4(
.Q(h), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(g), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF11(
.Q(i), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(l), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF10(
.Q(j), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(i), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF9(
.Q(k), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(j), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF8(
.Q(l), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(k), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 10:19:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_0_0(clk, rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_565[15:0],rgb_888[23:0]" */;
input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Listens to signals from a kernel to detect when
// all required items are processed.
module acl_kernel_done_detector
#(
parameter WIDTH = 32 // width of all the counters
)
(
input clock,
input resetn,
input start, // Assert to restart the iterators
// listen to kernel's stall/valid signals
input kernel_stall_out,
input kernel_valid_in,
input kernel_stall_in,
input kernel_valid_out,
// high when it looks like the kernel is done
// only is true if all the groups were also dispatched
output kernel_done
);
// counter for number of items inside the kernel
reg [WIDTH-1:0] items_not_done;
// Valid_in to kernel will go low when the fifo inside the acl_id_iterator
// becomes empty. This means there is no more groups to dispatch.
assign all_items_sent = ~kernel_valid_in & ~kernel_stall_out;
assign kernel_done = (items_not_done == {WIDTH{1'b0}});
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
items_not_done <= {WIDTH{1'b0}};
else if ( start )
items_not_done <= {WIDTH{1'b0}};
else begin
if (kernel_valid_in & ~kernel_stall_out & (~kernel_valid_out | kernel_stall_in))
items_not_done <= (items_not_done + 2'b01);
else
if (kernel_valid_out & ~kernel_stall_in & (~kernel_valid_in | kernel_stall_out))
items_not_done <= (items_not_done - 2'b01);
end
end
endmodule
// Produces finish signal when all kernel copies are done.
module acl_all_done_detector
#(
parameter NUM_COPIES = 1 // number of kernel instance copies
)
(
input clock,
input resetn,
input start,
input dispatched_all_groups,
input [NUM_COPIES-1:0] kernel_done,
output reg finish
);
// Need to know if sent at least one work item into any of the kernel
// copies (some kernel copies can never be used if don't have enough
// work-groups). Allow upto 5 cycles for the effect of the first item
// to propagate to kernel_done signals.
localparam MAX_CYCLE_COUNTER_VALUE = 5;
reg [3:0] cycles_since_sent_first_item;
wire sent_first_item = (cycles_since_sent_first_item == MAX_CYCLE_COUNTER_VALUE);
// used to bring down 'finish' after it being high for one cycle.
reg not_finished;
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
finish <= 1'b0;
else if ( start )
finish <= 1'b0;
else
finish <= not_finished &
dispatched_all_groups &
sent_first_item &
(kernel_done == {NUM_COPIES{1'b1}});
end
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
not_finished <= 1'b1;
else if ( start )
not_finished <= 1'b1;
else if ( finish )
not_finished <= 1'b0;
else
not_finished <= not_finished;
end
// Assuming that if dispatched all groups, sent at least one
// item into at least one kernel.
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
cycles_since_sent_first_item <= 0;
else if ( start )
cycles_since_sent_first_item <= 0;
else if ( cycles_since_sent_first_item == MAX_CYCLE_COUNTER_VALUE )
cycles_since_sent_first_item <= MAX_CYCLE_COUNTER_VALUE;
else if ( dispatched_all_groups | (cycles_since_sent_first_item > 0) )
cycles_since_sent_first_item <= cycles_since_sent_first_item + 1;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sdrdrum_arty (
// Clock and Reset
input wire clk_in,
input wire rstn_in,
// DACs
output wire dac_clk,
output wire dac_data,
output wire dac_ldac,
output wire dac_cs,
// ADCs
output wire adc_ab_clk,
output wire adc_ab_cnv,
output wire adc_cd_clk,
output wire adc_cd_cnv,
input wire adc_a_data,
input wire adc_b_data,
input wire adc_c_data,
input wire adc_d_data,
// Ethernet
input wire [3:0] eth_phy_rxd,
input wire eth_phy_rx_clk,
input wire eth_phy_rx_dv,
input wire eth_phy_rx_er,
output wire [3:0] eth_phy_txd,
input wire eth_phy_tx_clk,
output wire eth_phy_tx_en,
output wire eth_phy_clk,
output wire eth_phy_rstn,
input wire eth_phy_crs,
input wire eth_phy_col,
// UART
input wire usb_uart_rxd,
output wire usb_uart_txd,
// IO
input wire [3:0] switches,
input wire [3:0] buttons,
output wire [11:0] rgb_leds,
output wire [3:0] leds
);
//==============================================================================
// Control and Status Signals
//==============================================================================
wire [15:0] control;
wire [23:0] status;
wire [12:0] freq_1;
wire [12:0] freq_2;
//==============================================================================
// Clock Generator
//==============================================================================
wire resetn;
wire clk;
wire dcm_locked;
xlnx_clk_gen_pmod_eth clocks (
.clk_in1(clk_in),
.resetn(rstn_in),
.axi_clk(clk),
.eth_clk(eth_phy_clk),
.locked(dcm_locked)
);
//==============================================================================
// Stick Signal Generation
//==============================================================================
wire stick_1_phase_ready;
wire [23:0] stick_1_phase_data;
wire stick_1_phase_valid;
wire stick_signal_ready;
wire stick_1_signal_valid;
wire [16:0] stick_1_signal_data;
wire stick_2_phase_ready;
wire [23:0] stick_2_phase_data;
wire stick_2_phase_valid;
wire stick_2_signal_valid;
wire [16:0] stick_2_signal_data;
axis_phase_generator #(
.AXIS_TDATA_WIDTH(24),
.PHASE_WIDTH(15)
) stick_1_phase (
.aclk(clk),
.aresetn(resetn),
.cfg_data({2'b0, freq_1}),
.m_axis_tready(stick_1_phase_ready),
.m_axis_tdata(stick_1_phase_data),
.m_axis_tvalid(stick_1_phase_valid)
);
axis_phase_generator #(
.AXIS_TDATA_WIDTH(24),
.PHASE_WIDTH(15)
) stick_2_phase (
.aclk(clk),
.aresetn(resetn),
.cfg_data({2'b0, freq_2}),
.m_axis_tready(stick_2_phase_ready),
.m_axis_tdata(stick_2_phase_data),
.m_axis_tvalid(stick_2_phase_valid)
);
generator stick_1_gen (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_1_phase_data),
.phase_tready(stick_1_phase_ready),
.phase_tvalid(stick_1_phase_valid),
.signal_tdata(stick_1_signal_data),
.signal_tvalid(stick_1_signal_valid),
.signal_tready(stick_signal_ready)
);
generator stick_2_gen (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_2_phase_data),
.phase_tready(stick_2_phase_ready),
.phase_tvalid(stick_2_phase_valid),
.signal_tdata(stick_2_signal_data),
.signal_tvalid(stick_2_signal_valid),
.signal_tready(stick_signal_ready)
);
reg [31:0] stick_out_data;
always @* begin
if (stick_1_signal_data[16:0] == 17'h8000) begin
stick_out_data[31:16] = 16'hFFFF;
end else begin
stick_out_data[31:16] = {~stick_1_signal_data[15], stick_1_signal_data[14:0]};
end
if (stick_2_signal_data[16:0] == 17'h8000) begin
stick_out_data[15:0] = 16'hFFFF;
end else begin
stick_out_data[15:0] = {~stick_2_signal_data[15], stick_2_signal_data[14:0]};
end
end
ad5545 stick_dac_out (
.clk(clk),
.rstn(resetn),
.data(stick_out_data),
.ready(stick_signal_ready),
.valid(stick_1_signal_valid & stick_2_signal_valid),
.cs(dac_cs),
.din(dac_data),
.ldac(dac_ldac),
.sclk(dac_clk)
);
//==============================================================================
// Corner Signal DSP
//==============================================================================
wire [15:0] corner_a_data;
wire [15:0] corner_b_data;
wire [15:0] corner_c_data;
wire [15:0] corner_d_data;
wire corner_a_valid;
wire corner_b_valid;
wire corner_c_valid;
wire corner_d_valid;
wire dsp_a_ready;
wire dsp_b_ready;
wire dsp_c_ready;
wire dsp_d_ready;
wire [31:0] magnitude_1_a_data;
wire [31:0] magnitude_1_b_data;
wire [31:0] magnitude_1_c_data;
wire [31:0] magnitude_1_d_data;
wire [31:0] magnitude_2_a_data;
wire [31:0] magnitude_2_b_data;
wire [31:0] magnitude_2_c_data;
wire [31:0] magnitude_2_d_data;
wire magnitude_1_a_valid;
wire magnitude_1_b_valid;
wire magnitude_1_c_valid;
wire magnitude_1_d_valid;
wire magnitude_2_a_valid;
wire magnitude_2_b_valid;
wire magnitude_2_c_valid;
wire magnitude_2_d_valid;
ad7980 corner_a_adc_in (
.clk(clk),
.rstn(resetn),
.data(corner_a_data),
.ready(dsp_a_ready),
.valid(corner_a_valid),
.sdo(adc_a_data),
.cnv(adc_ab_cnv),
.sclk(adc_ab_clk)
);
ad7980 corner_b_adc_in (
.clk(clk),
.rstn(resetn),
.data(corner_b_data),
.ready(dsp_b_ready),
.valid(corner_b_valid),
.sdo(adc_b_data),
.cnv(),
.sclk()
);
ad7980 corner_c_adc_in (
.clk(clk),
.rstn(resetn),
.data(corner_c_data),
.ready(dsp_c_ready),
.valid(corner_c_valid),
.sdo(adc_c_data),
.cnv(adc_cd_cnv),
.sclk(adc_cd_clk)
);
ad7980 corner_d_adc_in (
.clk(clk),
.rstn(resetn),
.data(corner_d_data),
.ready(dsp_d_ready),
.valid(corner_d_valid),
.sdo(adc_d_data),
.cnv(),
.sclk()
);
channel corner_dsp_1_a (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_1_phase_data),
.phase_tready(),
.phase_tvalid(stick_1_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_a_data[15]}}, corner_a_data[14:0]}),
.samples_tready(dsp_a_ready),
.samples_tvalid(corner_a_valid),
.magnitude_tdata(magnitude_1_a_data),
.magnitude_tvalid(magnitude_1_a_valid)
);
channel corner_dsp_1_b (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_1_phase_data),
.phase_tready(),
.phase_tvalid(stick_1_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_b_data[15]}}, corner_b_data[14:0]}),
.samples_tready(dsp_b_ready),
.samples_tvalid(corner_b_valid),
.magnitude_tdata(magnitude_1_b_data),
.magnitude_tvalid(magnitude_1_b_valid)
);
channel corner_dsp_1_c (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_1_phase_data),
.phase_tready(),
.phase_tvalid(stick_1_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_c_data[15]}}, corner_c_data[14:0]}),
.samples_tready(dsp_c_ready),
.samples_tvalid(corner_c_valid),
.magnitude_tdata(magnitude_1_c_data),
.magnitude_tvalid(magnitude_1_c_valid)
);
channel corner_dsp_1_d (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_1_phase_data),
.phase_tready(),
.phase_tvalid(stick_1_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_d_data[15]}}, corner_d_data[14:0]}),
.samples_tready(dsp_d_ready),
.samples_tvalid(corner_d_valid),
.magnitude_tdata(magnitude_1_d_data),
.magnitude_tvalid(magnitude_1_d_valid)
);
channel corner_dsp_2_a (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_2_phase_data),
.phase_tready(),
.phase_tvalid(stick_2_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_a_data[15]}}, corner_a_data[14:0]}),
.samples_tready(),
.samples_tvalid(corner_a_valid),
.magnitude_tdata(magnitude_2_a_data),
.magnitude_tvalid(magnitude_2_a_valid)
);
channel corner_dsp_2_b (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_2_phase_data),
.phase_tready(),
.phase_tvalid(stick_2_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_b_data[15]}}, corner_b_data[14:0]}),
.samples_tready(),
.samples_tvalid(corner_b_valid),
.magnitude_tdata(magnitude_2_b_data),
.magnitude_tvalid(magnitude_2_b_valid)
);
channel corner_dsp_2_c (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_2_phase_data),
.phase_tready(),
.phase_tvalid(stick_2_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_c_data[15]}}, corner_c_data[14:0]}),
.samples_tready(),
.samples_tvalid(corner_c_valid),
.magnitude_tdata(magnitude_2_c_data),
.magnitude_tvalid(magnitude_2_c_valid)
);
channel corner_dsp_2_d (
.aclk(clk),
.aresetn(resetn),
.phase_tdata(stick_2_phase_data),
.phase_tready(),
.phase_tvalid(stick_2_phase_valid),
.samples_tdata({{7{1'b0}}, {2{~corner_d_data[15]}}, corner_d_data[14:0]}),
.samples_tready(),
.samples_tvalid(corner_d_valid),
.magnitude_tdata(magnitude_2_d_data),
.magnitude_tvalid(magnitude_2_d_valid)
);
//==============================================================================
// Ethernet Framer
//==============================================================================
wire [31:0] eth_mac_axi_awaddr;
wire eth_mac_axi_awvalid;
wire eth_mac_axi_awready;
wire [31:0] eth_mac_axi_wdata;
wire [3:0] eth_mac_axi_wstrb;
wire eth_mac_axi_wvalid;
wire eth_mac_axi_wready;
wire [1:0] eth_mac_axi_bresp;
wire eth_mac_axi_bvalid;
wire eth_mac_axi_bready;
wire [31:0] eth_mac_axi_araddr;
wire eth_mac_axi_arvalid;
wire eth_mac_axi_arready;
wire [31:0] eth_mac_axi_rdata;
wire [1:0] eth_mac_axi_rresp;
wire eth_mac_axi_rvalid;
wire eth_mac_axi_rready;
framer ethernet_framer (
.aclk(clk),
.aresetn(resetn),
.s_axis_tdata({magnitude_2_d_data, magnitude_2_c_data, magnitude_2_b_data, magnitude_2_a_data, magnitude_1_d_data, magnitude_1_c_data, magnitude_1_b_data, magnitude_1_a_data}),
.s_axis_tvalid(magnitude_1_a_valid),
.s_axis_tready(),
.m_axi_awaddr(eth_mac_axi_awaddr),
.m_axi_awvalid(eth_mac_axi_awvalid),
.m_axi_awready(eth_mac_axi_awready),
.m_axi_wdata(eth_mac_axi_wdata),
.m_axi_wstrb(eth_mac_axi_wstrb),
.m_axi_wvalid(eth_mac_axi_wvalid),
.m_axi_wready(eth_mac_axi_wready),
.m_axi_bresp(eth_mac_axi_bresp),
.m_axi_bvalid(eth_mac_axi_bvalid),
.m_axi_bready(eth_mac_axi_bready),
.m_axi_araddr(eth_mac_axi_araddr),
.m_axi_arvalid(eth_mac_axi_arvalid),
.m_axi_arready(eth_mac_axi_arready),
.m_axi_rdata(eth_mac_axi_rdata),
.m_axi_rresp(eth_mac_axi_rresp),
.m_axi_rvalid(eth_mac_axi_rvalid),
.m_axi_rready(eth_mac_axi_rready)
);
//==============================================================================
// MicroBlaze
//==============================================================================
controller controller (
.clk(clk),
.dcm_locked(dcm_locked),
.ext_reset(rstn_in),
.resetn(resetn),
.eth_mac_axi_awaddr(eth_mac_axi_awaddr),
.eth_mac_axi_awvalid(eth_mac_axi_awvalid),
.eth_mac_axi_awready(eth_mac_axi_awready),
.eth_mac_axi_awprot(3'b0),
.eth_mac_axi_wdata(eth_mac_axi_wdata),
.eth_mac_axi_wstrb(eth_mac_axi_wstrb),
.eth_mac_axi_wvalid(eth_mac_axi_wvalid),
.eth_mac_axi_wready(eth_mac_axi_wready),
.eth_mac_axi_bresp(eth_mac_axi_bresp),
.eth_mac_axi_bvalid(eth_mac_axi_bvalid),
.eth_mac_axi_bready(eth_mac_axi_bready),
.eth_mac_axi_araddr(eth_mac_axi_araddr),
.eth_mac_axi_arvalid(eth_mac_axi_arvalid),
.eth_mac_axi_arready(eth_mac_axi_arready),
.eth_mac_axi_arprot(3'b0),
.eth_mac_axi_rdata(eth_mac_axi_rdata),
.eth_mac_axi_rresp(eth_mac_axi_rresp),
.eth_mac_axi_rvalid(eth_mac_axi_rvalid),
.eth_mac_axi_rready(eth_mac_axi_rready),
.eth_mii_col(eth_phy_col),
.eth_mii_crs(eth_phy_crs),
.eth_mii_rst_n(eth_phy_rstn),
.eth_mii_rx_clk(eth_phy_rx_clk),
.eth_mii_rx_dv(eth_phy_rx_dv),
.eth_mii_rx_er(eth_phy_rx_er),
.eth_mii_rxd(eth_phy_rxd),
.eth_mii_tx_clk(eth_phy_tx_clk),
.eth_mii_tx_en(eth_phy_tx_en),
.eth_mii_txd(eth_phy_txd),
.usb_uart_rxd(usb_uart_rxd),
.usb_uart_txd(usb_uart_txd),
.switches(switches),
.buttons(buttons),
.leds(leds),
.rgb_leds(rgb_leds),
.control(control),
.status(status),
.freq_1_tri_o(freq_1),
.freq_2_tri_o(freq_2)
);
endmodule
|
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out1.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_out1 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input datain_h;
input datain_l;
input outclock;
output dataout;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_wire2;
wire sub_wire4 = datain_l;
wire sub_wire5 = sub_wire4;
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (sub_wire3),
.aclr (aclr),
.datain_l (sub_wire5),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_bb.v TRUE
|
`timescale 1 ns / 1 ps
module axis_red_pitaya_adc #
(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
output wire adc_clk,
// ADC signals
output wire adc_csn,
input wire adc_clk_p,
input wire adc_clk_n,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_a,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_b,
// Master side
output wire m_axis_tvalid,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata
);
localparam PADDING_WIDTH = AXIS_TDATA_WIDTH/2 - ADC_DATA_WIDTH;
reg [ADC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [ADC_DATA_WIDTH-1:0] int_dat_b_reg;
wire int_clk;
IBUFGDS adc_clk_inst (.I(adc_clk_p), .IB(adc_clk_n), .O(int_clk));
always @(posedge int_clk)
begin
int_dat_a_reg <= adc_dat_a;
int_dat_b_reg <= adc_dat_b;
end
assign adc_clk = int_clk;
assign adc_csn = 1'b1;
assign m_axis_tvalid = 1'b1;
assign m_axis_tdata = {
{(PADDING_WIDTH+1){int_dat_b_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_b_reg[ADC_DATA_WIDTH-2:0],
{(PADDING_WIDTH+1){int_dat_a_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_a_reg[ADC_DATA_WIDTH-2:0]};
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test is intended to be run with ``iverilog -S foo.v'',
* and tests the situation addressed by pr#519.
*/
module main;
reg [3:0] a, b, c, t;
(* ivl_combinational *)
always @(a, b) begin
t = a + b;
c = 4'd1 + ~t;
end
(* ivl_synthesis_off *)
initial begin
a = 1;
for (b = 0 ; b < 4'hf ; b = b + 1) begin
#1 if (c !== -(a + b)) begin
$display("FAILED -- a=%b, b=%b, t=%b, c=%b", a, b, t, c);
$finish;
end
end
$display("PASSED");
end // initial begin
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_SC_top.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_BCH_SC_top
// File Name: d_BCH_SC_top.v
//
// Version: v2.0.0-256B_T14
//
// Description: Syndrome calculator (SC) top module for data area
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
// * v2.0.0
// - change state machine: additional signal and state for pipeline
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: buffered output
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_SC_parameters.vh"
`timescale 1ns / 1ps
module d_BCH_SC_top(
input wire i_clk,
input wire i_RESET,
input wire i_stop_dec,
input wire i_buf_available,
input wire [4:0] i_chunk_number,
output wire o_sc_available, // [indicate] syndrome calculator ready
input wire i_exe_sc, // syndrome calculation start command signal
input wire i_code_valid, // code BUS strobe signal
input wire [`D_SC_P_LVL-1:0] i_code, // code block data BUS
output reg o_code_ready,
output wire o_sc_start, // [indicate] syndrome calculation start
output wire o_last_c_block_rcvd, // [indicate] last code block received
output wire o_sc_cmplt, // [indicate] syndrome calculation complete
output reg o_error_detected, // [indicate] ERROR detected
output reg o_BRAM_write_enable, // BRAM write enable
output wire [`D_SC_I_CNT_BIT-2:0] o_BRAM_write_address, // BRAM write address
output wire [`D_SC_P_LVL-1:0] o_BRAM_write_data, // BRAM write data
output reg [11:0] o_chunk_number,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_001,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_002,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_003,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_004,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_005,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_006,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_007,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_008,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_009,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_010,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_011,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_012,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_013,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_014,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_015,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_016,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_017,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_018,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_019,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_020,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_021,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_022,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_023,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_024,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_025,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_026,
output reg [`D_SC_GF_ORDER-1:0] o_sdr_027
);
parameter SC_FSM_BIT = 8;
parameter RESET_SC = 8'b0000_0001; // RESET: syndrome calculator sequence reset
parameter SDR_STwB = 8'b0000_0010; // syndrome computation: start mode, BRAM write
parameter SDR_FBwB = 8'b0000_0100; // syndrome computation: feedback mode, BRAM write
parameter SDR_FBwoB = 8'b0000_1000; // syndrome computation: feedback mode
parameter COD_T_PwB = 8'b0001_0000; // code transmit paused, BRAM write pause
parameter COD_T_PwoB = 8'b0010_0000; // code transmit paused
parameter EVALUATION = 8'b0100_0000; // evaluation stage
parameter SDR_OUT = 8'b1000_0000; // syndrome out: finish
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_001;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_002;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_003;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_004;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_005;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_006;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_007;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_008;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_009;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_010;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_011;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_012;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_013;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_014;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_015;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_016;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_017;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_018;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_019;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_020;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_021;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_022;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_023;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_024;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_025;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_026;
wire [`D_SC_GF_ORDER-1:0] w_evaluated_remainder_027;
// registered input
reg [`D_SC_P_LVL-1:0] r_code_b;
reg [4:0] r_chunk_number;
// syndrome calculator FSM state
reg [SC_FSM_BIT-1:0] r_cur_state;
reg [SC_FSM_BIT-1:0] r_nxt_state;
// internal counter
reg [`D_SC_I_CNT_BIT-1:0] r_counter;
reg [2:0] r_output_counter;
// registers for remainders
reg [(`D_SC_ECC_T * `D_SC_GF_ORDER)-1:0] r_remainders;
wire [(`D_SC_ECC_T * `D_SC_GF_ORDER)-1:0] w_nxt_remainders;
// internal variable
wire w_valid_execution;
wire w_BRAM_write_cmplt; // BRAM write complete
wire w_division_cmplt; // division complete
//wire w_output_cmplt; // output complete
// generate control/indicate signal
assign o_sc_available = (r_cur_state == RESET_SC);
assign w_valid_execution = (i_exe_sc) & (i_code_valid);
assign o_sc_start = (r_cur_state == SDR_STwB);
assign w_BRAM_write_cmplt = (r_counter == `D_SC_MSG_LENGTH-1);
assign o_last_c_block_rcvd = (i_code_valid == 1) & (r_counter == `D_SC_I_CNT-2);
assign w_division_cmplt = (r_counter == `D_SC_I_CNT-1);
assign o_sc_cmplt = (r_cur_state == SDR_OUT) && (i_buf_available);
//assign w_output_cmplt = (r_output_counter == 3'b111);
assign o_BRAM_write_address[`D_SC_MSG_LENGTH_BIT-1:0] = r_counter[`D_SC_MSG_LENGTH_BIT-1:0]; // use partial bit
assign o_BRAM_write_data[`D_SC_P_LVL-1:0] = r_code_b[`D_SC_P_LVL-1:0];
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET) || (i_stop_dec)) begin
r_cur_state <= RESET_SC;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
RESET_SC: begin
r_nxt_state <= (w_valid_execution)? (SDR_STwB):(RESET_SC);
end
SDR_STwB: begin
r_nxt_state <= (i_code_valid)? (SDR_FBwB):(COD_T_PwB);
end
SDR_FBwB: begin
r_nxt_state <= (i_code_valid)? ((w_BRAM_write_cmplt)? (SDR_FBwoB):(SDR_FBwB)):
((w_BRAM_write_cmplt)? (COD_T_PwoB):(COD_T_PwB));
end
SDR_FBwoB: begin
r_nxt_state <= (w_division_cmplt)? (EVALUATION):
((i_code_valid)? (SDR_FBwoB):(COD_T_PwoB));
end
COD_T_PwB: begin
r_nxt_state <= (i_code_valid)? (SDR_FBwB):(COD_T_PwB);
end
COD_T_PwoB: begin
r_nxt_state <= (i_code_valid)? (SDR_FBwoB):(COD_T_PwoB);
end
EVALUATION: begin
r_nxt_state <= SDR_OUT;
end
SDR_OUT: begin
r_nxt_state <= (i_buf_available)? (RESET_SC):(SDR_OUT);
end
default: begin
r_nxt_state <= RESET_SC;
end
endcase
end
always @ (posedge i_clk)
begin
if (i_RESET)
o_code_ready <= 1;
else
case (r_nxt_state)
RESET_SC:
o_code_ready <= 1;
SDR_FBwoB:
o_code_ready <= (o_last_c_block_rcvd) ? 0 : 1;
default:
o_code_ready <= o_code_ready;
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if (i_RESET || i_stop_dec) begin
r_code_b <= 0;
r_remainders <= 0;
r_counter <= 0;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
else begin
case (r_nxt_state)
RESET_SC: begin
r_code_b <= 0;
r_remainders <= 0;
r_counter <= 0;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
SDR_STwB: begin
r_code_b <= i_code;
r_remainders <= 0;
r_counter <= 0;
o_BRAM_write_enable <= 1;
r_output_counter <= 0;
end
SDR_FBwB: begin
r_code_b <= i_code;
r_remainders <= w_nxt_remainders;
r_counter <= r_counter + 1'b1;
o_BRAM_write_enable <= 1;
r_output_counter <= 0;
end
SDR_FBwoB: begin
r_code_b <= i_code;
r_remainders <= w_nxt_remainders;
r_counter <= r_counter + 1'b1;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
COD_T_PwB: begin
r_code_b <= r_code_b;
r_remainders <= r_remainders;
r_counter <= r_counter;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
COD_T_PwoB: begin
r_code_b <= r_code_b;
r_remainders <= r_remainders;
r_counter <= r_counter;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
EVALUATION: begin
r_code_b <= 0;
r_remainders <= w_nxt_remainders;
r_counter <= 0;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
SDR_OUT: begin
r_code_b <= 0;
r_remainders <= r_remainders;
r_counter <= 0;
o_BRAM_write_enable <= 0;
r_output_counter <= r_output_counter + 1'b1;
end
default: begin
r_code_b <= 0;
r_remainders <= 0;
r_counter <= 0;
o_BRAM_write_enable <= 0;
r_output_counter <= 0;
end
endcase
end
end
always @ (posedge i_clk)
begin
if (i_RESET || i_stop_dec)
r_chunk_number <= 0;
else begin
case (r_nxt_state)
RESET_SC:
r_chunk_number <= 0;
SDR_STwB:
r_chunk_number <= i_chunk_number;
default:
r_chunk_number <= r_chunk_number;
endcase
end
end
always @ (posedge i_clk)
begin
if (i_RESET || i_stop_dec) begin
o_error_detected <= 0;
o_chunk_number <= 0;
o_sdr_001 <= 0;
o_sdr_002 <= 0;
o_sdr_003 <= 0;
o_sdr_004 <= 0;
o_sdr_005 <= 0;
o_sdr_006 <= 0;
o_sdr_007 <= 0;
o_sdr_008 <= 0;
o_sdr_009 <= 0;
o_sdr_010 <= 0;
o_sdr_011 <= 0;
o_sdr_012 <= 0;
o_sdr_013 <= 0;
o_sdr_014 <= 0;
o_sdr_015 <= 0;
o_sdr_016 <= 0;
o_sdr_017 <= 0;
o_sdr_018 <= 0;
o_sdr_019 <= 0;
o_sdr_020 <= 0;
o_sdr_021 <= 0;
o_sdr_022 <= 0;
o_sdr_023 <= 0;
o_sdr_024 <= 0;
o_sdr_025 <= 0;
o_sdr_026 <= 0;
o_sdr_027 <= 0;
end
else begin
case (r_nxt_state)
SDR_OUT: begin
o_error_detected <= (|w_evaluated_remainder_001) | (|w_evaluated_remainder_003) | (|w_evaluated_remainder_005) | (|w_evaluated_remainder_007) | (|w_evaluated_remainder_009) | (|w_evaluated_remainder_011) | (|w_evaluated_remainder_013) | (|w_evaluated_remainder_015) | (|w_evaluated_remainder_017) | (|w_evaluated_remainder_019) | (|w_evaluated_remainder_021) | (|w_evaluated_remainder_023) | (|w_evaluated_remainder_025) | (|w_evaluated_remainder_027);
o_chunk_number <= r_chunk_number;
o_sdr_001 <= w_evaluated_remainder_001;
o_sdr_002 <= w_evaluated_remainder_002;
o_sdr_003 <= w_evaluated_remainder_003;
o_sdr_004 <= w_evaluated_remainder_004;
o_sdr_005 <= w_evaluated_remainder_005;
o_sdr_006 <= w_evaluated_remainder_006;
o_sdr_007 <= w_evaluated_remainder_007;
o_sdr_008 <= w_evaluated_remainder_008;
o_sdr_009 <= w_evaluated_remainder_009;
o_sdr_010 <= w_evaluated_remainder_010;
o_sdr_011 <= w_evaluated_remainder_011;
o_sdr_012 <= w_evaluated_remainder_012;
o_sdr_013 <= w_evaluated_remainder_013;
o_sdr_014 <= w_evaluated_remainder_014;
o_sdr_015 <= w_evaluated_remainder_015;
o_sdr_016 <= w_evaluated_remainder_016;
o_sdr_017 <= w_evaluated_remainder_017;
o_sdr_018 <= w_evaluated_remainder_018;
o_sdr_019 <= w_evaluated_remainder_019;
o_sdr_020 <= w_evaluated_remainder_020;
o_sdr_021 <= w_evaluated_remainder_021;
o_sdr_022 <= w_evaluated_remainder_022;
o_sdr_023 <= w_evaluated_remainder_023;
o_sdr_024 <= w_evaluated_remainder_024;
o_sdr_025 <= w_evaluated_remainder_025;
o_sdr_026 <= w_evaluated_remainder_026;
o_sdr_027 <= w_evaluated_remainder_027;
end
default: begin
o_error_detected <= 0;
o_chunk_number <= 0;
o_sdr_001 <= 0;
o_sdr_002 <= 0;
o_sdr_003 <= 0;
o_sdr_004 <= 0;
o_sdr_005 <= 0;
o_sdr_006 <= 0;
o_sdr_007 <= 0;
o_sdr_008 <= 0;
o_sdr_009 <= 0;
o_sdr_010 <= 0;
o_sdr_011 <= 0;
o_sdr_012 <= 0;
o_sdr_013 <= 0;
o_sdr_014 <= 0;
o_sdr_015 <= 0;
o_sdr_016 <= 0;
o_sdr_017 <= 0;
o_sdr_018 <= 0;
o_sdr_019 <= 0;
o_sdr_020 <= 0;
o_sdr_021 <= 0;
o_sdr_022 <= 0;
o_sdr_023 <= 0;
o_sdr_024 <= 0;
o_sdr_025 <= 0;
o_sdr_026 <= 0;
o_sdr_027 <= 0;
end
endcase
end
end
d_SC_parallel_lfs_XOR_001 d_SC_LFSXOR_matrix_001(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]));
d_SC_parallel_lfs_XOR_003 d_SC_LFSXOR_matrix_003(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(1+1)-1:`D_SC_GF_ORDER*1]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(1+1)-1:`D_SC_GF_ORDER*1]));
d_SC_parallel_lfs_XOR_005 d_SC_LFSXOR_matrix_005(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(2+1)-1:`D_SC_GF_ORDER*2]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(2+1)-1:`D_SC_GF_ORDER*2]));
d_SC_parallel_lfs_XOR_007 d_SC_LFSXOR_matrix_007(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(3+1)-1:`D_SC_GF_ORDER*3]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(3+1)-1:`D_SC_GF_ORDER*3]));
d_SC_parallel_lfs_XOR_009 d_SC_LFSXOR_matrix_009(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(4+1)-1:`D_SC_GF_ORDER*4]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(4+1)-1:`D_SC_GF_ORDER*4]));
d_SC_parallel_lfs_XOR_011 d_SC_LFSXOR_matrix_011(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(5+1)-1:`D_SC_GF_ORDER*5]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(5+1)-1:`D_SC_GF_ORDER*5]));
d_SC_parallel_lfs_XOR_013 d_SC_LFSXOR_matrix_013(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(6+1)-1:`D_SC_GF_ORDER*6]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(6+1)-1:`D_SC_GF_ORDER*6]));
d_SC_parallel_lfs_XOR_015 d_SC_LFSXOR_matrix_015(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(7+1)-1:`D_SC_GF_ORDER*7]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(7+1)-1:`D_SC_GF_ORDER*7]));
d_SC_parallel_lfs_XOR_017 d_SC_LFSXOR_matrix_017(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(8+1)-1:`D_SC_GF_ORDER*8]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(8+1)-1:`D_SC_GF_ORDER*8]));
d_SC_parallel_lfs_XOR_019 d_SC_LFSXOR_matrix_019(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(9+1)-1:`D_SC_GF_ORDER*9]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(9+1)-1:`D_SC_GF_ORDER*9]));
d_SC_parallel_lfs_XOR_021 d_SC_LFSXOR_matrix_021(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(10+1)-1:`D_SC_GF_ORDER*10]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(10+1)-1:`D_SC_GF_ORDER*10]));
d_SC_parallel_lfs_XOR_023 d_SC_LFSXOR_matrix_023(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(11+1)-1:`D_SC_GF_ORDER*11]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(11+1)-1:`D_SC_GF_ORDER*11]));
d_SC_parallel_lfs_XOR_025 d_SC_LFSXOR_matrix_025(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(12+1)-1:`D_SC_GF_ORDER*12]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(12+1)-1:`D_SC_GF_ORDER*12]));
d_SC_parallel_lfs_XOR_027 d_SC_LFSXOR_matrix_027(
.i_message(r_code_b),
.i_cur_remainder(r_remainders[`D_SC_GF_ORDER*(13+1)-1:`D_SC_GF_ORDER*13]),
.o_nxt_remainder(w_nxt_remainders[`D_SC_GF_ORDER*(13+1)-1:`D_SC_GF_ORDER*13]));
d_SC_evaluation_matrix_001 d_SC_EM_001 (
.i_in(r_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]),
.o_out(w_evaluated_remainder_001) );
d_SC_evaluation_matrix_002 d_SC_EM_002 (
.i_in(r_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]),
.o_out(w_evaluated_remainder_002) );
d_SC_evaluation_matrix_003 d_SC_EM_003 (
.i_in(r_remainders[`D_SC_GF_ORDER*(1+1)-1:`D_SC_GF_ORDER*1]),
.o_out(w_evaluated_remainder_003) );
d_SC_evaluation_matrix_004 d_SC_EM_004 (
.i_in(r_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]),
.o_out(w_evaluated_remainder_004) );
d_SC_evaluation_matrix_005 d_SC_EM_005 (
.i_in(r_remainders[`D_SC_GF_ORDER*(2+1)-1:`D_SC_GF_ORDER*2]),
.o_out(w_evaluated_remainder_005) );
d_SC_evaluation_matrix_006 d_SC_EM_006 (
.i_in(r_remainders[`D_SC_GF_ORDER*(1+1)-1:`D_SC_GF_ORDER*1]),
.o_out(w_evaluated_remainder_006) );
d_SC_evaluation_matrix_007 d_SC_EM_007 (
.i_in(r_remainders[`D_SC_GF_ORDER*(3+1)-1:`D_SC_GF_ORDER*3]),
.o_out(w_evaluated_remainder_007) );
d_SC_evaluation_matrix_008 d_SC_EM_008 (
.i_in(r_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]),
.o_out(w_evaluated_remainder_008) );
d_SC_evaluation_matrix_009 d_SC_EM_009 (
.i_in(r_remainders[`D_SC_GF_ORDER*(4+1)-1:`D_SC_GF_ORDER*4]),
.o_out(w_evaluated_remainder_009) );
d_SC_evaluation_matrix_010 d_SC_EM_010 (
.i_in(r_remainders[`D_SC_GF_ORDER*(2+1)-1:`D_SC_GF_ORDER*2]),
.o_out(w_evaluated_remainder_010) );
d_SC_evaluation_matrix_011 d_SC_EM_011 (
.i_in(r_remainders[`D_SC_GF_ORDER*(5+1)-1:`D_SC_GF_ORDER*5]),
.o_out(w_evaluated_remainder_011) );
d_SC_evaluation_matrix_012 d_SC_EM_012 (
.i_in(r_remainders[`D_SC_GF_ORDER*(1+1)-1:`D_SC_GF_ORDER*1]),
.o_out(w_evaluated_remainder_012) );
d_SC_evaluation_matrix_013 d_SC_EM_013 (
.i_in(r_remainders[`D_SC_GF_ORDER*(6+1)-1:`D_SC_GF_ORDER*6]),
.o_out(w_evaluated_remainder_013) );
d_SC_evaluation_matrix_014 d_SC_EM_014 (
.i_in(r_remainders[`D_SC_GF_ORDER*(3+1)-1:`D_SC_GF_ORDER*3]),
.o_out(w_evaluated_remainder_014) );
d_SC_evaluation_matrix_015 d_SC_EM_015 (
.i_in(r_remainders[`D_SC_GF_ORDER*(7+1)-1:`D_SC_GF_ORDER*7]),
.o_out(w_evaluated_remainder_015) );
d_SC_evaluation_matrix_016 d_SC_EM_016 (
.i_in(r_remainders[`D_SC_GF_ORDER*(0+1)-1:`D_SC_GF_ORDER*0]),
.o_out(w_evaluated_remainder_016) );
d_SC_evaluation_matrix_017 d_SC_EM_017 (
.i_in(r_remainders[`D_SC_GF_ORDER*(8+1)-1:`D_SC_GF_ORDER*8]),
.o_out(w_evaluated_remainder_017) );
d_SC_evaluation_matrix_018 d_SC_EM_018 (
.i_in(r_remainders[`D_SC_GF_ORDER*(4+1)-1:`D_SC_GF_ORDER*4]),
.o_out(w_evaluated_remainder_018) );
d_SC_evaluation_matrix_019 d_SC_EM_019 (
.i_in(r_remainders[`D_SC_GF_ORDER*(9+1)-1:`D_SC_GF_ORDER*9]),
.o_out(w_evaluated_remainder_019) );
d_SC_evaluation_matrix_020 d_SC_EM_020 (
.i_in(r_remainders[`D_SC_GF_ORDER*(2+1)-1:`D_SC_GF_ORDER*2]),
.o_out(w_evaluated_remainder_020) );
d_SC_evaluation_matrix_021 d_SC_EM_021 (
.i_in(r_remainders[`D_SC_GF_ORDER*(10+1)-1:`D_SC_GF_ORDER*10]),
.o_out(w_evaluated_remainder_021) );
d_SC_evaluation_matrix_022 d_SC_EM_022 (
.i_in(r_remainders[`D_SC_GF_ORDER*(5+1)-1:`D_SC_GF_ORDER*5]),
.o_out(w_evaluated_remainder_022) );
d_SC_evaluation_matrix_023 d_SC_EM_023 (
.i_in(r_remainders[`D_SC_GF_ORDER*(11+1)-1:`D_SC_GF_ORDER*11]),
.o_out(w_evaluated_remainder_023) );
d_SC_evaluation_matrix_024 d_SC_EM_024 (
.i_in(r_remainders[`D_SC_GF_ORDER*(1+1)-1:`D_SC_GF_ORDER*1]),
.o_out(w_evaluated_remainder_024) );
d_SC_evaluation_matrix_025 d_SC_EM_025 (
.i_in(r_remainders[`D_SC_GF_ORDER*(12+1)-1:`D_SC_GF_ORDER*12]),
.o_out(w_evaluated_remainder_025) );
d_SC_evaluation_matrix_026 d_SC_EM_026 (
.i_in(r_remainders[`D_SC_GF_ORDER*(6+1)-1:`D_SC_GF_ORDER*6]),
.o_out(w_evaluated_remainder_026) );
d_SC_evaluation_matrix_027 d_SC_EM_027 (
.i_in(r_remainders[`D_SC_GF_ORDER*(13+1)-1:`D_SC_GF_ORDER*13]),
.o_out(w_evaluated_remainder_027) );
endmodule
|
`default_nettype none
module rom1ktest (
input wire sysclk,
input wire clk,
input wire rst,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
wire [15:0] dout;
reg [9:0] addr;
//-- Instanciar la memoria rom
rom1K16
ROM (
.clk(sysclk),
.addr(addr),
.data(dout)
);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(clk),
.D_IN_0(clk2)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(rst),
.D_IN_0(rst2)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign rst_in = ~rst2;
assign sw = ~clk2;
//-- switch button debounced
wire sw_deb;
wire clk_pres;
debounce deb1 (
.clk(sysclk),
.sw_in(sw),
.sw_out(sw_deb)
);
prescaler #(
.N(24)
) pres1 (
.clk_in(sysclk),
.ena(~sw_deb),
.clk_out(clk_pres)
);
assign clk_in = sw_deb | clk_pres;
//-- Counter for incrementing the address
always @(posedge clk_in or posedge rst_in) begin
if (rst_in==1'b1)
addr <= 10'b0;
else
addr <= addr + 1;
end
assign {d7,d6,d5,d4,d3,d2,d1,d0} = dout[15:8];
endmodule
module rom1K16 (input clk,
input wire [9:0] addr,
output reg [15:0] data);
//-- Name of the file with the rom contents
parameter ROMFILE = "rom-08.list";
//-- Memoria
reg [15:0] rom [0:1023];
always @(negedge clk) begin
data <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
module test;
initial begin
$display("Error: \"FloatTest.bsv\", line 234, column 24: (R0001)\n Mutually exclusive rules (from the ME sets [RL_action_l234c24] and\n [RL_action_l235c24, RL_action_l236c24, RL_action_l237c24, RL_action_l238c24,\n RL_action_l239c24, RL_action_l240c24, RL_action_l241c24, RL_action_l242c24,\n RL_action_l243c24, RL_action_l244c24, RL_action_l245c24, RL_action_l246c24,\n RL_action_l247c24, RL_action_l248c24, RL_action_l249c24, RL_action_l250c24,\n RL_action_l251c24, RL_action_l252c24, RL_action_l253c24, RL_action_l255c24,\n RL_action_l256c24, RL_action_l257c24, RL_action_l258c24, RL_action_l259c24,\n RL_action_l260c24, RL_action_l261c24, RL_action_l262c24, RL_action_l263c24,\n RL_action_l264c24, RL_action_l265c24, RL_action_l266c24, RL_action_l267c24,\n RL_action_l268c24, RL_action_l269c24, RL_action_l270c24, RL_action_l271c24,\n RL_action_l272c24, RL_action_l273c24, RL_action_l274c24, RL_action_l276c24,\n RL_action_l277c24, RL_action_l278c24, RL_action_l279c24, RL_action_l280c24,\n RL_action_l281c24, RL_action_l282c24, RL_action_l283c24, RL_action_l284c24,\n RL_action_l285c24, RL_action_l286c24, RL_action_l287c24, RL_action_l288c24,\n RL_action_l289c24, RL_action_l290c24, RL_action_l291c24, RL_action_l292c24,\n RL_action_l293c24, RL_action_l294c24, RL_action_l295c24, RL_action_l297c24,\n RL_action_l298c24, RL_action_l299c24, RL_action_l300c24, RL_action_l301c24,\n RL_action_l302c24, RL_action_l303c24, RL_action_l304c24, RL_action_l305c24,\n RL_action_l306c24, RL_action_l307c24, RL_action_l308c24, RL_action_l309c24,\n RL_action_l310c24, RL_action_l311c24, RL_action_l312c24, RL_action_l313c24,\n RL_action_l314c24, RL_action_l315c24, RL_action_l316c24, RL_action_l318c24,\n RL_action_l319c24, RL_action_l320c24, RL_action_l321c24, RL_action_l322c24,\n RL_action_l323c24, RL_action_l324c24, RL_action_l326c24, RL_action_l327c24,\n RL_action_l328c24, RL_action_l329c24, RL_action_l330c24, RL_action_l331c24,\n RL_action_l332c24, RL_action_l333c24, RL_action_l334c24, RL_action_l335c24,\n RL_action_l336c24, RL_action_l337c24, RL_action_l338c24, RL_action_l339c24,\n RL_action_l340c24, RL_action_l341c24, RL_action_l342c24, RL_action_l343c24,\n RL_action_l344c24, RL_action_l345c24, RL_action_l348c18, RL_action_l353c22,\n RL_action_l354c22, RL_action_l355c22, RL_action_l356c22, RL_action_l357c22,\n RL_action_l358c22, RL_action_l359c22, RL_action_l360c22, RL_action_l361c22,\n RL_action_l362c22, RL_action_l363c22, RL_action_l364c22, RL_action_l365c22,\n RL_action_l366c22, RL_action_l367c22, RL_action_l368c22, RL_action_l369c22,\n RL_action_l370c22, RL_action_l371c22, RL_action_l372c22, RL_action_l374c22,\n RL_action_l376c22, RL_action_l377c22, RL_action_l378c22, RL_action_l379c22,\n RL_action_l381c22, RL_action_l383c22, RL_action_l384c22, RL_action_l386c22,\n RL_action_l387c22, RL_action_l390c18, RL_action_l395c23, RL_action_l396c23,\n RL_action_l398c23, RL_action_l399c23, RL_action_l400c23, RL_action_l401c23,\n RL_action_l402c23, RL_action_l403c23, RL_action_l404c23, RL_action_l405c23,\n RL_action_l406c23, RL_action_l407c23, RL_action_l408c23, RL_action_l409c23,\n RL_action_l410c23, RL_action_l411c23, RL_action_l412c23, RL_action_l413c23,\n RL_action_l414c23, RL_action_l415c23, RL_action_l416c23, RL_action_l417c23,\n RL_action_l419c23, RL_action_l420c23, RL_action_l421c23, RL_action_l422c23,\n RL_action_l423c23, RL_action_l424c23, RL_action_l425c23, RL_action_l426c23,\n RL_action_l427c23, RL_action_l428c23, RL_action_l429c23, RL_action_l430c23,\n RL_action_l431c23, RL_action_l432c23, RL_action_l433c23, RL_action_l434c23,\n RL_action_l435c23, RL_action_l436c23, RL_action_l437c23, RL_action_l438c23,\n RL_action_l441c18, RL_action_l446c28, RL_action_l447c28, RL_action_l448c28,\n RL_action_l449c28, RL_action_l450c28, RL_action_l451c28, RL_action_l452c28,\n RL_action_l453c28, RL_action_l455c28, RL_action_l456c28, RL_action_l457c28,\n RL_action_l458c28, RL_action_l459c28, RL_action_l460c28, RL_action_l461c28,\n RL_action_l462c28, RL_action_l463c28, RL_action_l464c28, RL_action_l465c28,\n RL_action_l466c28, RL_action_l467c28, RL_action_l468c28, RL_action_l469c28,\n RL_action_l470c28, RL_action_l471c28, RL_action_l472c28, RL_action_l473c28,\n RL_action_l474c28, RL_action_l475c28, RL_action_l476c28, RL_action_l478c28,\n RL_action_l479c28, RL_action_l481c28, RL_action_l484c18, RL_action_l489c21,\n RL_action_l490c21, RL_action_l491c21, RL_action_l492c21, RL_action_l493c21,\n RL_action_l494c21, RL_action_l495c21, RL_action_l496c21, RL_action_l497c21,\n RL_action_l498c21, RL_action_l499c21, RL_action_l500c21, RL_action_l501c21,\n RL_action_l502c21, RL_action_l503c21, RL_action_l504c21, RL_action_l505c21,\n RL_action_l506c21, RL_action_l507c21, RL_action_l508c21, RL_action_l509c21,\n RL_action_l510c21, RL_action_l512c21, RL_action_l513c21, RL_action_l514c21,\n RL_action_l515c21, RL_action_l516c21, RL_action_l517c21, RL_action_l518c21,\n RL_action_l519c21, RL_action_l520c21, RL_action_l521c21, RL_action_l522c21,\n RL_action_l523c21, RL_action_l524c21, RL_action_l525c21, RL_action_l526c21,\n RL_action_l527c21, RL_action_l528c21, RL_action_l529c21, RL_action_l530c21,\n RL_action_l531c21, RL_action_l533c26, RL_action_l534c26, RL_action_l535c26,\n RL_action_l536c26, RL_action_l537c26, RL_action_l538c26, RL_action_l539c26,\n RL_action_l540c26, RL_action_l542c26, RL_action_l543c26, RL_action_l544c26,\n RL_action_l545c26, RL_action_l546c26, RL_action_l547c26, RL_action_l548c26,\n RL_action_l549c26, RL_action_l550c26, RL_action_l551c26, RL_action_l552c26,\n RL_action_l553c26, RL_action_l554c26, RL_action_l555c26, RL_action_l556c26,\n RL_action_l557c26, RL_action_l558c26, RL_action_l559c26, RL_action_l560c26,\n RL_action_l561c26, RL_action_l562c26, RL_action_l563c26, RL_action_l565c26,\n RL_action_l566c26, RL_action_l568c26, RL_action_l570c21, RL_action_l572c21,\n RL_action_l574c26, RL_action_l576c26, RL_action_l577c26, RL_action_l579c26,\n RL_action_l582c18, RL_action_l587c28, RL_action_l588c28, RL_action_l589c28,\n RL_action_l590c28, RL_action_l591c28, RL_action_l592c28, RL_action_l593c28,\n RL_action_l594c28, RL_action_l595c28, RL_action_l596c28, RL_action_l597c28,\n RL_action_l598c28, RL_action_l599c28, RL_action_l600c28, RL_action_l601c28,\n RL_action_l602c28, RL_action_l603c28, RL_action_l604c28, RL_action_l605c28,\n RL_action_l606c28, RL_action_l607c28, RL_action_l609c28, RL_action_l610c28,\n RL_action_l611c28, RL_action_l613c28, RL_action_l614c28, RL_action_l615c28,\n RL_action_l616c28, RL_action_l617c28, RL_action_l618c28, RL_action_l619c28,\n RL_action_l621c28, RL_action_l622c28, RL_action_l623c28, RL_action_l624c28,\n RL_action_l625c28, RL_action_l626c28, RL_action_l627c28, RL_action_l628c28,\n RL_action_l629c28, RL_action_l630c28, RL_action_l631c28, RL_action_l632c28,\n RL_action_l633c28, RL_action_l634c28, RL_action_l635c28, RL_action_l636c28,\n RL_action_l637c28, RL_action_l638c28, RL_action_l639c28, RL_action_l645c18,\n RL_action_l647c7] ) fired in the same clock cycle.\nPASSED");
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Tue Sep 16 21:34:47 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule
|
`timescale 1ns / 1ps
module NaN_mod_64
(
input wire [1:0] operation,
input wire [63:0] data1,
input wire [63:0] data2,
output reg NaN_flag
);
always @*
begin
case(operation)
2'b00:
begin
if((data1 == 64'h7ff0000000000000) && (data2 == 64'h7ff0000000000000))
NaN_flag = 1'b1;
else if((data1 == 64'hfff0000000000000) && (data2 == 64'hfff0000000000000))
NaN_flag = 1'b1;
else if((data1 == 64'h7ff0000000000000) && (data2 == 64'hfff0000000000000))
NaN_flag = 1'b1;
else if((data1 == 64'hfff0000000000000) && (data2 == 64'h7ff0000000000000))
NaN_flag = 1'b1;
else
NaN_flag = 1'b0;
end
2'b01:
begin
if(data1 == 64'h7ff0000000000000)
NaN_flag = 1'b1;
else if(data1 == 64'hfff0000000000000)
NaN_flag = 1'b1;
else
NaN_flag = 1'b0;
end
2'b10:
begin
if((data1 == 64'h0000000000000000) && (data2 == 64'h7ff0000000000000))
NaN_flag = 1'b1;
else if((data1 == 64'h0000000000000000) && (data2 == 64'hfff0000000000000))
NaN_flag = 1'b1;
else if((data1 == 64'hfff0000000000000) && (data2 == 64'h0000000000000000))
NaN_flag = 1'b1;
else if((data1 == 64'h7ff0000000000000) && (data2 == 64'h0000000000000000))
NaN_flag = 1'b1;
else
NaN_flag = 1'b0;
end
default:
NaN_flag = 1'b0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFRTP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BLACKBOX_V
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:46:27 02/23/2009
// Design Name:
// Module Name: MSG_utils
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//module inst_TX_MSG ( CLK,
// CLKDIV,
// DATA_IN,
// OSER_OQ,
// RST,
// CLKWR,
// WREN,
// CON_P, //input feedback from decode module
// CON_N,
// BACK_WRONG, //feedback output to internal module
// BACK_RIGHT,
// ALMOSTFULL,
// EMPTY);
module RCB_FRL_TX_MSG (
CLK,
CLKDIV,
DATA_IN,
OSER_OQ,
RST,
CLKWR,
WREN,
CON_P,
CON_N,
BACK_WRONG,
BACK_RIGHT,
ALMOSTFULL,
EMPTY,
probe,
EN_SIG,
RE_SIG,
TRAINING_DONE
);
input CLK, CLKDIV, RST, CLKWR, WREN, CON_P, CON_N, TRAINING_DONE;
input [39:0] DATA_IN;
output probe;
input RE_SIG, EN_SIG;
output OSER_OQ;
output BACK_WRONG, BACK_RIGHT, ALMOSTFULL;
output EMPTY;
reg [7:0] input_reg;
wire [39:0] fifo_DO;
wire ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL;
wire EMPTY_fifo; // Added by Jiansong, 2010-5-27
wire RDEN;
reg [8:0] count;
parameter NUM = 8'h06;
reg RDEN_REG;
RCB_FRL_fifo_MSG RCB_FRL_fifo_MSG_inst (
.ALMOSTEMPTY(ALMOSTEMPTY),
.ALMOSTFULL(ALMOSTFULL),
.DO(fifo_DO),
// .EMPTY(EMPTY),
.EMPTY(EMPTY_fifo), // modified by Jiansong, 2010-5-27
.FULL(FULL),
.DI(DATA_IN),
.RDCLK(CLKDIV),
.RDEN(RDEN_REG),
.WRCLK(CLKWR),
.WREN(WREN),
.RST(RST)
);
//assign EMPTY = 0; //xt
wire [7:0] CRC;
RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst ( .D({{NUM},{fifo_DO}}), .NewCRC(CRC));
// Added by Jiansong, 2010-5-27, do not send out control message in training stage
assign EMPTY = EMPTY_fifo | (~TRAINING_DONE);
reg [3:0] times;
reg BACK_WRONG, BACK_RIGHT;
assign probe = RDEN_REG;
always @ (posedge CLKDIV) begin
if (RST == 1'b1) begin
count <= 9'h000;
RDEN_REG <= 1'b0;
times <= 4'h0;
end
else begin
if (count == 9'h1FF | count == 9'h1FE)
begin
count <= 9'h000;
end
else if (count == 9'h000) begin
if ( EN_SIG == 1'b1) // Jiansong: ACK first
begin
count <= 9'h1FF;
end
else if (RE_SIG == 1'b1)
begin
count <= 9'h1FE;
end
else
begin
if (EMPTY == 1'b1 & times == 4'h0) begin
count <= 9'h000;
end
else if (EMPTY == 1'b0) begin
count <= 9'h001;
RDEN_REG <= 1'b0;
end
else if (times == 4'h1 | times ==4'h2) begin
count <= 9'h001;
RDEN_REG <= 1'b0;
end
else if (times == 4'h3) begin
times <= 1'b0;
RDEN_REG <= 1'b0;
end
end
BACK_WRONG <= 1'b0;
BACK_RIGHT <= 1'b0;
end
else if (count == 9'h001) begin
if (times == 4'h0) begin
RDEN_REG <= 1'b1;
end
times <= times + 4'h1;
count <= 9'h002;
BACK_WRONG <= 1'b0;
BACK_RIGHT <= 1'b0;
end
else if (count == 9'h002) begin
RDEN_REG <= 1'b0;
count <= 9'h003;
end
//else if (count == (NUM+8'h03) ) begin
else if ( CON_P == 1'b1) begin
// if (EMPTY == 1'b0) begin
// count <= 9'h001;
// end
// else begin
count <= 9'h000;
// end
times <= 4'h0;
BACK_RIGHT <= 1'b1;
end
else if (times == 4'h3 & count == 9'h150) begin
// if (EMPTY == 1'b0) begin
// count <= 9'h001;
// end
// else begin
count <= 9'h000;
// end
times <= 4'h0;
BACK_WRONG <= 1'b1;
end
else if ( CON_N == 1'b1 | count == 9'h150) begin
count <= 9'h000;
end
else begin
count <= count + 9'h001;
end
end
end
reg [8:0] data_counter;
always @ (negedge CLKDIV) begin
if ( RST == 1'b1 ) begin
input_reg[7:0] <= 8'h00;
data_counter <= 8'h00;
end
else if (count == 9'h001) begin
input_reg[7:0] <= 8'hF5;
end
else if (count == 9'h002) begin
input_reg[7:0] <= NUM;
end
else if (count == 9'h000) begin
input_reg[7:0] <= 8'h44; // modified by zjs, 2009-3-8, send 8'h44 on idle state to train LVDS receiver
end
else if (count == 9'h003) begin
input_reg[7:0] <= fifo_DO[39:32];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h004) begin
input_reg[7:0] <= fifo_DO[31:24];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h005) begin
input_reg[7:0] <= fifo_DO[23:16];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h006) begin
input_reg[7:0] <= fifo_DO[15:8];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h007) begin
input_reg[7:0] <= fifo_DO[7:0];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h008) begin
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
input_reg[7:0] <= CRC[7:0];
//input_reg[7:0] = 8'h02;
end
else if (count == 9'h1FF) begin
input_reg[7:0] <= 8'h5f;
end
else if (count == 9'h1FE) begin
input_reg[7:0] <= 8'haf;
end
else begin
input_reg[7:0] <= 8'h00;
end
end
/*
wire CE;
assign CE = 1'b1;
wire [9:0] OUTPUT_REG;
encode_8b10b_lut_base inst_encode_8b10b_lut_base_CMD(
.DIN(input_reg[7:0]),
.KIN(),
.CLK(CLKDIV), // : IN STD_LOGIC :='0' ;
.DOUT(OUTPUT_REG[9:0]), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) :=
// str_to_slv(C_FORCE_CODE_VAL, 10) ;
.CE(CE), // : IN STD_LOGIC :='0' ;
.FORCE_CODE(), // : IN STD_LOGIC :='0' ;
.FORCE_DISP(), // : IN STD_LOGIC :='0' ;
.DISP_IN(), // : IN STD_LOGIC :='0' ;
.DISP_OUT(), // : OUT STD_LOGIC :=
// bint_2_sl(C_FORCE_CODE_DISP);
.KERR(), // : OUT STD_LOGIC :='0' ;
.ND() // : OUT STD_LOGIC :='0'
);
*/
wire [7:0] PATTERN;
RCB_FRL_TrainingPattern RCB_FRL_TrainingPattern_inst(
.CLK(CLKDIV),
.RST(RST),
.DATA_OUT(PATTERN));
wire [7:0] input_reg_inv;
assign input_reg_inv = TRAINING_DONE ? input_reg : PATTERN;
//assign input_reg_inv = PATTERN;
//inst_OSERDES_MSG inst_OSERDES1 (.OQ(OSER_OQ), .CLK(CLK), .CLKDIV(CLKDIV), .DI(input_reg_inv), .OCE(1'b1), .SR(RST));
RCB_FRL_OSERDES_MSG RCB_FRL_OSERDES_MSG_inst (
.OQ(OSER_OQ), .CLK(CLK), .CLKDIV(CLKDIV), .DI(input_reg_inv), .OCE(1'b1), .SR(RST));
endmodule
|
module crc
#(parameter BITS=8, parameter POLY=7, parameter INIT=0)
(input wire i_clk, input wire i_rst, input wire i_stb, input wire i_bit, output wire[BITS-1:0] o_crc);
//
// Сдвиговый регистр контрольной суммы.
reg[BITS-1:0] crcreg;
// Провода между регистрами.
wire[BITS-1:0] crcwires;
// Выходное значение CRC.
assign o_crc = crcreg;
initial begin
crcreg <= INIT[BITS-1:0];
end
// Выбор режима сдвига - с XOR или без.
assign sel = crcreg[BITS-1] ^ i_bit;
// Нулевой провод.
assign crcwires[0] = POLY[0] ? sel : 0;
genvar i;
generate
for(i = 1; i < BITS; i = i + 1) begin: gen_crc_wires
assign crcwires[i] = POLY[i] ? crcreg[i - 1] ^ sel : crcreg[i - 1];
end
endgenerate
// Процесс регистра.
always @(posedge i_clk or negedge i_rst) begin
if(!i_rst) begin
crcreg <= #1 INIT[BITS-1:0];
end else begin
if(i_stb) begin
crcreg <= #1 crcwires;
end else begin
crcreg <= #1 crcreg;
end
end
end
endmodule
|
`timescale 1ns/1ps
/*
This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
behavioral Verilog constructs only.
*/
module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule
module GP_3LUT(input IN0, IN1, IN2, output OUT);
parameter [7:0] INIT = 0;
assign OUT = INIT[{IN2, IN1, IN0}];
endmodule
module GP_4LUT(
input wire IN0,
input wire IN1,
input wire IN2,
input wire IN3,
output wire OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
module GP_COUNT14(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
reg[13:0] count = COUNT_TO;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 14'h0);
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT14 not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT14");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
reg[13:0] count = COUNT_TO;
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
if(UP)
OUT <= (count == 14'h3fff);
else
OUT <= (count == 14'h0);
POUT <= count[7:0];
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT14_ADV");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
reg[7:0] count = COUNT_TO;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
if(UP)
OUT <= (count == 8'hff);
else
OUT <= (count == 8'h0);
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT8_ADV");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT8(
input wire CLK,
input wire RST,
output reg OUT,
output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
reg[7:0] count = COUNT_TO;
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 8'h0);
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT8 not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT8");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_DCMPREF(output reg[7:0]OUT);
parameter[7:0] REF_VAL = 8'h00;
initial OUT = REF_VAL;
endmodule
module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
always @(*) begin
case(SEL)
2'd00: begin
OUTA <= IN0;
OUTB <= IN3;
end
2'd01: begin
OUTA <= IN1;
OUTB <= IN2;
end
2'd02: begin
OUTA <= IN2;
OUTB <= IN1;
end
2'd03: begin
OUTA <= IN3;
OUTB <= IN0;
end
endcase
end
endmodule
module GP_DELAY(input IN, output reg OUT);
parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;
initial OUT = 0;
generate
if(GLITCH_FILTER) begin
initial begin
$display("ERROR: GP_DELAY glitch filter mode not implemented");
$finish;
end
end
//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
//Change simulation-mode delay depending on global Vdd range (how to specify this?)
always @(*) begin
case(DELAY_STEPS)
1: #166 OUT = IN;
2: #318 OUT = IN;
2: #471 OUT = IN;
3: #622 OUT = IN;
default: begin
$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
$finish;
end
endcase
end
endgenerate
endmodule
module GP_DFF(input D, CLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK) begin
Q <= D;
end
endmodule
module GP_DFFI(input D, CLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK) begin
nQ <= ~D;
end
endmodule
module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
nQ <= 1'b1;
else
nQ <= ~D;
end
endmodule
module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b1;
else
Q <= D;
end
endmodule
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
nQ <= 1'b0;
else
nQ <= ~D;
end
endmodule
module GP_DFFSR(input D, CLK, nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= SRMODE;
else
Q <= D;
end
endmodule
module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
nQ <= ~SRMODE;
else
nQ <= ~D;
end
endmodule
module GP_DLATCH(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHI(input D, input nCLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b0;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nRST)
nQ <= 1'b1;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b1;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSET)
nQ <= 1'b0;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= SRMODE;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSR)
nQ <= ~SRMODE;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_IBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_IOBUF(input IN, input OE, output OUT, inout IO);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule
module GP_INV(input IN, output OUT);
assign OUT = ~IN;
endmodule
module GP_OBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
assign OUT = OE ? IN : 1'bz;
endmodule
module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
initial OUT = 0;
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;
localparam COUNT_MAX = PATTERN_LEN - 1'h1;
reg[3:0] count = 0;
always @(posedge CLK, negedge nRST) begin
if(!nRST)
count <= 0;
else begin
count <= count - 1'h1;
if(count == 0)
count <= COUNT_MAX;
end
end
always @(*)
OUT = PATTERN_DATA[count];
endmodule
module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0;
parameter OUTB_TAP = 1;
reg[15:0] shreg = 0;
always @(posedge CLK, negedge nRST) begin
if(!nRST)
shreg = 0;
else
shreg <= {shreg[14:0], IN};
end
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
assign OUTB = shreg[OUTB_TAP - 1];
endmodule
module GP_VDD(output OUT);
assign OUT = 1;
endmodule
module GP_VSS(output OUT);
assign OUT = 0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] inp = crc[31:0];
wire reset = (cyc < 5);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] outp; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outp (outp[31:0]),
// Inputs
.reset (reset),
.clk (clk),
.inp (inp[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, outp};
// What checksum will we end up with
`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
outp,
// Inputs
reset, clk, inp
);
input reset;
input clk;
input [31:0] inp;
output [31:0] outp;
function [31:0] no_inline_function;
input [31:0] var1;
input [31:0] var2;
/*verilator no_inline_task*/
reg [31*2:0] product1 ;
reg [31*2:0] product2 ;
integer i;
reg [31:0] tmp;
begin
product2 = {(31*2+1){1'b0}};
for (i = 0; i < 32; i = i + 1)
if (var2[i]) begin
product1 = { {31*2+1-32{1'b0}}, var1} << i;
product2 = product2 ^ product1;
end
no_inline_function = 0;
for (i= 0; i < 31; i = i + 1 )
no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i];
end
endfunction
reg [31:0] outp;
reg [31:0] inp_d;
always @( posedge clk ) begin
if( reset ) begin
outp <= 0;
end
else begin
inp_d <= inp;
outp <= no_inline_function(inp, inp_d);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKINVLP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH
// Engineer: Krzysztof Kapusta/Mateusz Furdyna
//
// Create Date: 17:11:37 11/01/2014
// Design Name: UART_memory
// Module Name: UART_memory
// Project Name: UART_memory
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 1.0
//
//
//////////////////////////////////////////////////////////////////////////////////
module UART_Tx(
input CLK,
input [7:0]D,
input WR,
input RST,
output TX,
output reg TXE = 1'b1
);
parameter CLOCK = 1_000_000;
parameter BAUD_RATE = 9_600;
localparam CLK_DIV = CLOCK/(BAUD_RATE*2);
reg [$clog2(CLK_DIV)-1:0]baud_counter = 0;
reg prev_CLK_B;
reg CLK_B = 1'b0;
reg [9:0]send_reg = 10'h3FF;
reg [3:0]counter = 0;
assign TX = send_reg[0];
// clock gen
always @ (posedge CLK) begin
prev_CLK_B <= CLK_B;
baud_counter <= baud_counter+1'b1;
if ( baud_counter == CLK_DIV-1) begin
baud_counter <=0;
CLK_B <= ~CLK_B;
end
end
// uart tx logic
always @(posedge CLK) begin
if (RST == 1'b1) begin
send_reg <= 10'h3FF;
counter <= 0;
TXE <= 1'b1;
end
else if (WR == 1'b1 && TXE) begin
send_reg <= {D, 1'b0, 1'b1};
counter <= 10;
TXE <= 1'b0;
end
else if(CLK_B == 1'b1 && prev_CLK_B == 1'b0) begin
send_reg <= {1'b1, send_reg[9:1]};
if(counter > 0) begin
counter <= counter - 1'b1;
end else begin
TXE <= 1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD0_TB_V
`define SKY130_FD_SC_LP__BUSHOLD0_TB_V
/**
* bushold0: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates internal node weak driver).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bushold0.v"
module top();
// Inputs are registered
reg RESET;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
RESET = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 RESET = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 RESET = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 RESET = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 RESET = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 RESET = 1'bx;
end
sky130_fd_sc_lp__bushold0 dut (.RESET(RESET), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD0_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_2_V
`define SKY130_FD_SC_LS__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_2_V
|
`timescale 1ns / 1ps
module CORDIC_FSM_v2
(
//Input Signals
input wire clk, // Reloj del sitema.
input wire reset, // Reset del sitema.
input wire beg_FSM_CORDIC, // Señal de inicio de la maquina de estados.
input wire ACK_FSM_CORDIC, // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
input wire operation, // Señal que determina si lo que se requiere es realizar un coseno(1´b0) o seno (1'b1).
input wire exception,
input wire [1:0] shift_region_flag, // Señal que indica si el angulo a calcular se encuentra fuera del rango de calculo del algoritmo CORDIC.
input wire [1:0] cont_var, // Señal que indica cual varible se va a calcular. Proveniente del contador de variables.
input wire ready_add_subt, // Señal proveniente del módulo de suma/resta, indica que se ha terminado la operacion y que se puede disponer del resultado de dicho modulo.
input wire max_tick_iter, min_tick_iter, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
input wire max_tick_var, min_tick_var, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
//Output Signals
output reg reset_reg_cordic,
output reg ready_CORDIC, // Señal que indica que el calculo CORDIC se ha terminado.
output reg beg_add_subt, // Señal que indica al modulo de suma/resta que inicie su operacion.
output reg ack_add_subt, // Señal que le indica al modulo de suma/resta que se ha recibido exitosamente el resultado que este entrega.
output reg sel_mux_1, sel_mux_3, // Señales de seleccion de mux, la primera escoge el canal 0 si es la primera iteracion, en otro caso escoge el canal 1, y la segunda escoge cual variable (X o Y) debe aparecer a la salida.
output reg [1:0] sel_mux_2, // Señal de seleccion de mux, que escoge entre X, Y o Z dependiendo de cual variable se deba calcular en ese momento.
output reg enab_cont_iter, load_cont_iter, // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
output reg enab_cont_var, load_cont_var, // Señales de habilitacion y carga, respectivamente, en el contador de variables.
output reg enab_RB1, enab_RB2, // Señales de habilitacion para los registros de variables de entrada y para los valores de las variables despues de los primeros mux, respectivamente.
output reg enab_d_ff_Xn, enab_d_ff_Yn, enab_d_ff_Zn, // Señales de habilitacion para los registros que guardan los resultados de cada variable en cada iteracion provenientes del modulo de suma/resta.
output reg enab_d_ff_out,enab_dff_5, // Señales de habilitacion para los registros en la salida, el primero antes del cambio de signo y el segundo es el que se encuentra en la salida.
output reg enab_RB3,
output reg enab_reg_sel_mux1,enab_reg_sel_mux2,enab_reg_sel_mux3
);
//symbolic state declaration
localparam [3:0] est0 = 4'b0000,
est1 = 4'b0001,
est2 = 4'b0010,
est3 = 4'b0011,
est4 = 4'b0100,
est5 = 4'b0101,
est6 = 4'b0110,
est7 = 4'b0111,
est8 = 4'b1000,
est9 = 4'b1001,
est10 = 4'b1010,
est11 = 4'b1011,
est12 = 4'b1100,
est13 = 4'b1101;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge reset)
begin
if(reset) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
ready_CORDIC = 1'b0;
beg_add_subt = 1'b0;
ack_add_subt = 1'b0;
sel_mux_1 = 1'b0;
sel_mux_2 = 2'b00;
sel_mux_3 = 1'b0;
enab_cont_iter = 1'b0;
load_cont_iter = 1'b0;
enab_cont_var = 1'b0;
load_cont_var = 1'b0;
enab_RB1 = 1'b0;
enab_RB2 = 1'b0;
enab_RB3 = 1'b0;
enab_d_ff_Xn = 1'b0;
enab_d_ff_Yn = 1'b0;
enab_d_ff_Zn = 1'b0;
enab_d_ff_out = 1'b0;
reset_reg_cordic = 1'b0;
enab_dff_5 = 1'b0;
enab_reg_sel_mux1 = 1'b0;
enab_reg_sel_mux2 = 1'b0;
enab_reg_sel_mux3 = 1'b0;
case(state_reg)
est0:
begin
reset_reg_cordic = 1'b1;
enab_reg_sel_mux1 = 1'b1;
enab_reg_sel_mux2 = 1'b1;
enab_reg_sel_mux3 = 1'b1;
state_next = est1;
end
est1:
begin
if(beg_FSM_CORDIC)
begin
state_next = est2;
end
else
state_next = est1;
end
est2:
begin
enab_RB1 = 1'b1;
enab_cont_iter = 1'b1;
load_cont_iter = 1'b1;
state_next = est3;
end
est3:
begin
if(min_tick_iter)
sel_mux_1 = 1'b0;
else
sel_mux_1 = 1'b1;
enab_reg_sel_mux1 = 1'b1;
state_next = est4;
end
est4:
begin
if(exception)
state_next = est0;
else
state_next = est5;
enab_RB2 = 1'b1;
end
est5:
begin
enab_RB3 = 1'b1;
enab_cont_var = 1'b1;
load_cont_var = 1'b1;
state_next = est6;
end
est6:
begin
if(max_tick_iter)
begin
if(operation == 1'b0)
begin
if(shift_region_flag == 2'b00)
sel_mux_2 = 2'b00;
else if(shift_region_flag == 2'b01)
sel_mux_2 = 2'b01;
else if(shift_region_flag == 2'b10)
sel_mux_2 = 2'b01;
else
sel_mux_2 = 2'b00;
enab_reg_sel_mux2 = 1'b1;
end
else
begin
if(shift_region_flag == 2'b00)
sel_mux_2 = 2'b01;
else if(shift_region_flag == 2'b01)
sel_mux_2 = 2'b00;
else if(shift_region_flag == 2'b10)
sel_mux_2 = 2'b00;
else
sel_mux_2 = 2'b01;
enab_reg_sel_mux2 = 1'b1;
end
end
else
sel_mux_2 = cont_var;
enab_reg_sel_mux2 = 1'b1;
state_next = est7;
end
est7:
begin
beg_add_subt = 1'b1;
state_next = est8;
end
est8:
begin
if(ready_add_subt)
begin
if(max_tick_iter)
begin
if(operation == 1'b0)
begin
if(shift_region_flag == 2'b00)
enab_d_ff_Xn = 1'b1;
else if(shift_region_flag == 2'b01)
enab_d_ff_Yn = 1'b1;
else if(shift_region_flag == 2'b10)
enab_d_ff_Yn = 1'b1;
else
enab_d_ff_Xn = 1'b1;
end
else
begin
if(shift_region_flag == 2'b00)
enab_d_ff_Yn = 1'b1;
else if(shift_region_flag == 2'b01)
enab_d_ff_Xn = 1'b1;
else if(shift_region_flag == 2'b10)
enab_d_ff_Xn = 1'b1;
else
enab_d_ff_Yn = 1'b1;
end
end
else
begin
if(min_tick_var)
enab_d_ff_Xn = 1'b1;
else if(max_tick_var)
enab_d_ff_Zn = 1'b1;
else
enab_d_ff_Yn = 1'b1;
end
state_next = est9;
end
else
state_next = est8;
end
est9:
begin
ack_add_subt = 1'b1;
if(max_tick_iter)
begin
state_next = est10;
end
else
begin
if(max_tick_var)
begin
enab_cont_iter = 1'b1;
state_next = est3;
end
else
begin
enab_cont_var = 1'b1;
state_next = est6;
end
end
end
est10:
begin
if(operation == 1'b0)
begin
if(shift_region_flag == 2'b00)
sel_mux_3 = 1'b0;
else if(shift_region_flag == 2'b01)
sel_mux_3 = 1'b1;
else if(shift_region_flag == 2'b10)
sel_mux_3 = 1'b1;
else
sel_mux_3 = 1'b0;
enab_reg_sel_mux3 = 1'b1;
end
else
begin
if(shift_region_flag == 2'b00)
sel_mux_3 = 1'b1;
else if(shift_region_flag == 2'b01)
sel_mux_3 = 1'b0;
else if(shift_region_flag == 2'b10)
sel_mux_3 = 1'b0;
else
sel_mux_3 = 1'b1;
enab_reg_sel_mux3 = 1'b1;
end
enab_reg_sel_mux3 = 1'b1;
state_next = est11;
end
est11:
begin
enab_dff_5 = 1'b1;
state_next = est12;
end
est12:
begin
enab_d_ff_out = 1'b1;
state_next = est13;
end
est13:
begin
ready_CORDIC = 1'b1;
if(ACK_FSM_CORDIC)
state_next = est0;
else
state_next = est13;
end
default : state_next = est0;
endcase
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "utils/cdc_pulse_sync.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "utils/ramb_8_to_n.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "utils/RAMB16_S1_S9_sim.v"
`include "utils/CG_MOD_pos.v"
`include "gpac_adc_rx/gpac_adc_rx_core.v"
`include "gpac_adc_rx/gpac_adc_rx.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_syncfifo.v"
`include "utils/pulse_gen_rising.v"
`include "utils/clock_divider.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/cdc_reset_sync.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam SEQ_GEN_BASEADDR = 32'h1000; //0x1000
localparam SEQ_GEN_HIGHADDR = 32'h3000-1; //0x300f
localparam ADC_RX_BASEADDR = 32'h3000;
localparam ADC_RX_HIGHADDR = 32'h5000 - 1;
localparam SPI_ADC_BASEADDR = 32'h5000;
localparam SPI_ADC_HIGHADDR = 32'h6000-1;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire DIV_CLK;
clock_divider #(
.DIVISOR(8)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(DIV_CLK)
);
wire EX_START_PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(DIV_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire [15:0] SEQ_OUT;
seq_gen #(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16*1024),
.OUT_BITS(16)
) i_seq_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(DIV_CLK),
.SEQ_OUT(SEQ_OUT)
);
wire SDI;
spi #(
.BASEADDR(SPI_ADC_BASEADDR),
.HIGHADDR(SPI_ADC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(2)
) i_spi (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(DIV_CLK),
.SCLK(),
.SDI(SDI),
.SDO(SDI),
.SEN(),
.SLD()
);
wire FIFO_READ_ADC;
wire FIFO_EMPTY_ADC;
wire [31:0] FIFO_DATA_ADC;
gpac_adc_rx #(
.BASEADDR(ADC_RX_BASEADDR),
.HIGHADDR(ADC_RX_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.ADC_ID(0),
.HEADER_ID(0)
) i_gpac_adc_rx (
.ADC_ENC(DIV_CLK),
.ADC_IN(SEQ_OUT[13:0]),
.ADC_SYNC(EX_START_PULSE),
.ADC_TRIGGER(1'b0),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ(FIFO_READ_ADC),
.FIFO_EMPTY(FIFO_EMPTY_ADC),
.FIFO_DATA(FIFO_DATA_ADC),
.LOST_ERROR()
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_ADC;
assign FIFO_EMPTY = FIFO_EMPTY_ADC;
assign FIFO_READ_ADC = FIFO_READ;
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("adcrx.vcd");
$dumpvars(0);
end
endmodule
|
module LCD (
input clk,
input [7:0] data_in,
output reg [7:0] data_out,
output reg lcd_e,
output reg lcd_r,
output LED0,
output LED1,
output LED2,
output LED3
);
// implementing a FSM
assign LED0 = state[0];
assign LED1 = state[1];
assign LED2 = state[2];
assign LED3 = state[3];
localparam INIT = 4'b0001;
localparam FIRST = 4'b0010;
localparam SECOND = 4'b0100;
reg [3:0] state = INIT;
integer j = 0 ;
integer i = 0 ;
reg [7:0] conf [0:5];
initial
begin
conf[0] <= 8'h38; // to enable 8-bit, 2 lines, 5x7 Dots
conf[1] <= 8'h0C; // Display on & Cursor off
conf[2] <= 8'h06; // Entry mode
conf[3] <= 8'h01; // Clear Display & DDRAM
conf[4] <= 8'h80; // Force cursor to 1'st line
conf[5] <= 8'hC0; // Force cursor to 2'nd line
end
always @ (posedge clk)
begin
state <= state;
data_out <= data_out;
case (state)
INIT:
begin
lcd_r <= 0;
if (j < 5)
begin
if (i <= 1000000)
begin
lcd_e = 1;
data_out <= conf[j];
i <= i + 1;
state <= INIT;
end
else if (i > 1000000 && i < 2000000)
begin
lcd_e = 0;
i <= i + 1;
state <= INIT;
end
else if (i == 2000000)
begin
j <= j + 1;
i <= 0;
state <= INIT;
end
end
else
begin
j <= 0;
lcd_r <= 1;
state <= FIRST;
end
end
FIRST:
begin
if (j < 16)
begin
if (i <= 1000000)
begin
lcd_e <= 1;
data_out <= data_in;
i <= i + 1;
state <= FIRST;
end
else if (i > 1000000 && i < 2000000)
begin
lcd_e = 0;
i <= i + 1;
state <= FIRST;
end
else if (i == 2000000)
begin
j <= j + 1;
i <= 0;
state <= FIRST;
end
end
else
begin
j <= 0;
lcd_r <= 0;
data_out <= conf[5];
state <= SECOND;
end
end
SECOND:
begin
lcd_r <= 1;
if (j < 16)
begin
if (i <= 1000000)
begin
lcd_e <= 1;
data_out <= data_in;
i <= i + 1;
state <= SECOND;
end
else if (i > 1000000 && i < 2000000)
begin
lcd_e = 0;
i <= i + 1;
state <= SECOND;
end
else if (i == 2000000)
begin
j <= j + 1;
i <= 0;
state <= SECOND;
end
end
else
begin
j <= 0;
lcd_r <= 0;
data_out <= conf[5];
state <= INIT;
end
end
default: state <= INIT;
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:21:18 03/06/2017
// Design Name: DNlatch_NAND
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testDNlatch_NAND.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DNlatch_NAND
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDNlatch_NAND;
// Inputs
reg En;
reg D;
// Outputs
wire Q;
wire not_Q;
// Instantiate the DESIGN Under Test (DUT)
DNlatch_NAND dut (
.En(En),
.D(D),
.Q(Q),
.not_Q(not_Q)
);
initial begin
// Initialize Inputs
En = 1;
D = 0;
// Wait 100 ns for global reset to finish
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
#50;
En = 0;
D = 0;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
#50;
En = 0;
D = 1;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
// Add stimulus here
end
endmodule
|
module test
(input wire clk,
output reg foo, bar,
input wire foo_valid, foo_in,
input wire bar_valid, bar_in
/* */);
always @(posedge clk)
begin
if (foo_valid) foo <= foo_in;
if (bar_valid) bar <= bar_in;
end
endmodule // test
module main;
reg clk;
wire foo, bar;
reg foo_valid, foo_in;
reg bar_valid, bar_in;
test dut (.clk(clk),
.foo(foo), .bar(bar),
.foo_valid(foo_valid), .bar_valid(bar_valid),
.foo_in(foo_in), .bar_in(bar_in));
task fail;
begin
$display("FAILED -- foo/bar=%b/%b, foo/bar_valid=%b/%b, foo/bar_in=%b/%b",
foo, bar, foo_valid, bar_valid, foo_in, bar_in);
$finish;
end
endtask // fail
initial begin
clk = 0;
foo_valid = 1;
bar_valid = 1;
foo_in = 0;
bar_in = 0;
#1 clk = 1;
#1 clk = 0;
if (foo !== 0 || bar !== 0)
fail;
bar_in = 1;
#1 clk = 1;
#1 clk = 0;
if (foo !== 0 || bar !== 1)
fail;
foo_in = 1;
bar_in = 0;
foo_valid = 1;
bar_valid = 0;
#1 clk = 1;
#1 clk = 0;
if (foo !== 1 || bar !== 1)
fail;
$display("PASSED");
end
endmodule // main
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RESPONSE_QUEUE.v when simulating
// the core, RESPONSE_QUEUE. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RESPONSE_QUEUE(
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(8),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(127),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(126),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(8),
.C_RD_DEPTH(128),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(7),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(8),
.C_WR_DEPTH(128),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(7),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.SRST(srst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.RST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
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