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/*
File: axi_slave.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_slave (/*AUTOARG*/
// Outputs
csysack, cactive, awready, wready, bid, bresp, bvalid, arready,
rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
emesh_wr_wait_inb, emesh_rd_wait_inb,
// Inputs
aclk, eclk, reset, csysreq, awid, awaddr, awlen, awsize, awburst,
awlock, awcache, awprot, awvalid, wid, wdata, wstrb, wlast, wvalid,
bready, arid, araddr, arlen, arsize, arburst, arlock, arcache,
arprot, arvalid, rready, emesh_access_outb, emesh_write_outb,
emesh_datamode_outb, emesh_ctrlmode_outb, emesh_dstaddr_outb,
emesh_srcaddr_outb, emesh_data_outb, emesh_wr_wait_outb,
emesh_rd_wait_outb, awqos, arqos
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
input csysreq;// system exit low-power state request
//########################
//# Write address channel
//########################
input [SIDW-1:0] awid; //write address ID
input [SAW-1:0] awaddr; //write address
input [3:0] awlen; //burst lenght (the number of data transfers)
input [2:0] awsize; //burst size (the size of each transfer)
input [1:0] awburst; //burst type
input [1:0] awlock; //lock type (atomic characteristics)
input [3:0] awcache; //memory type
input [2:0] awprot; //protection type
input awvalid; //write address valid
//########################
//# Write data channel
//########################
input [SIDW-1:0] wid; //write ID tag (supported only in AXI3)
input [SDW-1:0] wdata; //write data
input [3:0] wstrb; //write strobes
input wlast; //write last. Indicates the last transfer in burst
input wvalid;//write valid
//########################
// Write response channel
//########################
input bready;//response ready
//########################
//# Read address channel
//########################
input [SIDW-1:0] arid; //read address ID
input [SAW-1:0] araddr; //read address
input [3:0] arlen; //burst lenght (the number of data transfers)
input [2:0] arsize; //burst size (the size of each transfer)
input [1:0] arburst; //burst type
input [1:0] arlock; //lock type (atomic characteristics)
input [3:0] arcache; //memory type
input [2:0] arprot; //protection type
input arvalid; //write address valid
//########################
//# Read data channel
//########################
input rready; //read ready
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_wr_wait_outb;
input emesh_rd_wait_outb;
//##########
//# Outputs
//##########
// global signals
output csysack;//exit low-power state acknowledgement
output cactive;//clock active
//########################
//# Write address channel
//########################
output awready; //write address ready
//########################
//# Write data channel
//########################
output wready; //write ready
//########################
// Write response channel
//########################
output [SIDW-1:0] bid; //response ID tag
output [1:0] bresp; //write response
output bvalid;//write response valid
//########################
//# Read address channel
//########################
output arready;//read address ready
//########################
//# Read data channel
//########################
output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
output [SDW-1:0] rdata; //read data
output [1:0] rresp; //read response
output rlast; //read last, indicates the last transfer in burst
output rvalid;//read valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
output emesh_rd_wait_inb;
//#######################################################################
//# The following feature are not supported (AXI4 only)
//# If un-commented, those signals have to be driven with default values
//#######################################################################
input [3:0] awqos; //Quality of Service (AXI4 only) default 4'b0000
// input [3:0] awregion;//region identifier (AXI4 only)
// input awuser; //user signal (AXI4 only)
// input wuser; //user signal (AXI4 only)
input [3:0] arqos; //quality of service (AXI4 only) default 4'b0000
// input [3:0] arregion;//region identifier (AXI4 only)
// input aruser; //user signal (AXI4 only)
// output buser; //user signal (AXI4 only)
// output ruser; //user signal (AXI4 only)
//#########
//# Regs
//#########
reg csysack;
//#########
//# Wires
//#########
wire emesh_wr_access_inb;
wire emesh_wr_write_inb;
wire [1:0] emesh_wr_datamode_inb;
wire [3:0] emesh_wr_ctrlmode_inb;
wire [31:0] emesh_wr_dstaddr_inb;
wire [31:0] emesh_wr_srcaddr_inb;
wire [31:0] emesh_wr_data_inb;
wire emesh_rd_access_inb;
wire emesh_rd_write_inb;
wire [1:0] emesh_rd_datamode_inb;
wire [3:0] emesh_rd_ctrlmode_inb;
wire [31:0] emesh_rd_dstaddr_inb;
wire [31:0] emesh_rd_srcaddr_inb;
wire [31:0] emesh_rd_data_inb;
wire emesh_rd_wait;
/*AUTOINPUT*/
/*AUTOWIRE*/
//##################################################
//# This block doesn't accept read transactions
//# from emesh.
//##################################################
assign emesh_rd_wait_inb = 1'b0;
//##################################################
//# Low Power State
//# We don't support low power state
//##################################################
assign cactive = 1'b1;
always @ (posedge eclk or posedge reset)
if(reset)
csysack <= 1'b1;
else
csysack <= csysreq;
//##################################################
//# RD/WR transaction selection
//# *Write transactions are of the higher priority
//##################################################
assign emesh_rd_wait = emesh_rd_wait_outb | emesh_wr_access_inb;
assign emesh_access_inb = emesh_wr_access_inb | emesh_rd_access_inb;
assign emesh_write_inb = emesh_wr_access_inb ? emesh_wr_write_inb :
emesh_rd_write_inb;
assign emesh_datamode_inb[1:0] = emesh_wr_access_inb ?
emesh_wr_datamode_inb[1:0] :
emesh_rd_datamode_inb[1:0];
assign emesh_ctrlmode_inb[3:0] = emesh_wr_access_inb ?
emesh_wr_ctrlmode_inb[3:0] :
emesh_rd_ctrlmode_inb[3:0];
assign emesh_dstaddr_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_dstaddr_inb[31:0] :
emesh_rd_dstaddr_inb[31:0];
assign emesh_srcaddr_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_srcaddr_inb[31:0] :
emesh_rd_srcaddr_inb[31:0];
assign emesh_data_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_data_inb[31:0] :
emesh_rd_data_inb[31:0];
//##################################
//# Slave Write Port Instantiation
//##################################
/*axi_slave_wr AUTO_TEMPLATE(.emesh_wr_wait_outb (emesh_wr_wait_outb),
.emesh_\(.*\)_inb (emesh_wr_\1_inb[]),
);
*/
axi_slave_wr axi_slave_wr(/*AUTOINST*/
// Outputs
.awready (awready),
.wready (wready),
.bid (bid[SIDW-1:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.emesh_access_inb (emesh_wr_access_inb), // Templated
.emesh_write_inb (emesh_wr_write_inb), // Templated
.emesh_datamode_inb(emesh_wr_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(emesh_wr_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.awid (awid[SIDW-1:0]),
.awaddr (awaddr[SAW-1:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[SIDW-1:0]),
.wdata (wdata[SDW-1:0]),
.wstrb (wstrb[3:0]),
.wlast (wlast),
.wvalid (wvalid),
.bready (bready),
.emesh_wr_wait_outb(emesh_wr_wait_outb)); // Templated
//##################################
//# Slave Read Port Instantiation
//##################################
/*axi_slave_rd AUTO_TEMPLATE(.emesh_rd_wait_outb (emesh_rd_wait),
.emesh_wr_wait_inb (emesh_wr_wait_inb),
.emesh_\(.*\)_inb (emesh_rd_\1_inb[]),
);
*/
axi_slave_rd axi_slave_rd(/*AUTOINST*/
// Outputs
.arready (arready),
.rid (rid[SIDW-1:0]),
.rdata (rdata[SDW-1:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid),
.emesh_access_inb (emesh_rd_access_inb), // Templated
.emesh_write_inb (emesh_rd_write_inb), // Templated
.emesh_datamode_inb(emesh_rd_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(emesh_rd_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (emesh_wr_wait_inb), // Templated
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.arid (arid[SIDW-1:0]),
.araddr (araddr[SAW-1:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arburst (arburst[1:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready),
.emesh_access_outb (emesh_access_outb),
.emesh_write_outb (emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]),
.emesh_rd_wait_outb(emesh_rd_wait)); // Templated
endmodule // axi_slave
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
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// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
`timescale 1ns / 1ps
module forwarding_unit (
input ex_mem_reg_write,
input mem_wb_reg_write,
input [4:0] ex_mem_dst_reg,
input [4:0] mem_wb_dst_reg,
input [4:0] id_ex_rs,
input [4:0] id_ex_rt,
input [4:0] if_id_rs,
input [4:0] if_id_rt,
output [1:0] if_rs_forward_control,
output [1:0] id_rt_forward_control,
output [1:0] ex_rs_forward_control,
output [1:0] ex_rt_forward_control );
//tmp signals
wire [3:0] id_fwd_ctrl, ex_fwd_ctrl;
// encoding for muxes control signals
// general for both forwarding muxes
// 2'b01 - from EX_MEM pipe reg
// 2'b10 - from MEM_WB pipe reg
// 2'b00 - no forwarding
assign if_rs_forward_control = id_fwd_ctrl[0] ? 2'b01 : id_fwd_ctrl[2] ? 2'b10 : 2'b00;
assign id_rt_forward_control = id_fwd_ctrl[1] ? 2'b01 : id_fwd_ctrl[3] ? 2'b10 : 2'b00;
assign ex_rs_forward_control = ex_fwd_ctrl[0] ? 2'b01 : ex_fwd_ctrl[2] ? 2'b10 : 2'b00;
assign ex_rt_forward_control = ex_fwd_ctrl[1] ? 2'b01 : ex_fwd_ctrl[3] ? 2'b10 : 2'b00;
base_forwarding_unit ex_forwarding_inst(
.ex_mem_reg_write(ex_mem_reg_write),
.mem_wb_reg_write(mem_wb_reg_write),
.ex_mem_dst_reg(ex_mem_dst_reg),
.mem_wb_dst_reg(mem_wb_dst_reg),
.rs(id_ex_rs),
.rt(id_ex_rt),
.forward_control(ex_fwd_ctrl));
base_forwarding_unit id_forwarding_inst(
.ex_mem_reg_write(ex_mem_reg_write),
.mem_wb_reg_write(mem_wb_reg_write),
.ex_mem_dst_reg(ex_mem_dst_reg),
.mem_wb_dst_reg(mem_wb_dst_reg),
.rs(if_id_rs),
.rt(if_id_rt),
.forward_control(id_fwd_ctrl));
endmodule
/* Generic base logic module to implement forwarding
*
* Description of forward_control signal:
* 0000 - no forwarding
* 0001 - forwarding value from EX_MEM for replace rs value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rs]
* 0010 - forwarding value from EX_MEM for replace rt value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rt]
* 0100 - forwarding value from WB for replace rs value on destination stage.
* WB[Value] -> PIPE_STAGE[rs]
* 1000 - forwarding value from WB for replace rt value on destination stage.
* WB[Value] -> PIPE_STAGE[rt]
* 0011 - forwarding value from EX_MEM for replace rs and rt value on destination stage
* EX_MEM[Value] -> PIPE_STAGE[rs]; EX_MEM[Value] -> PIPE_STAGE[rt]
* 1100 - forwarding value from WB for replace Rs and Rt value on destination stage
* WB[Value] -> PIPE_STAGE[rs]; WB[Value] -> PIPE_STAGE[rt]
* 0110 - forwarding value from EX_MEM for replace rt value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rt]
* forwarding value from WB for replace rs value on destination stage.
* WB[Value] -> PIPE_STAGE[rs]
* 1001 - forwarding value from EX_MEM for replace rs value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rs]
* forwarding value from WB for replace rt value on destination stage.
* WB[Value] -> PIPE_STAGE[rt]
*/
module base_forwarding_unit ( input ex_mem_reg_write,
input mem_wb_reg_write,
input [4:0] ex_mem_dst_reg,
input [4:0] mem_wb_dst_reg,
input [4:0] rs,
input [4:0] rt,
output reg [3:0] forward_control);
//service signals
reg ex_mem_dst_reg_is_not_zero;
reg mem_wb_dst_reg_is_not_zero;
always @* begin
ex_mem_dst_reg_is_not_zero = |ex_mem_dst_reg;
mem_wb_dst_reg_is_not_zero = |mem_wb_dst_reg;
forward_control = 4'h0;
if (ex_mem_reg_write & ex_mem_dst_reg_is_not_zero) begin
if (ex_mem_dst_reg == rs)
forward_control[0] = 1'b1;
else
forward_control[0] = 1'b0;
if (ex_mem_dst_reg == rt)
forward_control[1] = 1'b1;
else
forward_control[1] = 1'b0;
end
else
forward_control[1:0] = 2'b00;
if (mem_wb_reg_write & mem_wb_dst_reg_is_not_zero) begin
if ((mem_wb_dst_reg == rs) & (ex_mem_dst_reg != rs))
forward_control[2] = 1'b1;
else
forward_control[2] = 1'b0;
if ((mem_wb_dst_reg == rt) & (ex_mem_dst_reg != rt))
forward_control[3] = 1'b1;
else
forward_control[3] = 1'b0;
end
else
forward_control[3:2] = 2'b00;
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module soc_system_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/25/2009
Version 1.0
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_TB_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_hdll__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_TB_V
|
// test_data_dma.v
`timescale 1ns / 1ps
module test_data_dma;
// avalon clock interface
reg clk = 0;
reg reset = 1;
// avalon mm slave: control port
reg [1:0]avs_ctrl_address = 2'bxx;
reg avs_ctrl_write = 0;
reg [31:0]avs_ctrl_writedata = 32'hxxxx_xxxx;
reg avs_ctrl_read = 0;
wire [31:0]avs_ctrl_readdata;
// avalon mm master: DMA data write port
wire [31:0]avm_data_address;
wire avm_data_write;
wire [15:0]avm_data_writedata;
reg avm_data_waitrequest;
wire [1:0]avm_data_byteenable;
// avalon conduit: external data source
reg write;
wire waitrq;
reg [15:0]data;
always #10 clk = !clk;
initial #25 reset = 0;
// --- data generator -----------------------------------------------------
integer dg_cnt = 0;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data <= 100;
write <= 0;
end
else
begin
write <= (dg_cnt % 10) > 2;
dg_cnt = dg_cnt + 1;
if (write & !waitrq) data <= data + 1;
end
end
// --- ram ----------------------------------------------------------------
integer ram_cnt = 0;
always @(posedge clk)
begin
ram_cnt = ram_cnt + 1;
avm_data_waitrequest <= (ram_cnt % 13) >= 11;
end
// --- DMA programming ----------------------------------------------------
task WriteCtrl(input [1:0]register, input [31:0]data);
begin
@(posedge clk);
avs_ctrl_write <= 1;
avs_ctrl_address <= register;
avs_ctrl_writedata <= data;
@(posedge clk)
avs_ctrl_write <= 0;
avs_ctrl_address <= 2'bxx;
avs_ctrl_writedata <= 32'hxxxx_xxxx;
end
endtask
initial
begin
#160;
WriteCtrl(0, 32'h0100_0000);
WriteCtrl(1, 100);
WriteCtrl(2, 1);
#2000 $stop(2);
end
data_dma DUT
(
.csi_clock_clk(clk),
.csi_clock_reset(reset),
// avalon mm slave: control port
.avs_ctrl_address(avs_ctrl_address),
.avs_ctrl_write(avs_ctrl_write),
.avs_ctrl_writedata(avs_ctrl_writedata),
.avs_ctrl_read(avs_ctrl_read),
.avs_ctrl_readdata(avs_ctrl_readdata),
// avalon mm master: DMA data write port
.avm_data_address(avm_data_address),
.avm_data_write(avm_data_write),
.avm_data_writedata(avm_data_writedata),
.avm_data_waitrequest(avm_data_waitrequest),
.avm_data_byteenable(avm_data_byteenable),
// avalon conduit: external data source
.write(write),
.waitrq(waitrq),
.data(data)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_1_V
`define SKY130_FD_SC_MS__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_4_V
`define SKY130_FD_SC_HS__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_4_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_7_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [8-1:0] cmd_repeat,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [8-1:0] repeat_cnt_pre;
reg [8-1:0] repeat_cnt;
wire [8-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 8'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 2'b01;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 8'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = cmd_id;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of enumerated type methods
//
// This code exercises the various enumeration methods
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
// **** Pin Identifiers ****
typedef enum int
{
PINID_A0 = 32'd0, // MUST BE ZERO!
// - Standard Ports -
PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7,
PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7,
PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7,
PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7,
PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7,
PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7,
PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7,
PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7,
// PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1
PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7,
PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7,
PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7,
PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7,
PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7,
// PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0
PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7,
PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7,
PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7,
// - AUX Port (Custom) -
PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7,
// - PDI Port -
PINID_D2W_DAT, PINID_D2W_CLK,
// - Power Pins -
PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3,
PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3,
// - Maximum number of pins -
PINID_MAX
} t_pinid;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
test test_i (/*AUTOINST*/
// Inputs
.clk (clk));
// This is a compile time only test. Immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module test (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Use the enumeration size to initialize a dynamic array
t_pinid e;
int myarray1 [] = new [e.num];
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Enumeration has %d members\n", e.num);
`endif
e = e.first;
forever begin
myarray1[e] <= e.prev;
`ifdef TEST_VERBOSE
$write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]);
`endif
if (e == e.last) begin
break;
end
else begin
e = e.next;
end
end
end
endmodule
|
// altera_ram.v this now takes parameter ADDRBITS to set size
// Use ADDRBITS = 10 for 1024 words, 9 for 512 (halfram)
// NB since I HAVE edited this file (contrary to the warning
// below, its probably not a good idea to invoke the wizard)
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 153 11/29/2010 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram # ( parameter ADDRBITS=10 ) (
address,
clock,
data,
wren,
q);
input [ADDRBITS-1:0] address;
input clock;
input [255:0] data;
input wren;
output [255:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [255:0] sub_wire0;
wire [255:0] q = sub_wire0[255:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2 << (ADDRBITS-1),
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.widthad_a = ADDRBITS,
altsyncram_component.width_a = 256,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "256"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "256"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL "data[255..0]"
// Retrieval info: USED_PORT: q 0 0 256 0 OUTPUT NODEFVAL "q[255..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 256 0 data 0 0 256 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 256 0 @q_a 0 0 256 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
/*
* Copyright (c) 2014, Aleksander Osman
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module simple_ram
#(parameter width = 1,
parameter widthad = 1
)
(
input clk,
input [widthad-1:0] wraddress,
input wren,
input [width-1:0] data,
input [widthad-1:0] rdaddress,
output reg [width-1:0] q
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren) mem[wraddress] <= data;
q <= mem[rdaddress];
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS)
)
(
input logic [ADDRESS_W-1:0] address,
output logic [NUM_BANKS-1:0] bank_sel, // one-hot
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] bank_address
);
integer i;
// To support NUM_BANKS=1 we need a wider address
logic [ADDRESS_W:0] wider_address;
assign wider_address = {1'b0,address};
always@*
begin
for (i=0; i<NUM_BANKS; i=i+1)
bank_sel[i] = (wider_address[BANK_SEL_BIT+$clog2(NUM_BANKS)-1 : BANK_SEL_BIT] == i);
end
assign bank_address = ((address>>(BANK_SEL_BIT+$clog2(NUM_BANKS)))<<(BANK_SEL_BIT)) |
// Take address[BANKS_SEL_BIT-1:0] in a manner that allows BANK_SEL_BIT=0
((~({ADDRESS_W{1'b1}}<<BANK_SEL_BIT)) & address);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Nnat ZArith_base ROmega ZArithRing Zdiv Morphisms.
Local Open Scope Z_scope.
(** This file provides results about the Round-Toward-Zero Euclidean
division [Z.quotrem], whose projections are [Z.quot] (noted ÷)
and [Z.rem].
This division and [Z.div] agree only on positive numbers.
Otherwise, [Z.div] performs Round-Toward-Bottom (a.k.a Floor).
This [Z.quot] is compatible with the division of usual
programming languages such as Ocaml. In addition, it has nicer
properties with respect to opposite and other usual operations.
The definition of this division is now in file [BinIntDef],
while most of the results about here are now in the main module
[BinInt.Z], thanks to the generic "Numbers" layer. Remain here:
- some compatibility notation for old names.
- some extra results with less preconditions (in particular
exploiting the arbitrary value of division by 0).
*)
Notation Ndiv_Zquot := N2Z.inj_quot (compat "8.3").
Notation Nmod_Zrem := N2Z.inj_rem (compat "8.3").
Notation Z_quot_rem_eq := Z.quot_rem' (compat "8.3").
Notation Zrem_lt := Z.rem_bound_abs (compat "8.3").
Notation Zquot_unique := Z.quot_unique (compat "8.3").
Notation Zrem_unique := Z.rem_unique (compat "8.3").
Notation Zrem_1_r := Z.rem_1_r (compat "8.3").
Notation Zquot_1_r := Z.quot_1_r (compat "8.3").
Notation Zrem_1_l := Z.rem_1_l (compat "8.3").
Notation Zquot_1_l := Z.quot_1_l (compat "8.3").
Notation Z_quot_same := Z.quot_same (compat "8.3").
Notation Z_quot_mult := Z.quot_mul (compat "8.3").
Notation Zquot_small := Z.quot_small (compat "8.3").
Notation Zrem_small := Z.rem_small (compat "8.3").
Notation Zquot2_quot := Zquot2_quot (compat "8.3").
(** Particular values taken for [a÷0] and [(Z.rem a 0)].
We avise to not rely on these arbitrary values. *)
Lemma Zquot_0_r a : a ÷ 0 = 0.
Proof. now destruct a. Qed.
Lemma Zrem_0_r a : Z.rem a 0 = a.
Proof. now destruct a. Qed.
(** The following results are expressed without the [b<>0] condition
whenever possible. *)
Lemma Zrem_0_l a : Z.rem 0 a = 0.
Proof. now destruct a. Qed.
Lemma Zquot_0_l a : 0÷a = 0.
Proof. now destruct a. Qed.
Hint Resolve Zrem_0_l Zrem_0_r Zquot_0_l Zquot_0_r Z.quot_1_r Z.rem_1_r
: zarith.
Ltac zero_or_not a :=
destruct (Z.eq_decidable a 0) as [->|?];
[rewrite ?Zquot_0_l, ?Zrem_0_l, ?Zquot_0_r, ?Zrem_0_r;
auto with zarith|].
Lemma Z_rem_same a : Z.rem a a = 0.
Proof. zero_or_not a. now apply Z.rem_same. Qed.
Lemma Z_rem_mult a b : Z.rem (a*b) b = 0.
Proof. zero_or_not b. now apply Z.rem_mul. Qed.
(** * Division and Opposite *)
(* The precise equalities that are invalid with "historic" Zdiv. *)
Theorem Zquot_opp_l a b : (-a)÷b = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_l. Qed.
Theorem Zquot_opp_r a b : a÷(-b) = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_r. Qed.
Theorem Zrem_opp_l a b : Z.rem (-a) b = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_l. Qed.
Theorem Zrem_opp_r a b : Z.rem a (-b) = Z.rem a b.
Proof. zero_or_not b. now apply Z.rem_opp_r. Qed.
Theorem Zquot_opp_opp a b : (-a)÷(-b) = a÷b.
Proof. zero_or_not b. now apply Z.quot_opp_opp. Qed.
Theorem Zrem_opp_opp a b : Z.rem (-a) (-b) = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_opp. Qed.
(** The sign of the remainder is the one of [a]. Due to the possible
nullity of [a], a general result is to be stated in the following form:
*)
Theorem Zrem_sgn a b : 0 <= Z.sgn (Z.rem a b) * Z.sgn a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- zero_or_not (Z.rem a b).
rewrite Z.rem_sign_nz; trivial. apply Z.square_nonneg.
Qed.
(** This can also be said in a simplier way: *)
Theorem Zrem_sgn2 a b : 0 <= (Z.rem a b) * a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- now apply Z.rem_sign_mul.
Qed.
(** Reformulation of [Z.rem_bound_abs] in 2 then 4 particular cases. *)
Theorem Zrem_lt_pos a b : 0<=a -> b<>0 -> 0 <= Z.rem a b < Z.abs b.
Proof.
intros; generalize (Z.rem_nonneg a b) (Z.rem_bound_abs a b);
romega with *.
Qed.
Theorem Zrem_lt_neg a b : a<=0 -> b<>0 -> -Z.abs b < Z.rem a b <= 0.
Proof.
intros; generalize (Z.rem_nonpos a b) (Z.rem_bound_abs a b);
romega with *.
Qed.
Theorem Zrem_lt_pos_pos a b : 0<=a -> 0<b -> 0 <= Z.rem a b < b.
Proof.
intros; generalize (Zrem_lt_pos a b); romega with *.
Qed.
Theorem Zrem_lt_pos_neg a b : 0<=a -> b<0 -> 0 <= Z.rem a b < -b.
Proof.
intros; generalize (Zrem_lt_pos a b); romega with *.
Qed.
Theorem Zrem_lt_neg_pos a b : a<=0 -> 0<b -> -b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); romega with *.
Qed.
Theorem Zrem_lt_neg_neg a b : a<=0 -> b<0 -> b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); romega with *.
Qed.
(** * Unicity results *)
Definition Remainder a b r :=
(0 <= a /\ 0 <= r < Z.abs b) \/ (a <= 0 /\ -Z.abs b < r <= 0).
Definition Remainder_alt a b r :=
Z.abs r < Z.abs b /\ 0 <= r * a.
Lemma Remainder_equiv : forall a b r,
Remainder a b r <-> Remainder_alt a b r.
Proof.
unfold Remainder, Remainder_alt; intuition.
- romega with *.
- romega with *.
- rewrite <-(Z.mul_opp_opp). apply Z.mul_nonneg_nonneg; romega.
- assert (0 <= Z.sgn r * Z.sgn a).
{ rewrite <-Z.sgn_mul, Z.sgn_nonneg; auto. }
destruct r; simpl Z.sgn in *; romega with *.
Qed.
Theorem Zquot_mod_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b /\ r = Z.rem a b.
Proof.
destruct 1 as [(H,H0)|(H,H0)]; intros.
apply Zdiv_mod_unique with b; auto.
apply Zrem_lt_pos; auto.
romega with *.
rewrite <- H1; apply Z.quot_rem'.
rewrite <- (Z.opp_involutive a).
rewrite Zquot_opp_l, Zrem_opp_l.
generalize (Zdiv_mod_unique b (-q) (-a÷b) (-r) (Z.rem (-a) b)).
generalize (Zrem_lt_pos (-a) b).
rewrite <-Z.quot_rem', Z.mul_opp_r, <-Z.opp_add_distr, <-H1.
romega with *.
Qed.
Theorem Zquot_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
Theorem Zrem_unique_full a b q r :
Remainder a b r -> a = b*q + r -> r = Z.rem a b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
(** * Order results about Zrem and Zquot *)
(* Division of positive numbers is positive. *)
Lemma Z_quot_pos a b : 0 <= a -> 0 <= b -> 0 <= a÷b.
Proof. intros. zero_or_not b. apply Z.quot_pos; auto with zarith. Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_quot_lt a b : 0 < a -> 2 <= b -> a÷b < a.
Proof. intros. apply Z.quot_lt; auto with zarith. Qed.
(** [<=] is compatible with a positive division. *)
Lemma Z_quot_monotone a b c : 0<=c -> a<=b -> a÷c <= b÷c.
Proof. intros. zero_or_not c. apply Z.quot_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a÷b) is always done toward 0: *)
Lemma Z_mult_quot_le a b : 0 <= a -> 0 <= b*(a÷b) <= a.
Proof. intros. zero_or_not b. apply Z.mul_quot_le; auto with zarith. Qed.
Lemma Z_mult_quot_ge a b : a <= 0 -> a <= b*(a÷b) <= 0.
Proof. intros. zero_or_not b. apply Z.mul_quot_ge; auto with zarith. Qed.
(** The previous inequalities between [b*(a÷b)] and [a] are exact
iff the modulo is zero. *)
Lemma Z_quot_exact_full a b : a = b*(a÷b) <-> Z.rem a b = 0.
Proof. intros. zero_or_not b. intuition. apply Z.quot_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zrem_le a b : 0 <= a -> 0 <= b -> Z.rem a b <= a.
Proof. intros. zero_or_not b. apply Z.rem_le; auto with zarith. Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zquot_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a÷b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_upper_bound. Qed.
Theorem Zquot_lt_upper_bound:
forall a b q, 0 <= a -> 0 < b -> a < q*b -> a÷b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_lt_upper_bound. Qed.
Theorem Zquot_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a÷b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_lower_bound. Qed.
Theorem Zquot_sgn: forall a b,
0 <= Z.sgn (a÷b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
unfold Z.quot; simpl; destruct N.pos_div_eucl; simpl; destruct n; simpl; auto with zarith.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
(** First, a result that used to be always valid with Zdiv,
but must be restricted here.
For instance, now (9+(-5)*2) rem 2 = -1 <> 1 = 9 rem 2 *)
Lemma Z_rem_plus : forall a b c:Z,
0 <= (a+b*c) * a ->
Z.rem (a + b * c) c = Z.rem a c.
Proof. intros. zero_or_not c. apply Z.rem_add; auto with zarith. Qed.
Lemma Z_quot_plus : forall a b c:Z,
0 <= (a+b*c) * a -> c<>0 ->
(a + b * c) ÷ c = a ÷ c + b.
Proof. intros. apply Z.quot_add; auto with zarith. Qed.
Theorem Z_quot_plus_l: forall a b c : Z,
0 <= (a*b+c)*c -> b<>0 ->
b<>0 -> (a * b + c) ÷ b = a + c ÷ b.
Proof. intros. apply Z.quot_add_l; auto with zarith. Qed.
(** Cancellations. *)
Lemma Zquot_mult_cancel_r : forall a b c:Z,
c<>0 -> (a*c)÷(b*c) = a÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_cancel_r; auto. Qed.
Lemma Zquot_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)÷(c*b) = a÷b.
Proof.
intros. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.quot_mul_cancel_l; auto.
Qed.
Lemma Zmult_rem_distr_l: forall a b c,
Z.rem (c*a) (c*b) = c * (Z.rem a b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_rem_distr_l; auto.
Qed.
Lemma Zmult_rem_distr_r: forall a b c,
Z.rem (a*c) (b*c) = (Z.rem a b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c). zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_rem_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zrem_rem: forall a n, Z.rem (Z.rem a n) n = Z.rem a n.
Proof. intros. zero_or_not n. apply Z.rem_rem; auto. Qed.
Theorem Zmult_rem: forall a b n,
Z.rem (a * b) n = Z.rem (Z.rem a n * Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.mul_rem; auto. Qed.
(** addition and modulo
Generally speaking, unlike with Zdiv, we don't have
(a+b) rem n = (a rem n + b rem n) rem n
for any a and b.
For instance, take (8 + (-10)) rem 3 = -2 whereas
(8 rem 3 + (-10 rem 3)) rem 3 = 1. *)
Theorem Zplus_rem: forall a b n,
0 <= a * b ->
Z.rem (a + b) n = Z.rem (Z.rem a n + Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.add_rem; auto. Qed.
Lemma Zplus_rem_idemp_l: forall a b n,
0 <= a * b ->
Z.rem (Z.rem a n + b) n = Z.rem (a + b) n.
Proof. intros. zero_or_not n. apply Z.add_rem_idemp_l; auto. Qed.
Lemma Zplus_rem_idemp_r: forall a b n,
0 <= a*b ->
Z.rem (b + Z.rem a n) n = Z.rem (b + a) n.
Proof.
intros. zero_or_not n. apply Z.add_rem_idemp_r; auto.
rewrite Z.mul_comm; auto.
Qed.
Lemma Zmult_rem_idemp_l: forall a b n, Z.rem (Z.rem a n * b) n = Z.rem (a * b) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_l; auto. Qed.
Lemma Zmult_rem_idemp_r: forall a b n, Z.rem (b * Z.rem a n) n = Z.rem (b * a) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_r; auto. Qed.
(** Unlike with Zdiv, the following result is true without restrictions. *)
Lemma Zquot_Zquot : forall a b c, (a÷b)÷c = a÷(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.quot_quot; auto.
Qed.
(** A last inequality: *)
Theorem Zquot_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a÷b) <= (c*a)÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_le; auto with zarith. Qed.
(** Z.rem is related to divisibility (see more in Znumtheory) *)
Lemma Zrem_divides : forall a b,
Z.rem a b = 0 <-> exists c, a = b*c.
Proof.
intros. zero_or_not b. firstorder.
rewrite Z.rem_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zquot2_odd_remainder : forall a,
Remainder a 2 (if Z.odd a then Z.sgn a else 0).
Proof.
intros [ |p|p]. simpl.
left. simpl. auto with zarith.
left. destruct p; simpl; auto with zarith.
right. destruct p; simpl; split; now auto with zarith.
Qed.
Lemma Zrem_odd : forall a, Z.rem a 2 = if Z.odd a then Z.sgn a else 0.
Proof.
intros. symmetry.
apply Zrem_unique_full with (Z.quot2 a).
apply Zquot2_odd_remainder.
apply Zquot2_odd_eqn.
Qed.
Lemma Zrem_even : forall a, Z.rem a 2 = if Z.even a then 0 else Z.sgn a.
Proof.
intros a. rewrite Zrem_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zeven_rem : forall a, Z.even a = Z.eqb (Z.rem a 2) 0.
Proof.
intros a. rewrite Zrem_even.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
Lemma Zodd_rem : forall a, Z.odd a = negb (Z.eqb (Z.rem a 2) 0).
Proof.
intros a. rewrite Zrem_odd.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
(** * Interaction with "historic" Zdiv *)
(** They agree at least on positive numbers: *)
Theorem Zquotrem_Zdiv_eucl_pos : forall a b:Z, 0 <= a -> 0 < b ->
a÷b = a/b /\ Z.rem a b = a mod b.
Proof.
intros.
apply Zdiv_mod_unique with b.
apply Zrem_lt_pos; auto with zarith.
rewrite Z.abs_eq; auto with *; apply Z_mod_lt; auto with *.
rewrite <- Z_div_mod_eq; auto with *.
symmetry; apply Z.quot_rem; auto with *.
Qed.
Theorem Zquot_Zdiv_pos : forall a b, 0 <= a -> 0 <= b ->
a÷b = a/b.
Proof.
intros a b Ha Hb. Z.le_elim Hb.
- generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb); intuition.
- subst; now rewrite Zquot_0_r, Zdiv_0_r.
Qed.
Theorem Zrem_Zmod_pos : forall a b, 0 <= a -> 0 < b ->
Z.rem a b = a mod b.
Proof.
intros a b Ha Hb; generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb);
intuition.
Qed.
(** Modulos are null at the same places *)
Theorem Zrem_Zmod_zero : forall a b, b<>0 ->
(Z.rem a b = 0 <-> a mod b = 0).
Proof.
intros.
rewrite Zrem_divides, Zmod_divides; intuition.
Qed.
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPP xxx - 1:5 Differential Data De-serializer
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_1_to_5_diff_data.v
//
// Description : This module instantiates IODELAY2 and ISERDES2 primitives
// to receive TMDS differential data in 1:5 format
//
// Note:
//
// Author : Bob Feng
//////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serdes_1_to_5_diff_data # (
parameter DIFF_TERM = "TRUE",
parameter SIM_TAP_DELAY = 49,
parameter BITSLIP_ENABLE = "FALSE"
)(
input wire use_phase_detector, // '1' enables the phase detector logic
input wire datain_p, // Input from LVDS receiver pin
input wire datain_n, // Input from LVDS receiver pin
input wire rxioclk, // IO Clock network
input wire rxserdesstrobe, // Parallel data capture strobe
input wire reset, // Reset line
input wire gclk, // Global clock
input wire bitslip, // Bitslip control line
output wire [4:0] data_out // Output data
);
wire ddly_m;
wire ddly_s;
wire busys;
wire rx_data_in;
wire cascade;
wire pd_edge;
reg [8:0] counter;
reg [3:0] state;
reg cal_data_sint;
wire busy_data;
reg busy_data_d;
wire cal_data_slave;
reg enable;
reg cal_data_master;
reg rst_data;
reg inc_data_int;
wire inc_data;
reg ce_data;
reg valid_data_d;
reg incdec_data_d;
reg [4:0] pdcounter;
wire valid_data;
wire incdec_data;
reg flag;
reg mux;
reg ce_data_inta ;
wire [1:0] incdec_data_or;
wire incdec_data_im;
wire [1:0] valid_data_or;
wire valid_data_im;
wire [1:0] busy_data_or;
wire all_ce;
wire [1:0] debug_in = 2'b00;
assign busy_data = busys ;
assign cal_data_slave = cal_data_sint ;
/////////////////////////////////////////////////
//
// IDELAY Calibration FSM
//
/////////////////////////////////////////////////
always @ (posedge gclk or posedge reset)
begin
if (reset == 1'b1) begin
state <= 0 ;
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
counter <= 9'h000 ;
enable <= 1'b0 ;
mux <= 1'h1 ;
end
else begin
counter <= counter + 9'h001 ;
if (counter[8] == 1'b1) begin
counter <= 9'h000 ;
end
if (counter[5] == 1'b1) begin
enable <= 1'b1 ;
end
if (state == 0 && enable == 1'b1) begin // Wait for IODELAY to be available
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 1 ;
end
end
else if (state == 1) begin // Issue calibrate command to both master and slave, needed for simulation, not for the silicon
cal_data_master <= 1'b1 ;
cal_data_sint <= 1'b1 ;
if (busy_data_d == 1'b1) begin // and wait for command to be accepted
state <= 2 ;
end
end
else if (state == 2) begin // Now RST master and slave IODELAYs needed for simulation, not for the silicon
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
rst_data <= 1'b1 ;
state <= 3 ;
end
end
else if (state == 3) begin // Wait for IODELAY to be available
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
else if (state == 4) begin // Wait for occasional enable
if (counter[8] == 1'b1) begin
state <= 5 ;
end
end
else if (state == 5) begin // Calibrate slave only
if (busy_data_d == 1'b0) begin
cal_data_sint <= 1'b1 ;
state <= 6 ;
end
end
else if (state == 6) begin // Wait for command to be accepted
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b1) begin
state <= 7 ;
end
end
else if (state == 7) begin // Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
end
end
always @ (posedge gclk or posedge reset) // Per-bit phase detection state machine
begin
if (reset == 1'b1) begin
pdcounter <= 5'b1000 ;
ce_data_inta <= 1'b0 ;
flag <= 1'b0 ; // flag is there to only allow one inc or dec per cal (test)
end
else begin
busy_data_d <= busy_data_or[1] ;
if (use_phase_detector == 1'b1) begin // decide whther pd is used
incdec_data_d <= incdec_data_or[1] ;
valid_data_d <= valid_data_or[1] ;
if (ce_data_inta == 1'b1) begin
ce_data <= mux ;
end
else begin
ce_data <= 64'h0000000000000000 ;
end
if (state == 7) begin
flag <= 1'b0 ;
end
else if (state != 4 || busy_data_d == 1'b1) begin // Reset filter if state machine issues a cal command or unit is busy
pdcounter <= 5'b10000 ;
ce_data_inta <= 1'b0 ;
end
else if (pdcounter == 5'b11111 && flag == 1'b0) begin // Filter has reached positive max - increment the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b1 ;
pdcounter <= 5'b10000 ;
flag <= 1'b1 ;
end
else if (pdcounter == 5'b00000 && flag == 1'b0) begin // Filter has reached negative max - decrement the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b0 ;
pdcounter <= 5'b10000 ;
flag <= 1'b1 ;
end
else if (valid_data_d == 1'b1) begin // increment filter
ce_data_inta <= 1'b0 ;
if (incdec_data_d == 1'b1 && pdcounter != 5'b11111) begin
pdcounter <= pdcounter + 5'b00001 ;
end
else if (incdec_data_d == 1'b0 && pdcounter != 5'b00000) begin // decrement filter
pdcounter <= pdcounter + 5'b11111 ;
end
end
else begin
ce_data_inta <= 1'b0 ;
end
end
else begin
ce_data <= all_ce ;
inc_data_int <= debug_in[1] ;
end
end
end
assign inc_data = inc_data_int ;
assign incdec_data_or[0] = 1'b0 ; // Input Mux - Initialise generate loop OR gates
assign valid_data_or[0] = 1'b0 ;
assign busy_data_or[0] = 1'b0 ;
assign incdec_data_im = incdec_data & mux; // Input muxes
assign incdec_data_or[1] = incdec_data_im | incdec_data_or; // AND gates to allow just one signal through at a tome
assign valid_data_im = valid_data & mux; // followed by an OR
assign valid_data_or[1] = valid_data_im | valid_data_or; // for the three inputs from each PD
assign busy_data_or[1] = busy_data | busy_data_or; // The busy signals just need an OR gate
assign all_ce = debug_in[0] ;
IBUFDS #(
.DIFF_TERM (DIFF_TERM))
data_in (
.I (datain_p),
.IB (datain_n),
.O (rx_data_in)
);
//
// Master IDELAY
//
IODELAY2 #(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.IDELAY2_VALUE (0),
.IDELAY_MODE ("NORMAL" ),
.ODELAY_VALUE (0),
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), //("WRAPAROUND"),
.DELAY_SRC ("IDATAIN"),
.SERDES_MODE ("MASTER"),
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)
) iodelay_m (
.IDATAIN (rx_data_in), // data from IBUFDS
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (gclk), // Fabric clock (GCLK) for control signals
.CAL (cal_data_master), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY () // output signal indicating sync circuit has finished / calibration has finished
);
//
// Slave IDELAY
//
IODELAY2 #(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.IDELAY2_VALUE (0),
.IDELAY_MODE ("NORMAL" ),
.ODELAY_VALUE (0),
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),
.COUNTER_WRAPAROUND ("WRAPAROUND"),
.DELAY_SRC ("IDATAIN"),
.SERDES_MODE ("SLAVE"),
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)
) iodelay_s (
.IDATAIN (rx_data_in), // data from IBUFDS
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s), // Slave output data to ILOGIC/ISERDES2
.DATAOUT2 (), //
.IOCLK0 (rxioclk), // High speed IO clock for calibration
.IOCLK1 (1'b0),
.CLK (gclk), // Fabric clock (GCLK) for control signals
.CAL (cal_data_slave), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY (busys) // output signal indicating sync circuit has finished / calibration has finished
);
//
// Master ISERDES
//
ISERDES2 #(
.DATA_WIDTH (5),
.DATA_RATE ("SDR"),
.BITSLIP_ENABLE (BITSLIP_ENABLE),
.SERDES_MODE ("MASTER"),
.INTERFACE_TYPE ("RETIMED"))
iserdes_m (
.D (ddly_m),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rxserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.SHIFTIN (pd_edge),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (data_out[4]),
.Q3 (data_out[3]),
.Q2 (data_out[2]),
.Q1 (data_out[1]),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (valid_data),
.INCDEC (incdec_data),
.SHIFTOUT (cascade));
//
// Slave ISERDES
//
ISERDES2 #(
.DATA_WIDTH (5),
.DATA_RATE ("SDR"),
.BITSLIP_ENABLE (BITSLIP_ENABLE),
.SERDES_MODE ("SLAVE"),
.INTERFACE_TYPE ("RETIMED")
) iserdes_s (
.D (ddly_s),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rxserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.SHIFTIN (cascade),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (data_out[0]),
.Q3 (),
.Q2 (),
.Q1 (),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (),
.INCDEC (),
.SHIFTOUT (pd_edge));
reg [7:0] rxpdcntr = 8'h7f;
always @ (posedge gclk or posedge reset) begin
if (reset)
rxpdcntr <= 8'h7f;
else if (ce_data)
if (inc_data)
rxpdcntr <= rxpdcntr + 1'b1;
else
rxpdcntr <= rxpdcntr - 1'b1;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_32x16_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_32_32x16_be (
data,
wren,
wraddress,
rdaddress,
byteena_a,
wrclock,
rdclock,
q);
input [31:0] data;
input wren;
input [3:0] wraddress;
input [3:0] rdaddress;
input [3:0] byteena_a;
input wrclock;
input rdclock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.byteena_a (byteena_a),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 32,
altsyncram_component.widthad_a = 4,
altsyncram_component.numwords_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.widthad_b = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 4,
altsyncram_component.byte_size = 8,
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.power_up_uninitialized = "FALSE";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_wave*.jpg FALSE
|
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 4761 2008-12-27 01:11:00Z jnaous $
//
// Module: small_fifo.v
// Project: UNET
// Description: small fifo with no fallthrough i.e. data valid after rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 11/2/09 -- Modified to have both prog threshold and almost full
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
localparam MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk)
if (wr_en)
queue[wr_ptr] <= din;
always@(posedge clk)
if(reset)
dout<=0;
else if (rd_en)
dout <=queue[rd_ptr];
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <= depth + 'h1;
else if (~wr_en & rd_en) depth <=depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // small_fifo
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/);
// Note these are NOT pure.
import "DPI-C" function int dpii_clear ();
import "DPI-C" function int dpii_count (input int ctr);
import "DPI-C" function bit dpii_inc0 (input int ctr);
import "DPI-C" function bit dpii_inc1 (input int ctr);
import "DPI-C" function bit dpii_incx (input int ctr, input bit value);
integer i;
integer j;
integer k;
bit b;
integer errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
task check(integer line, int got, int ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
// Test loop
initial begin
// bug963
// verilator lint_off IGNOREDRETURN
dpii_clear();
// verilator lint_on IGNOREDRETURN
j = 0;
for (i=0; i<64; i++) begin
if (i[0])
j = 0;
else
j = {31'b0, dpii_inc1(0)};
k = k + j;
end
$write("%x\n",k);
check (`__LINE__, dpii_count(0), 32);
if (|errors) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
`ifndef VERILATOR
`error "Only Verilator supports PLI-ish DPI calls and sformat conversion."
`endif
import "DPI-C" context dpii_display_call
= function void \$dpii_display (input string formatted /*verilator sformat*/ );
integer a;
initial begin
// Check variable width constant string conversions
$dpii_display("");
$dpii_display("c");
$dpii_display("co");
$dpii_display("cons");
$dpii_display("constant");
$dpii_display("constant_value");
a = $c("10"); // Don't optimize away "a"
$display ("one10=%x ",a); // Check single arg
$dpii_display("one10=%x ",a);
$display ("Mod=%m 16=%d 10=%x ",a,a); // Check multiarg
$dpii_display("Mod=%m 16=%d 10=%x ",a,a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
`include "config.v"
module AXI2S
(
rst,
Sclk,
Sin,
Ien,
Sout,
Oen,
sync,
ibase,
isize,
obase,
osize,
iacnt,
ibcnt,
oacnt,
obcnt,
AXI_clk,
AXI_rst_n,
AXI_araddr,
AXI_arburst,
AXI_arcache,
AXI_arid,
AXI_arlen,
AXI_arlock,
AXI_arprot,
AXI_arqos,
AXI_arready,
AXI_arsize,
AXI_arvalid,
AXI_awaddr,
AXI_awburst,
AXI_awcache,
AXI_awid,
AXI_awlen,
AXI_awlock,
AXI_awprot,
AXI_awqos,
AXI_awready,
AXI_awsize,
AXI_awvalid,
AXI_bid,
AXI_bready,
AXI_bresp,
AXI_bvalid,
AXI_rdata,
AXI_rid,
AXI_rlast,
AXI_rready,
AXI_rresp,
AXI_rvalid,
AXI_wdata,
AXI_wid,
AXI_wlast,
AXI_wready,
AXI_wstrb,
AXI_wvalid
);
input rst;
input Sclk;
input [31:0]Sin;
input Ien;
output [31:0]Sout;
input Oen;
input sync;
input AXI_clk;
input AXI_rst_n;
output [31:0]AXI_araddr;
output [1:0]AXI_arburst;
output [3:0]AXI_arcache;
output [5:0]AXI_arid;
output [3:0]AXI_arlen;
output [1:0]AXI_arlock;
output [2:0]AXI_arprot;
output [3:0]AXI_arqos;
input AXI_arready;
output [2:0]AXI_arsize;
output AXI_arvalid;
output [31:0]AXI_awaddr;
output [1:0]AXI_awburst;
output [3:0]AXI_awcache;
output [5:0]AXI_awid;
output [3:0]AXI_awlen;
output [1:0]AXI_awlock;
output [2:0]AXI_awprot;
output [3:0]AXI_awqos;
input AXI_awready;
output [2:0]AXI_awsize;
output AXI_awvalid;
input [5:0]AXI_bid;
output AXI_bready;
input [1:0]AXI_bresp;
input AXI_bvalid;
input [31:0]AXI_rdata;
input [5:0]AXI_rid;
input AXI_rlast;
output AXI_rready;
input [1:0]AXI_rresp;
input AXI_rvalid;
output [31:0]AXI_wdata;
output [5:0]AXI_wid;
output AXI_wlast;
input AXI_wready;
output [3:0]AXI_wstrb;
output AXI_wvalid;
input [31:0]ibase;
input [31:0]obase;
input [23:6]isize;
input [23:6]osize;
output [23:6]iacnt;
output [23:6]oacnt;
output [31:0]ibcnt;
output [31:0]obcnt;
wire [4:0] Iaddr,Oaddr,s2a_addr,a2s_addr;
wire s2a_en,s2a_wea,a2s_en,a2s_wea;
wire [31:0] s2a_cnt,a2s_cnt;
assign s2a_wea = Ien;
assign a2s_wea = a2s_en;
blk_mem_axi2s s2axi (
.ena(Ien), // input wire ena
.wea(s2a_wea), // input wire [0 : 0] wea
.addra(Iaddr), // input wire [4 : 0] addra
.dina(Sin), // input wire [31 : 0] dina
.clka(Sclk), // input wire clka
.clkb(AXI_clk), // input wire clkb
.enb(s2a_en), // input wire enb
.addrb(s2a_addr), // input wire [4 : 0] addrb
.doutb(AXI_wdata) // output wire [31 : 0] doutb
);
blk_mem_axi2s axi2s (
.clka(AXI_clk), // input wire clka
.ena(a2s_en), // input wire ena
.wea(a2s_wea), // input wire [0 : 0] wea
.addra(a2s_addr), // input wire [4 : 0] addra
.dina(AXI_rdata), // input wire [31 : 0] dina
.clkb(Sclk), // input wire clkb
.enb(Oen), // input wire enb
.addrb(Oaddr), // input wire [4 : 0] addrb
.doutb(Sout) // output wire [31 : 0] doutb
);
assign AXI_arid = 6'b111111;
assign AXI_arlen = 4'hf;
assign AXI_arsize = 3'b010; //size: 4byte
assign AXI_arburst = 2'b01; //"01"; --incr
assign AXI_arlock = 2'b00; //"00";
assign AXI_arcache = 4'h0; //x"0";
assign AXI_arprot = 3'b000; //"000";
assign AXI_arqos = 4'h0; //x"0";
assign AXI_awid = 6'b111111;
assign AXI_wid = 6'b111111;
assign AXI_awlen = 4'hf; //x"F"; burst length: 16
assign AXI_awsize = 3'b010; //size: 4byte
assign AXI_awburst = 2'b01; //"01"; --incr
assign AXI_awlock = 2'b00; //"00";
assign AXI_awcache = 4'h0; //x"0";
assign AXI_awprot = 3'b000; //"000";
assign AXI_awqos = 4'h0; //x"0";
assign AXI_wstrb = 4'hf;
S2A_controller cs2a(
.Sclk(Sclk),
.rst(rst),
.sync(sync),
.Ien(Ien),
.Iaddr(Iaddr),
.ibase(ibase),
.isize(isize),
.iacnt(iacnt),
.ibcnt(ibcnt),
.AXI_clk(AXI_clk),
.AXI_rst_n(AXI_rst_n),
.AXI_awaddr(AXI_awaddr),
.AXI_awvalid(AXI_awvalid),
.AXI_awready(AXI_awready),
.AXI_wready(AXI_wready),
.AXI_wvalid(AXI_wvalid),
.AXI_wlast(AXI_wlast),
.s2a_addr(s2a_addr),
.s2a_en(s2a_en)
);
A2S_controller ca2s(
.rst(rst),
.Sclk(Sclk),
.sync(sync),
.Oen(Oen),
.Oaddr(Oaddr),
.obase(obase),
.osize(osize),
.oacnt(oacnt),
.obcnt(obcnt),
.AXI_clk(AXI_clk),
.AXI_rst_n(AXI_rst_n),
.AXI_araddr(AXI_araddr),
.AXI_arvalid(AXI_arvalid),
.AXI_arready(AXI_arready),
.AXI_rready(AXI_rready),
.AXI_rvalid(AXI_rvalid),
.AXI_rlast(AXI_rlast),
.a2s_addr(a2s_addr),
.a2s_en(a2s_en)
);
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 09:32:00 01/19/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #1 Demo
// Module Name: TF_EECS301_Lab1_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Test Bench Simulation for EECS301_Lab1_TopLevel
//
//
// Dependencies: EECS301_Lab1_TopLevel.v
//
//////////////////////////////////////////////////////////////////////////////////
module TF_EECS301_Lab1_TopLevel();
//
// Signal Declarations
//
// Signals must be declared before they are used so either
// declare everything at the top of the file or
// group the declarations with the code where they are first used.
//
reg CLOCK_50;
reg [3:0] KEY;
wire [9:0] LEDR;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
wire [6:0] HEX4;
wire [6:0] HEX5;
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal.
// The CLK_HALF_PER calculation converts Hz into ns for the clock period then
// divides by 2 so the signal is toggled twice per cycle.
//
localparam CLK_RATE_HZ = 50000000; // 50 MHz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: EECS301_Lab1_TopLevel
//
// This is the instantiation of the module being tested.
// Input signals
// CLOCK_50 1-bit 50MHz Clock
// KEY 4-bit Push Button Inputs (Active-Low)
// Output signals
// LEDR 10-bit Status LED Controls
// HEX0 7-bit Seven-Segment LED Controls (Active-Low)
// HEX1 7-bit Seven-Segment LED Controls (Active-Low)
// HEX2 7-bit Seven-Segment LED Controls (Active-Low)
// HEX3 7-bit Seven-Segment LED Controls (Active-Low)
// HEX4 7-bit Seven-Segment LED Controls (Active-Low)
// HEX5 7-bit Seven-Segment LED Controls (Active-Low)
EECS301_Lab1_TopLevel uut
(
// Clock Signals
.CLOCK_50( CLOCK_50 ),
// LED Signals
.LEDR( LEDR ),
// HEX LED Display Signals (Active-Low)
.HEX0( HEX0 ), // HEX LED Disp 0
.HEX1( HEX1 ), // HEX LED Disp 1
.HEX2( HEX2 ), // HEX LED Disp 2
.HEX3( HEX3 ), // HEX LED Disp 3
.HEX4( HEX4 ), // HEX LED Disp 4
.HEX5( HEX5 ), // HEX LED Disp 5
// Key Button Signals (Active-Low)
.KEY( KEY )
);
//
// Expected Key Value Computation
//
wire [3:0] exp_key_value;
wire [3:0] exp_key0_value = ~KEY[0] ? 4'h1 : 4'h0; // KEY[0] = 1
wire [3:0] exp_key1_value = ~KEY[1] ? 4'h2 : 4'h0; // KEY[1] = 2
wire [3:0] exp_key2_value = ~KEY[2] ? 4'h3 : 4'h0; // KEY[3] = 3
wire [3:0] exp_key3_value = ~KEY[3] ? 4'h4 : 4'h0; // KEY[4] = 4
assign exp_key_value = exp_key3_value + exp_key2_value + exp_key1_value + exp_key0_value;
//
// Expected LED Output Computation
//
// The expected LED output value is determined from the computed
// key value.
reg [9:0] exp_ledr_value;
always @*
begin
case (exp_key_value)
4'h0 : exp_ledr_value <= 10'b0000000000;
4'h1 : exp_ledr_value <= 10'b0000000001;
4'h2 : exp_ledr_value <= 10'b0000000011;
4'h3 : exp_ledr_value <= 10'b0000000111;
4'h4 : exp_ledr_value <= 10'b0000001111;
4'h5 : exp_ledr_value <= 10'b0000011111;
4'h6 : exp_ledr_value <= 10'b0000111111;
4'h7 : exp_ledr_value <= 10'b0001111111;
4'h8 : exp_ledr_value <= 10'b0011111111;
4'h9 : exp_ledr_value <= 10'b0111111111;
4'hA : exp_ledr_value <= 10'b1111111111;
default : exp_ledr_value <= 10'bxxxxxxxxxx; // Invalid Key Value
endcase
end
//
// Test Stimulus
//
// This process provides the main testing routine for the simulation.
// Note the use of blocking assignments for sequential process execution.
//
integer i;
reg [3:0] test_key_reg;
reg test_pass_fail;
initial
begin
// Initialize Signals
KEY = 4'hF; // The 4'hF value sets each of the four KEY bits high (off)
test_pass_fail = 1'b1;
test_key_reg = 4'h0;
// Delay for system to stabilize (in lieu of a Reset)
#1000; // Delay 1000 ns
/////////////////////////////////////////////////////
//
// Start Testing
//
//
// Simulate single button presses
//
// Each of the four Keys are individually pressed for 1000ns.
// The LEDR output is verified 100ns after the key press starts.
// There is 1000ns between Key Press tests.
//
// The $display function prints messages to the terminal message log
$display("Single Button Press Tests");
// Press Key 1
KEY[0] = 1'b0; // Press Key (KEY is indexed so only bit 0 is changed)
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0; // This uses the ternary if-then-else operation
if (test_pass_fail)
$display(" KEY[0] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[0] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[0] = 1'b1; // Release Key
#1000;
// Press Key 2
KEY[1] = 1'b0; // Press Key
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY[1] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[1] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[1] = 1'b1; // Release Key
#1000;
// Press Key 3
KEY[2] = 1'b0; // Press Key
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY[2] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[2] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[2] = 1'b1; // Release Key
#1000;
// Press Key 4
KEY[3] = 1'b0; // Press Key
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY[3] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[3] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[3] = 1'b1; // Release Key
#2000;
//
// Run thorough all KEY input combinations
//
// The same test routine is used in a loop to test every possible key
// press combination for full coverage verification.
$display("Full Coverage Key Press Tests");
test_key_reg = 4'h0;
for (i=0; i < 16; i=i+1)
begin
// Assign the test pattern to the KEY input
KEY = ~test_key_reg; // KEY is active-low so invert the test pattern
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY Pattern [%04b] Press Passed. Key Value = %d", test_key_reg, exp_key_value);
else
$display(" KEY Pattern [%04b] Press FAILED!!! Expected [%010b] != Actual [%010b]", test_key_reg, exp_ledr_value, LEDR);
#900;
KEY = 4'hF; // Release All Keys
#1000;
// Next Test Key Pattern
test_key_reg = test_key_reg + 1'b1;
end
KEY = 4'hF; // Release All Keys
//
// Add another Key Test Pattern here...
KEY = 4'h5; // Press Key (KEY is indexed so only bit 0 is changed)
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0; // This uses the ternary if-then-else operation
if (test_pass_fail)
$display(" KEY[0] and KEY[2] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[0] and KEY[2] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY = 4'hF; // Release Key
//
#2000;
$finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sin_taylor_seriesdEe
#(parameter
ID = 7,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
sin_taylor_series_ap_dadd_3_full_dsp_64 sin_taylor_series_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
`define ADDER_WIDTH 005
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
module erx_core (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, idelay_value, load_taps, rxrd_access,
rxrd_packet, rxrr_access, rxrr_packet, rxwr_access, rxwr_packet,
erx_cfg_wait, mailbox_irq,
// Inputs
nreset, clk, rx_packet, rx_access, rx_burst, rxrd_wait, rxrr_wait,
rxwr_wait, erx_cfg_access, erx_cfg_packet
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h999;
parameter TARGET = "GENERIC";
//clock and reset
input nreset; //synced to clk
input clk;
//IO Interface
input [PW-1:0] rx_packet;
input rx_access;
input rx_burst;
output rx_rd_wait;
output rx_wr_wait;
output [44:0] idelay_value;
output load_taps;
//FIFO Access
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//register interface
input erx_cfg_access;
input [PW-1:0] erx_cfg_packet;
output erx_cfg_wait;
//mailbox outputs
output mailbox_irq;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dma_access; // From erx_cfg of erx_cfg.v
wire ecfg_access; // From erx_cfg of erx_cfg.v
wire [PW-1:0] ecfg_packet; // From erx_cfg of erx_cfg.v
wire edma_wait; // From erx_arbiter of erx_arbiter.v
wire emesh_remap_access; // From erx_remap of erx_remap.v
wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v
wire emmu_access; // From erx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From erx_mmu of emmu.v
wire erx_access; // From erx_protocol of erx_protocol.v
wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
wire mailbox_access; // From erx_cfg of erx_cfg.v
wire mailbox_irq_en; // From erx_cfg of erx_cfg.v
wire [31:0] mailbox_rdata; // From erx_mailbox of emailbox.v
wire mailbox_wait; // From erx_mailbox of emailbox.v
wire mmu_access; // From erx_cfg of erx_cfg.v
wire mmu_enable; // From erx_cfg of erx_cfg.v
wire [31:0] remap_base; // From erx_cfg of erx_cfg.v
wire [1:0] remap_mode; // From erx_cfg of erx_cfg.v
wire [11:0] remap_pattern; // From erx_cfg of erx_cfg.v
wire [11:0] remap_sel; // From erx_cfg of erx_cfg.v
wire test_mode; // From erx_cfg of erx_cfg.v
// End of automatics
//regs
wire [8:0] gpio_datain;
wire [15:0] rx_status;
wire rxwr_full;
wire rxrr_full;
wire rxrd_full;
wire rxrd_empty;
wire rxwr_empty;
wire rxrr_empty;
wire [103:0] edma_packet;
/**************************************************************/
/*ELINK PROTOCOL LOGIC */
/**************************************************************/
erx_protocol #(.ID(ID))
erx_protocol (/*AUTOINST*/
// Outputs
.erx_access (erx_access),
.erx_packet (erx_packet[PW-1:0]),
// Inputs
.clk (clk),
.test_mode (test_mode),
.rx_packet (rx_packet[PW-1:0]),
.rx_burst (rx_burst),
.rx_access (rx_access));
/**************************************************************/
/*ADDRESS REMPAPPING */
/**************************************************************/
/*erx_remap AUTO_TEMPLATE (
.emesh_\(.*\)_out (emesh_remap_\1[]),
//Inputs
.emesh_access_in (erx_access),
.emesh_\(.*\)_in (erx_\1[]),
.mmu_en (ecfg_rx_mmu_enable),
.emesh_packet_hi_out (),
);
*/
erx_remap #(.ID(ID))
erx_remap (/*AUTOINST*/
// Outputs
.emesh_access_out (emesh_remap_access), // Templated
.emesh_packet_out (emesh_remap_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.emesh_access_in (erx_access), // Templated
.emesh_packet_in (erx_packet[PW-1:0]), // Templated
.remap_mode (remap_mode[1:0]),
.remap_sel (remap_sel[11:0]),
.remap_pattern (remap_pattern[11:0]),
.remap_base (remap_base[31:0]));
/************************************************************/
/*ELINK MEMORY MANAGEMENT UNIT */
/************************************************************/
/*emmu AUTO_TEMPLATE (.reg_access (mmu_access),
.reg_packet (erx_cfg_packet[PW-1:0]),
.emesh_\(.*\)_out (emmu_\1[]),
.emesh_\(.*\)_in (emesh_remap_\1[]),
.mmu_en (mmu_enable),
.\(.*\)_clk (clk),
);
*/
emmu erx_mmu (.emesh_wait_in (1'b0),
.reg_rdata (),
/*AUTOINST*/
// Outputs
.emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
// Inputs
.nreset (nreset),
.mmu_en (mmu_enable), // Templated
.wr_clk (clk), // Templated
.reg_access (mmu_access), // Templated
.reg_packet (erx_cfg_packet[PW-1:0]), // Templated
.rd_clk (clk), // Templated
.emesh_access_in (emesh_remap_access), // Templated
.emesh_packet_in (emesh_remap_packet[PW-1:0])); // Templated
/************************************************************/
/*EMAILBOX */
/************************************************************/
/*emailbox AUTO_TEMPLATE (
.mi_en (mi_cfg_en),
.mi_dout (mi_mailbox_dout[]),
.\(.*\)_clk (clk),
.emesh_\(.*\) (emmu_\1[]),
.reg_access (mailbox_access),
.reg_rdata (mailbox_rdata[31:0]),
.reg_packet (erx_cfg_packet[PW-1:0]),
);
*/
emailbox #(.ID(ID), .TARGET(TARGET))
erx_mailbox(
/*AUTOINST*/
// Outputs
.reg_rdata (mailbox_rdata[31:0]), // Templated
.mailbox_irq (mailbox_irq),
.mailbox_wait (mailbox_wait),
// Inputs
.nreset (nreset),
.wr_clk (clk), // Templated
.rd_clk (clk), // Templated
.emesh_access (emmu_access), // Templated
.emesh_packet (emmu_packet[PW-1:0]), // Templated
.reg_access (mailbox_access), // Templated
.reg_packet (erx_cfg_packet[PW-1:0]), // Templated
.mailbox_irq_en (mailbox_irq_en));
/************************************************************/
/* ERX CONFIGURATION */
/************************************************************/
erx_cfg erx_cfg (.gpio_datain (9'b0),
.rx_status ({11'b0,
rx_rd_wait,
rx_wr_wait,
rxrr_wait,
rxrd_wait,
rxwr_wait
}
),
.edma_rdata (32'b0),
/*AUTOINST*/
// Outputs
.mmu_access (mmu_access),
.dma_access (dma_access),
.mailbox_access (mailbox_access),
.ecfg_access (ecfg_access),
.ecfg_packet (ecfg_packet[PW-1:0]),
.mmu_enable (mmu_enable),
.remap_mode (remap_mode[1:0]),
.remap_base (remap_base[31:0]),
.remap_pattern (remap_pattern[11:0]),
.remap_sel (remap_sel[11:0]),
.idelay_value (idelay_value[44:0]),
.load_taps (load_taps),
.test_mode (test_mode),
.mailbox_irq_en (mailbox_irq_en),
// Inputs
.nreset (nreset),
.clk (clk),
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
.mailbox_rdata (mailbox_rdata[31:0]),
.erx_access (erx_access),
.erx_packet (erx_packet[PW-1:0]));
/************************************************************/
/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
/*(figures out who RX transaction belongs to) */
/************************************************************/
/*erx_arbiter AUTO_TEMPLATE (
//Inputs
.mmu_en (ecfg_rx_mmu_enable),
.ecfg_wait (erx_cfg_wait),
.erx_access (emmu_access),
.erx_packet (emmu_packet[PW-1:0]),
)
*/
erx_arbiter #(.ID(ID))
erx_arbiter (.edma_access (1'b0),
.edma_packet ({(PW){1'b0}}),
/*AUTOINST*/
// Outputs
.rx_rd_wait (rx_rd_wait),
.rx_wr_wait (rx_wr_wait),
.edma_wait (edma_wait),
.ecfg_wait (erx_cfg_wait), // Templated
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
// Inputs
.erx_access (emmu_access), // Templated
.erx_packet (emmu_packet[PW-1:0]), // Templated
.mailbox_wait (mailbox_wait),
.ecfg_access (ecfg_access),
.ecfg_packet (ecfg_packet[PW-1:0]),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait));
endmodule // erx_core
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
// End:
|
module lsu_bursting_read
(
clk, clk2x, reset, flush, i_nop, o_stall, i_valid, i_address, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid,
avm_burstcount,
// Profiling
extra_unaligned_reqs,
req_cache_hit_count
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=8; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=64; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=$clog2(WIDTH_BYTES); // Request address alignment (address bits)
parameter DEVICE = "Stratix V"; // DEVICE
parameter BURSTCOUNT_WIDTH=5; // MAX BURST = 2**(BURSTCOUNT_WIDTH-1)
parameter KERNEL_SIDE_MEM_LATENCY=1; // Effective Latency in cycles as seen by the kernel pipeline
parameter MEMORY_SIDE_MEM_LATENCY = 1; // Latency in cycles between LSU and memory
parameter MAX_THREADS=64; // Maximum # of threads to group into a burst request
parameter TIME_OUT=8; // Time out counter max
parameter USECACHING = 0; // Enable internal cache
parameter CACHE_SIZE_N=1024; // Cache depth (width = WIDTH_BYTES)
parameter ACL_PROFILE = 0; // Profiler
parameter HIGH_FMAX = 1; // Add pipeline to io if set to 1
parameter UNALIGNED = 0; // Output word unaligned
/*****************
* Local Parameters *
*****************/
localparam MAX_BURST = 2**(BURSTCOUNT_WIDTH-1);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam A_BYTES = 2**ALIGNMENT_ABITS;
localparam WORD_BYTES = (WIDTH_BYTES >= A_BYTES & (UNALIGNED == 0))? WIDTH_BYTES : A_BYTES;
localparam NUM_WORD = MWIDTH_BYTES / WORD_BYTES;
localparam MB_W=$clog2(MWIDTH_BYTES);
localparam OB_W = $clog2(WIDTH_BYTES);
localparam PAGE_ADDR_WIDTH = AWIDTH - MB_W;
localparam OFFSET_WIDTH = $clog2(NUM_WORD);
localparam CACHE_ADDR_W=$clog2(CACHE_SIZE_N);
localparam CACHE_BASE_ADDR_W = AWIDTH-MB_W-CACHE_ADDR_W;
localparam UNALIGNED_DIV_ALIGN = WIDTH_BYTES / A_BYTES;
localparam UNALIGNED_SELECTION_BITS=$clog2(UNALIGNED_DIV_ALIGN);
// Standard global signals
input clk;
input clk2x;
input reset;
input flush;
input i_nop;
// Upstream interface
output logic o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// Profiling
output logic extra_unaligned_reqs;
output logic req_cache_hit_count;
// internal signals
logic stall_pre;
wire reg_valid;
wire reg_nop;
wire [AWIDTH-1:0] reg_address;
// registed to help P&R
logic R_valid, R_nop;
wire [AWIDTH-1:0] addr_next_wire;
logic [AWIDTH-1:0] R_addr, R_addr_next, R_addr_next_hold;
// cache status
reg [CACHE_BASE_ADDR_W:0] cache [CACHE_SIZE_N] /* synthesis ramstyle = "M20K" */;
wire [1:0] in_cache_pre;
logic [CACHE_BASE_ADDR_W-1:0] cached_tag [2];
wire [CACHE_BASE_ADDR_W-1:0] R_tag [2];
wire [CACHE_ADDR_W-1:0] rd_c_index [2];
wire [CACHE_ADDR_W-1:0] wr_c_index;
logic cached_tag_valid [2];
wire tag_match [2];
wire consecutive;
reg cache_ready;
logic [1:0] in_cache;
wire [MB_W-1:0] byte_offset;
reg include_2nd_part;
logic update_cache;
logic [CACHE_BASE_ADDR_W-1:0] new_tag;
logic issue_2nd_word;
reg issue_2nd_hold;
logic need_2_page;
wire stall_int;
wire need_2_cc;
wire [UNALIGNED_SELECTION_BITS-1:0] shift;
logic [AWIDTH-1:0] lsu_i_address;
reg p_valid;
reg [AWIDTH-1:0] p_addr;
reg [1:0] R_consecutive;
reg [63:0] non_align_hit_cache;
// coalesced addr
wire [BURSTCOUNT_WIDTH-1:0]c_burstcount;
wire [PAGE_ADDR_WIDTH-1:0] c_page_addr;
wire c_req_valid;
wire c_new_page;
logic [OFFSET_WIDTH-1 : 0] p_offset, c_word_offset;
logic p_offset_valid;
reg [CACHE_ADDR_W-1:0] R_cache_addr;
// fifo
reg fifo_din_en;
reg [1:0] fi_in_cache;
reg [CACHE_ADDR_W-1:0] fi_cached_addr;
reg [UNALIGNED_SELECTION_BITS-1:0] fi_shift;
reg fi_second, fi_2nd_valid;
reg [UNALIGNED_SELECTION_BITS-1:0] R_shift;
reg [MB_W-1:0] fi_byte_offset;
wire p_ae;
generate
if(HIGH_FMAX) begin: GEN_PIPE_INPUT
acl_io_pipeline #(
.WIDTH(1+AWIDTH)
) in_pipeline (
.clk(clk),
.reset(reset),
.i_stall(stall_pre),
.i_valid(i_valid),
.i_data({i_nop, i_address}),
.o_stall(o_stall),
.o_valid(reg_valid),
.o_data({reg_nop, reg_address})
);
end
else begin : GEN_FAST_INPUT
assign {reg_valid, reg_nop, reg_address} = {i_valid, i_nop, i_address};
end
if(USECACHING) begin : GEN_ENABLE_CACHE
reg R_flush;
reg [CACHE_ADDR_W:0] flush_cnt;
reg cache_status_ready;
assign rd_c_index[0] = R_addr[CACHE_ADDR_W-1+MB_W:MB_W];
assign rd_c_index[1] = R_addr_next[CACHE_ADDR_W-1+MB_W:MB_W];
assign {cached_tag_valid[0], cached_tag[0]} = cache[rd_c_index[0]];
assign {cached_tag_valid[1], cached_tag[1]} = cache[rd_c_index[1]];
assign wr_c_index = lsu_i_address[CACHE_ADDR_W-1+MB_W:MB_W];
assign R_tag[0] = R_addr[AWIDTH-1:MB_W+CACHE_ADDR_W];
assign R_tag[1] = R_addr_next[AWIDTH-1:MB_W+CACHE_ADDR_W];
assign tag_match[0] = cached_tag[0] == R_tag[0] & cached_tag_valid[0] === 1'b1;
assign tag_match[1] = cached_tag[1] == R_tag[1] & cached_tag_valid[1] === 1'b1;
assign in_cache_pre[0] = tag_match[0] & !issue_2nd_word & cache_ready;
assign in_cache_pre[1] = tag_match[1] & !issue_2nd_word & cache_ready;
assign new_tag = lsu_i_address[AWIDTH-1:MB_W+CACHE_ADDR_W];
assign update_cache = R_valid & !R_nop | issue_2nd_word;
always @(posedge clk or posedge reset) begin
if(reset) cache_status_ready <= 1'b0;
else cache_status_ready <= flush_cnt[CACHE_ADDR_W];
end
always @ (posedge clk) begin
R_flush <= flush;
if(flush & !R_flush) flush_cnt <= '0;
else if(!flush_cnt[CACHE_ADDR_W]) flush_cnt <= flush_cnt + 1'b1;
cache_ready <= flush_cnt[CACHE_ADDR_W];
if(!flush_cnt[CACHE_ADDR_W]) cache[flush_cnt] <= '0;
else if(update_cache) cache[wr_c_index] <= {1'b1, new_tag};
in_cache[0] <= R_valid & (in_cache_pre[0] | R_nop) & !issue_2nd_word;
in_cache[1] <= UNALIGNED? R_valid & (in_cache_pre[1] | R_nop) & !issue_2nd_word & need_2_page : 1'b0;
include_2nd_part <= issue_2nd_word | in_cache_pre[1] & need_2_page;
p_valid <= issue_2nd_word | R_valid & !in_cache_pre[0] & !R_nop; // not include nop
p_offset_valid <= issue_2nd_word | R_valid;
p_addr <= lsu_i_address;
R_cache_addr <= lsu_i_address[MB_W+CACHE_ADDR_W-1:MB_W];
end
if(OFFSET_WIDTH > 0) begin
always @ (posedge clk) begin
p_offset <= R_addr[MB_W-1:MB_W-OFFSET_WIDTH];
end
end
if(ACL_PROFILE == 1) begin
assign req_cache_hit_count = ((|fi_in_cache) & fifo_din_en);
end
else
begin
assign req_cache_hit_count = 1'b0;
end
end // end GEN_ENABLE_CACHE
else begin : GEN_DISABLE_CACHE
assign req_cache_hit_count = 1'b0;
assign in_cache_pre = 2'b0;
assign in_cache = 2'b0;
assign include_2nd_part = issue_2nd_word;
assign p_valid = issue_2nd_word | R_valid & !R_nop; // not include nop
assign p_offset_valid = issue_2nd_word | R_valid;
assign p_addr = lsu_i_address;
if(OFFSET_WIDTH > 0) begin
assign p_offset = R_addr[MB_W-1:MB_W-OFFSET_WIDTH];
end
end // end GEN_DISABLE_CACHE
if (UNALIGNED) begin : GEN_UNALIGN
assign addr_next_wire[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH] = reg_address[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH]+1'b1;
assign addr_next_wire[AWIDTH-PAGE_ADDR_WIDTH-1:0] = '0;
// Look at the higher bits to determine how much we need to shift the two aligned accesses
wire [UNALIGNED_SELECTION_BITS-1:0] temp = NUM_WORD - R_addr[AWIDTH-1:ALIGNMENT_ABITS];
assign shift = UNALIGNED_DIV_ALIGN - temp;
assign consecutive = reg_nop | reg_address[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH] == R_addr_next[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH];
// When do we need to issue the 2nd word ?
// The previous address needed a 2nd page and
// [1] the current requested address isn't in the (previous+1)th page and
// [2] The second page is not in the cache
assign need_2_cc = need_2_page & !in_cache_pre[1] & R_valid & (!issue_2nd_word | R_consecutive[0]); // need 2 clock cycles to combine segments from 2 pages
// simulation only
assign byte_offset = stall_pre? R_addr[MB_W-1:0] : reg_address[MB_W-1:0];
always @(posedge clk or posedge reset) begin
if(reset) begin
issue_2nd_word <= 1'b0;
R_consecutive <= 'x;
stall_pre <= 1'b0;
issue_2nd_hold <= 'x;
end
else begin
issue_2nd_word <= need_2_cc;
if(!stall_pre | issue_2nd_word) issue_2nd_hold <= need_2_cc;
R_consecutive[0] <= reg_valid & !stall_int & consecutive & need_2_cc;
R_consecutive[1] <= R_consecutive[0];
stall_pre <= (stall_int | need_2_cc & reg_valid & !consecutive);
end
end
always @(posedge clk) begin
if(reg_valid & !stall_pre) need_2_page <= !reg_nop & (reg_address[MB_W-1:0] + WIDTH_BYTES) > MWIDTH_BYTES;
if(reg_valid & !stall_pre & !reg_nop) begin
R_addr <= reg_address;
R_addr_next <= addr_next_wire;
end
R_addr_next_hold <= R_addr_next;
if(!issue_2nd_word | !stall_pre) begin
R_valid <= reg_valid & !stall_pre;
R_nop <= reg_nop;
end
end
if(ACL_PROFILE == 1) begin
assign extra_unaligned_reqs = need_2_cc & reg_valid & !consecutive;
always @(posedge clk or posedge reset) begin
if(reset) begin
non_align_hit_cache <= '0;
end
else begin
non_align_hit_cache <= non_align_hit_cache + (need_2_page & in_cache_pre[1] & R_valid & (!issue_2nd_word | R_consecutive[0]) & reg_valid & !consecutive);
end
end
end // end ACL_PROFILE == 1
end // end GEN_UNALIGN
else begin : GEN_ALIGN
assign issue_2nd_word = 1'b0;
assign need_2_page = 1'b0;
assign R_addr = reg_address;
assign R_valid = reg_valid & !stall_int;
assign R_nop = reg_nop;
assign stall_pre = stall_int;
end // end GEN_ALIGN
endgenerate
assign lsu_i_address = issue_2nd_word ? R_addr_next_hold : R_addr;
always @(posedge clk) begin
c_word_offset <= p_offset;
R_shift <= need_2_page? shift : '0;
fifo_din_en <= (|in_cache) | p_offset_valid;
{fi_in_cache, fi_cached_addr, fi_second} <= {in_cache, R_cache_addr, include_2nd_part};
if(!include_2nd_part) fi_byte_offset <= p_addr[MB_W-1:0];
fi_shift <= USECACHING? R_shift : (need_2_page? shift : '0);
fi_2nd_valid <= USECACHING? R_consecutive[1] : R_consecutive[0];
end
acl_stall_free_coalescer #(
.AW(AWIDTH),
.PAGE_AW(PAGE_ADDR_WIDTH),
.MAX_BURST(MAX_BURST),
.TIME_OUT(TIME_OUT),
.CACHE_LAST(USECACHING),
.MAX_THREAD(MAX_THREADS),
.DISABLE_COALESCE(0)
) coalescer(
.clk(clk),
.reset(reset),
.i_valid(p_valid),
.i_addr(p_addr),
.i_empty(p_ae),
.o_page_addr(c_page_addr),
.o_page_addr_valid(c_req_valid),
.o_num_burst(c_burstcount),
.o_new_page(c_new_page)
);
lsu_bursting_pipelined_read #(
.INPUT_AW(PAGE_ADDR_WIDTH),
.AWIDTH(AWIDTH),
.WIDTH(WIDTH),
.MWIDTH(MWIDTH),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.DEVICE(DEVICE),
.CACHE_SIZE_N(CACHE_SIZE_N),
.USECACHING(USECACHING),
.UNALIGNED(UNALIGNED),
.UNALIGNED_SHIFT_WIDTH(UNALIGNED_SELECTION_BITS),
.MAX_BURST(MAX_BURST),
.INCLUDE_BYTE_OFFSET(0), // sim-only
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) pipelined_read(
.clk (clk),
.reset (reset),
.i_address (c_page_addr),
.i_addr_valid (c_req_valid),
.i_burst_count (c_burstcount),
.i_new_page (c_new_page),
.i_word_offset (c_word_offset),
.i_byte_offset (fi_byte_offset),
.i_in_cache (fi_in_cache),
.i_cache_addr (fi_cached_addr),
.i_shift (fi_shift),
.i_second (fi_second),
.i_2nd_valid (fi_2nd_valid), // has two segments' info in one cc
.i_word_offset_valid(fifo_din_en),
.i_stall (i_stall),
.o_ae (p_ae),
.o_empty (p_empty),
.o_readdata (o_readdata),
.o_valid (o_valid),
.o_stall (stall_int),
.avm_address (avm_address),
.avm_read (avm_read),
.avm_readdata (avm_readdata),
.avm_waitrequest (avm_waitrequest),
.avm_byteenable (avm_byteenable),
.avm_readdatavalid(avm_readdatavalid),
.avm_burstcount (avm_burstcount)
);
endmodule
module acl_io_pipeline #(
parameter WIDTH = 1
)(
input clk,
input reset,
input i_stall,
input i_valid,
input [WIDTH-1:0] i_data,
output o_stall,
output reg o_valid,
output reg [WIDTH-1:0] o_data
);
reg R_valid;
assign o_stall = i_stall & R_valid;
always@(posedge clk) begin
if(!o_stall) {o_valid, o_data} <= {i_valid, i_data};
end
always@(posedge clk or posedge reset)begin
if(reset) R_valid <= 1'b0;
else if(!o_stall) R_valid <= i_valid;
end
endmodule
module lsu_bursting_pipelined_read
(
clk, reset,
i_in_cache,
i_cache_addr,
i_addr_valid,
i_address,
i_burst_count,
i_word_offset,
i_byte_offset,
i_shift,
i_second,
i_2nd_valid,
i_word_offset_valid,
i_new_page,
o_readdata,
o_valid,
i_stall,
o_stall,
o_empty,
o_ae,
avm_address,
avm_read,
avm_readdata,
avm_waitrequest,
avm_byteenable,
avm_burstcount,
avm_readdatavalid
);
parameter INPUT_AW = 32;
parameter AWIDTH=32;
parameter WIDTH=32;
parameter MWIDTH=512;
parameter MAX_BURST = 16;
parameter ALIGNMENT_ABITS=2;
parameter DEVICE = "Stratix V";
parameter MEMORY_SIDE_MEM_LATENCY=160;
parameter USECACHING = 0;
parameter CACHE_SIZE_N = 1024;
parameter UNALIGNED = 0;
parameter UNALIGNED_SHIFT_WIDTH = 0;
parameter INCLUDE_BYTE_OFFSET = 0; // testing purpose
localparam ALIGNMENT_WIDTH = 2**ALIGNMENT_ABITS * 8;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH/8);
localparam WORD_WIDTH = (WIDTH >= ALIGNMENT_WIDTH & (UNALIGNED == 0))? WIDTH : ALIGNMENT_WIDTH;
localparam NUM_WORD = MWIDTH / WORD_WIDTH;
localparam OFFSET_WIDTH = (NUM_WORD==1)? 1 : $clog2(NUM_WORD);
localparam WIDE_FIFO_DEPTH = (MEMORY_SIDE_MEM_LATENCY < 256)? 256 : MEMORY_SIDE_MEM_LATENCY;
localparam OFFSET_FIFO_DEPTH = (MEMORY_SIDE_MEM_LATENCY <= 246)? 256 : MEMORY_SIDE_MEM_LATENCY + 10;
localparam REQUEST_FIFO_DEPTH = OFFSET_FIFO_DEPTH;
localparam WIDE_FIFO_DEPTH_THRESH = MEMORY_SIDE_MEM_LATENCY;
localparam WIDE_FIFO_AW = $clog2(WIDE_FIFO_DEPTH);
localparam BURST_CNT_WIDTH = (MAX_BURST == 1)? 1 : $clog2(MAX_BURST + 1);
localparam REQUEST_FIFO_AW = $clog2(REQUEST_FIFO_DEPTH);
localparam OFFSET_FIFO_AW = $clog2(OFFSET_FIFO_DEPTH);
localparam REQUEST_FIFO_WIDTH = INPUT_AW + BURST_CNT_WIDTH;
localparam CACHE_SIZE_LOG2N=$clog2(CACHE_SIZE_N);
localparam CACHE_ADDR_W=$clog2(CACHE_SIZE_N);
localparam OFFSET_FIFO_WIDTH = 1 + ((NUM_WORD > 1)? OFFSET_WIDTH : 0) + (USECACHING? 1 + CACHE_ADDR_W : 0) + (UNALIGNED? UNALIGNED_SHIFT_WIDTH + 3 : 0) + (INCLUDE_BYTE_OFFSET? BYTE_SELECT_BITS : 0);
// I/O
input clk, reset;
input [UNALIGNED:0] i_in_cache;
input [CACHE_ADDR_W-1:0] i_cache_addr;
input [INPUT_AW-1:0] i_address;
input [BURST_CNT_WIDTH-1:0] i_burst_count;
input [OFFSET_WIDTH-1:0] i_word_offset;
input [BYTE_SELECT_BITS-1:0] i_byte_offset; // simulation
input [UNALIGNED_SHIFT_WIDTH-1:0] i_shift; // used only when UNALIGNED = 1
input i_second; // used only when UNALIGNED = 1
input i_2nd_valid; // used only when UNALIGNED = 1
input i_word_offset_valid;
input i_new_page;
input i_addr_valid;
input i_stall;
output logic [WIDTH-1:0] o_readdata;
output logic o_valid;
output reg o_stall;
output reg o_empty;
output o_ae;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output reg avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH/8-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURST_CNT_WIDTH-1:0] avm_burstcount;
// offset fifo
wire [OFFSET_FIFO_WIDTH-1:0] offset_fifo_din;
wire [OFFSET_FIFO_WIDTH-1:0] offset_fifo_dout;
// req FIFO
wire rd_req_en;
wire req_fifo_ae, req_fifo_af, req_overflow, offset_overflow, rd_req_empty; // FIFO status
// end req FIFO
// output FIFO
wire rd_data_fifo;
reg R_rd_data;
wire rd_data_empty;
wire rd_offset;
wire offset_fifo_empty;
wire offset_af;
wire [UNALIGNED:0] d_in_cache;
wire rd_next_page;
wire [CACHE_ADDR_W-1:0] d_cache_addr;
wire [BYTE_SELECT_BITS-1:0] d_byte_offset; // for simulation
reg R_in_cache;
wire d_second, d_2nd_valid;
wire unalign_stall_offset, unalign_stall_data;
wire [UNALIGNED_SHIFT_WIDTH-1:0] d_shift;
wire [OFFSET_WIDTH-1 : 0] d_offset;
reg [OFFSET_WIDTH-1 : 0] R_offset;
reg [MWIDTH-1:0] R_avm_rd_data;
wire [MWIDTH-1:0] rd_data;
// end output FIFO
assign avm_address[AWIDTH - INPUT_AW - 1 : 0] = 0;
assign avm_byteenable = {(MWIDTH/8){1'b1}};
assign o_ae = req_fifo_ae;
assign rd_req_en = !avm_read | !avm_waitrequest;
always @(posedge clk or posedge reset) begin
if(reset) begin
o_empty = 1'b0;
avm_read <= 1'b0;
o_stall <= 1'b0;
end
else begin
o_empty <= rd_req_empty;
o_stall <= offset_af;
if(rd_req_en) avm_read <= !rd_req_empty;
end
end
generate
if(NUM_WORD > 1) begin : GEN_WORD_OFFSET_FIFO
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (OFFSET_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (OFFSET_FIFO_WIDTH),
.lpm_widthu (OFFSET_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON"),
.almost_full_value(OFFSET_FIFO_DEPTH - 10)
) offset_fifo (
.clock (clk),
.data (offset_fifo_din),
.wrreq (i_word_offset_valid),
.rdreq (rd_offset),
.usedw (offset_flv),
.empty (offset_fifo_empty),
.full (offset_overflow),
.q (offset_fifo_dout),
.almost_empty (),
.almost_full (offset_af),
.aclr (reset)
);
end
else begin : GEN_SINGLE_WORD_RD_NEXT
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (OFFSET_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (OFFSET_FIFO_WIDTH),
.lpm_widthu (OFFSET_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "OFF"), // not instantiate block ram
.almost_full_value(OFFSET_FIFO_DEPTH - 10)
) offset_fifo (
.clock (clk),
.data (offset_fifo_din),
.wrreq (i_word_offset_valid),
.rdreq (rd_offset),
.usedw (offset_flv),
.empty (offset_fifo_empty),
.full (offset_overflow),
.q (offset_fifo_dout),
.almost_empty (),
.almost_full (offset_af),
.aclr (reset)
);
end
endgenerate
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (REQUEST_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (REQUEST_FIFO_WIDTH),
.lpm_widthu (REQUEST_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON"),
.almost_full_value(20),
.almost_empty_value(3)
) rd_request_fifo (
.clock (clk),
.data ({i_address, i_burst_count}),
.wrreq (i_addr_valid),
.rdreq (rd_req_en),
.usedw (),
.empty (rd_req_empty),
.full (req_overflow),
.q ({avm_address[AWIDTH - 1: AWIDTH - INPUT_AW], avm_burstcount}),
.almost_empty (req_fifo_ae),
.almost_full (req_fifo_af),
.aclr (reset)
);
/*------------------------------
Generate output data
--------------------------------*/
reg offset_valid;
reg [1:0] o_valid_pre;
wire rd_next_page_en, downstream_stall, wait_data, offset_stall, data_stall, valid_hold;
generate
if(USECACHING) begin : ENABLE_CACHE
reg [MWIDTH-1:0] cache [CACHE_SIZE_N] /* synthesis ramstyle = "no_rw_check, M20K" */;
logic [MWIDTH-1:0] reused_data[2] ;
reg [CACHE_ADDR_W-1:0] R_cache_addr, R_cache_next;
if(NUM_WORD == 1) begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_2nd_valid, i_shift, i_second, i_cache_addr, i_in_cache, i_new_page};
assign {d_2nd_valid, d_shift, d_second, d_cache_addr, d_in_cache, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
else begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_byte_offset, i_2nd_valid, i_shift, i_second, i_word_offset, i_cache_addr, i_in_cache, i_new_page};
assign {d_byte_offset, d_2nd_valid, d_shift, d_second, d_offset, d_cache_addr, d_in_cache, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
if(UNALIGNED) begin : GEN_UNALIGNED
wire need_2nd_page;
reg [UNALIGNED_SHIFT_WIDTH-1:0] R_shift [3];
reg hold_dout;
reg R_second;
reg R_need_2nd_page;
reg [WIDTH*2-ALIGNMENT_WIDTH-1:0] data_int;
reg [WIDTH-1:0] R_o_readdata;
reg [1:0] R_2nd_valid;
reg second_part_in_cache;
wire [WIDTH-1:0] c0_data_h, rd_data_h, c0_data_mux, rd_data_mux;
wire [WIDTH-ALIGNMENT_WIDTH-1:0] c1_data_l, rd_data_l;
wire get_new_offset, offset_backpressure_stall ;
wire [CACHE_ADDR_W-1:0] caddr_next;
wire [1:0] rw_wire;
reg [1:0] rw;
reg [WIDTH-ALIGNMENT_WIDTH-1:0] R_c1_data_l;
assign need_2nd_page = |d_shift;
assign valid_hold = |o_valid_pre;
assign rw_wire[0] = d_cache_addr == R_cache_addr & R_rd_data;
assign rw_wire[1] = caddr_next == R_cache_addr & R_rd_data;
assign c0_data_h = rw[0]? rd_data[MWIDTH-1:MWIDTH-WIDTH] : reused_data[0][MWIDTH-1:MWIDTH-WIDTH];
assign c1_data_l = rw[1]? R_c1_data_l : reused_data[1][WIDTH-ALIGNMENT_WIDTH-1:0];
assign rd_data_h = rd_data[MWIDTH-1:MWIDTH-WIDTH];
assign rd_data_l = rd_data[WIDTH-ALIGNMENT_WIDTH-1:0];
assign c0_data_mux = rw[0]? rd_data >> R_offset*ALIGNMENT_WIDTH : reused_data[0] >> R_offset*ALIGNMENT_WIDTH ;
assign rd_data_mux = rd_data >> R_offset*ALIGNMENT_WIDTH;
assign caddr_next = d_cache_addr+1;
assign unalign_stall_offset = d_2nd_valid & !offset_backpressure_stall & !R_2nd_valid[0]; //it is a one-cc pulse
assign unalign_stall_data = R_2nd_valid[0];
assign get_new_offset = rd_offset | unalign_stall_offset;
assign offset_backpressure_stall = wait_data | downstream_stall & offset_valid;
assign offset_stall = offset_backpressure_stall | unalign_stall_offset;
assign data_stall = downstream_stall | unalign_stall_data;
assign wait_data = rd_next_page_en & rd_data_empty & !R_2nd_valid[0];
assign o_readdata = hold_dout? R_o_readdata : data_int[R_shift[2]*ALIGNMENT_WIDTH +: WIDTH];
always@(posedge clk or posedge reset)begin
if(reset) begin
o_valid_pre <= 2'b0;
o_valid <= 1'b0;
end
else begin
o_valid_pre[0] <= offset_valid & get_new_offset & (!need_2nd_page | !R_2nd_valid[0] & d_second);
if(i_stall & o_valid & o_valid_pre[0]) o_valid_pre[1] <= 1'b1;
else if(!i_stall) o_valid_pre[1] <= 1'b0;
if(o_valid_pre[0]) o_valid <= 1'b1;
else if(!i_stall) o_valid <= valid_hold;
end
end
always @(posedge clk) begin
if(R_rd_data) cache[R_cache_addr] <= rd_data;
if(get_new_offset) begin
{R_in_cache, R_offset, R_shift[0], R_second} <= {|d_in_cache, d_offset, d_shift, d_second};
R_cache_addr <= d_cache_addr;
R_cache_next <= caddr_next;
R_shift[1] <= R_shift[0];
R_need_2nd_page <= need_2nd_page;
second_part_in_cache <= !d_in_cache[0] & d_in_cache[1];
R_2nd_valid[1] <= R_2nd_valid[0];
`ifdef SIM_ONLY
if(d_in_cache[0]) reused_data[0] <= rw_wire[0]? 'x : cache[d_cache_addr];
reused_data[1] <= rw_wire[1]? 'x : cache[caddr_next];
`else
if(d_in_cache[0]) reused_data[0] <= cache[d_cache_addr];
reused_data[1] <= cache[caddr_next];
`endif
if(d_in_cache[1]) R_c1_data_l <= rd_data[WIDTH-ALIGNMENT_WIDTH-1:0];
end
// work-around to deal with read-during-write
if(!downstream_stall & (|d_in_cache)) rw <= rw_wire & d_in_cache;
if(!offset_backpressure_stall) R_2nd_valid[0] <= d_2nd_valid & !R_2nd_valid[0];
R_o_readdata <= o_readdata;
hold_dout <= i_stall & o_valid;
if(R_in_cache) begin
data_int[WIDTH*2-ALIGNMENT_WIDTH-1:WIDTH] <= c1_data_l;
data_int[WIDTH-1:0] <= second_part_in_cache? rd_data_h : R_need_2nd_page? c0_data_h : c0_data_mux;
end
else begin
if(R_second) data_int[WIDTH*2-ALIGNMENT_WIDTH-1:WIDTH] <= rd_data_l;
if(!R_second | R_2nd_valid[1]) data_int[WIDTH-1:0] <= R_need_2nd_page? rd_data_h : rd_data_mux;
end
R_shift[2] <= (R_in_cache | !R_second | R_2nd_valid[1])? R_shift[0] : R_shift[1];
end
end // end UNALIGNED
else begin : GEN_ALIGNED
reg [MWIDTH-1:0] cache [CACHE_SIZE_N] /* synthesis ramstyle = "no_rw_check, M20K" */;
assign valid_hold = o_valid;
assign offset_stall = wait_data | downstream_stall & offset_valid;
assign data_stall = downstream_stall;
assign wait_data = rd_next_page_en & rd_data_empty; // there is a valid offset, need data to demux
if(NUM_WORD == 1) assign o_readdata = R_in_cache? reused_data[0][WIDTH-1:0] : rd_data[WIDTH-1:0];
else assign o_readdata = R_in_cache? reused_data[0] >> R_offset*WORD_WIDTH: rd_data >> R_offset*WORD_WIDTH;
always @(posedge clk) begin
if(rd_offset) begin
R_cache_addr <= d_cache_addr;
R_in_cache <= d_in_cache & !(R_rd_data & R_cache_addr == d_cache_addr);
R_offset <= d_offset;
// registered cache input and output to infer megafunction RAM
`ifdef SIM_ONLY // for simulation accuracy
reused_data[0] <= (d_cache_addr == R_cache_addr & R_rd_data)? 'x : cache[d_cache_addr]; // read during write
`else
reused_data[0] <= cache[d_cache_addr];
`endif
end
else if(R_rd_data & R_cache_addr == d_cache_addr) R_in_cache <= 1'b0; // read during write
if(R_rd_data) cache[R_cache_addr] <= rd_data; // update cache
end
always@(posedge clk or posedge reset)begin
if(reset) o_valid <= 1'b0;
else if(!i_stall | !o_valid) o_valid <= rd_offset & offset_valid;
end
end // end ALIGNED
end // end USECACHING
else begin : DISABLE_CACHE
if(NUM_WORD == 1) begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_2nd_valid, i_shift, i_second, i_new_page};
assign {d_2nd_valid, d_shift, d_second, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
else begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_byte_offset, i_2nd_valid, i_shift, i_second, i_word_offset, i_new_page};
assign {d_byte_offset, d_2nd_valid, d_shift, d_second, d_offset, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
if(UNALIGNED) begin : GEN_UNALIGNED
wire need_2nd_page;
reg [UNALIGNED_SHIFT_WIDTH-1:0] R_shift [3];
reg hold_dout;
reg R_second;
reg R_need_2nd_page;
reg [WIDTH*2-ALIGNMENT_WIDTH-1:0] data_int;
reg [WIDTH-1:0] R_o_readdata;
reg [1:0] R_2nd_valid;
wire [WIDTH-1:0] rd_data_h, rd_data_mux;
wire [WIDTH-ALIGNMENT_WIDTH-1:0] rd_data_l;
wire get_new_offset, offset_backpressure_stall;
assign need_2nd_page = |d_shift;
assign valid_hold = |o_valid_pre;
assign rd_data_h = rd_data[MWIDTH-1:MWIDTH-WIDTH];
assign rd_data_l = rd_data[WIDTH-ALIGNMENT_WIDTH-1:0];
assign rd_data_mux = rd_data >> R_offset*ALIGNMENT_WIDTH;
assign unalign_stall_offset = d_2nd_valid & !offset_backpressure_stall & !R_2nd_valid[0]; //it is a one-cc pulse
assign unalign_stall_data = R_2nd_valid[0];
assign get_new_offset = rd_offset | unalign_stall_offset;
assign offset_backpressure_stall = wait_data | downstream_stall & offset_valid;
assign offset_stall = offset_backpressure_stall | unalign_stall_offset;
assign data_stall = downstream_stall | unalign_stall_data;
assign wait_data = rd_next_page_en & rd_data_empty & !R_2nd_valid[0];
assign o_readdata = hold_dout? R_o_readdata : data_int >> R_shift[2]*ALIGNMENT_WIDTH;
always@(posedge clk or posedge reset)begin
if(reset) begin
o_valid_pre <= 2'b0;
o_valid <= 1'b0;
end
else begin
o_valid_pre[0] <= offset_valid & get_new_offset & (!need_2nd_page | !R_2nd_valid[0] & d_second);
if(i_stall & o_valid & o_valid_pre[0]) o_valid_pre[1] <= 1'b1;
else if(!i_stall) o_valid_pre[1] <= 1'b0;
if(o_valid_pre[0]) o_valid <= 1'b1;
else if(!i_stall) o_valid <= valid_hold;
end
end
always @(posedge clk) begin
if(get_new_offset) begin
{R_offset, R_shift[0], R_second} <= {d_offset, d_shift, d_second};
R_shift[1] <= R_shift[0];
R_need_2nd_page <= need_2nd_page;
R_2nd_valid[1] <= R_2nd_valid[0];
end
if(!offset_backpressure_stall) R_2nd_valid[0] <= d_2nd_valid & !R_2nd_valid[0];
R_o_readdata <= o_readdata;
hold_dout <= i_stall & o_valid;
if(R_second) data_int[WIDTH*2-ALIGNMENT_WIDTH-1:WIDTH] <= rd_data_l;
if(!R_second | R_2nd_valid[1]) data_int[WIDTH-1:0] <= R_need_2nd_page? rd_data_h : rd_data_mux;
R_shift[2] <= (!R_second | R_2nd_valid[1])? R_shift[0] : R_shift[1];
end
end // end GEN_UNALIGNED
else begin : GEN_ALIGNED
assign valid_hold = o_valid;
assign offset_stall = wait_data | downstream_stall & offset_valid;
assign data_stall = downstream_stall;
assign wait_data = rd_next_page_en & rd_data_empty; // there is a valid offset, need data to demux
if(NUM_WORD == 1) assign o_readdata = rd_data[WIDTH-1:0];
else assign o_readdata = rd_data >> R_offset*WORD_WIDTH;
always @(posedge clk) begin
if(rd_offset) R_offset <= d_offset;
end
always@(posedge clk or posedge reset)begin
if(reset) o_valid <= 1'b0;
else if(!i_stall | !o_valid) o_valid <= rd_offset & offset_valid;
end
end // end GEN_ALIGNED
end // end DISABLE_CACHE
endgenerate
assign downstream_stall = i_stall & valid_hold;
assign rd_next_page_en = offset_valid & rd_next_page;
assign rd_offset = !offset_stall;
assign rd_data_fifo = rd_next_page_en & !data_stall;
always@(posedge clk or posedge reset)begin
if(reset) begin
offset_valid <= 1'b0;
R_rd_data <= 1'b0;
end
else begin
if(rd_offset) offset_valid <= !offset_fifo_empty;
R_rd_data <= rd_data_fifo & !rd_data_empty;
end
end
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (WIDE_FIFO_DEPTH),
.almost_full_value(WIDE_FIFO_DEPTH_THRESH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (MWIDTH),
.lpm_widthu (WIDE_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON")
) rd_back_wfifo (
.clock (clk),
.data (avm_readdata),
.wrreq (avm_readdatavalid),
.rdreq (rd_data_fifo),
.usedw (),
.empty (rd_data_empty),
.full (),
.q (rd_data),
.almost_empty (),
.almost_full (),
.aclr (reset)
);
endmodule
module acl_stall_free_coalescer (
clk, // clock
reset, // reset
i_valid, // valid address
i_empty, // request FIFO is empty
i_addr, // input address
o_page_addr, // output page address
o_page_addr_valid, // page address valid
o_num_burst, // number of burst
o_new_page
);
parameter AW = 1,
PAGE_AW = 1,
MAX_BURST = 1,
TIME_OUT = 1,
MAX_THREAD = 1,
CACHE_LAST = 0,
DISABLE_COALESCE = 0;
localparam BURST_CNT_WIDTH = $clog2(MAX_BURST+1);
localparam TIME_OUT_W = $clog2(TIME_OUT+1);
localparam THREAD_W = $clog2(MAX_THREAD+1);
input clk;
input reset;
input i_valid;
input i_empty;
input [AW-1:0] i_addr;
// all output signals are registered to help P&R
output reg [PAGE_AW-1:0] o_page_addr;
output reg o_page_addr_valid;
output reg [BURST_CNT_WIDTH-1:0] o_num_burst;
output reg o_new_page;
logic init;
wire match_current_wire, match_next_wire, reset_cnt;
reg [BURST_CNT_WIDTH-1:0] num_burst;
reg valid_burst;
wire [PAGE_AW-1:0] page_addr;
reg [PAGE_AW-1:0] R_page_addr = 0;
reg [PAGE_AW-1:0] R_page_addr_next = 0;
reg [PAGE_AW-1:0] addr_hold = 0;
reg [3:0] delay_cnt; // it takes 5 clock cycles from o_page_addr_valid to being read out from FIFO (if avm_stall = 0), assuming 3 extra clock cycles to reach global mem
reg [TIME_OUT_W-1:0] time_out_cnt = 0;
reg [THREAD_W-1:0] thread_cnt = 0;
wire time_out;
wire max_thread;
assign page_addr = i_addr[AW-1:AW-PAGE_AW]; // page address
assign match_current_wire = page_addr == R_page_addr;
assign max_thread = thread_cnt[THREAD_W-1] & i_empty;
assign time_out = time_out_cnt[TIME_OUT_W-1] & i_empty;
assign reset_cnt = valid_burst & (
num_burst[BURST_CNT_WIDTH-1] // reach max burst
| time_out
| max_thread
| !match_current_wire & !match_next_wire & !init & i_valid ); // new burst
generate
if(MAX_BURST == 1) begin : BURST_ONE
assign match_next_wire = 1'b0;
end
else begin : BURST_N
assign match_next_wire = page_addr == R_page_addr_next & !init & i_valid & (|page_addr[BURST_CNT_WIDTH-2:0]);
end
if(DISABLE_COALESCE) begin : GEN_DISABLE_COALESCE
always@(*) begin
o_page_addr = page_addr;
o_page_addr_valid = i_valid;
o_num_burst = 1;
o_new_page = 1'b1;
end
end
else begin : ENABLE_COALESCE
always@(posedge clk) begin
if(i_valid) begin
R_page_addr <= page_addr;
R_page_addr_next <= page_addr + 1'b1;
end
o_num_burst <= num_burst;
o_page_addr <= addr_hold;
if(i_valid | reset_cnt) time_out_cnt <= 0; // nop is valid thread, should reset time_out counter too
else if(!time_out_cnt[TIME_OUT_W-1] & valid_burst) time_out_cnt <= time_out_cnt + 1;
if(reset_cnt) thread_cnt <= i_valid;
else if(i_valid & !thread_cnt[THREAD_W-1]) thread_cnt <= thread_cnt + 1;
if(o_page_addr_valid) delay_cnt <= 1;
else if(!delay_cnt[3]) delay_cnt <= delay_cnt + 1;
if(reset_cnt) begin
num_burst <= i_valid & !match_current_wire;
addr_hold <= page_addr;
end
else if(i_valid) begin
num_burst <= (!valid_burst & !match_current_wire | init)? 1 : num_burst + match_next_wire;
if(!valid_burst | init) addr_hold <= page_addr;
end
o_new_page <= (!match_current_wire| init) & i_valid;
end
always@(posedge clk or posedge reset) begin
if(reset) begin
o_page_addr_valid <= 1'b0;
valid_burst <= 1'b0;
end
else begin
if(reset_cnt) valid_burst <= i_valid & !match_current_wire;
else if(i_valid) begin
if(!valid_burst & !match_current_wire | init) valid_burst <= 1'b1;
else if(match_next_wire) valid_burst <= 1'b1;
end
o_page_addr_valid <= reset_cnt;
end
end
end
if(CACHE_LAST) begin : GEN_ENABLE_CACHE
always@(posedge clk or posedge reset) begin
if(reset) init <= 1'b1;
else begin
if(!valid_burst & !o_page_addr_valid & (!i_valid | match_current_wire & !init)) init <= 1'b1; // set init to 1 when the previous request is read out
else if(i_valid) init <= 1'b0;
end
end
end
else begin : GEN_DISABLE_CACHE
always@(posedge clk or posedge reset) begin
if(reset) init <= 1'b1;
else begin
if(!valid_burst & delay_cnt[3] & !o_page_addr_valid & i_empty & (!i_valid | match_current_wire & !init)) init <= 1'b1; // set init to 1 when the previous request is read out
else if(i_valid) init <= 1'b0;
end
end
end
endgenerate
endmodule
module lsu_bursting_write
(
clk, clk2x, reset, o_stall, i_valid, i_nop, i_address, i_writedata, i_stall, o_valid,
i_2nd_offset,
i_2nd_data,
i_2nd_byte_en,
i_2nd_en,
i_thread_valid,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest,
avm_burstcount,
i_byteenable
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // The max number of live threads
parameter MEMORY_SIDE_MEM_LATENCY=32; // The latency to get to the iface (no response needed from DDR, we generate writeack right before the iface).
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USE_WRITE_ACK=0; // Wait till the write has actually made it to global memory
parameter HIGH_FMAX=1;
parameter USE_BYTE_EN=0;
parameter UNALIGN=0;
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam ALIGNMENT_ABYTES=2**ALIGNMENT_ABITS;
/********
* Ports *
********/
// Standard global signals
input clk;
input clk2x;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// used for unaligned
input [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0] i_2nd_offset;
input [WIDTH-1:0] i_2nd_data;
input [WIDTH_BYTES-1:0] i_2nd_byte_en;
input i_2nd_en;
input i_thread_valid;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
input [WIDTH_BYTES-1:0] i_byteenable;
// Byte enable control
reg reg_lsu_i_valid, reg_lsu_i_thread_valid;
reg [AWIDTH-1:0] reg_lsu_i_address;
reg [WIDTH-1:0] reg_lsu_i_writedata;
reg [WIDTH_BYTES-1:0] reg_lsu_i_byte_enable;
reg reg_common_burst, reg_lsu_i_2nd_en;
reg reg_i_nop;
reg [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0] reg_lsu_i_2nd_offset;
reg [WIDTH-1:0]reg_lsu_i_2nd_data;
reg [WIDTH_BYTES-1:0] reg_lsu_i_2nd_byte_en;
wire stall_signal_directly_from_lsu;
assign o_stall = reg_lsu_i_valid & stall_signal_directly_from_lsu;
// --------------- Pipeline stage : Burst Checking --------------------
always@(posedge clk or posedge reset)
begin
if (reset)
begin
reg_lsu_i_valid <= 1'b0;
reg_lsu_i_thread_valid <= 1'b0;
end
else
begin
if (~o_stall) begin
reg_lsu_i_valid <= i_valid;
reg_lsu_i_thread_valid <= i_thread_valid;
end
end
end
always@(posedge clk) begin
if (~o_stall & i_valid & ~i_nop) reg_lsu_i_address <= i_address;
if (~o_stall) begin
reg_i_nop <= i_nop;
reg_lsu_i_writedata <= i_writedata;
reg_lsu_i_byte_enable <= i_byteenable;
reg_lsu_i_2nd_offset <= i_2nd_offset;
reg_lsu_i_2nd_en <= i_2nd_en;
reg_lsu_i_2nd_data <= i_2nd_data;
reg_lsu_i_2nd_byte_en <= i_2nd_byte_en;
reg_common_burst <= i_nop | (reg_lsu_i_address[AWIDTH-1:BYTE_SELECT_BITS+BURSTCOUNT_WIDTH-1] == i_address[AWIDTH-1:BYTE_SELECT_BITS+BURSTCOUNT_WIDTH-1]);
end
end
// -------------------------------------------------------------------
lsu_bursting_write_internal #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(USE_BYTE_EN),
.UNALIGN(UNALIGN),
.HIGH_FMAX(HIGH_FMAX)
) bursting_write (
.clk(clk),
.clk2x(clk2x),
.reset(reset),
.i_nop(reg_i_nop),
.o_stall(stall_signal_directly_from_lsu),
.i_valid(reg_lsu_i_valid),
.i_thread_valid(reg_lsu_i_thread_valid),
.i_address(reg_lsu_i_address),
.i_writedata(reg_lsu_i_writedata),
.i_2nd_offset(reg_lsu_i_2nd_offset),
.i_2nd_data(reg_lsu_i_2nd_data),
.i_2nd_byte_en(reg_lsu_i_2nd_byte_en),
.i_2nd_en(reg_lsu_i_2nd_en),
.i_stall(i_stall),
.o_valid(o_valid),
.o_active(o_active),
.i_byteenable(reg_lsu_i_byte_enable),
.avm_address(avm_address),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest),
.common_burst(reg_common_burst)
);
endmodule
//
// Burst coalesced write module
// Again, top level comments later
//
module lsu_bursting_write_internal
(
clk, clk2x, reset, o_stall, i_valid, i_nop, i_address, i_writedata, i_stall, o_valid,
o_active, //Debugging signal
i_2nd_offset,
i_2nd_data,
i_2nd_byte_en,
i_2nd_en,
i_thread_valid,
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest,
avm_burstcount,
i_byteenable,
common_burst
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter MEMORY_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USE_WRITE_ACK=0; // Wait till the write has actually made it to global memory
parameter HIGH_FMAX=1;
parameter USE_BYTE_EN=0;
parameter UNALIGN=0;
// WARNING: Kernels will hang if InstrDataDep claims that a store
// has more capacity than this number
//
parameter MAX_CAPACITY=128; // Must be a power-of-2 to keep things simple
// Derived parameters
localparam MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
//
// Notice that in the non write ack case, the number of threads seems to be twice the sensible number
// This is because MAX_THREADS is usually the limiter on the counter width. Once one request is assemembled,
// we want to be able to start piplining another burst. Thus the factor of 2.
// The MEMORY_SIDE_MEM_LATENCY will further increase this depth if the compiler
// thinks the lsu will see a lot of contention on the Avalon side.
//
localparam __WRITE_FIFO_DEPTH = (WIDTH_BYTES==MWIDTH_BYTES) ? 3*MAX_BURST : 2*MAX_BURST;
// No reason this should need more than max MLAB depth
localparam _WRITE_FIFO_DEPTH = ( __WRITE_FIFO_DEPTH < 64 ) ? __WRITE_FIFO_DEPTH : 64;
// Need at least 4 to account for fifo push-to-pop latency
localparam WRITE_FIFO_DEPTH = ( _WRITE_FIFO_DEPTH > 8 ) ? _WRITE_FIFO_DEPTH : 8;
// If writeack, make this equal to
localparam MAX_THREADS=(USE_WRITE_ACK ? KERNEL_SIDE_MEM_LATENCY - MEMORY_SIDE_MEM_LATENCY : (2*MWIDTH_BYTES/WIDTH_BYTES*MAX_BURST)); // Maximum # of threads to group into a burst request
//
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH=8*SEGMENT_WIDTH_BYTES;
localparam NUM_WORD = MWIDTH_BYTES/SEGMENT_WIDTH_BYTES;
localparam UNALIGN_BITS = $clog2(WIDTH_BYTES)-ALIGNMENT_ABITS;
// Constants
localparam COUNTER_WIDTH=(($clog2(MAX_THREADS)+1 < $clog2(MAX_CAPACITY+1)) ?
$clog2(MAX_CAPACITY+1) : ($clog2(MAX_THREADS)+1)); // Determines the max writes 'in-flight'
/********
* Ports *
********/
// Standard global signals
input clk;
input clk2x;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// used for unaligned
input [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0] i_2nd_offset;
input [WIDTH-1:0] i_2nd_data;
input [WIDTH_BYTES-1:0] i_2nd_byte_en;
input i_2nd_en;
input i_thread_valid;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// Byte enable control
input [WIDTH_BYTES-1:0] i_byteenable;
// Help from outside
input common_burst;
/***************
* Architecture *
***************/
wire [WIDTH_BYTES-1:0] word_byte_enable;
wire [WIDTH-1:0] word_bit_enable, word2_bit_enable;
wire input_accepted;
wire output_acknowledged;
wire write_accepted;
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire c_new_page;
wire c_page_done;
wire c_nop;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire c_stall;
reg [COUNTER_WIDTH-1:0] occ_counter;
// Replicated version of the occ and stores counters that decrement instead of increment
// This allows me to check the topmost bit to determine if the counter is non-empty
reg [COUNTER_WIDTH-1:0] nop_cnt;
reg [COUNTER_WIDTH-1:0] occ_counter_neg;
reg [COUNTER_WIDTH-1:0] ack_counter_neg;
reg [COUNTER_WIDTH-1:0] ack_counter;
reg [COUNTER_WIDTH-1:0] next_counter;
reg [MWIDTH-1:0] wm_writedata;
reg [MWIDTH_BYTES-1:0] wm_byteenable;
reg [MWIDTH-1:0] wm_wide_wdata;
reg [MWIDTH_BYTES-1:0] wm_wide_be;
reg [MWIDTH-1:0] wm_wide_bite;
wire w_fifo_full;
wire [BURSTCOUNT_WIDTH-1:0] c_burstcount;
// Track the current item in the write burst since we issue c_burstcount burst reqs
reg [BURSTCOUNT_WIDTH-1:0] burstcounter;
// The address components
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
assign word_byte_enable = i_nop? '0: (USE_BYTE_EN ? i_byteenable :{WIDTH_BYTES{1'b1}}) ;
generate
genvar byte_num;
for( byte_num = 0; byte_num < WIDTH_BYTES; byte_num++)
begin : biten
assign word_bit_enable[(byte_num+1)*8-1: byte_num*8] = {8{word_byte_enable[byte_num]}};
assign word2_bit_enable[(byte_num+1)*8-1: byte_num*8] = {8{i_2nd_byte_en[byte_num]}};
end
endgenerate
wire oc_full;
wire cnt_valid;
wire coalescer_active;
// Coalescer - Groups subsequent requests together if they are compatible
// and the output register stage is stalled
bursting_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(16),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.MAXBURSTCOUNT(MAX_BURST),
.MAX_THREADS(MAX_THREADS)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !oc_full && !w_fifo_full),
.i_nop(i_nop),
.o_stall(c_stall),
.o_start_nop(c_nop), // new burst starts with nop
.o_new_page(c_new_page),
.o_page_done(c_page_done),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(w_fifo_full),
.o_burstcount(c_burstcount),
.common_burst(common_burst),
.o_active(coalescer_active)
);
// Writedata MUX
generate if( SEGMENT_SELECT_BITS > 0 )
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
if(UNALIGN) begin : GEN_UNALIGN
assign cnt_valid = i_thread_valid;
always@(*) begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_bite = {MWIDTH{1'b0}};
if(i_2nd_en) begin
wm_wide_wdata[WIDTH-1:0] = i_2nd_data;
wm_wide_wdata = wm_wide_wdata << (i_2nd_offset*SEGMENT_WIDTH);
wm_wide_wdata[WIDTH-1:0] = i_writedata;
wm_wide_be[WIDTH_BYTES-1:0] = i_2nd_byte_en;
wm_wide_be = wm_wide_be << (i_2nd_offset*SEGMENT_WIDTH_BYTES);
wm_wide_be[WIDTH_BYTES-1:0] = word_byte_enable;
wm_wide_bite[WIDTH-1:0] = word2_bit_enable;
wm_wide_bite = wm_wide_bite << (i_2nd_offset*SEGMENT_WIDTH);
wm_wide_bite[WIDTH-1:0] = word_bit_enable;
end
else begin
wm_wide_wdata[WIDTH-1:0] = i_writedata;
wm_wide_wdata = wm_wide_wdata << (segment_select*SEGMENT_WIDTH);
wm_wide_be[WIDTH_BYTES-1:0] = word_byte_enable;
wm_wide_be = wm_wide_be << (segment_select*SEGMENT_WIDTH_BYTES);
wm_wide_bite[WIDTH-1:0] = word_bit_enable;
wm_wide_bite = wm_wide_bite << (segment_select*SEGMENT_WIDTH);
end
end
end // end GEN_UNALIGN
else begin: GEN_ALIGN
assign cnt_valid = i_valid;
always@(*) begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[WIDTH-1:0] = i_writedata;
wm_wide_wdata = wm_wide_wdata << (segment_select*SEGMENT_WIDTH);
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[WIDTH_BYTES-1:0] = word_byte_enable;
wm_wide_be = wm_wide_be << (segment_select*SEGMENT_WIDTH_BYTES);
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[WIDTH-1:0] = word_bit_enable;
wm_wide_bite = wm_wide_bite << (segment_select*SEGMENT_WIDTH);
end
end
end
else
begin
assign cnt_valid = i_valid;
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[0 +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[0 +: WIDTH_BYTES] = word_byte_enable;
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[0 +: WIDTH] = word_bit_enable;
end
end
endgenerate
// Track the current write burst data - coalesce writes together until the
// output registers are ready for a new request.
always@(posedge clk or posedge reset)
begin
if(reset)
begin
wm_writedata <= {MWIDTH{1'b0}};
wm_byteenable <= {MWIDTH_BYTES{1'b0}};
end
else
begin
if(c_new_page)
begin
wm_writedata <= wm_wide_wdata;
wm_byteenable <= wm_wide_be;
end
else if(input_accepted)
begin
wm_writedata <= (wm_wide_wdata & wm_wide_bite) | (wm_writedata & ~wm_wide_bite);
wm_byteenable <= wm_wide_be | wm_byteenable;
end
end
end
wire [COUNTER_WIDTH-1:0] num_threads_written;
// This FIFO stores the actual data to be written
//
//
wire w_data_fifo_full, req_fifo_empty;
wire wr_page = c_page_done & !w_fifo_full;
acl_data_fifo #(
.DATA_WIDTH(COUNTER_WIDTH+MWIDTH+MWIDTH_BYTES),
.DEPTH(WRITE_FIFO_DEPTH),
.IMPL(HIGH_FMAX ? "ram_plus_reg" : "ram")
) req_fifo (
.clock(clk),
.resetn(~reset),
.data_in( {wm_writedata,wm_byteenable} ),
.valid_in( wr_page ),
.data_out( {avm_writedata,avm_byteenable} ),
.stall_in( ~write_accepted ),
.stall_out( w_data_fifo_full ),
.empty(req_fifo_empty)
);
// This FIFO stores the number of valid's to release with each writeack
//
wire w_ack_fifo_full;
acl_data_fifo #(
.DATA_WIDTH(COUNTER_WIDTH),
.DEPTH(2*WRITE_FIFO_DEPTH),
.IMPL(HIGH_FMAX ? "ram_plus_reg" : "ram")
) ack_fifo (
.clock(clk),
.resetn(~reset),
.data_in( next_counter),
.valid_in( wr_page ),
.data_out( num_threads_written ),
.stall_in( !avm_writeack),
.stall_out( w_ack_fifo_full )
);
// This FIFO hold the request information { address & burstcount }
//
wire w_fifo_stall_in;
assign w_fifo_stall_in = !(write_accepted && (burstcounter == avm_burstcount));
wire w_request_fifo_full;
acl_data_fifo #(
.DATA_WIDTH(PAGE_SELECT_BITS+BURSTCOUNT_WIDTH),
.DEPTH(WRITE_FIFO_DEPTH),
.IMPL(HIGH_FMAX ? "ram_plus_reg" : "ram")
) req_fifo2 (
.clock(clk),
.resetn(~reset),
.data_in( {c_req_addr,c_burstcount} ),
.valid_in( c_req_valid & !w_fifo_full ), // The basical coalescer stalls on w_fifo_full holding c_req_valid high
.data_out( {avm_address[AWIDTH-1: BYTE_SELECT_BITS],avm_burstcount} ),
.valid_out( avm_write ),
.stall_in( w_fifo_stall_in ),
.stall_out( w_request_fifo_full )
);
assign avm_address[BYTE_SELECT_BITS-1:0] = '0;
// The w_fifo_full is the OR of the data or request fifo's being full
assign w_fifo_full = w_data_fifo_full | w_request_fifo_full | w_ack_fifo_full;
// Occupancy counter - track the number of successfully transmitted writes
// and the number of writes pending in the next request.
// occ_counter - the total occupancy (in threads) of the unit
// next_counter - the number of threads coalesced into the next transfer
// ack_counter - the number of pending threads with write completion acknowledged
reg pending_nop;
wire pending_cc = nop_cnt != occ_counter;
wire burst_start_nop = cnt_valid & c_nop & !o_stall;
wire start_with_nop = !pending_cc && i_nop && cnt_valid && !o_stall; // nop starts when there are no pending writes
wire normal_cc_valid = cnt_valid && !o_stall && !i_nop;
wire clear_nop_cnt = normal_cc_valid || !pending_cc;
assign input_accepted = cnt_valid && !o_stall && !(c_nop || start_with_nop);
assign write_accepted = avm_write && !avm_waitrequest;
assign output_acknowledged = o_valid && !i_stall;
wire [8:0] ack_pending = {1'b1, {COUNTER_WIDTH{1'b0}}} - ack_counter;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
occ_counter_neg <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
next_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter_neg <= '0;
nop_cnt <= '0;
burstcounter <= 6'b000001;
o_active <= 1'b0;
pending_nop <= 1'b0;
end
else
begin
if(clear_nop_cnt) begin
nop_cnt <= '0;
pending_nop <= 1'b0;
end
else if(!start_with_nop) begin
nop_cnt <= nop_cnt + burst_start_nop;
if(burst_start_nop) pending_nop <= 1'b1;
end
occ_counter <= occ_counter + (cnt_valid && !o_stall) - output_acknowledged;
occ_counter_neg <= occ_counter_neg - (cnt_valid && !o_stall) + output_acknowledged;
next_counter <= input_accepted + (c_page_done ? {COUNTER_WIDTH{1'b0}} : next_counter) + (normal_cc_valid? nop_cnt : 0);
if(USE_WRITE_ACK) begin
ack_counter <= ack_counter
- (avm_writeack? num_threads_written : 0)
- ( (!pending_cc & !normal_cc_valid)? nop_cnt : 0)
- start_with_nop
+ output_acknowledged;
o_active <= occ_counter_neg[COUNTER_WIDTH-1];
end
else begin
ack_counter <= ack_counter - (cnt_valid && !o_stall) + output_acknowledged;
ack_counter_neg <= ack_counter_neg - wr_page + avm_writeack;
o_active <= occ_counter_neg[COUNTER_WIDTH-1] | ack_counter_neg[COUNTER_WIDTH-1] | coalescer_active; // do not use num_threads_written, because it takes extra resource
end
burstcounter <= write_accepted ? ((burstcounter == avm_burstcount) ? 6'b000001 : burstcounter+1) : burstcounter;
end
end
assign oc_full = occ_counter[COUNTER_WIDTH-1];
// Pipeline control signals
assign o_stall = oc_full || c_stall || w_fifo_full;
assign o_valid = ack_counter[COUNTER_WIDTH-1];
endmodule
// BURST COALESCING MODULE
//
// Similar to the basic coalescer but supports checking if accesses are in consecutive DRAM "pages"
// Supports the ad-hocly discovered protocols for bursting efficiently with avalaon
// - Don't burst from an ODD address
// - If not on a burst boundary, then just burst up to the next burst bondary
//
// Yes, I know, this could be incorporated into the basic coalescer. But that's really not my "thing"
//
module bursting_coalescer
(
clk, reset, i_page_addr, i_nop, i_valid, o_stall, o_new_page, o_page_done, o_req_addr, o_burstcount,
o_req_valid, i_stall, o_start_nop,
common_burst,
// For the purposes of maintaining latency correctly, we need to know if total # of threads
// accepted by the caching LSU
i_input_accepted_from_wrapper_lsu,
i_reset_timeout,
o_active
);
parameter PAGE_ADDR_WIDTH=32;
parameter TIMEOUT=8;
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter MAXBURSTCOUNT=32; // This isn't the max supported by Avalon, but the max that the instantiating module needs
parameter MAX_THREADS=64; // Must be a power of 2
parameter USECACHING=0;
localparam SLAVE_MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
localparam THREAD_COUNTER_WIDTH=$clog2(MAX_THREADS+1);
input clk;
input reset;
input [PAGE_ADDR_WIDTH-1:0] i_page_addr;
input i_nop;
input i_valid;
output o_stall;
output o_new_page;
output o_page_done;
output o_start_nop;
output [PAGE_ADDR_WIDTH-1:0] o_req_addr;
output o_req_valid;
output [BURSTCOUNT_WIDTH-1:0] o_burstcount;
input i_stall;
input common_burst;
input i_input_accepted_from_wrapper_lsu;
input i_reset_timeout;
output o_active;
reg [PAGE_ADDR_WIDTH-1:0] page_addr;
reg [PAGE_ADDR_WIDTH-1:0] last_page_addr;
reg [PAGE_ADDR_WIDTH-1:0] last_page_addr_p1;
reg [BURSTCOUNT_WIDTH-1:0] burstcount;
reg valid;
wire ready;
wire waiting;
wire match;
wire timeout;
reg [$clog2(TIMEOUT):0] timeout_counter;
reg [THREAD_COUNTER_WIDTH-1:0] thread_counter;
generate if(USECACHING)
begin
assign timeout = timeout_counter[$clog2(TIMEOUT)] | thread_counter[THREAD_COUNTER_WIDTH-1];
end
else
begin
assign timeout = timeout_counter[$clog2(TIMEOUT)];
end
endgenerate
// Internal signal logic
wire match_burst_address;
wire match_next_page;
wire match_current_page;
generate
if ( BURSTCOUNT_WIDTH > 1 )
begin
assign match_next_page = (i_page_addr[BURSTCOUNT_WIDTH-2:0] === last_page_addr_p1[BURSTCOUNT_WIDTH-2:0]) && (|last_page_addr_p1[BURSTCOUNT_WIDTH-2:0]);
assign match_current_page = (i_page_addr[BURSTCOUNT_WIDTH-2:0] === last_page_addr[BURSTCOUNT_WIDTH-2:0]);
end
else
begin
assign match_next_page = 1'b0;
assign match_current_page = 1'b1;
end
endgenerate
assign match_burst_address = common_burst;//(i_page_addr[PAGE_ADDR_WIDTH-1:BURSTCOUNT_WIDTH-1] == last_page_addr[PAGE_ADDR_WIDTH-1:BURSTCOUNT_WIDTH-1]);
assign match = (match_burst_address && (match_current_page || match_next_page)) && !thread_counter[THREAD_COUNTER_WIDTH-1];
assign ready = !valid || !(i_stall || waiting);
assign waiting = !timeout && (!i_valid || match);
wire input_accepted = i_valid && !o_stall;
assign o_start_nop = i_nop & ready;
assign o_active = valid;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
last_page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
last_page_addr_p1 <= {PAGE_ADDR_WIDTH{1'b0}};
burstcount <= 1;
valid <= 1'b0;
timeout_counter <= 0;
thread_counter <= {THREAD_COUNTER_WIDTH{1'b0}};
end
else
begin
page_addr <= ready ? i_page_addr : page_addr;
last_page_addr <= ready ? i_page_addr : (input_accepted && match_next_page ? i_page_addr : last_page_addr );
last_page_addr_p1 <= ready ? i_page_addr+1 : (input_accepted && match_next_page ? i_page_addr+1 : last_page_addr_p1 );
valid <= ready ? i_valid & !i_nop : valid; // burst should not start with nop thread
burstcount <= ready ? 6'b000001 : (input_accepted && match_next_page ? burstcount+1 : burstcount );
thread_counter <= ready ? 1 : (USECACHING ?
(i_input_accepted_from_wrapper_lsu && !thread_counter[THREAD_COUNTER_WIDTH-1] ? thread_counter+1 : thread_counter ) :
(input_accepted ? thread_counter+1 : thread_counter));
if( USECACHING && i_reset_timeout || !USECACHING && i_valid )
timeout_counter <= 'd1;
else if( valid && !timeout )
timeout_counter <= timeout_counter + 'd1;
end
end
// Outputs
assign o_stall = !match && !ready && i_valid;
// We're starting a new page (used by loads)
assign o_new_page = ready || i_valid && match_burst_address && !thread_counter[THREAD_COUNTER_WIDTH-1] && match_next_page;
assign o_req_addr = page_addr;
assign o_burstcount = burstcount;
assign o_req_valid = valid && !waiting;
// We're just finished with a page (used by stores)
assign o_page_done = valid && !waiting && !i_stall || !ready && i_valid && match_burst_address && !thread_counter[THREAD_COUNTER_WIDTH-1] && match_next_page;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t ();
// See also t_lint_width
parameter A_ONE = '1;
// verilator lint_off WIDTH
parameter [3:0] A_W4 = A_ONE;
// verilator lint_on WIDTH
initial begin
if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop;
if ($bits(A_W4) != 4) $stop;
if (A_W4 != 4'b0001) $stop;
end
b #(.B_WIDTH(48)) b ();
reg [4:0] c;
integer c_i;
initial begin
c_i = 3;
c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax
if (c != 5'b1000) $stop;
end
localparam D_TT = 32'd23;
localparam D_SIX = 6;
// verilator lint_off WIDTH
localparam [5:0] D_SUB = D_TT - D_SIX;
// verilator lint_on WIDTH
initial begin
if (D_SUB != 17) $stop;
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module b;
parameter B_WIDTH = 1;
localparam B_VALUE0 = {B_WIDTH{1'b0}};
localparam B_VALUE1 = {B_WIDTH{1'b1}};
reg [47:0] b_val;
initial begin
b_val = B_VALUE0;
if (b_val != 48'b0) $stop;
b_val = B_VALUE1;
if (b_val != ~48'b0) $stop;
end
endmodule
|
//----------------------------------------------------------------------
// Title : Demo Testbench
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : demo_tb.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This testbench will exercise the PHY ports of the EMAC
// to demonstrate the functionality.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module testbench;
//--------------------------------------------------------------------
// Testbench signals
//--------------------------------------------------------------------
wire reset;
wire tx_client_clk;
wire [7:0] tx_ifg_delay;
wire rx_client_clk;
wire [15:0] pause_val;
wire pause_req;
// GMII wires
wire gmii_tx_clk;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_txd;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire gmii_rx_er;
wire [7:0] gmii_rxd;
// Not asserted: full duplex only testbench
wire mii_tx_clk;
wire gmii_crs;
wire gmii_col;
// MDIO wires
wire mdc;
wire mdc_in;
wire mdio_in;
wire mdio_out;
wire mdio_tri;
// Host wires
wire [1:0] host_opcode;
wire [9:0] host_addr;
wire [31:0] host_wr_data;
wire [31:0] host_rd_data;
wire host_miim_sel;
wire host_req;
wire host_miim_rdy;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Testbench Semaphores
//----------------------------------------------------------------
wire configuration_busy;
wire monitor_finished_1g;
wire monitor_finished_100m;
wire monitor_finished_10m;
//----------------------------------------------------------------
// Wire up device under test
//----------------------------------------------------------------
v6_emac_v1_3_example_design dut
(
// Client receiver interface
.EMACCLIENTRXDVLD (),
.EMACCLIENTRXFRAMEDROP (),
.EMACCLIENTRXSTATS (),
.EMACCLIENTRXSTATSVLD (),
.EMACCLIENTRXSTATSBYTEVLD (),
// Client transmitter interface
.CLIENTEMACTXIFGDELAY (tx_ifg_delay),
.EMACCLIENTTXSTATS (),
.EMACCLIENTTXSTATSVLD (),
.EMACCLIENTTXSTATSBYTEVLD (),
// MAC Control interface
.CLIENTEMACPAUSEREQ (pause_req),
.CLIENTEMACPAUSEVAL (pause_val),
// Clock signal
.GTX_CLK (gtx_clk),
// GMII interface
.GMII_TXD (gmii_txd),
.GMII_TX_EN (gmii_tx_en),
.GMII_TX_ER (gmii_tx_er),
.GMII_TX_CLK (gmii_tx_clk),
.GMII_RXD (gmii_rxd),
.GMII_RX_DV (gmii_rx_dv),
.GMII_RX_ER (gmii_rx_er),
.GMII_RX_CLK (gmii_rx_clk),
// MDIO interface
.MDC (mdc),
.MDIO_I (mdio_in),
.MDIO_O (mdio_out),
.MDIO_T (mdio_tri),
// Host interface
.HOSTCLK (host_clk),
.HOSTOPCODE (host_opcode),
.HOSTREQ (host_req),
.HOSTMIIMSEL (host_miim_sel),
.HOSTADDR (host_addr),
.HOSTWRDATA (host_wr_data),
.HOSTMIIMRDY (host_miim_rdy),
.HOSTRDDATA (host_rd_data),
.REFCLK (refclk),
// Asynchronous reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req = 1'b0;
assign pause_val = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay = 8'b0;
//--------------------------------------------------------------------------
// Simulate the MDIO_IN port floating high
//--------------------------------------------------------------------------
assign (strong0, weak1) mdio_in = 1'b1;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the PHY stimulus and monitor
//--------------------------------------------------------------------
phy_tb phy_test
(
//----------------------------------------------------------------
// GMII interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_rx_clk (gmii_rx_clk),
.gmii_col (gmii_col),
.gmii_crs (gmii_crs),
.mii_tx_clk (mii_tx_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
//--------------------------------------------------------------------
// Instantiate the host configuration stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host interface
//----------------------------------------------------------------
.host_clk (host_clk),
.host_opcode (host_opcode),
.host_req (host_req),
.host_miim_sel (host_miim_sel),
.host_addr (host_addr),
.host_wr_data (host_wr_data),
.host_miim_rdy (host_miim_rdy),
.host_rd_data (host_rd_data),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
endmodule
|
// psi2c_control
`timescale 1 ps / 1 ps
/*
-- registers b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
-- 0 w: tbm go
-- 0 r: ful tbm run
-- 1 w: send raw S P D7 D6 D5 D4 !D4 D3 D2 D1 D0 !D0
-- 2 w: send D7 D6 D5 D4 D3 D2 D1 D0
-- 3 w: send S D7 D6 D5 D4 D3 D2 D1 D0
-- 4 w: send P D7 D6 D5 D4 D3 D2 D1 D0
-- 5 w: send SP D7 D6 D5 D4 D3 D2 D1 D0
-- 1 r: rdb raw run to 0 _s3 _rw _d4 _d0 S ha4 ha3 ha2 ha1 ha0 pa2 pa1 pa0
-- ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0
--
-- tbm = read back on
-- ful = fifo full
-- go = start transmission
-- run = i2c running
-- S = Start Bit, P = Stop Bit
-- D = Send Data
-- ha = Hub Address
-- pa = Port Address
-- ra = Register Address
-- rd = Register Data
*/
module i2c_control
(
// avalon slave
input clk,
input reset,
// avalon slave interface
input [2:0]address,
input write,
input [31:0]writedata,
input read,
output reg [31:0]readdata,
output reg go,
input full,
output reg [11:0]memd,
output memw,
input busy,
output tbm,
input [31:0]rda
);
wire [9:0]i2c_data;
reg rdbff;
assign memw = write & (address>=1) & (address<=5);
assign i2c_data = {writedata[7:4], !writedata[4],
writedata[3:0], !writedata[0]};
always @(*)
case (address)
3'd2: memd <= {2'b00, i2c_data};
3'd3: memd <= {2'b10, i2c_data}; // S
3'd4: memd <= {2'b01, i2c_data}; // P
3'd5: memd <= {2'b11, i2c_data}; // SP
default: memd <= writedata[11:0];
endcase
always @(*)
case (address)
3'd1: readdata <= rda;
default readdata <= {28'h1234_567, 1'b0, full, rdbff, busy || rda[31]};
endcase
// tbm mode
always @(posedge clk or posedge reset)
begin
if (reset)
begin
rdbff <= 0;
go <= 0;
end
else if (write && (address == 3'd0))
begin
rdbff <= writedata[1];
go <= writedata[0];
end
else go <= 0;
end
assign tbm = rdbff;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input in; // inputs don't get flagged as undriven
output out; // outputs don't get flagged as unused
sub sub ();
// Check we don't warn about unused UDP signals
udp_mux2 udpsub (out, in, in, in);
// Check ignoreds mark as used
reg sysused;
initial $bboxed(sysused);
// Check file IO. The fopen is the "driver" all else a usage.
integer infile;
integer outfile;
initial begin
outfile = $fopen("obj_dir/t_lint_unused_bad/open.log", "w");
$fwrite(outfile, "1\n");
$fclose(outfile);
infile = $fopen("obj_dir/t_lint_unused_bad/open.log", "r");
if ($fgetc(infile) != "1") begin end
end
wire _unused_ok;
endmodule
module sub;
wire pub /*verilator public*/; // Ignore publics
localparam THREE = 3;
endmodule
primitive udp_mux2 (q, a, b, s);
output q;
input a, b, s;
table
//a b s : out
1 ? 0 : 1 ;
0 ? 0 : 0 ;
? 1 1 : 1 ;
? 0 1 : 0 ;
0 0 x : 0 ;
1 1 x : 1 ;
endtable
endprimitive
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "true";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_SYMBOL_V
/**
* top_power_hvc_wpad: A power pad with an ESD high-voltage clamp.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpad (
//# {{data|Data Signals}}
inout P_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout VSWITCH ,
inout DRN_HVC ,
inout OGC_HVC ,
inout P_CORE ,
inout SRC_BDY_HVC,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: rgmii_io.v
// Project: NetFPGA
// Description: Instantiate the IO flops for the rgmii interface for one TEMAC.
//
// See the Xilinx TriMode Ethernet MAC USer Guide (UG138) for details
//
///////////////////////////////////////////////////////////////////////////////
module rgmii_io (
//-----------------------------------------------------------------------
//-- Pad side signals
//-----------------------------------------------------------------------
output wire [3:0] rgmii_txd ,
output wire rgmii_tx_ctl ,
output wire rgmii_txc ,
input wire [3:0] rgmii_rxd ,
input wire rgmii_rx_ctl ,
//-----------------------------------------------------------------------
//-- Core side signals
//-----------------------------------------------------------------------
input wire [7:0] gmii_txd_int , // Internal gmii_txd signal.
input wire gmii_tx_en_int ,
input wire gmii_tx_er_int ,
output wire gmii_col_int ,
output wire gmii_crs_int ,
output reg [7:0] gmii_rxd_reg , // RGMII double data rate data valid.
output reg gmii_rx_dv_reg , // gmii_rx_dv_ibuf registered in IOBs.
output reg gmii_rx_er_reg , // gmii_rx_er_ibuf registered in IOBs.
//-----------------------------------------------------------------------
//-- Clocks and misc
//-----------------------------------------------------------------------
output reg eth_link_status ,
output reg [1:0] eth_clock_speed ,
output reg eth_duplex_status ,
// Following are generated by DCMs
input wire tx_rgmii_clk_int , // Internal RGMII transmitter clock.
input wire tx_rgmii_clk90_int, // Internal RGMII transmitter clock w/ 90 deg phase
input wire rx_rgmii_clk_int , // Internal RGMII receiver clock
input wire reset
);
reg [7:0] gmii_txd_rising; // gmii_txd signal registered on the rising edge of tx_rgmii_clk_int.
reg gmii_tx_en_rising; // gmii_tx_en signal registered on the rising edge of tx_rgmii_clk_int.
reg rgmii_tx_ctl_rising; // RGMII control signal registered on the rising edge of tx_rgmii_clk_int.
reg [3:0] gmii_txd_falling; // gmii_txd signal registered on the falling edge of tx_rgmii_clk_int
reg rgmii_tx_ctl_falling;// RGMII control signal registered on the falling edge of tx_rgmii_clk_int.
wire [3:0] rgmii_txd_obuf; // RGMII transmit data output.
//(* IOB="FORCE" *)
wire [3:0] rgmii_rxd_ibuf; // RGMII receiver data input.
//(* IOB="FORCE" *)
wire rgmii_rx_ctl_ibuf;
reg [7:0] rgmii_rxd_ddr;
reg rgmii_rx_dv_ddr; // Inverted version of the rx_rgmii_clk_int signal.
reg rgmii_rx_ctl_ddr; // RGMII double data rate data.
reg [7:0] rgmii_rxd_reg; // RGMII double data rate data valid.
reg rgmii_rx_dv_reg; // RGMII double data rate control signal.
reg rgmii_rx_ctl_reg; // RGMII data. gmii_tx_en signal.
//----------------------------------------------------------------
// Transmit interface
//----------------------------------------------------------------
//----------------------------------------------------------------
// Tx clock.
// Instantiate a DDR output register. This is a good way to drive
// RGMII_TXC since the clock-to-PAD delay will be the same as that
// for data driven from IOB Ouput flip-flops eg rgmii_rxd[3:0].
// This is set to produce a 90 degree phase shifted clock w.r.t.
// gtx_clk_bufg so that the clock edges are centralised within the
// rgmii_txd[3:0] valid window.
//----------------------------------------------------------------
wire rgmii_txc_obuf;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_inst (
.Q(rgmii_txc_obuf),
.C(tx_rgmii_clk90_int),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(1'b0),
.S(1'b0)
);
// drive clock through Output Buffers and onto PADS.
OBUF drive_rgmii_txc (.I(rgmii_txc_obuf), .O(rgmii_txc));
//-------------------------------------------------------------------
// RGMII Transmitter Logic :
// drive TX signals through IOBs onto RGMII interface
//-------------------------------------------------------------------
// Encode rgmii ctl signal
wire rgmii_tx_ctl_int;
assign rgmii_tx_ctl_int = gmii_tx_en_int ^ gmii_tx_er_int;
// Register all output signals on rising edge of gtx_clk_bufg
always @(posedge tx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
gmii_txd_rising <= 8'b0;
gmii_tx_en_rising <= 1'b0;
rgmii_tx_ctl_rising <= 1'b0;
end
else
begin
gmii_txd_rising <= gmii_txd_int;
gmii_tx_en_rising <= gmii_tx_en_int;
rgmii_tx_ctl_rising <= rgmii_tx_ctl_int;
end
end
wire not_tx_rgmii_clk_int;
assign not_tx_rgmii_clk_int = ~(tx_rgmii_clk_int);
// Register falling edge RGMII output signals on rising edge of not_gtx_clk_bufg
always @(posedge not_tx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
gmii_txd_falling <= 4'b0;
rgmii_tx_ctl_falling <= 1'b0;
end
else
begin
gmii_txd_falling <= gmii_txd_rising[7:4];
rgmii_tx_ctl_falling <= rgmii_tx_ctl_rising;
end
end
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out3 (
.Q(rgmii_txd_obuf[3]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[3]),
.D2(gmii_txd_falling[3]),
.R(reset),
.S(1'b0)
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out2 (
.Q(rgmii_txd_obuf[2]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[2]),
.D2(gmii_txd_falling[2]),
.R(reset),
.S(1'b0)
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out1 (
.Q(rgmii_txd_obuf[1]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[1]),
.D2(gmii_txd_falling[1]),
.R(reset),
.S(1'b0)
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out0 (
.Q(rgmii_txd_obuf[0]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[0]),
.D2(gmii_txd_falling[0]),
.R(reset),
.S(1'b0)
);
wire rgmii_tx_ctl_obuf;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_ctl
(
.Q(rgmii_tx_ctl_obuf),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_tx_en_rising),
.D2(rgmii_tx_ctl_falling),
.R(reset),
.S(1'b0)
);
// Drive RGMII Tx signals through Output Buffers and onto PADS.
OBUF drive_rgmii_tx_ctl (.I(rgmii_tx_ctl_obuf), .O(rgmii_tx_ctl));
OBUF drive_rgmii_txd3 (.I(rgmii_txd_obuf[3]), .O(rgmii_txd[3]));
OBUF drive_rgmii_txd2 (.I(rgmii_txd_obuf[2]), .O(rgmii_txd[2]));
OBUF drive_rgmii_txd1 (.I(rgmii_txd_obuf[1]), .O(rgmii_txd[1]));
OBUF drive_rgmii_txd0 (.I(rgmii_txd_obuf[0]), .O(rgmii_txd[0]));
//----------------------------------------------------------------
// Receive interface
//----------------------------------------------------------------
//-------------------------------------------------------------------
// RGMII Receiver Logic : receive RGMII_RX signals through IOBs from
// RGMII interface and convert to gmii_rx signals.
//-------------------------------------------------------------------
// Drive input RGMII Rx signals from PADS through Input Buffers.
IBUF drive_rgmii_rx_ctl (.I(rgmii_rx_ctl), .O(rgmii_rx_ctl_ibuf));
IBUF drive_rgmii_rxd3 (.I(rgmii_rxd[3]), .O(rgmii_rxd_ibuf[3]));
IBUF drive_rgmii_rxd2 (.I(rgmii_rxd[2]), .O(rgmii_rxd_ibuf[2]));
IBUF drive_rgmii_rxd1 (.I(rgmii_rxd[1]), .O(rgmii_rxd_ibuf[1]));
IBUF drive_rgmii_rxd0 (.I(rgmii_rxd[0]), .O(rgmii_rxd_ibuf[0]));
// Infer Double Data Rate Input flip-flops.
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_ddr[3:0] <= 4'b0;
rgmii_rx_dv_ddr <= 1'b0;
end
else
begin
rgmii_rxd_ddr[3:0] <= rgmii_rxd_ibuf;
rgmii_rx_dv_ddr <= rgmii_rx_ctl_ibuf;
end
end
wire not_rx_rgmii_clk_int;
assign not_rx_rgmii_clk_int = ~(rx_rgmii_clk_int);
always @(posedge not_rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_ddr[7:4] <= 4'b0;
rgmii_rx_ctl_ddr <= 1'b0;
end
else
begin
rgmii_rxd_ddr[7:4] <= rgmii_rxd_ibuf;
rgmii_rx_ctl_ddr <= rgmii_rx_ctl_ibuf;
end
end
// Register DDR signals internally to FPGA fabric
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_reg[3:0] <= 4'b0;
rgmii_rx_dv_reg <= 1'b0;
end
else
begin
rgmii_rxd_reg[3:0] <= rgmii_rxd_ddr[3:0];
rgmii_rx_dv_reg <= rgmii_rx_dv_ddr;
end
end // always @(posedge rx_rgmii_clk_int or posedge reset)
always @(posedge not_rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_reg[7:4] <= 4'b0;
rgmii_rx_ctl_reg <= 1'b0;
end
else
begin
rgmii_rxd_reg[7:4] <= rgmii_rxd_ddr[7:4];
rgmii_rx_ctl_reg <= rgmii_rx_ctl_ddr;
end
end
// Register all input signals on rising edge of gmii_rx_clk_bufg to syncronise.
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
gmii_rxd_reg[7:0] <= 8'b0;
gmii_rx_dv_reg <= 1'b0;
gmii_rx_er_reg <= 1'b0;
end
else
begin
gmii_rxd_reg[7:0] <= rgmii_rxd_reg[7:0];
gmii_rx_dv_reg <= rgmii_rx_dv_reg;
gmii_rx_er_reg <= rgmii_rx_ctl_reg ^ rgmii_rx_dv_reg;
end
end
//--------------------------------------------------------------------
// RGMII Inband Status Registers
// extract the inband status from received rgmii data
//--------------------------------------------------------------------
// Enable inband status registers during Interframe Gap
wire inband_ce;
assign inband_ce = !(gmii_rx_dv_reg || gmii_rx_er_reg);
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
eth_link_status <= 1'b0;
eth_clock_speed[1:0] <= 2'b0;
eth_duplex_status <= 1'b0;
end
else
if (inband_ce)
begin
eth_link_status <= gmii_rxd_reg[0];
eth_clock_speed[1:0] <= gmii_rxd_reg[2:1];
eth_duplex_status <= gmii_rxd_reg[3];
end
end
assign gmii_col_int = (gmii_tx_en_int | gmii_tx_er_int) & (gmii_rx_dv_reg | gmii_rx_er_reg);
assign gmii_crs_int = (gmii_tx_en_int | gmii_tx_er_int) | (gmii_rx_dv_reg | gmii_rx_er_reg);
endmodule // rgmii_io
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_ap_idle
always @(posedge ACLK) begin
if (ARESET)
int_ap_idle <= 1'b0;
else if (ACLK_EN) begin
int_ap_idle <= ap_idle;
end
end
// int_ap_ready
always @(posedge ACLK) begin
if (ARESET)
int_ap_ready <= 1'b0;
else if (ACLK_EN) begin
int_ap_ready <= ap_ready;
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
/*
* UART interface
*/
input wire rxd,
output wire txd,
/*
* Status
*/
output wire tx_busy,
output wire rx_busy,
output wire rx_overrun_error,
output wire rx_frame_error,
/*
* Configuration
*/
input wire [1:0] uart_bits,
input wire [1:0] uart_parity,
input wire [1:0] uart_stopbit,
input wire [15:0] prescale
);
// Decoder
reg [3:0] uart_data_width;
always @(uart_bits or uart_parity) begin
case(uart_bits)
2'b00: uart_data_width = 4'd8;
2'b01: uart_data_width = 4'd7;
2'b10: uart_data_width = 4'd6;
2'b11: uart_data_width = 4'd5;
default: uart_data_width = 4'd8;
endcase
if(uart_parity) uart_data_width = uart_data_width + 1;
end
uart_tx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
// output
.txd(txd),
// status
.busy(tx_busy),
// configuration
.uart_bits(uart_bits),
.uart_data_width(uart_data_width),
.uart_parity(uart_parity),
.uart_stopbit(uart_stopbit),
.prescale(prescale)
);
uart_rx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst (
.clk(clk),
.rst(rst),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
// input
.rxd(rxd),
// status
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
// configuration
.uart_data_width(uart_data_width),
.uart_parity(uart_parity),
.uart_stopbit(uart_stopbit),
.prescale(prescale)
);
endmodule
|
module test(
input clk, wen,
input [7:0] uns,
input signed [7:0] a, b,
input signed [23:0] c,
input signed [2:0] sel,
output [15:0] s, d, y, z, u, q, p, mul, div, mod, mux, And, Or, Xor, eq, neq, gt, lt, geq, leq, eqx, shr, sshr, shl, sshl, Land, Lor, Lnot, Not, Neg, pos, Andr, Orr, Xorr, Xnorr, Reduce_bool,
output [7:0] PMux
);
//initial begin
//$display("shr = %b", shr);
//end
assign s = a+{b[6:2], 2'b1};
assign d = a-b;
assign y = x;
assign z[7:0] = s+d;
assign z[15:8] = s-d;
assign p = a & b | x;
assign mul = a * b;
assign div = a / b;
assign mod = a % b;
assign mux = x[0] ? a : b;
assign And = a & b;
assign Or = a | b;
assign Xor = a ^ b;
assign Not = ~a;
assign Neg = -a;
assign eq = a == b;
assign neq = a != b;
assign gt = a > b;
assign lt = a < b;
assign geq = a >= b;
assign leq = a <= b;
assign eqx = a === b;
assign shr = a >> b; //0111111111000000
assign sshr = a >>> b;
assign shl = a << b;
assign sshl = a <<< b;
assign Land = a && b;
assign Lor = a || b;
assign Lnot = !a;
assign pos = $signed(uns);
assign Andr = &a;
assign Orr = |a;
assign Xorr = ^a;
assign Xnorr = ~^a;
always @*
if(!a) begin
Reduce_bool = a;
end else begin
Reduce_bool = b;
end
//always @(sel or c or a)
// begin
// case (sel)
// 3'b000: PMux = a;
// 3'b001: PMux = c[7:0];
// 3'b010: PMux = c[15:8];
// 3'b100: PMux = c[23:16];
// endcase
// end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 19:42:00 09/01/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: TF_EECS301_Lab3_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: EECS301 Lab3 Top Level Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_EECS301_Lab3_TopLevel();
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
reg CLOCK_50;
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: CLS_LED_Output_Fader
//
wire [9:0] LEDR;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
wire [6:0] HEX4;
wire [6:0] HEX5;
reg [3:0] KEY;
reg [1:0] SW;
EECS301_Lab3_TopLevel
#(
// Shorten the delay times for simulation
.KEY_LOCK_DELAY( 100000 ), // 100 uS
.SW_DEBOUNCE_TIME( 100 ), // 100 nS
.PWM_DUTY_RATE( 100000 ), // 100 kHz
.FADE_RATE_HZ( 10000 ) // 10 kHz
)
uut
(
// Clock Signals
.CLOCK_50( CLOCK_50 ),
// LED Signals
.LEDR( LEDR ),
// 7-Segment Display Signals (Active-Low)
.HEX0( HEX0 ),
.HEX1( HEX1 ),
.HEX2( HEX2 ),
.HEX3( HEX3 ),
.HEX4( HEX4 ),
.HEX5( HEX5 ),
// Button Signals (Active-Low)
.KEY( KEY ),
// Switch Signals
.SW( SW )
);
//
// Test Stimulus
//
initial
begin
// Initialize Signals
KEY = 4'hF; // Active-Low
SW = 2'h3;
#1000;
//
// Begin Testing
//
KEY[0] = 1'b0; // Press LED1 Right Button
KEY[3] = 1'b0; // Press LED2 Left Button
// Wait 5 ms
#5000000;
KEY[0] = 1'b1; // Release LED1 Right Button
KEY[1] = 1'b0; // Press LED1 Left Button
KEY[3] = 1'b0; // Press LED2 Left Button
// Wait 5 ms
#5000000;
KEY[3] = 1'b1; // Release LED2 Left Button
KEY[1] = 1'b0; // Press LED1 Left Button
KEY[2] = 1'b0; // Press LED2 Right Button
// Run simulation for 15 mS
end
endmodule
|
/*
Instruction Word
15: 0, First Word
31:16, Second Word
*/
`include "CoreDefs.v"
module DecOp3(
/* verilator lint_off UNUSED */
clk,
istrWord,
regCsFl,
idRegN,
idRegS,
idRegT,
idImm,
idStepPc,
idStepPc2,
idUCmd
);
parameter decEnable64 = 0; //Enable BJX1-64 ISA
parameter decEnable64A = 0; //Enable BJX1-64A ISA
parameter decEnableBJX1 = 1; //Enable BJX1 extensions
input clk; //clock
input[47:0] istrWord; //source instruction word
input[15:0] regCsFl; //current SR/FPSCR
output[6:0] idRegN;
output[6:0] idRegS;
output[6:0] idRegT;
output[31:0] idImm;
output[3:0] idStepPc;
output[3:0] idStepPc2;
output[7:0] idUCmd;
reg isOp32; //opcode is 32-bit
reg isOp8E; //8Ezz_zzzz
reg isOpCE; //CEzz_zzzz
reg isOpXE; //8Ezz_zzzz || CEzz_zzzz
reg isOpCC0; //CC0e_zzzz
reg isOpCC3; //CC3e_zzzz
reg[3:0] opCCe;
reg opPsDQ;
reg opPwDQ;
reg opPlDQ;
reg opJQ;
// reg opMovFpr;
reg opUseBase16; //op uses basic 16-bit decoder
reg[7:0] opPfxImm;
reg[15:0] opCmdWord;
reg[6:0] opRegN;
reg[6:0] opRegS;
reg[6:0] opRegT; //Index for mem ops
reg[31:0] opImm; //Disp for mem ops
reg[7:0] opUCmd;
reg[3:0] opStepPc;
reg[3:0] opStepPc2;
assign idRegN = opRegN;
assign idRegS = opRegS;
assign idRegT = opRegT;
assign idImm = opImm;
assign idUCmd = opUCmd;
assign idStepPc = opStepPc;
assign idStepPc2 = opStepPc2;
// reg[6:0] tOpRegDflN;
// reg[6:0] tOpRegDflM;
// reg tOpDflRns;
// reg tOpDflRnst;
reg[4:0] tOpDecXfrm;
reg[3:0] tOpDecXfrmZx;
reg[7:0] tOpW2;
reg[6:0] opRegN_Dfl;
reg[6:0] opRegM_Dfl;
reg[6:0] opRegO_Dfl;
reg[6:0] opRegS_8E;
reg[6:0] opRegT_8E;
reg[6:0] opRegN_CEf;
reg[6:0] opRegM_CEf;
reg[6:0] opRegN_CEe;
reg[6:0] opRegM_CEe;
reg[6:0] opRegO_CEe;
reg[6:0] opRegT_CEe;
reg[6:0] opRegM_CR;
reg[6:0] opRegM_SR;
reg[6:0] opRegN_FR;
reg[6:0] opRegM_FR;
reg[6:0] opRegO_FR;
reg[6:0] opRegS_FR;
reg[6:0] opRegT_FR;
reg[6:0] opRegN_N3;
reg[6:0] opRegM_N3;
reg[31:0] opImm_Zx4;
reg[31:0] opImm_Zx4_8E;
reg[31:0] opImm_Zx8;
reg[31:0] opImm_Sx8;
reg[31:0] opImm_Sx12;
reg[31:0] opImm_Sx8E;
reg[31:0] opImm_Zx8E;
reg[31:0] opImm_Nx8E;
reg[31:0] opImm_Sx16_8E;
reg[31:0] opImm_Sx20_8E;
reg[31:0] opImmM_Sx12_8E;
reg[31:0] opImmO_Sx12_8E;
reg[31:0] opImm6_SxCE;
reg[31:0] opImm6_ZxCE;
reg[31:0] opImm6_NxCE;
reg opIsRegN_FR;
reg opIsRegM_FR;
reg opIsRegS_FR;
reg opIsRegT_FR;
reg opIsRegM_CR;
reg opIsRegM_SR;
always @*
begin
opStepPc = 2;
// opPfxImm=0;
// opCmdWord=0;
opPfxImm=8'hXX;
opCmdWord=0;
// opRegN=0;
// opRegS=0;
// opRegT=0;
opUCmd=UCMD_UDBRK;
opImm=0;
isOp32=0;
isOp8E=0; isOpCE=0; isOpXE=0;
isOpCC0=0; isOpCC3=0; opCCe=0;
// opMovFpr=0;
opUseBase16=1;
opRegN=UREG_ZZR;
opRegS=UREG_ZZR;
opRegT=UREG_ZZR;
opIsRegN_FR=0; opIsRegM_FR=0;
opIsRegS_FR=0; opIsRegT_FR=0;
opIsRegM_CR=0; opIsRegM_SR=0;
tOpDecXfrm=UXFORM_CST;
tOpDecXfrmZx=UXFORMZX_SX;
if(decEnable64 && regCsFl[5])
begin
opJQ=1; opPsDQ=regCsFl[6];
opPwDQ=opPsDQ; opPlDQ=0;
end else begin
opJQ=0; opPsDQ=0;
opPwDQ=0; opPlDQ=0;
end
opCmdWord=istrWord[15:0];
tOpW2=istrWord[31:24];
if(decEnableBJX1)
begin
case(istrWord[15:8])
8'h8A: begin
isOp32=1;
opCmdWord=istrWord[15:0];
tOpW2=istrWord[47:40];
opImm[31:24]=istrWord[7]?8'hFF:8'h00;
opImm[23:16]=istrWord[7:0];
opImm[15: 0]=istrWord[31:16];
opRegN=UREG_R0;
opUCmd=UCMD_MOV_RI;
tOpDecXfrm=UXFORM_CST;
opUseBase16=0;
end
8'h8E: begin
isOp32=1;
isOp8E=1;
isOpXE=1;
opPfxImm=istrWord[7:0];
opCmdWord=istrWord[31:16];
tOpW2=istrWord[47:40];
end
8'hCC: begin
if(decEnable64A && opJQ)
begin
isOp32=1;
isOpCE=0;
isOpXE=0;
isOpCC0 = (istrWord[7:4]==4'h0);
isOpCC3 = (istrWord[7:4]==4'h3);
opCCe=istrWord[3:0];
opPsDQ=istrWord[3];
opPwDQ=0;
opPlDQ=opPsDQ;
opPfxImm=0;
opCmdWord=istrWord[31:16];
tOpW2=istrWord[47:40];
end
end
8'hCE: begin
if(decEnable64A && opJQ)
begin
isOp32=1;
isOpCE=1;
isOpXE=1;
opPfxImm=istrWord[7:0];
opCmdWord=istrWord[31:16];
tOpW2=istrWord[47:40];
opPsDQ=istrWord[7];
opPwDQ=0;
opPlDQ=0;
end
end
default: begin
end
endcase
if(isOp32)
opStepPc = 4;
end
opStepPc2 = 2;
if(decEnableBJX1)
begin
case(tOpW2)
8'h8A: opStepPc2 = 4;
8'h8C: opStepPc2 = 4;
8'h8E: opStepPc2 = 4;
8'hCC: opStepPc2 = (opJQ && decEnable64A) ? 4 : 2;
8'hCE: opStepPc2 = (opJQ && decEnable64A) ? 4 : 2;
default: opStepPc2 = 2;
endcase
end
if(decEnable64A)
begin
if(isOpCC3) /* BJX1-64A */
begin
opUseBase16=0;
casez(opCmdWord[15:12])
4'h0: opUCmd=UCMD_ALU_ADD;
4'h1: opUCmd=UCMD_ALU_SUB;
4'h2: opUCmd=UCMD_ALU_MUL;
4'h3: opUCmd=UCMD_ALU_AND;
4'h4: opUCmd=UCMD_ALU_OR;
4'h5: opUCmd=UCMD_ALU_XOR;
4'h6: opUCmd=opCCe[3] ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD;
4'h7: opUCmd=opCCe[3] ? UCMD_ALU_SHLDRQ : UCMD_ALU_SHLDR;
4'h8: opUCmd=opCCe[3] ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD;
4'h9: opUCmd=opCCe[3] ? UCMD_ALU_SHADRQ : UCMD_ALU_SHADR;
4'hC: opUCmd=UCMD_FPU_ADD;
4'hD: opUCmd=UCMD_FPU_SUB;
4'hE: opUCmd=UCMD_FPU_MUL;
default: begin end
endcase
if(opCmdWord[15:14]==2'h3)
begin
opRegN={2'h2, opCCe[2], opCmdWord[11:8]};
opRegS={2'h2, opCCe[1], opCmdWord[ 7:4]};
opRegT={2'h2, opCCe[0], opCmdWord[ 3:0]};
end
else
begin
opRegN={2'h0, opCCe[2], opCmdWord[11:8]};
opRegS={2'h0, opCCe[1], opCmdWord[ 7:4]};
opRegT={2'h0, opCCe[0], opCmdWord[ 3:0]};
end
tOpDecXfrm=UXFORM_CST;
end
end
if(opUseBase16)
casez(opCmdWord[15:0])
16'h0zz0: begin
/* Unimplemented, 2A */
end
16'h0zz1: begin
/* Unimplemented, 2A */
end
16'h0zz2: begin //0xx2, STC
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS;
tOpDecXfrmZx=UXFORMZX_CR;
end
16'h0zz4: begin //0xx4
opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h0zz5: begin //0xx5
opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h0zz6: begin //0xx6
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h0zz7: begin //0xx7
if(isOpXE)
begin
opUCmd=UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_NSO;
end
else
begin
opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST;
end
end
/* 0xx8 */
16'h0z08: begin //0x08
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_CLRT;
tOpDecXfrm=UXFORM_CST;
end
16'h0z18: begin //0x18
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_SETT;
tOpDecXfrm=UXFORM_CST;
end
16'h0z28: begin //0x28
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_CLRMAC;
tOpDecXfrm=UXFORM_CST;
end
16'h0z38: begin //0x38
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_LDTLB;
tOpDecXfrm=UXFORM_CST;
end
16'h0z48: begin //0x48
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_CLRS;
tOpDecXfrm=UXFORM_CST;
end
16'h0z58: begin //0x58
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_SETS;
tOpDecXfrm=UXFORM_CST;
end
16'h0z68: begin //0x68
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_NOTT;
tOpDecXfrm=UXFORM_CST;
end
/* 0xx9 */
16'h0z09: begin //0x09
opUCmd=UCMD_NONE; tOpDecXfrm=UXFORM_Z;
end
16'h0z19: begin //0x19
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_DIV0U;
tOpDecXfrm=UXFORM_CST;
end
16'h0z29: begin //0x29
opUCmd=UCMD_ALU_MOVT; tOpDecXfrm=UXFORM_N;
end
16'h0z39: begin //0x39
opUCmd=UCMD_ALU_MOVRT; tOpDecXfrm=UXFORM_N;
end
16'h0zzA: begin //0xxA
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS;
tOpDecXfrmZx=UXFORMZX_SR;
end
/* 0xxB */
16'h0z0B: begin //0z0B
opUCmd=UCMD_RTS; tOpDecXfrm=UXFORM_Z;
end
16'h0z1B: begin //0x1B
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_SLEEP;
tOpDecXfrm=UXFORM_CST;
end
16'h0z2B: begin //0z2B
opUCmd=UCMD_RTE; tOpDecXfrm=UXFORM_Z;
end
16'h0z3B: begin //0z3B
opUCmd=UCMD_UDBRK; tOpDecXfrm=UXFORM_Z;
opImm=1;
if(opCmdWord[11:8]==4'hF)
begin
opUCmd=UCMD_NONE;
opStepPc=0;
end
end
16'h0z6B: begin //0z6B
opUCmd=UCMD_RTSN; tOpDecXfrm=UXFORM_Z;
end
16'h0zzC: begin //0xxC
opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h0zzD: begin //0xxD
opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h0zzE: begin //0xxE
opUCmd = opPlDQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h0zzF: begin //0xxF
//MAC.L
end
16'h1zzz: begin //1nmd, MOV.L Rm, @(Rn, disp4)
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSJ;
end
16'h2zz0: begin //2xx0, MOV.B Rm, @Rn
opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS;
end
16'h2zz1: begin //2xx1, MOV.W Rm, @Rn
opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
16'h2zz2: begin //2xx2, MOV.L Rm, @Rn
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
16'h2zz3: begin //2xx3, CAS.L Rm, Rn, @R0
opUCmd=UCMD_CASL; tOpDecXfrm=UXFORM_MOV_NSO;
end
16'h2zz4: begin //2xx4, MOV.B @Rm, Rn
opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PDEC;
end
16'h2zz5: begin //2xx5, MOV.W @Rm, Rn
opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PDEC;
end
16'h2zz6: begin //2xx6, MOV.L @Rm, Rn
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PDEC;
end
16'h2zz7: begin //2xx7, DIV0S Rm, Rn
opUCmd=UCMD_ALU_DIV0S; tOpDecXfrm=UXFORM_ARI_ST;
end
16'h2zz8: begin //2xx8, TST Rm, Rn
opUCmd=UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_ST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h2zz9: begin //2xx9, AND Rm, Rn
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h2zzA: begin //2xxA, XOR Rm, Rn
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h2zzB: begin //2xxB, OR Rm, Rn
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h2zzC: begin //2xxC, CMPSTR Rm, Rn
opUCmd=UCMD_ALU_CMPSTR; tOpDecXfrm=UXFORM_ARI_NST;
end
16'h2zzD: begin //2xxD, XTRCT Rm, Rn
opUCmd=UCMD_ALU_XTRCT; tOpDecXfrm=UXFORM_ARI_NST;
end
16'h2zzE: begin //2xxE, MULU.W Rm, Rn
opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST;
end
16'h2zzF: begin //2xxF, MULS.W Rm, Rn
opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST;
end
16'h3zz0: begin //3xx0, CMP/EQ Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ;
tOpDecXfrm=UXFORM_CMP_ST;
end
16'h3zz1: begin //3xx1
end
16'h3zz2: begin //3xx2, CMP/HS Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS;
tOpDecXfrm=UXFORM_CMP_ST;
end
16'h3zz3: begin //3xx3, CMP/GE Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE;
tOpDecXfrm=UXFORM_CMP_ST;
end
16'h3zz4: begin //3xx4, DIV1 Rm, Rn
opUCmd=UCMD_ALU_DIV1; tOpDecXfrm=UXFORM_ARI_NST;
end
16'h3zz5: begin //3xx5, DMULU.L Rm, Rn
opUCmd=UCMD_ALU_DMULU; tOpDecXfrm=UXFORM_ARI_ST;
end
16'h3zz6: begin //3xx6, CMP/HI Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_HI : UCMD_CMP_HI;
tOpDecXfrm=UXFORM_CMP_ST;
end
16'h3zz7: begin //3xx7, CMP/GT Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT;
tOpDecXfrm=UXFORM_CMP_ST;
end
16'h3zz8: begin //3xx8, SUB Rm, Rn
opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h3zz9: begin //3xx9
end
16'h3zzA: begin //3xxA, SUBC Rm, Rn
opUCmd=UCMD_ALU_SUBC; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h3zzB: begin //3xxB, SUBV Rm, Rn
opUCmd=UCMD_ALU_SUBV; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h3zzC: begin //3xxC, ADD Rm, Rn
opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
16'h3zzD: begin //3xxD, DMULS.L Rm, Rn
opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST;
end
16'h3zzE: begin //3xxE, ADDC Rm, Rn
opUCmd=UCMD_ALU_ADDC; tOpDecXfrm=UXFORM_ARI_NST;
end
16'h3zzF: begin //3xxF, ADDV Rm, Rn
opUCmd=UCMD_ALU_ADDV; tOpDecXfrm=UXFORM_ARI_NST;
end
/* 4xx0 */
16'h4z00: begin //4x00
opUCmd=UCMD_ALU_SHLL; tOpDecXfrm=UXFORM_N;
end
16'h4z10: begin //4x10
opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N;
end
16'h4z20: begin //4x20
opUCmd=UCMD_ALU_SHAL; tOpDecXfrm=UXFORM_N;
end
/* 4xx1 */
16'h4z01: begin //4x01
opUCmd=UCMD_ALU_SHLR; tOpDecXfrm=UXFORM_N;
end
16'h4z11: begin //4x11
opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE;
tOpDecXfrm=UXFORM_M;
end
16'h4z21: begin //4x21
opUCmd=UCMD_ALU_SHAR; tOpDecXfrm=UXFORM_N;
end
16'h4zz2: begin //4xx2
opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_SR;
end
16'h4zz3: begin //4xx3
if(isOpXE) begin
case(opCmdWord[7:4])
4'h0: begin
opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_NST_8E;
end
4'h1: begin
opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_NST_8E;
end
4'h2: begin
opUCmd=UCMD_ALU_MUL; tOpDecXfrm=UXFORM_NST_8E;
end
4'h3: begin
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_NST_8E;
end
4'h4: begin
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h5: begin
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h6: begin
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_NST_8E;
end
4'h7: begin
opUCmd=UCMD_ALU_SHLDR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h8: begin
opUCmd=UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_NST_8E;
end
4'h9: begin
opUCmd=UCMD_ALU_SHADR; tOpDecXfrm=UXFORM_NST_8E;
end
4'hC: begin
opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_NST_8E;
// opIsRegN_FR=1; opIsRegS_FR=1; opIsRegT_FR=1;
tOpDecXfrmZx=UXFORMZX_FF;
end
4'hD: begin
opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_NST_8E;
// opIsRegN_FR=1; opIsRegS_FR=1; opIsRegT_FR=1;
tOpDecXfrmZx=UXFORMZX_FF;
end
4'hE: begin
opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_NST_8E;
// opIsRegN_FR=1; opIsRegS_FR=1; opIsRegT_FR=1;
tOpDecXfrmZx=UXFORMZX_FF;
end
default: begin end
endcase
end
else
begin
opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_CR;
end
end
/* 4xx4 */
16'h4z04: begin //4x00
opUCmd=UCMD_ALU_ROTL; tOpDecXfrm=UXFORM_N;
end
16'h4z14: begin //4x10
// opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N;
end
16'h4z24: begin //4x20
opUCmd=UCMD_ALU_ROTCL; tOpDecXfrm=UXFORM_N;
end
/* 4xx5 */
16'h4z05: begin //4x01
opUCmd=UCMD_ALU_ROTR; tOpDecXfrm=UXFORM_N;
end
16'h4z15: begin //4x11
opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT;
tOpDecXfrm=UXFORM_M;
end
16'h4z25: begin //4x21
opUCmd=UCMD_ALU_ROTCR; tOpDecXfrm=UXFORM_N;
end
16'h4zz6: begin //4xx6
opUCmd = opJQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_RS;
end
16'h4zz7: begin //4xx7
opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_RC;
end
/* 4xx8 */
16'h4z08: begin //4x08
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=2;
end
16'h4z18: begin //4x18
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=8;
end
16'h4z28: begin //4x28
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=16;
end
/* 4xx9 */
16'h4z09: begin //4x09
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=-2;
end
16'h4z19: begin //4x19
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=-8;
end
16'h4z29: begin //4x29
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=-16;
end
16'h4zzA: begin //4xxA, LDS
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS;
tOpDecXfrmZx=UXFORMZX_RS;
end
/* 4xxB */
16'h4z0B: begin
opUCmd=UCMD_JSR; tOpDecXfrm=UXFORM_M;
end
16'h4z2B: begin
opUCmd=UCMD_JMP; tOpDecXfrm=UXFORM_M;
end
16'h4z3B: begin
end
16'h4z4B: begin
opUCmd=UCMD_JSRN; tOpDecXfrm=UXFORM_M;
end
16'h4zzC: begin //4xxC
opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_SX;
end
16'h4zzD: begin //4xxD
opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_SX;
end
16'h4zzE: begin //4xxE, LDC
if(isOpXE) begin
case(opCmdWord[7:4])
4'h0: begin
opUCmd=UCMD_MOVUB_MR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h1: begin
opUCmd=UCMD_MOVUW_MR; tOpDecXfrm=UXFORM_NST_8E;
end
default: begin end
endcase
end
else
begin
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS;
tOpDecXfrmZx=UXFORMZX_RC;
end
end
16'h5zzz: begin //5xxx
opUCmd = opPlDQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSJ;
end
16'h6zz0: begin //6xx0
opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS;
end
16'h6zz1: begin //6xx1
opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
16'h6zz2: begin //6xx2
opUCmd = opPlDQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
16'h6zz3: begin //6xx3
if(isOpXE) begin
opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zz4: begin //6xx4
if(isOpXE) begin
opUCmd=UCMD_LEAB_MR; tOpDecXfrm=UXFORM_MOV_NSO;
end else begin
opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PINC;
end
end
16'h6zz5: begin //6xx5
if(isOpXE) begin
opUCmd=UCMD_LEAW_MR; tOpDecXfrm=UXFORM_MOV_NSO;
end else begin
opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PINC;
end
end
16'h6zz6: begin //6xx6
if(isOpXE) begin
opUCmd=UCMD_LEAL_MR; tOpDecXfrm=UXFORM_MOV_NSO;
end else begin
opUCmd = opPlDQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PINC;
end
end
16'h6zz7: begin
if(isOpXE) begin
opUCmd=UCMD_LEAQ_MR; tOpDecXfrm=UXFORM_MOV_NSO;
end else begin
opUCmd=UCMD_ALU_NOT; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zz8: begin
if(isOpXE) begin
opUCmd=UCMD_LEAB_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_SWAPB; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zz9: begin
if(isOpXE) begin
opUCmd=UCMD_LEAW_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_SWAPW; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zzA: begin
if(isOpXE) begin
opUCmd=UCMD_LEAL_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_NEGC; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zzB: begin
if(isOpXE) begin
opUCmd=UCMD_LEAQ_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_NEG; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zzC: begin
if(isOpXE) begin
opUCmd=UCMD_MOVUB_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_EXTUB; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zzD: begin
if(isOpXE) begin
opUCmd=UCMD_MOVUW_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_EXTUW; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zzE: begin
if(isOpXE) begin
opUCmd=UCMD_MOVUL_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_EXTSB; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h6zzF: begin
if(isOpXE) begin
opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NS;
end else begin
opUCmd=UCMD_ALU_EXTSW; tOpDecXfrm=UXFORM_ARI_NS;
end
end
16'h7zzz: begin //7xxx
opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI;
end
16'h80zz: begin //80xx
opUCmd=UCMD_MOVB_RM;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_RM0;
end
16'h81zz: begin //81xx
opUCmd=UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_RM0;
end
16'h82zz: begin //82xx
opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8;
end
16'h83zz: begin //83xx
if(isOpXE) begin
opUCmd=UCMD_BSRN; tOpDecXfrm=UXFORM_BR_D8;
end else begin
tOpDecXfrm=UXFORM_MOV_SP4RN;
if(opCmdWord[7])
begin
opUCmd=UCMD_MOVL_MR;
tOpDecXfrmZx=UXFORMZX_MR3;
end else begin
opUCmd=UCMD_MOVL_RM;
tOpDecXfrmZx=UXFORMZX_RM3;
end
end
end
16'h84zz: begin //84xx
opUCmd=UCMD_MOVB_MR;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_MR0;
end
16'h85zz: begin //85xx
opUCmd=UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_MR0;
end
16'h86zz: begin //86xx
if(isOpXE) begin
// opUCmd=UCMD_BSRN; tOpDecXfrm=UXFORM_BR_D8;
end else begin
tOpDecXfrm=UXFORM_MOV_SP4RN;
if(opCmdWord[7])
begin
opUCmd=UCMD_MOVL_MR;
tOpDecXfrmZx=UXFORMZX_MF3;
end else begin
opUCmd=UCMD_MOVL_RM;
tOpDecXfrmZx=UXFORMZX_FM3;
end
end
end
16'h87zz: begin //87xx
end
16'h88zz: begin //88xx
opUCmd=UCMD_CMP_EQ;
tOpDecXfrm=UXFORM_ARI_I8R0;
end
16'h89zz: begin //89xx
opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8;
end
16'h8Azz: begin //8Axx-xxxx
if(isOpXE) begin
// opUCmd=UCMD_BSRN; tOpDecXfrm=UXFORM_BR_D8;
end else begin
opRegN=UREG_R0;
opUCmd=UCMD_MOV_RI;
tOpDecXfrm=UXFORM_CST;
end
end
16'h8Bzz: begin //8Bxx, BF disp
opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8;
end
16'h8Czz: begin //8Cxx
/* Escape */
end
16'h8Dzz: begin //8Dxx, BTS disp
opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8;
end
16'h8Ezz: begin //8Exx
/* Escape */
end
16'h8Fzz: begin //8Fxx, BFS disp
opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8;
end
16'h9zzz: begin //9xxx
if(isOpXE)
begin //LDSH16 #imm, Rn
opUCmd=UCMD_ALU_LDSH16;
tOpDecXfrm=UXFORM_ARI_NNI;
end else begin //MOV.W @(PC, disp), Rn
opRegN[3:0]=opCmdWord[11:8];
opRegS=UREG_PCW;
opRegT=UREG_ZZR;
opImm[7:0]=opCmdWord[ 7:0];
opUCmd=UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_CST;
end
end
16'hAzzz: begin //Axxx
opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12;
end
16'hBzzz: begin //Bxxx
opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12;
end
16'hC0zz: begin
if(opJQ)
begin
opUCmd=UCMD_MOVQ_RM;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_RM;
end else begin
opUCmd=UCMD_MOVB_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_RM;
end
end
16'hC1zz: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_RM;
end
end
16'hC2zz: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_RM;
end
end
16'hC4zz: begin
if(opJQ)
begin
opUCmd=UCMD_MOVQ_MR;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_MR;
end else begin
opUCmd=UCMD_MOVB_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_MR;
end
end
16'hC5zz: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_MR;
end
end
16'hC6zz: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_MR;
end
end
16'hC8zz: begin //CMP/EQ #imm, R0
opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST;
tOpDecXfrm=UXFORM_CMP_I8R0;
end
16'hC9zz: begin //AND #imm, R0
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0;
end
16'hCAzz: begin //XOR #imm, R0
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0;
end
16'hCBzz: begin //OR #imm, R0
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0;
end
16'hDzzz: begin //Dxxx, MOV @(PC,disp), Rn
opRegN[3:0]=opCmdWord[11:8];
opRegS=UREG_PCL;
opRegT=UREG_ZZR;
opImm[7:0]=opCmdWord[ 7:0];
opUCmd=UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_CST;
end
16'hEzzz: begin //Exxx, MOV #imm, Rn
opUCmd=UCMD_MOV_RI;
tOpDecXfrm=UXFORM_ARI_NNI;
end
16'hFzz0: begin
opUCmd=UCMD_FPU_ADD;
tOpDecXfrm=UXFORM_FPARI_NS;
// tOpDecXfrmZx=UXFORMZX_FF;
end
16'hFzz1: begin
opUCmd=UCMD_FPU_SUB;
tOpDecXfrm=UXFORM_FPARI_NS;
// tOpDecXfrmZx=UXFORMZX_FF;
end
16'hFzz2: begin
opUCmd=UCMD_FPU_MUL;
tOpDecXfrm=UXFORM_FPARI_NS;
// tOpDecXfrmZx=UXFORMZX_FF;
end
16'hFzz4: begin
opUCmd=UCMD_FPU_CMPEQ;
tOpDecXfrm=UXFORM_FPARI_NS;
// tOpDecXfrmZx=UXFORMZX_FF;
end
16'hFzz5: begin
opUCmd=UCMD_FPU_CMPGT;
tOpDecXfrm=UXFORM_FPARI_NS;
// tOpDecXfrmZx=UXFORMZX_FF;
end
16'hFzz6: begin
opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO;
tOpDecXfrmZx=UXFORMZX_RF;
end
16'hFzz7: begin
opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO;
tOpDecXfrmZx=UXFORMZX_FR;
end
16'hFzz8: begin
opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS;
// opIsRegN_FR=1;
tOpDecXfrmZx=UXFORMZX_RF;
end
16'hFzz9: begin
opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC;
// opIsRegN_FR=1;
tOpDecXfrmZx=UXFORMZX_RFI;
end
16'hFzzA: begin
opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS;
// opIsRegM_FR=1;
tOpDecXfrmZx=UXFORMZX_FR;
end
16'hFzzB: begin
// opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC;
opIsRegM_FR=1;
tOpDecXfrmZx=UXFORMZX_FRD;
end
default: begin end
endcase
// opIsRegN_FR=0;
// opIsRegM_FR=0;
// opIsRegS_FR=0;
// opIsRegT_FR=0;
// opIsRegM_CR=0;
// opIsRegM_SR=0;
if(decEnable64A)
begin
/*
opRegN_Dfl = {opIsRegN_FR?2'b10:2'b00, opCCe[2], opCmdWord[11:8]};
opRegN_CEf = {opIsRegN_FR?2'b10:2'b00, opPfxImm[7], opCmdWord[11:8]};
opRegN_CEe = {opIsRegN_FR?2'b10:2'b00, opPfxImm[6], opCmdWord[11:8]};
opRegM_Dfl = {opIsRegM_FR?2'b10:2'b00, opCCe[1], opCmdWord[ 7:4]};
opRegM_CEf = {opIsRegM_FR?2'b10:2'b00, opPfxImm[6], opCmdWord[ 7:4]};
opRegS_CEe = {opIsRegM_FR?2'b10:2'b00, opPfxImm[5], opCmdWord[ 7:4]};
opRegT_CEe = {opIsRegT_FR?2'b10:2'b00, opPfxImm[4], opPfxImm [ 3:0]};
*/
opRegN_Dfl = {2'b00, opCCe[2], opCmdWord[11:8]};
opRegN_CEf = {2'b00, opPfxImm[7], opCmdWord[11:8]};
opRegN_CEe = {2'b00, opPfxImm[6], opCmdWord[11:8]};
opRegM_Dfl = {2'b00, opCCe[1], opCmdWord[ 7:4]};
opRegM_CEf = {2'b00, opPfxImm[6], opCmdWord[ 7:4]};
opRegM_CEe = {2'b00, opPfxImm[5], opCmdWord[ 7:4]};
opRegO_CEe = {2'b00, opPfxImm[4], opCmdWord[ 3:0]};
opRegT_CEe = {2'b00, opPfxImm[4], opPfxImm [ 3:0]};
opRegO_Dfl = {2'b00, opCCe[0], opCmdWord[ 3:0]};
opImm6_SxCE = {opPfxImm[5] ? 26'h3FFFFFF : 26'h0, opPfxImm [ 5:0]};
opImm6_ZxCE = {26'h000000, opPfxImm [ 5:0]};
opImm6_NxCE = {26'hFFFFFF, opPfxImm [ 5:0]};
end
else
begin
// opRegN_Dfl = {opIsRegN_FR?3'b100:3'b000, opCmdWord[11:8]};
// opRegM_Dfl = {opIsRegM_FR?3'b100:3'b000, opCmdWord[ 7:4]};
opRegN_Dfl = {3'b000, opCmdWord[11:8]};
opRegM_Dfl = {3'b000, opCmdWord[ 7:4]};
opRegO_Dfl = {3'b000, opCmdWord[ 3:0]};
// opRegN_CEf = 7'hXX;
// opRegM_CEf = 7'hXX;
opRegN_CEf = opRegN_Dfl;
opRegM_CEf = opRegM_Dfl;
opRegN_CEe = 7'hXX;
opRegM_CEe = 7'hXX;
opRegO_CEe = 7'hXX;
opRegT_CEe = 7'hXX;
end
/*
if(opIsRegM_CR)
begin
if(opCmdWord[11]) //RmB
opRegM_Dfl={3'h2, 1'b0, opCmdWord[6:4]};
else
opRegM_Dfl={3'h7, opCmdWord[7:4]};
end else if(opIsRegM_SR)
begin
opRegM_Dfl={3'h6, opCmdWord[7:4]};
end
*/
// /*
if(opCmdWord[11]) //RmB
opRegM_CR={3'h2, 1'b0, opCmdWord[6:4]};
else
opRegM_CR={3'h7, opCmdWord[7:4]};
opRegM_SR={3'h6, opCmdWord[7:4]};
// */
opRegN_FR = {3'h4, opCmdWord[11:8]};
opRegM_FR = {3'h4, opCmdWord[ 7:4]};
opRegO_FR = {3'h4, opCmdWord[ 3:0]};
if(decEnableBJX1)
begin
// opRegS_8E = {opIsRegS_FR?3'b100:3'b000, opPfxImm [ 7:4]};
// opRegT_8E = {opIsRegT_FR?3'b100:3'b000, opPfxImm [ 3:0]};
opRegS_8E = {3'b000, opPfxImm [ 7:4]};
opRegT_8E = {3'b000, opPfxImm [ 3:0]};
opRegS_FR = {3'h4, opPfxImm [ 7:4]};
opRegT_FR = {3'h4, opPfxImm [ 3:0]};
opImm_Zx4_8E = {28'h0, opPfxImm [ 3:0]};
opImm_Sx8E = {opPfxImm[7] ? 24'hFFFFFF : 24'h0, opPfxImm [ 7:0]};
opImm_Zx8E = {24'h000000, opPfxImm [ 7:0]};
opImm_Nx8E = {24'hFFFFFF, opPfxImm [ 7:0]};
opImmM_Sx12_8E = {opPfxImm[7] ? 20'hFFFFF : 20'h0,
opPfxImm [ 7:0], opCmdWord [ 7:4]};
opImmO_Sx12_8E = {opPfxImm[7] ? 20'hFFFFF : 20'h0,
opPfxImm [ 7:0], opCmdWord [ 3:0]};
opImm_Sx16_8E = {opPfxImm[7] ? 16'hFFFF : 16'h0000,
opPfxImm [ 7:0], opCmdWord [ 7:0]};
opImm_Sx20_8E = {opPfxImm[7] ? 12'hFFF : 12'h000,
opPfxImm [ 7:0], opCmdWord [11:0]};
opRegN_N3 = (opCmdWord[6:4]==3'b111) ? UREG_R0 :
{3'h0, 1'b1, opCmdWord[6:4]};
opRegM_N3 = (opCmdWord[2:0]==3'b111) ? UREG_R0 :
{3'h0, 1'b1, opCmdWord[2:0]};
end
else
begin
opRegS_8E = 7'hXX; opRegT_8E = 7'hXX;
opRegS_FR = 7'hXX; opRegT_FR = 7'hXX;
opImm_Zx4_8E = 32'hXXXXXXXX; opImm_Sx8E = 32'hXXXXXXXX;
opImm_Zx8E = 32'hXXXXXXXX; opImm_Nx8E = 32'hXXXXXXXX;
opImm_Sx16_8E = 32'hXXXXXXXX; opImm_Sx20_8E = 32'hXXXXXXXX;
opImmM_Sx12_8E = 32'hXXXXXXXX; opImmO_Sx12_8E = 32'hXXXXXXXX;
opRegN_N3=UREG_XX; opRegM_N3=UREG_XX;
end
opImm_Zx4 = {28'h0, opCmdWord[ 3:0]};
opImm_Zx8 = {24'h0, opCmdWord[ 7:0]};
opImm_Sx8 = {opCmdWord[ 7] ? 24'hFFFFFF : 24'h000000, opCmdWord [ 7:0]};
opImm_Sx12 = {opCmdWord[11] ? 20'hFFFFF : 20'h00000 , opCmdWord [11:0]};
case(tOpDecXfrm)
UXFORM_CST: begin
end
UXFORM_N: begin
opRegN=opRegN_Dfl;
opRegS=opRegN;
end
UXFORM_MOV_NS: begin
if(isOpCE)
begin
opRegN = opRegN_CEf; opRegS = opRegM_CEf;
opImm = opImm6_ZxCE;
end else if(isOp8E)
begin
opRegN = opRegN_Dfl; opRegS = opRegM_Dfl;
opImm = opImm_Sx8E;
end else begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
// if(tOpDecXfrmZx==UXFORMZX_RF) opRegN[6:5]=2'b10;
// if(tOpDecXfrmZx==UXFORMZX_FR) opRegS[6:5]=2'b10;
end
UXFORM_MOV_NSO: begin
if(isOpCE)
begin
opRegN=opRegN_CEe; opRegS=opRegM_CEe;
opRegT=opRegT_CEe; opImm=0;
end else if(isOp8E)
begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=opRegS_8E; opImm=opImm_Zx4_8E;
end else begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_R0; opImm=0;
end
// if(tOpDecXfrmZx==UXFORMZX_RF) opRegN[6:5]=2'b10;
// if(tOpDecXfrmZx==UXFORMZX_FR) opRegS[6:5]=2'b10;
end
UXFORM_MOV_NSJ: begin
if(isOpCE)
begin
opRegN = opRegN_CEe;
opRegS = opRegM_CEe;
opRegT = opRegO_CEe;
opImm = opImm_Zx4_8E;
end else if(isOp8E)
begin
opRegN = opRegN_Dfl; opRegS = opRegM_Dfl;
opRegT = opRegO_Dfl; opImm = opImm_Sx8E;
end else begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opImm = opImm_Zx4;
end
// if(tOpDecXfrmZx==UXFORMZX_RF) opRegN[6:5]=2'b10;
// if(tOpDecXfrmZx==UXFORMZX_FR) opRegS[6:5]=2'b10;
end
UXFORM_MOV_NSDEC: begin
case(tOpDecXfrmZx)
UXFORMZX_PDEC: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMDEC;
end
UXFORMZX_PINC: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMINC;
end
// /*
UXFORMZX_FRD: begin
opRegN=opRegN_Dfl; opRegS=opRegM_FR;
opRegT=UREG_MR_MEMDEC;
end
UXFORMZX_RFI: begin
opRegN=opRegN_FR; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMINC;
end
UXFORMZX_RS: begin
opRegN=opRegM_SR; opRegS=opRegN_Dfl;
opRegT=UREG_MR_MEMINC;
end
UXFORMZX_RC: begin
opRegN=opRegM_CR; opRegS=opRegN_Dfl;
opRegT=UREG_MR_MEMINC;
end
UXFORMZX_SR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_SR;
opRegT=UREG_MR_MEMDEC;
end
UXFORMZX_CR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_CR;
opRegT=UREG_MR_MEMDEC;
end
// */
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_FPARI_NS: begin
opRegN=opRegN_FR;
opRegS=opRegM_FR;
end
UXFORM_ARI_NS: begin
// opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
// /*
case(tOpDecXfrmZx)
UXFORMZX_RR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
UXFORMZX_FF: begin
opRegN=opRegN_FR; opRegS=opRegM_FR;
end
UXFORMZX_RS: begin
opRegN=opRegM_SR; opRegS=opRegN_Dfl;
end
UXFORMZX_RC: begin
opRegN=opRegM_CR; opRegS=opRegN_Dfl;
end
UXFORMZX_SR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_SR;
end
UXFORMZX_CR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_CR;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
// */
end
UXFORM_ARI_NST: begin
if(isOpCE)
begin
opRegN=opRegN_CEf; opRegS=opRegM_CEf;
opRegT=UREG_MR_IMM;
case(tOpDecXfrmZx)
UXFORMZX_SX: opImm=opImm6_SxCE;
UXFORMZX_ZX: opImm=opImm6_ZxCE;
UXFORMZX_NX: opImm=opImm6_NxCE;
default: begin end
endcase
end else if(isOp8E)
begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM;
case(tOpDecXfrmZx)
UXFORMZX_SX: opImm=opImm_Sx8E;
UXFORMZX_ZX: opImm=opImm_Zx8E;
UXFORMZX_NX: opImm=opImm_Nx8E;
default: begin end
endcase
end else begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=opRegM_Dfl;
end
end
UXFORM_CMP_ST: begin
if(isOp8E)
begin
opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM;
opImm=opImmM_Sx12_8E;
end else begin
opRegS=opRegN_Dfl; opRegT=opRegM_Dfl;
end
end
UXFORM_ARI_ST: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
UXFORM_ARI_NNI: begin
if(isOpXE)
begin
opRegN={2'h0, isOpCE, opCmdWord[11:8]};
opRegS=opRegN;
opRegT=UREG_MR_IMM; opImm=opImm_Sx16_8E;
end else begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Sx8;
end
end
UXFORM_BR_D8: begin
opImm = isOpXE ? opImm_Sx16_8E : opImm_Sx8;
end
UXFORM_BR_D12: begin
opImm = isOpXE ? opImm_Sx20_8E : opImm_Sx12;
end
UXFORM_ARI_I8R0: begin
if(isOpXE)
begin
opRegN=opRegM_Dfl; opRegS=opRegN;
opRegT=UREG_MR_IMM; opImm=opImmO_Sx12_8E;
end else begin
opRegN=UREG_R0; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
end
UXFORM_N_C: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM;
end
UXFORM_MOV_GD8R0: begin
case(tOpDecXfrmZx)
UXFORMZX_RM: begin
opRegN=UREG_GBR; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
UXFORMZX_MR: begin
opRegN=UREG_R0; opRegS=UREG_GBR;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_MOV_SP4RN: begin
case(tOpDecXfrmZx)
UXFORMZX_RM: begin
opRegN=UREG_R15; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_MR: begin
opRegN=opRegM_Dfl; opRegS=UREG_R15;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
// /*
UXFORMZX_RM3: begin
opRegN=UREG_R15; opRegS=opRegN_N3;
opRegT=UREG_MR_IMM;
opImm[3:0]=opCmdWord[3:0];
opImm[31:4]=1;
end
UXFORMZX_MR3: begin
opRegN=opRegN_N3; opRegS=UREG_R15;
opRegT=UREG_MR_IMM;
opImm[3:0]=opCmdWord[3:0];
opImm[31:4]=1;
end
UXFORMZX_FM3: begin
opRegN=UREG_R15;
opRegS={3'h4, 1'b1, opCmdWord[6:4]};
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_MF3: begin
opRegN={3'h4, 1'b1, opCmdWord[6:4]};
opRegS=UREG_R15;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
// */
UXFORMZX_RM0: begin
opRegN=opRegM_Dfl; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_MR0: begin
opRegN=UREG_R0; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_NST_8E: begin
// opRegN=opRegN_Dfl;
// opRegS=opRegS_8E;
// opRegT=opRegT_8E;
// /*
case(tOpDecXfrmZx)
UXFORMZX_RR: begin
opRegN=opRegN_Dfl;
opRegS=opRegS_8E;
opRegT=opRegT_8E;
end
UXFORMZX_FF: begin
opRegN=opRegN_FR;
opRegS=opRegS_FR;
opRegT=opRegT_FR;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
// */
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
// if(opIsRegN_FR)
// opRegN[6:5]=2'b10;
// if(opIsRegM_FR || opIsRegS_FR)
// opRegS[6:5]=2'b10;
// if(opIsRegT_FR)
// opRegT[6:5]=2'b10;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n", $time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1
bufa3 (drv_3, drv_a[3], drv_e[3]),
bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_8_V
`define SKY130_FD_SC_MS__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_8_V
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_phy_io.v
// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates calibration logic, data, data strobe and the
// data mask iobs.
//Reference:
//Revision History:
// Rev 1.1 - DM_IOB instance made based on USE_DM_PORT value . PK. 25/6/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_io #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter CLK_WIDTH = 1,
parameter USE_DM_PORT = 1,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_BITS = 4,
parameter DQS_WIDTH = 9,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter ODT_WIDTH = 1,
parameter ADDITIVE_LAT = 0,
parameter CAS_LAT = 5,
parameter REG_ENABLE = 1,
parameter CLK_PERIOD = 3000,
parameter DDR_TYPE = 1,
parameter SIM_ONLY = 0,
parameter DEBUG_EN = 0,
parameter FPGA_SPEED_GRADE = 2
)
(
input clk0,
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input dm_ce,
input [1:0] dq_oe_n,
input dqs_oe_n,
input dqs_rst_n,
input [3:0] calib_start,
input ctrl_rden,
input phy_init_rden,
input calib_ref_done,
output [3:0] calib_done,
output calib_ref_req,
output [DQS_WIDTH-1:0] calib_rden,
output [DQS_WIDTH-1:0] calib_rden_sel,
input [DQ_WIDTH-1:0] wr_data_rise,
input [DQ_WIDTH-1:0] wr_data_fall,
input [(DQ_WIDTH/8)-1:0] mask_data_rise,
input [(DQ_WIDTH/8)-1:0] mask_data_fall,
output [(DQ_WIDTH)-1:0] rd_data_rise,
output [(DQ_WIDTH)-1:0] rd_data_fall,
output [CLK_WIDTH-1:0] ddr_ck,
output [CLK_WIDTH-1:0] ddr_ck_n,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
);
// ratio of # of physical DM outputs to bytes in data bus
// may be different - e.g. if using x4 components
localparam DM_TO_BYTE_RATIO = DM_WIDTH / (DQ_WIDTH/8);
wire [CLK_WIDTH-1:0] ddr_ck_q;
wire [DQS_WIDTH-1:0] delayed_dqs;
wire [DQ_WIDTH-1:0] dlyce_dq;
wire [DQS_WIDTH-1:0] dlyce_dqs;
wire [DQS_WIDTH-1:0] dlyce_gate;
wire [DQ_WIDTH-1:0] dlyinc_dq;
wire [DQS_WIDTH-1:0] dlyinc_dqs;
wire [DQS_WIDTH-1:0] dlyinc_gate;
wire dlyrst_dq;
wire dlyrst_dqs;
wire [DQS_WIDTH-1:0] dlyrst_gate;
wire [DQS_WIDTH-1:0] dq_ce;
(* KEEP = "TRUE" *) wire [DQS_WIDTH-1:0] en_dqs /* synthesis syn_keep = 1 */;
wire [DQS_WIDTH-1:0] rd_data_sel;
//***************************************************************************
ddr2_phy_calib #
(
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.CAS_LAT (CAS_LAT),
.REG_ENABLE (REG_ENABLE),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN)
)
u_phy_calib
(
.clk (clk0),
.clkdiv (clkdiv0),
.rstdiv (rstdiv0),
.calib_start (calib_start),
.ctrl_rden (ctrl_rden),
.phy_init_rden (phy_init_rden),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.calib_ref_done (calib_ref_done),
.calib_done (calib_done),
.calib_ref_req (calib_ref_req),
.calib_rden (calib_rden),
.calib_rden_sel (calib_rden_sel),
.dlyrst_dq (dlyrst_dq),
.dlyce_dq (dlyce_dq),
.dlyinc_dq (dlyinc_dq),
.dlyrst_dqs (dlyrst_dqs),
.dlyce_dqs (dlyce_dqs),
.dlyinc_dqs (dlyinc_dqs),
.dlyrst_gate (dlyrst_gate),
.dlyce_gate (dlyce_gate),
.dlyinc_gate (dlyinc_gate),
.en_dqs (en_dqs),
.rd_data_sel (rd_data_sel),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
);
//***************************************************************************
// Memory clock generation
//***************************************************************************
genvar ck_i;
generate
for(ck_i = 0; ck_i < CLK_WIDTH; ck_i = ck_i+1) begin: gen_ck
ODDR #
(
.SRTYPE ("SYNC"),
.DDR_CLK_EDGE ("OPPOSITE_EDGE")
)
u_oddr_ck_i
(
.Q (ddr_ck_q[ck_i]),
.C (clk0),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (1'b0),
.S (1'b0)
);
// Can insert ODELAY here if required
OBUFDS u_obuf_ck_i
(
.I (ddr_ck_q[ck_i]),
.O (ddr_ck[ck_i]),
.OB (ddr_ck_n[ck_i])
);
end
endgenerate
//***************************************************************************
// DQS instances
//***************************************************************************
genvar dqs_i;
generate
for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
ddr2_phy_dqs_iob #
(
.DDR_TYPE (DDR_TYPE),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP)
)
u_iob_dqs
(
.clk0 (clk0),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.dlyinc_dqs (dlyinc_dqs[dqs_i]),
.dlyce_dqs (dlyce_dqs[dqs_i]),
.dlyrst_dqs (dlyrst_dqs),
.dlyinc_gate (dlyinc_gate[dqs_i]),
.dlyce_gate (dlyce_gate[dqs_i]),
.dlyrst_gate (dlyrst_gate[dqs_i]),
.dqs_oe_n (dqs_oe_n),
.dqs_rst_n (dqs_rst_n),
.en_dqs (en_dqs[dqs_i]),
.ddr_dqs (ddr_dqs[dqs_i]),
.ddr_dqs_n (ddr_dqs_n[dqs_i]),
.dq_ce (dq_ce[dqs_i]),
.delayed_dqs (delayed_dqs[dqs_i])
);
end
endgenerate
//***************************************************************************
// DM instances
//***************************************************************************
genvar dm_i;
generate
if (USE_DM_PORT) begin: gen_dm_inst
for(dm_i = 0; dm_i < DM_WIDTH; dm_i = dm_i+1) begin: gen_dm
ddr2_phy_dm_iob u_iob_dm
(
.clk90 (clk90),
.dm_ce (dm_ce),
.mask_data_rise (mask_data_rise[dm_i/DM_TO_BYTE_RATIO]),
.mask_data_fall (mask_data_fall[dm_i/DM_TO_BYTE_RATIO]),
.ddr_dm (ddr_dm[dm_i])
);
end
end
endgenerate
//***************************************************************************
// DQ IOB instances
//***************************************************************************
genvar dq_i;
generate
for(dq_i = 0; dq_i < DQ_WIDTH; dq_i = dq_i+1) begin: gen_dq
ddr2_phy_dq_iob #
(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_iob_dq
(
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst90 (rst90),
.dlyinc (dlyinc_dq[dq_i]),
.dlyce (dlyce_dq[dq_i]),
.dlyrst (dlyrst_dq),
.dq_oe_n (dq_oe_n),
.dqs (delayed_dqs[dq_i/DQ_PER_DQS]),
.ce (dq_ce[dq_i/DQ_PER_DQS]),
.rd_data_sel (rd_data_sel[dq_i/DQ_PER_DQS]),
.wr_data_rise (wr_data_rise[dq_i]),
.wr_data_fall (wr_data_fall[dq_i]),
.rd_data_rise (rd_data_rise[dq_i]),
.rd_data_fall (rd_data_fall[dq_i]),
.ddr_dq (ddr_dq[dq_i])
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__OR3_FUNCTIONAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_FUNCTIONAL_PP_V |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the rx_engine and buffers the output
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAIN_FIFO_DEPTH = 1024,
parameter C_SG_FIFO_DEPTH = 512,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
input SG_DATA_REN, // Scatter gather TX buffer data read enable
input SG_RST, // Scatter gather TX buffer data reset
output SG_ERR, // Scatter gather TX encountered an error
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
input TXN_DONE_ACK, // Read transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN // Channel read data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wPackedMainData;
wire wPackedMainWen;
wire wPackedMainDone;
wire wPackedMainErr;
wire wMainFlush;
wire wMainFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
wire wPackedSgRxWen;
wire wPackedSgRxDone;
wire wPackedSgRxErr;
wire wSgRxFlush;
wire wSgRxFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
wire wPackedSgTxWen;
wire wPackedSgTxDone;
wire wPackedSgTxErr;
wire wSgTxFlush;
wire wSgTxFlushed;
wire wMainDataRen;
wire wMainDataEmpty;
wire [C_DATA_WIDTH-1:0] wMainData;
wire wSgRxRst;
wire wSgRxDataRen;
wire wSgRxDataEmpty;
wire [C_DATA_WIDTH-1:0] wSgRxData;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
wire wSgTxRst;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
wire wSgRxReq;
wire [63:0] wSgRxReqAddr;
wire [9:0] wSgRxReqLen;
wire wSgTxReq;
wire [63:0] wSgTxReqAddr;
wire [9:0] wSgTxReqLen;
wire wSgRxReqProc;
wire wSgTxReqProc;
wire wMainReqProc;
wire wReqAck;
wire wSgElemRdy;
wire wSgElemRen;
wire [63:0] wSgElemAddr;
wire [31:0] wSgElemLen;
wire wSgRst;
wire wMainReq;
wire [63:0] wMainReqAddr;
wire [9:0] wMainReqLen;
wire wTxnErr;
wire wChnlRx;
wire wChnlRxRecvd;
wire wChnlRxAckRecvd;
wire wChnlRxLast;
wire [31:0] wChnlRxLen;
wire [30:0] wChnlRxOff;
wire [31:0] wChnlRxConsumed;
reg [4:0] rWideRst=0;
reg rRst=0;
assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Pack received data tightly into our FIFOs
fifo_packer_32 mainFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(MAIN_DATA),
.DATA_IN_EN(MAIN_DATA_EN),
.DATA_IN_DONE(MAIN_DONE),
.DATA_IN_ERR(MAIN_ERR),
.DATA_IN_FLUSH(wMainFlush),
.PACKED_DATA(wPackedMainData),
.PACKED_WEN(wPackedMainWen),
.PACKED_DATA_DONE(wPackedMainDone),
.PACKED_DATA_ERR(wPackedMainErr),
.PACKED_DATA_FLUSHED(wMainFlushed)
);
fifo_packer_32 sgRxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_RX_DATA),
.DATA_IN_EN(SG_RX_DATA_EN),
.DATA_IN_DONE(SG_RX_DONE),
.DATA_IN_ERR(SG_RX_ERR),
.DATA_IN_FLUSH(wSgRxFlush),
.PACKED_DATA(wPackedSgRxData),
.PACKED_WEN(wPackedSgRxWen),
.PACKED_DATA_DONE(wPackedSgRxDone),
.PACKED_DATA_ERR(wPackedSgRxErr),
.PACKED_DATA_FLUSHED(wSgRxFlushed)
);
fifo_packer_32 sgTxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_TX_DATA),
.DATA_IN_EN(SG_TX_DATA_EN),
.DATA_IN_DONE(SG_TX_DONE),
.DATA_IN_ERR(SG_TX_ERR),
.DATA_IN_FLUSH(wSgTxFlush),
.PACKED_DATA(wPackedSgTxData),
.PACKED_WEN(wPackedSgTxWen),
.PACKED_DATA_DONE(wPackedSgTxDone),
.PACKED_DATA_ERR(wPackedSgTxErr),
.PACKED_DATA_FLUSHED(wSgTxFlushed)
);
// FIFOs for storing received data for the channel.
(* RAM_STYLE="BLOCK" *)
async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
.WR_CLK(CLK),
.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.WR_EN(wPackedMainWen),
.WR_DATA(wPackedMainData),
.WR_FULL(),
.RD_CLK(CHNL_CLK),
.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.RD_EN(wMainDataRen),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
.RST(rRst | wSgRxRst),
.CLK(CLK),
.WR_EN(wPackedSgRxWen),
.WR_DATA(wPackedSgRxData),
.FULL(),
.RD_EN(wSgRxDataRen),
.RD_DATA(wSgRxData),
.EMPTY(wSgRxDataEmpty),
.COUNT(wSgRxFifoCount)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
.RST(rRst | wSgTxRst),
.CLK(CLK),
.WR_EN(wPackedSgTxWen),
.WR_DATA(wPackedSgTxData),
.FULL(),
.RD_EN(SG_DATA_REN),
.RD_DATA(SG_DATA),
.EMPTY(SG_DATA_EMPTY),
.COUNT(wSgTxFifoCount)
);
// Manage requesting and acknowledging scatter gather data. Note that
// these modules will share the main requestor's RX channel. They will
// take priority over the main logic's use of the RX channel.
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(wSgRst),
.BUF_RECVD(SG_RX_BUF_RECVD),
.BUF_DATA(SG_RX_BUF_DATA),
.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgRxFifoCount),
.FIFO_FLUSH(wSgRxFlush),
.FIFO_FLUSHED(wSgRxFlushed),
.FIFO_RST(wSgRxRst),
.RX_REQ(wSgRxReq),
.RX_ADDR(wSgRxReqAddr),
.RX_LEN(wSgRxReqLen),
.RX_REQ_ACK(wReqAck & wSgRxReqProc),
.RX_DONE(wPackedSgRxDone)
);
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(SG_RST),
.BUF_RECVD(SG_TX_BUF_RECVD),
.BUF_DATA(SG_TX_BUF_DATA),
.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgTxFifoCount),
.FIFO_FLUSH(wSgTxFlush),
.FIFO_FLUSHED(wSgTxFlushed),
.FIFO_RST(wSgTxRst),
.RX_REQ(wSgTxReq),
.RX_ADDR(wSgTxReqAddr),
.RX_LEN(wSgTxReqLen),
.RX_REQ_ACK(wReqAck & wSgTxReqProc),
.RX_DONE(wPackedSgTxDone)
);
// A read requester for the channel and scatter gather requesters.
rx_port_requester_mux requesterMux (
.RST(rRst),
.CLK(CLK),
.SG_RX_REQ(wSgRxReq),
.SG_RX_LEN(wSgRxReqLen),
.SG_RX_ADDR(wSgRxReqAddr),
.SG_RX_REQ_PROC(wSgRxReqProc),
.SG_TX_REQ(wSgTxReq),
.SG_TX_LEN(wSgTxReqLen),
.SG_TX_ADDR(wSgTxReqAddr),
.SG_TX_REQ_PROC(wSgTxReqProc),
.MAIN_REQ(wMainReq),
.MAIN_LEN(wMainReqLen),
.MAIN_ADDR(wMainReqAddr),
.MAIN_REQ_PROC(wMainReqProc),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.REQ_ACK(wReqAck)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | wSgRst),
.BUF_DATA(wSgRxData),
.BUF_DATA_EMPTY(wSgRxDataEmpty),
.BUF_DATA_REN(wSgRxDataRen),
.VALID(wSgElemRdy),
.EMPTY(),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Main port reader logic
rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.TXN_DATA(TXN_DATA),
.TXN_LEN_VALID(TXN_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.TXN_DATA_FLUSH(wMainFlush),
.TXN_DATA_FLUSHED(wMainFlushed),
.RX_REQ(wMainReq),
.RX_ADDR(wMainReqAddr),
.RX_LEN(wMainReqLen),
.RX_REQ_ACK(wReqAck & wMainReqProc),
.RX_DATA_EN(MAIN_DATA_EN),
.RX_DONE(wPackedMainDone),
.RX_ERR(wPackedMainErr),
.SG_DONE(wPackedSgRxDone),
.SG_ERR(wPackedSgRxErr),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(wSgRst),
.CHNL_RX(wChnlRx),
.CHNL_RX_LEN(wChnlRxLen),
.CHNL_RX_LAST(wChnlRxLast),
.CHNL_RX_OFF(wChnlRxOff),
.CHNL_RX_RECVD(wChnlRxRecvd),
.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
.CHNL_RX_CONSUMED(wChnlRxConsumed)
);
// Manage the CHNL_RX* signals in the CHNL_CLK domain.
rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.CLK(CLK),
.RX(wChnlRx),
.RX_RECVD(wChnlRxRecvd),
.RX_ACK_RECVD(wChnlRxAckRecvd),
.RX_LAST(wChnlRxLast),
.RX_LEN(wChnlRxLen),
.RX_OFF(wChnlRxOff),
.RX_CONSUMED(wChnlRxConsumed),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty),
.RD_EN(wMainDataRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({SG_RX_DATA_EN != 0, wSgElemRen, wMainReq | wSgRxReq | wSgTxReq,
RX_REQ, SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID,
wSgRst, wTxnErr | wPackedSgRxDone | wSgRxFlush | wSgRxFlushed, TXN_OFF_LAST_VALID | TXN_LEN_VALID}),
.DATA({
wPackedSgRxErr, // 1
wPackedSgRxDone, // 1
wPackedSgRxWen, // 1
wPackedSgRxData, // 64
SG_RX_ERR, // 1
SG_RX_DONE, // 1
SG_RX_DATA_EN, // 2
SG_RX_DATA, // 64
wSgRxDataRen, // 1
wSgRxDataEmpty, // 1
wSgRxData, // 64
wSgRst, // 1
SG_RST, // 1
wPackedSgRxDone, // 1
wSgRxRst, // 1
wSgRxFlushed, // 1
wSgRxFlush, // 1
SG_RX_BUF_ADDR_LO_VALID, // 1
SG_RX_BUF_ADDR_HI_VALID, // 1
SG_RX_BUF_LEN_VALID, // 1
SG_RX_BUF_DATA, // 32
RX_REQ_ADDR, // 64
RX_REQ_TAG, // 2
RX_REQ_ACK, // 1
RX_REQ, // 1
wSgTxReqProc, // 1
wSgTxReqAddr, // 64
wSgTxReq, // 1
wSgRxReqProc, // 1
wSgRxReqAddr, // 64
wSgRxReq, // 1
wMainReqProc, // 1
wMainReqAddr, // 64
wMainReq, // 1
wReqAck, // 1
wTxnErr, // 1
TXN_OFF_LAST_VALID, // 1
TXN_LEN_VALID}) // 1
);
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_SYMBOL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_SYMBOL_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1420582344 : 2899645186;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pcie_brams_7x.v
// Version : 3.2
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
//
// banks of brams are used for 1,2,4,8,18 brams
// brams are stacked for other values of NUM_BRAMS
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pcie_brams_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1,
parameter TCQ = 1 // synthesis warning removed: parameter declaration becomes local
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
// parameter TCQ = 1;
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
//synthesis translate_off
initial
begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_q;
reg [12:0] waddr_q;
reg [71:0] wdata_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
wen_q <= #TCQ 1'b0;
waddr_q <= #TCQ 13'b0;
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
// wdata_q <= #TCQ 72'b0;
end
else
begin
wen_q <= #TCQ wen;
waddr_q <= #TCQ waddr;
wdata_q <= #TCQ wdata;
end
end
assign wen_int = wen_q;
assign waddr_int = waddr_q;
assign wdata_int = wdata_q;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_q;
reg [12:0] raddr_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
ren_q <= #TCQ 1'b0;
raddr_q <= #TCQ 13'b0;
end
else
begin
ren_q <= #TCQ ren;
raddr_q <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_q;
assign raddr_int = raddr_q;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_q;
always @(posedge user_clk_i) begin
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
//if (reset_i)
//begin
// rdata_q <= #TCQ 72'b0;
//end
//else
//begin
rdata_q <= #TCQ rdata_int;
//end // else: !if(reset_i)
end
assign rdata = rdata_q;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar ii;
for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
PCIeGen2x8If128_pcie_bram_7x #(
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.IMPL_TARGET (IMPL_TARGET),
.DOB_REG (DOB_REG),
.WIDTH (WIDTH)
)
ram (
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.wen_i(wen_int),
.waddr_i(waddr_int),
.wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.ren_i(ren_int),
.raddr_i(raddr_int),
.rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.rce_i(rce)
);
end
endgenerate
endmodule // pcie_brams_7x
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(1'b1));
endmodule
// Async reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(1'b1));
endmodule
// Async reset
module \$_DFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(1'b1));
endmodule
// Async set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(!R));
endmodule
// Async set
module \$_DFF_PN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(R));
endmodule
module \$_DFFE_PP_ (D, C, E, Q);
input D;
input C;
input E;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(1'b1));
endmodule
module \$_DFFE_PN_ (D, C, E, Q);
input D;
input C;
input E;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(1'b1));
endmodule
// Async reset, enable
module \$_DFFE_PP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(1'b1));
endmodule
module \$_DFFE_PP0N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(1'b1));
endmodule
module \$_DFFE_PN0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
endmodule
module \$_DFFE_PN0N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(1'b1));
endmodule
// Async set, enable
module \$_DFFE_PP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(!R));
endmodule
module \$_DFFE_PP1N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(!R));
endmodule
module \$_DFFE_PN1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
endmodule
module \$_DFFE_PN1N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(R));
endmodule
// Async set & reset
module \$_DFFSR_PPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(!S));
endmodule
module \$_DFFSR_PNP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(S));
endmodule
module \$_DFFSR_PNN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(S));
endmodule
module \$_DFFSR_PPN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(!S));
endmodule
module \$_DFFSR_NPP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(!S));
endmodule
module \$_DFFSR_NNP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(S));
endmodule
module \$_DFFSR_NNN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(S));
endmodule
module \$_DFFSR_NPN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(!S));
endmodule
// Async set, reset & enable
module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(!S));
endmodule
module \$_DFFSRE_PNPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(S));
endmodule
module \$_DFFSRE_PPNP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(!S));
endmodule
module \$_DFFSRE_PNNP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
module \$_DFFSRE_PPPN_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(!S));
endmodule
module \$_DFFSRE_PNPN_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(S));
endmodule
module \$_DFFSRE_PPNN_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(!S));
endmodule
module \$_DFFSRE_PNNN_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(S));
endmodule
// Latch with async set and reset
module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
endmodule
module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q);
latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(1'b1));
endmodule
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(1'b1));
endmodule
module \$_DFF_NN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(R), .S(1'b1));
endmodule
module \$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(!R));
endmodule
module \$_DFF_NN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(R));
endmodule
module \$_DFFE_NP_ (D, C, E, Q);
input D;
input C;
input E;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(1'b1));
endmodule
module \$_DFFE_NN_ (D, C, E, Q);
input D;
input C;
input E;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(1'b1));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(1'b1));
endmodule
module \$_DFFE_NP0N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(1'b1));
endmodule
module \$_DFFE_NN0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
endmodule
module \$_DFFE_NN0N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(1'b1));
endmodule
module \$_DFFE_NP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(!R));
endmodule
module \$_DFFE_NP1N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(!R));
endmodule
module \$_DFFE_NN1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
endmodule
module \$_DFFE_NN1N_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(1'b1), .S(R));
endmodule
module \$_DFFSRE_NPPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(!S));
endmodule
module \$_DFFSRE_NNPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(S));
endmodule
module \$_DFFSRE_NPNP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(!S));
endmodule
module \$_DFFSRE_NNNP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
module \$_DFFSRE_NPPN_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(!S));
endmodule
module \$_DFFSRE_NNPN_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(!R), .S(S));
endmodule
module \$_DFFSRE_NPNN_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(!S));
endmodule
module \$_DFFSRE_NNNN_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(!E), .R(R), .S(S));
endmodule
module \$__SHREG_DFF_P_ (D, Q, C);
input D;
input C;
output Q;
parameter DEPTH = 2;
reg [DEPTH-2:0] q;
genvar i;
generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
// First in chain
generate if (i == 0) begin
sh_dff #() shreg_beg (
.Q(q[i]),
.D(D),
.C(C)
);
end endgenerate
// Middle in chain
generate if (i > 0 && i != DEPTH-1) begin
sh_dff #() shreg_mid (
.Q(q[i]),
.D(q[i-1]),
.C(C)
);
end endgenerate
// Last in chain
generate if (i == DEPTH-1) begin
sh_dff #() shreg_end (
.Q(Q),
.D(q[i-1]),
.C(C)
);
end endgenerate
end: slice
endgenerate
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always force reg_lvalue = constant ;
// D: No dependancy
module main ;
wire [3:0] value1 ;
initial
begin
#15;
if(value1 != 4'h5)
$display("FAILED - 3.1.3F always force net_lvalue = constant;\n");
else
begin
$display("PASSED\n");
$finish;
end
end
always force value1 = 4'h5;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_FUNCTIONAL_V |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Sun Mar 13 09:23:31 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/mult_gen_1/mult_gen_1_stub.v
// Design : mult_gen_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0,Vivado 2015.1" *)
module mult_gen_1(A, B, P)
/* synthesis syn_black_box black_box_pad_pin="A[11:0],B[13:0],P[32:0]" */;
input [11:0]A;
input [13:0]B;
output [32:0]P;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA
// Example to test prefix for VTypeArray (and using function as index).
module test_prefix_aray();
logic [1:0] sel_word;
logic [31:0] out_word;
prefix_array dut(sel_word, out_word);
initial begin
sel_word = 2;
#1;
if(out_word !== 32'd5) begin
$display("FAILED out_word = %d", out_word);
$finish();
end
$display("PASSED");
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Encoder Core - Verilog ////
//// ////
//// Author: David Lundgren ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
/* This module is the Huffman encoder. It takes in the quantized outputs
from the quantizer, and creates the Huffman codes from these value. The
output from this module is the jpeg code of the actual pixel data. The jpeg
file headers will need to be generated separately. The Huffman codes are constant,
and they can be changed by changing the parameters in this module. */
`timescale 1ns / 100ps
module y_huff(clk, rst, enable,
Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24, Y25, Y26, Y27, Y28,
Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38, Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48,
Y51, Y52, Y53, Y54, Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68,
Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84, Y85, Y86, Y87, Y88,
JPEG_bitstream, data_ready, output_reg_count, end_of_block_output,
end_of_block_empty);
input clk;
input rst;
input enable;
input [10:0] Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24;
input [10:0] Y25, Y26, Y27, Y28, Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38;
input [10:0] Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48, Y51, Y52, Y53, Y54;
input [10:0] Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68;
input [10:0] Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84;
input [10:0] Y85, Y86, Y87, Y88;
output [31:0] JPEG_bitstream;
output data_ready;
output [4:0] output_reg_count;
output end_of_block_output;
output end_of_block_empty;
reg [7:0] block_counter;
reg [11:0] Y11_amp, Y11_1_pos, Y11_1_neg, Y11_diff;
reg [11:0] Y11_previous, Y11_1;
reg [10:0] Y12_amp, Y12_pos, Y12_neg;
reg [10:0] Y21_pos, Y21_neg, Y31_pos, Y31_neg, Y22_pos, Y22_neg;
reg [10:0] Y13_pos, Y13_neg, Y14_pos, Y14_neg, Y15_pos, Y15_neg;
reg [10:0] Y16_pos, Y16_neg, Y17_pos, Y17_neg, Y18_pos, Y18_neg;
reg [10:0] Y23_pos, Y23_neg, Y24_pos, Y24_neg, Y25_pos, Y25_neg;
reg [10:0] Y26_pos, Y26_neg, Y27_pos, Y27_neg, Y28_pos, Y28_neg;
reg [10:0] Y32_pos, Y32_neg;
reg [10:0] Y33_pos, Y33_neg, Y34_pos, Y34_neg, Y35_pos, Y35_neg;
reg [10:0] Y36_pos, Y36_neg, Y37_pos, Y37_neg, Y38_pos, Y38_neg;
reg [10:0] Y41_pos, Y41_neg, Y42_pos, Y42_neg;
reg [10:0] Y43_pos, Y43_neg, Y44_pos, Y44_neg, Y45_pos, Y45_neg;
reg [10:0] Y46_pos, Y46_neg, Y47_pos, Y47_neg, Y48_pos, Y48_neg;
reg [10:0] Y51_pos, Y51_neg, Y52_pos, Y52_neg;
reg [10:0] Y53_pos, Y53_neg, Y54_pos, Y54_neg, Y55_pos, Y55_neg;
reg [10:0] Y56_pos, Y56_neg, Y57_pos, Y57_neg, Y58_pos, Y58_neg;
reg [10:0] Y61_pos, Y61_neg, Y62_pos, Y62_neg;
reg [10:0] Y63_pos, Y63_neg, Y64_pos, Y64_neg, Y65_pos, Y65_neg;
reg [10:0] Y66_pos, Y66_neg, Y67_pos, Y67_neg, Y68_pos, Y68_neg;
reg [10:0] Y71_pos, Y71_neg, Y72_pos, Y72_neg;
reg [10:0] Y73_pos, Y73_neg, Y74_pos, Y74_neg, Y75_pos, Y75_neg;
reg [10:0] Y76_pos, Y76_neg, Y77_pos, Y77_neg, Y78_pos, Y78_neg;
reg [10:0] Y81_pos, Y81_neg, Y82_pos, Y82_neg;
reg [10:0] Y83_pos, Y83_neg, Y84_pos, Y84_neg, Y85_pos, Y85_neg;
reg [10:0] Y86_pos, Y86_neg, Y87_pos, Y87_neg, Y88_pos, Y88_neg;
reg [3:0] Y11_bits_pos, Y11_bits_neg, Y11_bits, Y11_bits_1;
reg [3:0] Y12_bits_pos, Y12_bits_neg, Y12_bits, Y12_bits_1;
reg [3:0] Y12_bits_2, Y12_bits_3;
reg Y11_msb, Y12_msb, Y12_msb_1, data_ready;
reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12;
reg enable_13, enable_module, enable_latch_7, enable_latch_8;
reg Y12_et_zero, rollover, rollover_1, rollover_2, rollover_3;
reg rollover_4, rollover_5, rollover_6, rollover_7;
reg Y21_et_zero, Y21_msb, Y31_et_zero, Y31_msb;
reg Y22_et_zero, Y22_msb, Y13_et_zero, Y13_msb;
reg Y14_et_zero, Y14_msb, Y15_et_zero, Y15_msb;
reg Y16_et_zero, Y16_msb, Y17_et_zero, Y17_msb;
reg Y18_et_zero, Y18_msb;
reg Y23_et_zero, Y23_msb, Y24_et_zero, Y24_msb;
reg Y25_et_zero, Y25_msb, Y26_et_zero, Y26_msb;
reg Y27_et_zero, Y27_msb, Y28_et_zero, Y28_msb;
reg Y32_et_zero, Y32_msb, Y33_et_zero, Y33_msb;
reg Y34_et_zero, Y34_msb, Y35_et_zero, Y35_msb;
reg Y36_et_zero, Y36_msb, Y37_et_zero, Y37_msb;
reg Y38_et_zero, Y38_msb;
reg Y41_et_zero, Y41_msb, Y42_et_zero, Y42_msb;
reg Y43_et_zero, Y43_msb, Y44_et_zero, Y44_msb;
reg Y45_et_zero, Y45_msb, Y46_et_zero, Y46_msb;
reg Y47_et_zero, Y47_msb, Y48_et_zero, Y48_msb;
reg Y51_et_zero, Y51_msb, Y52_et_zero, Y52_msb;
reg Y53_et_zero, Y53_msb, Y54_et_zero, Y54_msb;
reg Y55_et_zero, Y55_msb, Y56_et_zero, Y56_msb;
reg Y57_et_zero, Y57_msb, Y58_et_zero, Y58_msb;
reg Y61_et_zero, Y61_msb, Y62_et_zero, Y62_msb;
reg Y63_et_zero, Y63_msb, Y64_et_zero, Y64_msb;
reg Y65_et_zero, Y65_msb, Y66_et_zero, Y66_msb;
reg Y67_et_zero, Y67_msb, Y68_et_zero, Y68_msb;
reg Y71_et_zero, Y71_msb, Y72_et_zero, Y72_msb;
reg Y73_et_zero, Y73_msb, Y74_et_zero, Y74_msb;
reg Y75_et_zero, Y75_msb, Y76_et_zero, Y76_msb;
reg Y77_et_zero, Y77_msb, Y78_et_zero, Y78_msb;
reg Y81_et_zero, Y81_msb, Y82_et_zero, Y82_msb;
reg Y83_et_zero, Y83_msb, Y84_et_zero, Y84_msb;
reg Y85_et_zero, Y85_msb, Y86_et_zero, Y86_msb;
reg Y87_et_zero, Y87_msb, Y88_et_zero, Y88_msb;
reg Y12_et_zero_1, Y12_et_zero_2, Y12_et_zero_3, Y12_et_zero_4, Y12_et_zero_5;
reg [10:0] Y_DC [11:0];
reg [3:0] Y_DC_code_length [11:0];
reg [15:0] Y_AC [161:0];
reg [4:0] Y_AC_code_length [161:0];
reg [7:0] Y_AC_run_code [250:0];
reg [10:0] Y11_Huff, Y11_Huff_1, Y11_Huff_2;
reg [15:0] Y12_Huff, Y12_Huff_1, Y12_Huff_2;
reg [3:0] Y11_Huff_count, Y11_Huff_shift, Y11_Huff_shift_1, Y11_amp_shift, Y12_amp_shift;
reg [3:0] Y12_Huff_shift, Y12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3;
reg [4:0] Y12_Huff_count, Y12_Huff_count_1;
reg [4:0] output_reg_count, Y11_output_count, old_orc_1, old_orc_2;
reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Y12_oc_1;
reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8;
reg [4:0] Y12_output_count;
reg [4:0] Y12_edge, Y12_edge_1, Y12_edge_2, Y12_edge_3, Y12_edge_4;
reg [31:0] JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5;
reg [31:0] JPEG_Y12_bs, JPEG_Y12_bs_1, JPEG_Y12_bs_2, JPEG_Y12_bs_3, JPEG_Y12_bs_4;
reg [31:0] JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4;
reg [21:0] Y11_JPEG_LSBs_3;
reg [10:0] Y11_JPEG_LSBs, Y11_JPEG_LSBs_1, Y11_JPEG_LSBs_2;
reg [9:0] Y12_JPEG_LSBs, Y12_JPEG_LSBs_1, Y12_JPEG_LSBs_2, Y12_JPEG_LSBs_3;
reg [25:0] Y11_JPEG_bits, Y11_JPEG_bits_1, Y12_JPEG_bits, Y12_JPEG_LSBs_4;
reg [7:0] Y12_code_entry;
reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s;
reg eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output;
reg end_of_block_empty;
wire [7:0] code_index = { zrl_2, Y12_bits };
always @(posedge clk)
begin
if (rst) begin
third_8_all_0s <= 0; fourth_8_all_0s <= 0;
fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0;
eighth_8_all_0s <= 0;
end
else if (enable_1) begin
third_8_all_0s <= Y25_et_zero & Y34_et_zero & Y43_et_zero & Y52_et_zero
& Y61_et_zero & Y71_et_zero & Y62_et_zero & Y53_et_zero;
fourth_8_all_0s <= Y44_et_zero & Y35_et_zero & Y26_et_zero & Y17_et_zero
& Y18_et_zero & Y27_et_zero & Y36_et_zero & Y45_et_zero;
fifth_8_all_0s <= Y54_et_zero & Y63_et_zero & Y72_et_zero & Y81_et_zero
& Y82_et_zero & Y73_et_zero & Y64_et_zero & Y55_et_zero;
sixth_8_all_0s <= Y46_et_zero & Y37_et_zero & Y28_et_zero & Y38_et_zero
& Y47_et_zero & Y56_et_zero & Y65_et_zero & Y74_et_zero;
seventh_8_all_0s <= Y83_et_zero & Y84_et_zero & Y75_et_zero & Y66_et_zero
& Y57_et_zero & Y48_et_zero & Y58_et_zero & Y67_et_zero;
eighth_8_all_0s <= Y76_et_zero & Y85_et_zero & Y86_et_zero & Y77_et_zero
& Y68_et_zero & Y78_et_zero & Y87_et_zero & Y88_et_zero;
end
end
/* end_of_block checks to see if there are any nonzero elements left in the block
If there aren't any nonzero elements left, then the last bits in the JPEG stream
will be the end of block code. The purpose of this register is to determine if the
zero run length code 15-0 should be used or not. It should be used if there are 15 or more
zeros in a row, followed by a nonzero value. If there are only zeros left in the block,
then end_of_block will be 1. If there are any nonzero values left in the block, end_of_block
will be 0. */
always @(posedge clk)
begin
if (rst)
end_of_block <= 0;
else if (enable)
end_of_block <= 0;
else if (enable_module & block_counter < 32)
end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s
& sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s;
else if (enable_module & block_counter < 48)
end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s
& eighth_8_all_0s;
else if (enable_module & block_counter <= 64)
end_of_block <= seventh_8_all_0s & eighth_8_all_0s;
else if (enable_module & block_counter > 64)
end_of_block <= 1;
end
always @(posedge clk)
begin
if (rst) begin
block_counter <= 0;
end
else if (enable) begin
block_counter <= 0;
end
else if (enable_module) begin
block_counter <= block_counter + 1;
end
end
always @(posedge clk)
begin
if (rst) begin
output_reg_count <= 0;
end
else if (end_of_block_output) begin
output_reg_count <= 0;
end
else if (enable_6) begin
output_reg_count <= output_reg_count + Y11_output_count;
end
else if (enable_latch_7) begin
output_reg_count <= output_reg_count + Y12_oc_1;
end
end
always @(posedge clk)
begin
if (rst) begin
old_orc_1 <= 0;
end
else if (end_of_block_output) begin
old_orc_1 <= 0;
end
else if (enable_module) begin
old_orc_1 <= output_reg_count;
end
end
always @(posedge clk)
begin
if (rst) begin
rollover <= 0; rollover_1 <= 0; rollover_2 <= 0;
rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0;
rollover_6 <= 0; rollover_7 <= 0;
old_orc_2 <= 0;
orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0;
orc_7 <= 0; orc_8 <= 0; data_ready <= 0;
end_of_block_output <= 0; end_of_block_empty <= 0;
end
else if (enable_module) begin
rollover <= (old_orc_1 > output_reg_count);
rollover_1 <= rollover;
rollover_2 <= rollover_1;
rollover_3 <= rollover_2;
rollover_4 <= rollover_3;
rollover_5 <= rollover_4;
rollover_6 <= rollover_5;
rollover_7 <= rollover_6;
old_orc_2 <= old_orc_1;
orc_3 <= old_orc_2;
orc_4 <= orc_3; orc_5 <= orc_4;
orc_6 <= orc_5; orc_7 <= orc_6;
orc_8 <= orc_7;
data_ready <= rollover_6 | block_counter == 77;
end_of_block_output <= block_counter == 77;
end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_5 <= 0;
end
else if (enable_module) begin
JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31];
JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30];
JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29];
JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28];
JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27];
JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26];
JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25];
JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24];
JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23];
JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22];
JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21];
JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20];
JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19];
JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18];
JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17];
JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16];
JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15];
JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14];
JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13];
JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12];
JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11];
JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10];
JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9];
JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8];
JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7];
JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6];
JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5];
JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4];
JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3];
JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2];
JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1];
JPEG_bs_5[0] <= JPEG_bs_4[0];
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0;
end
else if (enable_module) begin
JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3;
JPEG_ro_bs_4 <= (Y12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0;
Y12_edge_4 <= 0;
end
else if (enable_module) begin
JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2;
old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5;
JPEG_ro_bs_3 <= (Y12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2;
Y12_edge_4 <= (Y12_edge_3 <= 2) ? Y12_edge_3 : Y12_edge_3 - 2;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0;
Y12_edge_3 <= 0;
end
else if (enable_module) begin
JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1;
old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4;
JPEG_ro_bs_2 <= (Y12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1;
Y12_edge_3 <= (Y12_edge_2 <= 4) ? Y12_edge_2 : Y12_edge_2 - 4;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0;
Y12_edge_2 <= 0;
end
else if (enable_module) begin
JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs;
old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3;
JPEG_ro_bs_1 <= (Y12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs;
Y12_edge_2 <= (Y12_edge_1 <= 8) ? Y12_edge_1 : Y12_edge_1 - 8;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0;
Y12_edge_1 <= 0; Y11_JPEG_bits_1 <= 0;
end
else if (enable_module) begin
JPEG_bs <= (old_orc_2 >= 16) ? Y11_JPEG_bits >> 10 : Y11_JPEG_bits << 6;
old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2;
JPEG_ro_bs <= (Y12_edge <= 16) ? Y11_JPEG_bits_1 << 16 : Y11_JPEG_bits_1;
Y12_edge_1 <= (Y12_edge <= 16) ? Y12_edge : Y12_edge - 16;
Y11_JPEG_bits_1 <= Y11_JPEG_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_JPEG_bits <= 0; Y12_edge <= 0;
end
else if (enable_module) begin
Y12_JPEG_bits[25] <= (Y12_Huff_shift_1 >= 16) ? Y12_JPEG_LSBs_4[25] : Y12_Huff_2[15];
Y12_JPEG_bits[24] <= (Y12_Huff_shift_1 >= 15) ? Y12_JPEG_LSBs_4[24] : Y12_Huff_2[14];
Y12_JPEG_bits[23] <= (Y12_Huff_shift_1 >= 14) ? Y12_JPEG_LSBs_4[23] : Y12_Huff_2[13];
Y12_JPEG_bits[22] <= (Y12_Huff_shift_1 >= 13) ? Y12_JPEG_LSBs_4[22] : Y12_Huff_2[12];
Y12_JPEG_bits[21] <= (Y12_Huff_shift_1 >= 12) ? Y12_JPEG_LSBs_4[21] : Y12_Huff_2[11];
Y12_JPEG_bits[20] <= (Y12_Huff_shift_1 >= 11) ? Y12_JPEG_LSBs_4[20] : Y12_Huff_2[10];
Y12_JPEG_bits[19] <= (Y12_Huff_shift_1 >= 10) ? Y12_JPEG_LSBs_4[19] : Y12_Huff_2[9];
Y12_JPEG_bits[18] <= (Y12_Huff_shift_1 >= 9) ? Y12_JPEG_LSBs_4[18] : Y12_Huff_2[8];
Y12_JPEG_bits[17] <= (Y12_Huff_shift_1 >= 8) ? Y12_JPEG_LSBs_4[17] : Y12_Huff_2[7];
Y12_JPEG_bits[16] <= (Y12_Huff_shift_1 >= 7) ? Y12_JPEG_LSBs_4[16] : Y12_Huff_2[6];
Y12_JPEG_bits[15] <= (Y12_Huff_shift_1 >= 6) ? Y12_JPEG_LSBs_4[15] : Y12_Huff_2[5];
Y12_JPEG_bits[14] <= (Y12_Huff_shift_1 >= 5) ? Y12_JPEG_LSBs_4[14] : Y12_Huff_2[4];
Y12_JPEG_bits[13] <= (Y12_Huff_shift_1 >= 4) ? Y12_JPEG_LSBs_4[13] : Y12_Huff_2[3];
Y12_JPEG_bits[12] <= (Y12_Huff_shift_1 >= 3) ? Y12_JPEG_LSBs_4[12] : Y12_Huff_2[2];
Y12_JPEG_bits[11] <= (Y12_Huff_shift_1 >= 2) ? Y12_JPEG_LSBs_4[11] : Y12_Huff_2[1];
Y12_JPEG_bits[10] <= (Y12_Huff_shift_1 >= 1) ? Y12_JPEG_LSBs_4[10] : Y12_Huff_2[0];
Y12_JPEG_bits[9:0] <= Y12_JPEG_LSBs_4[9:0];
Y12_edge <= old_orc_2 + 26; // 26 is the size of Y11_JPEG_bits
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_JPEG_bits <= 0;
end
else if (enable_7) begin
Y11_JPEG_bits[25] <= (Y11_Huff_shift_1 >= 11) ? Y11_JPEG_LSBs_3[21] : Y11_Huff_2[10];
Y11_JPEG_bits[24] <= (Y11_Huff_shift_1 >= 10) ? Y11_JPEG_LSBs_3[20] : Y11_Huff_2[9];
Y11_JPEG_bits[23] <= (Y11_Huff_shift_1 >= 9) ? Y11_JPEG_LSBs_3[19] : Y11_Huff_2[8];
Y11_JPEG_bits[22] <= (Y11_Huff_shift_1 >= 8) ? Y11_JPEG_LSBs_3[18] : Y11_Huff_2[7];
Y11_JPEG_bits[21] <= (Y11_Huff_shift_1 >= 7) ? Y11_JPEG_LSBs_3[17] : Y11_Huff_2[6];
Y11_JPEG_bits[20] <= (Y11_Huff_shift_1 >= 6) ? Y11_JPEG_LSBs_3[16] : Y11_Huff_2[5];
Y11_JPEG_bits[19] <= (Y11_Huff_shift_1 >= 5) ? Y11_JPEG_LSBs_3[15] : Y11_Huff_2[4];
Y11_JPEG_bits[18] <= (Y11_Huff_shift_1 >= 4) ? Y11_JPEG_LSBs_3[14] : Y11_Huff_2[3];
Y11_JPEG_bits[17] <= (Y11_Huff_shift_1 >= 3) ? Y11_JPEG_LSBs_3[13] : Y11_Huff_2[2];
Y11_JPEG_bits[16] <= (Y11_Huff_shift_1 >= 2) ? Y11_JPEG_LSBs_3[12] : Y11_Huff_2[1];
Y11_JPEG_bits[15] <= (Y11_Huff_shift_1 >= 1) ? Y11_JPEG_LSBs_3[11] : Y11_Huff_2[0];
Y11_JPEG_bits[14:4] <= Y11_JPEG_LSBs_3[10:0];
end
else if (enable_latch_8) begin
Y11_JPEG_bits <= Y12_JPEG_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_oc_1 <= 0; Y12_JPEG_LSBs_4 <= 0;
Y12_Huff_2 <= 0; Y12_Huff_shift_1 <= 0;
end
else if (enable_module) begin
Y12_oc_1 <= (Y12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 :
Y12_bits_3 + Y12_Huff_count_1;
Y12_JPEG_LSBs_4 <= Y12_JPEG_LSBs_3 << Y12_Huff_shift;
Y12_Huff_2 <= Y12_Huff_1;
Y12_Huff_shift_1 <= Y12_Huff_shift;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_JPEG_LSBs_3 <= 0; Y11_Huff_2 <= 0;
Y11_Huff_shift_1 <= 0;
end
else if (enable_6) begin
Y11_JPEG_LSBs_3 <= Y11_JPEG_LSBs_2 << Y11_Huff_shift;
Y11_Huff_2 <= Y11_Huff_1;
Y11_Huff_shift_1 <= Y11_Huff_shift;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_Huff_shift <= 0;
Y12_Huff_1 <= 0; Y12_JPEG_LSBs_3 <= 0; Y12_bits_3 <= 0;
Y12_Huff_count_1 <= 0; Y12_et_zero_5 <= 0; code_15_0 <= 0;
end
else if (enable_module) begin
Y12_Huff_shift <= 16 - Y12_Huff_count;
Y12_Huff_1 <= Y12_Huff;
Y12_JPEG_LSBs_3 <= Y12_JPEG_LSBs_2;
Y12_bits_3 <= Y12_bits_2;
Y12_Huff_count_1 <= Y12_Huff_count;
Y12_et_zero_5 <= Y12_et_zero_4;
code_15_0 <= zrl_et_15 & !end_of_block;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_output_count <= 0; Y11_JPEG_LSBs_2 <= 0; Y11_Huff_shift <= 0;
Y11_Huff_1 <= 0;
end
else if (enable_5) begin
Y11_output_count <= Y11_bits_1 + Y11_Huff_count;
Y11_JPEG_LSBs_2 <= Y11_JPEG_LSBs_1 << Y11_amp_shift;
Y11_Huff_shift <= 11 - Y11_Huff_count;
Y11_Huff_1 <= Y11_Huff;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_JPEG_LSBs_2 <= 0;
Y12_Huff <= 0; Y12_Huff_count <= 0; Y12_bits_2 <= 0;
Y12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0;
end
else if (enable_module) begin
Y12_JPEG_LSBs_2 <= Y12_JPEG_LSBs_1 << Y12_amp_shift;
Y12_Huff <= Y_AC[Y12_code_entry];
Y12_Huff_count <= Y_AC_code_length[Y12_code_entry];
Y12_bits_2 <= Y12_bits_1;
Y12_et_zero_4 <= Y12_et_zero_3;
zrl_et_15 <= zrl_3 == 15;
zrl_3 <= zrl_2;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_Huff <= 0; Y11_Huff_count <= 0; Y11_amp_shift <= 0;
Y11_JPEG_LSBs_1 <= 0; Y11_bits_1 <= 0;
end
else if (enable_4) begin
Y11_Huff[10:0] <= Y_DC[Y11_bits];
Y11_Huff_count <= Y_DC_code_length[Y11_bits];
Y11_amp_shift <= 11 - Y11_bits;
Y11_JPEG_LSBs_1 <= Y11_JPEG_LSBs;
Y11_bits_1 <= Y11_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_code_entry <= 0; Y12_JPEG_LSBs_1 <= 0; Y12_amp_shift <= 0;
Y12_bits_1 <= 0; Y12_et_zero_3 <= 0; zrl_2 <= 0;
end
else if (enable_module) begin
Y12_code_entry <= Y_AC_run_code[code_index];
Y12_JPEG_LSBs_1 <= Y12_JPEG_LSBs;
Y12_amp_shift <= 10 - Y12_bits;
Y12_bits_1 <= Y12_bits;
Y12_et_zero_3 <= Y12_et_zero_2;
zrl_2 <= zrl_1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_bits <= 0; Y11_JPEG_LSBs <= 0;
end
else if (enable_3) begin
Y11_bits <= Y11_msb ? Y11_bits_neg : Y11_bits_pos;
Y11_JPEG_LSBs <= Y11_amp[10:0]; // The top bit of Y11_amp is the sign bit
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_bits <= 0; Y12_JPEG_LSBs <= 0; zrl_1 <= 0;
Y12_et_zero_2 <= 0;
end
else if (enable_module) begin
Y12_bits <= Y12_msb_1 ? Y12_bits_neg : Y12_bits_pos;
Y12_JPEG_LSBs <= Y12_amp[9:0]; // The top bit of Y12_amp is the sign bit
zrl_1 <= block_counter == 62 & Y12_et_zero ? 0 : zero_run_length;
Y12_et_zero_2 <= Y12_et_zero_1;
end
end
// Y11_amp is the amplitude that will be represented in bits in the
// JPEG code, following the run length code
always @(posedge clk)
begin
if (rst) begin
Y11_amp <= 0;
end
else if (enable_2) begin
Y11_amp <= Y11_msb ? Y11_1_neg : Y11_1_pos;
end
end
always @(posedge clk)
begin
if (rst)
zero_run_length <= 0;
else if (enable)
zero_run_length <= 0;
else if (enable_module)
zero_run_length <= Y12_et_zero ? zero_run_length + 1: 0;
end
always @(posedge clk)
begin
if (rst) begin
Y12_amp <= 0;
Y12_et_zero_1 <= 0; Y12_msb_1 <= 0;
end
else if (enable_module) begin
Y12_amp <= Y12_msb ? Y12_neg : Y12_pos;
Y12_et_zero_1 <= Y12_et_zero;
Y12_msb_1 <= Y12_msb;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_1_pos <= 0; Y11_1_neg <= 0; Y11_msb <= 0;
Y11_previous <= 0;
end
else if (enable_1) begin
Y11_1_pos <= Y11_diff;
Y11_1_neg <= Y11_diff - 1;
Y11_msb <= Y11_diff[11];
Y11_previous <= Y11_1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_pos <= 0; Y12_neg <= 0; Y12_msb <= 0; Y12_et_zero <= 0;
Y13_pos <= 0; Y13_neg <= 0; Y13_msb <= 0; Y13_et_zero <= 0;
Y14_pos <= 0; Y14_neg <= 0; Y14_msb <= 0; Y14_et_zero <= 0;
Y15_pos <= 0; Y15_neg <= 0; Y15_msb <= 0; Y15_et_zero <= 0;
Y16_pos <= 0; Y16_neg <= 0; Y16_msb <= 0; Y16_et_zero <= 0;
Y17_pos <= 0; Y17_neg <= 0; Y17_msb <= 0; Y17_et_zero <= 0;
Y18_pos <= 0; Y18_neg <= 0; Y18_msb <= 0; Y18_et_zero <= 0;
Y21_pos <= 0; Y21_neg <= 0; Y21_msb <= 0; Y21_et_zero <= 0;
Y22_pos <= 0; Y22_neg <= 0; Y22_msb <= 0; Y22_et_zero <= 0;
Y23_pos <= 0; Y23_neg <= 0; Y23_msb <= 0; Y23_et_zero <= 0;
Y24_pos <= 0; Y24_neg <= 0; Y24_msb <= 0; Y24_et_zero <= 0;
Y25_pos <= 0; Y25_neg <= 0; Y25_msb <= 0; Y25_et_zero <= 0;
Y26_pos <= 0; Y26_neg <= 0; Y26_msb <= 0; Y26_et_zero <= 0;
Y27_pos <= 0; Y27_neg <= 0; Y27_msb <= 0; Y27_et_zero <= 0;
Y28_pos <= 0; Y28_neg <= 0; Y28_msb <= 0; Y28_et_zero <= 0;
Y31_pos <= 0; Y31_neg <= 0; Y31_msb <= 0; Y31_et_zero <= 0;
Y32_pos <= 0; Y32_neg <= 0; Y32_msb <= 0; Y32_et_zero <= 0;
Y33_pos <= 0; Y33_neg <= 0; Y33_msb <= 0; Y33_et_zero <= 0;
Y34_pos <= 0; Y34_neg <= 0; Y34_msb <= 0; Y34_et_zero <= 0;
Y35_pos <= 0; Y35_neg <= 0; Y35_msb <= 0; Y35_et_zero <= 0;
Y36_pos <= 0; Y36_neg <= 0; Y36_msb <= 0; Y36_et_zero <= 0;
Y37_pos <= 0; Y37_neg <= 0; Y37_msb <= 0; Y37_et_zero <= 0;
Y38_pos <= 0; Y38_neg <= 0; Y38_msb <= 0; Y38_et_zero <= 0;
Y41_pos <= 0; Y41_neg <= 0; Y41_msb <= 0; Y41_et_zero <= 0;
Y42_pos <= 0; Y42_neg <= 0; Y42_msb <= 0; Y42_et_zero <= 0;
Y43_pos <= 0; Y43_neg <= 0; Y43_msb <= 0; Y43_et_zero <= 0;
Y44_pos <= 0; Y44_neg <= 0; Y44_msb <= 0; Y44_et_zero <= 0;
Y45_pos <= 0; Y45_neg <= 0; Y45_msb <= 0; Y45_et_zero <= 0;
Y46_pos <= 0; Y46_neg <= 0; Y46_msb <= 0; Y46_et_zero <= 0;
Y47_pos <= 0; Y47_neg <= 0; Y47_msb <= 0; Y47_et_zero <= 0;
Y48_pos <= 0; Y48_neg <= 0; Y48_msb <= 0; Y48_et_zero <= 0;
Y51_pos <= 0; Y51_neg <= 0; Y51_msb <= 0; Y51_et_zero <= 0;
Y52_pos <= 0; Y52_neg <= 0; Y52_msb <= 0; Y52_et_zero <= 0;
Y53_pos <= 0; Y53_neg <= 0; Y53_msb <= 0; Y53_et_zero <= 0;
Y54_pos <= 0; Y54_neg <= 0; Y54_msb <= 0; Y54_et_zero <= 0;
Y55_pos <= 0; Y55_neg <= 0; Y55_msb <= 0; Y55_et_zero <= 0;
Y56_pos <= 0; Y56_neg <= 0; Y56_msb <= 0; Y56_et_zero <= 0;
Y57_pos <= 0; Y57_neg <= 0; Y57_msb <= 0; Y57_et_zero <= 0;
Y58_pos <= 0; Y58_neg <= 0; Y58_msb <= 0; Y58_et_zero <= 0;
Y61_pos <= 0; Y61_neg <= 0; Y61_msb <= 0; Y61_et_zero <= 0;
Y62_pos <= 0; Y62_neg <= 0; Y62_msb <= 0; Y62_et_zero <= 0;
Y63_pos <= 0; Y63_neg <= 0; Y63_msb <= 0; Y63_et_zero <= 0;
Y64_pos <= 0; Y64_neg <= 0; Y64_msb <= 0; Y64_et_zero <= 0;
Y65_pos <= 0; Y65_neg <= 0; Y65_msb <= 0; Y65_et_zero <= 0;
Y66_pos <= 0; Y66_neg <= 0; Y66_msb <= 0; Y66_et_zero <= 0;
Y67_pos <= 0; Y67_neg <= 0; Y67_msb <= 0; Y67_et_zero <= 0;
Y68_pos <= 0; Y68_neg <= 0; Y68_msb <= 0; Y68_et_zero <= 0;
Y71_pos <= 0; Y71_neg <= 0; Y71_msb <= 0; Y71_et_zero <= 0;
Y72_pos <= 0; Y72_neg <= 0; Y72_msb <= 0; Y72_et_zero <= 0;
Y73_pos <= 0; Y73_neg <= 0; Y73_msb <= 0; Y73_et_zero <= 0;
Y74_pos <= 0; Y74_neg <= 0; Y74_msb <= 0; Y74_et_zero <= 0;
Y75_pos <= 0; Y75_neg <= 0; Y75_msb <= 0; Y75_et_zero <= 0;
Y76_pos <= 0; Y76_neg <= 0; Y76_msb <= 0; Y76_et_zero <= 0;
Y77_pos <= 0; Y77_neg <= 0; Y77_msb <= 0; Y77_et_zero <= 0;
Y78_pos <= 0; Y78_neg <= 0; Y78_msb <= 0; Y78_et_zero <= 0;
Y81_pos <= 0; Y81_neg <= 0; Y81_msb <= 0; Y81_et_zero <= 0;
Y82_pos <= 0; Y82_neg <= 0; Y82_msb <= 0; Y82_et_zero <= 0;
Y83_pos <= 0; Y83_neg <= 0; Y83_msb <= 0; Y83_et_zero <= 0;
Y84_pos <= 0; Y84_neg <= 0; Y84_msb <= 0; Y84_et_zero <= 0;
Y85_pos <= 0; Y85_neg <= 0; Y85_msb <= 0; Y85_et_zero <= 0;
Y86_pos <= 0; Y86_neg <= 0; Y86_msb <= 0; Y86_et_zero <= 0;
Y87_pos <= 0; Y87_neg <= 0; Y87_msb <= 0; Y87_et_zero <= 0;
Y88_pos <= 0; Y88_neg <= 0; Y88_msb <= 0; Y88_et_zero <= 0;
end
else if (enable) begin
Y12_pos <= Y12;
Y12_neg <= Y12 - 1;
Y12_msb <= Y12[10];
Y12_et_zero <= !(|Y12);
Y13_pos <= Y13;
Y13_neg <= Y13 - 1;
Y13_msb <= Y13[10];
Y13_et_zero <= !(|Y13);
Y14_pos <= Y14;
Y14_neg <= Y14 - 1;
Y14_msb <= Y14[10];
Y14_et_zero <= !(|Y14);
Y15_pos <= Y15;
Y15_neg <= Y15 - 1;
Y15_msb <= Y15[10];
Y15_et_zero <= !(|Y15);
Y16_pos <= Y16;
Y16_neg <= Y16 - 1;
Y16_msb <= Y16[10];
Y16_et_zero <= !(|Y16);
Y17_pos <= Y17;
Y17_neg <= Y17 - 1;
Y17_msb <= Y17[10];
Y17_et_zero <= !(|Y17);
Y18_pos <= Y18;
Y18_neg <= Y18 - 1;
Y18_msb <= Y18[10];
Y18_et_zero <= !(|Y18);
Y21_pos <= Y21;
Y21_neg <= Y21 - 1;
Y21_msb <= Y21[10];
Y21_et_zero <= !(|Y21);
Y22_pos <= Y22;
Y22_neg <= Y22 - 1;
Y22_msb <= Y22[10];
Y22_et_zero <= !(|Y22);
Y23_pos <= Y23;
Y23_neg <= Y23 - 1;
Y23_msb <= Y23[10];
Y23_et_zero <= !(|Y23);
Y24_pos <= Y24;
Y24_neg <= Y24 - 1;
Y24_msb <= Y24[10];
Y24_et_zero <= !(|Y24);
Y25_pos <= Y25;
Y25_neg <= Y25 - 1;
Y25_msb <= Y25[10];
Y25_et_zero <= !(|Y25);
Y26_pos <= Y26;
Y26_neg <= Y26 - 1;
Y26_msb <= Y26[10];
Y26_et_zero <= !(|Y26);
Y27_pos <= Y27;
Y27_neg <= Y27 - 1;
Y27_msb <= Y27[10];
Y27_et_zero <= !(|Y27);
Y28_pos <= Y28;
Y28_neg <= Y28 - 1;
Y28_msb <= Y28[10];
Y28_et_zero <= !(|Y28);
Y31_pos <= Y31;
Y31_neg <= Y31 - 1;
Y31_msb <= Y31[10];
Y31_et_zero <= !(|Y31);
Y32_pos <= Y32;
Y32_neg <= Y32 - 1;
Y32_msb <= Y32[10];
Y32_et_zero <= !(|Y32);
Y33_pos <= Y33;
Y33_neg <= Y33 - 1;
Y33_msb <= Y33[10];
Y33_et_zero <= !(|Y33);
Y34_pos <= Y34;
Y34_neg <= Y34 - 1;
Y34_msb <= Y34[10];
Y34_et_zero <= !(|Y34);
Y35_pos <= Y35;
Y35_neg <= Y35 - 1;
Y35_msb <= Y35[10];
Y35_et_zero <= !(|Y35);
Y36_pos <= Y36;
Y36_neg <= Y36 - 1;
Y36_msb <= Y36[10];
Y36_et_zero <= !(|Y36);
Y37_pos <= Y37;
Y37_neg <= Y37 - 1;
Y37_msb <= Y37[10];
Y37_et_zero <= !(|Y37);
Y38_pos <= Y38;
Y38_neg <= Y38 - 1;
Y38_msb <= Y38[10];
Y38_et_zero <= !(|Y38);
Y41_pos <= Y41;
Y41_neg <= Y41 - 1;
Y41_msb <= Y41[10];
Y41_et_zero <= !(|Y41);
Y42_pos <= Y42;
Y42_neg <= Y42 - 1;
Y42_msb <= Y42[10];
Y42_et_zero <= !(|Y42);
Y43_pos <= Y43;
Y43_neg <= Y43 - 1;
Y43_msb <= Y43[10];
Y43_et_zero <= !(|Y43);
Y44_pos <= Y44;
Y44_neg <= Y44 - 1;
Y44_msb <= Y44[10];
Y44_et_zero <= !(|Y44);
Y45_pos <= Y45;
Y45_neg <= Y45 - 1;
Y45_msb <= Y45[10];
Y45_et_zero <= !(|Y45);
Y46_pos <= Y46;
Y46_neg <= Y46 - 1;
Y46_msb <= Y46[10];
Y46_et_zero <= !(|Y46);
Y47_pos <= Y47;
Y47_neg <= Y47 - 1;
Y47_msb <= Y47[10];
Y47_et_zero <= !(|Y47);
Y48_pos <= Y48;
Y48_neg <= Y48 - 1;
Y48_msb <= Y48[10];
Y48_et_zero <= !(|Y48);
Y51_pos <= Y51;
Y51_neg <= Y51 - 1;
Y51_msb <= Y51[10];
Y51_et_zero <= !(|Y51);
Y52_pos <= Y52;
Y52_neg <= Y52 - 1;
Y52_msb <= Y52[10];
Y52_et_zero <= !(|Y52);
Y53_pos <= Y53;
Y53_neg <= Y53 - 1;
Y53_msb <= Y53[10];
Y53_et_zero <= !(|Y53);
Y54_pos <= Y54;
Y54_neg <= Y54 - 1;
Y54_msb <= Y54[10];
Y54_et_zero <= !(|Y54);
Y55_pos <= Y55;
Y55_neg <= Y55 - 1;
Y55_msb <= Y55[10];
Y55_et_zero <= !(|Y55);
Y56_pos <= Y56;
Y56_neg <= Y56 - 1;
Y56_msb <= Y56[10];
Y56_et_zero <= !(|Y56);
Y57_pos <= Y57;
Y57_neg <= Y57 - 1;
Y57_msb <= Y57[10];
Y57_et_zero <= !(|Y57);
Y58_pos <= Y58;
Y58_neg <= Y58 - 1;
Y58_msb <= Y58[10];
Y58_et_zero <= !(|Y58);
Y61_pos <= Y61;
Y61_neg <= Y61 - 1;
Y61_msb <= Y61[10];
Y61_et_zero <= !(|Y61);
Y62_pos <= Y62;
Y62_neg <= Y62 - 1;
Y62_msb <= Y62[10];
Y62_et_zero <= !(|Y62);
Y63_pos <= Y63;
Y63_neg <= Y63 - 1;
Y63_msb <= Y63[10];
Y63_et_zero <= !(|Y63);
Y64_pos <= Y64;
Y64_neg <= Y64 - 1;
Y64_msb <= Y64[10];
Y64_et_zero <= !(|Y64);
Y65_pos <= Y65;
Y65_neg <= Y65 - 1;
Y65_msb <= Y65[10];
Y65_et_zero <= !(|Y65);
Y66_pos <= Y66;
Y66_neg <= Y66 - 1;
Y66_msb <= Y66[10];
Y66_et_zero <= !(|Y66);
Y67_pos <= Y67;
Y67_neg <= Y67 - 1;
Y67_msb <= Y67[10];
Y67_et_zero <= !(|Y67);
Y68_pos <= Y68;
Y68_neg <= Y68 - 1;
Y68_msb <= Y68[10];
Y68_et_zero <= !(|Y68);
Y71_pos <= Y71;
Y71_neg <= Y71 - 1;
Y71_msb <= Y71[10];
Y71_et_zero <= !(|Y71);
Y72_pos <= Y72;
Y72_neg <= Y72 - 1;
Y72_msb <= Y72[10];
Y72_et_zero <= !(|Y72);
Y73_pos <= Y73;
Y73_neg <= Y73 - 1;
Y73_msb <= Y73[10];
Y73_et_zero <= !(|Y73);
Y74_pos <= Y74;
Y74_neg <= Y74 - 1;
Y74_msb <= Y74[10];
Y74_et_zero <= !(|Y74);
Y75_pos <= Y75;
Y75_neg <= Y75 - 1;
Y75_msb <= Y75[10];
Y75_et_zero <= !(|Y75);
Y76_pos <= Y76;
Y76_neg <= Y76 - 1;
Y76_msb <= Y76[10];
Y76_et_zero <= !(|Y76);
Y77_pos <= Y77;
Y77_neg <= Y77 - 1;
Y77_msb <= Y77[10];
Y77_et_zero <= !(|Y77);
Y78_pos <= Y78;
Y78_neg <= Y78 - 1;
Y78_msb <= Y78[10];
Y78_et_zero <= !(|Y78);
Y81_pos <= Y81;
Y81_neg <= Y81 - 1;
Y81_msb <= Y81[10];
Y81_et_zero <= !(|Y81);
Y82_pos <= Y82;
Y82_neg <= Y82 - 1;
Y82_msb <= Y82[10];
Y82_et_zero <= !(|Y82);
Y83_pos <= Y83;
Y83_neg <= Y83 - 1;
Y83_msb <= Y83[10];
Y83_et_zero <= !(|Y83);
Y84_pos <= Y84;
Y84_neg <= Y84 - 1;
Y84_msb <= Y84[10];
Y84_et_zero <= !(|Y84);
Y85_pos <= Y85;
Y85_neg <= Y85 - 1;
Y85_msb <= Y85[10];
Y85_et_zero <= !(|Y85);
Y86_pos <= Y86;
Y86_neg <= Y86 - 1;
Y86_msb <= Y86[10];
Y86_et_zero <= !(|Y86);
Y87_pos <= Y87;
Y87_neg <= Y87 - 1;
Y87_msb <= Y87[10];
Y87_et_zero <= !(|Y87);
Y88_pos <= Y88;
Y88_neg <= Y88 - 1;
Y88_msb <= Y88[10];
Y88_et_zero <= !(|Y88);
end
else if (enable_module) begin
Y12_pos <= Y21_pos;
Y12_neg <= Y21_neg;
Y12_msb <= Y21_msb;
Y12_et_zero <= Y21_et_zero;
Y21_pos <= Y31_pos;
Y21_neg <= Y31_neg;
Y21_msb <= Y31_msb;
Y21_et_zero <= Y31_et_zero;
Y31_pos <= Y22_pos;
Y31_neg <= Y22_neg;
Y31_msb <= Y22_msb;
Y31_et_zero <= Y22_et_zero;
Y22_pos <= Y13_pos;
Y22_neg <= Y13_neg;
Y22_msb <= Y13_msb;
Y22_et_zero <= Y13_et_zero;
Y13_pos <= Y14_pos;
Y13_neg <= Y14_neg;
Y13_msb <= Y14_msb;
Y13_et_zero <= Y14_et_zero;
Y14_pos <= Y23_pos;
Y14_neg <= Y23_neg;
Y14_msb <= Y23_msb;
Y14_et_zero <= Y23_et_zero;
Y23_pos <= Y32_pos;
Y23_neg <= Y32_neg;
Y23_msb <= Y32_msb;
Y23_et_zero <= Y32_et_zero;
Y32_pos <= Y41_pos;
Y32_neg <= Y41_neg;
Y32_msb <= Y41_msb;
Y32_et_zero <= Y41_et_zero;
Y41_pos <= Y51_pos;
Y41_neg <= Y51_neg;
Y41_msb <= Y51_msb;
Y41_et_zero <= Y51_et_zero;
Y51_pos <= Y42_pos;
Y51_neg <= Y42_neg;
Y51_msb <= Y42_msb;
Y51_et_zero <= Y42_et_zero;
Y42_pos <= Y33_pos;
Y42_neg <= Y33_neg;
Y42_msb <= Y33_msb;
Y42_et_zero <= Y33_et_zero;
Y33_pos <= Y24_pos;
Y33_neg <= Y24_neg;
Y33_msb <= Y24_msb;
Y33_et_zero <= Y24_et_zero;
Y24_pos <= Y15_pos;
Y24_neg <= Y15_neg;
Y24_msb <= Y15_msb;
Y24_et_zero <= Y15_et_zero;
Y15_pos <= Y16_pos;
Y15_neg <= Y16_neg;
Y15_msb <= Y16_msb;
Y15_et_zero <= Y16_et_zero;
Y16_pos <= Y25_pos;
Y16_neg <= Y25_neg;
Y16_msb <= Y25_msb;
Y16_et_zero <= Y25_et_zero;
Y25_pos <= Y34_pos;
Y25_neg <= Y34_neg;
Y25_msb <= Y34_msb;
Y25_et_zero <= Y34_et_zero;
Y34_pos <= Y43_pos;
Y34_neg <= Y43_neg;
Y34_msb <= Y43_msb;
Y34_et_zero <= Y43_et_zero;
Y43_pos <= Y52_pos;
Y43_neg <= Y52_neg;
Y43_msb <= Y52_msb;
Y43_et_zero <= Y52_et_zero;
Y52_pos <= Y61_pos;
Y52_neg <= Y61_neg;
Y52_msb <= Y61_msb;
Y52_et_zero <= Y61_et_zero;
Y61_pos <= Y71_pos;
Y61_neg <= Y71_neg;
Y61_msb <= Y71_msb;
Y61_et_zero <= Y71_et_zero;
Y71_pos <= Y62_pos;
Y71_neg <= Y62_neg;
Y71_msb <= Y62_msb;
Y71_et_zero <= Y62_et_zero;
Y62_pos <= Y53_pos;
Y62_neg <= Y53_neg;
Y62_msb <= Y53_msb;
Y62_et_zero <= Y53_et_zero;
Y53_pos <= Y44_pos;
Y53_neg <= Y44_neg;
Y53_msb <= Y44_msb;
Y53_et_zero <= Y44_et_zero;
Y44_pos <= Y35_pos;
Y44_neg <= Y35_neg;
Y44_msb <= Y35_msb;
Y44_et_zero <= Y35_et_zero;
Y35_pos <= Y26_pos;
Y35_neg <= Y26_neg;
Y35_msb <= Y26_msb;
Y35_et_zero <= Y26_et_zero;
Y26_pos <= Y17_pos;
Y26_neg <= Y17_neg;
Y26_msb <= Y17_msb;
Y26_et_zero <= Y17_et_zero;
Y17_pos <= Y18_pos;
Y17_neg <= Y18_neg;
Y17_msb <= Y18_msb;
Y17_et_zero <= Y18_et_zero;
Y18_pos <= Y27_pos;
Y18_neg <= Y27_neg;
Y18_msb <= Y27_msb;
Y18_et_zero <= Y27_et_zero;
Y27_pos <= Y36_pos;
Y27_neg <= Y36_neg;
Y27_msb <= Y36_msb;
Y27_et_zero <= Y36_et_zero;
Y36_pos <= Y45_pos;
Y36_neg <= Y45_neg;
Y36_msb <= Y45_msb;
Y36_et_zero <= Y45_et_zero;
Y45_pos <= Y54_pos;
Y45_neg <= Y54_neg;
Y45_msb <= Y54_msb;
Y45_et_zero <= Y54_et_zero;
Y54_pos <= Y63_pos;
Y54_neg <= Y63_neg;
Y54_msb <= Y63_msb;
Y54_et_zero <= Y63_et_zero;
Y63_pos <= Y72_pos;
Y63_neg <= Y72_neg;
Y63_msb <= Y72_msb;
Y63_et_zero <= Y72_et_zero;
Y72_pos <= Y81_pos;
Y72_neg <= Y81_neg;
Y72_msb <= Y81_msb;
Y72_et_zero <= Y81_et_zero;
Y81_pos <= Y82_pos;
Y81_neg <= Y82_neg;
Y81_msb <= Y82_msb;
Y81_et_zero <= Y82_et_zero;
Y82_pos <= Y73_pos;
Y82_neg <= Y73_neg;
Y82_msb <= Y73_msb;
Y82_et_zero <= Y73_et_zero;
Y73_pos <= Y64_pos;
Y73_neg <= Y64_neg;
Y73_msb <= Y64_msb;
Y73_et_zero <= Y64_et_zero;
Y64_pos <= Y55_pos;
Y64_neg <= Y55_neg;
Y64_msb <= Y55_msb;
Y64_et_zero <= Y55_et_zero;
Y55_pos <= Y46_pos;
Y55_neg <= Y46_neg;
Y55_msb <= Y46_msb;
Y55_et_zero <= Y46_et_zero;
Y46_pos <= Y37_pos;
Y46_neg <= Y37_neg;
Y46_msb <= Y37_msb;
Y46_et_zero <= Y37_et_zero;
Y37_pos <= Y28_pos;
Y37_neg <= Y28_neg;
Y37_msb <= Y28_msb;
Y37_et_zero <= Y28_et_zero;
Y28_pos <= Y38_pos;
Y28_neg <= Y38_neg;
Y28_msb <= Y38_msb;
Y28_et_zero <= Y38_et_zero;
Y38_pos <= Y47_pos;
Y38_neg <= Y47_neg;
Y38_msb <= Y47_msb;
Y38_et_zero <= Y47_et_zero;
Y47_pos <= Y56_pos;
Y47_neg <= Y56_neg;
Y47_msb <= Y56_msb;
Y47_et_zero <= Y56_et_zero;
Y56_pos <= Y65_pos;
Y56_neg <= Y65_neg;
Y56_msb <= Y65_msb;
Y56_et_zero <= Y65_et_zero;
Y65_pos <= Y74_pos;
Y65_neg <= Y74_neg;
Y65_msb <= Y74_msb;
Y65_et_zero <= Y74_et_zero;
Y74_pos <= Y83_pos;
Y74_neg <= Y83_neg;
Y74_msb <= Y83_msb;
Y74_et_zero <= Y83_et_zero;
Y83_pos <= Y84_pos;
Y83_neg <= Y84_neg;
Y83_msb <= Y84_msb;
Y83_et_zero <= Y84_et_zero;
Y84_pos <= Y75_pos;
Y84_neg <= Y75_neg;
Y84_msb <= Y75_msb;
Y84_et_zero <= Y75_et_zero;
Y75_pos <= Y66_pos;
Y75_neg <= Y66_neg;
Y75_msb <= Y66_msb;
Y75_et_zero <= Y66_et_zero;
Y66_pos <= Y57_pos;
Y66_neg <= Y57_neg;
Y66_msb <= Y57_msb;
Y66_et_zero <= Y57_et_zero;
Y57_pos <= Y48_pos;
Y57_neg <= Y48_neg;
Y57_msb <= Y48_msb;
Y57_et_zero <= Y48_et_zero;
Y48_pos <= Y58_pos;
Y48_neg <= Y58_neg;
Y48_msb <= Y58_msb;
Y48_et_zero <= Y58_et_zero;
Y58_pos <= Y67_pos;
Y58_neg <= Y67_neg;
Y58_msb <= Y67_msb;
Y58_et_zero <= Y67_et_zero;
Y67_pos <= Y76_pos;
Y67_neg <= Y76_neg;
Y67_msb <= Y76_msb;
Y67_et_zero <= Y76_et_zero;
Y76_pos <= Y85_pos;
Y76_neg <= Y85_neg;
Y76_msb <= Y85_msb;
Y76_et_zero <= Y85_et_zero;
Y85_pos <= Y86_pos;
Y85_neg <= Y86_neg;
Y85_msb <= Y86_msb;
Y85_et_zero <= Y86_et_zero;
Y86_pos <= Y77_pos;
Y86_neg <= Y77_neg;
Y86_msb <= Y77_msb;
Y86_et_zero <= Y77_et_zero;
Y77_pos <= Y68_pos;
Y77_neg <= Y68_neg;
Y77_msb <= Y68_msb;
Y77_et_zero <= Y68_et_zero;
Y68_pos <= Y78_pos;
Y68_neg <= Y78_neg;
Y68_msb <= Y78_msb;
Y68_et_zero <= Y78_et_zero;
Y78_pos <= Y87_pos;
Y78_neg <= Y87_neg;
Y78_msb <= Y87_msb;
Y78_et_zero <= Y87_et_zero;
Y87_pos <= Y88_pos;
Y87_neg <= Y88_neg;
Y87_msb <= Y88_msb;
Y87_et_zero <= Y88_et_zero;
Y88_pos <= 0;
Y88_neg <= 0;
Y88_msb <= 0;
Y88_et_zero <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_diff <= 0; Y11_1 <= 0;
end
else if (enable) begin // Need to sign extend Y11 to 12 bits
Y11_diff <= {Y11[10], Y11} - Y11_previous;
Y11_1 <= Y11[10] ? { 1'b1, Y11 } : { 1'b0, Y11 };
end
end
always @(posedge clk)
begin
if (rst)
Y11_bits_pos <= 0;
else if (Y11_1_pos[10] == 1)
Y11_bits_pos <= 11;
else if (Y11_1_pos[9] == 1)
Y11_bits_pos <= 10;
else if (Y11_1_pos[8] == 1)
Y11_bits_pos <= 9;
else if (Y11_1_pos[7] == 1)
Y11_bits_pos <= 8;
else if (Y11_1_pos[6] == 1)
Y11_bits_pos <= 7;
else if (Y11_1_pos[5] == 1)
Y11_bits_pos <= 6;
else if (Y11_1_pos[4] == 1)
Y11_bits_pos <= 5;
else if (Y11_1_pos[3] == 1)
Y11_bits_pos <= 4;
else if (Y11_1_pos[2] == 1)
Y11_bits_pos <= 3;
else if (Y11_1_pos[1] == 1)
Y11_bits_pos <= 2;
else if (Y11_1_pos[0] == 1)
Y11_bits_pos <= 1;
else
Y11_bits_pos <= 0;
end
always @(posedge clk)
begin
if (rst)
Y11_bits_neg <= 0;
else if (Y11_1_neg[10] == 0)
Y11_bits_neg <= 11;
else if (Y11_1_neg[9] == 0)
Y11_bits_neg <= 10;
else if (Y11_1_neg[8] == 0)
Y11_bits_neg <= 9;
else if (Y11_1_neg[7] == 0)
Y11_bits_neg <= 8;
else if (Y11_1_neg[6] == 0)
Y11_bits_neg <= 7;
else if (Y11_1_neg[5] == 0)
Y11_bits_neg <= 6;
else if (Y11_1_neg[4] == 0)
Y11_bits_neg <= 5;
else if (Y11_1_neg[3] == 0)
Y11_bits_neg <= 4;
else if (Y11_1_neg[2] == 0)
Y11_bits_neg <= 3;
else if (Y11_1_neg[1] == 0)
Y11_bits_neg <= 2;
else if (Y11_1_neg[0] == 0)
Y11_bits_neg <= 1;
else
Y11_bits_neg <= 0;
end
always @(posedge clk)
begin
if (rst)
Y12_bits_pos <= 0;
else if (Y12_pos[9] == 1)
Y12_bits_pos <= 10;
else if (Y12_pos[8] == 1)
Y12_bits_pos <= 9;
else if (Y12_pos[7] == 1)
Y12_bits_pos <= 8;
else if (Y12_pos[6] == 1)
Y12_bits_pos <= 7;
else if (Y12_pos[5] == 1)
Y12_bits_pos <= 6;
else if (Y12_pos[4] == 1)
Y12_bits_pos <= 5;
else if (Y12_pos[3] == 1)
Y12_bits_pos <= 4;
else if (Y12_pos[2] == 1)
Y12_bits_pos <= 3;
else if (Y12_pos[1] == 1)
Y12_bits_pos <= 2;
else if (Y12_pos[0] == 1)
Y12_bits_pos <= 1;
else
Y12_bits_pos <= 0;
end
always @(posedge clk)
begin
if (rst)
Y12_bits_neg <= 0;
else if (Y12_neg[9] == 0)
Y12_bits_neg <= 10;
else if (Y12_neg[8] == 0)
Y12_bits_neg <= 9;
else if (Y12_neg[7] == 0)
Y12_bits_neg <= 8;
else if (Y12_neg[6] == 0)
Y12_bits_neg <= 7;
else if (Y12_neg[5] == 0)
Y12_bits_neg <= 6;
else if (Y12_neg[4] == 0)
Y12_bits_neg <= 5;
else if (Y12_neg[3] == 0)
Y12_bits_neg <= 4;
else if (Y12_neg[2] == 0)
Y12_bits_neg <= 3;
else if (Y12_neg[1] == 0)
Y12_bits_neg <= 2;
else if (Y12_neg[0] == 0)
Y12_bits_neg <= 1;
else
Y12_bits_neg <= 0;
end
always @(posedge clk)
begin
if (rst) begin
enable_module <= 0;
end
else if (enable) begin
enable_module <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_latch_7 <= 0;
end
else if (block_counter == 68) begin
enable_latch_7 <= 0;
end
else if (enable_6) begin
enable_latch_7 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_latch_8 <= 0;
end
else if (enable_7) begin
enable_latch_8 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
enable_4 <= 0; enable_5 <= 0; enable_6 <= 0;
enable_7 <= 0; enable_8 <= 0; enable_9 <= 0;
enable_10 <= 0; enable_11 <= 0; enable_12 <= 0;
enable_13 <= 0;
end
else begin
enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2;
enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5;
enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8;
enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11;
enable_13 <= enable_12;
end
end
/* These Y DC and AC code lengths, run lengths, and bit codes
were created from the Huffman table entries in the JPEG file header.
For different Huffman tables for different images, these values
below will need to be changed. I created a matlab file to automatically
create these entries from the already encoded JPEG image. This matlab program
won't be any help if you're starting from scratch with a .tif or other
raw image file format. The values below come from a Huffman table, they
do not actually create the Huffman table based on the probabilities of
each code created from the image data. You will need another program to
create the optimal Huffman table, or you can go with a generic Huffman table,
which will have slightly less than the best compression.*/
always @(posedge clk)
begin
Y_DC_code_length[0] <= 2;
Y_DC_code_length[1] <= 2;
Y_DC_code_length[2] <= 2;
Y_DC_code_length[3] <= 3;
Y_DC_code_length[4] <= 4;
Y_DC_code_length[5] <= 5;
Y_DC_code_length[6] <= 6;
Y_DC_code_length[7] <= 7;
Y_DC_code_length[8] <= 8;
Y_DC_code_length[9] <= 9;
Y_DC_code_length[10] <= 10;
Y_DC_code_length[11] <= 11;
Y_DC[0] <= 11'b00000000000;
Y_DC[1] <= 11'b01000000000;
Y_DC[2] <= 11'b10000000000;
Y_DC[3] <= 11'b11000000000;
Y_DC[4] <= 11'b11100000000;
Y_DC[5] <= 11'b11110000000;
Y_DC[6] <= 11'b11111000000;
Y_DC[7] <= 11'b11111100000;
Y_DC[8] <= 11'b11111110000;
Y_DC[9] <= 11'b11111111000;
Y_DC[10] <= 11'b11111111100;
Y_DC[11] <= 11'b11111111110;
Y_AC_code_length[0] <= 2;
Y_AC_code_length[1] <= 2;
Y_AC_code_length[2] <= 3;
Y_AC_code_length[3] <= 4;
Y_AC_code_length[4] <= 4;
Y_AC_code_length[5] <= 4;
Y_AC_code_length[6] <= 5;
Y_AC_code_length[7] <= 5;
Y_AC_code_length[8] <= 5;
Y_AC_code_length[9] <= 6;
Y_AC_code_length[10] <= 6;
Y_AC_code_length[11] <= 7;
Y_AC_code_length[12] <= 7;
Y_AC_code_length[13] <= 7;
Y_AC_code_length[14] <= 7;
Y_AC_code_length[15] <= 8;
Y_AC_code_length[16] <= 8;
Y_AC_code_length[17] <= 8;
Y_AC_code_length[18] <= 9;
Y_AC_code_length[19] <= 9;
Y_AC_code_length[20] <= 9;
Y_AC_code_length[21] <= 9;
Y_AC_code_length[22] <= 9;
Y_AC_code_length[23] <= 10;
Y_AC_code_length[24] <= 10;
Y_AC_code_length[25] <= 10;
Y_AC_code_length[26] <= 10;
Y_AC_code_length[27] <= 10;
Y_AC_code_length[28] <= 11;
Y_AC_code_length[29] <= 11;
Y_AC_code_length[30] <= 11;
Y_AC_code_length[31] <= 11;
Y_AC_code_length[32] <= 12;
Y_AC_code_length[33] <= 12;
Y_AC_code_length[34] <= 12;
Y_AC_code_length[35] <= 12;
Y_AC_code_length[36] <= 15;
Y_AC_code_length[37] <= 16;
Y_AC_code_length[38] <= 16;
Y_AC_code_length[39] <= 16;
Y_AC_code_length[40] <= 16;
Y_AC_code_length[41] <= 16;
Y_AC_code_length[42] <= 16;
Y_AC_code_length[43] <= 16;
Y_AC_code_length[44] <= 16;
Y_AC_code_length[45] <= 16;
Y_AC_code_length[46] <= 16;
Y_AC_code_length[47] <= 16;
Y_AC_code_length[48] <= 16;
Y_AC_code_length[49] <= 16;
Y_AC_code_length[50] <= 16;
Y_AC_code_length[51] <= 16;
Y_AC_code_length[52] <= 16;
Y_AC_code_length[53] <= 16;
Y_AC_code_length[54] <= 16;
Y_AC_code_length[55] <= 16;
Y_AC_code_length[56] <= 16;
Y_AC_code_length[57] <= 16;
Y_AC_code_length[58] <= 16;
Y_AC_code_length[59] <= 16;
Y_AC_code_length[60] <= 16;
Y_AC_code_length[61] <= 16;
Y_AC_code_length[62] <= 16;
Y_AC_code_length[63] <= 16;
Y_AC_code_length[64] <= 16;
Y_AC_code_length[65] <= 16;
Y_AC_code_length[66] <= 16;
Y_AC_code_length[67] <= 16;
Y_AC_code_length[68] <= 16;
Y_AC_code_length[69] <= 16;
Y_AC_code_length[70] <= 16;
Y_AC_code_length[71] <= 16;
Y_AC_code_length[72] <= 16;
Y_AC_code_length[73] <= 16;
Y_AC_code_length[74] <= 16;
Y_AC_code_length[75] <= 16;
Y_AC_code_length[76] <= 16;
Y_AC_code_length[77] <= 16;
Y_AC_code_length[78] <= 16;
Y_AC_code_length[79] <= 16;
Y_AC_code_length[80] <= 16;
Y_AC_code_length[81] <= 16;
Y_AC_code_length[82] <= 16;
Y_AC_code_length[83] <= 16;
Y_AC_code_length[84] <= 16;
Y_AC_code_length[85] <= 16;
Y_AC_code_length[86] <= 16;
Y_AC_code_length[87] <= 16;
Y_AC_code_length[88] <= 16;
Y_AC_code_length[89] <= 16;
Y_AC_code_length[90] <= 16;
Y_AC_code_length[91] <= 16;
Y_AC_code_length[92] <= 16;
Y_AC_code_length[93] <= 16;
Y_AC_code_length[94] <= 16;
Y_AC_code_length[95] <= 16;
Y_AC_code_length[96] <= 16;
Y_AC_code_length[97] <= 16;
Y_AC_code_length[98] <= 16;
Y_AC_code_length[99] <= 16;
Y_AC_code_length[100] <= 16;
Y_AC_code_length[101] <= 16;
Y_AC_code_length[102] <= 16;
Y_AC_code_length[103] <= 16;
Y_AC_code_length[104] <= 16;
Y_AC_code_length[105] <= 16;
Y_AC_code_length[106] <= 16;
Y_AC_code_length[107] <= 16;
Y_AC_code_length[108] <= 16;
Y_AC_code_length[109] <= 16;
Y_AC_code_length[110] <= 16;
Y_AC_code_length[111] <= 16;
Y_AC_code_length[112] <= 16;
Y_AC_code_length[113] <= 16;
Y_AC_code_length[114] <= 16;
Y_AC_code_length[115] <= 16;
Y_AC_code_length[116] <= 16;
Y_AC_code_length[117] <= 16;
Y_AC_code_length[118] <= 16;
Y_AC_code_length[119] <= 16;
Y_AC_code_length[120] <= 16;
Y_AC_code_length[121] <= 16;
Y_AC_code_length[122] <= 16;
Y_AC_code_length[123] <= 16;
Y_AC_code_length[124] <= 16;
Y_AC_code_length[125] <= 16;
Y_AC_code_length[126] <= 16;
Y_AC_code_length[127] <= 16;
Y_AC_code_length[128] <= 16;
Y_AC_code_length[129] <= 16;
Y_AC_code_length[130] <= 16;
Y_AC_code_length[131] <= 16;
Y_AC_code_length[132] <= 16;
Y_AC_code_length[133] <= 16;
Y_AC_code_length[134] <= 16;
Y_AC_code_length[135] <= 16;
Y_AC_code_length[136] <= 16;
Y_AC_code_length[137] <= 16;
Y_AC_code_length[138] <= 16;
Y_AC_code_length[139] <= 16;
Y_AC_code_length[140] <= 16;
Y_AC_code_length[141] <= 16;
Y_AC_code_length[142] <= 16;
Y_AC_code_length[143] <= 16;
Y_AC_code_length[144] <= 16;
Y_AC_code_length[145] <= 16;
Y_AC_code_length[146] <= 16;
Y_AC_code_length[147] <= 16;
Y_AC_code_length[148] <= 16;
Y_AC_code_length[149] <= 16;
Y_AC_code_length[150] <= 16;
Y_AC_code_length[151] <= 16;
Y_AC_code_length[152] <= 16;
Y_AC_code_length[153] <= 16;
Y_AC_code_length[154] <= 16;
Y_AC_code_length[155] <= 16;
Y_AC_code_length[156] <= 16;
Y_AC_code_length[157] <= 16;
Y_AC_code_length[158] <= 16;
Y_AC_code_length[159] <= 16;
Y_AC_code_length[160] <= 16;
Y_AC_code_length[161] <= 16;
Y_AC[0] <= 16'b0000000000000000;
Y_AC[1] <= 16'b0100000000000000;
Y_AC[2] <= 16'b1000000000000000;
Y_AC[3] <= 16'b1010000000000000;
Y_AC[4] <= 16'b1011000000000000;
Y_AC[5] <= 16'b1100000000000000;
Y_AC[6] <= 16'b1101000000000000;
Y_AC[7] <= 16'b1101100000000000;
Y_AC[8] <= 16'b1110000000000000;
Y_AC[9] <= 16'b1110100000000000;
Y_AC[10] <= 16'b1110110000000000;
Y_AC[11] <= 16'b1111000000000000;
Y_AC[12] <= 16'b1111001000000000;
Y_AC[13] <= 16'b1111010000000000;
Y_AC[14] <= 16'b1111011000000000;
Y_AC[15] <= 16'b1111100000000000;
Y_AC[16] <= 16'b1111100100000000;
Y_AC[17] <= 16'b1111101000000000;
Y_AC[18] <= 16'b1111101100000000;
Y_AC[19] <= 16'b1111101110000000;
Y_AC[20] <= 16'b1111110000000000;
Y_AC[21] <= 16'b1111110010000000;
Y_AC[22] <= 16'b1111110100000000;
Y_AC[23] <= 16'b1111110110000000;
Y_AC[24] <= 16'b1111110111000000;
Y_AC[25] <= 16'b1111111000000000;
Y_AC[26] <= 16'b1111111001000000;
Y_AC[27] <= 16'b1111111010000000;
Y_AC[28] <= 16'b1111111011000000;
Y_AC[29] <= 16'b1111111011100000;
Y_AC[30] <= 16'b1111111100000000;
Y_AC[31] <= 16'b1111111100100000;
Y_AC[32] <= 16'b1111111101000000;
Y_AC[33] <= 16'b1111111101010000;
Y_AC[34] <= 16'b1111111101100000;
Y_AC[35] <= 16'b1111111101110000;
Y_AC[36] <= 16'b1111111110000000;
Y_AC[37] <= 16'b1111111110000010;
Y_AC[38] <= 16'b1111111110000011;
Y_AC[39] <= 16'b1111111110000100;
Y_AC[40] <= 16'b1111111110000101;
Y_AC[41] <= 16'b1111111110000110;
Y_AC[42] <= 16'b1111111110000111;
Y_AC[43] <= 16'b1111111110001000;
Y_AC[44] <= 16'b1111111110001001;
Y_AC[45] <= 16'b1111111110001010;
Y_AC[46] <= 16'b1111111110001011;
Y_AC[47] <= 16'b1111111110001100;
Y_AC[48] <= 16'b1111111110001101;
Y_AC[49] <= 16'b1111111110001110;
Y_AC[50] <= 16'b1111111110001111;
Y_AC[51] <= 16'b1111111110010000;
Y_AC[52] <= 16'b1111111110010001;
Y_AC[53] <= 16'b1111111110010010;
Y_AC[54] <= 16'b1111111110010011;
Y_AC[55] <= 16'b1111111110010100;
Y_AC[56] <= 16'b1111111110010101;
Y_AC[57] <= 16'b1111111110010110;
Y_AC[58] <= 16'b1111111110010111;
Y_AC[59] <= 16'b1111111110011000;
Y_AC[60] <= 16'b1111111110011001;
Y_AC[61] <= 16'b1111111110011010;
Y_AC[62] <= 16'b1111111110011011;
Y_AC[63] <= 16'b1111111110011100;
Y_AC[64] <= 16'b1111111110011101;
Y_AC[65] <= 16'b1111111110011110;
Y_AC[66] <= 16'b1111111110011111;
Y_AC[67] <= 16'b1111111110100000;
Y_AC[68] <= 16'b1111111110100001;
Y_AC[69] <= 16'b1111111110100010;
Y_AC[70] <= 16'b1111111110100011;
Y_AC[71] <= 16'b1111111110100100;
Y_AC[72] <= 16'b1111111110100101;
Y_AC[73] <= 16'b1111111110100110;
Y_AC[74] <= 16'b1111111110100111;
Y_AC[75] <= 16'b1111111110101000;
Y_AC[76] <= 16'b1111111110101001;
Y_AC[77] <= 16'b1111111110101010;
Y_AC[78] <= 16'b1111111110101011;
Y_AC[79] <= 16'b1111111110101100;
Y_AC[80] <= 16'b1111111110101101;
Y_AC[81] <= 16'b1111111110101110;
Y_AC[82] <= 16'b1111111110101111;
Y_AC[83] <= 16'b1111111110110000;
Y_AC[84] <= 16'b1111111110110001;
Y_AC[85] <= 16'b1111111110110010;
Y_AC[86] <= 16'b1111111110110011;
Y_AC[87] <= 16'b1111111110110100;
Y_AC[88] <= 16'b1111111110110101;
Y_AC[89] <= 16'b1111111110110110;
Y_AC[90] <= 16'b1111111110110111;
Y_AC[91] <= 16'b1111111110111000;
Y_AC[92] <= 16'b1111111110111001;
Y_AC[93] <= 16'b1111111110111010;
Y_AC[94] <= 16'b1111111110111011;
Y_AC[95] <= 16'b1111111110111100;
Y_AC[96] <= 16'b1111111110111101;
Y_AC[97] <= 16'b1111111110111110;
Y_AC[98] <= 16'b1111111110111111;
Y_AC[99] <= 16'b1111111111000000;
Y_AC[100] <= 16'b1111111111000001;
Y_AC[101] <= 16'b1111111111000010;
Y_AC[102] <= 16'b1111111111000011;
Y_AC[103] <= 16'b1111111111000100;
Y_AC[104] <= 16'b1111111111000101;
Y_AC[105] <= 16'b1111111111000110;
Y_AC[106] <= 16'b1111111111000111;
Y_AC[107] <= 16'b1111111111001000;
Y_AC[108] <= 16'b1111111111001001;
Y_AC[109] <= 16'b1111111111001010;
Y_AC[110] <= 16'b1111111111001011;
Y_AC[111] <= 16'b1111111111001100;
Y_AC[112] <= 16'b1111111111001101;
Y_AC[113] <= 16'b1111111111001110;
Y_AC[114] <= 16'b1111111111001111;
Y_AC[115] <= 16'b1111111111010000;
Y_AC[116] <= 16'b1111111111010001;
Y_AC[117] <= 16'b1111111111010010;
Y_AC[118] <= 16'b1111111111010011;
Y_AC[119] <= 16'b1111111111010100;
Y_AC[120] <= 16'b1111111111010101;
Y_AC[121] <= 16'b1111111111010110;
Y_AC[122] <= 16'b1111111111010111;
Y_AC[123] <= 16'b1111111111011000;
Y_AC[124] <= 16'b1111111111011001;
Y_AC[125] <= 16'b1111111111011010;
Y_AC[126] <= 16'b1111111111011011;
Y_AC[127] <= 16'b1111111111011100;
Y_AC[128] <= 16'b1111111111011101;
Y_AC[129] <= 16'b1111111111011110;
Y_AC[130] <= 16'b1111111111011111;
Y_AC[131] <= 16'b1111111111100000;
Y_AC[132] <= 16'b1111111111100001;
Y_AC[133] <= 16'b1111111111100010;
Y_AC[134] <= 16'b1111111111100011;
Y_AC[135] <= 16'b1111111111100100;
Y_AC[136] <= 16'b1111111111100101;
Y_AC[137] <= 16'b1111111111100110;
Y_AC[138] <= 16'b1111111111100111;
Y_AC[139] <= 16'b1111111111101000;
Y_AC[140] <= 16'b1111111111101001;
Y_AC[141] <= 16'b1111111111101010;
Y_AC[142] <= 16'b1111111111101011;
Y_AC[143] <= 16'b1111111111101100;
Y_AC[144] <= 16'b1111111111101101;
Y_AC[145] <= 16'b1111111111101110;
Y_AC[146] <= 16'b1111111111101111;
Y_AC[147] <= 16'b1111111111110000;
Y_AC[148] <= 16'b1111111111110001;
Y_AC[149] <= 16'b1111111111110010;
Y_AC[150] <= 16'b1111111111110011;
Y_AC[151] <= 16'b1111111111110100;
Y_AC[152] <= 16'b1111111111110101;
Y_AC[153] <= 16'b1111111111110110;
Y_AC[154] <= 16'b1111111111110111;
Y_AC[155] <= 16'b1111111111111000;
Y_AC[156] <= 16'b1111111111111001;
Y_AC[157] <= 16'b1111111111111010;
Y_AC[158] <= 16'b1111111111111011;
Y_AC[159] <= 16'b1111111111111100;
Y_AC[160] <= 16'b1111111111111101;
Y_AC[161] <= 16'b1111111111111110;
Y_AC_run_code[1] <= 0;
Y_AC_run_code[2] <= 1;
Y_AC_run_code[3] <= 2;
Y_AC_run_code[0] <= 3;
Y_AC_run_code[4] <= 4;
Y_AC_run_code[17] <= 5;
Y_AC_run_code[5] <= 6;
Y_AC_run_code[18] <= 7;
Y_AC_run_code[33] <= 8;
Y_AC_run_code[49] <= 9;
Y_AC_run_code[65] <= 10;
Y_AC_run_code[6] <= 11;
Y_AC_run_code[19] <= 12;
Y_AC_run_code[81] <= 13;
Y_AC_run_code[97] <= 14;
Y_AC_run_code[7] <= 15;
Y_AC_run_code[34] <= 16;
Y_AC_run_code[113] <= 17;
Y_AC_run_code[20] <= 18;
Y_AC_run_code[50] <= 19;
Y_AC_run_code[129] <= 20;
Y_AC_run_code[145] <= 21;
Y_AC_run_code[161] <= 22;
Y_AC_run_code[8] <= 23;
Y_AC_run_code[35] <= 24;
Y_AC_run_code[66] <= 25;
Y_AC_run_code[177] <= 26;
Y_AC_run_code[193] <= 27;
Y_AC_run_code[21] <= 28;
Y_AC_run_code[82] <= 29;
Y_AC_run_code[209] <= 30;
Y_AC_run_code[240] <= 31;
Y_AC_run_code[36] <= 32;
Y_AC_run_code[51] <= 33;
Y_AC_run_code[98] <= 34;
Y_AC_run_code[114] <= 35;
Y_AC_run_code[130] <= 36;
Y_AC_run_code[9] <= 37;
Y_AC_run_code[10] <= 38;
Y_AC_run_code[22] <= 39;
Y_AC_run_code[23] <= 40;
Y_AC_run_code[24] <= 41;
Y_AC_run_code[25] <= 42;
Y_AC_run_code[26] <= 43;
Y_AC_run_code[37] <= 44;
Y_AC_run_code[38] <= 45;
Y_AC_run_code[39] <= 46;
Y_AC_run_code[40] <= 47;
Y_AC_run_code[41] <= 48;
Y_AC_run_code[42] <= 49;
Y_AC_run_code[52] <= 50;
Y_AC_run_code[53] <= 51;
Y_AC_run_code[54] <= 52;
Y_AC_run_code[55] <= 53;
Y_AC_run_code[56] <= 54;
Y_AC_run_code[57] <= 55;
Y_AC_run_code[58] <= 56;
Y_AC_run_code[67] <= 57;
Y_AC_run_code[68] <= 58;
Y_AC_run_code[69] <= 59;
Y_AC_run_code[70] <= 60;
Y_AC_run_code[71] <= 61;
Y_AC_run_code[72] <= 62;
Y_AC_run_code[73] <= 63;
Y_AC_run_code[74] <= 64;
Y_AC_run_code[83] <= 65;
Y_AC_run_code[84] <= 66;
Y_AC_run_code[85] <= 67;
Y_AC_run_code[86] <= 68;
Y_AC_run_code[87] <= 69;
Y_AC_run_code[88] <= 70;
Y_AC_run_code[89] <= 71;
Y_AC_run_code[90] <= 72;
Y_AC_run_code[99] <= 73;
Y_AC_run_code[100] <= 74;
Y_AC_run_code[101] <= 75;
Y_AC_run_code[102] <= 76;
Y_AC_run_code[103] <= 77;
Y_AC_run_code[104] <= 78;
Y_AC_run_code[105] <= 79;
Y_AC_run_code[106] <= 80;
Y_AC_run_code[115] <= 81;
Y_AC_run_code[116] <= 82;
Y_AC_run_code[117] <= 83;
Y_AC_run_code[118] <= 84;
Y_AC_run_code[119] <= 85;
Y_AC_run_code[120] <= 86;
Y_AC_run_code[121] <= 87;
Y_AC_run_code[122] <= 88;
Y_AC_run_code[131] <= 89;
Y_AC_run_code[132] <= 90;
Y_AC_run_code[133] <= 91;
Y_AC_run_code[134] <= 92;
Y_AC_run_code[135] <= 93;
Y_AC_run_code[136] <= 94;
Y_AC_run_code[137] <= 95;
Y_AC_run_code[138] <= 96;
Y_AC_run_code[146] <= 97;
Y_AC_run_code[147] <= 98;
Y_AC_run_code[148] <= 99;
Y_AC_run_code[149] <= 100;
Y_AC_run_code[150] <= 101;
Y_AC_run_code[151] <= 102;
Y_AC_run_code[152] <= 103;
Y_AC_run_code[153] <= 104;
Y_AC_run_code[154] <= 105;
Y_AC_run_code[162] <= 106;
Y_AC_run_code[163] <= 107;
Y_AC_run_code[164] <= 108;
Y_AC_run_code[165] <= 109;
Y_AC_run_code[166] <= 110;
Y_AC_run_code[167] <= 111;
Y_AC_run_code[168] <= 112;
Y_AC_run_code[169] <= 113;
Y_AC_run_code[170] <= 114;
Y_AC_run_code[178] <= 115;
Y_AC_run_code[179] <= 116;
Y_AC_run_code[180] <= 117;
Y_AC_run_code[181] <= 118;
Y_AC_run_code[182] <= 119;
Y_AC_run_code[183] <= 120;
Y_AC_run_code[184] <= 121;
Y_AC_run_code[185] <= 122;
Y_AC_run_code[186] <= 123;
Y_AC_run_code[194] <= 124;
Y_AC_run_code[195] <= 125;
Y_AC_run_code[196] <= 126;
Y_AC_run_code[197] <= 127;
Y_AC_run_code[198] <= 128;
Y_AC_run_code[199] <= 129;
Y_AC_run_code[200] <= 130;
Y_AC_run_code[201] <= 131;
Y_AC_run_code[202] <= 132;
Y_AC_run_code[210] <= 133;
Y_AC_run_code[211] <= 134;
Y_AC_run_code[212] <= 135;
Y_AC_run_code[213] <= 136;
Y_AC_run_code[214] <= 137;
Y_AC_run_code[215] <= 138;
Y_AC_run_code[216] <= 139;
Y_AC_run_code[217] <= 140;
Y_AC_run_code[218] <= 141;
Y_AC_run_code[225] <= 142;
Y_AC_run_code[226] <= 143;
Y_AC_run_code[227] <= 144;
Y_AC_run_code[228] <= 145;
Y_AC_run_code[229] <= 146;
Y_AC_run_code[230] <= 147;
Y_AC_run_code[231] <= 148;
Y_AC_run_code[232] <= 149;
Y_AC_run_code[233] <= 150;
Y_AC_run_code[234] <= 151;
Y_AC_run_code[241] <= 152;
Y_AC_run_code[242] <= 153;
Y_AC_run_code[243] <= 154;
Y_AC_run_code[244] <= 155;
Y_AC_run_code[245] <= 156;
Y_AC_run_code[246] <= 157;
Y_AC_run_code[247] <= 158;
Y_AC_run_code[248] <= 159;
Y_AC_run_code[249] <= 160;
Y_AC_run_code[250] <= 161;
Y_AC_run_code[16] <= 0;
Y_AC_run_code[32] <= 0;
Y_AC_run_code[48] <= 0;
Y_AC_run_code[64] <= 0;
Y_AC_run_code[80] <= 0;
Y_AC_run_code[96] <= 0;
Y_AC_run_code[112] <= 0;
Y_AC_run_code[128] <= 0;
Y_AC_run_code[144] <= 0;
Y_AC_run_code[160] <= 0;
Y_AC_run_code[176] <= 0;
Y_AC_run_code[192] <= 0;
Y_AC_run_code[208] <= 0;
Y_AC_run_code[224] <= 0;
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[31] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[31] <= JPEG_bs_5[31];
else if (enable_module && orc_8 == 0)
JPEG_bitstream[31] <= JPEG_bs_5[31];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[30] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[30] <= JPEG_bs_5[30];
else if (enable_module && orc_8 <= 1)
JPEG_bitstream[30] <= JPEG_bs_5[30];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[29] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[29] <= JPEG_bs_5[29];
else if (enable_module && orc_8 <= 2)
JPEG_bitstream[29] <= JPEG_bs_5[29];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[28] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[28] <= JPEG_bs_5[28];
else if (enable_module && orc_8 <= 3)
JPEG_bitstream[28] <= JPEG_bs_5[28];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[27] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[27] <= JPEG_bs_5[27];
else if (enable_module && orc_8 <= 4)
JPEG_bitstream[27] <= JPEG_bs_5[27];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[26] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[26] <= JPEG_bs_5[26];
else if (enable_module && orc_8 <= 5)
JPEG_bitstream[26] <= JPEG_bs_5[26];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[25] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[25] <= JPEG_bs_5[25];
else if (enable_module && orc_8 <= 6)
JPEG_bitstream[25] <= JPEG_bs_5[25];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[24] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[24] <= JPEG_bs_5[24];
else if (enable_module && orc_8 <= 7)
JPEG_bitstream[24] <= JPEG_bs_5[24];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[23] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[23] <= JPEG_bs_5[23];
else if (enable_module && orc_8 <= 8)
JPEG_bitstream[23] <= JPEG_bs_5[23];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[22] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[22] <= JPEG_bs_5[22];
else if (enable_module && orc_8 <= 9)
JPEG_bitstream[22] <= JPEG_bs_5[22];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[21] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[21] <= JPEG_bs_5[21];
else if (enable_module && orc_8 <= 10)
JPEG_bitstream[21] <= JPEG_bs_5[21];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[20] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[20] <= JPEG_bs_5[20];
else if (enable_module && orc_8 <= 11)
JPEG_bitstream[20] <= JPEG_bs_5[20];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[19] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[19] <= JPEG_bs_5[19];
else if (enable_module && orc_8 <= 12)
JPEG_bitstream[19] <= JPEG_bs_5[19];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[18] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[18] <= JPEG_bs_5[18];
else if (enable_module && orc_8 <= 13)
JPEG_bitstream[18] <= JPEG_bs_5[18];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[17] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[17] <= JPEG_bs_5[17];
else if (enable_module && orc_8 <= 14)
JPEG_bitstream[17] <= JPEG_bs_5[17];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[16] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[16] <= JPEG_bs_5[16];
else if (enable_module && orc_8 <= 15)
JPEG_bitstream[16] <= JPEG_bs_5[16];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[15] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[15] <= JPEG_bs_5[15];
else if (enable_module && orc_8 <= 16)
JPEG_bitstream[15] <= JPEG_bs_5[15];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[14] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[14] <= JPEG_bs_5[14];
else if (enable_module && orc_8 <= 17)
JPEG_bitstream[14] <= JPEG_bs_5[14];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[13] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[13] <= JPEG_bs_5[13];
else if (enable_module && orc_8 <= 18)
JPEG_bitstream[13] <= JPEG_bs_5[13];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[12] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[12] <= JPEG_bs_5[12];
else if (enable_module && orc_8 <= 19)
JPEG_bitstream[12] <= JPEG_bs_5[12];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[11] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[11] <= JPEG_bs_5[11];
else if (enable_module && orc_8 <= 20)
JPEG_bitstream[11] <= JPEG_bs_5[11];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[10] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[10] <= JPEG_bs_5[10];
else if (enable_module && orc_8 <= 21)
JPEG_bitstream[10] <= JPEG_bs_5[10];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[9] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[9] <= JPEG_bs_5[9];
else if (enable_module && orc_8 <= 22)
JPEG_bitstream[9] <= JPEG_bs_5[9];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[8] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[8] <= JPEG_bs_5[8];
else if (enable_module && orc_8 <= 23)
JPEG_bitstream[8] <= JPEG_bs_5[8];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[7] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[7] <= JPEG_bs_5[7];
else if (enable_module && orc_8 <= 24)
JPEG_bitstream[7] <= JPEG_bs_5[7];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[6] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[6] <= JPEG_bs_5[6];
else if (enable_module && orc_8 <= 25)
JPEG_bitstream[6] <= JPEG_bs_5[6];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[5] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[5] <= JPEG_bs_5[5];
else if (enable_module && orc_8 <= 26)
JPEG_bitstream[5] <= JPEG_bs_5[5];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[4] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[4] <= JPEG_bs_5[4];
else if (enable_module && orc_8 <= 27)
JPEG_bitstream[4] <= JPEG_bs_5[4];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[3] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[3] <= JPEG_bs_5[3];
else if (enable_module && orc_8 <= 28)
JPEG_bitstream[3] <= JPEG_bs_5[3];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[2] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[2] <= JPEG_bs_5[2];
else if (enable_module && orc_8 <= 29)
JPEG_bitstream[2] <= JPEG_bs_5[2];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[1] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[1] <= JPEG_bs_5[1];
else if (enable_module && orc_8 <= 30)
JPEG_bitstream[1] <= JPEG_bs_5[1];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[0] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[0] <= JPEG_bs_5[0];
else if (enable_module && orc_8 <= 31)
JPEG_bitstream[0] <= JPEG_bs_5[0];
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_dac_1c_2p_f (
rst,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_o,
spi_sd_i,
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
debug_clk,
debug_data,
debug_trigger,
delay_clk);
input rst;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output spi_cs0n;
output spi_cs1n;
output spi_clk;
output spi_sd_o;
input spi_sd_i;
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
output debug_clk;
output [79:0] debug_data;
output [ 7:0] debug_trigger;
input delay_clk;
reg up_dds_parity_type = 'd0;
reg up_dds_sel = 'd0;
reg up_dds_interpolate = 'd0;
reg up_dds_enable = 'd0;
reg [15:0] up_dds_incr = 'd0;
reg up_spi_devsel = 'd0;
reg up_spi_start = 'd0;
reg [31:0] up_spi_wdata_1 = 'd0;
reg [15:0] up_spi_wdata_0 = 'd0;
reg [ 7:0] up_status = 'd0;
reg up_spi_status_d = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_ovf_m2 = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_vdma_unf_m2 = 'd0;
reg up_vdma_unf = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
wire up_wr_s;
wire up_rd_s;
wire up_ack_s;
wire [ 7:0] up_spi_rdata_s;
wire up_spi_status_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [13:0] dds_data_00_s;
wire [13:0] dds_data_01_s;
wire [13:0] dds_data_02_s;
wire [13:0] dds_data_03_s;
wire [13:0] dds_data_04_s;
wire [13:0] dds_data_05_s;
wire [13:0] dds_data_06_s;
wire [13:0] dds_data_07_s;
wire [13:0] dds_data_08_s;
wire [13:0] dds_data_09_s;
wire [13:0] dds_data_10_s;
wire [13:0] dds_data_11_s;
assign up_wr_s = up_sel & ~up_rwn;
assign up_rd_s = up_sel & up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dds_parity_type <= 'd0;
up_dds_sel <= 'd0;
up_dds_interpolate <= 'd0;
up_dds_enable <= 'd0;
up_dds_incr <= 'd0;
up_spi_devsel <= 'd0;
up_spi_start <= 'd0;
up_spi_wdata_1 <= 'd0;
up_spi_wdata_0 <= 'd0;
up_status <= 'd0;
up_spi_status_d <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_ovf_m2 <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_vdma_unf_m2 <= 'd0;
up_vdma_unf <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_dds_parity_type <= up_wdata[19];
up_dds_sel <= up_wdata[18];
up_dds_interpolate <= up_wdata[17];
up_dds_enable <= up_wdata[16];
up_dds_incr <= up_wdata[15:0];
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_spi_devsel <= up_wdata[1];
end
if ((up_spi_status_d == 1'b0) && (up_spi_status_s == 1'b1)) begin
up_spi_start <= 1'b0;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_spi_start <= up_wdata[0];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_spi_wdata_1 <= up_wdata;
end
if ((up_addr == 5'h07) && (up_wr_s == 1'b1)) begin
up_spi_wdata_0 <= up_wdata[15:0];
end
up_status <= {4'd0, up_dds_parity_type, up_dds_sel, up_dds_interpolate, up_dds_enable};
up_spi_status_d <= up_spi_status_s;
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_ovf_m2 <= up_vdma_ovf_m1;
if (up_vdma_ovf_m2 == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_ovf <= up_vdma_ovf & (~up_wdata[1]);
end
up_vdma_unf_m1 <= vdma_unf_s;
up_vdma_unf_m2 <= up_vdma_unf_m1;
if (up_vdma_unf_m2 == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_unf <= up_vdma_unf & (~up_wdata[0]);
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {12'd0, up_dds_parity_type, up_dds_sel, up_dds_interpolate,
up_dds_enable, up_dds_incr};
5'h05: up_rdata <= {30'd0, up_spi_devsel, up_spi_start};
5'h06: up_rdata <= up_spi_wdata_1;
5'h07: up_rdata <= {16'd0, up_spi_wdata_0};
5'h08: up_rdata <= {23'd0, up_spi_status_s, up_spi_rdata_s};
5'h09: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
cf_spi i_spi (
.spi_cs0n (spi_cs0n),
.spi_cs1n (spi_cs1n),
.spi_clk (spi_clk),
.spi_sd_o (spi_sd_o),
.spi_sd_i (spi_sd_i),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_spi_start (up_spi_start),
.up_spi_devsel (up_spi_devsel),
.up_spi_wdata_1 (up_spi_wdata_1),
.up_spi_wdata_0 (up_spi_wdata_0),
.up_spi_rdata (up_spi_rdata_s),
.up_spi_status (up_spi_status_s),
.debug_trigger (),
.debug_data ());
cf_dds_top i_dds_top (
.vdma_clk (vdma_clk),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_sel (up_dds_sel),
.up_dds_incr (up_dds_incr),
.up_dds_enable (up_dds_enable),
.up_dds_interpolate (up_dds_interpolate),
.debug_clk (debug_clk),
.debug_data (debug_data),
.debug_trigger (debug_trigger));
cf_dac_if i_dac_if (
.rst (rst),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_enable (up_dds_enable),
.up_dds_parity_type (up_dds_parity_type));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Three basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
module ibyte_test;
parameter TRIALS = 100;
parameter MAX = 256;
reg [7:0] ar; // should it be "reg unsigned [7:0] aw"?
reg [7:0] ar_xz; // same as above here?
reg [7:0] ar_expected; // and here
byte unsigned bu;
byte unsigned bu_xz;
integer i;
assign bu = ar;
assign bu_xz = ar_xz;
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 8'b0 | bu_xz != 8'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// random numbers
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// with 'x injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect assigment to byte (when 'x): %b", bu);
$finish;
end
end
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead?
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<8; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [7:0] xz_expected (input [7:0] value_xz); // should it be "input unsigned [7:0] instead?
integer i;
begin
for (i=0; i<8; i=i+1)
begin
if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
value_xz[i] = 1'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable right shift in always
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
reg [7:0] value;
always @(var1 or var2)
value = var1 >> var2;
initial
begin
error = 0;
#1 ;
var1 = 8'h80;
var2 = 8'h7;
#1;
if(value !== 8'h1)
begin
error = 1;
$display ("FAILED - 80 >> 7 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h6;
#1;
if(value !== 8'h2)
begin
error = 1;
$display ("FAILED - 80 >> 6 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h5;
#1;
if(value !== 8'h4)
begin
error = 1;
$display ("FAILED - 80 >> 5 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h4;
#1;
if(value !== 8'h8)
begin
error = 1;
$display ("FAILED - 80 >> 4 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h3;
#1;
if(value !== 8'h10)
begin
error = 1;
$display ("FAILED - 80 >> 3 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h2;
#1;
if(value !== 8'h20)
begin
error = 1;
$display ("FAILED - 80 >> 2 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h1;
#1;
if(value !== 8'h40)
begin
error = 1;
$display ("FAILED - 80 >> 1 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h0;
#1;
if(value !== 8'h80)
begin
error = 1;
$display ("FAILED - 80 >> 0 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h7;
#1;
if(value !== 8'h01)
begin
error = 1;
$display ("FAILED - a5 >> 7 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h1;
#1;
if(value !== 8'h52)
begin
error = 1;
$display ("FAILED - aa >> 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
module test;
reg fail = 1'b0;
reg [3:0] bus = 4'b0;
initial begin
// Check the initial value.
if (bus !== 4'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1;
end
// Check a bit force and verify a normal bit assign does nothing.
#1 force bus[0] = 1'b1;
bus[0] = 1'bz;
if (bus !== 4'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
fail = 1'b1;
end
// Check a part force
#1 force bus[3:2] = 2'b11;
if (bus !== 4'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
fail = 1'b1;
end
// Check that we can change an unforced bit.
#1 bus[1] = 1'bz;
if (bus !== 4'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus);
fail = 1'b1;
end
#1 bus[1] = 1'b0;
// Check a bit release.
#1 release bus[0];
bus = 4'b000z;
if (bus !== 4'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
fail = 1'b1;
end
// Check a part release.
#1 release bus[3:2];
bus[3] = 1'b0;
if (bus !== 4'b010z) begin
$display("FAILED: release of bus[3:2], got %b, expected 010z.", bus);
fail = 1'b1;
end
// Check a force from the upper thread bits (>=8).
#1 force bus[2:1] = 2'bx1;
if (bus !== 4'b0x1z) begin
$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", bus);
fail = 1'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// related to, arising under or in connection with these
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// performance, such as life-support or safety devices or
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64, // LFSR shift register length
parameter DQS_CNT_WIDTH = 5,
parameter DQ_WIDTH = 72,
parameter VCCO_PAT_EN = 1,
parameter VCCAUX_PAT_EN = 1,
parameter ISI_PAT_EN = 1,
parameter FIXED_VICTIM = "TRUE"
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
input prbs_rdlvl_done,
input complex_wr_done,
input [2:0] victim_sel,
input [DQS_CNT_WIDTH:0] byte_cnt,
//output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
output [8*DQ_WIDTH-1:0] prbs_o,
output [9:0] dbg_prbs_gen,
input reset_rd_addr,
output prbs_ignore_first_byte,
output prbs_ignore_last_bytes
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
//******************************************************************************
// Complex pattern BRAM
//******************************************************************************
localparam BRAM_ADDR_WIDTH = 8;
localparam BRAM_DATA_WIDTH = 18;
localparam BRAM_DEPTH = 256;
integer i;
(* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr;
//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1];
reg [BRAM_DATA_WIDTH - 1:0] mem_out;
reg [BRAM_DATA_WIDTH - 3:0] dout_o;
reg [DQ_WIDTH-1:0] sel;
reg [DQ_WIDTH-1:0] dout_rise0;
reg [DQ_WIDTH-1:0] dout_fall0;
reg [DQ_WIDTH-1:0] dout_rise1;
reg [DQ_WIDTH-1:0] dout_fall1;
reg [DQ_WIDTH-1:0] dout_rise2;
reg [DQ_WIDTH-1:0] dout_fall2;
reg [DQ_WIDTH-1:0] dout_rise3;
reg [DQ_WIDTH-1:0] dout_fall3;
// VCCO noise injection pattern with matching victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
always @ (rd_addr) begin
case (rd_addr)
8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read
8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads
8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads
8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads
8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads
8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads
8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads
8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads
8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads
8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads
8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads
8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads
8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads
8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads
8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads
8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads
8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads
// VCCO noise injection pattern with non-matching victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read
8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads
8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads
8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads
8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads
8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads
8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads
8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads
8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads
8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads
8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads
8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads
8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads
8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads
8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads
8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads
8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads
// VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads
8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads
8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads
8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads
8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads
8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads
8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads
8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads
8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads
8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads
8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads
8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads
8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads
8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads
8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads
8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads
8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads
8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads
8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads
8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads
8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads
8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads
8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads
8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads
8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads
8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads
8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads
8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads
8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads
8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads
8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads
8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads
8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads
8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads
8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads
8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads
8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads
8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads
8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads
8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads
8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads
8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads
8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads
8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads
8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads
8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads
8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads
8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads
8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads
8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads
8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads
8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads
8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads
8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads
8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads
8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads
8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads
8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads
8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads
8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads
8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads
8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads
8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads
8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads
8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads
8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads
8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads
8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads
8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads
8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads
8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads
8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads
8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads
8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads
8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads
8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads
8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads
8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads
8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads
8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads
8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads
8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads
8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads
8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads
8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads
// ISI pattern (Back-to-back reads)
// content format
// {aggressor pattern, victim pattern}
8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111};
8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111};
8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000};
8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100};
8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001};
8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111};
8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101};
8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011};
8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101};
8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101};
8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000};
8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100};
8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101};
8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011};
8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111};
8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000};
8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011};
8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100};
8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011};
8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100};
8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101};
8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000};
//Additional for ISI
8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101};
8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101};
8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010};
8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010};
8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000};
//Available
8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001};
endcase
end
always @ (posedge clk_i) begin
if (rst_i | reset_rd_addr)
rd_addr <= #TCQ 'b0;
//rd_addr for complex oclkdelay calib
else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin
if (rd_addr == 'd156) rd_addr <= #TCQ 'b0;
else rd_addr <= #TCQ rd_addr + 1;
end
//rd_addr for complex rdlvl
else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin
if (rd_addr == 'd148) rd_addr <= #TCQ 'b0;
else rd_addr <= #TCQ rd_addr+1;
end
end
// Each pattern can be disabled independently
// When disabled zeros are written to and read from the DRAM
always @ (posedge clk_i) begin
if ((rd_addr < 42) && VCCO_PAT_EN)
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else if ((rd_addr < 127) && VCCAUX_PAT_EN)
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else if (ISI_PAT_EN && (rd_addr > 126))
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else
dout_o <= #TCQ 'd0;
end
reg prbs_ignore_first_byte_r;
always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16];
assign prbs_ignore_first_byte = prbs_ignore_first_byte_r;
reg prbs_ignore_last_bytes_r;
always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17];
assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r;
generate
if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed
// Fixed victim bit 3
always @(posedge clk_i)
sel <= #TCQ {DQ_WIDTH/8{8'h08}};
end else begin: victim_sel_rotate
// One-hot victim select
always @(posedge clk_i)
if (rst_i)
sel <= #TCQ 'd0;
else begin
for (i = 0; i < DQ_WIDTH; i = i+1) begin
if (i == byte_cnt*8+victim_sel)
sel[i] <= #TCQ 1'b1;
else
sel[i] <= #TCQ 1'b0;
end
end
end
endgenerate
// construct 8 X DATA_WIDTH output bus
always @(*)
for (i = 0; i < DQ_WIDTH; i = i+1) begin
dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]);
dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]);
dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]);
dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]);
dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]);
dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]);
dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]);
dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]);
end
assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0};
assign dbg_prbs_gen[9] = phy_if_empty_r;
assign dbg_prbs_gen[8] = clk_en_i;
assign dbg_prbs_gen[7:0] = rd_addr[7:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_8_V
`define SKY130_FD_SC_LP__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_8_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// $Id: aeMB_ctrl.v,v 1.10 2007-11-30 16:44:40 sybreon Exp $
//
// AEMB CONTROL UNIT
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <[email protected]>
//
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2007/11/15 09:26:43 sybreon
// Fixed minor typo causing synthesis failure.
//
// Revision 1.8 2007/11/14 23:19:24 sybreon
// Fixed minor typo.
//
// Revision 1.7 2007/11/14 22:14:34 sybreon
// Changed interrupt handling system (reported by M. Ettus).
//
// Revision 1.6 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.5 2007/11/09 20:51:52 sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.4 2007/11/08 17:48:14 sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.3 2007/11/08 14:17:47 sybreon
// Parameterised optional components.
//
// Revision 1.2 2007/11/02 19:20:58 sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1 2007/11/02 03:25:40 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
module aeMB_ctrl (/*AUTOARG*/
// Outputs
rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
fsl_stb_o, fsl_wre_o,
// Inputs
rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
);
// INTERNAL
//output [31:2] rPCLNK;
output [1:0] rMXDST;
output [1:0] rMXSRC, rMXTGT, rMXALT;
output [2:0] rMXALU;
output [4:0] rRW;
input rDLY;
input [15:0] rIMM;
input [10:0] rALT;
input [5:0] rOPC;
input [4:0] rRD, rRA, rRB;
input [31:2] rPC;
input rBRA;
input rMSR_IE;
input [31:0] xIREG;
// DATA WISHBONE
output dwb_stb_o;
output dwb_wre_o;
input dwb_ack_i;
// INST WISHBONE
input iwb_ack_i;
// FSL WISHBONE
output fsl_stb_o;
output fsl_wre_o;
input fsl_ack_i;
// SYSTEM
input gclk, grst, gena;
// --- DECODE INSTRUCTIONS
// TODO: Simplify
wire [5:0] wOPC;
wire [4:0] wRD, wRA, wRB;
wire [10:0] wALT;
assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
wire fSFT = (rOPC == 6'o44);
wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
wire fDIV = (rOPC == 6'o22);
wire fRTD = (rOPC == 6'o55);
wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
wire fBRA = fBRU & rRA[3];
wire fIMM = (rOPC == 6'o54);
wire fMOV = (rOPC == 6'o45);
wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
wire fLDST = (&rOPC[5:4]);
wire fPUT = (rOPC == 6'o33) & rRB[4];
wire fGET = (rOPC == 6'o33) & !rRB[4];
wire wSFT = (wOPC == 6'o44);
wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
wire wDIV = (wOPC == 6'o22);
wire wRTD = (wOPC == 6'o55);
wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
wire wBRA = wBRU & wRA[3];
wire wIMM = (wOPC == 6'o54);
wire wMOV = (wOPC == 6'o45);
wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
wire wLDST = (&wOPC[5:4]);
wire wPUT = (wOPC == 6'o33) & wRB[4];
wire wGET = (wOPC == 6'o33) & !wRB[4];
// --- BRANCH SLOT REGISTERS ---------------------------
reg [31:2] rPCLNK, xPCLNK;
reg [1:0] rMXDST, xMXDST;
reg [4:0] rRW, xRW;
reg [1:0] rMXSRC, xMXSRC;
reg [1:0] rMXTGT, xMXTGT;
reg [1:0] rMXALT, xMXALT;
// --- OPERAND SELECTOR ---------------------------------
wire wRDWE = |xRW;
wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
or wBFWD_R or wBRU or wOPC)
//if (rBRA | |rXCE) begin
if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xMXALT <= 2'h0;
xMXSRC <= 2'h0;
xMXTGT <= 2'h0;
// End of automatics
end else begin
xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
(wAFWD_M) ? 2'o2 : // RAM
(wAFWD_R) ? 2'o1 : // FWD
2'o0; // REG
xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
(wBFWD_M) ? 2'o2 : // RAM
(wBFWD_R) ? 2'o1 : // FWD
2'o0; // REG
xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
(wAFWD_R) ? 2'o1 : // FWD
2'o0; // REG
end // else: !if(rBRA)
// --- ALU CONTROL ---------------------------------------
reg [2:0] rMXALU, xMXALU;
always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
or wMUL or wSFT)
//if (rBRA | |rXCE) begin
if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xMXALU <= 3'h0;
// End of automatics
end else begin
xMXALU <= (wBRA | wMOV) ? 3'o3 :
(wSFT) ? 3'o2 :
(wLOG) ? 3'o1 :
(wMUL) ? 3'o4 :
(wBSF) ? 3'o5 :
(wDIV) ? 3'o6 :
3'o0;
end // else: !if(rBRA)
// --- DELAY SLOT REGISTERS ------------------------------
wire fSKIP = (rBRA & !rDLY);
always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
or fSTR or rRD)
if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xMXDST <= 2'h0;
xRW <= 5'h0;
// End of automatics
end else begin
xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
(fLOD | fGET) ? 2'o2 :
(fBRU) ? 2'o1 :
2'o0;
xRW <= rRD;
end // else: !if(fSKIP)
// --- DATA WISHBONE ----------------------------------
wire fDACK = !(dwb_stb_o ^ dwb_ack_i);
reg rDWBSTB, xDWBSTB;
reg rDWBWRE, xDWBWRE;
assign dwb_stb_o = rDWBSTB;
assign dwb_wre_o = rDWBWRE;
always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
//if (fSKIP | |rXCE) begin
if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xDWBSTB <= 1'h0;
xDWBWRE <= 1'h0;
// End of automatics
end else begin
xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
xDWBWRE <= fSTR & iwb_ack_i;
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBSTB <= 1'h0;
rDWBWRE <= 1'h0;
// End of automatics
end else if (fDACK) begin
rDWBSTB <= #1 xDWBSTB;
rDWBWRE <= #1 xDWBWRE;
end
// --- FSL WISHBONE -----------------------------------
wire fFACK = !(fsl_stb_o ^ fsl_ack_i);
reg rFSLSTB, xFSLSTB;
reg rFSLWRE, xFSLWRE;
assign fsl_stb_o = rFSLSTB;
assign fsl_wre_o = rFSLWRE;
always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
//if (fSKIP | |rXCE) begin
if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xFSLSTB <= 1'h0;
xFSLWRE <= 1'h0;
// End of automatics
end else begin
xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
xFSLWRE <= fPUT & iwb_ack_i;
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rFSLSTB <= 1'h0;
rFSLWRE <= 1'h0;
// End of automatics
end else if (fFACK) begin
rFSLSTB <= #1 xFSLSTB;
rFSLWRE <= #1 xFSLWRE;
end
// --- PIPELINE CONTROL DELAY ----------------------------
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rMXALT <= 2'h0;
rMXALU <= 3'h0;
rMXDST <= 2'h0;
rMXSRC <= 2'h0;
rMXTGT <= 2'h0;
rRW <= 5'h0;
// End of automatics
end else if (gena) begin // if (grst)
//rPCLNK <= #1 xPCLNK;
rMXDST <= #1 xMXDST;
rRW <= #1 xRW;
rMXSRC <= #1 xMXSRC;
rMXTGT <= #1 xMXTGT;
rMXALT <= #1 xMXALT;
rMXALU <= #1 xMXALU;
end
endmodule // aeMB_ctrl
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_7_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_7_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_7_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
/*
* File: imx_umc.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* unified (inst/data) on-chip memory controller hooked to IMX
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module imx_umc(
clk, rst,
iimx_adr_i, iimx_rqt_i,
iimx_rty_o, iimx_ack_o, iimx_err_o, iimx_dat_o, iimx_adr_o,
// icbu_adr_o, icbu_cycstb_o, icbu_ci_o, icbu_sel_o, icbu_tag_o,
// icbu_dat_i, icbu_ack_i, icbu_rty_i, icbu_err_i, icbu_tag_i,
dimx_adr_i, dimx_rqt_i, dimx_we_i, dimx_dat_i, dimx_sel_i,
dimx_dat_o, dimx_ack_o, dimx_err_o,
// dcbu_adr_o, dcbu_cycstb_o, dcbu_ci_o, dcbu_we_o, dcbu_sel_o, dcbu_tag_o, dcbu_dat_o,
// dcbu_dat_i, dcbu_ack_i, dcbu_rty_i, dcbu_err_i, dcbu_tag_i,
// uartlite backdoor
dsu_sram_ce, dsu_sram_we, dsu_sram_addr, dsu_sram_data,
dsu_burn_enable
);
parameter dw = 32;
input clk;
input rst;
//
// fetcher-umc interface
//
input [31:0] iimx_adr_i;
input iimx_rqt_i;
output [31:0] iimx_dat_o;
output iimx_ack_o;
output iimx_err_o;
output [31:0] iimx_adr_o;
output iimx_rty_o;
//
// umc-icbu interface
//
//output [31:0] icbu_adr_o;
//output icbu_cycstb_o;
//output icbu_ci_o;
//output [3:0] icbu_sel_o;
//output [3:0] icbu_tag_o;
//input [31:0] icbu_dat_i;
//input icbu_ack_i;
//input icbu_rty_i;
//input icbu_err_i;
//input [3:0] icbu_tag_i;
//
// lsu-umc interface
//
input [31:0] dimx_adr_i;
input dimx_rqt_i;
input [3:0] dimx_sel_i;
input dimx_we_i;
input [31:0] dimx_dat_i;
output [31:0] dimx_dat_o;
output dimx_ack_o;
output dimx_err_o;
//
// umc-dcbu interface
//
//output [31:0] dcbu_adr_o;
//output dcbu_cycstb_o;
//output dcbu_ci_o;
//output dcbu_we_o;
//output [3:0] dcbu_sel_o;
//output [3:0] dcbu_tag_o;
//output [dw-1:0] dcbu_dat_o;
//input [dw-1:0] dcbu_dat_i;
//input dcbu_ack_i;
//input dcbu_rty_i;
//input dcbu_err_i;
//input [3:0] dcbu_tag_i;
//
// dsu interface
//
input dsu_sram_ce;
input dsu_sram_we;
input [`UOCM_Word_BW-1:0] dsu_sram_addr;
input [31:0] dsu_sram_data;
input dsu_burn_enable;
//
// regs and wires
//
wire [3:0] dimx_sel_i;
wire imc_hit;
wire dmc_hit;
wire uocm_en;
wire uocm_we;
wire [31:0] uocm_addr;
wire [31:0] uocm_di, ram_di;
wire [31:0] ram_do;
wire [`UOCM_Word_BW-1:0]ram_addr;
reg [2:0] state;
reg dmc_ack;
reg imc_ack;
//
// address decoder
//
assign imc_hit = (iimx_adr_i & `pippo_IMC_MASK) == `pippo_IMC_ADDR;
assign dmc_hit = (dimx_adr_i & `pippo_DMC_MASK) == `pippo_DMC_ADDR;
assign imc_rqt_valid = imc_hit & iimx_rqt_i;
assign dmc_rqt_valid = dmc_hit & dimx_rqt_i;
//
// uocm access signals
//
assign uocm_addr = (dmc_rqt_valid) ? dimx_adr_i : iimx_adr_i;
assign uocm_en = imc_rqt_valid | dmc_rqt_valid;
// special case for byte/halfword store access
// cycle 1: store_nonword assert for two cycles
// reading memory to fetch the whole word
// cycle 2: store_nonword_reg assert for one cycle
// writing inserted word back to memory
// cycle 3: dmc_ack assert, the transaction complete
//
reg store_nonword_reg;
// "!dmc_ack" is to disassert store_nonword at cycle 3,
// if not, store_nonword_reg will assert at cycle 4.
assign store_nonword = !(&dimx_sel_i) & dmc_rqt_valid & dimx_we_i & !dmc_ack;
always @(posedge clk or posedge rst) begin
if (rst)
store_nonword_reg <= #1 1'b0;
else if (store_nonword_reg)
store_nonword_reg <= #1 1'b0;
else
store_nonword_reg <= #1 store_nonword;
end
reg [31:0] dat_nonword;
always @(*) begin
case(dimx_sel_i)
4'b1000: dat_nonword = {dimx_dat_i[31:24], ram_do[23:0]};
4'b0100: dat_nonword = {ram_do[31:24], dimx_dat_i[23:16], ram_do[15:0]};
4'b0010: dat_nonword = {ram_do[31:16], dimx_dat_i[15:8], ram_do[7:0]};
4'b0001: dat_nonword = {ram_do[31:8], dimx_dat_i[7:0]};
4'b1100: dat_nonword = {dimx_dat_i[31:16], ram_do[15:0]};
4'b0011: dat_nonword = {ram_do[31:16], dimx_dat_i[15:0]};
default: dat_nonword = ram_do;
endcase
end
// write happens:
// 1, normal store: only at the 1st cycle, dmc_ack assert at following cycle
// 2, byte/hw store: only at the 2nd cycle, dmc_ack assert at following cycle
assign uocm_we = dmc_rqt_valid & dimx_we_i & !dmc_ack & (!store_nonword | store_nonword_reg);
assign uocm_di = store_nonword ? dat_nonword : dimx_dat_i;
//
// backdoor for dsu
//
assign ram_addr = dsu_burn_enable ? dsu_sram_addr : uocm_addr[`UOCM_Word_BW+1:2];
assign ram_ce = dsu_burn_enable ? dsu_sram_ce : uocm_en;
assign ram_we = dsu_burn_enable ? dsu_sram_we : uocm_we;
assign ram_di = dsu_burn_enable ? dsu_sram_data : uocm_di;
// unified on-chip memory
imx_uocm imx_uocm(
.clk(clk),
.ce(ram_ce),
.we(ram_we),
.oe(1'b1),
.addr(ram_addr),
.di(ram_di),
.doq(ram_do)
);
//
// FSM for core response
// assumption: the uocm must be synchronous sram
//
`define pippo_UMCFSM_IDLE 3'd0
`define pippo_UMCFSM_LOAD 3'd1
`define pippo_UMCFSM_STORE 3'd2
`define pippo_UMCFSM_FETCH 3'd4
always @(posedge clk or `pippo_RST_EVENT rst) begin
if (rst == `pippo_RST_VALUE) begin
state <= `pippo_UMCFSM_IDLE;
dmc_ack <= 1'b0;
imc_ack <= 1'b0;
end
else case (state) // synopsys parallel_case
`pippo_UMCFSM_IDLE: begin
if (dmc_rqt_valid & dimx_we_i & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_STORE;
dmc_ack <= !dmc_ack & (!store_nonword | store_nonword_reg);
imc_ack <= 1'b0;
end
else if (dmc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_LOAD;
dmc_ack <= 1'b1;
imc_ack <= 1'b0;
end
else if (imc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_FETCH;
imc_ack <= 1'b1;
dmc_ack <= 1'b0;
end
end
`pippo_UMCFSM_STORE: begin
if (dmc_rqt_valid & dimx_we_i & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_STORE;
dmc_ack <= !dmc_ack & (!store_nonword | store_nonword_reg);
imc_ack <= 1'b0;
end
else if (dmc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_LOAD;
dmc_ack <= 1'b1;
imc_ack <= 1'b0;
end
else if (imc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_FETCH;
imc_ack <= 1'b1;
dmc_ack <= 1'b0;
end
else begin
state <= `pippo_UMCFSM_IDLE;
dmc_ack <= 1'b0;
imc_ack <= 1'b0;
end
end
`pippo_UMCFSM_LOAD: begin
if (dmc_rqt_valid & dimx_we_i & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_STORE;
dmc_ack <= !dmc_ack & (!store_nonword | store_nonword_reg);
imc_ack <= 1'b0;
end
else if (dmc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_LOAD;
dmc_ack <= 1'b1;
imc_ack <= 1'b0;
end
else if (imc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_FETCH;
imc_ack <= 1'b1;
dmc_ack <= 1'b0;
end
else begin
state <= `pippo_UMCFSM_IDLE;
dmc_ack <= 1'b0;
imc_ack <= 1'b0;
end
end
`pippo_UMCFSM_FETCH: begin
if (dmc_rqt_valid & dimx_we_i & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_STORE;
dmc_ack <= !dmc_ack & (!store_nonword | store_nonword_reg);
imc_ack <= 1'b0;
end
else if (dmc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_LOAD;
dmc_ack <= 1'b1;
imc_ack <= 1'b0;
end
else if (imc_rqt_valid & !dsu_burn_enable) begin
state <= `pippo_UMCFSM_FETCH;
imc_ack <= 1'b1;
dmc_ack <= 1'b0;
end
else begin
state <= `pippo_UMCFSM_IDLE;
dmc_ack <= 1'b0;
imc_ack <= 1'b0;
end
end
default: begin
state <= `pippo_UMCFSM_IDLE;
dmc_ack <= 1'b0;
imc_ack <= 1'b0;
end
endcase
end
// returned instruction address for fetcher
reg [31:0] rsp_addr;
always @(posedge clk or posedge rst) begin
if(rst) begin
rsp_addr <= #1 32'd0;
end
else if(imc_hit & iimx_rqt_i) begin
rsp_addr <= #1 uocm_addr;
end
else begin
rsp_addr <= #1 32'd0;
end
end
//
// umc response to core.fetcher
//
// address phase: for fetch pipeling, to improve performance
assign iimx_rty_o = imc_hit ? !(imc_rqt_valid & !dmc_rqt_valid) : 1'b1;
// data phase
assign iimx_ack_o = imc_hit ? imc_ack : 1'b0;
assign iimx_dat_o = imc_hit ? ram_do : 32'd0;
assign iimx_err_o = imc_hit ? !imc_ack : 1'b0;
assign iimx_adr_o = imc_hit ? rsp_addr : 32'd0;
//
// umc response to core.lsu
//
// data phase only, there is no address phase
assign dimx_ack_o = dmc_hit ? dmc_ack : 1'b0;
assign dimx_dat_o = dmc_hit ? ram_do : 32'd0;
assign dimx_err_o = dmc_hit ? !dmc_ack : 1'd0;
//
// umc response to core.fetcher
//
//assign iimx_rty_o = imc_ack ? !imc_ack : icbu_rty_i;
//assign iimx_ack_o = imc_ack ? imc_ack : icbu_ack_i;
//assign iimx_dat_o = imc_ack ? ram_do : icbu_dat_i;
//assign iimx_err_o = imc_ack ? !imc_ack : icbu_err_i;
//assign iimx_adr_o = imc_ack ? rsp_addr : icbu_adr_i;
//
// umc response to core.lsu
//
//assign dimx_ack_o = dmc_ack ? dmc_ack : dcbu_ack_i;
//assign dimx_dat_o = dmc_ack ? ram_do : dcbu_dat_i;
//assign dimx_err_o = dmc_ack ? !dmc_ack : dcbu_err_i;
//
// icbu request from umc
//
//assign icbu_adr_o = imc_hit ? 32'h0000_0000 : iimx_adr_i;
//assign icbu_cycstb_o = imc_hit ? 1'b0 : iimx_rqt_i;
//assign icbu_ci_o = imc_hit ? 1'b0 : iimx_ci_i;
//assign icbu_sel_o = imc_hit ? 4'h0 : iimx_sel_i;
//assign icbu_tag_o = imc_hit ? 4'h0 : iimx_tag_i;
//
// dcbu request from umc
//
//assign dcbu_adr_o = dmc_hit ? 32'h0000_0000 : dimx_adr_i;
//assign dcbu_cycstb_o = dmc_hit ? 1'b0 : dimx_rqt_i;
//assign dcbu_ci_o = dmc_hit ? 1'b0 : dimx_ci_i;
//assign dcbu_we_o = dmc_hit ? 1'b0 : dimx_we_i;
//assign dcbu_sel_o = dmc_hit ? 4'h0 : dimx_sel_i;
//assign dcbu_tag_o = dmc_hit ? 4'h0 : dimx_tag_i;
//assign dcbu_dat_o = dmc_hit ? 32'h0000_0000 : dimx_dat_i;
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
`define WIDTH 2
module top (
input OE1,
input OE2,
input [`WIDTH-1:0] A1,
input [`WIDTH-1:0] A2,
output [`WIDTH-1:0] Y1,
output [`WIDTH-1:0] Y2,
output [`WIDTH-1:0] Y3,
output [`WIDTH**2-1:0] W);
assign W[A1] = (OE2) ? A2[0] : 1'bz;
assign W[A2] = (OE1) ? A2[1] : 1'bz;
// have 2 different 'chips' drive the PAD to act like a bi-directional bus
wire [`WIDTH-1:0] PAD;
io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD));
io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD));
assign Y3 = PAD;
pullup p1(PAD);
// pulldown p1(PAD);
wire [5:0] fill = { 4'b0, A1 };
endmodule
module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD);
io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD));
endmodule
module io (input OE, input I, output O, inout PAD);
assign O = PAD;
assign PAD = OE ? I : 1'bz;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__AND4B_FUNCTIONAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_FUNCTIONAL_PP_V |
module soc_system (
button_pio_external_connection_export,
clk_clk,
dipsw_pio_external_connection_export,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
led_pio_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input [3:0] button_pio_external_connection_export;
input clk_clk;
input [3:0] dipsw_pio_external_connection_export;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] led_pio_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
/*------------------------------------------------------------------------------
Purpose
One stage of multicycle division.
------------------------------------------------------------------------------*/
module mips_div_stage #(
parameter WIDTH=32,
parameter STAGE=4
)
(
input[WIDTH-1:0] a,
input[WIDTH-1:0] b,
input[WIDTH-1:0] remainder_in,
output[WIDTH-1:0] quotient_out,
output[WIDTH-1:0] remainder_out
);
wire[WIDTH:0] result_temp[WIDTH:0];
wire[(WIDTH*2)-1:0] qr[WIDTH:0];
wire[WIDTH:0] divisor;
assign qr[WIDTH]={remainder_in,a[WIDTH-1:0]};
assign divisor={1'b0,b[WIDTH-1:0]};
generate
genvar gi;
for(gi=WIDTH;gi>(WIDTH-STAGE);gi=gi-1)
begin:gen
assign result_temp[gi-1]= qr[gi][(WIDTH*2)-1:WIDTH-1]-divisor;
assign qr[gi-1]= result_temp[gi-1][WIDTH] ? {qr[gi][(WIDTH*2)-2:0],1'd0} :
{result_temp[gi-1][WIDTH-1:0],qr[gi][WIDTH-2:0],1'd1};
end
endgenerate
assign quotient_out[WIDTH-1:0]= qr[WIDTH-STAGE][WIDTH-1:0];
assign remainder_out[WIDTH-1:0]= qr[WIDTH-STAGE][(2*WIDTH)-1:WIDTH];
endmodule
|
// system_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:14
`timescale 1 ps / 1 ps
module system_mm_interconnect_1 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire cra_root_reset_reset_bridge_in_reset_reset, // cra_root_reset_reset_bridge_in_reset.reset
input wire [29:0] acl_iface_kernel_cra_address, // acl_iface_kernel_cra.address
output wire acl_iface_kernel_cra_waitrequest, // .waitrequest
input wire [0:0] acl_iface_kernel_cra_burstcount, // .burstcount
input wire [7:0] acl_iface_kernel_cra_byteenable, // .byteenable
input wire acl_iface_kernel_cra_read, // .read
output wire [63:0] acl_iface_kernel_cra_readdata, // .readdata
output wire acl_iface_kernel_cra_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_cra_write, // .write
input wire [63:0] acl_iface_kernel_cra_writedata, // .writedata
input wire acl_iface_kernel_cra_debugaccess, // .debugaccess
output wire [3:0] cra_root_cra_slave_address, // cra_root_cra_slave.address
output wire cra_root_cra_slave_write, // .write
output wire cra_root_cra_slave_read, // .read
input wire [63:0] cra_root_cra_slave_readdata, // .readdata
output wire [63:0] cra_root_cra_slave_writedata, // .writedata
output wire [7:0] cra_root_cra_slave_byteenable, // .byteenable
input wire cra_root_cra_slave_readdatavalid, // .readdatavalid
input wire cra_root_cra_slave_waitrequest // .waitrequest
);
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest; // cra_root_cra_slave_translator:uav_waitrequest -> acl_iface_kernel_cra_translator:uav_waitrequest
wire [3:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount; // acl_iface_kernel_cra_translator:uav_burstcount -> cra_root_cra_slave_translator:uav_burstcount
wire [63:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata; // acl_iface_kernel_cra_translator:uav_writedata -> cra_root_cra_slave_translator:uav_writedata
wire [29:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_address; // acl_iface_kernel_cra_translator:uav_address -> cra_root_cra_slave_translator:uav_address
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_lock; // acl_iface_kernel_cra_translator:uav_lock -> cra_root_cra_slave_translator:uav_lock
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_write; // acl_iface_kernel_cra_translator:uav_write -> cra_root_cra_slave_translator:uav_write
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_read; // acl_iface_kernel_cra_translator:uav_read -> cra_root_cra_slave_translator:uav_read
wire [63:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata; // cra_root_cra_slave_translator:uav_readdata -> acl_iface_kernel_cra_translator:uav_readdata
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess; // acl_iface_kernel_cra_translator:uav_debugaccess -> cra_root_cra_slave_translator:uav_debugaccess
wire [7:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable; // acl_iface_kernel_cra_translator:uav_byteenable -> cra_root_cra_slave_translator:uav_byteenable
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid; // cra_root_cra_slave_translator:uav_readdatavalid -> acl_iface_kernel_cra_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) acl_iface_kernel_cra_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (cra_root_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_iface_kernel_cra_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (acl_iface_kernel_cra_translator_avalon_universal_master_0_read), // .read
.uav_write (acl_iface_kernel_cra_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (acl_iface_kernel_cra_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_cra_address), // avalon_anti_master_0.address
.av_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.av_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.av_read (acl_iface_kernel_cra_read), // .read
.av_readdata (acl_iface_kernel_cra_readdata), // .readdata
.av_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.av_write (acl_iface_kernel_cra_write), // .write
.av_writedata (acl_iface_kernel_cra_writedata), // .writedata
.av_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cra_root_cra_slave_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (cra_root_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_iface_kernel_cra_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (acl_iface_kernel_cra_translator_avalon_universal_master_0_read), // .read
.uav_write (acl_iface_kernel_cra_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (acl_iface_kernel_cra_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cra_root_cra_slave_address), // avalon_anti_slave_0.address
.av_write (cra_root_cra_slave_write), // .write
.av_read (cra_root_cra_slave_read), // .read
.av_readdata (cra_root_cra_slave_readdata), // .readdata
.av_writedata (cra_root_cra_slave_writedata), // .writedata
.av_byteenable (cra_root_cra_slave_byteenable), // .byteenable
.av_readdatavalid (cra_root_cra_slave_readdatavalid), // .readdatavalid
.av_waitrequest (cra_root_cra_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
//
// Create Date: 14:34:17 10/03/2016
// Module Name: IF_ID_tb
// Project Name: MIPS
// Description: Testing MIPS IF_ID register implementation in verilog.
//
// Dependencies: IF_ID.v
//
////////////////////////////////////////////////////////////////////////////////
module IF_ID_tb;
// Declare inputs.
reg clk;
reg [31:0] npc;
reg [31:0] instr;
// Declare outputs.
wire [31:0] instrout;
wire [31:0] npcout;
// Instantiate the IF_ID module.
IF_ID ifid(.clk(clk), .npc(npc), .instr(instr), .instrout(instrout),
.npcout(npcout));
initial begin
// Initialize inputs.
clk = 0;
npc = 0;
instr = 0;
// Test values.
npc = 32'h44444440;
instr = 32'hA0A0A0A0;
#10;
npc = 32'h22220022;
instr = 32'hFFFFFFFF;
#10;
npc = 32'h08080808;
instr = 32'hBBCCBBCC;
#10;
npc = 32'h78FF23A0;
instr = 32'h88905FBC;
// Terminate;
#10 $finish;
end
// Monitor values.
initial begin
$monitor("Time = %0d\tclk = %0d\tnpc = %8h \t instr = %8h\t\tnpcout = %8h\tinstrout = %8h",
$time, clk, npc, instr, npcout, instrout);
end
// Clock.
initial begin
forever begin
#10 clk = ~clk;
end
end
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t1] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete" program must not refer to any undefined
variables. We'll see shortly how to define the "free" variables
in a STLC term. A program is "closed", that is, it contains no
free variables.
*)
(** Having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
(* ###################################################################### *)
(** *** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
(* FILL IN HERE *)
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(* $Date: 2013-11-20 13:03:49 -0500 (Wed, 20 Nov 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
|
module allocator
(/*AUTOARG*/
// Outputs
allocator_cu_valid, allocator_cu_rejected, allocator_wg_id_out,
allocator_cu_id_out, allocator_wf_count, allocator_vgpr_size_out,
allocator_sgpr_size_out, allocator_lds_size_out,
allocator_gds_size_out, allocator_vgpr_start_out,
allocator_sgpr_start_out, allocator_lds_start_out,
allocator_gds_start_out,
// Inputs
clk, rst, inflight_wg_buffer_alloc_wg_id,
inflight_wg_buffer_alloc_num_wf,
inflight_wg_buffer_alloc_vgpr_size,
inflight_wg_buffer_alloc_sgpr_size,
inflight_wg_buffer_alloc_lds_size,
inflight_wg_buffer_alloc_gds_size, dis_controller_cu_busy,
dis_controller_alloc_ack, dis_controller_start_alloc,
grt_cam_up_valid, grt_cam_up_cu_id, grt_cam_up_vgpr_strt,
grt_cam_up_vgpr_size, grt_cam_up_sgpr_strt, grt_cam_up_sgpr_size,
grt_cam_up_lds_strt, grt_cam_up_lds_size, grt_cam_up_gds_strt,
grt_cam_up_gds_size, grt_cam_up_wg_count
);
parameter WG_ID_WIDTH = 6;
parameter CU_ID_WIDTH = 6;
parameter NUMBER_CU = 64;
parameter VGPR_ID_WIDTH = 10;
parameter NUMBER_VGPR_SLOTS = 1024;
parameter SGPR_ID_WIDTH = 10;
parameter NUMBER_SGPR_SLOTS = 1024;
parameter LDS_ID_WIDTH = 10;
parameter NUMBER_LDS_SLOTS = 1024;
parameter WG_SLOT_ID_WIDTH = 10;
parameter NUMBER_WF_SLOTS = 40;
parameter GDS_ID_WIDTH = 10;
parameter GDS_SIZE = 1024;
parameter WF_COUNT_WIDTH = 4;
// Allocation input port
input clk,rst;
input [WG_ID_WIDTH-1:0] inflight_wg_buffer_alloc_wg_id;
input [WF_COUNT_WIDTH-1:0] inflight_wg_buffer_alloc_num_wf;
input [VGPR_ID_WIDTH :0] inflight_wg_buffer_alloc_vgpr_size;
input [SGPR_ID_WIDTH :0] inflight_wg_buffer_alloc_sgpr_size;
input [LDS_ID_WIDTH :0] inflight_wg_buffer_alloc_lds_size;
input [GDS_ID_WIDTH :0] inflight_wg_buffer_alloc_gds_size;
input [NUMBER_CU-1:0] dis_controller_cu_busy;
input dis_controller_alloc_ack;
input dis_controller_start_alloc;
// Allocation output port
output allocator_cu_valid;
output allocator_cu_rejected;
output [WG_ID_WIDTH-1:0] allocator_wg_id_out;
output [CU_ID_WIDTH-1 :0] allocator_cu_id_out;
output [WF_COUNT_WIDTH-1:0] allocator_wf_count;
output [VGPR_ID_WIDTH :0] allocator_vgpr_size_out;
output [SGPR_ID_WIDTH :0] allocator_sgpr_size_out;
output [LDS_ID_WIDTH :0] allocator_lds_size_out;
output [GDS_ID_WIDTH :0] allocator_gds_size_out;
output [VGPR_ID_WIDTH-1 :0] allocator_vgpr_start_out;
output [SGPR_ID_WIDTH-1 :0] allocator_sgpr_start_out;
output [LDS_ID_WIDTH-1 :0] allocator_lds_start_out;
output [GDS_ID_WIDTH-1 :0] allocator_gds_start_out;
// CAM update port
input grt_cam_up_valid;
input [CU_ID_WIDTH-1 :0] grt_cam_up_cu_id;
input [VGPR_ID_WIDTH-1 :0] grt_cam_up_vgpr_strt;
input [VGPR_ID_WIDTH :0] grt_cam_up_vgpr_size;
input [SGPR_ID_WIDTH-1 :0] grt_cam_up_sgpr_strt;
input [SGPR_ID_WIDTH :0] grt_cam_up_sgpr_size;
input [LDS_ID_WIDTH-1 :0] grt_cam_up_lds_strt;
input [LDS_ID_WIDTH :0] grt_cam_up_lds_size;
input [GDS_ID_WIDTH-1 :0] grt_cam_up_gds_strt;
input [GDS_ID_WIDTH :0] grt_cam_up_gds_size;
input [WG_SLOT_ID_WIDTH:0] grt_cam_up_wg_count;
// Flop inputs
reg alloc_valid_i;
reg [WG_ID_WIDTH-1:0] alloc_wg_id_i;
reg [WF_COUNT_WIDTH-1:0] alloc_num_wf_i;
reg [VGPR_ID_WIDTH :0] alloc_vgpr_size_i;
reg [SGPR_ID_WIDTH :0] alloc_sgpr_size_i;
reg [LDS_ID_WIDTH :0] alloc_lds_size_i;
reg [GDS_ID_WIDTH :0] alloc_gds_size_i;
reg [NUMBER_CU-1:0] dis_controller_cu_busy_i;
reg cam_up_valid_i;
reg [CU_ID_WIDTH-1 :0] cam_up_cu_id_i;
reg [VGPR_ID_WIDTH-1 :0] cam_up_vgpr_strt_i;
reg [VGPR_ID_WIDTH :0] cam_up_vgpr_size_i;
reg [SGPR_ID_WIDTH-1 :0] cam_up_sgpr_strt_i;
reg [SGPR_ID_WIDTH :0] cam_up_sgpr_size_i;
reg [LDS_ID_WIDTH-1 :0] cam_up_lds_strt_i;
reg [LDS_ID_WIDTH :0] cam_up_lds_size_i;
reg [GDS_ID_WIDTH-1 :0] cam_up_gds_strt_i;
reg [GDS_ID_WIDTH :0] cam_up_gds_size_i;
reg [WG_SLOT_ID_WIDTH:0] cam_up_wg_count_i;
// cam outputs
reg cam_out_valid;
wire [NUMBER_CU-1 :0] vgpr_search_out, sgpr_search_out, lds_search_out,
wg_search_out;
reg gds_valid;
// Signals that bypass the cam
reg cam_wait_valid;
reg [WG_ID_WIDTH-1 : 0] cam_wait_wg_id;
reg [WF_COUNT_WIDTH-1: 0] cam_wait_wf_count;
reg [VGPR_ID_WIDTH:0] cam_wait_vgpr_size;
reg [SGPR_ID_WIDTH:0] cam_wait_sgpr_size;
reg [LDS_ID_WIDTH:0] cam_wait_lds_size;
reg [GDS_ID_WIDTH:0] cam_wait_gds_size;
reg [GDS_ID_WIDTH-1:0] cam_wait_gds_strt;
reg [NUMBER_CU-1:0] cam_wait_dis_controller_cu_busy;
// And cam outputs to check if there is anything we can use, choose the right cu
reg anded_cam_out_valid;
reg [NUMBER_CU-1: 0] anded_cam_out;
reg [WG_ID_WIDTH-1 :0] anded_cam_wg_id;
reg [WF_COUNT_WIDTH-1: 0] anded_cam_wf_count;
reg [VGPR_ID_WIDTH :0] anded_cam_vgpr_size;
reg [SGPR_ID_WIDTH :0] anded_cam_sgpr_size;
reg [LDS_ID_WIDTH :0] anded_cam_lds_size;
reg [GDS_ID_WIDTH :0] anded_cam_gds_size;
reg [GDS_ID_WIDTH-1 :0] anded_cam_gds_strt;
// Output encoder and find if we can use any cu, also addr the res start ram
reg encoded_cu_out_valid,
encoded_cu_found_valid, encoded_cu_found_valid_comb;
reg [CU_ID_WIDTH-1:0] encoded_cu_id, encoded_cu_id_comb;
reg [WG_ID_WIDTH-1 :0] encoded_cu_wg_id;
reg [WF_COUNT_WIDTH-1: 0] encoded_wf_count;
reg [VGPR_ID_WIDTH :0] encoded_vgpr_size;
reg [SGPR_ID_WIDTH :0] encoded_sgpr_size;
reg [LDS_ID_WIDTH :0] encoded_lds_size;
reg [GDS_ID_WIDTH :0] encoded_gds_size;
reg [GDS_ID_WIDTH-1 :0] encoded_gds_strt;
// res size ram lookup
reg size_ram_valid, size_ram_cu_id_found;
reg [CU_ID_WIDTH-1:0] cu_id_out;
reg [VGPR_ID_WIDTH-1:0] vgpr_start_out;
reg [SGPR_ID_WIDTH-1:0] sgpr_start_out;
reg [LDS_ID_WIDTH-1:0] lds_start_out;
reg [GDS_ID_WIDTH-1:0] gds_start_out;
reg [WG_ID_WIDTH-1 :0] wg_id_out;
reg [VGPR_ID_WIDTH :0] vgpr_size_out;
reg [SGPR_ID_WIDTH :0] sgpr_size_out;
reg [LDS_ID_WIDTH :0] lds_size_out;
reg [GDS_ID_WIDTH :0] gds_size_out;
reg [WF_COUNT_WIDTH-1: 0] wf_count_out;
localparam RAM_SIZE_WIDTH
= VGPR_ID_WIDTH + SGPR_ID_WIDTH + LDS_ID_WIDTH +GDS_ID_WIDTH;
localparam RES_SIZE_VGPR_START = 0;
localparam RES_SIZE_VGPR_END = RES_SIZE_VGPR_START+ VGPR_ID_WIDTH-1;
localparam RES_SIZE_SGPR_START = RES_SIZE_VGPR_END + 1;
localparam RES_SIZE_SGPR_END = RES_SIZE_SGPR_START+ SGPR_ID_WIDTH-1;
localparam RES_SIZE_LDS_START = RES_SIZE_SGPR_END + 1;
localparam RES_SIZE_LDS_END = RES_SIZE_LDS_START+ LDS_ID_WIDTH-1;
localparam RES_SIZE_GDS_START = RES_SIZE_LDS_END + 1;
localparam RES_SIZE_GDS_END = RES_SIZE_GDS_START+ GDS_ID_WIDTH-1;
wire [RAM_SIZE_WIDTH-1 :0] res_size_rd_wire, res_size_wr_wire;
reg [GDS_ID_WIDTH:0] gds_free;
reg [GDS_ID_WIDTH-1:0] gds_strt;
reg [NUMBER_CU-1:0] cu_initialized;
reg pipeline_waiting;
// Instantiate cams
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(VGPR_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_VGPR_SLOTS))
vgpr_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_vgpr_size_i),
// Search port out
.res_search_out(vgpr_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_vgpr_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(SGPR_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_SGPR_SLOTS))
sgpr_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_sgpr_size_i),
// Search port out
.res_search_out(sgpr_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_sgpr_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(LDS_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_LDS_SLOTS))
lds_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_lds_size_i),
// Search port out
.res_search_out(lds_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_lds_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(WG_SLOT_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_WF_SLOTS))
wf_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size({{(WG_SLOT_ID_WIDTH+1-(WF_COUNT_WIDTH)){1'b0}},
alloc_num_wf_i}),
// Search port out
.res_search_out(wg_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_wg_count_i));
ram_2_port
#(.WORD_SIZE(RAM_SIZE_WIDTH),
.ADDR_SIZE(CU_ID_WIDTH),
.NUM_WORDS(NUMBER_CU))
res_start_cam
(// Outputs
.rd_word (res_size_rd_wire),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (cam_up_valid_i),
.wr_addr (cam_up_cu_id_i),
.wr_word (res_size_wr_wire),
.rd_en (encoded_cu_out_valid &&
encoded_cu_found_valid),
.rd_addr (encoded_cu_id));
assign res_size_wr_wire = { cam_up_lds_strt_i,
cam_up_sgpr_strt_i, cam_up_vgpr_strt_i };
always @(posedge clk or rst) begin
if(rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
alloc_gds_size_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
alloc_lds_size_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
alloc_num_wf_i <= {WF_COUNT_WIDTH{1'b0}};
alloc_sgpr_size_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
alloc_valid_i <= 1'h0;
alloc_vgpr_size_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
alloc_wg_id_i <= {WG_ID_WIDTH{1'b0}};
anded_cam_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
anded_cam_gds_strt <= {GDS_ID_WIDTH{1'b0}};
anded_cam_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
anded_cam_out <= {NUMBER_CU{1'b0}};
anded_cam_out_valid <= 1'h0;
anded_cam_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
anded_cam_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
anded_cam_wf_count <= {WF_COUNT_WIDTH{1'b0}};
anded_cam_wg_id <= {WG_ID_WIDTH{1'b0}};
cam_up_cu_id_i <= {CU_ID_WIDTH{1'b0}};
cam_up_gds_size_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
cam_up_gds_strt_i <= {GDS_ID_WIDTH{1'b0}};
cam_up_lds_size_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
cam_up_lds_strt_i <= {LDS_ID_WIDTH{1'b0}};
cam_up_sgpr_size_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
cam_up_sgpr_strt_i <= {SGPR_ID_WIDTH{1'b0}};
cam_up_valid_i <= 1'h0;
cam_up_vgpr_size_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
cam_up_vgpr_strt_i <= {VGPR_ID_WIDTH{1'b0}};
cam_up_wg_count_i <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
cam_wait_dis_controller_cu_busy <= {NUMBER_CU{1'b0}};
cam_wait_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
cam_wait_gds_strt <= {GDS_ID_WIDTH{1'b0}};
cam_wait_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
cam_wait_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
cam_wait_valid <= 1'h0;
cam_wait_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
cam_wait_wf_count <= {WF_COUNT_WIDTH{1'b0}};
cam_wait_wg_id <= {WG_ID_WIDTH{1'b0}};
cu_id_out <= {CU_ID_WIDTH{1'b0}};
cu_initialized <= {NUMBER_CU{1'b0}};
dis_controller_cu_busy_i <= {NUMBER_CU{1'b0}};
encoded_cu_found_valid <= 1'h0;
encoded_cu_id <= {CU_ID_WIDTH{1'b0}};
encoded_cu_out_valid <= 1'h0;
encoded_cu_wg_id <= {WG_ID_WIDTH{1'b0}};
encoded_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
encoded_gds_strt <= {GDS_ID_WIDTH{1'b0}};
encoded_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
encoded_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
encoded_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
encoded_wf_count <= {WF_COUNT_WIDTH{1'b0}};
gds_free <= {(1+(GDS_ID_WIDTH)){1'b0}};
gds_size_out <= {(1+(GDS_ID_WIDTH)){1'b0}};
gds_start_out <= {GDS_ID_WIDTH{1'b0}};
gds_strt <= {GDS_ID_WIDTH{1'b0}};
gds_valid <= 1'h0;
lds_size_out <= {(1+(LDS_ID_WIDTH)){1'b0}};
pipeline_waiting <= 1'h0;
sgpr_size_out <= {(1+(SGPR_ID_WIDTH)){1'b0}};
size_ram_cu_id_found <= 1'h0;
size_ram_valid <= 1'h0;
vgpr_size_out <= {(1+(VGPR_ID_WIDTH)){1'b0}};
wf_count_out <= {WF_COUNT_WIDTH{1'b0}};
wg_id_out <= {WG_ID_WIDTH{1'b0}};
// End of automatics
gds_free <= GDS_SIZE;
end
else begin // if (rst)
// Locks the pipeline until an ack arrive from the controller
if(encoded_cu_out_valid && !pipeline_waiting) begin
pipeline_waiting <= 1'b1;
end
if(dis_controller_alloc_ack) begin
pipeline_waiting <= 1'b0;
end
if(!pipeline_waiting) begin
//////////////////////////////////
// Cam search pipeline
//////////////////////////////////
alloc_valid_i <= dis_controller_start_alloc;
alloc_wg_id_i <= inflight_wg_buffer_alloc_wg_id;
alloc_num_wf_i <= inflight_wg_buffer_alloc_num_wf;
alloc_vgpr_size_i <= inflight_wg_buffer_alloc_vgpr_size;
alloc_sgpr_size_i <= inflight_wg_buffer_alloc_sgpr_size;
alloc_lds_size_i <= inflight_wg_buffer_alloc_lds_size;
alloc_gds_size_i <= inflight_wg_buffer_alloc_gds_size;
dis_controller_cu_busy_i <= dis_controller_cu_busy;
// Wait for cam search
cam_wait_valid <= alloc_valid_i;
cam_wait_wg_id <= alloc_wg_id_i;
cam_wait_wf_count <= alloc_num_wf_i;
cam_wait_vgpr_size <= alloc_vgpr_size_i;
cam_wait_sgpr_size <= alloc_sgpr_size_i;
cam_wait_lds_size <= alloc_lds_size_i;
cam_wait_gds_size <= alloc_gds_size_i;
cam_wait_gds_strt <= gds_strt;
cam_wait_dis_controller_cu_busy <= dis_controller_cu_busy_i;
if(gds_free >= alloc_gds_size_i)
gds_valid <= 1'b1;
else
gds_valid <= 1'b0;
// AND all cam outs
anded_cam_out_valid <= cam_wait_valid;
anded_cam_out <= vgpr_search_out & sgpr_search_out & lds_search_out &
wg_search_out & {NUMBER_CU{gds_valid}} &
(~cam_wait_dis_controller_cu_busy);
anded_cam_wg_id <= cam_wait_wg_id;
anded_cam_wf_count <= cam_wait_wf_count;
anded_cam_vgpr_size <= cam_wait_vgpr_size;
anded_cam_sgpr_size <= cam_wait_sgpr_size;
anded_cam_lds_size <= cam_wait_lds_size;
anded_cam_gds_size <= cam_wait_gds_size;
anded_cam_gds_strt <= cam_wait_gds_strt;
// Use the encoded output to find the start of the resources
encoded_cu_out_valid <= anded_cam_out_valid;
encoded_cu_found_valid <= encoded_cu_found_valid_comb;
encoded_cu_id <= encoded_cu_id_comb;
encoded_wf_count <= anded_cam_wf_count;
encoded_cu_wg_id <= anded_cam_wg_id;
encoded_vgpr_size <= anded_cam_vgpr_size;
encoded_sgpr_size <= anded_cam_sgpr_size;
encoded_lds_size <= anded_cam_lds_size;
encoded_gds_size <= anded_cam_gds_size;
encoded_gds_strt <= anded_cam_gds_strt;
// Output the starts and the cu id
size_ram_valid <= encoded_cu_out_valid;
size_ram_cu_id_found <= encoded_cu_found_valid;
cu_id_out <= encoded_cu_id;
wg_id_out <= encoded_cu_wg_id;
wf_count_out <= encoded_wf_count;
vgpr_size_out <= encoded_vgpr_size;
sgpr_size_out <= encoded_sgpr_size;
lds_size_out <= encoded_lds_size;
gds_size_out <= encoded_gds_size;
gds_start_out <= encoded_gds_strt;
end // if (pipeline_waiting)
//////////////////////////////////
// Cam write
//////////////////////////////////
cam_up_valid_i <= grt_cam_up_valid;
cam_up_cu_id_i <= grt_cam_up_cu_id;
cam_up_vgpr_strt_i <= grt_cam_up_vgpr_strt;
cam_up_sgpr_strt_i <= grt_cam_up_sgpr_strt;
cam_up_lds_strt_i <= grt_cam_up_lds_strt;
cam_up_gds_strt_i <= grt_cam_up_gds_strt;
cam_up_wg_count_i <= grt_cam_up_wg_count;
if(cam_up_valid_i) begin
cu_initialized[cam_up_cu_id_i] <= 1'b1;
end
//////////////////////////////////
// Size ram write
//////////////////////////////////
cam_up_vgpr_size_i <= grt_cam_up_vgpr_size;
cam_up_sgpr_size_i <= grt_cam_up_sgpr_size;
cam_up_lds_size_i <= grt_cam_up_lds_size;
cam_up_gds_size_i <= grt_cam_up_gds_size;
if(cam_up_valid_i) begin
gds_free <= cam_up_gds_size_i;
gds_strt <= cam_up_gds_strt_i;
end
else if(alloc_valid_i && (gds_free >= alloc_gds_size_i) && !pipeline_waiting) begin
gds_free <= gds_free - alloc_gds_size_i;
gds_strt <= gds_strt + alloc_gds_size_i;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
assign allocator_cu_valid = size_ram_valid;
assign allocator_cu_rejected = ~size_ram_cu_id_found;
assign allocator_wg_id_out = wg_id_out;
assign allocator_cu_id_out = cu_id_out;
assign allocator_vgpr_size_out = vgpr_size_out;
assign allocator_sgpr_size_out = sgpr_size_out;
assign allocator_lds_size_out = lds_size_out;
assign allocator_gds_size_out = gds_size_out;
assign allocator_vgpr_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_VGPR_END:RES_SIZE_VGPR_START];
assign allocator_sgpr_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_SGPR_END:RES_SIZE_SGPR_START];
assign allocator_lds_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_LDS_END:RES_SIZE_LDS_START];
assign allocator_gds_start_out = (!cu_initialized[cu_id_out])? 0 :
gds_start_out;
assign allocator_wf_count = wf_count_out;
always @ ( /*AUTOSENSE*/anded_cam_out) begin : PRI_ENCODER_CAM_OUT
integer i;
reg found_valid;
found_valid = 1'b0;
encoded_cu_id_comb = 0;
for (i=0; i<NUMBER_CU; i = i+1) begin
if(~found_valid && anded_cam_out[i]) begin
found_valid = 1'b1;
encoded_cu_id_comb = i;
end
end
encoded_cu_found_valid_comb = found_valid;
end
endmodule // allocator
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_PP_SYMBOL_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2008 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Following defines conditionally include RX path circuitry
`include "../top/config.vh" // resolved relative to project root
module rx_chain_dig
(input clock,
input reset,
input enable,
input wire [15:0] i_in_ana,
input wire [15:0] q_in_ana,
input wire i_in_dig,
input wire q_in_dig,
output wire [15:0] i_out,
output wire [15:0] q_out
);
//assign upper 15 bits of output to analog input,
// discards lsb of analog input and replace with digital input bit (which comes from gpio)
assign i_out = (enable)?{i_in_ana[15:1],i_in_dig}:i_in_ana;
assign q_out = (enable)?{q_in_ana[15:1],q_in_dig}:q_in_ana;
endmodule // rx_chain_dig
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_qpll_reset.v
// Version : 1.7
//------------------------------------------------------------------------------
// Filename : qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Reset Module --------------------------------------------------
module pcie_7x_v1_8_qpll_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override
)
(
//---------- Input -------------------------------------
input QRST_CLK,
input QRST_RST_N,
input QRST_MMCM_LOCK,
input [PCIE_LANE-1:0] QRST_CPLLLOCK,
input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
input [ 1:0] QRST_RATE,
input [PCIE_LANE-1:0] QRST_QPLLRESET_IN,
input [PCIE_LANE-1:0] QRST_QPLLPD_IN,
//---------- Output ------------------------------------
output QRST_OVRD,
output QRST_DRP_START,
output QRST_QPLLRESET_OUT,
output QRST_QPLLPD_OUT,
output QRST_IDLE,
output [11:0] QRST_FSM
);
//---------- Input Register ----------------------------
reg mmcm_lock_reg1;
reg [PCIE_LANE-1:0] cplllock_reg1;
reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
reg [ 1:0] rate_reg1;
reg [PCIE_LANE-1:0] qpllreset_in_reg1;
reg [PCIE_LANE-1:0] qpllpd_in_reg1;
reg mmcm_lock_reg2;
reg [PCIE_LANE-1:0] cplllock_reg2;
reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
reg [ 1:0] rate_reg2;
reg [PCIE_LANE-1:0] qpllreset_in_reg2;
reg [PCIE_LANE-1:0] qpllpd_in_reg2;
//---------- Output Register --------------------------
reg ovrd = 1'd0;
reg qpllreset = 1'd1;
reg qpllpd = 1'd0;
reg [11:0] fsm = 12'd2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 12'b000000000001;
localparam FSM_WAIT_LOCK = 12'b000000000010;
localparam FSM_MMCM_LOCK = 12'b000000000100;
localparam FSM_DRP_START_NOM = 12'b000000001000;
localparam FSM_DRP_DONE_NOM = 12'b000000010000;
localparam FSM_QPLLLOCK = 12'b000000100000;
localparam FSM_DRP_START_OPT = 12'b000001000000;
localparam FSM_DRP_DONE_OPT = 12'b000010000000;
localparam FSM_QPLL_RESET = 12'b000100000000;
localparam FSM_QPLLLOCK2 = 12'b001000000000;
localparam FSM_QPLL_PDRESET = 12'b010000000000;
localparam FSM_QPLL_PD = 12'b100000000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= 1'd0;
cplllock_reg1 <= {PCIE_LANE{1'd1}};
drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg1 <= 2'd0;
qpllreset_in_reg1 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= 1'd0;
cplllock_reg2 <= {PCIE_LANE{1'd1}};
drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg2 <= 2'd0;
qpllreset_in_reg2 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= QRST_MMCM_LOCK;
cplllock_reg1 <= QRST_CPLLLOCK;
drp_done_reg1 <= QRST_DRP_DONE;
qplllock_reg1 <= QRST_QPLLLOCK;
rate_reg1 <= QRST_RATE;
qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
qpllpd_in_reg1 <= QRST_QPLLPD_IN;
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= mmcm_lock_reg1;
cplllock_reg2 <= cplllock_reg1;
drp_done_reg2 <= drp_done_reg1;
qplllock_reg2 <= qplllock_reg1;
rate_reg2 <= rate_reg1;
qpllreset_in_reg2 <= qpllreset_in_reg1;
qpllpd_in_reg2 <= qpllpd_in_reg1;
end
end
//---------- QPLL Reset FSM ----------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= &qpllreset_in_reg2;
qpllpd <= &qpllpd_in_reg2;
end
end
//---------- Wait for CPLL and QPLL to Lose Lock ---
FSM_WAIT_LOCK :
begin
fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for MMCM and CPLL Lock -----------
FSM_MMCM_LOCK :
begin
fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Normal QPLL Lock Mode
FSM_DRP_START_NOM:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_NOM :
begin
fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK :
begin
fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Optimized QPLL Lock Mode
FSM_DRP_START_OPT:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
ovrd <= 1'd1;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_OPT :
begin
if (&drp_done_reg2)
begin
fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= qpllpd;
end
else
begin
fsm <= FSM_DRP_DONE_OPT;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
end
//---------- Reset QPLL ----------------------------
FSM_QPLL_RESET :
begin
fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);
ovrd <= ovrd;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK2 :
begin
fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
//---------- Hold QPLL in Reset --------------------
FSM_QPLL_PDRESET :
begin
fsm <= FSM_QPLL_PD;
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
qpllpd <= qpllpd;
end
//---------- Power-down QPLL -----------------------
FSM_QPLL_PD :
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
endcase
end
end
//---------- QPLL Lock Output --------------------------------------------------
assign QRST_OVRD = ovrd;
assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT);
assign QRST_QPLLRESET_OUT = qpllreset;
assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign QRST_IDLE = (fsm == FSM_IDLE);
assign QRST_FSM = fsm;
endmodule
|
//======================================================================
//
// tb_chacha20_core.v
// ------------------
// Testbench for the Chacha stream cipher core. This TB verifies that
// the chacha20 core can be used as specified in RFC 7539. The
// big change is that the original core has 64 bit IV and 64 bit
// counter. In RFC 7539, the IV (called nonce in the RFC) is 96 bits
// and the counter is 32 bits. Also, in the RFC, the key is always
// 256 bits and uses 20 rounds. Testvectors are taken from the RFC.
//
//
// Copyright (c) 2016, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_chacha20_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter KEY_256_BITS = 1;
parameter TWENTY_ROUNDS = 20;
//----------------------------------------------------------------
// l2b()
//
// Swap bytes from little to big endian byte order.
//----------------------------------------------------------------
function [31 : 0] l2b(input [31 : 0] op);
begin
l2b = {op[7 : 0], op[15 : 8], op[23 : 16], op[31 : 24]};
end
endfunction // b2l
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_core_init;
reg tb_core_next;
reg [255 : 0] tb_core_key;
reg tb_core_keylen;
reg [4 : 0] tb_core_rounds;
reg [95 : 0] tb_core_nonce;
reg [31 : 0] tb_core_ctr;
wire tb_core_ready;
reg [0 : 511] tb_core_data_in;
wire [0 : 511] tb_core_data_out;
reg display_cycle_ctr;
reg display_ctrl_and_ctrs;
reg display_qround;
reg display_state;
reg display_x_state;
//----------------------------------------------------------------
// chacha_core device under test.
//
// Note that we instantiate with a l2b fix for the msb
// part of the counter.
//----------------------------------------------------------------
chacha_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.init(tb_core_init),
.next(tb_core_next),
.key(tb_core_key),
.keylen(tb_core_keylen),
.iv(tb_core_nonce[63 : 0]),
.ctr({l2b(tb_core_nonce[95 : 64]), tb_core_ctr}),
.rounds(tb_core_rounds),
.data_in(tb_core_data_in),
.ready(tb_core_ready),
.data_out(tb_core_data_out),
.data_out_valid(tb_core_data_out_valid)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor that displays different types of information
// every cycle depending on what flags test cases enable.
//
// The monitor includes a cycle counter for the testbench.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
dump_state();
// Display cycle counter.
if (display_cycle_ctr)
begin
$display("cycle = %08x:", cycle_ctr);
$display("");
end
end // dut_monitor
//----------------------------------------------------------------
// dump_state()
// Dump the internal CHACHA state to std out.
//----------------------------------------------------------------
task dump_state;
begin
$display("");
$display("Internal state:");
$display("---------------");
$display("State:");
$display("state00_reg = %08x state01_reg = %08x state02_reg = %08x state03_reg = %08x",
dut.state_reg[00], dut.state_reg[01], dut.state_reg[02], dut.state_reg[03]);
$display("state04_reg = %08x state05_reg = %08x state06_reg = %08x state07_reg = %08x",
dut.state_reg[04], dut.state_reg[05], dut.state_reg[06], dut.state_reg[07]);
$display("state08_reg = %08x state09_reg = %08x state10_reg = %08x state11_reg = %08x",
dut.state_reg[08], dut.state_reg[09], dut.state_reg[10], dut.state_reg[11]);
$display("state12_reg = %08x state13_reg = %08x state14_reg = %08x state15_reg = %08x",
dut.state_reg[12], dut.state_reg[13], dut.state_reg[14], dut.state_reg[15]);
$display("");
$display("rounds = %01x", dut.rounds);
$display("qr_ctr_reg = %01x, dr_ctr_reg = %01x", dut.qr_ctr_reg, dut.dr_ctr_reg);
$display("block0_ctr_reg = %08x, block1_ctr_reg = %08x", dut.block0_ctr_reg, dut.block1_ctr_reg);
$display("");
$display("chacha_ctrl_reg = %02x", dut.chacha_ctrl_reg);
$display("");
$display("data_in[255 : 192] = %016x", dut.data_in[255 : 192]);
$display("data_in[191 : 128] = %016x", dut.data_in[191 : 128]);
$display("data_in[127 : 064] = %016x", dut.data_in[127 : 064]);
$display("data_in[063 : 000] = %016x", dut.data_in[063 : 000]);
$display("data_out_valid_reg = %01x", dut.data_out_valid_reg);
$display("data_out = %064x", dut.data_out);
$display("");
end
endtask // dump_state
//----------------------------------------------------------------
// dump_inout()
// Dump the status for input and output ports.
//----------------------------------------------------------------
task dump_inout;
begin
$display("");
$display("State for input and output ports:");
$display("---------------------------------");
$display("init = %01x", dut.init);
$display("next = %01x", dut.next);
$display("keylen = %01x", dut.keylen);
$display("");
$display("key = %032x", dut.key);
$display("iv = %016x", dut.iv);
$display("");
$display("ready = %01x", dut.ready);
$display("data_in = %064x", dut.data_in);
$display("data_out = %064x", dut.data_out);
$display("data_out_valid = %01x", dut.data_out_valid);
$display("");
end
endtask // dump_inout
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
error_ctr = 0;
tb_core_init = 0;
tb_core_next = 0;
tb_core_key = 0;
tb_core_keylen = 0;
tb_core_nonce = 96'h0;
tb_core_ctr = 32'h0;
tb_core_rounds = 0;
tb_core_data_in = 512'h0;
end
endtask // init_dut
//----------------------------------------------------------------
// wait_ready
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_core_ready)
begin
#(1 * CLK_PERIOD);
end
$display("*** Ready seen.");
end
endtask // wait_ready
//----------------------------------------------------------------
// block_test
//
// Test that the initialization and block processing in the
// chacha core conforms to the specification in RFC 7539,
// chapter 2.3.2.
//----------------------------------------------------------------
task block_test;
begin : btest
reg test_error;
test_error = 0;
tc_ctr = tc_ctr + 1;
$display("*** Block Function Test (RFC 7539, ch 2.3.2:");
tb_core_rounds = TWENTY_ROUNDS;
tb_core_key = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
tb_core_keylen = KEY_256_BITS;
tb_core_nonce = 96'h000000090000004a00000000;
tb_core_ctr = 32'h00000001;
$display("*** Starting init of the cipher.");
tb_core_init = 1;
#(CLK_PERIOD);
tb_core_init = 0;
#(CLK_PERIOD);
dump_state();
dump_inout();
// Check if state is initialized correctly.
if (dut.state_reg[00] != 32'h61707865)
test_error = 1;
if (dut.state_reg[01] != 32'h3320646e)
test_error = 1;
if (dut.state_reg[02] != 32'h79622d32)
test_error = 1;
if (dut.state_reg[03] != 32'h6b206574)
test_error = 1;
if (dut.state_reg[04] != 32'h03020100)
test_error = 1;
if (dut.state_reg[05] != 32'h07060504)
test_error = 1;
if (dut.state_reg[06] != 32'h0b0a0908)
test_error = 1;
if (dut.state_reg[07] != 32'h0f0e0d0c)
test_error = 1;
if (dut.state_reg[08] != 32'h13121110)
test_error = 1;
if (dut.state_reg[09] != 32'h17161514)
test_error = 1;
if (dut.state_reg[10] != 32'h1b1a1918)
test_error = 1;
if (dut.state_reg[11] != 32'h1f1e1d1c)
test_error = 1;
if (dut.state_reg[12] != 32'h00000001)
test_error = 1;
if (dut.state_reg[13] != 32'h09000000)
test_error = 1;
if (dut.state_reg[14] != 32'h4a000000)
test_error = 1;
if (dut.state_reg[15] != 32'h00000000)
test_error = 1;
if (test_error)
$display("*** State after init is not correct.");
else
$display("*** State after init correct.");
$display("*** Waiting for end of processing first block.");
wait_ready();
dump_state();
end
endtask // block_test
//----------------------------------------------------------------
// chacha20_core_test
//----------------------------------------------------------------
initial
begin : chacha20_core_test
$display(" -- Testbench for chacha20 core started --");
$display("");
init_dut();
$display("*** State at init:");
dump_state();
reset_dut();
$display("*** State after reset:");
dump_state();
block_test();
$display("*** chacha_core simulation done ***");
display_test_result();
$finish;
end // chacha20_core_test
endmodule // tb_chacha20_core
//======================================================================
// EOF tb_chacha20_core.v
//======================================================================
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_ddrx_encoder_40.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Internal Build 157 07/06/2009 PN Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder CBX_AUTO_BLACKBOX="ALL" device_family="Stratix" lpm_pipeline=1 width_codeword=39 width_dataword=32 clock data q
//VERSION_BEGIN 9.1 cbx_altecc_encoder 2009:06:09:13:39:47:PN cbx_mgl 2009:07:03:02:47:54:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lut 39
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_ddrx_encoder_40_altecc_encoder_plb
(
clock,
data,
q) ;
input clock;
input [31:0] data;
output [38:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [38:0] output_pipeline0c;
wire aclr;
wire clocken;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final_wire;
wire [38:0] q_wire;
// synopsys translate_off
initial
output_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) output_pipeline0c <= 39'b0;
else if (clocken == 1'b1) output_pipeline0c <= q_wire;
assign
aclr = 1'b0,
clocken = 1'b1,
data_wire = data,
parity_01_wire = {(data_wire[30] ^ parity_01_wire[16]), (data_wire[28] ^ parity_01_wire[15]), (data_wire[26] ^ parity_01_wire[14]), (data_wire[25] ^ parity_01_wire[13]), (data_wire[23] ^ parity_01_wire[12]), (data_wire[21] ^ parity_01_wire[11]), (data_wire[19] ^ parity_01_wire[10]), (data_wire[17] ^ parity_01_wire[9]), (data_wire[15] ^ parity_01_wire[8]), (data_wire[13] ^ parity_01_wire[7]), (data_wire[11] ^ parity_01_wire[6]), (data_wire[10] ^ parity_01_wire[5]), (data_wire[8] ^ parity_01_wire[4]), (data_wire[6] ^ parity_01_wire[3]), (data_wire[4] ^ parity_01_wire[2]), (data_wire[3] ^ parity_01_wire[1]), (data_wire[1] ^ parity_01_wire[0]), data_wire[0]},
parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), data_wire[0]},
parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), ((data_wire[1] ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), data_wire[26]},
parity_final_wire = {(q_wire[37] ^ parity_final_wire[36]), (q_wire[36] ^ parity_final_wire[35]), (q_wire[35] ^ parity_final_wire[34]), (q_wire[34] ^ parity_final_wire[33]), (q_wire[33] ^ parity_final_wire[32]), (q_wire[32] ^ parity_final_wire[31]), (q_wire[31] ^ parity_final_wire[30]), (q_wire[30] ^ parity_final_wire[29]), (q_wire[29] ^ parity_final_wire[28]), (q_wire[28] ^ parity_final_wire[27]), (q_wire[27] ^ parity_final_wire[26]), (q_wire[26] ^ parity_final_wire[25]), (q_wire[25] ^ parity_final_wire[24]), (q_wire[24] ^ parity_final_wire[23]), (q_wire[23] ^ parity_final_wire[22]), (q_wire[22] ^ parity_final_wire[21]), (q_wire[21] ^ parity_final_wire[20]), (q_wire[20] ^ parity_final_wire[19]), (q_wire[19] ^ parity_final_wire[18]), (q_wire[18] ^ parity_final_wire[17]), (q_wire[17] ^ parity_final_wire[16]), (q_wire[16] ^ parity_final_wire[15]), (q_wire[15] ^ parity_final_wire[14]), (q_wire[14] ^ parity_final_wire[13]), (q_wire[13] ^ parity_final_wire[12]), (q_wire[12] ^ parity_final_wire[11]), (q_wire[11] ^ parity_final_wire[10]), (q_wire[10] ^ parity_final_wire[9]), (q_wire[9] ^ parity_final_wire[8]), (q_wire[8] ^ parity_final_wire[7]), (q_wire[7] ^ parity_final_wire[6]), (q_wire[6] ^ parity_final_wire[5]), (q_wire[5] ^ parity_final_wire[4]), (q_wire[4] ^ parity_final_wire[3]), (q_wire[3] ^ parity_final_wire[2]), (q_wire[2] ^ parity_final_wire[1]), (q_wire[1] ^ parity_final_wire[0]), q_wire[0]},
q = output_pipeline0c,
q_wire = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
endmodule //alt_ddrx_encoder_40_altecc_encoder_plb
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_ddrx_encoder_40 (
clock,
data,
q);
input clock;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_ddrx_encoder_40_altecc_encoder_plb alt_ddrx_encoder_40_altecc_encoder_plb_component (
.clock (clock),
.data (data),
.q (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "1"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40_bb.v FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND4_BEHAVIORAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_BEHAVIORAL_V |
// A few simple tests of translating parameters to generics
module top();
wire [7:0] v1, v2, v3;
wire [7:0] w1, w2, w3;
child c1(v1, w1);
child c2(v2, w2);
child c3(v3, w3);
defparam c1.MY_VALUE = 6;
defparam c2.MY_VALUE = 44;
initial begin
#2;
$display("c1 reg value: %d", v1);
$display("c2 reg value: %d", v2);
$display("c3 reg value: %d", v3);
$display("c1 wire value: %d", w1);
$display("c2 wire value: %d", w2);
$display("c3 wire value: %d", w3);
if (v1 !== 6)
$display("FAILED - v1 !== 6");
else if (v2 !== 44)
$display("FAILED - v2 !== 44");
else if (v3 !== 12)
$display("FAILED - v3 !== 12");
else if (w1 !== 7)
$display("FAILED - v1 !== 7");
else if (w2 !== 45)
$display("FAILED - v2 !== 45");
else if (w3 !== 13)
$display("FAILED - v3 !== 13");
else
$display("PASSED");
end
endmodule // top
module child(value, value_w);
output [7:0] value, value_w;
reg [7:0] value;
parameter MY_VALUE = 12;
assign value_w = MY_VALUE + 1;
// Make a non-trivial process
initial begin
#1;
value <= MY_VALUE;
end
endmodule // child
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_8x16_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_8x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [7:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [7:0] q = sub_wire3[7:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module altera_mem_if_hhp_qseq_synth_top
# ( parameter
APB_DATA_WIDTH = 32,
APB_ADDR_WIDTH = 32,
AVL_DATA_WIDTH = 32,
AVL_ADDR_WIDTH = 16, // for PHY
AVL_MMR_DATA_WIDTH = 32,
AVL_MMR_ADDR_WIDTH = 8,
MEM_IF_DQS_WIDTH = 1,
MEM_IF_DQ_WIDTH = 8,
MEM_IF_DM_WIDTH = 1,
MEM_IF_CS_WIDTH = 1
) (
);
endmodule
|
`timescale 1 ns / 1 ps
module gclk_generator_v1_0 #
(
// Users to add parameters here
parameter integer C_COUNTER_WIDTH = 16,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXI
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire clk_for_gclk,
output wire [2:0] gclk,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXI
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_awaddr,
input wire [2 : 0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_wdata,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [1 : 0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_araddr,
input wire [2 : 0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_rdata,
output wire [1 : 0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready
);
// Instantiation of Axi Bus Interface S_AXI
gclk_generator_v1_0_S_AXI # (
.C_COUNTER_WIDTH(C_COUNTER_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH)
) gclk_generator_v1_0_S_AXI_inst (
.clk_for_gclk(clk_for_gclk),
.gclk(gclk),
.S_AXI_ACLK(s_axi_aclk),
.S_AXI_ARESETN(s_axi_aresetn),
.S_AXI_AWADDR(s_axi_awaddr),
.S_AXI_AWPROT(s_axi_awprot),
.S_AXI_AWVALID(s_axi_awvalid),
.S_AXI_AWREADY(s_axi_awready),
.S_AXI_WDATA(s_axi_wdata),
.S_AXI_WSTRB(s_axi_wstrb),
.S_AXI_WVALID(s_axi_wvalid),
.S_AXI_WREADY(s_axi_wready),
.S_AXI_BRESP(s_axi_bresp),
.S_AXI_BVALID(s_axi_bvalid),
.S_AXI_BREADY(s_axi_bready),
.S_AXI_ARADDR(s_axi_araddr),
.S_AXI_ARPROT(s_axi_arprot),
.S_AXI_ARVALID(s_axi_arvalid),
.S_AXI_ARREADY(s_axi_arready),
.S_AXI_RDATA(s_axi_rdata),
.S_AXI_RRESP(s_axi_rresp),
.S_AXI_RVALID(s_axi_rvalid),
.S_AXI_RREADY(s_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer i;
reg [63:0] b;
real r, r2;
integer cyc=0;
realtime uninit;
initial if (uninit != 0.0) $stop;
sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
initial begin
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_cast_bug374(input clk, input [4:0] cyc5);
integer i;
always @(posedge clk) begin
i <= integer'(cyc5);
end
endmodule
|
module mask_gen(in,out);
input [5:0]in;
output [63:0]out;
assign out = (in == 6'd0) ? 64'h0000000000000001:
(in == 6'd1) ? 64'h0000000000000003:
(in == 6'd2) ? 64'h0000000000000007:
(in == 6'd3) ? 64'h000000000000000f:
(in == 6'd4) ? 64'h000000000000001f:
(in == 6'd5) ? 64'h000000000000003f:
(in == 6'd6) ? 64'h000000000000007f:
(in == 6'd7) ? 64'h00000000000000ff:
(in == 6'd8) ? 64'h00000000000001ff:
(in == 6'd9) ? 64'h00000000000003ff:
(in == 6'd10) ? 64'h00000000000007ff:
(in == 6'd11) ? 64'h0000000000000fff:
(in == 6'd12) ? 64'h0000000000001fff:
(in == 6'd13) ? 64'h0000000000003fff:
(in == 6'd14) ? 64'h0000000000007fff:
(in == 6'd15) ? 64'h000000000000ffff:
(in == 6'd16) ? 64'h000000000001ffff:
(in == 6'd17) ? 64'h000000000003ffff:
(in == 6'd18) ? 64'h000000000007ffff:
(in == 6'd19) ? 64'h00000000000fffff:
(in == 6'd20) ? 64'h00000000001fffff:
(in == 6'd21) ? 64'h00000000003fffff:
(in == 6'd22) ? 64'h00000000007fffff:
(in == 6'd23) ? 64'h0000000000ffffff:
(in == 6'd24) ? 64'h0000000001ffffff:
(in == 6'd25) ? 64'h0000000003ffffff:
(in == 6'd26) ? 64'h0000000007ffffff:
(in == 6'd27) ? 64'h000000000fffffff:
(in == 6'd28) ? 64'h000000001fffffff:
(in == 6'd29) ? 64'h000000003fffffff:
(in == 6'd30) ? 64'h000000007fffffff:
(in == 6'd31) ? 64'h00000000ffffffff:
(in == 6'd32) ? 64'h00000001ffffffff:
(in == 6'd33) ? 64'h00000003ffffffff:
(in == 6'd34) ? 64'h00000007ffffffff:
(in == 6'd35) ? 64'h0000000fffffffff:
(in == 6'd36) ? 64'h0000001fffffffff:
(in == 6'd37) ? 64'h0000003fffffffff:
(in == 6'd38) ? 64'h0000007fffffffff:
(in == 6'd39) ? 64'h000000ffffffffff:
(in == 6'd40) ? 64'h000001ffffffffff:
(in == 6'd41) ? 64'h000003ffffffffff:
(in == 6'd42) ? 64'h000007ffffffffff:
(in == 6'd43) ? 64'h00000fffffffffff:
(in == 6'd44) ? 64'h00001fffffffffff:
(in == 6'd45) ? 64'h00003fffffffffff:
(in == 6'd46) ? 64'h00007fffffffffff:
(in == 6'd47) ? 64'h0000ffffffffffff:
(in == 6'd48) ? 64'h0001ffffffffffff:
(in == 6'd49) ? 64'h0003ffffffffffff:
(in == 6'd50) ? 64'h0007ffffffffffff:
(in == 6'd51) ? 64'h000fffffffffffff:
(in == 6'd52) ? 64'h001fffffffffffff:
(in == 6'd53) ? 64'h003fffffffffffff:
(in == 6'd54) ? 64'h007fffffffffffff:
(in == 6'd55) ? 64'h00ffffffffffffff:
(in == 6'd56) ? 64'h01ffffffffffffff:
(in == 6'd57) ? 64'h03ffffffffffffff:
(in == 6'd58) ? 64'h07ffffffffffffff:
(in == 6'd59) ? 64'h0fffffffffffffff:
(in == 6'd60) ? 64'h1fffffffffffffff:
(in == 6'd61) ? 64'h3fffffffffffffff:
(in == 6'd62) ? 64'h7fffffffffffffff:
(in == 6'd63) ? 64'hffffffffffffffff:
64'd0;
endmodule |
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFBBN_PP_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_PP_BLACKBOX_V
|
// DUT based on oh/elink/dv/dut_axi_elink.v
//
`include "elink_regmap.vh"
module dut(/*AUTOARG*/
// Outputs
clkout, dut_active, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter S2_IDW = 12;
parameter M_IDW = 6;
parameter M2_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
parameter RETURN_ADDR = {ID,
`EGROUP_RR,
16'b0}; // axi return addr
//clock,reset
input clk1;
input clk2;
output clkout;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink0_cclk_n; // From elink0 of axi_elink.v
wire elink0_cclk_p; // From elink0 of axi_elink.v
wire elink0_chip_nreset; // From elink0 of axi_elink.v
wire [11:0] elink0_chipid; // From elink0 of axi_elink.v
wire [31:0] elink0_m_axi_araddr; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_arburst; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_arcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_arid; // From elink0 of axi_elink.v
wire [7:0] elink0_m_axi_arlen; // From elink0 of axi_elink.v
wire elink0_m_axi_arlock; // From elink0 of axi_elink.v
wire [2:0] elink0_m_axi_arprot; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_arqos; // From elink0 of axi_elink.v
wire elink0_m_axi_arready; // From axislave_stub of axislave_stub.v
wire [2:0] elink0_m_axi_arsize; // From elink0 of axi_elink.v
wire elink0_m_axi_arvalid; // From elink0 of axi_elink.v
wire [31:0] elink0_m_axi_awaddr; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_awburst; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_awcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_awid; // From elink0 of axi_elink.v
wire [7:0] elink0_m_axi_awlen; // From elink0 of axi_elink.v
wire elink0_m_axi_awlock; // From elink0 of axi_elink.v
wire [2:0] elink0_m_axi_awprot; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_awqos; // From elink0 of axi_elink.v
wire elink0_m_axi_awready; // From axislave_stub of axislave_stub.v
wire [2:0] elink0_m_axi_awsize; // From elink0 of axi_elink.v
wire elink0_m_axi_awvalid; // From elink0 of axi_elink.v
wire [S_IDW-1:0] elink0_m_axi_bid; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_bready; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_bresp; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_bvalid; // From axislave_stub of axislave_stub.v
wire [31:0] elink0_m_axi_rdata; // From axislave_stub of axislave_stub.v
wire [S_IDW-1:0] elink0_m_axi_rid; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rlast; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rready; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_rresp; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rvalid; // From axislave_stub of axislave_stub.v
wire [63:0] elink0_m_axi_wdata; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_wid; // From elink0 of axi_elink.v
wire elink0_m_axi_wlast; // From elink0 of axi_elink.v
wire elink0_m_axi_wready; // From axislave_stub of axislave_stub.v
wire [7:0] elink0_m_axi_wstrb; // From elink0 of axi_elink.v
wire elink0_m_axi_wvalid; // From elink0 of axi_elink.v
wire elink0_mailbox_irq; // From elink0 of axi_elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of axi_elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of axi_elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of axi_elink.v
wire elink0_rxo_wr_wait_p; // From elink0 of axi_elink.v
wire [7:0] elink0_txo_data_n; // From elink0 of axi_elink.v
wire [7:0] elink0_txo_data_p; // From elink0 of axi_elink.v
wire elink0_txo_frame_n; // From elink0 of axi_elink.v
wire elink0_txo_frame_p; // From elink0 of axi_elink.v
wire elink0_txo_lclk_n; // From elink0 of axi_elink.v
wire elink0_txo_lclk_p; // From elink0 of axi_elink.v
wire elink1_cclk_n; // From elink1 of axi_elink.v
wire elink1_cclk_p; // From elink1 of axi_elink.v
wire elink1_chip_nreset; // From elink1 of axi_elink.v
wire [11:0] elink1_chipid; // From elink1 of axi_elink.v
wire elink1_elink_active; // From elink1 of axi_elink.v
wire elink1_mailbox_irq; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_p; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_p; // From elink1 of axi_elink.v
wire [7:0] elink1_txo_data_n; // From elink1 of axi_elink.v
wire [7:0] elink1_txo_data_p; // From elink1 of axi_elink.v
wire elink1_txo_frame_n; // From elink1 of axi_elink.v
wire elink1_txo_frame_p; // From elink1 of axi_elink.v
wire elink1_txo_lclk_n; // From elink1 of axi_elink.v
wire elink1_txo_lclk_p; // From elink1 of axi_elink.v
wire [31:0] ext1_m_axi_araddr; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_arburst; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_arcache; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_arid; // From emaxi1 of emaxi.v
wire [7:0] ext1_m_axi_arlen; // From emaxi1 of emaxi.v
wire ext1_m_axi_arlock; // From emaxi1 of emaxi.v
wire [2:0] ext1_m_axi_arprot; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_arqos; // From emaxi1 of emaxi.v
wire ext1_m_axi_arready; // From elink1 of axi_elink.v
wire [2:0] ext1_m_axi_arsize; // From emaxi1 of emaxi.v
wire ext1_m_axi_arvalid; // From emaxi1 of emaxi.v
wire [31:0] ext1_m_axi_awaddr; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_awburst; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_awcache; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_awid; // From emaxi1 of emaxi.v
wire [7:0] ext1_m_axi_awlen; // From emaxi1 of emaxi.v
wire ext1_m_axi_awlock; // From emaxi1 of emaxi.v
wire [2:0] ext1_m_axi_awprot; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_awqos; // From emaxi1 of emaxi.v
wire ext1_m_axi_awready; // From elink1 of axi_elink.v
wire [2:0] ext1_m_axi_awsize; // From emaxi1 of emaxi.v
wire ext1_m_axi_awvalid; // From emaxi1 of emaxi.v
wire [S_IDW-1:0] ext1_m_axi_bid; // From elink1 of axi_elink.v
wire ext1_m_axi_bready; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_bresp; // From elink1 of axi_elink.v
wire ext1_m_axi_bvalid; // From elink1 of axi_elink.v
wire [31:0] ext1_m_axi_rdata; // From elink1 of axi_elink.v
wire [S_IDW-1:0] ext1_m_axi_rid; // From elink1 of axi_elink.v
wire ext1_m_axi_rlast; // From elink1 of axi_elink.v
wire ext1_m_axi_rready; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_rresp; // From elink1 of axi_elink.v
wire ext1_m_axi_rvalid; // From elink1 of axi_elink.v
wire [63:0] ext1_m_axi_wdata; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_wid; // From emaxi1 of emaxi.v
wire ext1_m_axi_wlast; // From emaxi1 of emaxi.v
wire ext1_m_axi_wready; // From elink1 of axi_elink.v
wire [7:0] ext1_m_axi_wstrb; // From emaxi1 of emaxi.v
wire ext1_m_axi_wvalid; // From emaxi1 of emaxi.v
wire [31:0] m_axi_araddr; // From emaxi0 of emaxi.v
wire [1:0] m_axi_arburst; // From emaxi0 of emaxi.v
wire [3:0] m_axi_arcache; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_arid; // From emaxi0 of emaxi.v
wire [7:0] m_axi_arlen; // From emaxi0 of emaxi.v
wire m_axi_arlock; // From emaxi0 of emaxi.v
wire [2:0] m_axi_arprot; // From emaxi0 of emaxi.v
wire [3:0] m_axi_arqos; // From emaxi0 of emaxi.v
wire m_axi_arready; // From elink0 of axi_elink.v
wire [2:0] m_axi_arsize; // From emaxi0 of emaxi.v
wire m_axi_arvalid; // From emaxi0 of emaxi.v
wire [31:0] m_axi_awaddr; // From emaxi0 of emaxi.v
wire [1:0] m_axi_awburst; // From emaxi0 of emaxi.v
wire [3:0] m_axi_awcache; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_awid; // From emaxi0 of emaxi.v
wire [7:0] m_axi_awlen; // From emaxi0 of emaxi.v
wire m_axi_awlock; // From emaxi0 of emaxi.v
wire [2:0] m_axi_awprot; // From emaxi0 of emaxi.v
wire [3:0] m_axi_awqos; // From emaxi0 of emaxi.v
wire m_axi_awready; // From elink0 of axi_elink.v
wire [2:0] m_axi_awsize; // From emaxi0 of emaxi.v
wire m_axi_awvalid; // From emaxi0 of emaxi.v
wire [S_IDW-1:0] m_axi_bid; // From elink0 of axi_elink.v
wire m_axi_bready; // From emaxi0 of emaxi.v
wire [1:0] m_axi_bresp; // From elink0 of axi_elink.v
wire m_axi_bvalid; // From elink0 of axi_elink.v
wire [31:0] m_axi_rdata; // From elink0 of axi_elink.v
wire [S_IDW-1:0] m_axi_rid; // From elink0 of axi_elink.v
wire m_axi_rlast; // From elink0 of axi_elink.v
wire m_axi_rready; // From emaxi0 of emaxi.v
wire [1:0] m_axi_rresp; // From elink0 of axi_elink.v
wire m_axi_rvalid; // From elink0 of axi_elink.v
wire [63:0] m_axi_wdata; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_wid; // From emaxi0 of emaxi.v
wire m_axi_wlast; // From emaxi0 of emaxi.v
wire m_axi_wready; // From elink0 of axi_elink.v
wire [7:0] m_axi_wstrb; // From emaxi0 of emaxi.v
wire m_axi_wvalid; // From emaxi0 of emaxi.v
wire [31:0] mem_m_axi_araddr; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_arburst; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_arcache; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_arid; // From elink1 of axi_elink.v
wire [7:0] mem_m_axi_arlen; // From elink1 of axi_elink.v
wire mem_m_axi_arlock; // From elink1 of axi_elink.v
wire [2:0] mem_m_axi_arprot; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_arqos; // From elink1 of axi_elink.v
wire mem_m_axi_arready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_arsize; // From elink1 of axi_elink.v
wire mem_m_axi_arvalid; // From elink1 of axi_elink.v
wire [31:0] mem_m_axi_awaddr; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_awburst; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_awcache; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_awid; // From elink1 of axi_elink.v
wire [7:0] mem_m_axi_awlen; // From elink1 of axi_elink.v
wire mem_m_axi_awlock; // From elink1 of axi_elink.v
wire [2:0] mem_m_axi_awprot; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_awqos; // From elink1 of axi_elink.v
wire mem_m_axi_awready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_awsize; // From elink1 of axi_elink.v
wire mem_m_axi_awvalid; // From elink1 of axi_elink.v
wire [S_IDW-1:0] mem_m_axi_bid; // From esaxi of esaxi.v
wire mem_m_axi_bready; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_bresp; // From esaxi of esaxi.v
wire mem_m_axi_bvalid; // From esaxi of esaxi.v
wire [31:0] mem_m_axi_rdata; // From esaxi of esaxi.v
wire [S_IDW-1:0] mem_m_axi_rid; // From esaxi of esaxi.v
wire mem_m_axi_rlast; // From esaxi of esaxi.v
wire mem_m_axi_rready; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_rresp; // From esaxi of esaxi.v
wire mem_m_axi_rvalid; // From esaxi of esaxi.v
wire [63:0] mem_m_axi_wdata; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_wid; // From elink1 of axi_elink.v
wire mem_m_axi_wlast; // From elink1 of axi_elink.v
wire mem_m_axi_wready; // From esaxi of esaxi.v
wire [7:0] mem_m_axi_wstrb; // From elink1 of axi_elink.v
wire mem_m_axi_wvalid; // From elink1 of axi_elink.v
wire mem_rd_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_rd_packet; // From esaxi of esaxi.v
wire mem_rr_access; // From ememory of ememory.v
wire [PW-1:0] mem_rr_packet; // From ememory of ememory.v
wire mem_rr_wait; // From esaxi of esaxi.v
wire mem_wait; // From ememory of ememory.v
wire mem_wr_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_wr_packet; // From esaxi of esaxi.v
wire rd_wait0; // From emaxi0 of emaxi.v
wire rd_wait1; // From emaxi1 of emaxi.v
wire rr_access; // From emaxi1 of emaxi.v
wire [PW-1:0] rr_packet; // From emaxi1 of emaxi.v
wire wr_wait0; // From emaxi0 of emaxi.v
wire wr_wait1; // From emaxi1 of emaxi.v
// End of automatics
//###################
// GLUE
//###################
assign clkout = clk1;
// Provide an easy way to send mailbox messages to elink0 via the 0x910 address
wire elink0_access_in;
wire elink1_access_in;
wire ext1_write_in;
wire ext1_read_in;
assign elink0_access_in = access_in &
(packet_in[39:28]==12'h810 |
packet_in[39:28]==12'h808 |
packet_in[39:28]==12'h920);
assign elink1_access_in = access_in &
(packet_in[39:28]==12'h820 |
packet_in[39:28]==12'h910);
assign ext1_write_in = elink1_access_in & packet_in[0];
assign ext1_read_in = elink1_access_in & ~packet_in[0];
//######################################################################
//AXI MASTER
//######################################################################
wire write_in;
wire read_in;
//Split stimulus to read/write
assign wait_out = wr_wait0 | rd_wait0 | wr_wait1 | rd_wait1;
assign write_in = elink0_access_in & packet_in[0];
assign read_in = elink0_access_in & ~packet_in[0];
//######################################################################
//AXI MASTER (DRIVES STIMULUS) to configure elink0
//######################################################################
/*emaxi AUTO_TEMPLATE (//Stimulus
.m_axi_aresetn (nreset),
.m_axi_aclk (clk1),
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}),
.m_\(.*\) (m_\1[]),
.rr_wait (wait_in),
.rr_access (access_out),
.rr_packet (packet_out[PW-1:0]),
.wr_access (write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_access (read_in),
.rd_packet (packet_in[PW-1:0]),
.wr_wait (wr_wait0),
.rd_wait (rd_wait0),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi0 (/*AUTOINST*/
// Outputs
.wr_wait (wr_wait0), // Templated
.rd_wait (rd_wait0), // Templated
.rr_access (access_out), // Templated
.rr_packet (packet_out[PW-1:0]), // Templated
.m_axi_awid (m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (m_axi_awlen[7:0]), // Templated
.m_axi_awsize (m_axi_awsize[2:0]), // Templated
.m_axi_awburst (m_axi_awburst[1:0]), // Templated
.m_axi_awlock (m_axi_awlock), // Templated
.m_axi_awcache (m_axi_awcache[3:0]), // Templated
.m_axi_awprot (m_axi_awprot[2:0]), // Templated
.m_axi_awqos (m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (m_axi_awvalid), // Templated
.m_axi_wid (m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (m_axi_wlast), // Templated
.m_axi_wvalid (m_axi_wvalid), // Templated
.m_axi_bready (m_axi_bready), // Templated
.m_axi_arid (m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (m_axi_araddr[31:0]), // Templated
.m_axi_arlen (m_axi_arlen[7:0]), // Templated
.m_axi_arsize (m_axi_arsize[2:0]), // Templated
.m_axi_arburst (m_axi_arburst[1:0]), // Templated
.m_axi_arlock (m_axi_arlock), // Templated
.m_axi_arcache (m_axi_arcache[3:0]), // Templated
.m_axi_arprot (m_axi_arprot[2:0]), // Templated
.m_axi_arqos (m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (m_axi_arvalid), // Templated
.m_axi_rready (m_axi_rready), // Templated
// Inputs
.wr_access (write_in), // Templated
.wr_packet (packet_in[PW-1:0]), // Templated
.rd_access (read_in), // Templated
.rd_packet (packet_in[PW-1:0]), // Templated
.rr_wait (wait_in), // Templated
.m_axi_aclk (clk1), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (m_axi_awready), // Templated
.m_axi_wready (m_axi_wready), // Templated
.m_axi_bid (m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (m_axi_bvalid), // Templated
.m_axi_arready (m_axi_arready), // Templated
.m_axi_rid (m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}), // Templated
.m_axi_rresp (m_axi_rresp[1:0]), // Templated
.m_axi_rlast (m_axi_rlast), // Templated
.m_axi_rvalid (m_axi_rvalid)); // Templated
//######################################################################
//ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.s_\(.*\) (m_\1[]),
.sys_clk (clk1),
.rxi_\(.*\) (elink1_txo_\1[]),
.txi_\(.*\) (elink1_rxo_\1[]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
axi_elink #(.ID(12'h810),
.ETYPE(0))
elink0 (.elink_active (dut_active),
.s_axi_wstrb ((m_axi_wstrb[3:0] | m_axi_wstrb[7:4])),//NOTE:HACK!!
.m_axi_rdata ({mem_m_axi_rdata[31:0],mem_m_axi_rdata[31:0]}),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink0_txo_lclk_p), // Templated
.txo_lclk_n (elink0_txo_lclk_n), // Templated
.txo_frame_p (elink0_txo_frame_p), // Templated
.txo_frame_n (elink0_txo_frame_n), // Templated
.txo_data_p (elink0_txo_data_p[7:0]), // Templated
.txo_data_n (elink0_txo_data_n[7:0]), // Templated
.chipid (elink0_chipid[11:0]), // Templated
.chip_nreset (elink0_chip_nreset), // Templated
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.mailbox_irq (elink0_mailbox_irq), // Templated
.m_axi_awid (elink0_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (elink0_m_axi_awlock), // Templated
.m_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (elink0_m_axi_awvalid), // Templated
.m_axi_wid (elink0_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (elink0_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (elink0_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (elink0_m_axi_wlast), // Templated
.m_axi_wvalid (elink0_m_axi_wvalid), // Templated
.m_axi_bready (elink0_m_axi_bready), // Templated
.m_axi_arid (elink0_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (elink0_m_axi_arlock), // Templated
.m_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (elink0_m_axi_arvalid), // Templated
.m_axi_rready (elink0_m_axi_rready), // Templated
.s_axi_arready (m_axi_arready), // Templated
.s_axi_awready (m_axi_awready), // Templated
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (m_axi_bvalid), // Templated
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
.s_axi_rlast (m_axi_rlast), // Templated
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_wready (m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (elink1_txo_lclk_p), // Templated
.rxi_lclk_n (elink1_txo_lclk_n), // Templated
.rxi_frame_p (elink1_txo_frame_p), // Templated
.rxi_frame_n (elink1_txo_frame_n), // Templated
.rxi_data_p (elink1_txo_data_p[7:0]), // Templated
.rxi_data_n (elink1_txo_data_n[7:0]), // Templated
.txi_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (elink0_m_axi_awready), // Templated
.m_axi_wready (elink0_m_axi_wready), // Templated
.m_axi_bid (elink0_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (elink0_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (elink0_m_axi_bvalid), // Templated
.m_axi_arready (elink0_m_axi_arready), // Templated
.m_axi_rid (elink0_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rresp (elink0_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (elink0_m_axi_rlast), // Templated
.m_axi_rvalid (elink0_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
.s_axi_arlock (m_axi_arlock), // Templated
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (m_axi_arvalid), // Templated
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
.s_axi_awlock (m_axi_awlock), // Templated
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (m_axi_awvalid), // Templated
.s_axi_bready (m_axi_bready), // Templated
.s_axi_rready (m_axi_rready), // Templated
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
.s_axi_wlast (m_axi_wlast), // Templated
.s_axi_wvalid (m_axi_wvalid)); // Templated
//######################################################################
//TIE OFF UNUSED MASTER PORT ON ELINK0
//######################################################################
/*axislave_stub AUTO_TEMPLATE (
// Outputs
.s_\(.*\) (elink0_m_\1[]),
);
*/
defparam axislave_stub.S_IDW = S_IDW;
axislave_stub axislave_stub (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
/*AUTOINST*/
// Outputs
.s_axi_arready (elink0_m_axi_arready), // Templated
.s_axi_awready (elink0_m_axi_awready), // Templated
.s_axi_bid (elink0_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (elink0_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (elink0_m_axi_bvalid), // Templated
.s_axi_rid (elink0_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (elink0_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (elink0_m_axi_rlast), // Templated
.s_axi_rresp (elink0_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (elink0_m_axi_rvalid), // Templated
.s_axi_wready (elink0_m_axi_wready), // Templated
// Inputs
.s_axi_arid (elink0_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (elink0_m_axi_arlock), // Templated
.s_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (elink0_m_axi_arvalid), // Templated
.s_axi_awid (elink0_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (elink0_m_axi_awlock), // Templated
.s_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (elink0_m_axi_awvalid), // Templated
.s_axi_bready (elink0_m_axi_bready), // Templated
.s_axi_rready (elink0_m_axi_rready), // Templated
.s_axi_wid (elink0_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (elink0_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (elink0_m_axi_wlast), // Templated
.s_axi_wstrb (elink0_m_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (elink0_m_axi_wvalid)); // Templated
//######################################################################
//AXI MASTER (DRIVES STIMULUS) to configure elink1
//######################################################################
/*emaxi AUTO_TEMPLATE (//Stimulus
.m_axi_aresetn (nreset),
.m_axi_aclk (clk1),
.m_\(.*\) (ext1_m_\1[]),
.rr_wait (1'b0),
.wr_access (ext1_write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_access (ext1_read_in),
.rd_packet (packet_in[PW-1:0]),
.wr_wait (wr_wait1),
.rd_wait (rd_wait1),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi1 (/*AUTOINST*/
// Outputs
.wr_wait (wr_wait1), // Templated
.rd_wait (rd_wait1), // Templated
.rr_access (rr_access),
.rr_packet (rr_packet[PW-1:0]),
.m_axi_awid (ext1_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (ext1_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (ext1_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (ext1_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (ext1_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (ext1_m_axi_awlock), // Templated
.m_axi_awcache (ext1_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (ext1_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (ext1_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (ext1_m_axi_awvalid), // Templated
.m_axi_wid (ext1_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (ext1_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (ext1_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (ext1_m_axi_wlast), // Templated
.m_axi_wvalid (ext1_m_axi_wvalid), // Templated
.m_axi_bready (ext1_m_axi_bready), // Templated
.m_axi_arid (ext1_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (ext1_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (ext1_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (ext1_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (ext1_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (ext1_m_axi_arlock), // Templated
.m_axi_arcache (ext1_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (ext1_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (ext1_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (ext1_m_axi_arvalid), // Templated
.m_axi_rready (ext1_m_axi_rready), // Templated
// Inputs
.wr_access (ext1_write_in), // Templated
.wr_packet (packet_in[PW-1:0]), // Templated
.rd_access (ext1_read_in), // Templated
.rd_packet (packet_in[PW-1:0]), // Templated
.rr_wait (1'b0), // Templated
.m_axi_aclk (clk1), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (ext1_m_axi_awready), // Templated
.m_axi_wready (ext1_m_axi_wready), // Templated
.m_axi_bid (ext1_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (ext1_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (ext1_m_axi_bvalid), // Templated
.m_axi_arready (ext1_m_axi_arready), // Templated
.m_axi_rid (ext1_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (ext1_m_axi_rdata[63:0]), // Templated
.m_axi_rresp (ext1_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (ext1_m_axi_rlast), // Templated
.m_axi_rvalid (ext1_m_axi_rvalid)); // Templated
//######################################################################
//2ND ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.sys_clk (clk1),
.rxi_\(.*\) (elink0_txo_\1[]),
.txi_\(.*\) (elink0_rxo_\1[]),
.s_\(.*\) (ext1_m_\1[]),
.m_\(.*\) (mem_m_\1[]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
defparam elink1.ID = 12'h820;
defparam elink1.ETYPE = 0;
defparam elink1.S_IDW = S2_IDW;
defparam elink1.M_IDW = M2_IDW;
//defparam elink1.WAIT_WRRD = 0;
axi_elink elink1 ( .s_axi_wstrb ((ext1_m_axi_wstrb[3:0] | ext1_m_axi_wstrb[7:4])),//NOTE:HACK!!
/*AUTOINST*/
// Outputs
.elink_active (elink1_elink_active), // Templated
.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink1_txo_lclk_p), // Templated
.txo_lclk_n (elink1_txo_lclk_n), // Templated
.txo_frame_p (elink1_txo_frame_p), // Templated
.txo_frame_n (elink1_txo_frame_n), // Templated
.txo_data_p (elink1_txo_data_p[7:0]), // Templated
.txo_data_n (elink1_txo_data_n[7:0]), // Templated
.chipid (elink1_chipid[11:0]), // Templated
.chip_nreset (elink1_chip_nreset), // Templated
.cclk_p (elink1_cclk_p), // Templated
.cclk_n (elink1_cclk_n), // Templated
.mailbox_irq (elink1_mailbox_irq), // Templated
.m_axi_awid (mem_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (mem_m_axi_awlock), // Templated
.m_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (mem_m_axi_awvalid), // Templated
.m_axi_wid (mem_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (mem_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (mem_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (mem_m_axi_wlast), // Templated
.m_axi_wvalid (mem_m_axi_wvalid), // Templated
.m_axi_bready (mem_m_axi_bready), // Templated
.m_axi_arid (mem_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (mem_m_axi_arlock), // Templated
.m_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (mem_m_axi_arvalid), // Templated
.m_axi_rready (mem_m_axi_rready), // Templated
.s_axi_arready (ext1_m_axi_arready), // Templated
.s_axi_awready (ext1_m_axi_awready), // Templated
.s_axi_bid (ext1_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (ext1_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (ext1_m_axi_bvalid), // Templated
.s_axi_rid (ext1_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (ext1_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (ext1_m_axi_rlast), // Templated
.s_axi_rresp (ext1_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (ext1_m_axi_rvalid), // Templated
.s_axi_wready (ext1_m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (elink0_txo_lclk_p), // Templated
.rxi_lclk_n (elink0_txo_lclk_n), // Templated
.rxi_frame_p (elink0_txo_frame_p), // Templated
.rxi_frame_n (elink0_txo_frame_n), // Templated
.rxi_data_p (elink0_txo_data_p[7:0]), // Templated
.rxi_data_n (elink0_txo_data_n[7:0]), // Templated
.txi_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.txi_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.txi_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.txi_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (mem_m_axi_awready), // Templated
.m_axi_wready (mem_m_axi_wready), // Templated
.m_axi_bid (mem_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (mem_m_axi_bvalid), // Templated
.m_axi_arready (mem_m_axi_arready), // Templated
.m_axi_rid (mem_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (mem_m_axi_rdata[63:0]), // Templated
.m_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (mem_m_axi_rlast), // Templated
.m_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (ext1_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (ext1_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (ext1_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (ext1_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (ext1_m_axi_arlock), // Templated
.s_axi_arlen (ext1_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (ext1_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (ext1_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (ext1_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (ext1_m_axi_arvalid), // Templated
.s_axi_awid (ext1_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (ext1_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (ext1_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (ext1_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (ext1_m_axi_awlock), // Templated
.s_axi_awlen (ext1_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (ext1_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (ext1_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (ext1_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (ext1_m_axi_awvalid), // Templated
.s_axi_bready (ext1_m_axi_bready), // Templated
.s_axi_rready (ext1_m_axi_rready), // Templated
.s_axi_wid (ext1_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (ext1_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (ext1_m_axi_wlast), // Templated
.s_axi_wvalid (ext1_m_axi_wvalid)); // Templated
//######################################################################
//AXI SLAVE
//######################################################################
/*esaxi AUTO_TEMPLATE (//Stimulus
.s_\(.*\) (mem_m_\1[]),
.\(.*\) (mem_\1[]),
);
*/
esaxi #(.S_IDW(S_IDW), .RETURN_ADDR(RETURN_ADDR))
esaxi (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
.s_axi_wstrb (mem_m_axi_wstrb[7:4] | mem_m_axi_wstrb[3:0]),
/*AUTOINST*/
// Outputs
.wr_access (mem_wr_access), // Templated
.wr_packet (mem_wr_packet[PW-1:0]), // Templated
.rd_access (mem_rd_access), // Templated
.rd_packet (mem_rd_packet[PW-1:0]), // Templated
.rr_wait (mem_rr_wait), // Templated
.s_axi_arready (mem_m_axi_arready), // Templated
.s_axi_awready (mem_m_axi_awready), // Templated
.s_axi_bid (mem_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (mem_m_axi_bvalid), // Templated
.s_axi_rid (mem_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (mem_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (mem_m_axi_rlast), // Templated
.s_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_wready (mem_m_axi_wready), // Templated
// Inputs
.wr_wait (mem_wr_wait), // Templated
.rd_wait (mem_rd_wait), // Templated
.rr_access (mem_rr_access), // Templated
.rr_packet (mem_rr_packet[PW-1:0]), // Templated
.s_axi_arid (mem_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (mem_m_axi_arlock), // Templated
.s_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (mem_m_axi_arvalid), // Templated
.s_axi_awid (mem_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (mem_m_axi_awlock), // Templated
.s_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (mem_m_axi_awvalid), // Templated
.s_axi_bready (mem_m_axi_bready), // Templated
.s_axi_rready (mem_m_axi_rready), // Templated
.s_axi_wid (mem_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (mem_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (mem_m_axi_wlast), // Templated
.s_axi_wvalid (mem_m_axi_wvalid)); // Templated
//######################################################################
// MEMORY PORT
//######################################################################
//"Arbitration" between read/write transaction
assign mem_access = mem_wr_access | mem_rd_access;
assign mem_packet[PW-1:0] = mem_wr_access ? mem_wr_packet[PW-1:0]:
mem_rd_packet[PW-1:0];
assign mem_rd_wait = (mem_wait & mem_rd_access) |
mem_wr_access;
assign mem_wr_wait = (mem_wait & mem_wr_access);
/*ememory AUTO_TEMPLATE (
// Outputsd
.\(.*\)_out (mem_rr_\1[]),
.\(.*\)_in (mem_\1[]),
.wait_out (mem_wait),
.wait_in (mem_rr_wait), //pushback on reads
);
*/
ememory #(.WAIT(0),
.MON(1))
ememory (.clk (clk1),
.coreid (12'h0),
/*AUTOINST*/
// Outputs
.wait_out (mem_wait), // Templated
.access_out (mem_rr_access), // Templated
.packet_out (mem_rr_packet[PW-1:0]), // Templated
// Inputs
.nreset (nreset),
.access_in (mem_access), // Templated
.packet_in (mem_packet[PW-1:0]), // Templated
.wait_in (mem_rr_wait)); // Templated
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../oh/elink/hdl" "../oh/emesh/dv" "../oh/axi/dv" "../oh/emesh/hdl" "../oh/memory/hdl" "../oh/axi/hdl")
// End:
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