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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_axis_tx
*/
module test_eth_axis_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_eth_payload_axis_tready;
wire s_eth_hdr_ready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_eth_axis_tx_64.lxt");
$dumpvars(0, test_eth_axis_tx_64);
end
eth_axis_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This is almost an exact copy of the lsu_burst_master, but has special support
// for placing items into a a block ram rather than a fifo. I'd rather leave them
// as separate files rather than complicating the already existing lsu's which are
// are known to work.
//
// Helper module to handle bursting large sequential blocks of memory to or
// from global memory.
//
/*****************************************************************************/
// Burst read master:
// Keeps a local buffer populated with data from a sequential block of
// global memory. The block of global memory is specified by a base address
// and size.
/*****************************************************************************/
module lsu_prefetch_block (
clk,
reset,
o_active, //Debugging signal
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
cache_line_to_write_to,
control_done,
control_early_done,
// user logic inputs and outputs
cache_line_to_read_from,
user_buffer_address,
user_buffer_data,
user_data_available,
read_reg_enable,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
/*************
* Parameters *
*************/
parameter DATAWIDTH = 32;
parameter MWIDTH = DATAWIDTH;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
parameter N=8;
parameter LOG2N=3;
/********
* Ports *
********/
input clk;
input reset;
output o_active;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
input [LOG2N-1:0] cache_line_to_write_to;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input [LOG2N-1:0] cache_line_to_read_from;
input [FIFODEPTH_LOG2-1:0] user_buffer_address;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
input read_reg_enable;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
/***************
* Architecture *
***************/
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
wire too_many_reads_pending;
reg [FIFODEPTH_LOG2:0] w_user_buffer_address;
// Pipelining
reg r_avm_readdatavalid;
reg [MWIDTH-1:0] r_avm_readdata /* synthesis dont_merge */;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// user buffer address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
w_user_buffer_address <= 0;
end
else
begin
if(control_go == 1)
begin
w_user_buffer_address <= 0;
end
else
begin
w_user_buffer_address <= w_user_buffer_address + r_avm_readdatavalid;
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = 1'b0;
assign control_early_done = 1'b0;
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = 0;
/* --- Pipeline Return Path --- */
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_avm_readdata <= 'x;
r_avm_readdatavalid <= 1'b0;
end
else
begin
r_avm_readdata <= master_readdata;
r_avm_readdatavalid <= master_readdatavalid;
end
end
assign user_data_available = w_user_buffer_address[FIFODEPTH_LOG2];
altsyncram altsyncram_component (
.clock0 (clk),
.address_a ({cache_line_to_write_to,w_user_buffer_address[FIFODEPTH_LOG2-1:0]}),
.wren_a (r_avm_readdatavalid),
.data_a (r_avm_readdata),
.address_b ({cache_line_to_read_from,user_buffer_address}),
.q_b (user_buffer_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (~read_reg_enable),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATAWIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = N*FIFODEPTH,
altsyncram_component.numwords_b = N*FIFODEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = FIFODEPTH_LOG2+LOG2N,
altsyncram_component.widthad_b = FIFODEPTH_LOG2+LOG2N,
altsyncram_component.width_a = DATAWIDTH,
altsyncram_component.width_b = DATAWIDTH,
altsyncram_component.width_byteena_a = 1;
assign o_active = |length;
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_9_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_9_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Read #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96,
parameter HASHADDR_WIDTH = 32,
parameter MEMADDR_WIDTH = 20
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] input_data,
input wire input_valid,
output wire input_ready,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] feedback_data,
input wire feedback_valid,
output wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg [31:0] rdcmd_data,
output reg rdcmd_valid,
input wire rdcmd_ready
);
reg selectInputNext;
reg selectInput; //1 == input, 0==feedback
localparam [2:0]
ST_IDLE = 0,
ST_ISSUE_READ = 3,
ST_OUTPUT_KEY = 4;
reg [2:0] state;
wire[HASHADDR_WIDTH+KEY_WIDTH+META_WIDTH-1:0] in_data;
wire in_valid;
reg in_ready;
wire[31:0] hash_data;
assign in_data = (selectInput==1) ? input_data : feedback_data;
assign in_valid = (selectInput==1) ? input_valid : feedback_valid;
assign input_ready = (selectInput==1) ? in_ready : 0;
assign feedback_ready = (selectInput==1) ? 0 : in_ready;
assign hash_data = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] : feedback_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH];
wire[MEMADDR_WIDTH-1:0] addr;
assign addr = hash_data[31:32 - MEMADDR_WIDTH] ^ hash_data[MEMADDR_WIDTH-1:0];
always @(posedge clk) begin
if (rst) begin
selectInput <= 1;
selectInputNext <= 0;
state <= ST_IDLE;
in_ready <= 0;
rdcmd_valid <= 0;
output_valid <= 0;
end
else begin
if (rdcmd_ready==1 && rdcmd_valid==1) begin
rdcmd_valid <= 0;
end
if (output_ready==1 && output_valid==1) begin
output_valid <= 0;
end
in_ready <= 0;
case (state)
ST_IDLE : begin
if (output_ready==1 && rdcmd_ready==1) begin
selectInput <= selectInputNext;
selectInputNext <= ~selectInputNext;
if (selectInputNext==1 && input_valid==0 && feedback_valid==1) begin
selectInput <= 0;
selectInputNext <= 1;
end
if (selectInputNext==0 && input_valid==1 && feedback_valid==0) begin
selectInput <= 1;
selectInputNext <= 0;
end
if (selectInput==1 && input_valid==1) begin
state <= ST_ISSUE_READ;
end
if (selectInput==0 && feedback_valid==1) begin
state <= ST_ISSUE_READ;
end
end
end
ST_ISSUE_READ: begin
if (in_data[KEY_WIDTH+META_WIDTH-4]==1) begin
// ignore this and don't send read!
end else begin
rdcmd_data <= addr;
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
state <= ST_OUTPUT_KEY;
output_data <= in_data;
output_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] <= addr; //(in_data[KEY_WIDTH+META_WIDTH-1]==0) ? addr1 : addr2;
in_ready <= 1;
end
ST_OUTPUT_KEY: begin
if (output_ready==1) begin
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
|
// Check the various variable indexed down selects (LSB > MSB).
module top;
parameter [-4:-1] ap = 4'he;
parameter [-4:-1] bp = 4'h1;
parameter [1:4] cp = 4'he;
parameter [1:4] dp = 4'h1;
reg passed;
wire [-4:-1] a = 4'he;
wire [-4:-1] b = 4'h1;
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [-4:-1] ar = 4'he;
reg [-4:-1] br = 4'h1;
wire [1:4] c = 4'he;
wire [1:4] d = 4'h1;
wire [0:0] s3 = 1;
wire [1:0] s4 = 1;
reg [1:4] cr = 4'he;
reg [1:4] dr = 4'h1;
wire [1:0] res_a0 = a[s0-:2];
wire [1:0] res_b0 = b[s0-:2];
wire [1:0] res_a1 = a[s1-:2];
wire [1:0] res_b1 = b[s1-:2];
wire [1:0] res_a2 = a[s2-:2];
wire [1:0] res_b2 = b[s2-:2];
wire [1:0] res_c3 = c[s3-:2];
wire [1:0] res_d3 = d[s3-:2];
wire [1:0] res_c4 = c[s4-:2];
wire [1:0] res_d4 = d[s4-:2];
reg [-4:-1] res_ab;
reg [1:4] res_cd;
initial begin
#1;
passed = 1'b1;
// Check procedural R-value variable index down selects of a net.
$display("a[s0-:2]: %b", a[s1-:2]);
if (a[s0-:2] !== 2'b0x) begin
$display("Failed a[s0-:2], expected 2'b0x, got %b", a[s0-:2]);
passed = 1'b0;
end
$display("b[s0-:2]: %b", b[s1-:2]);
if (b[s0-:2] !== 2'b1x) begin
$display("Failed b[s0-:2], expected 2'b1x, got %b", b[s0-:2]);
passed = 1'b0;
end
$display("a[s1-:2]: %b", a[s1-:2]);
if (a[s1-:2] !== 2'b0x) begin
$display("Failed a[s1-:2], expected 2'b0x, got %b", a[s1-:2]);
passed = 1'b0;
end
$display("b[s1-:2]: %b", b[s1-:2]);
if (b[s1-:2] !== 2'b1x) begin
$display("Failed b[s1-:2], expected 2'b1x, got %b", b[s1-:2]);
passed = 1'b0;
end
$display("a[s2-:2]: %b", a[s2-:2]);
if (a[s2-:2] !== 2'b0x) begin
$display("Failed a[s2-:2], expected 2'b0x, got %b", a[s2-:2]);
passed = 1'b0;
end
$display("b[s2-:2]: %b", b[s2-:2]);
if (b[s2-:2] !== 2'b1x) begin
$display("Failed b[s2-:2], expected 2'b1x, got %b", b[s2-:2]);
passed = 1'b0;
end
$display("c[s3-:2]: %b", c[s3-:2]);
if (c[s3-:2] !== 2'bx1) begin
$display("Failed c[s3-:2], expected 2'bx1, got %b", c[s3-:2]);
passed = 1'b0;
end
$display("d[s3-:2]: %b", d[s3-:2]);
if (d[s3-:2] !== 2'bx0) begin
$display("Failed d[s3-:2], expected 2'bx0, got %b", d[s3-:2]);
passed = 1'b0;
end
$display("c[s4-:2]: %b", c[s4-:2]);
if (c[s4-:2] !== 2'bx1) begin
$display("Failed c[s4-:2], expected 2'bx1, got %b", c[s4-:2]);
passed = 1'b0;
end
$display("d[s4-:2]: %b", d[s4-:2]);
if (d[s4-:2] !== 2'bx0) begin
$display("Failed d[s4-:2], expected 2'bx0, got %b", d[s4-:2]);
passed = 1'b0;
end
// Check procedural R-value variable index down selects of a parameter.
$display("ap[s0-:2]: %b", ap[s0-:2]);
if (ap[s0-:2] !== 2'b0x) begin
$display("Failed ap[s0-:2], expected 2'b0x, got %b", ap[s0-:2]);
passed = 1'b0;
end
$display("bp[s0-:2]: %b", bp[s0-:2]);
if (bp[s0-:2] !== 2'b1x) begin
$display("Failed bp[s0-:2], expected 2'b1x, got %b", bp[s0-:2]);
passed = 1'b0;
end
$display("ap[s1-:2]: %b", ap[s1-:2]);
if (ap[s1-:2] !== 2'b0x) begin
$display("Failed ap[s1-:2], expected 2'b0x, got %b", ap[s1-:2]);
passed = 1'b0;
end
$display("bp[s1-:2]: %b", bp[s1-:2]);
if (bp[s1-:2] !== 2'b1x) begin
$display("Failed bp[s1-:2], expected 2'b1x, got %b", bp[s1-:2]);
passed = 1'b0;
end
$display("ap[s2-:2]: %b", ap[s2-:2]);
if (ap[s2-:2] !== 2'b0x) begin
$display("Failed ap[s2-:2], expected 2'b0x, got %b", ap[s2-:2]);
passed = 1'b0;
end
$display("bp[s2-:2]: %b", bp[s2-:2]);
if (bp[s2-:2] !== 2'b1x) begin
$display("Failed bp[s2-:2], expected 2'b1x, got %b", bp[s2-:2]);
passed = 1'b0;
end
$display("cp[s3-:2]: %b", cp[s3-:2]);
if (cp[s3-:2] !== 2'bx1) begin
$display("Failed cp[s3-:2], expected 2'bx1, got %b", cp[s3-:2]);
passed = 1'b0;
end
$display("dp[s3-:2]: %b", dp[s3-:2]);
if (dp[s3-:2] !== 2'bx0) begin
$display("Failed dp[s3-:2], expected 2'bx0, got %b", dp[s3-:2]);
passed = 1'b0;
end
$display("cp[s4-:2]: %b", cp[s4-:2]);
if (cp[s4-:2] !== 2'bx1) begin
$display("Failed cp[s4-:2], expected 2'bx1, got %b", cp[s4-:2]);
passed = 1'b0;
end
$display("dp[s4-:2]: %b", dp[s4-:2]);
if (dp[s4-:2] !== 2'bx0) begin
$display("Failed dp[s4-:2], expected 2'bx0, got %b", dp[s4-:2]);
passed = 1'b0;
end
// Check procedural R-value variable index down selects of a reg.
$display("ar[s0-:2]: %b", ar[s0-:2]);
if (ar[s0-:2] !== 2'b0x) begin
$display("Failed ar[s0-:2], expected 2'b0x, got %b", ar[s0-:2]);
passed = 1'b0;
end
$display("br[s0-:2]: %b", br[s0-:2]);
if (br[s0-:2] !== 2'b1x) begin
$display("Failed br[s0-:2], expected 2'b1x, got %b", br[s0-:2]);
passed = 1'b0;
end
$display("ar[s1-:2]: %b", ar[s1-:2]);
if (ar[s1-:2] !== 2'b0x) begin
$display("Failed ar[s1-:2], expected 2'b0x, got %b", ar[s1-:2]);
passed = 1'b0;
end
$display("br[s1-:2]: %b", br[s1-:2]);
if (br[s1-:2] !== 2'b1x) begin
$display("Failed br[s1-:2], expected 2'b1x, got %b", br[s1-:2]);
passed = 1'b0;
end
$display("ar[s2-:2]: %b", ar[s2-:2]);
if (ar[s2-:2] !== 2'b0x) begin
$display("Failed ar[s2-:2], expected 2'b0x, got %b", ar[s2-:2]);
passed = 1'b0;
end
$display("br[s2-:2]: %b", br[s2-:2]);
if (br[s2-:2] !== 2'b1x) begin
$display("Failed br[s2-:2], expected 2'b1x, got %b", br[s2-:2]);
passed = 1'b0;
end
$display("cr[s3-:2]: %b", cr[s3-:2]);
if (cr[s3-:2] !== 2'bx1) begin
$display("Failed cr[s3-:2], expected 2'bx1, got %b", cr[s3-:2]);
passed = 1'b0;
end
$display("dr[s3-:2]: %b", dr[s3-:2]);
if (dr[s3-:2] !== 2'bx0) begin
$display("Failed dr[s3-:2], expected 2'bx0, got %b", dr[s3-:2]);
passed = 1'b0;
end
$display("cr[s4-:2]: %b", cr[s4-:2]);
if (cr[s4-:2] !== 2'bx1) begin
$display("Failed cr[s4-:2], expected 2'bx1, got %b", cr[s4-:2]);
passed = 1'b0;
end
$display("dr[s4-:2]: %b", dr[s4-:2]);
if (dr[s4-:2] !== 2'bx0) begin
$display("Failed dr[s4-:2], expected 2'bx0, got %b", dr[s4-:2]);
passed = 1'b0;
end
// Check continuous assignment R-value variable index down selects.
if (res_a0 !== 2'b0x) begin
$display("Failed res_a0, expected 2'b0x, got %b", res_a0);
passed = 1'b0;
end
if (res_b0 !== 2'b1x) begin
$display("Failed res_b0, expected 2'b1x, got %b", res_b0);
passed = 1'b0;
end
if (res_a1 !== 2'b0x) begin
$display("Failed res_a1, expected 2'b0x, got %b", res_a1);
passed = 1'b0;
end
if (res_b1 !== 2'b1x) begin
$display("Failed res_b1, expected 2'b1x, got %b", res_b1);
passed = 1'b0;
end
if (res_a2 !== 2'b0x) begin
$display("Failed res_a2, expected 2'b0x, got %b", res_a2);
passed = 1'b0;
end
if (res_b2 !== 2'b1x) begin
$display("Failed res_b2, expected 2'b1x, got %b", res_b2);
passed = 1'b0;
end
if (res_c3 !== 2'bx1) begin
$display("Failed res_c3, expected 2'bx1, got %b", res_c3);
passed = 1'b0;
end
if (res_d3 !== 2'bx0) begin
$display("Failed res_d3, expected 2'bx0, got %b", res_d3);
passed = 1'b0;
end
if (res_c4 !== 2'bx1) begin
$display("Failed res_c4, expected 2'bx1, got %b", res_c4);
passed = 1'b0;
end
if (res_d4 !== 2'bx0) begin
$display("Failed res_d4, expected 2'bx0, got %b", res_d4);
passed = 1'b0;
end
// Check procedural L-value variable index down selects.
res_ab = 4'bxxxx;
res_ab[s0-:2] = 2'b00;
if (res_ab !== 4'bxxx0) begin
$display("Failed res_ab[s0], expected 4'bxxx0, got %b", res_ab);
passed = 1'b0;
end
res_ab = 4'bxxxx;
res_ab[s1-:2] = 2'b00;
if (res_ab !== 4'bxxx0) begin
$display("Failed res_ab[s1], expected 4'bxxx0, got %b", res_ab);
passed = 1'b0;
end
res_ab = 4'bxxxx;
res_ab[s2-:2] = 2'b00;
if (res_ab !== 4'bxxx0) begin
$display("Failed res_ab[s2], expected 4'bxxx0, got %b", res_ab);
passed = 1'b0;
end
res_cd = 4'bxxxx;
res_cd[s3-:2] = 2'b00;
if (res_cd !== 4'b0xxx) begin
$display("Failed res_cd[s3], expected 4'b0xxx, got %b", res_cd);
passed = 1'b0;
end
res_cd = 4'bxxxx;
res_cd[s4-:2] = 2'b00;
if (res_cd !== 4'b0xxx) begin
$display("Failed res_cd[s4], expected 4'b0xxx, got %b", res_cd);
passed = 1'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2010 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
`include "../../shared/rtl/soclib/pipeconnect.h"
module toplevel(input clk, // 16 MHz
output reg [ 7:0] led,
output ram_lb_n,
output ram_ub_n,
inout [15:0] ram_data,
output ram_oe_n,
output ram_ce1_n,
output ram_we_n,
output ram_ce2,
output [17:0] ram_addr,
input rxd,
output txd
// input exp_rst_n,
// input exp_pres,
// inout [3:32] X202
);
parameter FREQ = 27'd50000000; // 27-bit is enough for 268 MHz
parameter BPS = 230400;
wire reset_button = 0 /*~exp_rst_n*/;
reg [26:0] rst_counter = FREQ;
wire reset = ~rst_counter[26];
wire clock;
wire clock_locked;
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [ 1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [ 3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [ 1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
always @(posedge clock)
if (rs232out_w)
led <= ~rs232out_d;
else if (rs232in_attention)
led <= ~rs232in_data;
always @(posedge clock)
if (reset_button | ~clock_locked)
rst_counter <= FREQ; // 1 sec delay
else if (~rst_counter[26])
rst_counter <= rst_counter - 1'd1;
// Actually, just a 1-1 clock filter at this point
pll pll_inst (
.inclk0 ( clk ),
.c0 ( clock ),
.locked ( clock_locked )
);
yari yari_inst
(.clock(clock)
,.rst(reset)
// Inputs
,.mem_waitrequest (mem_waitrequest)
,.mem_readdata (mem_readdata)
,.mem_readdataid (mem_readdataid)
// Outputs
,.mem_id (mem_id)
,.mem_address (mem_address)
,.mem_read (mem_read)
,.mem_write (mem_write)
,.mem_writedata (mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
defparam yari_inst.FREQ = FREQ;
assign ram_ce2 = 1;
sram16_ctrl sram16_ctrl_inst
(.clock(clock)
,.rst(reset)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(ram_addr)
,.sram_d(ram_data)
,.sram_cs_n(ram_ce1_n)
,.sram_be_n({ram_ub_n,ram_lb_n})
,.sram_oe_n(ram_oe_n)
,.sram_we_n(ram_we_n)
);
defparam sram16_ctrl_inst.FREQ = FREQ;
rs232out rs232out_inst
(.clock(clock),
.serial_out(txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clock),
.serial_in(rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clock),
.rst(reset),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: acl_int_mult64s.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 174 10/17/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult64u (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 64;
parameter INPUT2_WIDTH = 64;
input enable;
input clock;
input [INPUT1_WIDTH - 1 : 0] dataa;
input [INPUT2_WIDTH - 1 : 0] datab;
output reg [63:0] result;
wire [127:0] sub_wire0;
lpm_mult lpm_mult_component (
.clock (clock),
.datab (datab),
.clken (enable),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = INPUT1_WIDTH,
lpm_mult_component.lpm_widthb = INPUT2_WIDTH,
lpm_mult_component.lpm_widthp = 128;
always@(posedge clock)
begin
if (enable)
result <= sub_wire0[63:0];
end
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "3"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "64"
// Retrieval info: PRIVATE: WidthB NUMERIC "64"
// Retrieval info: PRIVATE: WidthP NUMERIC "128"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "128"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// add check for wg out of inflight wg buffer
module host_test (/*AUTOARG*/
// Outputs
host_wg_valid, host_wg_id, host_num_wf, host_vgpr_size_per_wf,
host_vgpr_size_total, host_sgpr_size_per_wf, host_sgpr_size_total,
host_lds_size_total, host_gds_size_total, host_wf_size,
host_start_pc, all_wf_dispatched,
// Inputs
rst, clk, inflight_wg_buffer_host_rcvd_ack
) ;
input rst, clk;
input inflight_wg_buffer_host_rcvd_ack;
parameter WG_ID_WIDTH = 6;
parameter WG_SLOT_ID_WIDTH = 6;
parameter CU_ID_WIDTH = 2;
parameter WAVE_ITEM_WIDTH = 6;
parameter WF_COUNT_WIDTH = 4;
localparam MAX_WF_PER_WG = 2**WF_COUNT_WIDTH;
parameter MEM_ADDR_WIDTH = 32;
parameter VGPR_ID_WIDTH = 8;
parameter NUMBER_VGPR_SLOTS = 256;
parameter SGPR_ID_WIDTH = 4;
parameter NUMBER_SGPR_SLOTS = 13;
parameter LDS_ID_WIDTH = 8;
parameter NUMBER_LDS_SLOTS = 256;
parameter GDS_ID_WIDTH = 14;
parameter GDS_SIZE = 16384;
output reg host_wg_valid;
output reg [WG_ID_WIDTH-1:0] host_wg_id;
output reg [WF_COUNT_WIDTH-1:0] host_num_wf;
output reg [VGPR_ID_WIDTH:0] host_vgpr_size_per_wf;
output reg [VGPR_ID_WIDTH:0] host_vgpr_size_total;
output reg [SGPR_ID_WIDTH:0] host_sgpr_size_per_wf;
output reg [SGPR_ID_WIDTH:0] host_sgpr_size_total;
output reg [LDS_ID_WIDTH:0] host_lds_size_total;
output reg [GDS_ID_WIDTH:0] host_gds_size_total;
output reg [WAVE_ITEM_WIDTH-1:0] host_wf_size;
output reg [MEM_ADDR_WIDTH-1:0] host_start_pc;
output reg all_wf_dispatched;
localparam NUM_ADDED_WG = 10;
reg [WG_ID_WIDTH-1:0] sim_host_wg_id[NUM_ADDED_WG-1:0];
reg [WAVE_ITEM_WIDTH-1:0] sim_host_wf_size[NUM_ADDED_WG-1:0];
reg [WF_COUNT_WIDTH-1:0] sim_host_num_wf[NUM_ADDED_WG-1:0];
reg [VGPR_ID_WIDTH:0] sim_host_vgpr_size_per_wf[NUM_ADDED_WG-1:0];
reg [VGPR_ID_WIDTH:0] sim_host_vgpr_size_total[NUM_ADDED_WG-1:0];
reg [SGPR_ID_WIDTH:0] sim_host_sgpr_size_per_wf[NUM_ADDED_WG-1:0];
reg [SGPR_ID_WIDTH:0] sim_host_sgpr_size_total[NUM_ADDED_WG-1:0];
reg [LDS_ID_WIDTH:0] sim_host_lds_size_total[NUM_ADDED_WG-1:0];
reg [GDS_ID_WIDTH:0] sim_host_gds_size_total[NUM_ADDED_WG-1:0];
reg [MEM_ADDR_WIDTH-1:0] sim_host_start_pc[NUM_ADDED_WG-1:0];
reg [NUM_ADDED_WG-1:0] sim_wg_accepted
= '{ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
reg [NUM_ADDED_WG-1:0] sim_wg_issued
= '{ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
reg [NUM_ADDED_WG-1:0] sim_wg_ended
= '{ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
integer host_curr_wg;
initial begin : INITIALIZE_VALUES
integer currInit;
for (currInit = 0; currInit < NUM_ADDED_WG; currInit=currInit+1) begin
sim_host_wg_id[currInit] = currInit;
sim_host_wf_size[currInit] = ({$random}%(2**WAVE_ITEM_WIDTH)) + 1;
sim_host_num_wf[currInit] = ({$random}%(MAX_WF_PER_WG-1))+1;
sim_host_vgpr_size_per_wf[currInit]
= {$random}%(NUMBER_VGPR_SLOTS/sim_host_num_wf[currInit]);
sim_host_vgpr_size_total[currInit]
= sim_host_vgpr_size_per_wf[currInit]*sim_host_num_wf[currInit];
sim_host_sgpr_size_per_wf[currInit]
= {$random}%(NUMBER_SGPR_SLOTS/sim_host_num_wf[currInit]);
sim_host_sgpr_size_total[currInit]
= sim_host_sgpr_size_per_wf[currInit]*sim_host_num_wf[currInit];
sim_host_lds_size_total[currInit]
= {$random}%NUMBER_LDS_SLOTS;
sim_host_gds_size_total[currInit]
= {$random}%(GDS_SIZE/50);
sim_host_start_pc[currInit] = {$random};
end
end
task host_new_wf;
input [WG_ID_WIDTH-1:0] wg_id;
input [WF_COUNT_WIDTH-1:0] num_wf;
input [WAVE_ITEM_WIDTH-1:0] wf_size;
input [VGPR_ID_WIDTH:0] vgpr_size_total;
input [VGPR_ID_WIDTH:0] vgpr_size_per_wf;
input [SGPR_ID_WIDTH:0] sgpr_size_total;
input [SGPR_ID_WIDTH:0] sgpr_size_per_wf;
input [LDS_ID_WIDTH:0] lds_size_total;
input [GDS_ID_WIDTH:0] gds_size_total;
input [MEM_ADDR_WIDTH-1:0] start_pc;
begin
host_wg_valid = 1'b1;
host_wg_id = wg_id;
host_num_wf = num_wf;
host_wf_size = wf_size;
host_gds_size_total = gds_size_total;
host_lds_size_total= lds_size_total;
host_sgpr_size_per_wf = sgpr_size_per_wf;
host_sgpr_size_total = sgpr_size_total;
host_vgpr_size_per_wf = vgpr_size_per_wf;
host_vgpr_size_total = vgpr_size_total;
host_start_pc = start_pc;
@(posedge clk);
while(!inflight_wg_buffer_host_rcvd_ack) @(posedge clk);
@(posedge clk);
host_wg_valid = 1'b0;
end
endtask //
// Host block
initial begin
host_curr_wg = 0;
host_wg_valid = 1'b0;
all_wf_dispatched = 1'b0;
@(posedge clk);
@(negedge rst);
@(posedge clk);
for (host_curr_wg = 0; host_curr_wg<NUM_ADDED_WG;
host_curr_wg = host_curr_wg + 1) begin
host_new_wf(sim_host_wg_id[host_curr_wg], sim_host_num_wf[host_curr_wg],
sim_host_wf_size[host_curr_wg],
sim_host_vgpr_size_total[host_curr_wg],
sim_host_vgpr_size_per_wf[host_curr_wg],
sim_host_sgpr_size_total[host_curr_wg],
sim_host_sgpr_size_per_wf[host_curr_wg],
sim_host_lds_size_total[host_curr_wg],
sim_host_gds_size_total[host_curr_wg],
sim_host_start_pc[host_curr_wg]);
@(posedge clk);
end
@(posedge clk);
@(posedge clk);
all_wf_dispatched = 1'b1;
end
endmodule // host_test
|
/*
for a elctric speed control, we will be generationg
1 - 1.5MS plus width: rolling speed from -max to 0, 0.1ms as 1 step
1.5 - 2MS plus width: rolling speed from 0 to +max
the pwm period is 18--22ms here we defined it as 20MS, 50 HZ
*/
module quadpwm(rst_n, freq_clk, enable, mode, led);
input rst_n;
input freq_clk;
input enable;
input mode;
output pwm0;
output pwm1;
output pwm2;
output pwm3;
reg pwm0_reg;
reg pwm1_reg;
reg pwm2_reg;
reg pwm3_reg;
reg[31:0] engine_reg;
//debug led
reg led;
// generate 2500 Hz from 50 MHz
reg [31:0] count_reg;
reg pwm_clk;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
pwm_clk <= 0;
end
else if (enable)
begin
if (count_reg < 999999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
pwm_clk <= ~pwm_clk;
end
end
end
reg[31:0] pwm_load_register;
/*process the pwm0 signal period*/
always @ (posedge pwm_clk or negedge rst_n)
begin
if (!rst_n)
begin
pwm_load_register <= 1'b0;
end
else if (out_div)
begin
case (pha_reg)
1'd1:
begin
pha_reg <= 1'd0;
end
1'd0:
begin
pha_reg <= 1'd1;
end
endcase
end
end
assign pwm0 = pwm0_reg;
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:58:00 10/31/2016
// Module Name: I_EXECUTE
// Project Name: MIPS
// Description: The MIPS EX_MEM register implementation.
//
// Dependencies: None.
//
////////////////////////////////////////////////////////////////////////////////
module EX_MEM(input clk,
input [1:0] ctlwb_out,
input [2:0] ctlm_out,
input [31:0] adder_out,
input aluzero,
input [31:0] aluout,
input [31:0] readdat2,
input [4:0] muxout,
output reg [1:0] wb_ctlout,
output reg [2:0] m_ctlout,
output reg [31:0] add_result,
output reg zero,
output reg [31:0] alu_result,
output reg [31:0] rdata2out,
output reg [4:0] five_bit_muxout);
// Initialize.
initial begin
wb_ctlout <= 0;
m_ctlout <= 0;
add_result <= 0;
zero <= 0;
alu_result <= 0;
rdata2out <= 0;
five_bit_muxout <= 0;
end
// Update.
always @ (posedge clk)
begin
wb_ctlout <= ctlwb_out;
m_ctlout <= ctlm_out;
add_result <= adder_out;
zero <= aluzero;
alu_result <= aluout;
rdata2out <= readdat2;
five_bit_muxout <= muxout;
end
endmodule
|
module io1_sub (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [w-1:0] pin; // To/From MD31_pad of autoinst_lopaz_srpad.v
wire [2*w-1:0] pin_in; // From MD31_pad of autoinst_lopaz_srpad.v, ...
wire templated; // To/From MD31_pad of autoinst_lopaz_srpad.v
// End of automatics
autoinst_lopaz_srpad MD31_pad
(.*,
.foo (touch_this_not_my_pretty));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
); */
autoinst_lopaz_srpad MD31_pad
(.*);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin (templated));
*/
autoinst_lopaz_srpad MD31_pad
(.*,
// Outputs
// Inouts
.pin (templated) // Templated
);
// And .name with auto inst
autoinst_lopaz_srpad MD31_pad22
(.pin,
.clk,
/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inputs
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
always @(posedge clk) begin
$display ("This .* shouldn't expand.\n");
end
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_lfo(
input rst,
input clk,
input cen,
input [4:0] cycles,
// configuration
input [7:0] lfo_freq,
input [6:0] lfo_amd,
input [6:0] lfo_pmd,
input [1:0] lfo_w,
input lfo_up,
input noise,
// test
input [7:0] test,
output reg lfo_clk,
// data
output reg [7:0] am,
output reg [7:0] pm
);
localparam [1:0] SAWTOOTH = 2'd0,
SQUARE = 2'd1,
TRIANG = 2'd2,
NOISE = 2'd3;
reg [14:0] lfo_lut[0:15];
// counters
reg [ 3:0] cnt1, cnt3, bitcnt;
reg [14:0] cnt2;
reg [15:0] next_cnt2;
reg [ 1:0] cnt1_ov, cnt2_ov;
// LFO state (value)
reg [15:0] val, // counts next integrator step
out2; // integrator for PM/AM
reg [ 6:0] out1;
wire pm_sign;
reg trig_sign, saw_sign;
reg bitcnt_rst, cnt2_load, cnt3_step;
wire lfo_clk_next;
reg lfo_clk_latch;
wire cyc_5 = cycles[3:0]==4'h5;
wire cyc_6 = cycles[3:0]==4'h6;
wire cyc_c = cycles[3:0]==4'hc; // 12
wire cyc_d = cycles[3:0]==4'hd; // 13
wire cyc_e = cycles[3:0]==4'he; // 14
wire cyc_f = cycles[3:0]==4'hf; // 15
reg cnt3_clk;
wire ampm_sel = bitcnt[3];
wire bit7 = &bitcnt[2:0];
reg lfo_up_latch;
assign pm_sign = lfo_w==TRIANG ? trig_sign : saw_sign;
assign lfo_clk_next = test[2] | next_cnt2[15] | cnt3_step;
always @(*) begin
if( cnt2_load ) begin
next_cnt2 = {1'b0, lfo_lut[ lfo_freq[7:4] ] };
end else begin
next_cnt2 = {1'd0,cnt2 } + {15'd0,cnt1_ov[1]|test[3]};
end
end
always @(posedge clk) begin
if( lfo_up )
lfo_up_latch <= 1;
else if( cen )
lfo_up_latch <= 0;
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
cnt1 <= 4'd0;
cnt2 <= 15'd0;
cnt3 <= 4'd0;
cnt1_ov <= 2'd0;
cnt3_step <= 0;
bitcnt <= 4'h8;
end else if( cen ) begin
// counter 1
if( cyc_c )
{ cnt1_ov[0], cnt1 } <= { 1'b0, cnt1 } + 1'd1;
else
cnt1_ov[0] <= 0;
cnt1_ov[1] <= cnt1_ov[0];
bitcnt_rst <= cnt1==4'd2;
if( bitcnt_rst && !cyc_c )
bitcnt <= 4'd0;
else if( cyc_e )
bitcnt <= bitcnt + 1'd1;
// counter 2
cnt2_load <= lfo_up_latch | next_cnt2[15];
cnt2 <= next_cnt2[14:0];
if( cyc_e ) begin
cnt2_ov[0] <= next_cnt2[15];
lfo_clk_latch <= lfo_clk_next;
end
if( cyc_5 ) cnt2_ov[1] <= cnt2_ov[0];
// counter 3
cnt3_step <= 0;
if( cnt2_ov[1] & cyc_d ) begin
cnt3_clk <= 1;
// frequency LSB control
if( !cnt3[0] ) cnt3_step <= lfo_freq[3];
else if( !cnt3[1] ) cnt3_step <= lfo_freq[2];
else if( !cnt3[2] ) cnt3_step <= lfo_freq[1];
else if( !cnt3[3] ) cnt3_step <= lfo_freq[0];
end else begin
cnt3_clk <= 0;
end
if( cnt3_clk )
cnt3 <= cnt3 + 1'd1;
// LFO clock
lfo_clk <= lfo_clk_next;
end
end
// LFO value
reg [1:0] val_sum;
reg val_c, wcarry, val0_next;
reg w1, w2, w3, w4, w5, w6, w7, w8;
reg [6:0] dmux;
reg integ_c, out1bit;
reg [1:0] out2sum;
wire [7:0] out2b;
reg [2:0] bitsel;
assign out2b = out2[15:8];
always @(*) begin
w1 = !lfo_clk || lfo_w==NOISE || !cyc_f;
w4 = lfo_clk_latch && lfo_w==NOISE;
w3 = !w4 && val[15] && !test[1];
w2 = !w1 && lfo_w==TRIANG;
wcarry = !w1 || ( !cyc_f && lfo_w!=NOISE && val_c);
val_sum = {1'b0, w2} + {1'b0, w3} + {1'b0, wcarry};
val0_next = val_sum[0] || (lfo_w==NOISE && lfo_clk_latch && noise);
// LFO compound output, AM/PM base value one after the other
w5 = ampm_sel ? saw_sign : (!trig_sign || lfo_w!=TRIANG);
w6 = w5 ^ w3;
w7 = cycles[3:0]<4'd7 || cycles[3:0]==4'd15;
w8 = lfo_w == SQUARE ? (ampm_sel?cyc_6 : !saw_sign) : w6;
w8 = ~(w8 & w7);
// Integrator
dmux = (ampm_sel ? lfo_pmd : lfo_amd) &~out1;
bitsel = ~(bitcnt[2:0]+3'd1);
out1bit = dmux[ bitsel ] & ~bit7;
out2sum = {1'b0, out1bit} + {1'b0, out2[0] && bitcnt[2:0]!=0} + {1'b0, integ_c & ~cyc_f };
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
val <= 16'd0;
val_c <= 0;
trig_sign <= 0;
saw_sign <= 0;
out1 <= ~7'd0;
out2 <= 16'd0;
integ_c <= 0;
end else if( cen ) begin
val <= {val[14:0], val0_next };
val_c <= val_sum[1];
if( cyc_f ) begin
trig_sign <= val[7];
saw_sign <= val[8];
end
// current step
out1 <= {out1[5:0], w8};
// integrator
integ_c <= out2sum[1];
out2 <= { out2sum[0], out2[15:1] };
// final output
if( bit7 & cyc_f ) begin
if( ampm_sel )
pm <= lfo_pmd==7'd0 ? 8'd0 : { out2b[7]^pm_sign, out2b[6:0]};
else
am <= out2b;
end
end
end
initial begin
lfo_lut[0] = 15'h0000;
lfo_lut[1] = 15'h4000;
lfo_lut[2] = 15'h6000;
lfo_lut[3] = 15'h7000;
lfo_lut[4] = 15'h7800;
lfo_lut[5] = 15'h7c00;
lfo_lut[6] = 15'h7e00;
lfo_lut[7] = 15'h7f00;
lfo_lut[8] = 15'h7f80;
lfo_lut[9] = 15'h7fc0;
lfo_lut[10] = 15'h7fe0;
lfo_lut[11] = 15'h7ff0;
lfo_lut[12] = 15'h7ff8;
lfo_lut[13] = 15'h7ffc;
lfo_lut[14] = 15'h7ffe;
lfo_lut[15] = 15'h7fff;
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module seven_seg_middle_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 15: 0] out_port;
output [ 15: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
reg [ 15: 0] data_out;
wire [ 15: 0] out_port;
wire [ 15: 0] read_mux_out;
wire [ 15: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[15 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Base Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME3_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/22/2014 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME3_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output LOCKED,
input CLKFBIN,
input CLKIN1,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "MMCME3_BASE";
reg trig_attr = 1'b0;
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire CLKFBIN_in;
wire CLKIN1_in;
wire PWRDWN_in;
wire RST_in;
assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0
assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0
assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CLKIN1_INVERTED_REG !== 1'b0) && (IS_CLKIN1_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-143] IS_CLKIN1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN1_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifndef XIL_XECLIB
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
`endif
wire CDDCDONE;
wire DRDY;
wire PSDONE;
wire CLKFBSTOPPED;
wire CLKINSTOPPED;
wire [15:0] DO;
MMCME3_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CDDCDONE (CDDCDONE),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(CLKFBSTOPPED),
.CLKINSTOPPED(CLKINSTOPPED),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (DO),
.DRDY (DRDY),
.LOCKED (LOCKED),
.PSDONE(PSDONE),
.CDDCREQ (1'b0),
.CLKFBIN (CLKFBIN_in),
.CLKIN1 (CLKIN1_in),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN_in),
.RST (RST_in)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2016 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// Special cases of "string parameters" :
// This table compares obtain results from big-3 simulators to Verilator
// expected behavior. Base specified integer literals are also included as
// string detection may impact results for such cases.
//
// | Option/Param file | simulator 1 | simulator 2 | simulator 3 | verilator |
// |---------------------|-------------|-------------|-------------|-------------|
// | -gC0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD |
// | -gC1=\"AB\ CD\" | AB CD | UNSUPPORTED | UNSUPPORTED | AB CD |
// | -gC2="\"AB CD\"" | AB CD | AB CD | AB CD | AB CD |
// | -gC3="\"AB\ CD\"" | AB CD | AB\\ CD | AB CD | AB CD |
// | -gC4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D|
// | -gC5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D|
// | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D|
// | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED |
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); $stop; end while(0);
module t;
parameter string1 = "Original String";
parameter string2 = "Original String";
parameter string11 = "Original String";
parameter string12 = "Original String";
parameter string21 = "Original String";
parameter string22 = "Original String";
parameter real11 = 0.1;
parameter real12 = 0.1;
parameter real21 = 0.1;
parameter real22 = 0.1;
parameter real31 = 0.1;
parameter real32 = 0.1;
parameter real41 = 0.1;
parameter real42 = 0.1;
parameter real51 = 0.1;
parameter real52 = 0.1;
parameter int11 = 1;
parameter int12 = 1;
parameter int21 = 1;
parameter int22 = 1;
parameter int31 = 1;
parameter int32 = 1;
parameter int41 = 1;
parameter int42 = 1;
parameter int51 = 1;
parameter int52 = 1;
parameter int61 = 1;
parameter int62 = 1;
parameter int71 = 1;
parameter int72 = 1;
initial begin
`check(string1,"New String");
`check(string2,"New String");
`check(string11,"New String");
`check(string12,"New String");
`check(string21,"New String");
`check(string22,"New String");
`check(real11,0.2);
`check(real12,0.2);
`check(real21,400);
`check(real22,400);
`check(real31,20);
`check(real32,20);
`check(real41,582.5);
`check(real42,582.5);
`check(real51,145.5);
`check(real52,145.5);
`check(int11,16);
`check(int12,16);
`check(int21,16);
`check(int22,16);
`check(int31,123);
`check(int32,123);
`check(int41,32'hdeadbeef);
`check(int42,32'hdeadbeef);
`check(int51,32'hdeadbeef);
`check(int52,32'hdeadbeef);
`check(int61,32'hdeadbeef);
`check(int62,32'hdeadbeef);
`check(int71,-1000);
`check(int72,-1000);
// Check parameter assigned simple integer literal is signed
if ((int11 << 27) >>> 31 != -1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_TB_V
`define SKY130_FD_SC_HDLL__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_debug_if.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core debug interface. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/12/02 ////
//// (See log for the revision history) ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.3 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.2 2001/12/12 22:17:30 gorban
// some synthesis bugs fixed
//
// Revision 1.1 2001/12/04 21:14:16 gorban
// committed the debug interface file
//
`include "uart_defines.v"
module uart_debug_if (/*AUTOARG*/
// Outputs
wb_dat32_o,
// Inputs
wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
lsr, rf_count, tf_count, tstate, rstate
) ;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
output [31:0] wb_dat32_o;
input [3:0] ier;
input [3:0] iir;
input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
input [4:0] mcr;
input [7:0] lcr;
input [7:0] msr;
input [7:0] lsr;
input [`UART_FIFO_COUNTER_W-1:0] rf_count;
input [`UART_FIFO_COUNTER_W-1:0] tf_count;
input [2:0] tstate;
input [3:0] rstate;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
reg [31:0] wb_dat32_o;
always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
or rf_count or rstate or tf_count or tstate or wb_adr_i)
case (wb_adr_i)
// 8 + 8 + 4 + 4 + 8
5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
// 5 + 2 + 5 + 4 + 5 + 3
5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
default: wb_dat32_o = 0;
endcase // case(wb_adr_i)
endmodule // uart_debug_if
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_MNC_readST for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_MNC_readST
// Module Name: NPCG_Toggle_MNC_readST
// File Name: NPCG_Toggle_MNC_readST.v
//
// Version: v1.0.0
//
// Description: Read status execution FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_MNC_readST
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oReadData ,
oReadLast ,
oReadValid ,
iReadReady ,
iWaySelect ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData ,
iPM_ReadData ,
iPM_ReadLast ,
iPM_ReadValid ,
oPM_ReadReady
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output [31:0] oReadData ;
output oReadLast ;
output oReadValid ;
input iReadReady ;
input [NumberOfWays - 1:0] iWaySelect ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
input [31:0] iPM_ReadData ;
input iPM_ReadLast ;
input iPM_ReadValid ;
output oPM_ReadReady ;
// FSM Parameters/Wires/Regs
localparam rST_FSM_BIT = 9; // read STatus
localparam rST_RESET = 9'b000000001;
localparam rST_READY = 9'b000000010;
localparam rST_PBRIssue = 9'b000000100; // capture, PBR start
localparam rST_CALIssue = 9'b000001000; // CAL start ready
localparam rST_CALData0 = 9'b000010000; // CA data
localparam rST_Timer1Issue = 9'b000100000; // Timer1 start ready
localparam rST_DataInIssue = 9'b001000000; // DI start ready
localparam rST_Timer2Issue = 9'b010000000; // Timer2 start ready
localparam rST_WAITDone = 9'b100000000; // wait for request done
reg [rST_FSM_BIT-1:0] r_rST_cur_state ;
reg [rST_FSM_BIT-1:0] r_rST_nxt_state ;
// Internal Wires/Regs
reg [4:0] rSourceID ;
reg rCMDReady ;
reg [NumberOfWays - 1:0] rWaySelect ;
wire wLastStep ;
reg [7:0] rPM_PCommand ;
reg [2:0] rPM_PCommandOption ;
reg [15:0] rPM_NumOfData ;
reg rPM_CASelect ;
reg [7:0] rPM_CAData ;
wire wPCGStart ;
wire wCapture ;
wire wPMReady ;
wire wPBRReady ;
wire wPBRStart ;
wire wPBRDone ;
wire wCALReady ;
wire wCALStart ;
wire wCALDone ;
wire wTMReady ;
wire wTMStart ;
wire wTMDone ;
wire wDIReady ;
wire wDIStart ;
wire wDIDone ;
// Control Signals
// Flow Contorl
assign wPCGStart = (iOpcode[5:0] == 6'b101001) & (iTargetID[4:0] == 5'b00101) & iCMDValid;
assign wCapture = (r_rST_cur_state[rST_FSM_BIT-1:0] == rST_READY);
assign wPMReady = (iPM_Ready[6:0] == 7'b1111111);
assign wPBRReady = wPMReady;
assign wPBRStart = wPBRReady & rPM_PCommand[6];
assign wPBRDone = iPM_LastStep[6];
assign wCALReady = wPMReady;
assign wCALStart = wCALReady & rPM_PCommand[3];
assign wCALDone = iPM_LastStep[3];
assign wTMReady = wPMReady;
assign wTMStart = wTMReady & rPM_PCommand[0];
assign wTMDone = iPM_LastStep[0];
assign wDIReady = wPMReady;
assign wDIStart = wDIReady & rPM_PCommand[1];
assign wDIDone = iPM_LastStep[1];
wire iCEHold;
assign iCEHold = 1'b1;
assign wLastStep = ((r_rST_cur_state[rST_FSM_BIT-1:0] == rST_WAITDone) & wTMDone & iCEHold);
// FSM: read STatus
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
r_rST_cur_state <= rST_RESET;
end else begin
r_rST_cur_state <= r_rST_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (r_rST_cur_state)
rST_RESET: begin
r_rST_nxt_state <= rST_READY;
end
rST_READY: begin
r_rST_nxt_state <= (wPCGStart)? rST_PBRIssue:rST_READY;
end
rST_PBRIssue: begin
r_rST_nxt_state <= (wPBRStart)? rST_CALIssue:rST_PBRIssue;
end
rST_CALIssue: begin
r_rST_nxt_state <= (wPBRDone & wCALStart)? rST_CALData0:rST_CALIssue;
end
rST_CALData0: begin
r_rST_nxt_state <= rST_Timer1Issue;
end
rST_Timer1Issue: begin
r_rST_nxt_state <= (wCALDone & wTMStart)? rST_DataInIssue:rST_Timer1Issue;
end
rST_DataInIssue: begin
r_rST_nxt_state <= (wTMDone & wDIStart)? rST_Timer2Issue:rST_DataInIssue;
end
rST_Timer2Issue: begin
r_rST_nxt_state <= (wDIDone & wTMStart)? rST_WAITDone:rST_Timer2Issue;
end
rST_WAITDone: begin
r_rST_nxt_state <= (wTMDone)? rST_READY:rST_WAITDone;
end
default:
r_rST_nxt_state <= rST_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end else begin
case (r_rST_nxt_state)
rST_RESET: begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_READY: begin
rSourceID[4:0] <= 0;
rCMDReady <= 1;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_PBRIssue: begin
rSourceID[4:0] <= (wCapture)? iSourceID[4:0]:rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= (wCapture)? iWaySelect[NumberOfWays - 1:0]:rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0100_0000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_CALIssue: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_1000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 1'b0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_CALData0: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 1'b0;
rPM_CAData[7:0] <= 8'h70;
end
rST_Timer1Issue: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0001;
rPM_PCommandOption[2:0] <= 3'b001; //CE on
rPM_NumOfData[15:0] <= 16'h0009; // 9 -> 10 cycle -> 100 ns
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_DataInIssue: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0010;
rPM_PCommandOption[2:0] <= 3'b000; // byte access
rPM_NumOfData[15:0] <= 16'h0000; // 0 -> 1
//rPM_NumOfData[15:0] <= 16'h0001; // 1 -> 2
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_Timer2Issue: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0001;
rPM_PCommandOption[2:0] <= 3'b100;
rPM_NumOfData[15:0] <= 16'd3; // 3 -> 4 cycle -> 40 ns
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
rST_WAITDone: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[0:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
end
endcase
end
end
// Output
assign oCMDReady = rCMDReady;
assign oStart = wPCGStart;
assign oLastStep = wLastStep;
assign oPM_PCommand[7:0] = { 1'b0, wPBRStart, 2'b00, wCALStart, 1'b0, wDIStart, wTMStart };
assign oPM_PCommandOption[2:0] = rPM_PCommandOption[2:0];
assign oPM_TargetWay[NumberOfWays - 1:0] = rWaySelect[NumberOfWays - 1:0];
assign oPM_NumOfData[15:0] = rPM_NumOfData[15:0];
assign oPM_CASelect = rPM_CASelect;
assign oPM_CAData[7:0] = rPM_CAData[7:0];
// Data Read Channel
assign oReadData[31:0] = { iPM_ReadData[30:0], 1'b1 };
assign oReadLast = iPM_ReadLast;
assign oReadValid = iPM_ReadValid;
assign oPM_ReadReady = iReadReady;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_com.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_com ();
/* Local variables */
reg [31:0] rx_file_ptr;
reg [7:0] frame_store_rx[5119:0];
integer frame_store_rx_idx;
reg [31:0] tx_file_ptr;
reg [7:0] frame_store_tx[5119:0];
integer frame_store_tx_idx;
reg [31:0] log_file_ptr;
integer _frame_store_idx;
event rcvd_cpld, rcvd_memrd, rcvd_memwr;
event rcvd_cpl, rcvd_memrd64, rcvd_memwr64;
event rcvd_msg, rcvd_msgd, rcvd_cfgrd0;
event rcvd_cfgwr0, rcvd_cfgrd1, rcvd_cfgwr1;
event rcvd_iord, rcvd_iowr;
initial begin
frame_store_rx_idx = 0;
frame_store_tx_idx = 0;
rx_file_ptr = $fopen("rx.dat");
if (!rx_file_ptr) begin
$write("ERROR: Could not open rx.dat.\n");
$finish;
end
tx_file_ptr = $fopen("tx.dat");
if (!tx_file_ptr) begin
$write("ERROR: Could not open tx.dat.\n");
$finish;
end
end
/************************************************************
Task : TSK_PARSE_FRAME
Inputs : None
Outputs : None
Description : Parse frame data
*************************************************************/
task TSK_PARSE_FRAME;
input log_file;
reg [1:0] fmt;
reg [4:0] f_type;
reg [2:0] traffic_class;
reg td;
reg ep;
reg [1:0] attr;
reg [9:0] length;
reg payload;
reg [15:0] requester_id;
reg [15:0] completer_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [7:0] message_code;
reg [31:0] address_low;
reg [31:0] address_high;
reg [9:0] register_address;
reg [2:0] completion_status;
reg [31:0] _log_file_ptr;
integer _frame_store_idx;
begin
if (log_file == `RX_LOG)
_log_file_ptr = rx_file_ptr;
else
_log_file_ptr = tx_file_ptr;
if (log_file == `RX_LOG) begin
_frame_store_idx = frame_store_rx_idx;
frame_store_rx_idx = 0;
end else begin
_frame_store_idx = frame_store_tx_idx;
frame_store_tx_idx = 0;
end
if (log_file == `RX_LOG) begin
$display("[%t] : TSK_PARSE_FRAME on Receive", $realtime);
end
else begin
$display("[%t] : TSK_PARSE_FRAME on Transmit", $realtime);
end
TSK_DECIPHER_FRAME (fmt, f_type, traffic_class, td, ep, attr, length, log_file);
// decode the packets received based on fmt and f_type
casex({fmt, f_type})
`PCI_EXP_MEM_READ32 : begin
$fdisplay(_log_file_ptr, "[%t] : Memory Read-32 Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_memrd;
end
`PCI_EXP_IO_READ : begin
$fdisplay(_log_file_ptr, "[%t] : IO Read Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_iord;
end
`PCI_EXP_CFG_READ0 : begin
$fdisplay(_log_file_ptr, "[%t] : Config Read Type 0 Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_cfgrd0;
end
`PCI_EXP_COMPLETION_WO_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Completion Without Data Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_cpl;
end
`PCI_EXP_MEM_READ64: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Read-64 Frame \n", $time);
payload = 0;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_memrd64;
end
`PCI_EXP_MSG_NODATA: begin
$fdisplay(_log_file_ptr, "[%t] : Message With No Data Frame \n", $time);
payload = 0;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_msg;
end
`PCI_EXP_MEM_WRITE32: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Write-32 Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_memwr;
end
`PCI_EXP_IO_WRITE: begin
$fdisplay(_log_file_ptr, "[%t] : IO Write Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_iowr;
end
`PCI_EXP_CFG_WRITE0: begin
$fdisplay(_log_file_ptr, "[%t] : Config Write Type 0 Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_cfgwr0;
end
`PCI_EXP_COMPLETION_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Completion With Data Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_cpld;
end
`PCI_EXP_MEM_WRITE64: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Write-64 Frame \n", $time);
payload = 1;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_memwr64;
end
`PCI_EXP_MSG_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Message With Data Frame \n", $time);
payload = 1;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_msgd;
end
default: begin
$fdisplay(_log_file_ptr, "[%t] : Not a valid frame \n", $time);
$display(_log_file_ptr, "[%t] : Received an invalid frame \n", $time);
$finish(2);
end
endcase
end
endtask // TSK_PARSE_FRAME
/************************************************************
Task : TSK_DECIPHER_FRAME
Inputs : None
Outputs : fmt, f_type, traffic_class, td, ep, attr, length
Description : Deciphers frame
*************************************************************/
task TSK_DECIPHER_FRAME;
output [1:0] fmt;
output [4:0] f_type;
output [2:0] traffic_class;
output td;
output ep;
output [1:0] attr;
output [9:0] length;
input txrx;
begin
fmt = (txrx ? frame_store_tx[0] : frame_store_rx[0]) >> 5;
f_type = txrx ? frame_store_tx[0] : frame_store_rx[0];
traffic_class = (txrx ? frame_store_tx[1] : frame_store_rx[1]) >> 4;
td = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 7;
ep = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 6;
attr = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 4;
length = (txrx ? frame_store_tx[2] : frame_store_rx[2]);
length = (length << 8) | (txrx ? frame_store_tx[3] : frame_store_rx[3]);
end
endtask // TSK_DECIPHER_FRAME
/************************************************************
Task : TSK_3DW
Inputs : fmt, f_type, traffic_class, td, ep, attr, length,
payload, _frame_store_idx
Outputs : None
Description : Gets variables and prints frame
*************************************************************/
task TSK_3DW;
input [1:0] fmt;
input [4:0] f_type;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input payload;
input [31:0] _frame_store_idx;
input [31:0] _log_file_ptr;
input txrx;
reg [15:0] requester_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [31:0] address_low;
reg [15:0] completer_id;
reg [9:0] register_address;
reg [2:0] completion_status;
reg [31:0] dword_data; // this will be used to recontruct bytes of data and sent to tx_app
integer _i;
begin
$fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(_log_file_ptr, "\t TD: %h", td);
$fdisplay(_log_file_ptr, "\t EP: %h", ep);
$fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
casex({fmt, f_type})
`PCI_EXP_CFG_READ0,
`PCI_EXP_CFG_WRITE0: begin
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
completer_id = {txrx ? frame_store_tx[8] : frame_store_rx[8], txrx ? frame_store_tx[9] : frame_store_rx[9]};
register_address = txrx ? frame_store_tx[10] : frame_store_rx[10];
register_address = (register_address << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
$fdisplay(_log_file_ptr, "\t Register Address: 0x%h \n", register_address);
if (payload == 1) begin
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
`PCI_EXP_COMPLETION_WO_DATA,
`PCI_EXP_COMPLETION_DATA: begin
completer_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
completion_status = txrx ? (frame_store_tx[6] >> 5) : (frame_store_rx[6] >> 5);
requester_id = txrx ? {frame_store_tx[8], frame_store_tx[9]} : {frame_store_rx[8], frame_store_rx[9]};
tag = txrx ? frame_store_tx[10] : frame_store_rx[10];
$fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
$fdisplay(_log_file_ptr, "\t Completion Status: 0x%h", completion_status);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h ", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h \n", tag);
if (payload == 1) begin
dword_data = 32'h0000_0000;
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
if (!txrx) begin // if we are called from rx
dword_data = dword_data >> 8; // build a dword to send to tx app
dword_data = dword_data | {frame_store_rx[_i], 24'h00_0000};
end
end
`TX_TASKS.TSK_SET_READ_DATA(4'hf,dword_data); // send the data to the tx_app
end
end
// memory reads, io reads, memory writes and io writes
default: begin
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
address_low = txrx ? frame_store_tx[8] : frame_store_rx[8];
address_low = (address_low << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", (txrx ? frame_store_tx[_i] : frame_store_rx[_i]));
end
end
end
endcase
end
endtask // TSK_3DW
/************************************************************
Task : TSK_4DW
Inputs : fmt, f_type, traffic_class, td, ep, attr, length
payload, _frame_store_idx
Outputs : None
Description : Gets variables and prints frame
*************************************************************/
task TSK_4DW;
input [1:0] fmt;
input [4:0] f_type;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input payload;
input [31:0] _frame_store_idx;
input [31:0] _log_file_ptr;
input txrx;
reg [15:0] requester_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [7:0] message_code;
reg [31:0] address_high;
reg [31:0] address_low;
reg [2:0] msg_type;
integer _i;
begin
$fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(_log_file_ptr, "\t TD: %h", td);
$fdisplay(_log_file_ptr, "\t EP: %h", ep);
$fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
message_code = txrx ? frame_store_tx[7] : frame_store_rx[7];
address_high = txrx ? frame_store_tx[8] : frame_store_rx[8];
address_high = (address_high << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
address_high = (address_high << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
address_high = (address_high << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
address_low = txrx ? frame_store_tx[12] : frame_store_rx[12];
address_low = (address_low << 8) | (txrx ? frame_store_tx[13] : frame_store_rx[13]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[14] : frame_store_rx[14]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[15] : frame_store_rx[15]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
casex({fmt, f_type})
`PCI_EXP_MEM_READ64,
`PCI_EXP_MEM_WRITE64: begin
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
`PCI_EXP_MSG_NODATA,
`PCI_EXP_MSG_DATA: begin
msg_type = f_type;
$fdisplay(_log_file_ptr, "\t Message Type: 0x%h", msg_type);
$fdisplay(_log_file_ptr, "\t Message Code: 0x%h", message_code);
$fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
endcase
end
endtask // TSK_4DW
/************************************************************
Task : TSK_READ_DATA
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_READ_DATA;
input last;
input txrx;
input [63:0] trn_d;
input [3:0] trn_rem;
integer _i;
reg [7:0] _byte;
reg [63:0] _msk;
reg [3:0] _rem;
begin
_msk = 64'hff00000000000000;
_rem = last ? ((trn_rem == 8'h0F) ? 4 : 8) : 8;
for (_i = 0; _i < _rem; _i = _i + 1) begin
_byte = (trn_d & (_msk >> (_i * 8))) >> (((7) - _i) * 8);
if (txrx) begin
board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
end else begin
board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
end
end
end
endtask // TSK_READ_DATA
/************************************************************
Task : TSK_READ_DATA_128
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_READ_DATA_128;
input first;
input last;
input txrx;
input [127:0] trn_d;
input [1:0] trn_rem;
integer _i;
reg [7:0] _byte;
reg [127:0] _msk;
reg [4:0] _rem;
reg [3:0] _strt_pos;
begin
_msk = (first && trn_rem[1]) ? 128'h0000000000000000ff00000000000000 : 128'hff000000000000000000000000000000;
_rem = first ? (last ? ((trn_rem == 2'b01) ? 12 : 16) : 8) : (last ? (trn_rem[1] ? (trn_rem[0] ? 4 : 8) : (trn_rem[0] ? 12 : 16)) : 16);
_strt_pos = (first && trn_rem[1]) ? 4'd7 : 4'd15;
for (_i = 0; _i < _rem; _i = _i + 1) begin
_byte = (trn_d & (_msk >> (_i * 8))) >> (((_strt_pos) - _i) * 8);
if (txrx) begin
board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
end else begin
board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
end
end
end
endtask // TSK_READ_DATA_128
`include "pci_exp_expect_tasks.v"
endmodule // pci_exp_usrapp_com
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for generics without a default value.
module vhdl_generic_default_test;
logic a;
vhdl_generic_default #(.\value (1'b1))dut(a);
initial begin
if(a !== 1'b1) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:09:00 02/19/2015
// Design Name:
// Module Name: fauxfs_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fauxfs_top(
// SDHC wishbone slave
input wb_sdhc_clk_i,
input wb_sdhc_rst_i,
input [31:0] wb_sdhc_adr_i,
input [31:0] wb_sdhc_dat_i,
input [3:0] wb_sdhc_sel_i,
input wb_sdhc_we_i,
input [1:0] wb_sdhc_bte_i,
input [2:0] wb_sdhc_cti_i,
input wb_sdhc_cyc_i,
input wb_sdhc_stb_i,
output reg wb_sdhc_ack_o,
output wb_sdhc_rty_o,
output wb_sdhc_err_o,
output reg [31:0] wb_sdhc_dat_o,
// CPU wishbone slave
input wb_cpu_clk_i,
input wb_cpu_rst_i,
input [31:0] wb_cpu_adr_i,
input [31:0] wb_cpu_dat_i,
input [3:0] wb_cpu_sel_i,
input wb_cpu_we_i,
input [1:0] wb_cpu_bte_i,
input [2:0] wb_cpu_cti_i,
input wb_cpu_cyc_i,
input wb_cpu_stb_i,
output reg wb_cpu_ack_o,
output wb_cpu_rty_o,
output wb_cpu_err_o,
output reg [31:0] wb_cpu_dat_o,
output wfile_dat_int_o,
output rfile_ack_int_o
);
`include "wb_common.v"
// common memories
reg [31:0] rfile_dat_mem[511:0];
reg [31:0] rfile_ack_mem[3:0];
reg [31:0] wfile_dat_mem[511:0];
reg [31:0] wfile_ack_mem[3:0];
// CPU side
reg wfile_dat_int_cpu, rfile_ack_int_cpu;
reg wfile_dat_clr_cpu, rfile_ack_clr_cpu;
assign wfile_dat_int_o = wfile_dat_int_cpu;
assign rfile_ack_int_o = rfile_ack_int_cpu;
assign wb_cpu_rty_o = 0;
assign wb_cpu_err_o = 0;
reg [12:0] cpu_adr_r;
wire [12:0] cpu_next_adr;
wire cpu_valid = wb_cpu_cyc_i & wb_cpu_stb_i;
reg cpu_valid_r;
wire cpu_new_cycle = cpu_valid & !cpu_valid_r;
assign cpu_next_adr = wb_next_adr(cpu_adr_r, wb_cpu_cti_i, wb_cpu_bte_i, 32);
wire [12:0] cpu_adr = cpu_new_cycle ? wb_cpu_adr_i[12:0] : cpu_next_adr;
always@(posedge wb_cpu_clk_i)
begin
cpu_adr_r <= cpu_adr;
cpu_valid_r <= cpu_valid;
wb_cpu_ack_o <= cpu_valid & (!((wb_cpu_cti_i == 3'b000) | (wb_cpu_cti_i == 3'b111)) | !wb_cpu_ack_o);
if(wb_cpu_rst_i)
begin
cpu_adr_r <= 0;
cpu_valid_r <= 0;
wb_cpu_ack_o <= 0;
end
end
always @(posedge wb_cpu_clk_i)
begin
wfile_dat_clr_cpu <= wfile_dat_clr_cpu & wfile_dat_int_cpu;
rfile_ack_clr_cpu <= rfile_ack_clr_cpu & rfile_ack_int_cpu;
if(wb_cpu_rst_i)
begin
wfile_dat_clr_cpu <= 0;
rfile_ack_clr_cpu <= 0;
end
else if(cpu_valid)
begin
case(cpu_adr[12:11])
2'b00: wb_cpu_dat_o <= wfile_dat_mem[cpu_adr[10:2]];
2'b01:
begin
wb_cpu_dat_o <= rfile_dat_mem[cpu_adr[10:2]];
if(wb_cpu_we_i & wb_cpu_sel_i[0])
rfile_dat_mem[cpu_adr[10:2]][ 7: 0] <= wb_cpu_dat_i[ 7: 0];
if(wb_cpu_we_i & wb_cpu_sel_i[1])
rfile_dat_mem[cpu_adr[10:2]][15: 8] <= wb_cpu_dat_i[15: 8];
if(wb_cpu_we_i & wb_cpu_sel_i[2])
rfile_dat_mem[cpu_adr[10:2]][23:16] <= wb_cpu_dat_i[23:16];
if(wb_cpu_we_i & wb_cpu_sel_i[3])
rfile_dat_mem[cpu_adr[10:2]][31:24] <= wb_cpu_dat_i[31:24];
end
2'b10:
begin
case(cpu_adr[10:4])
7'h00:
begin
wb_cpu_dat_o <= wfile_ack_mem[cpu_adr[3:2]];
if(wb_cpu_we_i & wb_cpu_sel_i[0])
wfile_ack_mem[cpu_adr[3:2]][ 7: 0] <= wb_cpu_dat_i[ 7: 0];
if(wb_cpu_we_i & wb_cpu_sel_i[1])
wfile_ack_mem[cpu_adr[3:2]][15: 8] <= wb_cpu_dat_i[15: 8];
if(wb_cpu_we_i & wb_cpu_sel_i[2])
wfile_ack_mem[cpu_adr[3:2]][23:16] <= wb_cpu_dat_i[23:16];
if(wb_cpu_we_i & wb_cpu_sel_i[3])
wfile_ack_mem[cpu_adr[3:2]][31:24] <= wb_cpu_dat_i[31:24];
end
7'h01:
wb_cpu_dat_o <= rfile_ack_mem[cpu_adr[3:2]];
7'h02:
begin
wb_cpu_dat_o <= { 30'h0, rfile_ack_int_cpu, wfile_dat_int_cpu };
if(wb_cpu_we_i & wb_cpu_sel_i[0])
begin
wfile_dat_clr_cpu <= wb_cpu_dat_i[0];
rfile_ack_clr_cpu <= wb_cpu_dat_i[1];
end
end
default: wb_cpu_dat_o <= 32'h0;
endcase
end
2'b11: wb_cpu_dat_o <= 32'h0;
endcase
end
end
// SDHC side
assign wb_sdhc_rty_o = 0;
assign wb_sdhc_err_o = 0;
reg wfile_dat_int_sdhc, rfile_ack_int_sdhc;
reg wfile_dat_clr_sdhc, rfile_ack_clr_sdhc;
reg [31:0] sdhc_adr_r;
wire [31:0] sdhc_next_adr;
// only ack if we're being addressed (< 2MB)
// FTL will also be tied to this wishbone bus but will only ack when
// receiving requests >2MB
wire sdhc_valid = wb_sdhc_cyc_i & wb_sdhc_stb_i & ((wb_sdhc_adr_i < 32'h200000));
reg sdhc_valid_r;
wire sdhc_new_cycle = sdhc_valid & !sdhc_valid_r;
assign sdhc_next_adr = wb_next_adr(sdhc_adr_r, wb_sdhc_cti_i, wb_sdhc_bte_i, 32);
wire [31:0] sdhc_adr = sdhc_new_cycle ? wb_sdhc_adr_i[31:0] : sdhc_next_adr;
always@(posedge wb_sdhc_clk_i)
begin
sdhc_adr_r <= sdhc_adr;
sdhc_valid_r <= sdhc_valid;
wb_sdhc_ack_o <= sdhc_valid & (!((wb_sdhc_cti_i == 3'b000) | (wb_sdhc_cti_i == 3'b111)) | !wb_sdhc_ack_o);
if(wb_sdhc_rst_i)
begin
sdhc_adr_r <= 0;
sdhc_valid_r <= 0;
wb_sdhc_ack_o <= 0;
end
end
wire mbr_rom_sel = ((sdhc_adr & 32'hfffffe00) == 32'h00000000);
wire fat_rom_sel = ((sdhc_adr & 32'hfffff000) == 32'h00100000);
wire rfile_sel = ((sdhc_adr & 32'hfffff800) == 32'h00105000);
wire wfile_sel = ((sdhc_adr & 32'hfffff800) == 32'h00105800);
always @(posedge wb_sdhc_clk_i)
begin
rfile_ack_int_sdhc <= rfile_ack_int_sdhc & ~rfile_ack_clr_sdhc;
wfile_dat_int_sdhc <= wfile_dat_int_sdhc & ~wfile_dat_clr_sdhc;
if(wb_sdhc_rst_i)
begin
rfile_ack_int_sdhc <= 0;
wfile_dat_int_sdhc <= 0;
end
else if(sdhc_valid)
begin
wb_sdhc_dat_o <= 32'h0;
if(mbr_rom_sel)
begin
case(sdhc_adr[8:2])
`include "mbr_rom.vh"
default: wb_sdhc_dat_o <= 32'h0;
endcase
end
if(fat_rom_sel)
begin
case(sdhc_adr[11:2])
`include "fat_rom.vh"
default: wb_sdhc_dat_o <= 32'h0;
endcase
end
if(rfile_sel)
begin
wb_sdhc_dat_o <= rfile_dat_mem[sdhc_adr[10:2]];
if(wb_sdhc_we_i && ((sdhc_adr & 32'hfffffff0) == 32'h00105000))
begin
if((sdhc_adr & 32'hfffffffc) == 32'h0010500c)
rfile_ack_int_sdhc <= 1;
rfile_ack_mem[sdhc_adr[3:2]] <= wb_sdhc_dat_i;
end
end
if(wfile_sel)
begin
wb_sdhc_dat_o <= wfile_ack_mem[sdhc_adr[3:2]];
if(wb_sdhc_we_i)
begin
if((sdhc_adr & 32'hfffffffc) == 32'h00105ffc)
wfile_dat_int_sdhc <= 1;
wfile_dat_mem[sdhc_adr[10:2]] <= wb_sdhc_dat_i;
end
end
end
end
// CDC stuff
reg wfile_dat_int_cpu_buf, rfile_ack_int_cpu_buf;
reg wfile_dat_clr_sdhc_buf, rfile_ack_clr_sdhc_buf;
always @(posedge wb_cpu_clk_i)
begin
wfile_dat_int_cpu <= wfile_dat_int_cpu_buf;
wfile_dat_int_cpu_buf <= wfile_dat_int_sdhc;
if(wb_cpu_rst_i)
begin
wfile_dat_int_cpu <= 0;
wfile_dat_int_cpu_buf <= 0;
end
end
always @(posedge wb_cpu_clk_i)
begin
rfile_ack_int_cpu <= rfile_ack_int_cpu_buf;
rfile_ack_int_cpu_buf <= rfile_ack_int_sdhc;
if(wb_cpu_rst_i)
begin
rfile_ack_int_cpu <= 0;
rfile_ack_int_cpu_buf <= 0;
end
end
always @(posedge wb_sdhc_clk_i)
begin
wfile_dat_clr_sdhc <= wfile_dat_clr_sdhc_buf;
wfile_dat_clr_sdhc_buf <= wfile_dat_clr_cpu;
if(wb_cpu_rst_i)
begin
wfile_dat_clr_sdhc <= 0;
wfile_dat_clr_sdhc_buf <= 0;
end
end
always @(posedge wb_sdhc_clk_i)
begin
rfile_ack_clr_sdhc <= rfile_ack_clr_sdhc_buf;
rfile_ack_clr_sdhc_buf <= rfile_ack_clr_cpu;
if(wb_cpu_rst_i)
begin
rfile_ack_clr_sdhc <= 0;
rfile_ack_clr_sdhc_buf <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_1_V
`define SKY130_FD_SC_HD__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_1_V
|
// Used for 32 bit data axi ports like GP0/GP1
module axi_master32_stub(
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [31:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [31:0] M2S_AXI_WDATA,
output [3:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read Transaction
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 32'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 32'b0;
assign M2S_AXI_WSTRB = 4'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule : axi_master32_stub
/*
axi_master_stub axi_master_XXX_stub (
.M2S_AXI_ACLK(M2S_XXX_AXI_ACLK),
//Read Transaction
.M2S_AXI_ARVALID(M2S_XXX_AXI_ARVALID),
.M2S_AXI_ARREADY(M2S_XXX_AXI_ARREADY),
.M2S_AXI_ARADDR(M2S_XXX_AXI_ARADDR[31:0]),
.M2S_AXI_ARBURST(M2S_XXX_AXI_ARBURST[1:0]),
.M2S_AXI_ARLEN(M2S_XXX_AXI_ARLEN[3:0]),
.M2S_AXI_ARSIZE(M2S_XXX_AXI_ARSIZE[1:0]),
//
.M2S_AXI_RVALID(M2S_XXX_AXI_RVALID),
.M2S_AXI_RREADY(M2S_XXX_AXI_RREADY),
.M2S_AXI_RLAST(M2S_XXX_AXI_RLAST),
.M2S_AXI_RDATA(M2S_XXX_AXI_RDATA[63:0]),
//
.M2S_AXI_RRESP(M2S_XXX_AXI_RRESP[1:0]),
// Write Transaction
.M2S_AXI_AWVALID(M2S_XXX_AXI_AWVALID),
.M2S_AXI_AWREADY(M2S_XXX_AXI_AWREADY),
.M2S_AXI_AWADDR(M2S_XXX_AXI_AWADDR[31:0]),
.M2S_AXI_AWBURST(M2S_XXX_AXI_AWBURST[1:0]),
.M2S_AXI_AWLEN(M2S_XXX_AXI_AWLEN[3:0]),
.M2S_AXI_AWSIZE(M2S_XXX_AXI_AWSIZE[1:0]),
//
.M2S_AXI_WVALID(M2S_XXX_AXI_WVALID),
.M2S_AXI_WREADY(M2S_XXX_AXI_WREADY),
.M2S_AXI_WLAST(M2S_XXX_AXI_WLAST),
.M2S_AXI_WDATA(M2S_XXX_AXI_WDATA[63:0]),
.M2S_AXI_WSTRB(M2S_XXX_AXI_WSTRB[7:0]),
//
.M2S_AXI_BVALID(M2S_XXX_AXI_BVALID),
.M2S_AXI_BREADY(M2S_XXX_AXI_BREADY),
.M2S_AXI_BRESP(M2S_XXX_AXI_BRESP[1:0])
);
*/
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
(** * IndPrinciples: Induction Principles *)
(** With the Curry-Howard correspondence and its realization in Coq in
mind, we can now take a deeper look at induction principles. *)
Set Warnings "-notation-overridden,-parsing".
From LF Require Export ProofObjects.
(* ################################################################# *)
(** * Basics *)
(** Every time we declare a new [Inductive] datatype, Coq
automatically generates an _induction principle_ for this type.
This induction principle is a theorem like any other: If [t] is
defined inductively, the corresponding induction principle is
called [t_ind]. Here is the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** The [induction] tactic is a straightforward wrapper that, at its
core, simply performs [apply t_ind]. To see this more clearly,
let's experiment with directly using [apply nat_ind], instead of
the [induction] tactic, to carry out some proofs. Here, for
example, is an alternate proof of a theorem that we saw in the
[Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *) simpl. intros n' IHn'. rewrite -> IHn'.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting.
First, in the induction step of the proof (the ["S"] case), we
have to do a little bookkeeping manually (the [intros]) that
[induction] does automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. By contrast, the
[induction] tactic works either with a variable in the context or
a quantified variable in the goal.
These conveniences make [induction] nicer to use in practice than
applying induction principles like [nat_ind] directly. But it is
important to realize that, modulo these bits of bookkeeping,
applying [nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, standard, optional (plus_one_r')
Complete this proof without using the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. Although of
course we don't need induction to prove properties of
non-recursive datatypes, the idea of an induction principle still
makes sense for them: it gives a way to prove that a property
holds for all values of the type.
These generated principles follow a similar pattern. If we define
a type [t] with constructors [c1] ... [cn], Coq generates a
theorem with this shape:
t_ind : forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... -> ...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes
| no.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, standard, optional (rgb)
Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red
| green
| blue.
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil
| ncons (n : nat) (l : natlist).
Check natlist_ind.
(* ===> (modulo a little variable renaming)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist),
P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, standard, optional (natlist1)
Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1
| nsnoc1 (l : natlist1) (n : nat).
(** Now what will the induction principle look like?
[] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1] ... [an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle says:
- "For all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of type
[t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, standard, optional (byntree_ind)
Write out the induction principle that Coq will generate for the
following datatype. (Again, write down your answer on paper or
type it into a comment, and then compare it with what Coq
prints.) *)
Inductive byntree : Type :=
| bempty
| bleaf (yn : yesno)
| nbranch (yn : yesno) (t1 t2 : byntree).
(** [] *)
(** **** Exercise: 1 star, standard, optional (ex_set)
Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(* ################################################################# *)
(** * Polymorphism *)
(** Next, what about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note that the _whole_ induction principle is parameterized on
[X]. That is, [list_ind] can be thought of as a polymorphic
function that, when applied to a type [X], gives us back an
induction principle specialized to the type [list X]. *)
(** **** Exercise: 1 star, standard, optional (tree)
Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf (x : X)
| node (t1 t2 : tree X).
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, standard, optional (mytype)
Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(** **** Exercise: 1 star, standard, optional (foo)
Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, standard, optional (foo')
Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 (l : list X) (f : foo' X)
| C2.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ################################################################# *)
(** * Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (or rather, strictly speaking, for all families of
propositions [P] indexed by a number [n]). Each time we
use this principle, we are choosing [P] to be a particular
expression of type [nat->Prop].
We can make proofs by induction more explicit by giving
this expression a name. For example, instead of stating
the theorem [mult_0_r] as "[forall n, n * 0 = 0]," we can
write it as "[forall n, P_m0r n]", where [P_m0r] is defined
as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently: *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now it is easier to see where [P_m0r] appears in the proof. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *)
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ################################################################# *)
(** * More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative... *)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
- (* n = O *) reflexivity.
- (* n = S n' *)
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
- (* n = O *) intros m. rewrite <- plus_n_O. reflexivity.
- (* n = S n' *) intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
- (* m = O *) simpl. rewrite <- plus_n_O. reflexivity.
- (* m = S m' *) simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, standard, optional (plus_explicit_prop)
Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE
[] *)
(* ################################################################# *)
(** * Induction Principles in [Prop] *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [even] are a
tiny bit more complicated. As with all induction principles, we
want to use the induction principle on [even] to prove things by
inductively considering the possible shapes that something in [even]
can have. Intuitively speaking, however, what we want to prove
are not statements about _evidence_ but statements about
_numbers_: accordingly, we want an induction principle that lets
us prove properties of numbers by induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [even]...
Inductive even : nat -> Prop :=
| ev_0 : even 0
| ev_SS : forall n : nat, even n -> even (S (S n)).
...to give rise to an induction principle that looks like this...
ev_ind_max : forall P : (forall n : nat, even n -> Prop),
P O ev_0 ->
(forall (m : nat) (E : even m),
P m E ->
P (S (S m)) (ev_SS m E)) ->
forall (n : nat) (E : even n),
P n E
... because:
- Since [even] is indexed by a number [n] (every [even] object [E] is
a piece of evidence that some particular number [n] is even),
the proposition [P] is parameterized by both [n] and [E] --
that is, the induction principle can be used to prove
assertions involving both an even number and the evidence that
it is even.
- Since there are two ways of giving evidence of evenness ([even]
has two constructors), applying the induction principle
generates two subgoals:
- We must prove that [P] holds for [O] and [ev_0].
- We must prove that, whenever [n] is an even number and [E]
is an evidence of its evenness, if [P] holds of [n] and
[E], then it also holds of [S (S n)] and [ev_SS n E].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ even numbers [n] and
evidence [E] of their evenness.
This is more flexibility than we normally need or want: it is
giving us a way to prove logical assertions where the assertion
involves properties of some piece of _evidence_ of evenness, while
all we really care about is proving properties of _numbers_ that
are even -- we are interested in assertions about numbers, not
about evidence. It would therefore be more convenient to have an
induction principle for proving propositions [P] that are
parameterized just by [n] and whose conclusion establishes [P] for
all even numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat,
even n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [even]: *)
Check even_ind.
(* ===> ev_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, even n -> P n -> P (S (S n))) ->
forall n : nat,
even n -> P n *)
(** In particular, Coq has dropped the evidence term [E] as a
parameter of the the proposition [P]. *)
(** In English, [ev_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is even, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is even and [P] holds for [n], then [P]
holds for [S (S n)]. *)
(** As expected, we can apply [ev_ind] directly instead of using
[induction]. For example, we can use it to show that [even'] (the
slightly awkward alternate definition of evenness that we saw in
an exercise in the \chap{IndProp} chapter) is equivalent to the
cleaner inductive definition [even]: *)
Theorem ev_ev' : forall n, even n -> even' n.
Proof.
apply even_ind.
- (* ev_0 *)
apply even'_0.
- (* ev_SS *)
intros m Hm IH.
apply (even'_sum 2 m).
+ apply even'_2.
+ apply IH.
Qed.
(** The precise form of an [Inductive] definition can affect the
induction principle Coq generates.
For example, in chapter [IndProp], we defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S m (H : le n m) : le n (S m).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(* ################################################################# *)
(** * Formal vs. Informal Proofs by Induction *)
(** Question: What is the relation between a formal proof of a
proposition [P] and an informal proof of the same proposition [P]?
Answer: The latter should _teach_ the reader how to produce the
former.
Question: How much detail is needed??
Unfortunately, there is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the "informal" proof will amount to just
transcribing the formal one into words). This may give the reader
the ability to reproduce the formal one for themselves, but it
probably doesn't _teach_ them anything much.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because often
writing the proof requires one or more significant insights into
the thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard work that we
went through to find the proof in the first place) plus high-level
suggestions for the more routine parts to save the reader from
spending too much time reconstructing these (e.g., what the IH says
and what must be shown in each case of an inductive proof), but not
so much detail that the main ideas are obscured.
Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief and
telegraphic. Although the ideal is somewhere in between, while one
is getting used to the style it is better to start out at the
pedantic end. Also, during the learning phase, it is probably
helpful to have a clear standard to compare against. With this in
mind, we offer two templates -- one for proofs by induction over
_data_ (i.e., where the thing we're doing induction on lives in
[Type]) and one for proofs by induction over _evidence_ (i.e.,
where the inductively defined thing lives in [Prop]). *)
(* ================================================================= *)
(** ** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if [length [] = n], then [index (S n) [] =
None].
This follows immediately from the definition of [index].
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
But this follows directly from the induction hypothesis,
picking [n'] to be [length l']. [] *)
(* ================================================================= *)
(** ** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* Wed Jan 9 12:02:46 EST 2019 *)
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_fpext_32ns_64_1
#(parameter
ID = 4,
NUM_STAGE = 1,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
feedforward_ap_fpext_0_no_dsp_32 feedforward_ap_fpext_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_decoder.v
// Title : Instruction decoder
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Support for static branch prediction. Information about
// : branch type is generated and passed on to the predictor.
// Version : 3.2
// : No change
// Version : 3.3
// : Renamed port names that conflict with keywords reserved
// : in System-Verilog.
// =============================================================================
`include "lm32_include.v"
// Index of opcode field in an instruction
`define LM32_OPCODE_RNG 31:26
`define LM32_OP_RNG 30:26
// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
`define LM32_OPCODE_ADD 5'b01101
`define LM32_OPCODE_AND 5'b01000
`define LM32_OPCODE_ANDHI 6'b011000
`define LM32_OPCODE_B 6'b110000
`define LM32_OPCODE_BI 6'b111000
`define LM32_OPCODE_BE 6'b010001
`define LM32_OPCODE_BG 6'b010010
`define LM32_OPCODE_BGE 6'b010011
`define LM32_OPCODE_BGEU 6'b010100
`define LM32_OPCODE_BGU 6'b010101
`define LM32_OPCODE_BNE 6'b010111
`define LM32_OPCODE_CALL 6'b110110
`define LM32_OPCODE_CALLI 6'b111110
`define LM32_OPCODE_CMPE 5'b11001
`define LM32_OPCODE_CMPG 5'b11010
`define LM32_OPCODE_CMPGE 5'b11011
`define LM32_OPCODE_CMPGEU 5'b11100
`define LM32_OPCODE_CMPGU 5'b11101
`define LM32_OPCODE_CMPNE 5'b11111
`define LM32_OPCODE_DIVU 6'b100011
`define LM32_OPCODE_LB 6'b000100
`define LM32_OPCODE_LBU 6'b010000
`define LM32_OPCODE_LH 6'b000111
`define LM32_OPCODE_LHU 6'b001011
`define LM32_OPCODE_LW 6'b001010
`define LM32_OPCODE_MODU 6'b110001
`define LM32_OPCODE_MUL 5'b00010
`define LM32_OPCODE_NOR 5'b00001
`define LM32_OPCODE_OR 5'b01110
`define LM32_OPCODE_ORHI 6'b011110
`define LM32_OPCODE_RAISE 6'b101011
`define LM32_OPCODE_RCSR 6'b100100
`define LM32_OPCODE_SB 6'b001100
`define LM32_OPCODE_SEXTB 6'b101100
`define LM32_OPCODE_SEXTH 6'b110111
`define LM32_OPCODE_SH 6'b000011
`define LM32_OPCODE_SL 5'b01111
`define LM32_OPCODE_SR 5'b00101
`define LM32_OPCODE_SRU 5'b00000
`define LM32_OPCODE_SUB 6'b110010
`define LM32_OPCODE_SW 6'b010110
`define LM32_OPCODE_USER 6'b110011
`define LM32_OPCODE_WCSR 6'b110100
`define LM32_OPCODE_XNOR 5'b01001
`define LM32_OPCODE_XOR 5'b00110
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_decoder (
// ----- Inputs -------
instruction,
// ----- Outputs -------
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith,
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift,
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext,
`endif
x_result_sel_logic,
`ifdef CFG_USER_ENABLED
x_result_sel_user,
`endif
x_result_sel_add,
m_result_sel_compare,
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift,
`endif
w_result_sel_load,
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul,
`endif
x_bypass_enable,
m_bypass_enable,
read_enable_0,
read_idx_0,
read_enable_1,
read_idx_1,
write_enable,
write_idx,
immediate,
branch_offset,
load,
store,
size,
sign_extend,
adder_op,
logic_op,
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction,
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
shift_left,
shift_right,
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
multiply,
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
divide,
modulus,
`endif
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
`ifdef CFG_DEBUG_ENABLED
break_opcode,
`endif
scall,
eret,
`ifdef CFG_DEBUG_ENABLED
bret,
`endif
`ifdef CFG_USER_ENABLED
user_opcode,
`endif
csr_write_enable
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
`ifdef LM32_MC_ARITHMETIC_ENABLED
output x_result_sel_mc_arith;
reg x_result_sel_mc_arith;
`endif
`ifdef LM32_NO_BARREL_SHIFT
output x_result_sel_shift;
reg x_result_sel_shift;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
output x_result_sel_sext;
reg x_result_sel_sext;
`endif
output x_result_sel_logic;
reg x_result_sel_logic;
`ifdef CFG_USER_ENABLED
output x_result_sel_user;
reg x_result_sel_user;
`endif
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
output m_result_sel_shift;
reg m_result_sel_shift;
`endif
output w_result_sel_load;
reg w_result_sel_load;
`ifdef CFG_PL_MULTIPLY_ENABLED
output w_result_sel_mul;
reg w_result_sel_mul;
`endif
output x_bypass_enable;
wire x_bypass_enable;
output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
output [`LM32_REG_IDX_RNG] read_idx_0;
wire [`LM32_REG_IDX_RNG] read_idx_0;
output read_enable_1;
wire read_enable_1;
output [`LM32_REG_IDX_RNG] read_idx_1;
wire [`LM32_REG_IDX_RNG] read_idx_1;
output write_enable;
wire write_enable;
output [`LM32_REG_IDX_RNG] write_idx;
wire [`LM32_REG_IDX_RNG] write_idx;
output [`LM32_WORD_RNG] immediate;
wire [`LM32_WORD_RNG] immediate;
output [`LM32_PC_RNG] branch_offset;
wire [`LM32_PC_RNG] branch_offset;
output load;
wire load;
output store;
wire store;
output [`LM32_SIZE_RNG] size;
wire [`LM32_SIZE_RNG] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
output [`LM32_LOGIC_OP_RNG] logic_op;
wire [`LM32_LOGIC_OP_RNG] logic_op;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
output direction;
wire direction;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
output shift_left;
wire shift_left;
output shift_right;
wire shift_right;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
output multiply;
wire multiply;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
output divide;
wire divide;
output modulus;
wire modulus;
`endif
output branch;
wire branch;
output branch_reg;
wire branch_reg;
output [`LM32_CONDITION_RNG] condition;
wire [`LM32_CONDITION_RNG] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
`ifdef CFG_DEBUG_ENABLED
output break_opcode;
wire break_opcode;
`endif
output scall;
wire scall;
output eret;
wire eret;
`ifdef CFG_DEBUG_ENABLED
output bret;
wire bret;
`endif
`ifdef CFG_USER_ENABLED
output [`LM32_USER_OPCODE_RNG] user_opcode;
wire [`LM32_USER_OPCODE_RNG] user_opcode;
`endif
output csr_write_enable;
wire csr_write_enable;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits
wire [`LM32_WORD_RNG] call_immediate; // Call immediate
wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
wire select_high_immediate; // Whether to select the high immediate
wire select_call_immediate; // Whether to select the call immediate
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Determine opcode
assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
`ifdef CFG_MC_DIVIDE_ENABLED
assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
`endif
assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
`ifdef CFG_MC_DIVIDE_ENABLED
assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
`endif
`ifdef LM32_MULTIPLY_ENABLED
assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
`endif
assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
`ifdef CFG_SIGN_EXTEND_ENABLED
assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
`endif
assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
`ifdef LM32_BARREL_SHIFT_ENABLED
assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;
`endif
assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
// Group opcodes by function
assign arith = op_add | op_sub;
assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
`ifdef LM32_BARREL_SHIFT_ENABLED
assign shift = op_sl | op_sr | op_sru;
`endif
`ifdef LM32_NO_BARREL_SHIFT
assign shift = op_sr | op_sru;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
assign shift_left = op_sl;
assign shift_right = op_sr | op_sru;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
assign sext = op_sextb | op_sexth;
`endif
`ifdef LM32_MULTIPLY_ENABLED
assign multiply = op_mul;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
assign divide = op_divu;
assign modulus = op_modu;
`endif
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
// Select pipeline multiplexor controls
always @(*)
begin
// D stage
if (call)
d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
else
d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
if (call)
d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;
else if ((instruction[31] == 1'b0) && !bra)
d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
else
d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1;
// X stage
x_result_sel_csr = `FALSE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith = `FALSE;
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift = `FALSE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext = `FALSE;
`endif
x_result_sel_logic = `FALSE;
`ifdef CFG_USER_ENABLED
x_result_sel_user = `FALSE;
`endif
x_result_sel_add = `FALSE;
if (op_rcsr)
x_result_sel_csr = `TRUE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
else if (shift_left | shift_right)
x_result_sel_mc_arith = `TRUE;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
else if (divide | modulus)
x_result_sel_mc_arith = `TRUE;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
else if (multiply)
x_result_sel_mc_arith = `TRUE;
`endif
`endif
`ifdef LM32_NO_BARREL_SHIFT
else if (shift)
x_result_sel_shift = `TRUE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
else if (sext)
x_result_sel_sext = `TRUE;
`endif
else if (logical)
x_result_sel_logic = `TRUE;
`ifdef CFG_USER_ENABLED
else if (op_user)
x_result_sel_user = `TRUE;
`endif
else
x_result_sel_add = `TRUE;
// M stage
m_result_sel_compare = cmp;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift = shift;
`endif
// W stage
w_result_sel_load = load;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul = op_mul;
`endif
end
// Set if result is valid at end of X stage
assign x_bypass_enable = arith
| logical
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
| shift_left
| shift_right
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
| multiply
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
| divide
| modulus
`endif
`ifdef LM32_NO_BARREL_SHIFT
| shift
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
| sext
`endif
`ifdef CFG_USER_ENABLED
| op_user
`endif
| op_rcsr
;
// Set if result is valid at end of M stage
assign m_bypass_enable = x_bypass_enable
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
| shift
`endif
| cmp
;
// Register file read port 0
assign read_enable_0 = ~(op_bi | op_calli);
assign read_idx_0 = instruction[25:21];
// Register file read port 1
assign read_enable_1 = ~(op_bi | op_calli | load);
assign read_idx_1 = instruction[20:16];
// Register file write port
assign write_enable = ~(bra | op_raise | store | op_wcsr);
assign write_idx = call
? 5'd29
: instruction[31] == 1'b0
? instruction[20:16]
: instruction[15:11];
// Size of load/stores
assign size = instruction[27:26];
// Whether to sign or zero extend
assign sign_extend = instruction[28];
// Set adder_op to 1 to perform a subtraction
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
// Logic operation (and, or, etc)
assign logic_op = instruction[29:26];
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
// Shift direction
assign direction = instruction[29];
`endif
// Control flow microcodes
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
`ifdef CFG_DEBUG_ENABLED
assign break_opcode = op_raise & ~instruction[2];
`endif
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
`ifdef CFG_DEBUG_ENABLED
assign bret = op_b & (instruction[25:21] == 5'd31);
`endif
`ifdef CFG_USER_ENABLED
// Extract user opcode
assign user_opcode = instruction[10:0];
`endif
// CSR read/write
assign csr_write_enable = op_wcsr;
// Extract immediate from instruction
assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
assign select_high_immediate = op_andhi | op_orhi;
assign select_call_immediate = instruction[31];
assign high_immediate = {instruction[15:0], 16'h0000};
assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
assign immediate = select_high_immediate == `TRUE
? high_immediate
: extended_immediate;
assign branch_offset = select_call_immediate == `TRUE
? call_immediate
: branch_immediate;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_1_1 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(0),
.DIN_TO(0)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[7];
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
/* ltcminer.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`ifdef NOLEDS
module ltcminer (osc_clk); // Version without LEDs for DE2-115
`else
module ltcminer (osc_clk, LEDS_out);
`endif
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
// LOCAL_MINERS determinse the number of cores (the terminology is consistent with the LX150 port)
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
input osc_clk;
`ifndef NOLEDS
output reg [7:0]LEDS_out; // Optional progress indicator
`endif
wire hash_clk;
`ifndef SIM
main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
// Virtual wire is now done here rather than in hashcore so as to support MULTICORE
`ifndef SIM
// 80 byte block header (NB this implimetation does not use midstate)
reg [255:0] data1 = 256'd0;
reg [255:0] data2 = 256'd0;
reg [127:0] data3 = 128'd0;
// final_hash=553a4b69b43913a61b42013ce210f713eaa7332e48cda1bdf3b93b10161d0876 (NOT a match)
`else
// Test data (MATCH nonce 0000318f)
reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df; // NB 0000318f is loaded into nonce
// final_hash=b303000066bd9f068aa115339cfd01cd94121ef65b2ff4d7d3796b738a174f7b (MATCH at target=000007ff/diff=32)
`endif
reg [31:0] target = 31'h000007ff; // Default to diff=32 for sane startup, this is overwritten by virtual_wire
wire [31:0]golden_nonce_out;
wire [31:0] nonce_out;
wire loadnonce = 1'b0; // Only used in serial comms interface
wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
wire [LOCAL_MINERS-1:0] golden_nonce_match;
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: for_local_miners
wire [31:0] nonce_out_i;
wire [3:0] nonce_core = i;
hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);
if (i==0)
assign nonce_out = nonce_out_i; // NB mining script will under-report hash rate by factor of LOCAL_MINERS
// TODO correctabe by a simple shift here of log2(LOCAL-MINERS)
end
endgenerate
// Simple queue as virtual_wire just reports current value of golden_nonce
// What I want here is a parameterised, one-hot (priority) selected multiplexor, but since
// my verilog is not very good, I'll just reuse the hub_core code instead
reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
function integer clog2; // Courtesy of razorfishsl, replaces $clog2() - needed for ISE < 14.1
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
assign golden_nonce_out = nonces_shifted[31:0];
// Mark nonces to be cleared during next clock cycle
reg [LOCAL_MINERS-1:0] clear_nonces = 0;
always @(posedge hash_clk)
begin
// Raise flags when new nonces appear; lower those that have been sent
new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;
if (port_counter == LOCAL_MINERS-1)
port_counter <= 0;
else
port_counter <= port_counter + 1'd1;
// kramble - the optimiser removes all but the low 32 bits of nonces_shifted since
// the following code implements a multiplexor on nonces input, NOT an actual shifter.
if (new_nonces_flag[port_counter])
begin
nonces_shifted <= golden_nonce_i >> port_counter*32;
clear_nonces[port_counter] <= 1;
end
else
begin
clear_nonces <= 0;
end
end
`ifndef SIM
//// Virtual Wire Control
wire [255:0] data1_vw;
wire [255:0] data2_vw;
wire [127:0] data3_vw; // 96 bits actually used, the extra 32 are the nonce, normally all zeros but for
// testing we can supply a nonce which will be loaded. Some pools set a non-zero nonce
// in getwork (which we will load), but this is of no consequence to live mining.
wire [31:0] target_vw; // This depends on the pool, variable diff pools will update the target dynamically
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));
always @ (posedge hash_clk)
begin
data1 <= data1_vw;
data2 <= data2_vw;
data3 <= data3_vw;
target <= target_vw;
end
//// Virtual Wire Output
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());
`endif
`ifndef NOLEDS
// Optional LED progress indicator
always @(posedge hash_clk) begin
`ifdef INVERTLEDS
LEDS_out <= ~nonce_out[15:8]; // Inverted for BeMicro
`else
LEDS_out <= nonce_out[15:8];
`endif
end
`endif
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test multidimensional arrays.
module vhdl_multidim_array_test;
vhdl_multidim_array dut();
initial begin
int i, j;
for(i = 0; i <= 1; i = i + 1) begin
for(j = dut.array_size - 1; j >= 0; j = j - 1) begin
$display("%d", dut.arr[i][j]);
//$display("%d, %d = %d", i, j, arr[i][j]);
//if(dut.arr[i][j] !== i * 10 + j) begin
//$display("FAILED: arr[%d][%d] == %d, instead of %d", i, j, dut.arr[i][j], i * 10 + j);
//$finish();
//end
end
end
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
/*
* PicoBlaze_OutReg.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/07/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : XC3S700AN - 4FGG484
* Board : Spartan-3AN Starter Kit.
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 19/06/2015.
*/
//////////////////////////////////////////////////////////////////////////////////
module PicoBlaze_OutReg
#(parameter LOCAL_PORT_ID = 8'h00)
(
clk,
reset,
port_id,
write_strobe,
out_port,
new_out_port);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
input wire clk;
input wire reset;
input wire [7:0] port_id;
input wire write_strobe;
input wire [7:0] out_port;
output reg [7:0] new_out_port;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg RegEnable=1;
//=======================================================
// Structural coding
//=======================================================
always @ (*)
begin
if (write_strobe == 1)
begin
case (port_id)
LOCAL_PORT_ID: RegEnable = 1;
default: RegEnable = 0;
endcase
end
else
RegEnable=0;
end
always @ (posedge clk, posedge reset)
begin
if(reset == 1)
new_out_port <= 8'h00;
else
begin
if(RegEnable == 1)
new_out_port <= out_port;
else
new_out_port <= new_out_port;
end
end
//=======================================================
// Connections & assigns
//=======================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_PP_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s4s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_PP_SYMBOL_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
input ena_i;
input dbg_i;
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
input [15:0] pulse_num_i;
output [15:0] rx_i_o;
output [15:0] rx_q_o;
output reg rx_strobe_o;
reg [15:0] count;
always @(posedge clk_i)
if (rst_i | ~ena_i)
count <= 16'b0;
else
count <= count + 16'b1;
wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i};
// Buffer incoming samples every clock
wire [31:0] fifo_out;
reg fifo_ack;
wire fifo_empty;
// Use model if simulating, otherwise Altera Megacell
`ifdef SIMULATION
fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`else
fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`endif
// Write samples to rx_fifo every third clock
`define ST_FIFO_IDLE 3'b001
`define ST_FIFO_STROBE 3'b010
`define ST_FIFO_ACK 3'b100
reg [2:0] state;
always @(posedge clk_i)
if (rst_i)
begin
state <= `ST_FIFO_IDLE;
rx_strobe_o <= 1'b0;
fifo_ack <= 1'b0;
end
else
case (state)
`ST_FIFO_IDLE:
if (!fifo_empty)
begin
// Tell rx_fifo sample is ready
rx_strobe_o <= 1'b1;
state <= `ST_FIFO_STROBE;
end
`ST_FIFO_STROBE:
begin
rx_strobe_o <= 1'b0;
// Ack our FIFO
fifo_ack <= 1'b1;
state <= `ST_FIFO_ACK;
end
`ST_FIFO_ACK:
begin
fifo_ack <= 1'b0;
state <= `ST_FIFO_IDLE;
end
endcase // case(state)
assign rx_i_o = fifo_out[31:16];
assign rx_q_o = fifo_out[15:0];
endmodule // radar_rx
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:33:23 06/15/2014
// Design Name:
// Module Name: bin_to_decimal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bin_to_decimal(
input [15:0] B,
output reg [19:0] bcdout
);
reg [35:0] z;
integer i;
always @(*)
begin
for(i = 0; i <= 35; i = i+1)
z[i] = 0;
z[18:3] = B; // shift b 3 places left
//for(i = 0; i <= 12; i = i+1)
repeat(13)
begin
if(z[19:16] > 4)
z[19:16] = z[19:16] + 3;
if(z[23:20] > 4)
z[23:20] = z[23:20] + 3;
if(z[27:24] > 4)
z[27:24] = z[27:24] + 3;
if(z[31:28] > 4)
z[31:28] = z[31:28] + 3;
if(z[35:32] > 4)
z[35:32] = z[35:32] + 3;
z[35:1] = z[34:0];
//z[34:2] = z[33:1];
end
bcdout = z[35:16];//20 bits
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Contribution by Claude Marché and Xavier Urbain *)
(** Euclidean Division
Defines first of function that allows Coq to normalize.
Then only after proves the main required property.
*)
Require Export ZArith_base.
Require Import Zbool Omega ZArithRing Zcomplements Setoid Morphisms.
Require ZDivFloor.
Open Local Scope Z_scope.
(** * Definitions of Euclidian operations *)
(** Euclidean division of a positive by a integer
(that is supposed to be positive).
Total function than returns an arbitrary value when
divisor is not positive
*)
Unboxed Fixpoint Zdiv_eucl_POS (a:positive) (b:Z) : Z * Z :=
match a with
| xH => if Zge_bool b 2 then (0, 1) else (1, 0)
| xO a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
| xI a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r + 1 in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
end.
(** Euclidean division of integers.
Total function than returns (0,0) when dividing by 0.
*)
(**
The pseudo-code is:
if b = 0 : (0,0)
if b <> 0 and a = 0 : (0,0)
if b > 0 and a < 0 : let (q,r) = div_eucl_pos (-a) b in
if r = 0 then (-q,0) else (-(q+1),b-r)
if b < 0 and a < 0 : let (q,r) = div_eucl (-a) (-b) in (q,-r)
if b < 0 and a > 0 : let (q,r) = div_eucl a (-b) in
if r = 0 then (-q,0) else (-(q+1),b+r)
In other word, when b is non-zero, q is chosen to be the greatest integer
smaller or equal to a/b. And sgn(r)=sgn(b) and |r| < |b| (at least when
r is not null).
*)
(* Nota: At least two others conventions also exist for euclidean division.
They all satify the equation a=b*q+r, but differ on the choice of (q,r)
on negative numbers.
* Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
* Another solution is to always pick a non-negative remainder:
a=b*q+r with 0 <= r < |b|
*)
Definition Zdiv_eucl (a b:Z) : Z * Z :=
match a, b with
| Z0, _ => (0, 0)
| _, Z0 => (0, 0)
| Zpos a', Zpos _ => Zdiv_eucl_POS a' b
| Zneg a', Zpos _ =>
let (q, r) := Zdiv_eucl_POS a' b in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b - r)
end
| Zneg a', Zneg b' => let (q, r) := Zdiv_eucl_POS a' (Zpos b') in (q, - r)
| Zpos a', Zneg b' =>
let (q, r) := Zdiv_eucl_POS a' (Zpos b') in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b + r)
end
end.
(** Division and modulo are projections of [Zdiv_eucl] *)
Definition Zdiv (a b:Z) : Z := let (q, _) := Zdiv_eucl a b in q.
Definition Zmod (a b:Z) : Z := let (_, r) := Zdiv_eucl a b in r.
(** Syntax *)
Infix "/" := Zdiv : Z_scope.
Infix "mod" := Zmod (at level 40, no associativity) : Z_scope.
(* Tests:
Eval compute in (Zdiv_eucl 7 3).
Eval compute in (Zdiv_eucl (-7) 3).
Eval compute in (Zdiv_eucl 7 (-3)).
Eval compute in (Zdiv_eucl (-7) (-3)).
*)
(** * Main division theorem *)
(** First a lemma for two positive arguments *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Zdiv_eucl_POS a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
simple induction a; cbv beta iota delta [Zdiv_eucl_POS] in |- *;
fold Zdiv_eucl_POS in |- *; cbv zeta.
intro p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r + 1)).
case (Zgt_bool b (2 * r + 1));
(rewrite BinInt.Zpos_xI; rewrite H0; split; [ ring | omega ]).
intros p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r)).
case (Zgt_bool b (2 * r)); rewrite BinInt.Zpos_xO;
change (Zpos (xO p)) with (2 * Zpos p) in |- *; rewrite H0;
(split; [ ring | omega ]).
generalize (Zge_cases b 2).
case (Zge_bool b 2); (intros; split; [ try ring | omega ]).
omega.
Qed.
(** Then the usual situation of a positive [b] and no restriction on [a] *)
Theorem Z_div_mod :
forall a b:Z,
b > 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
intros a b; case a; case b; try (simpl in |- *; intros; omega).
unfold Zdiv_eucl in |- *; intros; apply Z_div_mod_POS; trivial.
intros; discriminate.
intros.
generalize (Z_div_mod_POS (Zpos p) H p0).
unfold Zdiv_eucl in |- *.
case (Zdiv_eucl_POS p0 (Zpos p)).
intros z z0.
case z0.
intros [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zgt_pos_0 p1); omega.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zlt_neg_0 p1); omega.
intros; discriminate.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Zabs r < Zabs b /\ Zsgn r <> - Zsgn b.
(* In the last formulation, [ Zsgn r <> - Zsgn b ] is less nice than saying
[ Zsgn r = Zsgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full :
forall a b:Z,
b <> 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
destruct b as [|b|b].
(* b = 0 *)
intro H; elim H; auto.
(* b > 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
destruct Zdiv_eucl as (q,r); intuition; simpl; auto.
(* b < 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
unfold Remainder.
destruct a as [|a|a].
(* a = 0 *)
simpl; intuition.
(* a > 0 *)
unfold Zdiv_eucl; destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; [ | | omega with *].
rewrite <- Zmult_opp_comm; simpl Zopp; intuition.
rewrite <- Zmult_opp_comm; simpl Zopp.
rewrite Zmult_plus_distr_r; omega with *.
(* a < 0 *)
unfold Zdiv_eucl.
generalize (Z_div_mod_POS (Zpos b) H a).
destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; change (Zneg b) with (-Zpos b).
rewrite Zmult_opp_comm; omega with *.
rewrite <- Zmult_opp_comm, Zmult_plus_distr_r;
repeat rewrite Zmult_opp_comm; omega.
rewrite Zmult_opp_comm; omega with *.
Qed.
(** The same results as before, stated separately in terms of Zdiv and Zmod *)
Lemma Z_mod_remainder : forall a b:Z, b<>0 -> Remainder (a mod b) b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_lt : forall a b:Z, b > 0 -> 0 <= a mod b < b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_neg : forall a b:Z, b < 0 -> b < a mod b <= 0.
Proof.
unfold Zmod; intros a b Hb.
assert (Hb' : b<>0) by (auto with zarith).
generalize (Z_div_mod_full a b Hb').
destruct Zdiv_eucl.
unfold Remainder; intuition.
Qed.
Lemma Z_div_mod_eq_full : forall a b:Z, b <> 0 -> a = b*(a/b) + (a mod b).
Proof.
unfold Zdiv, Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_div_mod_eq : forall a b:Z, b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros; apply Z_div_mod_eq_full; auto with zarith.
Qed.
Lemma Zmod_eq_full : forall a b:Z, b<>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq_full; auto.
Qed.
Lemma Zmod_eq : forall a b:Z, b>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq; auto.
Qed.
(** We know enough to prove that [Zdiv] and [Zmod] are instances of
one of the abstract Euclidean divisions of Numbers.
We hence benefit from generic results about this abstract division. *)
Module Z.
Definition div := Zdiv.
Definition modulo := Zmod.
Local Obligation Tactic := simpl_relation.
Program Instance div_wd : Proper (eq==>eq==>eq) div.
Program Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Definition div_mod := Z_div_mod_eq_full.
Definition mod_pos_bound : forall a b:Z, 0<b -> 0<=a mod b<b.
Proof. intros; apply Z_mod_lt; auto with zarith. Qed.
Definition mod_neg_bound := Z_mod_neg.
Include ZBinary.Z <+ ZDivFloor.ZDivProp.
End Z.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Zdiv_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Implicit Arguments Zdiv_eucl_exist.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique :
forall b q1 q2 r1 r2:Z,
0 <= r1 < Zabs b -> 0 <= r2 < Zabs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof. exact Z.div_mod_unique. Qed.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof. exact Z.div_unique. Qed.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof. exact Z.mod_unique. Qed.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z_eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros. zero_or_not a. apply Z.div_1_r. Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof. exact Z.div_1_l. Qed.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof. exact Z.mod_1_l. Qed.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof. exact Z.div_same. Qed.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_mul. auto. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof. exact Z.div_mul. Qed.
(** * Order results about Zmod and Zdiv *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto with zarith. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof. intros. apply Z.div_lt; auto with zarith. Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof. exact Z.div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof. exact Z.mod_small. Qed.
(** [Zge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Zle_ge. apply Z.div_le_mono; auto with zarith. Qed.
(** Same, with [Zle]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto with zarith. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Zle_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; auto with zarith. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Zsgn (a/b) * Zsgn a * Zsgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z_div_pos (Zpos a) (Zpos b)); unfold Zdiv, Zdiv_eucl;
destruct Zdiv_eucl_POS as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros. zero_or_not c. apply Z.mod_add; auto. Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof. exact Z.div_add. Qed.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof. exact Z.div_add_l. Qed.
(** [Zopp] and [Zdiv], [Zmod].
Due to the choice of convention for our Euclidean division,
some of the relations about [Zopp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_l_z; auto. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_nz; auto. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros. rewrite (Zmult_comm c b); zero_or_not b.
rewrite (Zmult_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros. zero_or_not c. rewrite (Zmult_comm c b); zero_or_not b.
rewrite (Zmult_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros. zero_or_not b. rewrite (Zmult_comm b c); zero_or_not c.
rewrite (Zmult_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Definition eqm N a b := (a mod N = b mod N).
Lemma eqm_refl N : forall a, (eqm N) a a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym N : forall a b, (eqm N) a b -> (eqm N) b a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans N : forall a b c,
(eqm N) a b -> (eqm N) b c -> (eqm N) a c.
Proof. unfold eqm; eauto with *. Qed.
Add Parametric Relation N : Z (eqm N)
reflexivity proved by (eqm_refl N)
symmetry proved by (eqm_sym N)
transitivity proved by (eqm_trans N) as eqm_setoid.
Add Parametric Morphism N : Zplus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zplus_eqm.
Proof.
unfold eqm; intros; rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Add Parametric Morphism N : Zminus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zminus_eqm.
Proof.
unfold eqm; intros; rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Add Parametric Morphism N : Zmult
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zmult_eqm.
Proof.
unfold eqm; intros; rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Add Parametric Morphism N : Zopp
with signature (eqm N) ==> (eqm N) as Zopp_eqm.
Proof.
intros; change ((eqm N) (-x) (-y)) with ((eqm N) (0-x) (0-y)).
rewrite H; red; auto.
Qed.
Lemma Zmod_eqm N : forall a, (eqm N) (a mod N) a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Zmod and Zdiv are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros. zero_or_not b. rewrite Zmult_comm. zero_or_not c.
rewrite Zmult_comm. apply Z.div_div; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros. zero_or_not b. apply Z.div_mul_le; auto with zarith. Qed.
(** Zmod is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof. exact Z.mod_divides. Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Zmod *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if Zgt_bool b r' then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if Zgt_bool b r' then r' else (r' - b)
| xH => if Zge_bool b 2 then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct: forall a b, Zmod_POS a b = (snd (Zdiv_eucl_POS a b)).
Proof.
intros a b; elim a; simpl; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
case (Zge_bool b 2); auto.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = Zmod a b.
Proof.
intros a b; unfold Zmod; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Zdiv_eucl_POS p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Zabs b}.
Proof.
intros b Hb a.
elim (Z_le_gt_dec 0 b); intro Hb'.
cut (b > 0); [ intro Hb'' | omega ].
rewrite Zabs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
cut (- b > 0); [ intro Hb'' | omega ].
elim (Zdiv_eucl_exist Hb'' a); intros qr.
elim qr; intros q r Hqr.
exists (- q, r).
elim Hqr; intros.
split.
rewrite <- Zmult_opp_comm; assumption.
rewrite Zabs_non_eq; [ assumption | omega ].
Qed.
Implicit Arguments Zdiv_eucl_extended.
(** A third convention: Ocaml.
See files ZOdiv_def.v and ZOdiv.v.
Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
*)
|
// bsg_clk_gen_osc
//
// new settings are delivered via bsg_tag_i
//
// the clock is designed to be atomically updated
// between any of its values without glitching.
//
// the order of components is:
//
// ADT, CDT, FDT --> feedback (and buffer to outside world)
//
// All three stages invert their outputs.
//
// All of the modules have delay circuits that clock their config
// flops right after the signal has passed through. All of them are
// configured to grab the new value after a negedge enters the beginning of
// of the ADT, but of course since the signal is inverted at each stage
// ADT and FDT do it on posege and CDT does it on negedge.
//
// We employ a MUXI4 that is part of the TSMC 250 standard cell library
// that has balanced paths and is glitch-free, because it is based on a
// t-gate design. If the MUXI4 were made out of AND-OR circuits, care
// would have to be taken to make sure that the transitions occur when
// either all inputs are 0 or 1 to the MUXI4, depending on the implementation.
// For example, if the mux is AOI, triggered on negedge edge of input clock would
// be okay. Fortunately, we don't have to worry about this (and confirmed by spice.)
//
// We have verified this in TSMC 250 by running with sdf annotations.
//
// There is an implicit race between the bsg_tag's output fb_we_r (clocked on
// positive edge of FDT output) and these config flops that cannot be addressed
// in ICC because we cannot explicitly control timing between ICC-managed
// clocks and our internal oscillator clocks.
//
// A final check must be made on the 5 flops inside the adt / cdt / fdt
// to see that async reset drops and data inputs do not come too close
// to the appropriate clock edge. This could be verified via a script that
// processes the SDF file, but for now we pull the test trace up in DVE and
// manually check these points. Typically, the ADT is the closest
// call, where in MAX timing mode, the data changes about 481 ps before the
// positive edge of the flop's clock. With a setup time on the order of
// 261 ps, there is a slack of 220 ps. This path was originally a problem
// and it fixed by sending the clock out to the BTC at the beginning of
// the FDT as opposed to at the end. This gives more time for propagate
// through the ICC-generate clock tree for the BTC.
//
`include "bsg_clk_gen.vh"
module bsg_clk_gen_osc
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input async_reset_i
,input bsg_tag_s bsg_tag_i
,output clk_o
);
wire fb_clk, fb_btc_clk; // internal clock
wire async_reset_neg = ~async_reset_i;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s fb_tag_r;
wire fb_we_r;
// note: oscillator has to be already working in order
// for configuration state to pass through here
bsg_tag_client #(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
,.default_p(0)
) btc
(.bsg_tag_i (bsg_tag_i)
,.recv_clk_i (fb_btc_clk)
,.recv_reset_i (1'b0) // no default value is loaded;
,.recv_new_r_o (fb_we_r) // default is already in OSC flops
,.recv_data_r_o(fb_tag_r)
);
wire adt_lo, cdt_lo;
wire fb_clk_del;
// this adds some delay in the loop for RTL simulation
// should be ignored in synthesis
assign #4000 fb_clk_del = fb_clk;
bsg_rp_clk_gen_atomic_delay_tuner adt
(.i(fb_clk_del)
,.we_i(fb_we_r)
,.async_reset_neg_i(async_reset_neg)
,.sel_i(fb_tag_r.adg[0])
,.o(adt_lo)
);
// instantatiate CDT (coarse delay tuner)
// this one inverts the output
// captures config state on negative edge of input clock
bsg_rp_clk_gen_coarse_delay_tuner cdt
(.i (adt_lo)
,.we_i (fb_we_r )
,.async_reset_neg_i(async_reset_neg )
,.sel_i (fb_tag_r.cdt )
,.o (cdt_lo )
);
// instantiate FDT (fine delay tuner)
// captures config state on positive edge of (inverted) input clk
// non-inverting
bsg_rp_clk_gen_fine_delay_tuner fdt
(.i (cdt_lo)
,.we_i (fb_we_r )
,.async_reset_neg_i(async_reset_neg)
,.sel_i (fb_tag_r.fdt )
,.o (fb_clk) // in the actual critical loop
,.buf_btc_o (fb_btc_clk) // inside this module; to the btc
,.buf_o (clk_o) // outside this module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule // bsg_clk_gen_osc
`BSG_ABSTRACT_MODULE(bsg_clk_gen_osc)
|
module testmux();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
/*AUTO_LISP(setq verilog-auto-inst-param-value nil)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_symbolic[]),
.out (@_out_symbolic[]),
);
*/
testmux #(.WIDTH( 16 )) testmux_boo
(/*AUTOINST*/);
testmux testmux_defaultwidth
(/*AUTOINST*/);
//======================================================================
/*AUTO_LISP(setq verilog-auto-inst-param-value t)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_value[]),
.out (@_out_value[]),
);
*/
testmux #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/);
//======================================================================
testmux #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_TB_V
`define SKY130_FD_SC_HDLL__DIODE_TB_V
/**
* diode: Antenna tie-down diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__diode.v"
module top();
// Inputs are registered
reg DIODE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
DIODE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 DIODE = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 DIODE = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 DIODE = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 DIODE = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 DIODE = 1'bx;
end
sky130_fd_sc_hdll__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_TB_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v4_0_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack, app_ecc_single_err,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack, ecc_single
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [2*nCK_PER_CLK-1:0] ecc_single; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [2*nCK_PER_CLK-1:0] app_ecc_single_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v4_0_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v4_0_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v4_0_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.app_ecc_single_err (app_ecc_single_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
/****************************************************************************
Generic Register
****************************************************************************/
module register(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register - synchronous reset
****************************************************************************/
module register_sync(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register
- Special component, components starting with "pipereg" have
their enables treated independently of instructrions that use them.
- They are enabled whenever the stage is active and not stalled
****************************************************************************/
module pipereg(d,clk,resetn,en,squashn,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register 2 -OLD: If not enabled, queues squash
- This piperegister stalls the reset signal as well
module pipereg_full(d,clk,resetn,squashn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || (squashn==0 && en==1) || (squash_save&en))
q<=0;
else if (en==1)
q<=d;
end
always @(posedge clk)
begin
if (resetn==1 && squashn==0 && en==0)
squash_save<=1;
else
squash_save<=0;
end
endmodule
****************************************************************************/
/****************************************************************************
One cycle Stall circuit
****************************************************************************/
module onecyclestall(request,clk,resetn,stalled);
input request;
input clk;
input resetn;
output stalled;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(request or T)
begin
case(T)
1'b0: Tnext=request;
1'b1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
assign stalled=(request&~T);
endmodule
/****************************************************************************
Multi cycle Stall circuit - with wait signal
- One FF plus one 2:1 mux to stall 1st cycle on request, then wait
- this makes wait don't care for the first cycle
****************************************************************************/
module multicyclestall(request, devwait,clk,resetn,stalled);
input request;
input devwait;
input clk;
input resetn;
output stalled;
reg T;
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=stalled;
assign stalled=(T) ? devwait : request;
endmodule
/****************************************************************************
One cycle - Pipeline delay register
****************************************************************************/
module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input [4:0] dst;
input en;
input clk;
input resetn;
input squashn;
output stalled;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(en or T or dst)
begin
case(T)
0: Tnext=en&(|dst);
1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
assign stalled=(en&~T&(|dst));
endmodule
/****************************************************************************
Fake Delay
****************************************************************************/
module fakedelay(d,clk,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input clk;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Zeroer
****************************************************************************/
module zeroer(d,en,q);
parameter WIDTH=32;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q= (en) ? d : 0;
endmodule
/****************************************************************************
NOP - used to hack position of multiplexors
****************************************************************************/
module nop(d,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Const
****************************************************************************/
module const (out);
parameter WIDTH=32;
parameter VAL=31;
output [WIDTH-1:0] out;
assign out=VAL;
endmodule
/****************************************************************************
Branch detector
****************************************************************************/
module branch_detector(opcode, func, is_branch);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special=!(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func[5:3]==3'b001));
endmodule
|
// file: bclk_dll_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module bclk_dll_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk;
reg [C_W-1:0] counter;
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf
(.O (clk_in1_buf),
.I (CLK_IN1));
// Instantiation of the clocking network
//--------------------------------------
bclk_dll clknetwork
(// Clock in ports
.clk133in (clk_in1_buf),
// Clock out ports
.clk133 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
assign CLK_OUT[1] = clk_int;
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//Date: Thu Jul 11 11:26:45 2013
// ============================================================================
`define ENABLE_ADC
`define ENABLE_AUD
`define ENABLE_CLOCK2
`define ENABLE_CLOCK3
`define ENABLE_CLOCK4
`define ENABLE_CLOCK
`define ENABLE_DRAM
`define ENABLE_FAN
`define ENABLE_FPGA
`define ENABLE_GPIO
`define ENABLE_HEX
//`define ENABLE_HPS
`define ENABLE_IRDA
`define ENABLE_KEY
`define ENABLE_LEDR
`define ENABLE_PS2
`define ENABLE_SW
`define ENABLE_TD
`define ENABLE_VGA
module DE1_SOC_golden_top(
/* Enables ADC - 3.3V */
`ifdef ENABLE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
/* Enables AUD - 3.3V */
`ifdef ENABLE_AUD
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
/* Enables CLOCK2 */
`ifdef ENABLE_CLOCK2
input CLOCK2_50,
`endif
/* Enables CLOCK3 */
`ifdef ENABLE_CLOCK3
input CLOCK3_50,
`endif
/* Enables CLOCK4 */
`ifdef ENABLE_CLOCK4
input CLOCK4_50,
`endif
/* Enables CLOCK */
`ifdef ENABLE_CLOCK
input CLOCK_50,
`endif
/* Enables DRAM - 3.3V */
`ifdef ENABLE_DRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
/* Enables FAN - 3.3V */
`ifdef ENABLE_FAN
output FAN_CTRL,
`endif
/* Enables FPGA - 3.3V */
`ifdef ENABLE_FPGA
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
/* Enables GPIO - 3.3V */
`ifdef ENABLE_GPIO
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`endif
/* Enables HEX - 3.3V */
`ifdef ENABLE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
/* Enables HPS */
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N, //1.5V
output HPS_DDR3_CK_P, //1.5V
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
/* Enables IRDA - 3.3V */
`ifdef ENABLE_IRDA
input IRDA_RXD,
output IRDA_TXD,
`endif
/* Enables KEY - 3.3V */
`ifdef ENABLE_KEY
input [3:0] KEY,
`endif
/* Enables LEDR - 3.3V */
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
/* Enables PS2 - 3.3V */
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
/* Enables SW - 3.3V */
`ifdef ENABLE_SW
input [9:0] SW,
`endif
/* Enables TD - 3.3V */
`ifdef ENABLE_TD
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
/* Enables VGA - 3.3V */
`ifdef ENABLE_VGA
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:09:50
// Design Name:
// Module Name: ss_a_7seg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Dec_4b_seg(
input [3:0] NUM,
output reg [7:0] CATODOS
);
always @(*) begin
case(NUM)
4'd0: CATODOS=8'b00000011;
4'd1: CATODOS=8'b10011111;
4'd2: CATODOS=8'b00100101;
4'd3: CATODOS=8'b00001101;
4'd4: CATODOS=8'b10011001;
4'd5: CATODOS=8'b01001001;
4'd6: CATODOS=8'b01000001;
4'd7: CATODOS=8'b00011111;
4'd8: CATODOS=8'b00000001;
4'd9: CATODOS=8'b00011001;
4'd10: CATODOS=8'b00010001;
4'd11: CATODOS=8'b11000001;
4'd12: CATODOS=8'b01100011;
4'd13: CATODOS=8'b10000101;
4'd14: CATODOS=8'b01100001;
4'd15: CATODOS=8'b01110001;
default CATODOS=8'b11111101;
endcase
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module spw_babasu (
autostart_external_connection_export,
clk_clk,
currentstate_external_connection_export,
data_i_external_connection_export,
data_o_external_connection_export,
flags_external_connection_export,
link_disable_external_connection_export,
link_start_external_connection_export,
pll_0_locked_export,
pll_0_outclk0_clk,
rd_data_external_connection_export,
reset_reset_n,
rx_empty_external_connection_export,
spill_enable_external_connection_export,
tick_in_external_connection_export,
tick_out_external_connection_export,
time_in_external_connection_export,
time_out_external_connection_export,
tx_clk_div_external_connection_export,
tx_full_external_connection_export,
wr_data_external_connection_export);
output autostart_external_connection_export;
input clk_clk;
input [2:0] currentstate_external_connection_export;
output [8:0] data_i_external_connection_export;
input [8:0] data_o_external_connection_export;
input [10:0] flags_external_connection_export;
output link_disable_external_connection_export;
output link_start_external_connection_export;
output pll_0_locked_export;
output pll_0_outclk0_clk;
output rd_data_external_connection_export;
input reset_reset_n;
input rx_empty_external_connection_export;
output spill_enable_external_connection_export;
output tick_in_external_connection_export;
input tick_out_external_connection_export;
output [7:0] time_in_external_connection_export;
input [7:0] time_out_external_connection_export;
output [6:0] tx_clk_div_external_connection_export;
input tx_full_external_connection_export;
output wr_data_external_connection_export;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_1_V
`define SKY130_FD_SC_MS__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_1_V
|
`ifndef ROI
ERROR: must set ROI
`endif
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
`ROI
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
/******************************************************************************
*******************************************************************************
DATA ROI
*******************************************************************************
******************************************************************************/
/******************************************************************************
Toggle a single data bit to locate a single instance (BRAM36)
******************************************************************************/
module roi_bram36d_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bram36d_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
Toggle a single data bit to locate a single instance (BRAM18)
******************************************************************************/
module roi_bram18d_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bram18d_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
Toggle all bits to show the size of the data section
******************************************************************************/
module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
Toggle one bit per BRAM in the ROI to show pitch between entries
******************************************************************************/
module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b0), .INIT({256{1'b0}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b0), .INIT({256{1'b0}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b0), .INIT({256{1'b0}}))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b0), .INIT({256{1'b0}}))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b0), .INIT({256{1'b0}}))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b0), .INIT({256{1'b0}}))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b0), .INIT({256{1'b0}}))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b0), .INIT({256{1'b0}}))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b0), .INIT({256{1'b0}}))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b1), .INIT({256{1'b0}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b1), .INIT({256{1'b0}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b1), .INIT({256{1'b0}}))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b1), .INIT({256{1'b0}}))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b1), .INIT({256{1'b0}}))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b1), .INIT({256{1'b0}}))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b1), .INIT({256{1'b0}}))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b1), .INIT({256{1'b0}}))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b1), .INIT({256{1'b0}}))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
/******************************************************************************
Set all data bits
******************************************************************************/
module roi_bram36_0s(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bram36_1s(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
*******************************************************************************
Library
*******************************************************************************
******************************************************************************/
/*
Site RAMB18_X0Y42
Pushed it outside the pblock
lets extend pblock
for i in xrange(0x08): print '.INITP_%02X(INIT),' % i
for i in xrange(0x40): print '.INIT_%02X(INIT),' % i
*/
module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
(* LOC=LOC *)
RAMB18E1 #(
.INITP_00(INIT),
.INITP_01(INIT),
.INITP_02(INIT),
.INITP_03(INIT),
.INITP_04(INIT),
.INITP_05(INIT),
.INITP_06(INIT),
.INITP_07(INIT),
.INIT_00(INIT0),
.INIT_01(INIT),
.INIT_02(INIT),
.INIT_03(INIT),
.INIT_04(INIT),
.INIT_05(INIT),
.INIT_06(INIT),
.INIT_07(INIT),
.INIT_08(INIT),
.INIT_09(INIT),
.INIT_0A(INIT),
.INIT_0B(INIT),
.INIT_0C(INIT),
.INIT_0D(INIT),
.INIT_0E(INIT),
.INIT_0F(INIT),
.INIT_10(INIT),
.INIT_11(INIT),
.INIT_12(INIT),
.INIT_13(INIT),
.INIT_14(INIT),
.INIT_15(INIT),
.INIT_16(INIT),
.INIT_17(INIT),
.INIT_18(INIT),
.INIT_19(INIT),
.INIT_1A(INIT),
.INIT_1B(INIT),
.INIT_1C(INIT),
.INIT_1D(INIT),
.INIT_1E(INIT),
.INIT_1F(INIT),
.INIT_20(INIT),
.INIT_21(INIT),
.INIT_22(INIT),
.INIT_23(INIT),
.INIT_24(INIT),
.INIT_25(INIT),
.INIT_26(INIT),
.INIT_27(INIT),
.INIT_28(INIT),
.INIT_29(INIT),
.INIT_2A(INIT),
.INIT_2B(INIT),
.INIT_2C(INIT),
.INIT_2D(INIT),
.INIT_2E(INIT),
.INIT_2F(INIT),
.INIT_30(INIT),
.INIT_31(INIT),
.INIT_32(INIT),
.INIT_33(INIT),
.INIT_34(INIT),
.INIT_35(INIT),
.INIT_36(INIT),
.INIT_37(INIT),
.INIT_38(INIT),
.INIT_39(INIT),
.INIT_3A(INIT),
.INIT_3B(INIT),
.INIT_3C(INIT),
.INIT_3D(INIT),
.INIT_3E(INIT),
.INIT_3F(INIT),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_ENARDEN_INVERTED = 1'b0;
(* LOC=LOC *)
RAMB36E1 #(
.INITP_00(INIT),
.INITP_01(INIT),
.INITP_02(INIT),
.INITP_03(INIT),
.INITP_04(INIT),
.INITP_05(INIT),
.INITP_06(INIT),
.INITP_07(INIT),
.INITP_08(INIT),
.INITP_09(INIT),
.INITP_0A(INIT),
.INITP_0B(INIT),
.INITP_0C(INIT),
.INITP_0D(INIT),
.INITP_0E(INIT),
.INITP_0F(INIT),
.INIT_00(INIT0),
.INIT_01(INIT),
.INIT_02(INIT),
.INIT_03(INIT),
.INIT_04(INIT),
.INIT_05(INIT),
.INIT_06(INIT),
.INIT_07(INIT),
.INIT_08(INIT),
.INIT_09(INIT),
.INIT_0A(INIT),
.INIT_0B(INIT),
.INIT_0C(INIT),
.INIT_0D(INIT),
.INIT_0E(INIT),
.INIT_0F(INIT),
.INIT_10(INIT),
.INIT_11(INIT),
.INIT_12(INIT),
.INIT_13(INIT),
.INIT_14(INIT),
.INIT_15(INIT),
.INIT_16(INIT),
.INIT_17(INIT),
.INIT_18(INIT),
.INIT_19(INIT),
.INIT_1A(INIT),
.INIT_1B(INIT),
.INIT_1C(INIT),
.INIT_1D(INIT),
.INIT_1E(INIT),
.INIT_1F(INIT),
.INIT_20(INIT),
.INIT_21(INIT),
.INIT_22(INIT),
.INIT_23(INIT),
.INIT_24(INIT),
.INIT_25(INIT),
.INIT_26(INIT),
.INIT_27(INIT),
.INIT_28(INIT),
.INIT_29(INIT),
.INIT_2A(INIT),
.INIT_2B(INIT),
.INIT_2C(INIT),
.INIT_2D(INIT),
.INIT_2E(INIT),
.INIT_2F(INIT),
.INIT_30(INIT),
.INIT_31(INIT),
.INIT_32(INIT),
.INIT_33(INIT),
.INIT_34(INIT),
.INIT_35(INIT),
.INIT_36(INIT),
.INIT_37(INIT),
.INIT_38(INIT),
.INIT_39(INIT),
.INIT_3A(INIT),
.INIT_3B(INIT),
.INIT_3C(INIT),
.INIT_3D(INIT),
.INIT_3E(INIT),
.INIT_3F(INIT),
.INIT_40(INIT),
.INIT_41(INIT),
.INIT_42(INIT),
.INIT_43(INIT),
.INIT_44(INIT),
.INIT_45(INIT),
.INIT_46(INIT),
.INIT_47(INIT),
.INIT_48(INIT),
.INIT_49(INIT),
.INIT_4A(INIT),
.INIT_4B(INIT),
.INIT_4C(INIT),
.INIT_4D(INIT),
.INIT_4E(INIT),
.INIT_4F(INIT),
.INIT_50(INIT),
.INIT_51(INIT),
.INIT_52(INIT),
.INIT_53(INIT),
.INIT_54(INIT),
.INIT_55(INIT),
.INIT_56(INIT),
.INIT_57(INIT),
.INIT_58(INIT),
.INIT_59(INIT),
.INIT_5A(INIT),
.INIT_5B(INIT),
.INIT_5C(INIT),
.INIT_5D(INIT),
.INIT_5E(INIT),
.INIT_5F(INIT),
.INIT_60(INIT),
.INIT_61(INIT),
.INIT_62(INIT),
.INIT_63(INIT),
.INIT_64(INIT),
.INIT_65(INIT),
.INIT_66(INIT),
.INIT_67(INIT),
.INIT_68(INIT),
.INIT_69(INIT),
.INIT_6A(INIT),
.INIT_6B(INIT),
.INIT_6C(INIT),
.INIT_6D(INIT),
.INIT_6E(INIT),
.INIT_6F(INIT),
.INIT_70(INIT),
.INIT_71(INIT),
.INIT_72(INIT),
.INIT_73(INIT),
.INIT_74(INIT),
.INIT_75(INIT),
.INIT_76(INIT),
.INIT_77(INIT),
.INIT_78(INIT),
.INIT_79(INIT),
.INIT_7A(INIT),
.INIT_7B(INIT),
.INIT_7C(INIT),
.INIT_7D(INIT),
.INIT_7E(INIT),
.INIT_7F(INIT),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_cmd_translator.v
//
// Description:
// INCR and WRAP burst modes are decoded in parallel and then the output is
// chosen based on the AxBURST value. FIXED burst mode is not supported and
// is mapped to the INCR command instead.
//
// Specifications:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr ,
input wire [7:0] s_axlen ,
input wire [2:0] s_axsize ,
input wire [1:0] s_axburst ,
input wire s_axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr ,
output wire incr_burst ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: qdr_rld_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:36:29 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: QDRII+ SRAM / RLDRAM II SDRAM
//Purpose: Phase shift address/commands to center w.rto K/K# clocks at memory
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_LEN = 4, //Burst Length
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3636, // Internal clock period (in ps) - for a 550 MHz clk(clk period-1818ps), fabric clk period is 3636ps
parameter N_CTL_LANES = 3 // Number of control byte lanes
)
(
input clk, // half or quarter rate core clock
input rst, // half or quarter rate core clk reset
input cmd_delay_start,
//input phy_ctl_ready, // PHY Control Block is ready for operation
output reg [5:0] ctl_lane_cnt, // The control byte lane Phaser_Out
// being accessed
output reg po_stg2_f_incdec,// Inc/dec Phaser_Out fine delay line
output reg po_en_stg2_f, // Enable Phaser_Out fine delay inc/dec
output po_ck_addr_cmd_delay_done // Completed delaying Ck,addr,
// cmd and ctl Phaser_Outs
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (CLK_PERIOD > 5000 ? 4 :
CLK_PERIOD > 2500 ? 2 : 1);
localparam real FREQ_REF_PS = CLK_PERIOD/FREQ_REF_DIV;
localparam integer PHASER_TAP_RES = ((FREQ_REF_PS/2)/64);
// No. of Phaser taps for 1/4 of memory clock period
localparam CALC_TAP_CNT = (CLK_PERIOD / (4 * PHASER_TAP_RES));
//For now make sure our TAP_CNT calculation doesn't overflow
localparam TAP_CNT = (CALC_TAP_CNT > TAP_CNT_LIMIT) ?
TAP_CNT_LIMIT : CALC_TAP_CNT;
// // Quarter memory clock cycle in ps
// localparam DIV4_CK
// = ((CLK_PERIOD/nCK_PER_CLK)/4);
//
// // Determine the number of Phaser_Out taps required to delay by 300 ps
// // 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// localparam TAP_CNT = (300 + ((CLK_PERIOD/nCK_PER_CLK)/64) - 1)/
// ((CLK_PERIOD/nCK_PER_CLK)/64);
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] delay_cnt_r;
assign po_ck_addr_cmd_delay_done = (BURST_LEN == 2)? cmd_delay_start : delay_done_r4;
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst || ~cmd_delay_start || delay_done || (delay_cnt_r == 6'd1)) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (((delay_cnt_r == 6'd0) || (delay_cnt_r == TAP_CNT)) && (ctl_lane_cnt < N_CTL_LANES)) begin
po_stg2_f_incdec <= #TCQ 1'b1;
po_en_stg2_f <= #TCQ 1'b1;
end
end
// delay counter to count TAP_CNT cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_CNT
if (rst || ~cmd_delay_start ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt < N_CTL_LANES)))
delay_cnt_r <= #TCQ TAP_CNT;
else if (po_en_stg2_f && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delay_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delay_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// when all the ctl_lanes have their output phase shifted by 1/4 cycle, delay shifting is done.
always @(posedge clk) begin
if (rst ) begin
delay_done <= #TCQ 1'b0;
//end else if (((delay_cnt_r == 6'd2) && (ctl_lane_cnt == N_CTL_LANES-1)) || (BURST_LEN == 2)) begin
end else if ((delay_cnt_r == 6'd2) && (ctl_lane_cnt == N_CTL_LANES-1)) begin
delay_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_M_V
`define SKY130_FD_SC_LP__NOR4B_M_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_m (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_m (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_M_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_buttons (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 7: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] d1_data_in;
reg [ 7: 0] d2_data_in;
wire [ 7: 0] data_in;
reg [ 7: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 7: 0] edge_detect;
wire irq;
reg [ 7: 0] irq_mask;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({8 {(address == 0)}} & data_in) |
({8 {(address == 2)}} & irq_mask) |
({8 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[7 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem2x
#(
parameter DEPTH_WORDS=1,
parameter WIDTH=32,
parameter RDW_MODE="DONT_CARE",
parameter RAM_OPERATION_MODE = "BIDIR_DUAL_PORT", // altsyncram's OPERATION_MODE parameter
parameter RAM_BLOCK_TYPE = "AUTO" // altsyncram's RAM_BLOCK_TYPE parameter
)
(
input clk,
input clk2x,
input resetn,
input [WIDTH-1:0] avs_port1_writedata,
input [WIDTH-1:0] avs_port2_writedata,
input [WIDTH-1:0] avs_port3_writedata,
input [WIDTH-1:0] avs_port4_writedata,
input [WIDTH/8-1:0] avs_port1_byteenable,
input [WIDTH/8-1:0] avs_port2_byteenable,
input [WIDTH/8-1:0] avs_port3_byteenable,
input [WIDTH/8-1:0] avs_port4_byteenable,
input [$clog2(DEPTH_WORDS)-1:0] avs_port1_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port2_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port3_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port4_address,
input avs_port1_read,
input avs_port2_read,
input avs_port3_read,
input avs_port4_read,
input avs_port1_write,
input avs_port2_write,
input avs_port3_write,
input avs_port4_write,
output reg [WIDTH-1:0] avs_port1_readdata,
output reg [WIDTH-1:0] avs_port2_readdata,
output reg [WIDTH-1:0] avs_port3_readdata,
output reg [WIDTH-1:0] avs_port4_readdata,
output avs_port1_readdatavalid,
output avs_port2_readdatavalid,
output avs_port3_readdatavalid,
output avs_port4_readdatavalid,
output avs_port1_waitrequest,
output avs_port2_waitrequest,
output avs_port3_waitrequest,
output avs_port4_waitrequest
);
localparam LOG2DEPTH = $clog2( DEPTH_WORDS );
assign avs_port1_waitrequest=1'b0;
assign avs_port2_waitrequest=1'b0;
assign avs_port3_waitrequest=1'b0;
assign avs_port4_waitrequest=1'b0;
wire [WIDTH-1:0] data_out_a_unreg;
wire [WIDTH-1:0] data_out_b_unreg;
reg [WIDTH-1:0] data_out_a_reg;
reg [WIDTH-1:0] data_out_b_reg;
reg [WIDTH-1:0] data_out_a_reg2;
reg [WIDTH-1:0] data_out_b_reg2;
_acl_mem2x_shiftreg readatavalid_1(.D(avs_port1_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port1_readdatavalid));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_2(.D(avs_port2_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port2_readdatavalid));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_3(.D(avs_port3_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port3_readdatavalid));
defparam readatavalid_3.WIDTH = 1;
defparam readatavalid_3.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_4(.D(avs_port4_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port4_readdatavalid));
defparam readatavalid_4.WIDTH = 1;
defparam readatavalid_4.DEPTH = 4;
localparam PREFERRED_WIDTH=128;
localparam NUM_RAMS=((WIDTH+PREFERRED_WIDTH-1)/PREFERRED_WIDTH);
genvar n;
generate
for(n=0; n<NUM_RAMS; n++)
begin : block_n
localparam MY_WIDTH=( (n==NUM_RAMS-1) ? (WIDTH-(NUM_RAMS-1)*PREFERRED_WIDTH) : PREFERRED_WIDTH );
reg [LOG2DEPTH-1:0] addr_1_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg2x /* synthesis dont_merge */;
reg write_1_reg2x /* synthesis dont_merge */;
reg write_2_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_1_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_3_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_4_reg /* synthesis dont_merge */;
reg write_1_reg, write_2_reg /* synthesis dont_merge */;
reg write_3_reg, write_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_4_reg /* synthesis dont_merge */;
reg clk_90deg, sel2x /* synthesis dont_merge */;
//Convert clock to data signal
always@(negedge clk2x)
clk_90deg<=clk;
always@(posedge clk2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clk
always@(posedge clk2x)
begin
addr_1_reg2x <= (!sel2x) ? addr_2_reg : addr_1_reg;
addr_2_reg2x <= (!sel2x) ? addr_4_reg : addr_3_reg;
write_1_reg2x <= (!sel2x) ? write_2_reg : write_1_reg;
write_2_reg2x <= (!sel2x) ? write_4_reg : write_3_reg;
end
always@(posedge clk)
begin
addr_1_reg <= avs_port1_address;
addr_2_reg <= avs_port2_address;
addr_3_reg <= avs_port3_address;
addr_4_reg <= avs_port4_address;
write_1_reg <= avs_port1_write;
write_2_reg <= avs_port2_write;
write_3_reg <= avs_port3_write;
write_4_reg <= avs_port4_write;
end
//Register before double pumping
always@(posedge clk)
begin
data_1_reg <= avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_2_reg <= avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_3_reg <= avs_port3_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_4_reg <= avs_port4_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_1_reg <= avs_port1_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_2_reg <= avs_port2_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_3_reg <= avs_port3_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_4_reg <= avs_port4_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
// Consider making only one port r/w and the rest read only
always@(posedge clk2x)
begin
data_1_reg2x <= (!sel2x) ? data_2_reg : data_1_reg;
data_2_reg2x <= (!sel2x) ? data_4_reg : data_3_reg;
byteen_1_reg2x <= (!sel2x) ? byteen_2_reg : byteen_1_reg;
byteen_2_reg2x <= (!sel2x) ? byteen_4_reg : byteen_3_reg;
end
altsyncram altsyncram_component (
.clock0 (clk2x),
.wren_a (write_1_reg2x),
.wren_b (write_2_reg2x),
.address_a (addr_1_reg2x),
.address_b (addr_2_reg2x),
.data_a (data_1_reg2x),
.data_b (data_2_reg2x),
.q_a (data_out_a_unreg[n*PREFERRED_WIDTH +: MY_WIDTH]),
.q_b (data_out_b_unreg[n*PREFERRED_WIDTH +: MY_WIDTH]),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (byteen_1_reg2x),
.byteena_b (byteen_2_reg2x),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH_WORDS,
altsyncram_component.numwords_b = DEPTH_WORDS,
altsyncram_component.operation_mode = RAM_OPERATION_MODE,
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = RDW_MODE,
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = MY_WIDTH,
altsyncram_component.width_b = MY_WIDTH,
altsyncram_component.width_byteena_a = MY_WIDTH/8,
altsyncram_component.width_byteena_b = MY_WIDTH/8,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.ram_block_type = RAM_BLOCK_TYPE;
end
endgenerate
always@(posedge clk2x)
begin
data_out_a_reg<=data_out_a_unreg;
data_out_b_reg<=data_out_b_unreg;
data_out_a_reg2<=data_out_a_reg;
data_out_b_reg2<=data_out_b_reg;
end
always@(posedge clk)
begin
avs_port1_readdata <= data_out_a_reg;
avs_port2_readdata <= data_out_a_reg2;
avs_port3_readdata <= data_out_b_reg;
avs_port4_readdata <= data_out_b_reg2;
end
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module _acl_mem2x_shiftreg(D, clock, resetn, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, resetn, enable;
output [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn)
local_ffs <= '0;
else if (enable)
local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$PKG$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
state = 0;
invalid_rd = 0;
end else begin
case (state)
0 : begin
state = 0;
invalid_rd = 0;
if(req)begin
state = 1;
invalid_rd = invalid_rd_req;
end
end
1 : begin
state = 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
state = 0;
invalid_rd = 0;
end
end
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
sub a (.inst(1));
sub b (.inst(2));
initial begin
a.test1;
b.test1;
a.test2;
b.test2;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input integer inst);
import "DPI-C" context function int dpic_line();
import "DPI-C" context function int dpic_save(int value);
import "DPI-C" context function int dpic_restore();
import "DPI-C" context function int unsigned dpic_getcontext();
int result;
task test1;
// Check line numbering
`ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test
result = dpic_line(); if (!result) $stop;
`else
result = dpic_line(); if (result !== `__LINE__) $stop;
//
result = dpic_line(); if (result !== `__LINE__) $stop;
`endif
// Check save-restore
result = dpic_save(23+inst);
if (result==0) $stop;
endtask
task test2;
if (dpic_restore() != 23+inst) $stop;
endtask
int unsigned cntxt1;
int unsigned cntxt2;
initial begin
cntxt1 = dpic_getcontext();
begin : caller_context
// call from a different scope - should still get the context of the function declaration
cntxt2 = dpic_getcontext();
end
// svContext should be the context of the function declaration, not the context of the function call
if (cntxt1 != cntxt2) $stop;
end
endmodule
|
module timer #
(
parameter WIDTH = 64,
parameter USE_2XCLK = 0,
parameter S_WIDTH_A = 2
)
(
input clk,
input clk2x,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
input slave_write,
input [WIDTH/8-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH-1:0] slave_readdata,
output slave_readdatavalid
);
reg [WIDTH-1:0] counter;
reg [WIDTH-1:0] counter2x;
reg clock_sel;
always@(posedge clk or negedge resetn)
if (!resetn)
clock_sel <= 1'b0;
else if (slave_write)
if (|slave_writedata)
clock_sel <= 1'b1;
else
clock_sel <= 1'b0;
always@(posedge clk or negedge resetn)
if (!resetn)
counter <= {WIDTH{1'b0}};
else if (slave_write)
counter <= {WIDTH{1'b0}};
else
counter <= counter + 2'b01;
always@(posedge clk2x or negedge resetn)
if (!resetn)
counter2x <= {WIDTH{1'b0}};
else if (slave_write)
counter2x <= {WIDTH{1'b0}};
else
counter2x <= counter2x + 2'b01;
assign slave_waitrequest = 1'b0;
assign slave_readdata = (USE_2XCLK && clock_sel) ? counter2x : counter;
assign slave_readdatavalid = slave_read;
endmodule
|
/* Basic Gates */
module or2(output Z, input A, B);
wire i;
not(Z, i);
nor(i, A, B);
endmodule
module or4(output Z, input A, B, C, D);
wire [1:0]i;
or2 o0(i[0], A, B),
o1(i[1], C, D),
o2(Z, i[0], i[1]);
endmodule
module and2(output Z, input A, B);
nand(nz, A, B);
not(Z, nz);
endmodule
module and3(output Z, input A, B, C);
wire i;
and2 a0(i, A, B),
a1(Z, i, C);
endmodule
module xnor2(output Z, input A, B);
wire [1:0]i;
not(na, A);
not(nb, B);
and2 a0(i[0], A, B),
a1(i[1], na, nb);
or2 o0(Z, i[0], i[1]);
endmodule
module xor2(output Z, input A, B);
wire [1:0]i;
not (na, A);
not (nb, B);
and2 a0(i[0], A, nb),
a1(i[1], na, B);
or2 o0(Z, i[0], i[1]);
endmodule
/* ALU OP Codes */
module op_00(output Z, input A, B);
or2 o(Z, A, B);
endmodule
module op_01(output Z, input A, B);
xor2 x(Z, A, B);
endmodule
module op_10(output Z, input A, B, C);
wire i;
xnor2 x(i, B, C);
and2 a(Z, i, A);
endmodule
module op_11(output Z, input A, B, C);
wire i;
xor2 x(i, A, B);
nand n(Z, i, C);
endmodule
/* Mux (4) */
module mux_4_1(output Z, input [1:0] sel, input [3:0] i);
wire [1:0]n_s;
wire [3:0]a;
not(n_s[0], sel[0]);
not(n_s[1], sel[1]);
and3 a0(a[0], n_s[1], n_s[0], i[0]),
a1(a[1], n_s[1], sel[0], i[1]),
a2(a[2], sel[1], n_s[0], i[2]),
a3(a[3], sel[1], sel[0], i[3]);
or4 o0(Z, a[0], a[1], a[2], a[3]);
endmodule
/* ALUs */
module alu_01(output Z, input [1:0]op, input A, B, C);
wire [3:0]op_z;
op_00 op00(op_z[0], A, B);
op_01 op01(op_z[1], A, B);
op_10 op10(op_z[2], A, B, C);
op_11 op11(op_z[3], A, B, C);
mux_4_1 mux(Z, op, op_z);
endmodule
module alu_02(output [1:0]Z, input [1:0]op, input [1:0] A, B, C);
alu_01 a0(Z[0], op, A[0], B[0], C[0]),
a1(Z[1], op, A[1], B[1], C[1]);
endmodule
module alu_04(output [3:0]Z, input [1:0]op, input [3:0] A, B, C);
alu_02 a0(Z[1:0], op, A[1:0], B[1:0], C[1:0]),
a1(Z[3:2], op, A[3:2], B[3:2], C[3:2]);
endmodule
module alu_08(output [7:0]Z, input [1:0]op, input [7:0] A, B, C);
alu_04 a0(Z[3:0], op, A[3:0], B[3:0], C[3:0]),
a1(Z[7:4], op, A[7:4], B[7:4], C[7:4]);
endmodule
module alu_16(output [15:0]Z, input [1:0]op, input [15:0] A, B, C);
alu_08 a0(Z[7:0], op, A[7:0], B[7:0], C[7:0]),
a1(Z[15:8], op, A[15:8], B[15:8], C[15:8]);
endmodule
module alu_32(output [31:0]Z, input [1:0]op, input [31:0] A, B, C);
alu_16 a0(Z[15:0], op, A[15:0], B[15:0], C[15:0]),
a1(Z[31:16], op, A[31:16], B[31:16], C[31:16]);
endmodule
/* Testbench */
module p2_tb();
reg [31:0]A, B, C;
reg [1:0]op;
wire [31:0] Z;
alu_32 device(Z, op, A, B, C);
integer op_i, val_i;
initial begin
$dumpfile("p2.vcd");
$dumpvars(0, device);
$monitor("op(%b) A=%b B=%b C=%b => %b", op, A, B, C, Z);
for( op_i = 0; op_i <= 'b11; op_i = op_i + 1) begin
op = op_i[1:0];
for(val_i = 0; val_i <= 'b111; val_i = val_i + 1) begin
A = {32{val_i[2]}};
B = {32{val_i[1]}};
C = {32{val_i[0]}};
#10;
end
end
end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_MS__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_BEHAVIORAL_V |
// FIXME:
//
// Any l2 cache pipe can go to any directory (and viceversa). The reason is to
// allow a per bank SMT option (dc_pipe and l2_pipe) and to handle the TLB
// misses that can go out of bank.
//
// Effectively, a 4 pipe dual core can switch to a 8 independent l2 coherent
// cores. No need to have a switch command as the DCs and L2s are coherent.
module net_2core2dr(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
// c0 core L2I
,input logic c0_l2itodr_req_valid
,output logic c0_l2itodr_req_retry
,input I_l2todr_req_type c0_l2itodr_req
,output logic c0_drtol2i_snack_valid
,input logic c0_drtol2i_snack_retry
,output I_drtol2_snack_type c0_drtol2i_snack
,input c0_l2itodr_snoop_ack_valid
,output c0_l2itodr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2itodr_snoop_ack
,input logic c0_l2itodr_disp_valid
,output logic c0_l2itodr_disp_retry
,input I_l2todr_disp_type c0_l2itodr_disp
,output logic c0_drtol2i_dack_valid
,input logic c0_drtol2i_dack_retry
,output I_drtol2_dack_type c0_drtol2i_dack
,input logic c0_l2itodr_pfreq_valid
,output logic c0_l2itodr_pfreq_retry
,input I_l2todr_pfreq_type c0_l2itodr_pfreq
// c0 core L2I TLB
,input logic c0_l2ittodr_req_valid
,output logic c0_l2ittodr_req_retry
,input I_l2todr_req_type c0_l2ittodr_req
,output logic c0_drtol2it_snack_valid
,input logic c0_drtol2it_snack_retry
,output I_drtol2_snack_type c0_drtol2it_snack
,input c0_l2ittodr_snoop_ack_valid
,output c0_l2ittodr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2ittodr_snoop_ack
,input logic c0_l2ittodr_disp_valid
,output logic c0_l2ittodr_disp_retry
,input I_l2todr_disp_type c0_l2ittodr_disp
,output logic c0_drtol2it_dack_valid
,input logic c0_drtol2it_dack_retry
,output I_drtol2_dack_type c0_drtol2it_dack
// c0 core L2D
,input logic c0_l2d_0todr_req_valid
,output logic c0_l2d_0todr_req_retry
,input I_l2todr_req_type c0_l2d_0todr_req
,output logic c0_drtol2d_0_snack_valid
,input logic c0_drtol2d_0_snack_retry
,output I_drtol2_snack_type c0_drtol2d_0_snack
,input c0_l2d_0todr_snoop_ack_valid
,output c0_l2d_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2d_0todr_snoop_ack
,input logic c0_l2d_0todr_disp_valid
,output logic c0_l2d_0todr_disp_retry
,input I_l2todr_disp_type c0_l2d_0todr_disp
,output logic c0_drtol2d_0_dack_valid
,input logic c0_drtol2d_0_dack_retry
,output I_drtol2_dack_type c0_drtol2d_0_dack
,input logic c0_l2d_0todr_pfreq_valid
,output logic c0_l2d_0todr_pfreq_retry
,input I_l2todr_pfreq_type c0_l2d_0todr_pfreq
// c0 core L2D TLB
,input logic c0_l2dt_0todr_req_valid
,output logic c0_l2dt_0todr_req_retry
,input I_l2todr_req_type c0_l2dt_0todr_req
,output logic c0_drtol2dt_0_snack_valid
,input logic c0_drtol2dt_0_snack_retry
,output I_drtol2_snack_type c0_drtol2dt_0_snack
,input c0_l2dt_0todr_snoop_ack_valid
,output c0_l2dt_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2dt_0todr_snoop_ack
,input logic c0_l2dt_0todr_disp_valid
,output logic c0_l2dt_0todr_disp_retry
,input I_l2todr_disp_type c0_l2dt_0todr_disp
,output logic c0_drtol2dt_0_dack_valid
,input logic c0_drtol2dt_0_dack_retry
,output I_drtol2_dack_type c0_drtol2dt_0_dack
// c1 core L2I
,input logic c1_l2itodr_req_valid
,output logic c1_l2itodr_req_retry
,input I_l2todr_req_type c1_l2itodr_req
,output logic c1_drtol2i_snack_valid
,input logic c1_drtol2i_snack_retry
,output I_drtol2_snack_type c1_drtol2i_snack
,input c1_l2itodr_snoop_ack_valid
,output c1_l2itodr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2itodr_snoop_ack
,input logic c1_l2itodr_disp_valid
,output logic c1_l2itodr_disp_retry
,input I_l2todr_disp_type c1_l2itodr_disp
,output logic c1_drtol2i_dack_valid
,input logic c1_drtol2i_dack_retry
,output I_drtol2_dack_type c1_drtol2i_dack
,input logic c1_l2itodr_pfreq_valid
,output logic c1_l2itodr_pfreq_retry
,input I_l2todr_pfreq_type c1_l2itodr_pfreq
// c1 core L2I TLB
,input logic c1_l2ittodr_req_valid
,output logic c1_l2ittodr_req_retry
,input I_l2todr_req_type c1_l2ittodr_req
,output logic c1_drtol2it_snack_valid
,input logic c1_drtol2it_snack_retry
,output I_drtol2_snack_type c1_drtol2it_snack
,input c1_l2ittodr_snoop_ack_valid
,output c1_l2ittodr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2ittodr_snoop_ack
,input logic c1_l2ittodr_disp_valid
,output logic c1_l2ittodr_disp_retry
,input I_l2todr_disp_type c1_l2ittodr_disp
,output logic c1_drtol2it_dack_valid
,input logic c1_drtol2it_dack_retry
,output I_drtol2_dack_type c1_drtol2it_dack
// c1 core L2D
,input logic c1_l2d_0todr_req_valid
,output logic c1_l2d_0todr_req_retry
,input I_l2todr_req_type c1_l2d_0todr_req
,output logic c1_drtol2d_0_snack_valid
,input logic c1_drtol2d_0_snack_retry
,output I_drtol2_snack_type c1_drtol2d_0_snack
,input c1_l2d_0todr_snoop_ack_valid
,output c1_l2d_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2d_0todr_snoop_ack
,input logic c1_l2d_0todr_disp_valid
,output logic c1_l2d_0todr_disp_retry
,input I_l2todr_disp_type c1_l2d_0todr_disp
,output logic c1_drtol2d_0_dack_valid
,input logic c1_drtol2d_0_dack_retry
,output I_drtol2_dack_type c1_drtol2d_0_dack
,input logic c1_l2d_0todr_pfreq_valid
,output logic c1_l2d_0todr_pfreq_retry
,input I_l2todr_pfreq_type c1_l2d_0todr_pfreq
// c1 core L2D TLB
,input logic c1_l2dt_0todr_req_valid
,output logic c1_l2dt_0todr_req_retry
,input I_l2todr_req_type c1_l2dt_0todr_req
,output logic c1_drtol2dt_0_snack_valid
,input logic c1_drtol2dt_0_snack_retry
,output I_drtol2_snack_type c1_drtol2dt_0_snack
,input c1_l2dt_0todr_snoop_ack_valid
,output c1_l2dt_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2dt_0todr_snoop_ack
,input logic c1_l2dt_0todr_disp_valid
,output logic c1_l2dt_0todr_disp_retry
,input I_l2todr_disp_type c1_l2dt_0todr_disp
,output logic c1_drtol2dt_0_dack_valid
,input logic c1_drtol2dt_0_dack_retry
,output I_drtol2_dack_type c1_drtol2dt_0_dack
// directory 0
,output l2todr0_req_valid
,input l2todr0_req_retry
,output I_l2todr_req_type l2todr0_req
,input dr0tol2_snack_valid
,output dr0tol2_snack_retry
,input I_drtol2_snack_type dr0tol2_snack
,output l2todr0_disp_valid
,input l2todr0_disp_retry
,output I_l2todr_disp_type l2todr0_disp
,input dr0tol2_dack_valid
,output dr0tol2_dack_retry
,input I_drtol2_dack_type dr0tol2_dack
,output l2todr0_snoop_ack_valid
,input l2todr0_snoop_ack_retry
,output I_drsnoop_ack_type l2todr0_snoop_ack
,output logic l2todr0_pfreq_valid
,input logic l2todr0_pfreq_retry
,output I_l2todr_pfreq_type l2todr0_pfreq
// directory 1
,output l2todr1_req_valid
,input l2todr1_req_retry
,output I_l2todr_req_type l2todr1_req
,input dr1tol2_snack_valid
,output dr1tol2_snack_retry
,input I_drtol2_snack_type dr1tol2_snack
,output l2todr1_disp_valid
,input l2todr1_disp_retry
,output I_l2todr_disp_type l2todr1_disp
,input dr1tol2_dack_valid
,output dr1tol2_dack_retry
,input I_drtol2_dack_type dr1tol2_dack
,output l2todr1_snoop_ack_valid
,input l2todr1_snoop_ack_retry
,output I_drsnoop_ack_type l2todr1_snoop_ack
,output logic l2todr1_pfreq_valid
,input logic l2todr1_pfreq_retry
,output I_l2todr_pfreq_type l2todr1_pfreq
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
);
// Input reqs to directory
I_l2todr_req_type l2todr0_req_next;
I_l2todr_req_type l2todr1_req_next;
// Give some order to our valid REQ signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_req_valid;
assign c0_l2itodr0_req_valid = c0_l2itodr_req_valid & ~c0_l2itodr_req.paddr[9];
logic c0_l2itodr1_req_valid;
assign c0_l2itodr1_req_valid = c0_l2itodr_req_valid & c0_l2itodr_req.paddr[9];
// c0 l2 instruction cache tlb
logic c0_l2ittodr0_req_valid;
assign c0_l2ittodr0_req_valid = c0_l2ittodr_req_valid & ~c0_l2ittodr_req.paddr[9];
logic c0_l2ittodr1_req_valid;
assign c0_l2ittodr1_req_valid = c0_l2ittodr_req_valid & c0_l2ittodr_req.paddr[9];
// c0 l2 data cache
logic c0_l2d_0todr0_req_valid;
assign c0_l2d_0todr0_req_valid = c0_l2d_0todr_req_valid & ~c0_l2d_0todr_req.paddr[9];
logic c0_l2d_0todr1_req_valid;
assign c0_l2d_0todr1_req_valid = c0_l2d_0todr_req_valid & c0_l2d_0todr_req.paddr[9];
// c0 l2 data tlb
logic c0_l2dt_0todr0_req_valid;
assign c0_l2dt_0todr0_req_valid = c0_l2dt_0todr_req_valid & ~c0_l2dt_0todr_req.paddr[9];
logic c0_l2dt_0todr1_req_valid;
assign c0_l2dt_0todr1_req_valid = c0_l2dt_0todr_req_valid & c0_l2dt_0todr_req.paddr[9];
// c1 l2 instruction cache
logic c1_l2itodr0_req_valid;
assign c1_l2itodr0_req_valid = c1_l2itodr_req_valid & ~c1_l2itodr_req.paddr[9];
logic c1_l2itodr1_req_valid;
assign c1_l2itodr1_req_valid = c1_l2itodr_req_valid & c1_l2itodr_req.paddr[9];
// c1 l2 instruction cache tlb
logic c1_l2ittodr0_req_valid;
assign c1_l2ittodr0_req_valid = c1_l2ittodr_req_valid & ~c1_l2ittodr_req.paddr[9];
logic c1_l2ittodr1_req_valid;
assign c1_l2ittodr1_req_valid = c1_l2ittodr_req_valid & c1_l2ittodr_req.paddr[9];
// c1 l2 data cache
logic c1_l2d_0todr0_req_valid;
assign c1_l2d_0todr0_req_valid = c1_l2d_0todr_req_valid & ~c1_l2d_0todr_req.paddr[9];
logic c1_l2d_0todr1_req_valid;
assign c1_l2d_0todr1_req_valid = c1_l2d_0todr_req_valid & c1_l2d_0todr_req.paddr[9];
// c1 l2 data tlb
logic c1_l2dt_0todr0_req_valid;
assign c1_l2dt_0todr0_req_valid = c1_l2dt_0todr_req_valid & ~c1_l2dt_0todr_req.paddr[9];
logic c1_l2dt_0todr1_req_valid;
assign c1_l2dt_0todr1_req_valid = c1_l2dt_0todr_req_valid & c1_l2dt_0todr_req.paddr[9];
logic c0_l2todr0_req_valid;
logic c0_l2todr1_req_valid;
logic c1_l2todr0_req_valid;
logic c1_l2todr1_req_valid;
logic l2todr0_req_inp_valid;
logic l2todr1_req_inp_valid;
assign c0_l2todr0_req_valid = c0_l2itodr0_req_valid|c0_l2ittodr0_req_valid|c0_l2d_0todr0_req_valid|c0_l2dt_0todr0_req_valid;
assign c0_l2todr1_req_valid = c0_l2itodr1_req_valid|c0_l2ittodr1_req_valid|c0_l2d_0todr1_req_valid|c0_l2dt_0todr1_req_valid;
assign c1_l2todr0_req_valid = c1_l2itodr0_req_valid|c1_l2ittodr0_req_valid|c1_l2d_0todr0_req_valid|c1_l2dt_0todr0_req_valid;
assign c1_l2todr1_req_valid = c1_l2itodr1_req_valid|c1_l2ittodr1_req_valid|c1_l2d_0todr1_req_valid|c1_l2dt_0todr1_req_valid;
assign l2todr0_req_inp_valid = c0_l2todr0_req_valid | c1_l2todr0_req_valid;
assign l2todr1_req_inp_valid = c0_l2todr1_req_valid | c1_l2todr1_req_valid;
logic c0_l2itodr0_req_retry;
logic c0_l2ittodr0_req_retry;
logic c0_l2d_0todr0_req_retry;
logic c0_l2dt_0todr0_req_retry;
logic c1_l2itodr0_req_retry;
logic c1_l2ittodr0_req_retry;
logic c1_l2d_0todr0_req_retry;
logic c1_l2dt_0todr0_req_retry;
logic c0_l2itodr1_req_retry;
logic c0_l2ittodr1_req_retry;
logic c0_l2d_0todr1_req_retry;
logic c0_l2dt_0todr1_req_retry;
logic c1_l2itodr1_req_retry;
logic c1_l2ittodr1_req_retry;
logic c1_l2d_0todr1_req_retry;
logic c1_l2dt_0todr1_req_retry;
logic l2todr_req_inp0_retry;
logic l2todr_req_inp1_retry;
//***********************REQs**********************
// For every request if the request is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 reqs
always_comb begin
c0_l2itodr0_req_retry = 1;
c0_l2ittodr0_req_retry = 1;
c0_l2d_0todr0_req_retry = 1;
c0_l2dt_0todr0_req_retry = 1;
c1_l2itodr0_req_retry = 1;
c1_l2ittodr0_req_retry = 1;
c1_l2d_0todr0_req_retry = 1;
c1_l2dt_0todr0_req_retry = 1;
if (c0_l2itodr0_req_valid) begin
l2todr0_req_next = c0_l2itodr_req;
c0_l2itodr0_req_retry = l2todr_req_inp0_retry;
end else if (c0_l2ittodr0_req_valid) begin
c0_l2ittodr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2ittodr_req;
end else if (c0_l2d_0todr0_req_valid) begin
c0_l2d_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2d_0todr_req;
end else if (c0_l2dt_0todr0_req_valid) begin
c0_l2dt_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2dt_0todr_req;
end else if (c1_l2itodr0_req_valid) begin
l2todr0_req_next = c1_l2itodr_req;
c1_l2itodr0_req_retry = l2todr_req_inp0_retry;
end else if (c1_l2ittodr0_req_valid) begin
c1_l2ittodr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2ittodr_req;
end else if (c1_l2d_0todr0_req_valid) begin
c1_l2d_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2d_0todr_req;
end else if (c1_l2dt_0todr0_req_valid) begin
c1_l2dt_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2dt_0todr_req;
end
end
// Handle DIR 1 reqs
always_comb begin
c0_l2itodr1_req_retry = 1;
c0_l2ittodr1_req_retry = 1;
c0_l2d_0todr1_req_retry = 1;
c0_l2dt_0todr1_req_retry = 1;
c1_l2itodr1_req_retry = 1;
c1_l2ittodr1_req_retry = 1;
c1_l2d_0todr1_req_retry = 1;
c1_l2dt_0todr1_req_retry = 1;
if (c0_l2itodr1_req_valid) begin
c0_l2itodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c0_l2itodr_req;
end else if (c0_l2ittodr1_req_valid) begin
c0_l2ittodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c0_l2ittodr_req;
end else if (c0_l2d_0todr1_req_valid) begin
c0_l2d_0todr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c0_l2d_0todr_req;
end else if (c0_l2dt_0todr1_req_valid) begin
c0_l2dt_0todr1_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2dt_0todr_req;
end else if (c1_l2itodr1_req_valid) begin
c1_l2itodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c1_l2itodr_req;
end else if (c1_l2ittodr1_req_valid) begin
c1_l2ittodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c1_l2ittodr_req;
end else if (c1_l2d_0todr1_req_valid) begin
c1_l2d_0todr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c1_l2d_0todr_req;
end else if (c1_l2d_0todr1_req_valid) begin
c1_l2dt_0todr1_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2dt_0todr_req;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid request to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_req_retry = c0_l2itodr0_req_retry & c0_l2itodr1_req_retry;
c0_l2ittodr_req_retry = c0_l2ittodr0_req_retry & c0_l2ittodr1_req_retry;
c0_l2d_0todr_req_retry = c0_l2d_0todr0_req_retry & c0_l2d_0todr1_req_retry;
c0_l2dt_0todr_req_retry = c0_l2dt_0todr0_req_retry & c0_l2dt_0todr1_req_retry;
c1_l2itodr_req_retry = c1_l2itodr0_req_retry & c1_l2itodr1_req_retry;
c1_l2ittodr_req_retry = c1_l2ittodr0_req_retry & c1_l2ittodr1_req_retry;
c1_l2d_0todr_req_retry = c1_l2d_0todr0_req_retry & c1_l2d_0todr1_req_retry;
c1_l2dt_0todr_req_retry = c1_l2dt_0todr0_req_retry & c1_l2dt_0todr1_req_retry;
end
fflop #(.Size($bits(I_l2todr_req_type))) req_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_req_next),
.dinValid (l2todr0_req_inp_valid),
.dinRetry (l2todr_req_inp0_retry),
.q (l2todr0_req),
.qValid (l2todr0_req_valid),
.qRetry (l2todr0_req_retry)
);
fflop #(.Size($bits(I_l2todr_req_type))) req_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_req_next),
.dinValid (l2todr1_req_inp_valid),
.dinRetry (l2todr_req_inp1_retry),
.q (l2todr1_req),
.qValid (l2todr1_req_valid),
.qRetry (l2todr1_req_retry)
);
// Input disps to directory
I_l2todr_disp_type l2todr0_disp_next;
I_l2todr_disp_type l2todr1_disp_next;
// Give some order to our valid DISP signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_disp_valid;
assign c0_l2itodr0_disp_valid = c0_l2itodr_disp_valid & ~c0_l2itodr_disp.paddr[9];
logic c0_l2itodr1_disp_valid;
assign c0_l2itodr1_disp_valid = c0_l2itodr_disp_valid & c0_l2itodr_disp.paddr[9];
// c0 l2 instruction cache tlb
logic c0_l2ittodr0_disp_valid;
assign c0_l2ittodr0_disp_valid = c0_l2ittodr_disp_valid & ~c0_l2ittodr_disp.paddr[9];
logic c0_l2ittodr1_disp_valid;
assign c0_l2ittodr1_disp_valid = c0_l2ittodr_disp_valid & c0_l2ittodr_disp.paddr[9];
// c0 l2 data cache
logic c0_l2d_0todr0_disp_valid;
assign c0_l2d_0todr0_disp_valid = c0_l2d_0todr_disp_valid & ~c0_l2d_0todr_disp.paddr[9];
logic c0_l2d_0todr1_disp_valid;
assign c0_l2d_0todr1_disp_valid = c0_l2d_0todr_disp_valid & c0_l2d_0todr_disp.paddr[9];
// c0 l2 data tlb
logic c0_l2dt_0todr0_disp_valid;
assign c0_l2dt_0todr0_disp_valid = c0_l2dt_0todr_disp_valid & ~c0_l2dt_0todr_disp.paddr[9];
logic c0_l2dt_0todr1_disp_valid;
assign c0_l2dt_0todr1_disp_valid = c0_l2dt_0todr_disp_valid & c0_l2dt_0todr_disp.paddr[9];
// c1 l2 instruction cache
logic c1_l2itodr0_disp_valid;
assign c1_l2itodr0_disp_valid = c1_l2itodr_disp_valid & ~c1_l2itodr_disp.paddr[9];
logic c1_l2itodr1_disp_valid;
assign c1_l2itodr1_disp_valid = c1_l2itodr_disp_valid & c1_l2itodr_disp.paddr[9];
// c1 l2 instruction cache tlb
logic c1_l2ittodr0_disp_valid;
assign c1_l2ittodr0_disp_valid = c1_l2ittodr_disp_valid & ~c1_l2ittodr_disp.paddr[9];
logic c1_l2ittodr1_disp_valid;
assign c1_l2ittodr1_disp_valid = c1_l2ittodr_disp_valid & c1_l2ittodr_disp.paddr[9];
// c1 l2 data cache
logic c1_l2d_0todr0_disp_valid;
assign c1_l2d_0todr0_disp_valid = c1_l2d_0todr_disp_valid & ~c1_l2d_0todr_disp.paddr[9];
logic c1_l2d_0todr1_disp_valid;
assign c1_l2d_0todr1_disp_valid = c1_l2d_0todr_disp_valid & c1_l2d_0todr_disp.paddr[9];
// c1 l2 data tlb
logic c1_l2dt_0todr0_disp_valid;
assign c1_l2dt_0todr0_disp_valid = c1_l2dt_0todr_disp_valid & ~c1_l2dt_0todr_disp.paddr[9];
logic c1_l2dt_0todr1_disp_valid;
assign c1_l2dt_0todr1_disp_valid = c1_l2dt_0todr_disp_valid & c1_l2dt_0todr_disp.paddr[9];
logic c0_l2todr0_disp_valid;
logic c0_l2todr1_disp_valid;
logic c1_l2todr0_disp_valid;
logic c1_l2todr1_disp_valid;
logic l2todr0_disp_inp_valid;
logic l2todr1_disp_inp_valid;
assign c0_l2todr0_disp_valid = c0_l2itodr0_disp_valid|c0_l2ittodr0_disp_valid|c0_l2d_0todr0_disp_valid|c0_l2dt_0todr0_disp_valid;
assign c0_l2todr1_disp_valid = c0_l2itodr1_disp_valid|c0_l2ittodr1_disp_valid|c0_l2d_0todr1_disp_valid|c0_l2dt_0todr1_disp_valid;
assign c1_l2todr0_disp_valid = c1_l2itodr0_disp_valid|c1_l2ittodr0_disp_valid|c1_l2d_0todr0_disp_valid|c1_l2dt_0todr0_disp_valid;
assign c1_l2todr1_disp_valid = c1_l2itodr1_disp_valid|c1_l2ittodr1_disp_valid|c1_l2d_0todr1_disp_valid|c1_l2dt_0todr1_disp_valid;
assign l2todr0_disp_inp_valid = c0_l2todr0_disp_valid | c1_l2todr0_disp_valid;
assign l2todr1_disp_inp_valid = c0_l2todr1_disp_valid | c1_l2todr1_disp_valid;
logic c0_l2itodr0_disp_retry;
logic c0_l2ittodr0_disp_retry;
logic c0_l2d_0todr0_disp_retry;
logic c0_l2dt_0todr0_disp_retry;
logic c1_l2itodr0_disp_retry;
logic c1_l2ittodr0_disp_retry;
logic c1_l2d_0todr0_disp_retry;
logic c1_l2dt_0todr0_disp_retry;
logic c0_l2itodr1_disp_retry;
logic c0_l2ittodr1_disp_retry;
logic c0_l2d_0todr1_disp_retry;
logic c0_l2dt_0todr1_disp_retry;
logic c1_l2itodr1_disp_retry;
logic c1_l2ittodr1_disp_retry;
logic c1_l2d_0todr1_disp_retry;
logic c1_l2dt_0todr1_disp_retry;
logic l2todr_disp_inp0_retry;
logic l2todr_disp_inp1_retry;
//***********************disps**********************
// For every disp if the disp is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 disps
always_comb begin
c0_l2itodr0_disp_retry = 1;
c0_l2ittodr0_disp_retry = 1;
c0_l2d_0todr0_disp_retry = 1;
c0_l2dt_0todr0_disp_retry = 1;
c1_l2itodr0_disp_retry = 1;
c1_l2ittodr0_disp_retry = 1;
c1_l2d_0todr0_disp_retry = 1;
c1_l2dt_0todr0_disp_retry = 1;
if (c0_l2itodr0_disp_valid) begin
l2todr0_disp_next = c0_l2itodr_disp;
c0_l2itodr0_disp_retry = l2todr_disp_inp0_retry;
end else if (c0_l2ittodr0_disp_valid) begin
c0_l2ittodr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2ittodr_disp;
end else if (c0_l2d_0todr0_disp_valid) begin
c0_l2d_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2d_0todr_disp;
end else if (c0_l2dt_0todr0_disp_valid) begin
c0_l2dt_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2dt_0todr_disp;
end else if (c1_l2itodr0_disp_valid) begin
l2todr0_disp_next = c1_l2itodr_disp;
c1_l2itodr0_disp_retry = l2todr_disp_inp0_retry;
end else if (c1_l2ittodr0_disp_valid) begin
c1_l2ittodr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2ittodr_disp;
end else if (c1_l2d_0todr0_disp_valid) begin
c1_l2d_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2d_0todr_disp;
end else if (c1_l2dt_0todr0_disp_valid) begin
c1_l2dt_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2dt_0todr_disp;
end
end
// Handle DIR 1 disps
always_comb begin
c0_l2itodr1_disp_retry = 1;
c0_l2ittodr1_disp_retry = 1;
c0_l2d_0todr1_disp_retry = 1;
c0_l2dt_0todr1_disp_retry = 1;
c1_l2itodr1_disp_retry = 1;
c1_l2ittodr1_disp_retry = 1;
c1_l2d_0todr1_disp_retry = 1;
c1_l2dt_0todr1_disp_retry = 1;
if (c0_l2itodr1_disp_valid) begin
c0_l2itodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c0_l2itodr_disp;
end else if (c0_l2ittodr1_disp_valid) begin
c0_l2ittodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c0_l2ittodr_disp;
end else if (c0_l2d_0todr1_disp_valid) begin
c0_l2d_0todr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c0_l2d_0todr_disp;
end else if (c0_l2dt_0todr1_disp_valid) begin
c0_l2dt_0todr1_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2dt_0todr_disp;
end else if (c1_l2itodr1_disp_valid) begin
c1_l2itodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c1_l2itodr_disp;
end else if (c1_l2ittodr1_disp_valid) begin
c1_l2ittodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c1_l2ittodr_disp;
end else if (c1_l2d_0todr1_disp_valid) begin
c1_l2d_0todr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c1_l2d_0todr_disp;
end else if (c1_l2d_0todr1_disp_valid) begin
c1_l2dt_0todr1_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2dt_0todr_disp;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid dispuest to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_disp_retry = c0_l2itodr0_disp_retry & c0_l2itodr1_disp_retry;
c0_l2ittodr_disp_retry = c0_l2ittodr0_disp_retry & c0_l2ittodr1_disp_retry;
c0_l2d_0todr_disp_retry = c0_l2d_0todr0_disp_retry & c0_l2d_0todr1_disp_retry;
c0_l2dt_0todr_disp_retry = c0_l2dt_0todr0_disp_retry & c0_l2dt_0todr1_disp_retry;
c1_l2itodr_disp_retry = c1_l2itodr0_disp_retry & c1_l2itodr1_disp_retry;
c1_l2ittodr_disp_retry = c1_l2ittodr0_disp_retry & c1_l2ittodr1_disp_retry;
c1_l2d_0todr_disp_retry = c1_l2d_0todr0_disp_retry & c1_l2d_0todr1_disp_retry;
c1_l2dt_0todr_disp_retry = c1_l2dt_0todr0_disp_retry & c1_l2dt_0todr1_disp_retry;
end
fflop #(.Size($bits(I_l2todr_disp_type))) disp_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_disp_next),
.dinValid (l2todr0_disp_inp_valid),
.dinRetry (l2todr_disp_inp0_retry),
.q (l2todr0_disp),
.qValid (l2todr0_disp_valid),
.qRetry (l2todr0_disp_retry)
);
fflop #(.Size($bits(I_l2todr_disp_type))) disp_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_disp_next),
.dinValid (l2todr1_disp_inp_valid),
.dinRetry (l2todr_disp_inp1_retry),
.q (l2todr1_disp),
.qValid (l2todr1_disp_valid),
.qRetry (l2todr1_disp_retry)
);
// Input pfreqs to directory
I_l2todr_pfreq_type l2todr0_pfreq_next;
I_l2todr_pfreq_type l2todr1_pfreq_next;
// Give some order to our valid pfreq signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_pfreq_valid;
assign c0_l2itodr0_pfreq_valid = c0_l2itodr_pfreq_valid & ~c0_l2itodr_pfreq.paddr[9];
logic c0_l2itodr1_pfreq_valid;
assign c0_l2itodr1_pfreq_valid = c0_l2itodr_pfreq_valid & c0_l2itodr_pfreq.paddr[9];
// c0 l2 data cache
logic c0_l2d_0todr0_pfreq_valid;
assign c0_l2d_0todr0_pfreq_valid = c0_l2d_0todr_pfreq_valid & ~c0_l2d_0todr_pfreq.paddr[9];
logic c0_l2d_0todr1_pfreq_valid;
assign c0_l2d_0todr1_pfreq_valid = c0_l2d_0todr_pfreq_valid & c0_l2d_0todr_pfreq.paddr[9];
// c1 l2 instruction cache
logic c1_l2itodr0_pfreq_valid;
assign c1_l2itodr0_pfreq_valid = c1_l2itodr_pfreq_valid & ~c1_l2itodr_pfreq.paddr[9];
logic c1_l2itodr1_pfreq_valid;
assign c1_l2itodr1_pfreq_valid = c1_l2itodr_pfreq_valid & c1_l2itodr_pfreq.paddr[9];
// c1 l2 data cache
logic c1_l2d_0todr0_pfreq_valid;
assign c1_l2d_0todr0_pfreq_valid = c1_l2d_0todr_pfreq_valid & ~c1_l2d_0todr_pfreq.paddr[9];
logic c1_l2d_0todr1_pfreq_valid;
assign c1_l2d_0todr1_pfreq_valid = c1_l2d_0todr_pfreq_valid & c1_l2d_0todr_pfreq.paddr[9];
logic c0_l2todr0_pfreq_valid;
logic c0_l2todr1_pfreq_valid;
logic c1_l2todr0_pfreq_valid;
logic c1_l2todr1_pfreq_valid;
logic l2todr0_pfreq_inp_valid;
logic l2todr1_pfreq_inp_valid;
assign c0_l2todr0_pfreq_valid = c0_l2itodr0_pfreq_valid|c0_l2d_0todr0_pfreq_valid;
assign c0_l2todr1_pfreq_valid = c0_l2itodr1_pfreq_valid|c0_l2d_0todr1_pfreq_valid;
assign c1_l2todr0_pfreq_valid = c1_l2itodr0_pfreq_valid|c1_l2d_0todr0_pfreq_valid;
assign c1_l2todr1_pfreq_valid = c1_l2itodr1_pfreq_valid|c1_l2d_0todr1_pfreq_valid;
assign l2todr0_pfreq_inp_valid = c0_l2todr0_pfreq_valid | c1_l2todr0_pfreq_valid;
assign l2todr1_pfreq_inp_valid = c0_l2todr1_pfreq_valid | c1_l2todr1_pfreq_valid;
logic c0_l2itodr0_pfreq_retry;
logic c0_l2d_0todr0_pfreq_retry;
logic c1_l2itodr0_pfreq_retry;
logic c1_l2d_0todr0_pfreq_retry;
logic c0_l2itodr1_pfreq_retry;
logic c0_l2d_0todr1_pfreq_retry;
logic c1_l2itodr1_pfreq_retry;
logic c1_l2d_0todr1_pfreq_retry;
logic l2todr_pfreq_inp0_retry;
logic l2todr_pfreq_inp1_retry;
//***********************pfreqs**********************
// For every pfreq if the pfreq is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 pfreqs
always_comb begin
c0_l2itodr0_pfreq_retry = 1;
c0_l2d_0todr0_pfreq_retry = 1;
c1_l2itodr0_pfreq_retry = 1;
c1_l2d_0todr0_pfreq_retry = 1;
if (c0_l2itodr0_pfreq_valid) begin
l2todr0_pfreq_next = c0_l2itodr_pfreq;
c0_l2itodr0_pfreq_retry = l2todr_pfreq_inp0_retry;
end else if (c0_l2d_0todr0_pfreq_valid) begin
c0_l2d_0todr0_pfreq_retry = l2todr_pfreq_inp0_retry;
l2todr0_pfreq_next = c0_l2d_0todr_pfreq;
end else if (c1_l2itodr0_pfreq_valid) begin
l2todr0_pfreq_next = c1_l2itodr_pfreq;
c1_l2itodr0_pfreq_retry = l2todr_pfreq_inp0_retry;
end else if (c1_l2d_0todr0_pfreq_valid) begin
c1_l2d_0todr0_pfreq_retry = l2todr_pfreq_inp0_retry;
l2todr0_pfreq_next = c1_l2d_0todr_pfreq;
end
end
// Handle DIR 1 pfreqs
always_comb begin
c0_l2itodr1_pfreq_retry = 1;
c0_l2d_0todr1_pfreq_retry = 1;
c1_l2itodr1_pfreq_retry = 1;
c1_l2d_0todr1_pfreq_retry = 1;
if (c0_l2itodr1_pfreq_valid) begin
c0_l2itodr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c0_l2itodr_pfreq;
end else if (c0_l2d_0todr1_pfreq_valid) begin
c0_l2d_0todr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c0_l2d_0todr_pfreq;
end else if (c1_l2itodr1_pfreq_valid) begin
c1_l2itodr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c1_l2itodr_pfreq;
end else if (c1_l2d_0todr1_pfreq_valid) begin
c1_l2d_0todr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c1_l2d_0todr_pfreq;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid pfrequest to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_pfreq_retry = c0_l2itodr0_pfreq_retry & c0_l2itodr1_pfreq_retry;
c0_l2d_0todr_pfreq_retry = c0_l2d_0todr0_pfreq_retry & c0_l2d_0todr1_pfreq_retry;
c1_l2itodr_pfreq_retry = c1_l2itodr0_pfreq_retry & c1_l2itodr1_pfreq_retry;
c1_l2d_0todr_pfreq_retry = c1_l2d_0todr0_pfreq_retry & c1_l2d_0todr1_pfreq_retry;
end
fflop #(.Size($bits(I_l2todr_pfreq_type))) pfreq_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_pfreq_next),
.dinValid (l2todr0_pfreq_inp_valid),
.dinRetry (l2todr_pfreq_inp0_retry),
.q (l2todr0_pfreq),
.qValid (l2todr0_pfreq_valid),
.qRetry (l2todr0_pfreq_retry)
);
fflop #(.Size($bits(I_l2todr_pfreq_type))) pfreq_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_pfreq_next),
.dinValid (l2todr1_pfreq_inp_valid),
.dinRetry (l2todr_pfreq_inp1_retry),
.q (l2todr1_pfreq),
.qValid (l2todr1_pfreq_valid),
.qRetry (l2todr1_pfreq_retry)
);
// Input snoop_acks to directory
I_l2snoop_ack_type l2todr0_snoop_ack_next;
I_l2snoop_ack_type l2todr1_snoop_ack_next;
// Give some order to our valid snoop_ack signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_snoop_ack_valid;
assign c0_l2itodr0_snoop_ack_valid = c0_l2itodr_snoop_ack_valid & ~c0_l2itodr_snoop_ack.directory_id[0];
logic c0_l2itodr1_snoop_ack_valid;
assign c0_l2itodr1_snoop_ack_valid = c0_l2itodr_snoop_ack_valid & c0_l2itodr_snoop_ack.directory_id[0];
// c0 l2 instruction cache tlb
logic c0_l2ittodr0_snoop_ack_valid;
assign c0_l2ittodr0_snoop_ack_valid = c0_l2ittodr_snoop_ack_valid & ~c0_l2ittodr_snoop_ack.directory_id[0];
logic c0_l2ittodr1_snoop_ack_valid;
assign c0_l2ittodr1_snoop_ack_valid = c0_l2ittodr_snoop_ack_valid & c0_l2ittodr_snoop_ack.directory_id[0];
// c0 l2 data cache
logic c0_l2d_0todr0_snoop_ack_valid;
assign c0_l2d_0todr0_snoop_ack_valid = c0_l2d_0todr_snoop_ack_valid & ~c0_l2d_0todr_snoop_ack.directory_id[0];
logic c0_l2d_0todr1_snoop_ack_valid;
assign c0_l2d_0todr1_snoop_ack_valid = c0_l2d_0todr_snoop_ack_valid & c0_l2d_0todr_snoop_ack.directory_id[0];
// c0 l2 data tlb
logic c0_l2dt_0todr0_snoop_ack_valid;
assign c0_l2dt_0todr0_snoop_ack_valid = c0_l2dt_0todr_snoop_ack_valid & ~c0_l2dt_0todr_snoop_ack.directory_id[0];
logic c0_l2dt_0todr1_snoop_ack_valid;
assign c0_l2dt_0todr1_snoop_ack_valid = c0_l2dt_0todr_snoop_ack_valid & c0_l2dt_0todr_snoop_ack.directory_id[0];
// c1 l2 instruction cache
logic c1_l2itodr0_snoop_ack_valid;
assign c1_l2itodr0_snoop_ack_valid = c1_l2itodr_snoop_ack_valid & ~c1_l2itodr_snoop_ack.directory_id[0];
logic c1_l2itodr1_snoop_ack_valid;
assign c1_l2itodr1_snoop_ack_valid = c1_l2itodr_snoop_ack_valid & c1_l2itodr_snoop_ack.directory_id[0];
// c1 l2 instruction cache tlb
logic c1_l2ittodr0_snoop_ack_valid;
assign c1_l2ittodr0_snoop_ack_valid = c1_l2ittodr_snoop_ack_valid & ~c1_l2ittodr_snoop_ack.directory_id[0];
logic c1_l2ittodr1_snoop_ack_valid;
assign c1_l2ittodr1_snoop_ack_valid = c1_l2ittodr_snoop_ack_valid & c1_l2ittodr_snoop_ack.directory_id[0];
// c1 l2 data cache
logic c1_l2d_0todr0_snoop_ack_valid;
assign c1_l2d_0todr0_snoop_ack_valid = c1_l2d_0todr_snoop_ack_valid & ~c1_l2d_0todr_snoop_ack.directory_id[0];
logic c1_l2d_0todr1_snoop_ack_valid;
assign c1_l2d_0todr1_snoop_ack_valid = c1_l2d_0todr_snoop_ack_valid & c1_l2d_0todr_snoop_ack.directory_id[0];
// c1 l2 data tlb
logic c1_l2dt_0todr0_snoop_ack_valid;
assign c1_l2dt_0todr0_snoop_ack_valid = c1_l2dt_0todr_snoop_ack_valid & ~c1_l2dt_0todr_snoop_ack.directory_id[0];
logic c1_l2dt_0todr1_snoop_ack_valid;
assign c1_l2dt_0todr1_snoop_ack_valid = c1_l2dt_0todr_snoop_ack_valid & c1_l2dt_0todr_snoop_ack.directory_id[0];
logic c0_l2todr0_snoop_ack_valid;
logic c0_l2todr1_snoop_ack_valid;
logic c1_l2todr0_snoop_ack_valid;
logic c1_l2todr1_snoop_ack_valid;
logic l2todr0_snoop_ack_inp_valid;
logic l2todr1_snoop_ack_inp_valid;
assign c0_l2todr0_snoop_ack_valid = c0_l2itodr0_snoop_ack_valid|c0_l2ittodr0_snoop_ack_valid|c0_l2d_0todr0_snoop_ack_valid|c0_l2dt_0todr0_snoop_ack_valid;
assign c0_l2todr1_snoop_ack_valid = c0_l2itodr1_snoop_ack_valid|c0_l2ittodr1_snoop_ack_valid|c0_l2d_0todr1_snoop_ack_valid|c0_l2dt_0todr1_snoop_ack_valid;
assign c1_l2todr0_snoop_ack_valid = c1_l2itodr0_snoop_ack_valid|c1_l2ittodr0_snoop_ack_valid|c1_l2d_0todr0_snoop_ack_valid|c1_l2dt_0todr0_snoop_ack_valid;
assign c1_l2todr1_snoop_ack_valid = c1_l2itodr1_snoop_ack_valid|c1_l2ittodr1_snoop_ack_valid|c1_l2d_0todr1_snoop_ack_valid|c1_l2dt_0todr1_snoop_ack_valid;
assign l2todr0_snoop_ack_inp_valid = c0_l2todr0_snoop_ack_valid | c1_l2todr0_snoop_ack_valid;
assign l2todr1_snoop_ack_inp_valid = c0_l2todr1_snoop_ack_valid | c1_l2todr1_snoop_ack_valid;
logic c0_l2itodr0_snoop_ack_retry;
logic c0_l2ittodr0_snoop_ack_retry;
logic c0_l2d_0todr0_snoop_ack_retry;
logic c0_l2dt_0todr0_snoop_ack_retry;
logic c1_l2itodr0_snoop_ack_retry;
logic c1_l2ittodr0_snoop_ack_retry;
logic c1_l2d_0todr0_snoop_ack_retry;
logic c1_l2dt_0todr0_snoop_ack_retry;
logic c0_l2itodr1_snoop_ack_retry;
logic c0_l2ittodr1_snoop_ack_retry;
logic c0_l2d_0todr1_snoop_ack_retry;
logic c0_l2dt_0todr1_snoop_ack_retry;
logic c1_l2itodr1_snoop_ack_retry;
logic c1_l2ittodr1_snoop_ack_retry;
logic c1_l2d_0todr1_snoop_ack_retry;
logic c1_l2dt_0todr1_snoop_ack_retry;
logic l2todr_snoop_ack_inp0_retry;
logic l2todr_snoop_ack_inp1_retry;
//***********************snoop_acks**********************
// For every snoop_ack if the snoop_ack is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 snoop_acks
always_comb begin
c0_l2itodr0_snoop_ack_retry = 1;
c0_l2ittodr0_snoop_ack_retry = 1;
c0_l2d_0todr0_snoop_ack_retry = 1;
c0_l2dt_0todr0_snoop_ack_retry = 1;
c1_l2itodr0_snoop_ack_retry = 1;
c1_l2ittodr0_snoop_ack_retry = 1;
c1_l2d_0todr0_snoop_ack_retry = 1;
c1_l2dt_0todr0_snoop_ack_retry = 1;
if (c0_l2itodr0_snoop_ack_valid) begin
l2todr0_snoop_ack_next = c0_l2itodr_snoop_ack;
c0_l2itodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
end else if (c0_l2ittodr0_snoop_ack_valid) begin
c0_l2ittodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2ittodr_snoop_ack;
end else if (c0_l2d_0todr0_snoop_ack_valid) begin
c0_l2d_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2d_0todr_snoop_ack;
end else if (c0_l2dt_0todr0_snoop_ack_valid) begin
c0_l2dt_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2dt_0todr_snoop_ack;
end else if (c1_l2itodr0_snoop_ack_valid) begin
l2todr0_snoop_ack_next = c1_l2itodr_snoop_ack;
c1_l2itodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
end else if (c1_l2ittodr0_snoop_ack_valid) begin
c1_l2ittodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2ittodr_snoop_ack;
end else if (c1_l2d_0todr0_snoop_ack_valid) begin
c1_l2d_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2d_0todr_snoop_ack;
end else if (c1_l2dt_0todr0_snoop_ack_valid) begin
c1_l2dt_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2dt_0todr_snoop_ack;
end
end
// Handle DIR 1 snoop_acks
always_comb begin
c0_l2itodr1_snoop_ack_retry = 1;
c0_l2ittodr1_snoop_ack_retry = 1;
c0_l2d_0todr1_snoop_ack_retry = 1;
c0_l2dt_0todr1_snoop_ack_retry = 1;
c1_l2itodr1_snoop_ack_retry = 1;
c1_l2ittodr1_snoop_ack_retry = 1;
c1_l2d_0todr1_snoop_ack_retry = 1;
c1_l2dt_0todr1_snoop_ack_retry = 1;
if (c0_l2itodr1_snoop_ack_valid) begin
c0_l2itodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c0_l2itodr_snoop_ack;
end else if (c0_l2ittodr1_snoop_ack_valid) begin
c0_l2ittodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c0_l2ittodr_snoop_ack;
end else if (c0_l2d_0todr1_snoop_ack_valid) begin
c0_l2d_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c0_l2d_0todr_snoop_ack;
end else if (c0_l2dt_0todr1_snoop_ack_valid) begin
c0_l2dt_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2dt_0todr_snoop_ack;
end else if (c1_l2itodr1_snoop_ack_valid) begin
c1_l2itodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c1_l2itodr_snoop_ack;
end else if (c1_l2ittodr1_snoop_ack_valid) begin
c1_l2ittodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c1_l2ittodr_snoop_ack;
end else if (c1_l2d_0todr1_snoop_ack_valid) begin
c1_l2d_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c1_l2d_0todr_snoop_ack;
end else if (c1_l2d_0todr1_snoop_ack_valid) begin
c1_l2dt_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2dt_0todr_snoop_ack;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid snoop_ack to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_snoop_ack_retry = c0_l2itodr0_snoop_ack_retry & c0_l2itodr1_snoop_ack_retry;
c0_l2ittodr_snoop_ack_retry = c0_l2ittodr0_snoop_ack_retry & c0_l2ittodr1_snoop_ack_retry;
c0_l2d_0todr_snoop_ack_retry = c0_l2d_0todr0_snoop_ack_retry & c0_l2d_0todr1_snoop_ack_retry;
c0_l2dt_0todr_snoop_ack_retry = c0_l2dt_0todr0_snoop_ack_retry & c0_l2dt_0todr1_snoop_ack_retry;
c1_l2itodr_snoop_ack_retry = c1_l2itodr0_snoop_ack_retry & c1_l2itodr1_snoop_ack_retry;
c1_l2ittodr_snoop_ack_retry = c1_l2ittodr0_snoop_ack_retry & c1_l2ittodr1_snoop_ack_retry;
c1_l2d_0todr_snoop_ack_retry = c1_l2d_0todr0_snoop_ack_retry & c1_l2d_0todr1_snoop_ack_retry;
c1_l2dt_0todr_snoop_ack_retry = c1_l2dt_0todr0_snoop_ack_retry & c1_l2dt_0todr1_snoop_ack_retry;
end
fflop #(.Size($bits(I_drsnoop_ack_type))) snoop_ack_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_snoop_ack_next),
.dinValid (l2todr0_snoop_ack_inp_valid),
.dinRetry (l2todr_snoop_ack_inp0_retry),
.q (l2todr0_snoop_ack),
.qValid (l2todr0_snoop_ack_valid),
.qRetry (l2todr0_snoop_ack_retry)
);
fflop #(.Size($bits(I_drsnoop_ack_type))) snoop_ack_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_snoop_ack_next),
.dinValid (l2todr1_snoop_ack_inp_valid),
.dinRetry (l2todr_snoop_ack_inp1_retry),
.q (l2todr1_snoop_ack),
.qValid (l2todr1_snoop_ack_valid),
.qRetry (l2todr1_snoop_ack_retry)
);
I_drtol2_snack_type c0_drtol2i_snack_next;
I_drtol2_snack_type c0_drtol2it_snack_next;
I_drtol2_snack_type c0_drtol2d_0_snack_next;
I_drtol2_snack_type c0_drtol2dt_0_snack_next;
I_drtol2_snack_type c1_drtol2i_snack_next;
I_drtol2_snack_type c1_drtol2it_snack_next;
I_drtol2_snack_type c1_drtol2d_0_snack_next;
I_drtol2_snack_type c1_drtol2dt_0_snack_next;
logic c0_drtol2i_snack_valid_next;
logic c0_drtol2it_snack_valid_next;
logic c0_drtol2d_0_snack_valid_next;
logic c0_drtol2dt_0_snack_valid_next;
logic c1_drtol2i_snack_valid_next;
logic c1_drtol2it_snack_valid_next;
logic c1_drtol2d_0_snack_valid_next;
logic c1_drtol2dt_0_snack_valid_next;
always_comb begin
// start retry signals high so they must be set low to pass through
dr0tol2_snack_retry = 1;
dr1tol2_snack_retry = 1;
// Set all valids low so they have to be set high to pass through
c0_drtol2i_snack_valid_next = 1'b0;
c0_drtol2it_snack_valid_next = 1'b0;
c0_drtol2d_0_snack_valid_next = 1'b0;
c0_drtol2dt_0_snack_valid_next = 1'b0;
c1_drtol2i_snack_valid_next = 1'b0;
c1_drtol2it_snack_valid_next = 1'b0;
c1_drtol2d_0_snack_valid_next = 1'b0;
c1_drtol2dt_0_snack_valid_next = 1'b0;
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b000)) begin
c0_drtol2i_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2i_snack_retry;
c0_drtol2i_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b000)) begin
c0_drtol2i_snack_next = dr1tol2_snack;
dr0tol2_snack_retry = c0_drtol2i_snack_retry;
c0_drtol2i_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b001)) begin
c0_drtol2it_snack_valid_next = 1'b1;
c0_drtol2it_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2it_snack_retry;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b001)) begin
c0_drtol2it_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c0_drtol2it_snack_retry;
c0_drtol2it_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2d_0_snack_retry;
c0_drtol2d_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c0_drtol2d_0_snack_retry;
c0_drtol2d_0_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2dt_0_snack_retry;
c0_drtol2dt_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c0_drtol2dt_0_snack_retry;
c0_drtol2dt_0_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b100)) begin
c1_drtol2i_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2i_snack_retry;
c1_drtol2i_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b100)) begin
c1_drtol2i_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2i_snack_retry;
c1_drtol2i_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b101)) begin
c1_drtol2it_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2it_snack_retry;
c1_drtol2it_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b101)) begin
c1_drtol2it_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2it_snack_retry;
c1_drtol2it_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2d_0_snack_retry;
c1_drtol2d_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2d_0_snack_retry;
c1_drtol2d_0_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2dt_0_snack_retry;
c1_drtol2dt_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2dt_0_snack_retry;
c1_drtol2dt_0_snack_valid_next = 1'b1;
end
end
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2i_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2i_snack_next),
.dinValid (c0_drtol2i_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2i_snack),
.qValid (c0_drtol2i_snack_valid),
.qRetry (c0_drtol2i_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2it_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2it_snack_next),
.dinValid (c0_drtol2it_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2it_snack),
.qValid (c0_drtol2it_snack_valid),
.qRetry (c0_drtol2it_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2d_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2d_0_snack_next),
.dinValid (c0_drtol2d_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2d_0_snack),
.qValid (c0_drtol2d_0_snack_valid),
.qRetry (c0_drtol2d_0_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2dt_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2dt_0_snack_next),
.dinValid (c0_drtol2dt_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2dt_0_snack),
.qValid (c0_drtol2dt_0_snack_valid),
.qRetry (c0_drtol2dt_0_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2i_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2i_snack_next),
.dinValid (c1_drtol2i_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2i_snack),
.qValid (c1_drtol2i_snack_valid),
.qRetry (c1_drtol2i_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2it_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2it_snack_next),
.dinValid (c1_drtol2it_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2it_snack),
.qValid (c1_drtol2it_snack_valid),
.qRetry (c1_drtol2it_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2d_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2d_0_snack_next),
.dinValid (c1_drtol2d_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2d_0_snack),
.qValid (c1_drtol2d_0_snack_valid),
.qRetry (c1_drtol2d_0_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2dt_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2dt_0_snack_next),
.dinValid (c1_drtol2dt_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2dt_0_snack),
.qValid (c1_drtol2dt_0_snack_valid),
.qRetry (c1_drtol2dt_0_snack_retry)
);
I_drtol2_dack_type c0_drtol2i_dack_next;
I_drtol2_dack_type c0_drtol2it_dack_next;
I_drtol2_dack_type c0_drtol2d_0_dack_next;
I_drtol2_dack_type c0_drtol2dt_0_dack_next;
I_drtol2_dack_type c1_drtol2i_dack_next;
I_drtol2_dack_type c1_drtol2it_dack_next;
I_drtol2_dack_type c1_drtol2d_0_dack_next;
I_drtol2_dack_type c1_drtol2dt_0_dack_next;
logic c0_drtol2i_dack_valid_next;
logic c0_drtol2it_dack_valid_next;
logic c0_drtol2d_0_dack_valid_next;
logic c0_drtol2dt_0_dack_valid_next;
logic c1_drtol2i_dack_valid_next;
logic c1_drtol2it_dack_valid_next;
logic c1_drtol2d_0_dack_valid_next;
logic c1_drtol2dt_0_dack_valid_next;
always_comb begin
// start retry signals high so they must be set low to pass through
dr0tol2_dack_retry = 1;
dr1tol2_dack_retry = 1;
// stary valid signals low so they must be set high to pass through
c0_drtol2i_dack_valid_next = 1'b0;
c0_drtol2it_dack_valid_next = 1'b0;
c0_drtol2d_0_dack_valid_next = 1'b0;
c0_drtol2dt_0_dack_valid_next = 1'b0;
c1_drtol2i_dack_valid_next = 1'b0;
c1_drtol2it_dack_valid_next = 1'b0;
c1_drtol2d_0_dack_valid_next = 1'b0;
c1_drtol2dt_0_dack_valid_next = 1'b0;
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b000)) begin
c0_drtol2i_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2i_dack_retry;
c0_drtol2i_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b000)) begin
c0_drtol2i_dack_next = dr1tol2_dack;
dr0tol2_dack_retry = c0_drtol2i_dack_retry;
c0_drtol2i_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b001)) begin
c0_drtol2it_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2it_dack_retry;
c0_drtol2it_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b001)) begin
c0_drtol2it_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c0_drtol2it_dack_retry;
c0_drtol2it_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2d_0_dack_retry;
c0_drtol2d_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c0_drtol2d_0_dack_retry;
c0_drtol2d_0_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2dt_0_dack_retry;
c0_drtol2dt_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c0_drtol2dt_0_dack_retry;
c0_drtol2dt_0_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b100)) begin
c1_drtol2i_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2i_dack_retry;
c1_drtol2i_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b100)) begin
c1_drtol2i_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2i_dack_retry;
c1_drtol2i_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b101)) begin
c1_drtol2it_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2it_dack_retry;
c1_drtol2it_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b101)) begin
c1_drtol2it_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2it_dack_retry;
c1_drtol2it_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2d_0_dack_retry;
c1_drtol2d_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2d_0_dack_retry;
c1_drtol2d_0_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2dt_0_dack_retry;
c1_drtol2dt_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2dt_0_dack_retry;
c1_drtol2dt_0_dack_valid_next = 1'b1;
end
end
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2i_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2i_dack_next),
.dinValid (c0_drtol2i_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2i_dack),
.qValid (c0_drtol2i_dack_valid),
.qRetry (c0_drtol2i_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2it_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2it_dack_next),
.dinValid (c0_drtol2it_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2it_dack),
.qValid (c0_drtol2it_dack_valid),
.qRetry (c0_drtol2it_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2d_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2d_0_dack_next),
.dinValid (c0_drtol2d_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2d_0_dack),
.qValid (c0_drtol2d_0_dack_valid),
.qRetry (c0_drtol2d_0_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2dt_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2dt_0_dack_next),
.dinValid (c0_drtol2dt_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2dt_0_dack),
.qValid (c0_drtol2dt_0_dack_valid),
.qRetry (c0_drtol2dt_0_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2i_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2i_dack_next),
.dinValid (c1_drtol2i_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2i_dack),
.qValid (c1_drtol2i_dack_valid),
.qRetry (c1_drtol2i_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2it_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2it_dack_next),
.dinValid (c1_drtol2it_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2it_dack),
.qValid (c1_drtol2it_dack_valid),
.qRetry (c1_drtol2it_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2d_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2d_0_dack_next),
.dinValid (c1_drtol2d_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2d_0_dack),
.qValid (c1_drtol2d_0_dack_valid),
.qRetry (c1_drtol2d_0_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2dt_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2dt_0_dack_next),
.dinValid (c1_drtol2dt_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2dt_0_dack),
.qValid (c1_drtol2dt_0_dack_valid),
.qRetry (c1_drtol2dt_0_dack_retry)
);
endmodule |
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
reg clk;
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
`ifdef SINGLE
parameter SW = 24;
`endif
`ifdef DOUBLE
parameter SW = 54;// */
`endif
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
wire [2*SW-1:0] FKOARES;
reg clk;
reg rst;
reg load_b_i;
`ifdef SINGLE
Sgf_Multiplication_SW24 #(.SW(SW))
`endif
`ifdef DOUBLE
Sgf_Multiplication_SW54 #(.SW(SW))
`endif
inst_Sgf_Multiplication (.clk(clk),.rst(rst),.load_b_i(load_b_i),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(FKOARES));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b, FKOARES, a*b);
end
initial begin
b = 1;
rst = 1;
a = 1;
load_b_i = 0;
#30;
rst = 0;
#15;
load_b_i = 1;
#100;
b = 2;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Mahdi Enan
//
// Create Date: 10:06:06 01/18/2017
// Design Name: retnuoCl
// Module Name: tb_retnuoCl.v
// Project Name: spongent
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: retnuoCl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_retnuoCl;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
retnuoCl uut (
.lfsr(lfsr),
.out(out)
);
initial begin
// Initialize Inputs
lfsr = 16'b0000000000000000;
$display("set lsfr to : %d", lfsr);
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, out=%b, (hex): %h", lfsr, out, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_from_half(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Convert a floating-point number from half-precision to single-precision. No rounding is required.
// Half format is [sign, 5-bit exponent, 10-bit mantissa]
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input [15:0] dataa;
output [31:0] result;
input valid_in, stall_in, enable;
output valid_out, stall_out;
wire c1_enable;
reg c1_valid;
wire c1_stall;
reg [7:0] c1_exponent;
reg [22:0] c1_mantissa;
reg c1_sign;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
wire [3:0] count;
wire [9:0] shifted_mantissa;
half_type_clz clz(.mantissa(dataa[9:0]), .count(count));
assign shifted_mantissa = dataa[9:0] << count;
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
c1_valid <= 1'b0;
c1_exponent <= 8'dx;
c1_mantissa <= 23'dx;
c1_sign <= 1'bx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= dataa[15];
if (&dataa[14:10])
begin
c1_exponent <= 8'hff;
c1_mantissa <= {dataa[9:0], 13'd0};
end
else if (~(|dataa[14:10]))
begin
// in a case of exponent being 0, we only set exponent to zero if the mantissa is all zeros.
// Otherwise, we must shift the mantissa left and adjust the exponent accordingly.
if (~|dataa[9:0])
begin
c1_exponent <= 8'd0;
c1_mantissa <= 23'd0;
end
else
begin
c1_exponent <= 8'd112 - {1'b0, count};
c1_mantissa <= {shifted_mantissa[8:0], 14'd0};
end
end
else
begin
c1_exponent <= 8'd112 + {1'b0, dataa[14:10]};
c1_mantissa <= {dataa[9:0], 13'd0};
end
end
end
assign result = {c1_sign, c1_exponent, c1_mantissa};
assign valid_out = c1_valid;
assign c1_stall = stall_in;
endmodule
module half_type_clz(mantissa, count);
input [9:0] mantissa;
output [3:0] count;
assign count[3] = ~|mantissa[9:2];
assign count[2] = |mantissa[9:2] & ~|mantissa[9:6];
assign count[1] = count[3] & ~|mantissa[1:0] | ~count[3] & (~count[2] & ~|mantissa[9:8] | count[2] & ~|mantissa[5:4]);
assign count[0] = (mantissa[9:8] == 2'b01) |
(mantissa[9:6] == 4'b0001) |
(mantissa[9:4] == 6'b000001) |
(mantissa[9:2] == 8'b00000001) |
(mantissa == 10'b0000000001);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V |
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in1.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test multidimensional arrays.
module vhdl_multidim_array_test;
vhdl_multidim_array dut();
initial begin
int i, j;
for(i = 0; i <= 1; i = i + 1) begin
for(j = dut.array_size - 1; j >= 0; j = j - 1) begin
$display("%d", dut.arr[i][j]);
//$display("%d, %d = %d", i, j, arr[i][j]);
//if(dut.arr[i][j] !== i * 10 + j) begin
//$display("FAILED: arr[%d][%d] == %d, instead of %d", i, j, dut.arr[i][j], i * 10 + j);
//$finish();
//end
end
end
$display("PASSED");
end
endmodule
|
`timescale 1 ns/100 ps
// Version: 9.0 SP1 9.0.2.9
module dmem_128B(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input WEN, REN;
input [6:0] WADDR, RADDR;
input RWCLK;
input RESET;
wire VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]),
.ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]),
.ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]),
.ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND),
.ADDRB7(GND), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]),
.ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]),
.ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(
WD[7]), .DINA6(WD[6]), .DINA5(WD[5]), .DINA4(WD[4]),
.DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]), .DINA0(WD[0])
, .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(GND),
.DINB0(GND), .WIDTHA0(VCC), .WIDTHA1(VCC), .WIDTHB0(VCC),
.WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND),
.WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(
VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(),
.DOUTA7(), .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(),
.DOUTA2(), .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(RD[7])
, .DOUTB6(RD[6]), .DOUTB5(RD[5]), .DOUTB4(RD[4]), .DOUTB3(
RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(RD[0]));
endmodule
|
`timescale 1ns/1ps
module localbus_manage(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
cs_n,
rd_wr,
data,
ale,
ack_n,
data_out,
set_ip_src_valid,
set_ip_src,
mode,
xtr_id,
set_port
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
output wire cs_n;
output wire rd_wr;
output wire [31:0] data;
output reg ale;
input ack_n;
input [31:0] data_out;
output reg set_ip_src_valid;
output reg [130:0] set_ip_src;
output reg mode;
output reg [7:0] xtr_id;
output reg [7:0] set_port;
//----------reg--------------//
reg [31:0] localbus_addr;
reg [127:0] ip_src_1,ip_src_2,ip_src_3,ip_src_4,ip_src_5,ip_src_6,ip_src_7,ip_src_8;
reg [127:0] read_ip_src;
//--state--//
reg [3:0] localbus_state;
parameter idle_s = 4'd0,
wait_set_s = 4'd1,
wait_read_s = 4'd2,
wait_ack_s = 4'd3,
wait_back_s = 4'd4;
assign rd_wr = localbus_rd_wr;
assign data = localbus_data;
assign cs_n = localbus_cs_n;
//----------------localbus_state-------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_ip_src_valid <= 1'b0;
set_ip_src <= 130'b0;
mode <= 1'b1;
xtr_id <= 8'h12;
set_port <= 8'h80;
ale <= 1'b0;
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
localbus_addr <= 32'b0;
read_ip_src <= 128'b0;
// ip_src_1 <= 128'b0;
ip_src_2 <= 128'b0;ip_src_3 <= 128'b0;ip_src_4 <= 128'b0;
ip_src_5 <= 128'b0;ip_src_6 <= 128'b0;ip_src_7 <= 128'b0;ip_src_8 <= 128'b0;
localbus_state <= idle_s;
end
else
begin
case(localbus_state)
idle_s:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_data[23] == 1'b1)
begin
ale <= 1'b0;
if(localbus_rd_wr == 1'b1) localbus_state <= wait_read_s;
else localbus_state <= wait_set_s;
case(localbus_data[6:4])
3'd0: read_ip_src <= ip_src_1;
3'd1: read_ip_src <= ip_src_2;
3'd2: read_ip_src <= ip_src_3;
3'd3: read_ip_src <= ip_src_4;
3'd4: read_ip_src <= ip_src_5;
3'd5: read_ip_src <= ip_src_6;
3'd6: read_ip_src <= ip_src_7;
3'd7: read_ip_src <= ip_src_8;
endcase
end
else
begin
ale <= 1'b1;
localbus_state <= wait_ack_s;
end
end
else
begin
ale <= 1'b0;
localbus_state <= idle_s;
end
end
wait_set_s:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[13:12])
2'd0: mode <= localbus_data[0];
2'd1:
begin
case(localbus_addr[1:0])
2'd0: set_ip_src[130:96] <= {localbus_addr[6:4],localbus_data};
2'd1: set_ip_src[95:64] <= localbus_data;
2'd2: set_ip_src[63:32] <= localbus_data;
2'd3:
begin
set_ip_src_valid <= 1'b1;
set_ip_src[31:0] <= localbus_data;
end
endcase
end
2'd2: xtr_id <= localbus_data[7:0];
2'd3: set_port <= localbus_data[7:0];
endcase
localbus_ack_n <= 1'b0;
localbus_state <= wait_back_s;
end
else localbus_state <= wait_set_s;
end
wait_read_s:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[13:12])
2'd0: localbus_data_out <= {31'b0,mode};
2'd1:
begin
case(localbus_addr[1:0])
2'd0: localbus_data_out <= read_ip_src[127:96];
2'd1: localbus_data_out <= read_ip_src[95:64];
2'd2: localbus_data_out <= read_ip_src[63:32];
2'd3: localbus_data_out <= read_ip_src[31:0];
endcase
end
2'd2: localbus_data_out <= {24'b0,xtr_id};
2'd3: localbus_data_out <= {24'b0,set_port};
endcase
localbus_ack_n <= 1'b0;
localbus_state <= wait_back_s;
end
else localbus_state <= wait_read_s;
end
wait_ack_s:
begin
ale <= 1'b0;
if(ack_n == 1'b0)
begin
localbus_data_out <= data_out;
localbus_ack_n <= 1'b0;
localbus_state <= wait_back_s;
end
else localbus_state <= wait_ack_s;
end
wait_back_s:
begin
if(set_ip_src_valid == 1'b1)
begin
case(set_ip_src[130:128])
3'd0: ip_src_1 <= set_ip_src[127:0];
3'd1: ip_src_2 <= set_ip_src[127:0];
3'd2: ip_src_3 <= set_ip_src[127:0];
3'd3: ip_src_4 <= set_ip_src[127:0];
3'd4: ip_src_5 <= set_ip_src[127:0];
3'd5: ip_src_6 <= set_ip_src[127:0];
3'd6: ip_src_7 <= set_ip_src[127:0];
3'd7: ip_src_8 <= set_ip_src[127:0];
endcase
end
set_ip_src_valid <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
localbus_state <= idle_s;
end
else localbus_state <= wait_back_s;
end
default:
begin
localbus_state <= idle_s;
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_div ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// division entity for the division unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, [email protected] ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module fpu_div
(
clk,
rst,
dvdnd_i,
dvsor_i,
sign_dvd_i,
sign_div_i,
start_i,
ready_o,
qutnt_o,
rmndr_o,
sign_o,
div_zero_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk;
input rst;
input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i;
input [FRAC_WIDTH+3:0] dvsor_i;
input sign_dvd_i;
input sign_div_i;
input start_i;
output ready_o;
output [FRAC_WIDTH+3:0] qutnt_o;
output [FRAC_WIDTH+3:0] rmndr_o;
output sign_o;
output div_zero_o;
parameter t_state_waiting = 1'b0,
t_state_busy = 1'b1;
reg [FRAC_WIDTH+3:0] s_qutnt_o;
reg [FRAC_WIDTH+3:0] s_rmndr_o;
reg [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_i;
reg [FRAC_WIDTH+3:0] s_dvsor_i;
reg s_sign_dvd_i, s_sign_div_i;
wire s_sign_o;
wire s_div_zero_o;
reg s_start_i;
reg s_ready_o;
reg s_state;
reg [4:0] s_count;
reg [FRAC_WIDTH+3:0] s_dvd;
// Input Register
always @(posedge clk or posedge rst)
if (rst)
begin
s_dvdnd_i <= 'd0;
s_dvsor_i <= 'd0;
s_sign_dvd_i<= 1'b0;
s_sign_div_i<= 1'b0;
s_start_i <= 1'b0;
end
else
begin
s_dvdnd_i <= dvdnd_i;
s_dvsor_i <= dvsor_i;
s_sign_dvd_i<= sign_dvd_i;
s_sign_div_i<= sign_div_i;
s_start_i <= start_i;
end
assign qutnt_o = s_qutnt_o;
assign rmndr_o = s_rmndr_o;
assign sign_o = s_sign_o;
assign ready_o = s_ready_o;
assign div_zero_o = s_div_zero_o;
assign s_sign_o = sign_dvd_i ^ sign_div_i;
assign s_div_zero_o = !(|s_dvsor_i) & (|s_dvdnd_i);
always @(posedge clk or posedge rst)
if (rst)
begin
s_state <= t_state_waiting;
s_count <= 0;
s_ready_o <= 0;
end
else
if (s_start_i)
begin
s_state <= t_state_busy;
s_count <= 26;
end
else if (!(|s_count) & s_state==t_state_busy)
begin
s_state <= t_state_waiting;
s_ready_o <= 1;
s_count <=26;
end
else if (s_state==t_state_busy)
s_count <= s_count - 1;
else
begin
s_state <= t_state_waiting;
s_ready_o <= 0;
end
wire [26:0] v_div;
assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd;
wire [26:0] v_div_minus_s_dvsor_i;
assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
s_qutnt_o <= 0;
s_rmndr_o <= 0;
end
else
if (s_start_i)
begin
s_qutnt_o <= 0;
s_rmndr_o <= 0;
end
else if (s_state==t_state_busy)
begin
if (v_div < s_dvsor_i)
begin
s_qutnt_o[s_count] <= 1'b0;
s_dvd <= {v_div[25:0],1'b0};
end
else
begin
s_qutnt_o[s_count] <= 1'b1;
s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0};
end
s_rmndr_o <= v_div;
end // if (s_state==t_state_busy)
end // always @ (posedge clk or posedge rst)
endmodule // fpu_div
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_m00_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [5 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [5 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [5 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [5 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_9_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(6),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H1),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_1_V
`define SKY130_FD_SC_LP__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_1_V
|
// Copyright (c) 2000 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This module implements what essentially amounts to an array of DFF
* devices with output enable. This test checks the operation of the
* bufif0 and bufif1 devices.
*/
module grayGap (ad, clk, read, write);
output [31:0] ad;
input clk, read, write;
reg [15:0] regff;
bufif0 ad_drv [31:0] (ad, {16'b0, regff}, read);
always @(posedge clk)
if (write) regff = ad[15:0];
endmodule
module main;
wire [31:0] ad;
reg clk, read, write;
reg [31:0] ad_val;
reg ad_en;
bufif1 ad_drv[31:0] (ad, ad_val, ad_en);
grayGap test (ad, clk, read, write);
always #10 clk = ~clk;
initial begin
clk = 1;
read = 1;
write = 0;
$monitor($time, "ad=%b", ad);
// Set up to write a value into the grayGap register.
@(negedge clk)
ad_val = 32'haaaa_aaaa;
read = 1;
write = 1;
ad_en = 1;
// The posedge has passed, now set up to read that value
// out. Turn all the drivers off for a moment, to see that the
// line becomes tri-state...
@(negedge clk)
ad_en = 0;
write = 0;
// Now read the value.
#1 read = 0;
#1 $display("Wrote %h, got %h", ad_val, ad);
if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin
$display("FAILED -- ad is %b", ad);
$finish;
end
#2 read = 1;
$display("PASSED");
$finish;
end
endmodule // main
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`timescale 1ns/1ns
module unitTestNext();
reg clk;
wire rst;
reg start;
reg test_expr;
wire inv;
wire assert;
initial begin
clk = 1'b0;
start = 1'b0;
test_expr = 1'b0;
end
assign rst = 1'b0;
assign inv = 1'b0;
always begin
#10 clk = ~clk;
#10 clk = ~clk;
// Make sure missing start doesn't fire
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test to make sure test can fire early and stay late as long as it is valid at num cks
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start =1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test normal operation
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test for assertion violations
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test for overlapping starts
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
ovl_next_wrapped onw(
.clk(clk),
.rst(rst),
.num_cks(3'd3),
.start_event(start),
.test_expr(test_expr),
.prevConfigInvalid(inv),
.out(assert)
);
endmodule |
Require Import String List.
Require Import CoqCompile.CpsK.
Require Import CoqCompile.CpsKUtil.
Require Import ExtLib.ExtLib.
Require Import ExtLib.Structures.Monads.
Require Import ExtLib.Structures.Sets.
Require Import ExtLib.Structures.Maps.
Require Import ExtLib.Structures.Reducible.
Require Import ExtLib.Structures.Monoid.
Require Import ExtLib.Data.Set.ListSet.
Require Import ExtLib.Data.Map.FMapAList.
Set Implicit Arguments.
Set Strict Implicit.
Section map_monoid.
Variable M : Type -> Type.
Variable K : Type.
Variable E : Type.
Variable Monoid_e : Monoid E.
Context {DMap_M : DMap K M}.
Context {Foldable_M : Foldable (M E) (K * E)}.
Definition Monoid_map : Monoid (M E) :=
{| monoid_unit := Maps.empty
; monoid_plus := Maps.combine (K := K) (fun _ => monoid_plus Monoid_e)
|}.
End map_monoid.
Module Contify.
Import CpsK.CPSK.
(** A function [f] can be made into a continuation [k] if all execution
** paths in [f] return to the same continuation.
**
** Further: The function must be in the scope of the continuation (can I move it?).
** In particular, this means that I can not contify a function inside a function
** if I know that it refers to the outer continuation.
** - My analysis should never say that I can do this because we always do return
** to a passed-in continuation
**)
Definition map_monoid : Monoid (alist var (lset (@eq (list cont)))) :=
@Monoid_map (alist var) _ _ (@Monoid_set_union _ _ _ _) _ _.
Definition set_monoid := @Monoid_set_union (lset (@eq var)) _ _ _.
Section monadic.
Variable m : Type -> Type.
Context {Monad_m : Monad m}.
Context {Contexts_m : MonadWriter map_monoid m}.
Context {Escapes_m : MonadWriter set_monoid m}.
Context {MonadExc_m : MonadExc string m}.
Context {ContSubst_m : MonadReader (alist cont cont) m}.
Definition call (f : op) (ks : list cont) : m unit :=
match f with
| Var_o f =>
tell (Maps.singleton f (Sets.singleton ks))
| _ => raise "Calling non-variable"%string
end.
Definition escapes (o : op) : m unit :=
match o with
| Var_o v => tell (Sets.singleton v)
| _ => ret tt
end.
Import MonadNotation.
Local Open Scope monad_scope.
Definition isSingleton {A} (ls : lset (@eq A)) : option A :=
match ls with
| x :: nil => Some x
| _ => None
end.
Fixpoint replaceCalls (f : op) (k : cont) (e : exp) : exp :=
match e with
| App_e f' ks xs => if eq_dec f f' then AppK_e k xs else e
| AppK_e _ _ => e
| Halt_e _ _ => e
| Let_e d e => Let_e d (replaceCalls f k e)
| LetK_e ks e =>
let ks' := map (fun kxse => let '(k,xs,e) := kxse in
(k, xs, replaceCalls f k e)) ks
in
LetK_e ks' (replaceCalls f k e)
| Letrec_e ds e =>
Letrec_e ds (replaceCalls f k e)
| Switch_e o arms def =>
let arms' := map (fun x => (fst x, replaceCalls f k (snd x))) arms in
let def' := map (replaceCalls f k) def in
Switch_e o arms' def'
end.
Definition replaceAllCalls (cs : list (op * cont)) (e : exp) : exp :=
List.fold_left (fun acc e_c => let '(f,c) := e_c in
replaceCalls f c acc) cs e.
Definition var_to_cont (v : var) : m cont :=
ret match v with
| Anon_v p => K "" p
| Named_v s None => K s 1
| Named_v s (Some p) => K s p
end.
Definition contify_k (k : cont) : m cont :=
k' <- asks (Maps.lookup k) ;;
match k' with
| None => ret k
| Some k => ret k
end.
Fixpoint withConts {T} (ks ks' : list cont) (c : m T) : m T :=
match ks , ks' with
| nil , nil => c
| k :: ks , k' :: ks' => local (Maps.add k k') (withConts ks ks' c)
| _ , _ => raise "inconsistent continutations "%string
end.
Definition mark_escapes (rec : bool) (d : decl) : m unit :=
let fvars : lset (@eq (var + cont)) := free_vars_decl rec d in
iterM (fun x => match x with
| inl v => escapes (Var_o v)
| _ => ret tt
end) fvars.
Definition remove_escapes {T} (ls : list var) (c : m T) : m T :=
censor (List.fold_left (fun acc v => Sets.remove v acc) ls) c.
Definition remove_calls {T} (ls : list var) (c : m T) : m T :=
censor (List.fold_left (fun acc v => Maps.remove v acc) ls) c.
Definition contifiable (f : var) (escapes : lset (@eq var)) (calls : alist var (lset (@eq (list cont)))) : option (list cont) :=
if Sets.contains f escapes then None
else match Maps.lookup f calls with
| None => Some nil (** it isn't used and it doesn't escape, it is dead code **)
| Some calls => isSingleton calls
end.
Fixpoint contify_exp (e : exp) : m exp.
refine (
match e with
| AppK_e k xs =>
iterM escapes xs ;;
k <- contify_k k ;;
ret (AppK_e k xs)
| App_e f ks xs =>
iterM escapes xs ;;
ks <- mapM contify_k ks ;;
call f ks ;;
ret (App_e f ks xs)
| Halt_e x w =>
ret (Halt_e x w)
| Switch_e o arms def =>
arms' <- mapM (fun pe => let '(p,e) := pe in
e' <- contify_exp e ;;
ret (p, e')) arms ;;
def' <- mapM contify_exp def ;;
ret (Switch_e o arms' def')
| Let_e (Fn_d f ks xs e_body) e =>
e'_conts <- remove_escapes xs (censor (Maps.remove f) (listen (MonadWriter := Escapes_m) (listen (MonadWriter := Contexts_m) (contify_exp e)))) ;;
let '(e',calls,escape_vars) := e'_conts in
let contifiable := contifiable f escape_vars calls in
match contifiable with
| None =>
e_body' <- contify_exp e_body ;;
mark_escapes false (Fn_d f ks xs e_body') ;;
ret (Let_e (Fn_d f ks xs e_body') e')
| Some args =>
(** We can contify f **)
k <- var_to_cont f ;;
let e' := replaceCalls (Var_o f) k e' in
e_body' <- withConts ks args (contify_exp e_body) ;;
ret (LetK_e ((k, xs, e_body') :: nil) e')
end
| Let_e d e =>
mark_escapes false d ;;
e' <- contify_exp e ;;
ret (Let_e d e')
| Letrec_e ds e =>
e' <- contify_exp e ;;
let names := List.map (fun d => match d with
| Fn_d v _ _ _
| Prim_d v _ _
| Op_d v _
| Bind_d v _ _ _ => v
end) ds in
(** Only consider for contification if it contains only functions **)
let has_non_func := List.fold_left (fun acc d => match d with
| Fn_d _ _ _ _ => acc
| _ => true
end) ds false in
if has_non_func then
(** mark the escapes and return **)
iterM (mark_escapes true) ds ;;
ret (Letrec_e ds e')
else
func_names <- mapM (fun d => match d with
| Fn_d v _ _ _ => ret v
| _ => raise "unreachable"%string
end) ds ;;
e'_conts <- remove_escapes func_names (remove_calls func_names (listen (listen (
ds <- mapM (fun d =>
match d with
| Fn_d v ks xs e =>
e' <- remove_escapes xs (contify_exp e) ;;
ret (Fn_d v ks xs e)
| _ => raise "unreachable"%string
end) ds ;;
e' <- contify_exp e ;;
ret (ds, e')
)))) ;;
let '((ds',e'),conts,escape_vars) := e'_conts in
(** we can contify if all ds are contifiable **)
(fix continue (ds : list decl) (ks' : list (var * list var * exp)) :=
match ds with
| nil =>
(** We can contify the let rec **)
ks'' <- mapM (fun f => let '(f,_,_) := f in
k' <- var_to_cont f ;;
ret (Var_o f, k')) ks' ;;
let _ : alist op cont := ks'' in
ks' <-
mapM (fun kxse => let '(f,xs,e) := kxse in
match Maps.lookup (Var_o f) ks'' with
| None => raise "unreachable"%string
| Some k => ret (k, xs, replaceAllCalls ks'' e)
end) ks' ;;
ret (LetK_e ks' (replaceAllCalls ks'' e'))
| Fn_d v ks xs e :: ds =>
match contifiable v conts escape_vars with
| None =>
(** can't contify **)
ret (Letrec_e ds' e')
| Some args =>
continue ds ((v, xs, e) :: ks')
end
| _ => raise "unreachable"%string
end) ds' nil
| LetK_e ks e =>
ks' <- mapM (fun kxse => let '(k,xs,e) := kxse in
e' <- contify_exp e ;;
ret (k, xs, e')) ks ;;
e' <- contify_exp e ;;
ret (LetK_e ks' e')
end).
Defined.
End monadic.
Require Import ExtLib.Data.Monads.WriterMonad.
Require Import ExtLib.Data.Monads.ReaderMonad.
Definition contify (e : exp) : string + exp :=
runReaderT (evalWriterT (Monoid_S := set_monoid) (evalWriterT (Monoid_S := map_monoid) (contify_exp e))) (Maps.empty : alist cont cont).
(*
Module TESTS.
Require Import ExtLib.Programming.Show.
Require Import CoqCompile.CpsKConvert.
Require Import CoqCompile.Parse.
(*
Fixpoint even (x : nat) :=
match x with
| 0 => true
| S n => odd n
end
with odd (x : nat) :=
match x with
| 0 => false
| S n => even n
end.
Definition main := even 1.
Extraction Language Scheme.
Recursive Extraction main.
*)
Definition even :=
"(define even (lambda (x)
(match x
((O) `(True))
((S n) (odd n)))))
(define odd (lambda (x)
(match x
((O) `(False))
((S n) (even n)))))
(define main (even `(S ,`(O))))"%string.
Definition simple :=
"(define f (lambda (x) `(S ,x)))
(define main (f `(S ,`(O))))"%string.
Definition simple_no :=
"(define f (lambda (x) `(S ,x)))
(define main `(Pair ,f ,(f `(S ,`(O)))))"%string.
Definition simple_lam :=
Eval vm_compute in
Parse.parse_topdecls simple.
Definition simple_cps : CPSK.exp :=
Eval vm_compute in
match simple_lam as parsed return match parsed with
| inl _ => unit
| inr _ => CPSK.exp
end
with
| inl _ => tt
| inr x =>
let res := CpsKConvert.CPS_pure x in res (*
match res with
| Letrec_e (d :: nil) e => Let_e d e
| _ => res
end *)
end.
Eval vm_compute in to_string simple_cps.
Eval vm_compute in to_string (contify simple_cps).
Definition simple_no_lam :=
Eval vm_compute in
Parse.parse_topdecls simple_no.
Definition simple_no_cps : CPSK.exp :=
Eval vm_compute in
match simple_no_lam as parsed return match parsed with
| inl _ => unit
| inr _ => CPSK.exp
end
with
| inl _ => tt
| inr x =>
let res := CpsKConvert.CPS_pure x in
match res with
| Letrec_e (d :: nil) e => Let_e d e
| _ => res
end
end.
Eval vm_compute in to_string simple_no_cps.
Eval vm_compute in to_string (contify simple_no_cps).
Definition even_lam :=
Eval vm_compute in
Parse.parse_topdecls even.
Definition even_cps : CPSK.exp :=
Eval vm_compute in
match even_lam as parsed return match parsed with
| inl _ => unit
| inr _ => CPSK.exp
end
with
| inl _ => tt
| inr x =>
let res := CpsKConvert.CPS_pure x in res (*
match res with
| Letrec_e (d :: nil) e => Let_e d e
| _ => res
end *)
end.
Eval vm_compute in to_string even_cps.
Eval vm_compute in to_string (contify even_cps).
End TESTS.
*)
End Contify.
|
module s344 (
B0,
A1,
B1,
A2,
A3,
blif_clk_net,
START,
B3,
A0,
blif_reset_net,
B2,
P7,
P5,
CNTVCON2,
P2,
CNTVCO2,
P1,
P0,
READY,
P6,
P3,
P4);
// Start PIs
input B0;
input A1;
input B1;
input A2;
input A3;
input blif_clk_net;
input START;
input B3;
input A0;
input blif_reset_net;
input B2;
// Start POs
output P7;
output P5;
output CNTVCON2;
output P2;
output CNTVCO2;
output P1;
output P0;
output READY;
output P6;
output P3;
output P4;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire P3;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire P5;
wire net_117;
wire net_12;
wire B1;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire P1;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire net_141;
wire net_160;
wire net_83;
wire net_115;
wire B3;
wire net_4;
wire net_95;
wire net_17;
wire net_78;
wire A1;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_16;
wire net_22;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire A3;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire B0;
wire net_34;
wire net_108;
wire net_150;
wire net_63;
wire P2;
wire net_152;
wire net_116;
wire net_30;
wire net_91;
wire net_106;
wire net_24;
wire net_55;
wire net_99;
wire net_46;
wire net_140;
wire net_118;
wire P7;
wire net_148;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire P4;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire P0;
wire net_138;
wire net_13;
wire P6;
wire net_94;
wire net_11;
wire CNTVCON2;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire CNTVCO2;
wire net_170;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire A2;
wire net_71;
wire net_153;
wire START;
wire net_156;
wire net_3;
wire net_84;
wire net_154;
wire net_112;
wire net_1;
wire net_92;
wire net_103;
wire net_139;
wire net_43;
wire net_10;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_79;
wire net_143;
wire net_97;
wire net_88;
wire net_145;
wire net_60;
wire net_81;
wire net_163;
wire net_58;
wire B2;
wire net_67;
wire net_82;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_8;
wire net_75;
wire net_86;
wire net_133;
wire READY;
wire A0;
wire net_125;
// Start cells
CLKBUF_X2 inst_145 ( .A(net_133), .Z(net_134) );
INV_X2 inst_103 ( .A(net_22), .ZN(net_17) );
DFFR_X1 inst_125 ( .D(net_97), .RN(net_96), .QN(net_2), .CK(net_138) );
CLKBUF_X2 inst_138 ( .A(net_126), .Z(net_127) );
CLKBUF_X2 inst_159 ( .A(net_138), .Z(net_148) );
NAND3_X2 inst_15 ( .ZN(net_84), .A3(net_78), .A1(net_59), .A2(P6) );
CLKBUF_X2 inst_134 ( .A(net_122), .Z(net_123) );
CLKBUF_X2 inst_179 ( .A(net_148), .Z(net_168) );
NAND3_X1 inst_24 ( .ZN(net_83), .A3(net_82), .A1(net_73), .A2(net_72) );
DFFR_X2 inst_114 ( .RN(net_96), .D(net_69), .QN(net_5), .CK(net_160) );
OR2_X4 inst_6 ( .ZN(net_41), .A2(READY), .A1(B1) );
CLKBUF_X2 inst_131 ( .A(net_119), .Z(net_120) );
INV_X4 inst_76 ( .ZN(net_19), .A(net_10) );
CLKBUF_X2 inst_180 ( .A(net_168), .Z(net_169) );
CLKBUF_X2 inst_160 ( .A(net_119), .Z(net_149) );
CLKBUF_X2 inst_150 ( .A(net_129), .Z(net_139) );
NAND2_X4 inst_33 ( .A2(net_104), .A1(net_103), .ZN(net_90) );
CLKBUF_X2 inst_172 ( .A(net_133), .Z(net_161) );
INV_X4 inst_83 ( .ZN(net_32), .A(net_11) );
NAND2_X2 inst_47 ( .ZN(net_50), .A1(net_34), .A2(net_31) );
NAND3_X2 inst_19 ( .ZN(net_117), .A2(net_91), .A3(net_87), .A1(net_84) );
DFFR_X2 inst_123 ( .RN(net_96), .D(net_93), .QN(net_1), .CK(net_128) );
DFFR_X2 inst_121 ( .RN(net_96), .D(net_79), .QN(net_13), .CK(net_134) );
OR3_X2 inst_2 ( .A3(net_113), .A1(net_112), .ZN(net_65), .A2(net_56) );
NOR2_X2 inst_8 ( .A2(net_29), .A1(net_14), .ZN(CNTVCO2) );
DFFR_X2 inst_118 ( .RN(net_96), .D(net_76), .QN(net_11), .CK(net_147) );
INV_X4 inst_86 ( .A(net_73), .ZN(P6) );
CLKBUF_X2 inst_153 ( .A(net_141), .Z(net_142) );
NAND3_X2 inst_20 ( .A2(net_117), .A3(net_94), .ZN(net_93), .A1(net_57) );
NAND2_X4 inst_27 ( .ZN(net_62), .A1(net_30), .A2(net_27) );
NAND2_X2 inst_38 ( .ZN(net_45), .A2(net_30), .A1(net_17) );
INV_X2 inst_100 ( .A(net_48), .ZN(P4) );
NAND2_X2 inst_52 ( .A2(net_62), .ZN(net_58), .A1(net_48) );
INV_X4 inst_90 ( .ZN(net_44), .A(net_24) );
CLKBUF_X2 inst_140 ( .A(net_122), .Z(net_129) );
NAND2_X2 inst_40 ( .ZN(net_33), .A1(net_32), .A2(READY) );
CLKBUF_X2 inst_162 ( .A(net_150), .Z(net_151) );
CLKBUF_X2 inst_167 ( .A(net_124), .Z(net_156) );
INV_X2 inst_93 ( .A(net_114), .ZN(net_113) );
INV_X4 inst_81 ( .ZN(net_28), .A(net_4) );
INV_X2 inst_95 ( .ZN(net_26), .A(net_7) );
XOR2_X2 inst_1 ( .Z(net_63), .B(net_45), .A(net_16) );
INV_X4 inst_72 ( .ZN(net_115), .A(P0) );
CLKBUF_X2 inst_139 ( .A(net_127), .Z(net_128) );
CLKBUF_X2 inst_155 ( .A(net_123), .Z(net_144) );
NAND2_X2 inst_59 ( .ZN(net_75), .A1(net_62), .A2(net_50) );
CLKBUF_X2 inst_135 ( .A(net_123), .Z(net_124) );
NAND2_X2 inst_44 ( .A1(net_113), .ZN(net_99), .A2(net_56) );
NAND2_X2 inst_55 ( .ZN(net_111), .A1(net_44), .A2(net_2) );
CLKBUF_X2 inst_174 ( .A(net_162), .Z(net_163) );
DFFR_X2 inst_115 ( .RN(net_96), .D(net_70), .QN(net_4), .CK(net_155) );
NAND2_X2 inst_37 ( .A2(net_116), .ZN(net_47), .A1(net_26) );
CLKBUF_X2 inst_148 ( .A(net_136), .Z(net_137) );
CLKBUF_X2 inst_164 ( .A(net_152), .Z(net_153) );
OR2_X4 inst_5 ( .ZN(net_40), .A2(READY), .A1(B2) );
CLKBUF_X2 inst_157 ( .A(net_145), .Z(net_146) );
INV_X4 inst_84 ( .ZN(net_37), .A(net_12) );
NAND2_X2 inst_51 ( .A2(net_62), .ZN(net_57), .A1(net_56) );
CLKBUF_X2 inst_142 ( .A(net_120), .Z(net_131) );
INV_X4 inst_80 ( .ZN(net_20), .A(net_5) );
CLKBUF_X2 inst_173 ( .A(net_161), .Z(net_162) );
INV_X2 inst_105 ( .A(CNTVCO2), .ZN(CNTVCON2) );
MUX2_X2 inst_68 ( .Z(net_70), .B(net_28), .S(net_27), .A(A0) );
INV_X4 inst_78 ( .ZN(net_73), .A(net_2) );
NAND2_X2 inst_42 ( .ZN(net_38), .A1(net_37), .A2(READY) );
CLKBUF_X2 inst_175 ( .A(net_163), .Z(net_164) );
NAND2_X2 inst_53 ( .A2(net_62), .ZN(net_61), .A1(net_60) );
CLKBUF_X2 inst_177 ( .A(net_164), .Z(net_166) );
CLKBUF_X2 inst_133 ( .A(net_121), .Z(net_122) );
NAND2_X4 inst_26 ( .ZN(net_112), .A1(net_100), .A2(net_28) );
CLKBUF_X2 inst_151 ( .A(net_139), .Z(net_140) );
DFFR_X2 inst_112 ( .RN(net_96), .D(net_55), .QN(net_10), .CK(net_167) );
NAND2_X1 inst_64 ( .A2(net_88), .ZN(net_87), .A1(net_83) );
INV_X2 inst_107 ( .ZN(net_110), .A(net_64) );
MUX2_X2 inst_67 ( .Z(net_69), .S(net_27), .B(net_20), .A(A1) );
CLKBUF_X2 inst_181 ( .A(net_169), .Z(net_170) );
AND2_X4 inst_127 ( .A1(net_116), .ZN(net_100), .A2(net_0) );
MUX2_X2 inst_70 ( .S(net_91), .Z(net_77), .A(net_52), .B(net_35) );
CLKBUF_X2 inst_129 ( .A(blif_clk_net), .Z(net_118) );
INV_X4 inst_92 ( .ZN(net_91), .A(net_62) );
NAND2_X4 inst_29 ( .A2(net_99), .A1(net_98), .ZN(net_82) );
NAND3_X2 inst_17 ( .ZN(net_109), .A1(net_88), .A3(net_60), .A2(net_47) );
NOR2_X2 inst_11 ( .ZN(net_74), .A2(net_63), .A1(START) );
CLKBUF_X2 inst_146 ( .A(net_126), .Z(net_135) );
NAND3_X2 inst_14 ( .A1(net_113), .A3(net_112), .A2(net_56), .ZN(net_54) );
DFFR_X2 inst_122 ( .RN(net_96), .D(net_89), .QN(net_0), .CK(net_130) );
NAND2_X4 inst_31 ( .A2(net_102), .A1(net_101), .ZN(net_88) );
NAND2_X4 inst_25 ( .A2(net_116), .ZN(net_21), .A1(net_20) );
CLKBUF_X3 inst_126 ( .A(net_116), .Z(P0) );
CLKBUF_X2 inst_158 ( .A(net_146), .Z(net_147) );
CLKBUF_X2 inst_141 ( .A(net_129), .Z(net_130) );
NAND2_X2 inst_62 ( .ZN(net_92), .A1(net_91), .A2(net_90) );
INV_X1 inst_110 ( .A(net_82), .ZN(net_78) );
INV_X4 inst_74 ( .ZN(net_56), .A(net_1) );
NAND2_X2 inst_57 ( .A2(net_91), .ZN(net_71), .A1(net_32) );
NAND2_X2 inst_35 ( .A2(net_116), .ZN(net_24), .A1(net_23) );
INV_X2 inst_99 ( .A(net_60), .ZN(P7) );
NAND2_X2 inst_48 ( .ZN(net_51), .A1(net_39), .A2(net_36) );
MUX2_X2 inst_69 ( .S(net_91), .Z(net_76), .A(net_53), .B(net_37) );
NAND2_X2 inst_46 ( .ZN(net_49), .A1(net_48), .A2(net_25) );
INV_X4 inst_82 ( .ZN(net_60), .A(net_3) );
CLKBUF_X2 inst_136 ( .A(net_124), .Z(net_125) );
NAND2_X4 inst_30 ( .A2(net_111), .ZN(net_101), .A1(net_82) );
INV_X2 inst_102 ( .ZN(net_16), .A(net_9) );
INV_X2 inst_108 ( .A(net_88), .ZN(net_85) );
CLKBUF_X2 inst_165 ( .A(net_153), .Z(net_154) );
NAND2_X4 inst_32 ( .A2(net_110), .ZN(net_103), .A1(net_88) );
NAND3_X2 inst_22 ( .ZN(net_95), .A2(net_94), .A3(net_92), .A1(net_61) );
CLKBUF_X2 inst_144 ( .A(net_132), .Z(net_133) );
NAND2_X4 inst_34 ( .A2(net_109), .ZN(net_105), .A1(net_90) );
NAND3_X4 inst_12 ( .ZN(net_30), .A2(net_19), .A3(net_15), .A1(net_9) );
NAND2_X2 inst_56 ( .A2(net_112), .ZN(net_66), .A1(net_49) );
MUX2_X2 inst_71 ( .S(net_91), .Z(net_79), .B(net_66), .A(net_51) );
NAND3_X2 inst_21 ( .ZN(net_107), .A3(net_106), .A1(net_105), .A2(net_91) );
INV_X2 inst_104 ( .ZN(net_18), .A(P6) );
NAND2_X2 inst_60 ( .ZN(net_80), .A2(net_75), .A1(net_71) );
CLKBUF_X2 inst_169 ( .A(net_157), .Z(net_158) );
CLKBUF_X2 inst_168 ( .A(net_156), .Z(net_157) );
INV_X2 inst_97 ( .A(net_37), .ZN(P2) );
CLKBUF_X2 inst_161 ( .A(net_149), .Z(net_150) );
DFFR_X2 inst_124 ( .RN(net_96), .D(net_95), .QN(net_3), .CK(net_125) );
NAND3_X2 inst_18 ( .A2(net_94), .ZN(net_89), .A3(net_86), .A1(net_58) );
NAND3_X2 inst_16 ( .A2(net_91), .ZN(net_86), .A3(net_81), .A1(net_65) );
INV_X4 inst_88 ( .ZN(net_22), .A(net_15) );
OR2_X4 inst_3 ( .ZN(net_29), .A1(net_22), .A2(net_9) );
CLKBUF_X2 inst_156 ( .A(net_144), .Z(net_145) );
NOR2_X2 inst_9 ( .ZN(net_64), .A1(net_60), .A2(net_47) );
DFFR_X2 inst_113 ( .RN(net_96), .D(net_67), .QN(net_7), .CK(net_165) );
CLKBUF_X2 inst_170 ( .A(net_158), .Z(net_159) );
NAND2_X2 inst_50 ( .ZN(net_53), .A1(net_41), .A2(net_33) );
CLKBUF_X2 inst_137 ( .A(net_118), .Z(net_126) );
NAND2_X2 inst_41 ( .ZN(net_36), .A1(net_35), .A2(READY) );
CLKBUF_X2 inst_130 ( .A(net_118), .Z(net_119) );
INV_X4 inst_91 ( .ZN(net_72), .A(net_44) );
CLKBUF_X2 inst_132 ( .A(blif_clk_net), .Z(net_121) );
CLKBUF_X2 inst_143 ( .A(net_131), .Z(net_132) );
CLKBUF_X2 inst_176 ( .A(net_164), .Z(net_165) );
CLKBUF_X2 inst_152 ( .A(net_140), .Z(net_141) );
NAND2_X2 inst_58 ( .ZN(net_102), .A1(net_73), .A2(net_72) );
NAND2_X2 inst_36 ( .A2(net_116), .A1(net_28), .ZN(net_25) );
CLKBUF_X2 inst_147 ( .A(net_135), .Z(net_136) );
INV_X4 inst_87 ( .A(net_19), .ZN(net_14) );
NAND2_X2 inst_61 ( .ZN(net_106), .A2(net_85), .A1(net_64) );
NAND2_X2 inst_45 ( .ZN(net_104), .A1(net_60), .A2(net_47) );
INV_X2 inst_96 ( .A(net_32), .ZN(P1) );
INV_X2 inst_101 ( .A(net_56), .ZN(P5) );
XOR2_X2 inst_0 ( .Z(net_43), .A(net_29), .B(net_19) );
NOR2_X2 inst_10 ( .ZN(net_55), .A2(net_43), .A1(START) );
OR2_X4 inst_4 ( .ZN(net_39), .A2(READY), .A1(B3) );
MUX2_X2 inst_65 ( .Z(net_67), .S(net_27), .B(net_26), .A(A3) );
CLKBUF_X2 inst_178 ( .A(net_166), .Z(net_167) );
INV_X4 inst_89 ( .A(net_30), .ZN(READY) );
NAND2_X4 inst_28 ( .A2(net_112), .ZN(net_98), .A1(net_42) );
DFFR_X2 inst_111 ( .RN(net_96), .D(net_46), .QN(net_8), .CK(net_170) );
MUX2_X2 inst_66 ( .Z(net_68), .S(net_27), .B(net_23), .A(A2) );
DFFR_X2 inst_117 ( .RN(net_96), .D(net_74), .QN(net_9), .CK(net_148) );
INV_X2 inst_98 ( .A(net_35), .ZN(P3) );
NAND2_X1 inst_63 ( .A2(net_82), .ZN(net_81), .A1(net_54) );
OR2_X2 inst_7 ( .ZN(net_34), .A2(READY), .A1(B0) );
NAND2_X2 inst_49 ( .ZN(net_52), .A1(net_40), .A2(net_38) );
DFFR_X2 inst_120 ( .QN(net_116), .RN(net_96), .D(net_80), .CK(net_120) );
CLKBUF_X2 inst_154 ( .A(net_142), .Z(net_143) );
NAND3_X2 inst_13 ( .ZN(net_27), .A2(net_22), .A3(net_10), .A1(net_9) );
DFFR_X2 inst_119 ( .RN(net_96), .D(net_77), .QN(net_12), .CK(net_143) );
INV_X4 inst_75 ( .ZN(net_15), .A(net_8) );
CLKBUF_X2 inst_166 ( .A(net_154), .Z(net_155) );
DFFR_X2 inst_116 ( .RN(net_96), .D(net_68), .QN(net_6), .CK(net_151) );
CLKBUF_X2 inst_163 ( .A(net_122), .Z(net_152) );
INV_X4 inst_85 ( .ZN(net_94), .A(START) );
NAND2_X2 inst_54 ( .ZN(net_108), .A2(net_62), .A1(net_18) );
INV_X4 inst_79 ( .ZN(net_35), .A(net_13) );
INV_X1 inst_109 ( .ZN(net_96), .A(blif_reset_net) );
INV_X2 inst_106 ( .A(net_72), .ZN(net_59) );
CLKBUF_X2 inst_149 ( .A(net_137), .Z(net_138) );
NAND2_X2 inst_43 ( .A2(net_114), .ZN(net_42), .A1(net_1) );
NAND2_X2 inst_39 ( .A1(net_115), .ZN(net_31), .A2(READY) );
AND2_X2 inst_128 ( .A1(net_94), .ZN(net_46), .A2(net_45) );
INV_X4 inst_73 ( .ZN(net_114), .A(net_21) );
NAND3_X2 inst_23 ( .A3(net_108), .A1(net_107), .ZN(net_97), .A2(net_94) );
CLKBUF_X2 inst_171 ( .A(net_159), .Z(net_160) );
INV_X4 inst_77 ( .ZN(net_48), .A(net_0) );
INV_X2 inst_94 ( .ZN(net_23), .A(net_6) );
endmodule
|
module ALU (
input signed [15:0] DATA_A, DATA_B,
input [3:0] S_ALU,
output [15:0] ALU_OUT,
output [3:0] FLAG_OUT);
localparam IADD = 4'b0000;
localparam ISUB = 4'b0001;
localparam IAND = 4'b0010;
localparam IOR = 4'b0011;
localparam IXOR = 4'b0100;
localparam ISLL = 4'b1000;
localparam ISLR = 4'b1001;
localparam ISRL = 4'b1010;
localparam ISRA = 4'b1011;
localparam IIDT = 4'b1100;
localparam INON = 4'b1111;
wire S, Z, V;
function [16:0] amux(
input signed [15:0] A, B,
input [3:0] Selector);
case (Selector)
IADD : amux = {1'b0, A} + {1'b0, B};
ISUB : amux = {1'b0, A} - {1'b0, B};
IAND : amux = {1'b0, A & B};
IOR : amux = {1'b0, A | B};
IXOR : amux = {1'b0, A ^ B};
ISLL : amux = {1'b0, A} << B[3:0];
ISLR : amux = ({1'b0, A} << B[3:0]) | (A >> 16 - B[3:0]);
ISRL : amux = {B[3:0] > 0 ? A[B[3:0] - 1] : 1'b0, A >> B[3:0]};
ISRA : amux = {B[3:0] > 0 ? A[B[3:0] - 1] : 1'b0, A >>> B[3:0]};
IIDT : amux = {1'b0, B};
INON : amux = 17'b0;
default : amux = 17'b0;
endcase
endfunction
wire [16:0] result;
assign result = amux(DATA_A, DATA_B, S_ALU);
assign ALU_OUT = result[15:0];
assign S = result[15] == 1'b1 ? 1'b1 : 1'b0;
assign Z = result[15:0] == 16'b0 ? 1'b1 : 1'b0;
assign V = (((S_ALU == IADD) && (DATA_A[15] == DATA_B[15]) && (DATA_A[15] != result[15]))
|| ((S_ALU == ISUB) && (DATA_A[15] != DATA_B[15]) && (DATA_A[15] != result[15]))) ? 1'b1 : 1'b0;
assign FLAG_OUT = {S, Z, result[16], V};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_SYMBOL_V
`define SKY130_FD_SC_HD__DLRTP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_SYMBOL_V
|
module top (
fpga_clk_50,
fpga_reset_n,
ledr, // LEDR
hex0, //HEX0
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [9:0] ledr;
output wire [3:0] hex0;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
wire [29:0] fpga_internal_led;
wire kernel_clk;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0 ), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1 ), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2 ), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3 ), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5 ), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6 ), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7 ), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK ), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP ), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT ), // .hps_io_usb1_inst_NXT
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.acl_iface_led_pio_external_connection_export (ledr[7:0]), //FPGA LED_PIO
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl)
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
// assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
assign hex0[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 29-10-2018
*/
module jt12_eg_step(
input attack,
input [ 4:0] base_rate,
input [ 4:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input [ 1:0] ks,
output cnt_lsb,
output reg step,
output reg [5:0] rate,
output reg sum_up
);
reg [6:0] pre_rate;
always @(*) begin : pre_rate_calc
if( base_rate == 5'd0 )
pre_rate = 7'd0;
else
case( ks )
2'd3: pre_rate = { base_rate, 1'b0 } + { 1'b0, keycode };
2'd2: pre_rate = { base_rate, 1'b0 } + { 2'b0, keycode[4:1] };
2'd1: pre_rate = { base_rate, 1'b0 } + { 3'b0, keycode[4:2] };
2'd0: pre_rate = { base_rate, 1'b0 } + { 4'b0, keycode[4:3] };
endcase
end
always @(*)
rate = pre_rate[6] ? 6'd63 : pre_rate[5:0];
reg [2:0] cnt;
reg [4:0] mux_sel;
always @(*) begin
mux_sel = attack ? (rate[5:2]+4'd1): {1'b0,rate[5:2]};
end // always @(*)
always @(*)
case( mux_sel )
5'h0: cnt = eg_cnt[14:12];
5'h1: cnt = eg_cnt[13:11];
5'h2: cnt = eg_cnt[12:10];
5'h3: cnt = eg_cnt[11: 9];
5'h4: cnt = eg_cnt[10: 8];
5'h5: cnt = eg_cnt[ 9: 7];
5'h6: cnt = eg_cnt[ 8: 6];
5'h7: cnt = eg_cnt[ 7: 5];
5'h8: cnt = eg_cnt[ 6: 4];
5'h9: cnt = eg_cnt[ 5: 3];
5'ha: cnt = eg_cnt[ 4: 2];
5'hb: cnt = eg_cnt[ 3: 1];
default: cnt = eg_cnt[ 2: 0];
endcase
////////////////////////////////
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate[5:2]==4'hf && attack)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate[5:2]==4'd0 && !attack)
step_idx = 8'b11111110; // limit slowest decay rate
else
case( rate[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate of zero keeps the level still
step = rate[5:1]==5'd0 ? 1'b0 : step_idx[ cnt ];
end
assign cnt_lsb = cnt[0];
always @(*) begin
sum_up = cnt[0] != cnt_in;
end
endmodule // eg_step |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:31:54 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_stub.v
// Design : zynq_design_1_system_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_c3fe,Vivado 2017.2" *)
module zynq_design_1_system_ila_0_0(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, SLOT_0_AXI_bready,
SLOT_0_AXI_araddr, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready, SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, resetn)
/* synthesis syn_black_box black_box_pad_pin="clk,SLOT_0_AXI_awaddr[8:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[8:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */;
input clk;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_awready;
input [31:0]SLOT_0_AXI_wdata;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input SLOT_0_AXI_wready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input SLOT_0_AXI_bready;
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arvalid;
input SLOT_0_AXI_arready;
input [31:0]SLOT_0_AXI_rdata;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input SLOT_0_AXI_rready;
input resetn;
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off LITENDIAN
// verilator lint_off BLKANDNBLK
// 3 3 4
reg [71:0] memw [2:0][1:3][5:2];
reg [7:0] memn [2:0][1:3][5:2];
// verilator lint_on BLKANDNBLK
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [71:0] wide;
reg [7:0] narrow;
reg [1:0] index0;
reg [1:0] index1;
reg [2:0] index2;
integer i0,i1,i2;
integer imem[2:0][1:3];
reg [2:0] cstyle[2];
// verilator lint_on LITENDIAN
initial begin
for (i0=0; i0<3; i0=i0+1) begin
for (i1=1; i1<4; i1=i1+1) begin
imem[i0[1:0]] [i1[1:0]] = i1;
for (i2=2; i2<6; i2=i2+1) begin
memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]};
memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001;
end
end
end
end
reg [71:0] wread;
reg wreadb;
always @ (posedge clk) begin
//$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
narrow <= 8'h0;
wide <= 72'h0;
index0 <= 2'b0;
index1 <= 2'b0;
index2 <= 3'b0;
end
else if (cyc<90) begin
index0 <= crc[1:0];
index1 <= crc[3:2];
index2 <= crc[6:4];
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
// We never read past bounds, or get unspecific results
// We also never read lowest indexes, as writing outside of range may corrupt them
if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin
narrow <= ({narrow[6:0], narrow[7]^narrow[0]}
^ {memn[index0][index1][index2]});
wread = memw[index0][index1][index2];
wreadb = memw[index0][index1][index2][2];
wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread);
//$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread);
end
// We may write past bounds of memory
memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0];
memn[index0][index1][index2] <= {~crc[6:0],crc[7]};
memw[index0][index1][index2] <= {~crc[7:0],crc};
//$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc});
cstyle[cyc[0]] <= cyc[2:0];
if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop;
end
else if (cyc==90) begin
memn[0][1][3] <= memn[0][1][3] ^ 8'ha8;
end
else if (cyc==91) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide);
if (crc != 64'h65e3bddcd9bc2750) $stop;
if (narrow != 8'hca) $stop;
if (wide != 72'h4edafed31ba6873f73) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_align_double( clock, resetn,
input_a_mantissa, input_a_exponent, input_a_sign,
input_b_mantissa, input_b_exponent, input_b_sign,
left_mantissa, left_exponent, left_sign,
right_mantissa, right_exponent, right_sign,
valid_in, valid_out, stall_in, stall_out,
enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input [55:0] input_a_mantissa;
input [11:0] input_a_exponent;
input input_a_sign;
input [55:0] input_b_mantissa;
input [11:0] input_b_exponent;
input input_b_sign;
output [55:0] left_mantissa;
output [11:0] left_exponent;
output left_sign;
output [55:0] right_mantissa;
output [11:0] right_exponent;
output right_sign;
input enable, valid_in, stall_in;
output valid_out, stall_out;
// This module aligns two floating point input values such that their exponents are equal,
// permitting a proper addition of the two numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_valid;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
wire c5_enable;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c5_stall;
// Cycle 1 - Determine the magnitude of both numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_r_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [13:0] c1_l_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [13:0] c1_r_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_l_sign, c1_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0]c1_matissa_r_greater, c1_matissas_equal;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exp_equal;
assign c1_enable = (HIGH_CAPACITY ? (~c1_stall | ~c1_valid) : enable);
assign stall_out = c1_stall & c1_valid;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_l_mantissa <= 56'dx;
c1_r_mantissa <= 56'dx;
c1_l_exponent <= 12'dx;
c1_r_exponent <= 12'dx;
c1_l_mantissa_nonzero <= 14'dx;
c1_r_mantissa_nonzero <= 14'dx;
c1_l_sign <= 1'bx;
c1_r_sign <= 1'bx;
c1_matissa_r_greater <= 2'bxx;
c1_exp_diff <= 12'dx;
c1_exp_equal <= 1'bx;
c1_matissas_equal <= 2'bxx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if ((FINITE_MATH_ONLY == 0) && (input_a_exponent[11] || input_b_exponent[11]))
begin
c1_exp_diff <= 12'd0;
c1_exp_equal <= 1'b1;
end
else
begin
c1_exp_diff <= {1'b0, input_a_exponent[10:0]} - {1'b0, input_b_exponent[10:0]};
c1_exp_equal <= (input_a_exponent[10:0] == input_b_exponent[10:0]);
end
c1_l_mantissa <= input_a_mantissa;
c1_r_mantissa <= input_b_mantissa;
c1_l_exponent <= input_a_exponent;
c1_r_exponent <= input_b_exponent;
c1_l_mantissa_nonzero <= {input_a_exponent[11] ? (|input_a_mantissa[54:52]) : (|input_a_mantissa[55:52]), |input_a_mantissa[51:48], |input_a_mantissa[47:44], |input_a_mantissa[43:40], |input_a_mantissa[39:36], |input_a_mantissa[35:32], |input_a_mantissa[31:28], |input_a_mantissa[27:24], |input_a_mantissa[23:20], |input_a_mantissa[19:16], |input_a_mantissa[15:12], |input_a_mantissa[11:8], |input_a_mantissa[7:3], |input_a_mantissa[2:0]};
c1_r_mantissa_nonzero <= {input_b_exponent[11] ? (|input_b_mantissa[54:52]) : (|input_b_mantissa[55:52]), |input_b_mantissa[51:48], |input_b_mantissa[47:44], |input_b_mantissa[43:40], |input_b_mantissa[39:36], |input_b_mantissa[35:32], |input_b_mantissa[31:28], |input_b_mantissa[27:24], |input_b_mantissa[23:20], |input_b_mantissa[19:16], |input_b_mantissa[15:12], |input_b_mantissa[11:8], |input_b_mantissa[7:3], |input_b_mantissa[2:0]};
c1_l_sign <= input_a_sign;
c1_r_sign <= input_b_sign;
c1_matissa_r_greater <= {{1'b0, input_b_mantissa[55:28]} > {1'b0, input_a_mantissa[55:28]}, {1'b0, input_b_mantissa[27:0]} > {1'b0, input_a_mantissa[27:0]} };
c1_matissas_equal <= {(input_b_mantissa[55:28] == input_a_mantissa[55:28]),(input_b_mantissa[27:0] == input_a_mantissa[27:0])};
end
end
// Cycle 2 - Swap numbers such that the larger one is the left and the smaller one is the right.
// If the numbers are equal in magnitude, then pick the positive one to be the left one.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c2_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c2_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c2_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_l_sign, c2_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c2_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_r_mantissa_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_lr_mantissa_info;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_diff_signs;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c2_exponents;
assign c2_enable = (HIGH_CAPACITY ? (~c2_stall | ~c2_valid) : enable);
assign c1_stall = c2_stall & c2_valid;
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_l_mantissa <= 56'dx;
c2_r_mantissa <= 56'dx;
c2_l_exponent <= 12'dx;
c2_l_sign <= 1'bx;
c2_r_sign <= 1'bx;
c2_r_mantissa_nonzero <= 4'dx;
c2_lr_mantissa_info <= 4'dx;
c2_diff_signs <= 1'bx;
c2_exponents <= 2'bxx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_diff_signs <= c1_l_sign ^ c1_r_sign;
c2_exponents <= {c1_l_exponent[11], c1_r_exponent[11]};
// Here we account for denorms
if (c1_exp_diff[11])
begin
c2_exp_diff <= {12{c1_r_mantissa[55] ^ c1_l_mantissa[55]}} - c1_exp_diff;
end
else
begin
if (FINITE_MATH_ONLY == 0)
c2_exp_diff <= (c1_l_exponent[11] || c1_r_exponent[11]) ? c1_exp_diff : c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
else
c2_exp_diff <= c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
end
if ((c1_l_exponent[11] || c1_r_exponent[11]) && (FINITE_MATH_ONLY == 0))
begin
// Here we handle the cases of NaN and Inf values.
// I need to split this into two stages, otherwise the logic is really complicated.
// When testing for non-zero mantissa we need to check that the exponent is maxed out.
// We use c3_lr_mantissa_info to convey this information to the next cycle.
c2_lr_mantissa_info <= {|c1_l_mantissa_nonzero[13:7], |c1_l_mantissa_nonzero[6:0], |c1_r_mantissa_nonzero[13:7], |c1_r_mantissa_nonzero[6:0]};
c2_l_mantissa[55] <= 1'b1; // Inf
c2_l_mantissa[54:0] <= 55'd0; // Inf
c2_r_mantissa <= 56'd0;
c2_l_exponent <= 12'hfff;
c2_l_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
else
if ((&c1_matissas_equal) & c1_exp_equal & ~c1_r_sign |
(c1_exp_equal & (c1_matissa_r_greater[1] | c1_matissas_equal[1] & c1_matissa_r_greater[0])) | (c1_exp_diff[11]))
begin
// Swap left and right inputs
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_r_mantissa;
c2_r_mantissa <= c1_l_mantissa;
c2_l_exponent <= c1_r_exponent;
c2_l_sign <= c1_r_sign;
c2_r_sign <= c1_l_sign;
c2_r_mantissa_nonzero <= {|c1_l_mantissa_nonzero[13:12], |c1_l_mantissa_nonzero[11:8], |c1_l_mantissa_nonzero[7:4], |c1_l_mantissa_nonzero[3:0]};
end
else
begin
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_l_mantissa;
c2_r_mantissa <= c1_r_mantissa;
c2_l_exponent <= c1_l_exponent;
c2_l_sign <= c1_l_sign;
c2_r_sign <= c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
end
end
end
else
begin
// Do not register this stage in low-latency mode.
always @(*)
begin
c2_valid <= c1_valid;
c2_diff_signs <= c1_l_sign ^ c1_r_sign;
c2_exponents <= {c1_l_exponent[11], c1_r_exponent[11]};
// Here we account for denorms
if (c1_exp_diff[11])
begin
c2_exp_diff <= {12{c1_r_mantissa[55] ^ c1_l_mantissa[55]}} - c1_exp_diff;
end
else
begin
if (FINITE_MATH_ONLY == 0)
c2_exp_diff <= (c1_l_exponent[11] || c1_r_exponent[11]) ? c1_exp_diff : c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
else
c2_exp_diff <= c1_exp_diff - {1'b0, c1_r_mantissa[55] ^ c1_l_mantissa[55]};
end
if ((c1_l_exponent[11] || c1_r_exponent[11]) && (FINITE_MATH_ONLY == 0))
begin
// Here we handle the cases of NaN and Inf values.
// I need to split this into two stages, otherwise the logic is really complicated.
// When testing for non-zero mantissa we need to check that the exponent is maxed out.
// We use c3_lr_mantissa_info to convey this information to the next cycle.
c2_lr_mantissa_info <= {|c1_l_mantissa_nonzero[13:7], |c1_l_mantissa_nonzero[6:0], |c1_r_mantissa_nonzero[13:7], |c1_r_mantissa_nonzero[6:0]};
c2_l_mantissa[55] <= 1'b1; // Inf
c2_l_mantissa[54:0] <= 55'd0; // Inf
c2_r_mantissa <= 56'd0;
c2_l_exponent <= 12'hfff;
c2_l_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_sign <= c1_l_exponent[11] ? c1_l_sign : c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
else
if ((&c1_matissas_equal) & c1_exp_equal & ~c1_r_sign |
(c1_exp_equal & (c1_matissa_r_greater[1] | c1_matissas_equal[1] & c1_matissa_r_greater[0])) | (c1_exp_diff[11]))
begin
// Swap left and right inputs
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_r_mantissa;
c2_r_mantissa <= c1_l_mantissa;
c2_l_exponent <= c1_r_exponent;
c2_l_sign <= c1_r_sign;
c2_r_sign <= c1_l_sign;
c2_r_mantissa_nonzero <= {|c1_l_mantissa_nonzero[13:12], |c1_l_mantissa_nonzero[11:8], |c1_l_mantissa_nonzero[7:4], |c1_l_mantissa_nonzero[3:0]};
end
else
begin
c2_lr_mantissa_info <= 4'd0;
c2_l_mantissa <= c1_l_mantissa;
c2_r_mantissa <= c1_r_mantissa;
c2_l_exponent <= c1_l_exponent;
c2_l_sign <= c1_l_sign;
c2_r_sign <= c1_r_sign;
c2_r_mantissa_nonzero <= {|c1_r_mantissa_nonzero[13:12], |c1_r_mantissa_nonzero[11:8], |c1_r_mantissa_nonzero[7:4], |c1_r_mantissa_nonzero[3:0]};
end
end
end
endgenerate
// Cycle 3 - shift data in the right input as much as needed to match exponents
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c3_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c3_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c3_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_l_sign, c3_r_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c3_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_clear_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_sticky_right;
assign c3_enable = (HIGH_CAPACITY ? (~c3_stall | ~c3_valid) : enable);
assign c2_stall = c3_stall & c3_valid;
reg [1:0] c3_select;
always@(*)
begin
if (c2_exp_diff >= 9'd48)
c3_select = 2'b11;
else if (c2_exp_diff >= 9'd32)
c3_select = 2'b10;
else if (c2_exp_diff >= 9'd16)
c3_select = 2'b01;
else
c3_select = 2'b00;
end
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_l_mantissa <= 27'dx;
c3_r_mantissa <= 27'dx;
c3_l_exponent <= 9'dx;
c3_l_sign <= 1'bx;
c3_r_sign <= 1'bx;
c3_clear_right <= 1'bx;
c3_sticky_right <= 1'bx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
// A number becomes a NaN when
// 1. it is a sum of positive and negative infinities
// 2. one of the numbers is a NaN
if ((FINITE_MATH_ONLY == 0) && ((c2_exponents[1] & c2_exponents[0] & ~(|c2_lr_mantissa_info) & c2_diff_signs) ||
(c2_exponents[1] & (|c2_lr_mantissa_info[3:2]) | c2_exponents[0] & (|c2_lr_mantissa_info[1:0]))))
c3_l_mantissa[54] <= 1'b1; // Make a number into a NaN if it was infinity before.
else
c3_l_mantissa[54] <= c2_l_mantissa[54];
c3_l_mantissa[55] <= c2_l_mantissa[55];
c3_l_mantissa[53:0] <= c2_l_mantissa[53:0];
c3_l_exponent <= c2_l_exponent;
c3_l_sign <= c2_l_sign;
c3_r_sign <= c2_r_sign;
c3_clear_right <= (c2_exp_diff >= 12'd56);
if (REMOVE_STICKY == 1)
c3_sticky_right <= 1'b0;
else
c3_sticky_right <= |c2_r_mantissa_nonzero;
c3_exp_diff <= c2_exp_diff - {1'b0, c3_select, 4'd0};
case(c3_select)
2'b11:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {48'd0, c2_r_mantissa[55:49], c2_r_mantissa[48]};
else
c3_r_mantissa <= {48'd0, c2_r_mantissa[55:49], c2_r_mantissa[48] | (|c2_r_mantissa_nonzero[2:0])};
end
2'b10:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {32'd0, c2_r_mantissa[55:33], c2_r_mantissa[32]};
else
c3_r_mantissa <= {32'd0, c2_r_mantissa[55:33], c2_r_mantissa[32] | (|c2_r_mantissa_nonzero[1:0])};
end
2'b01:
begin
if (REMOVE_STICKY == 1)
c3_r_mantissa <= {16'd0, c2_r_mantissa[55:17], c2_r_mantissa[16]};
else
c3_r_mantissa <= {16'd0, c2_r_mantissa[55:17], c2_r_mantissa[16] | (c2_r_mantissa_nonzero[0])};
end
2'b00:
begin
c3_r_mantissa <= c2_r_mantissa;
end
endcase
end
end
// Cycle 4 - Shift by 12, 8 or 4.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c4_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c4_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c4_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c4_exp_diff;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_l_sign, c4_r_sign;
assign c4_enable = (HIGH_CAPACITY ? (~c4_stall | ~c4_valid) : enable);
assign c3_stall = c4_stall & c4_valid;
reg c4_sticky_bit;
always@(*)
begin
if (REMOVE_STICKY == 1)
c4_sticky_bit = 1'b0;
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_sticky_bit = |c3_r_mantissa[11:0];
2'h2: c4_sticky_bit = |c3_r_mantissa[7:0];
2'h1: c4_sticky_bit = |c3_r_mantissa[3:0];
2'h0: c4_sticky_bit = 1'b0;
endcase
end
end
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_l_mantissa <= 56'dx;
c4_r_mantissa <= 56'dx;
c4_l_exponent <= 12'dx;
c4_l_sign <= 1'bx;
c4_r_sign <= 1'bx;
c4_exp_diff <= 2'bxx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_l_mantissa <= c3_l_mantissa;
c4_l_exponent <= c3_l_exponent;
c4_l_sign <= c3_l_sign;
c4_r_sign <= c3_r_sign;
c4_exp_diff <= c3_exp_diff[1:0];
if (c3_clear_right)
begin
c4_r_mantissa <= c3_sticky_right ? 56'd1 : 56'd0;
end
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_r_mantissa <= {12'd0, c3_r_mantissa[55:13], c3_r_mantissa[12] | c4_sticky_bit};
2'h2: c4_r_mantissa <= {8'd0, c3_r_mantissa[55:9], c3_r_mantissa[8] | c4_sticky_bit};
2'h1: c4_r_mantissa <= {4'd0, c3_r_mantissa[55:5], c3_r_mantissa[4] | c4_sticky_bit};
2'h0: c4_r_mantissa <= c3_r_mantissa;
endcase
end
end
end
end
else
begin
// in low latency mode do not register this stage.
always @(*)
begin
c4_valid <= c3_valid;
c4_l_mantissa <= c3_l_mantissa;
c4_l_exponent <= c3_l_exponent;
c4_l_sign <= c3_l_sign;
c4_r_sign <= c3_r_sign;
c4_exp_diff <= c3_exp_diff[1:0];
if (c3_clear_right)
begin
c4_r_mantissa <= c3_sticky_right ? 56'd1 : 56'd0;
end
else
begin
case(c3_exp_diff[3:2])
2'h3: c4_r_mantissa <= {12'd0, c3_r_mantissa[55:13], c3_r_mantissa[12] | c4_sticky_bit};
2'h2: c4_r_mantissa <= {8'd0, c3_r_mantissa[55:9], c3_r_mantissa[8] | c4_sticky_bit};
2'h1: c4_r_mantissa <= {4'd0, c3_r_mantissa[55:5], c3_r_mantissa[4] | c4_sticky_bit};
2'h0: c4_r_mantissa <= c3_r_mantissa;
endcase
end
end
end
endgenerate
// Cycle 5 - Complete the shifting of data and produce a final result
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c5_l_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c5_r_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c5_l_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_l_sign, c5_r_sign;
assign c5_enable = (HIGH_CAPACITY ? (~c5_stall | ~c5_valid) : enable);
assign c4_stall = c5_stall & c5_valid;
reg c5_sticky_bit;
always@(*)
begin
case(c4_exp_diff)
2'h3: c5_sticky_bit = |c4_r_mantissa[2:0];
2'h2: c5_sticky_bit = |c4_r_mantissa[1:0];
2'h1: c5_sticky_bit = c4_r_mantissa[0];
2'h0: c5_sticky_bit = 1'b0;
endcase
end
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_l_mantissa <= 27'dx;
c5_r_mantissa <= 27'dx;
c5_l_exponent <= 9'dx;
c5_l_sign <= 1'bx;
c5_r_sign <= 1'bx;
c5_valid <= 1'b0;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_l_mantissa <= c4_l_mantissa;
c5_l_exponent <= c4_l_exponent;
c5_l_sign <= c4_l_sign;
c5_r_sign <= c4_r_sign;
c5_r_mantissa <= (c4_r_mantissa >> c4_exp_diff) | c5_sticky_bit;
end
end
assign c5_stall = stall_in;
assign valid_out = c5_valid;
assign left_mantissa = c5_l_mantissa;
assign left_exponent = c5_l_exponent;
assign left_sign = c5_l_sign;
assign right_mantissa = c5_r_mantissa;
assign right_exponent = c5_l_exponent;
assign right_sign = c5_r_sign;
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module acl_fp_custom_mul_op_s5 (
clock, resetn,
mantissa_left, exponent_left, sign_left,
mantissa_right, exponent_right, sign_right,
result_mantissa,
result_exponent,
result_sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
parameter HIGH_LATENCY = 1;
input clock, resetn;
input [26:0] mantissa_left;
input [8:0] exponent_left;
input sign_left;
input [26:0] mantissa_right;
input [8:0] exponent_right;
input sign_right;
input enable;
input stall_in, valid_in;
output stall_out, valid_out;
output [27:0] result_mantissa;
output [8:0] result_exponent;
output result_sign;
wire [53:0] sub_wire0;
wire enable_mult_stage;
// The multiplier. -- CAUTION This only works for HIGH_LATENCY == 0 --> 2 cycles
sv_mult27 the_multiplier(clock,enable_mult_stage,mantissa_left,mantissa_right,sub_wire0);
reg [9:0] exponent_1;
reg [8:0] exponent_2;
reg [8:0] exponent_3;
reg [5:0] man_a_clear;
reg [5:0] man_b_clear;
reg exp_zeroed;
reg sign_1, sign_2, sign_3, exp_out_of_range, generate_inf, exp_left, exp_right;
reg valid_1, valid_2, valid_3, flush_mantissa, make_nan, make_nan_r;
wire stall_mult;
assign enable_mult_stage = (HIGH_CAPACITY == 1) ? (~valid_2 | ~stall_mult) : enable;
assign stall_out = valid_2 & stall_mult;
generate
if (HIGH_LATENCY == 1)
begin
reg flush_mantissa_r;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exponent_1 <= 10'dx;
exponent_2 <= 9'dx;
exponent_3 <= 9'dx;
exp_out_of_range <= 1'bx;
sign_1 <= 1'bx;
sign_2 <= 1'bx;
sign_3 <= 1'bx;
flush_mantissa_r <= 1'bx;
flush_mantissa <= 1'bx;
man_a_clear <= 6'dx;
man_b_clear <= 6'dx;
make_nan_r <= 1'bx;
make_nan <= 1'bx;
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
exp_left <= 1'bx;
exp_right <= 1'bx;
exp_zeroed <= 1'bx;
end
else if (enable_mult_stage)
begin
valid_1 <= valid_in;
valid_2 <= valid_1;
sign_1 <= sign_left ^ sign_right;
sign_2 <= sign_1;
exp_left <= exponent_left[8];
exp_right <= exponent_right[8];
exp_out_of_range <= (exponent_left[8] | exponent_right[8]);
if ((exponent_left[8] || exponent_right[8]) && (FINITE_MATH_ONLY == 0))
exponent_1 <= 10'h1ff;
else
exponent_1 <= exponent_left + exponent_right - 10'd127;
man_a_clear <= {mantissa_left[26], |mantissa_left[25:21], |mantissa_left[20:15], |mantissa_left[14:10], |mantissa_left[9:5], |mantissa_left[4:0]};
man_b_clear <= {mantissa_right[26], |mantissa_right[25:21], |mantissa_right[20:15], |mantissa_right[14:10], |mantissa_right[9:5], |mantissa_right[4:0]};
// Second cycle.
flush_mantissa_r <= 1'b0;
make_nan_r <= 1'b0;
if (exp_out_of_range && (FINITE_MATH_ONLY == 0))
begin
exponent_2 <= 9'h1ff;
if (((exp_left & (~|man_a_clear[4:0])) & (~exp_right & (~|man_b_clear))) ||
((exp_right & (~|man_b_clear[4:0])) & (~exp_left & (~|man_a_clear))) ||
((exp_left & (|man_a_clear[4:0])) || (exp_right & (|man_b_clear[4:0]))))
make_nan_r <= 1'b1;
else
flush_mantissa_r <= 1'b1;
end
else if (exponent_1[9]) // resulting exponent is less than zero.
begin
exponent_2 <= 9'd0;
flush_mantissa_r <= 1'b1;
end
else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0))// resulting exponent is above max
begin
flush_mantissa_r <= 1'b1;
exponent_2 <= 9'h1ff;
end
else
exponent_2 <= exponent_1[8:0];
// Third cycle.
exp_zeroed <= ~|exponent_2;
flush_mantissa <= flush_mantissa_r;
exponent_3 <= exponent_2;
sign_3 <= sign_2;
valid_3 <= valid_2;
make_nan <= make_nan_r;
end
end
end
else
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exponent_1 <= 10'dx;
exponent_2 <= 9'dx;
exp_out_of_range <= 1'bx;
sign_1 <= 1'bx;
sign_2 <= 1'bx;
flush_mantissa <= 1'bx;
man_a_clear <= 5'dx;
man_b_clear <= 5'dx;
make_nan <= 1'bx;
valid_1 <= 1'b0;
valid_2 <= 1'b0;
exp_left <= 1'bx;
exp_right <= 1'bx;
exp_zeroed <= 1'bx;
end
else if (enable_mult_stage)
begin
valid_1 <= valid_in;
valid_2 <= valid_1;
sign_1 <= sign_left ^ sign_right;
sign_2 <= sign_1;
exp_out_of_range <= exponent_left[8] | exponent_right[8];
exp_left <= exponent_left[8];
exp_right <= exponent_right[8];
if ((exponent_left[8] || exponent_right[8]) && (FINITE_MATH_ONLY == 0))
exponent_1 <= 10'h1ff;
else
exponent_1 <= exponent_left + exponent_right - 10'd127;
man_a_clear <= {mantissa_left[26], |mantissa_left[25:21], |mantissa_left[20:15], |mantissa_left[14:10], |mantissa_left[9:5], |mantissa_left[4:0]};
man_b_clear <= {mantissa_right[26], |mantissa_right[25:21], |mantissa_right[20:15], |mantissa_right[14:10], |mantissa_right[9:5], |mantissa_right[4:0]};
// Second cycle.
flush_mantissa <= 1'b0;
make_nan <= 1'b0;
if (exp_out_of_range && (FINITE_MATH_ONLY == 0))
begin
exponent_2 <= 9'h1ff;
if (((exp_left & (~|man_a_clear[4:0])) & (~exp_right & (~|man_b_clear))) ||
((exp_right & (~|man_b_clear[4:0])) & (~exp_left & (~|man_a_clear))) ||
((exp_left & (|man_a_clear[4:0])) || (exp_right & (|man_b_clear[4:0]))))
make_nan <= 1'b1;
else
flush_mantissa <= 1'b1;
end
else if (exponent_1[9]) // resulting exponent is less than zero.
begin
exponent_2 <= 9'd0;
flush_mantissa <= 1'b1;
end
else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0)) // resulting exponent is above max
begin
flush_mantissa <= 1'b1;
exponent_2 <= 9'h1ff;
end
else
exponent_2 <= exponent_1[8:0];
exp_zeroed <= ~|exponent_1;
end
end
end
endgenerate
// Now collect results in registers.
reg [27:0] mult_result_int;
reg [8:0] mult_exp_int;
reg mult_sign_int;
reg mult_valid_int;
reg [4:0] mult_tail_bits;
reg exp_was_zero;
reg clear_mantissa;
reg is_nan;
wire stall_post_int;
wire enable_post_mult_stage_int;
assign enable_post_mult_stage_int = (HIGH_CAPACITY == 1) ? (~mult_valid_int | ~stall_post_int) : enable;
assign stall_mult = mult_valid_int & stall_post_int;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
mult_valid_int <= 1'b0;
mult_result_int <= 28'dx;
mult_exp_int <= 9'dx;
clear_mantissa <= 1'bx;
mult_tail_bits <= 5'dx;
exp_was_zero <= 1'bx;
is_nan <= 1'bx;
mult_sign_int <= 1'bx;
end
else if (enable_post_mult_stage_int)
begin
mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2;
is_nan <= make_nan;
clear_mantissa <= flush_mantissa | ((FLUSH_DENORMS == 1) & exp_zeroed & (~|sub_wire0[53:52]));
mult_result_int <= sub_wire0[53:26];
exp_was_zero <= exp_zeroed;
mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2;
mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2;
if (REMOVE_STICKY == 1)
mult_tail_bits <= 5'd0;
else
mult_tail_bits <= {|sub_wire0[25:20],|sub_wire0[19:15],|sub_wire0[14:10],|sub_wire0[9:5],|sub_wire0[4:0]};
end
end
end
else
begin
always@(*)
begin
mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2;
is_nan <= make_nan;
clear_mantissa <= flush_mantissa | ((FLUSH_DENORMS == 1) & exp_zeroed & (~|sub_wire0[53:52]));
mult_result_int <= sub_wire0[53:26];
exp_was_zero <= exp_zeroed;
mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2;
mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2;
if (REMOVE_STICKY == 1)
mult_tail_bits <= 5'd0;
else
mult_tail_bits <= {|sub_wire0[25:20],|sub_wire0[19:15],|sub_wire0[14:10],|sub_wire0[9:5],|sub_wire0[4:0]};
end
end
endgenerate
// Now collect results in registers.
reg [27:0] mult_result;
reg [8:0] mult_exp;
reg mult_sign;
reg mult_valid;
wire stall_post, enable_post_mult_stage;
assign enable_post_mult_stage = (HIGH_CAPACITY == 1) ? (~mult_valid | ~stall_post) : enable;
assign stall_post_int = mult_valid & stall_post;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
mult_valid <= 1'b0;
mult_result <= 28'dx;
mult_exp <= 9'dx;
mult_sign <= 1'bx;
end
else if (enable_post_mult_stage)
begin
mult_valid <= mult_valid_int;
if (REMOVE_STICKY == 1)
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:1]};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0];
end
else
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:2], |mult_result_int[1:0] | (|mult_tail_bits)};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] | (|mult_tail_bits)};
end
if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa)
mult_exp <= 9'd1;
else
mult_exp <= mult_exp_int;
mult_sign <= mult_sign_int;
end
end
end
else
begin
always@(*)
begin
mult_valid <= mult_valid_int;
if (REMOVE_STICKY == 1)
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:1]};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0];
end
else
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:2], |mult_result_int[1:0] | (|mult_tail_bits)};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] | (|mult_tail_bits)};
end
if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa)
mult_exp <= 9'd1;
else
mult_exp <= mult_exp_int;
mult_sign <= mult_sign_int;
end
end
endgenerate
// Now put a staging register if we are in high-capacity mode
generate
if (HIGH_CAPACITY == 1)
begin
reg [27:0] result_mantissa_sr;
reg [8:0] result_exponent_sr;
reg result_sign_sr;
reg result_sr_valid;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_mantissa_sr <= 28'dx;
result_exponent_sr <= 9'dx;
result_sign_sr <= 1'bx;
result_sr_valid <= 1'b0;
end
else
begin
if (~stall_in)
result_sr_valid <= 1'b0;
else if (~result_sr_valid)
result_sr_valid <= mult_valid;
if (~result_sr_valid)
begin
result_mantissa_sr <= mult_result;
result_exponent_sr <= mult_exp;
result_sign_sr <= mult_sign;
end
end
end
assign result_mantissa = result_sr_valid ? result_mantissa_sr : mult_result;
assign result_exponent = result_sr_valid ? result_exponent_sr : mult_exp;
assign result_sign = result_sr_valid ? result_sign_sr : mult_sign;
assign valid_out = result_sr_valid | mult_valid;
assign stall_post = result_sr_valid;
end
else
begin
assign result_mantissa = mult_result;
assign result_exponent = mult_exp;
assign result_sign = mult_sign;
assign valid_out = mult_valid;
assign stall_post = stall_in;
end
endgenerate
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_div CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" OPTIMIZE="SPEED" PIPELINE=24 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_div 2012:05:31:20:08:02:SJ cbx_altsyncram 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_abs 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_decode 2012:05:31:20:08:02:SJ cbx_lpm_divide 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_stratixiii 2012:05:31:20:08:02:SJ cbx_stratixv 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altfp_div_pst CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" FILE_NAME="acl_fp_div_s5_double.v:a" PIPELINE=24 WIDTH_EXP=11 WIDTH_MAN=52 aclr clk_en clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_div 2012:05:31:20:08:02:SJ cbx_altsyncram 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_abs 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_decode 2012:05:31:20:08:02:SJ cbx_lpm_divide 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_stratixiii 2012:05:31:20:08:02:SJ cbx_stratixv 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = altsyncram 1 lpm_add_sub 8 lpm_compare 1 lpm_mult 9 mux21 141 reg 3551
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_s5_double_altfp_div_pst_luf
(
aclr,
clk_en,
clock,
dataa,
datab,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] wire_altsyncram3_q_a;
reg a_is_infinity_dffe_0;
reg a_is_infinity_dffe_1;
reg a_is_infinity_dffe_10;
reg a_is_infinity_dffe_11;
reg a_is_infinity_dffe_12;
reg a_is_infinity_dffe_13;
reg a_is_infinity_dffe_14;
reg a_is_infinity_dffe_15;
reg a_is_infinity_dffe_16;
reg a_is_infinity_dffe_17;
reg a_is_infinity_dffe_18;
reg a_is_infinity_dffe_19;
reg a_is_infinity_dffe_2;
reg a_is_infinity_dffe_20;
reg a_is_infinity_dffe_21;
reg a_is_infinity_dffe_22;
reg a_is_infinity_dffe_3;
reg a_is_infinity_dffe_4;
reg a_is_infinity_dffe_5;
reg a_is_infinity_dffe_6;
reg a_is_infinity_dffe_7;
reg a_is_infinity_dffe_8;
reg a_is_infinity_dffe_9;
reg a_zero_b_not_dffe_0;
reg a_zero_b_not_dffe_1;
reg a_zero_b_not_dffe_10;
reg a_zero_b_not_dffe_11;
reg a_zero_b_not_dffe_12;
reg a_zero_b_not_dffe_13;
reg a_zero_b_not_dffe_14;
reg a_zero_b_not_dffe_15;
reg a_zero_b_not_dffe_16;
reg a_zero_b_not_dffe_17;
reg a_zero_b_not_dffe_18;
reg a_zero_b_not_dffe_19;
reg a_zero_b_not_dffe_2;
reg a_zero_b_not_dffe_20;
reg a_zero_b_not_dffe_21;
reg a_zero_b_not_dffe_22;
reg a_zero_b_not_dffe_3;
reg a_zero_b_not_dffe_4;
reg a_zero_b_not_dffe_5;
reg a_zero_b_not_dffe_6;
reg a_zero_b_not_dffe_7;
reg a_zero_b_not_dffe_8;
reg a_zero_b_not_dffe_9;
reg [62:0] b1_dffe_0;
reg [62:0] b1_dffe_1;
reg [62:0] b1_dffe_10;
reg [62:0] b1_dffe_11;
reg [62:0] b1_dffe_12;
reg [62:0] b1_dffe_13;
reg [62:0] b1_dffe_2;
reg [62:0] b1_dffe_3;
reg [62:0] b1_dffe_4;
reg [62:0] b1_dffe_5;
reg [62:0] b1_dffe_6;
reg [62:0] b1_dffe_7;
reg [62:0] b1_dffe_8;
reg [62:0] b1_dffe_9;
reg b_is_infinity_dffe_0;
reg b_is_infinity_dffe_1;
reg b_is_infinity_dffe_10;
reg b_is_infinity_dffe_11;
reg b_is_infinity_dffe_12;
reg b_is_infinity_dffe_13;
reg b_is_infinity_dffe_14;
reg b_is_infinity_dffe_15;
reg b_is_infinity_dffe_16;
reg b_is_infinity_dffe_17;
reg b_is_infinity_dffe_18;
reg b_is_infinity_dffe_19;
reg b_is_infinity_dffe_2;
reg b_is_infinity_dffe_20;
reg b_is_infinity_dffe_21;
reg b_is_infinity_dffe_22;
reg b_is_infinity_dffe_3;
reg b_is_infinity_dffe_4;
reg b_is_infinity_dffe_5;
reg b_is_infinity_dffe_6;
reg b_is_infinity_dffe_7;
reg b_is_infinity_dffe_8;
reg b_is_infinity_dffe_9;
reg both_exp_zeros_dffe;
reg divbyzero_pipe_dffe_0;
reg divbyzero_pipe_dffe_1;
reg divbyzero_pipe_dffe_10;
reg divbyzero_pipe_dffe_11;
reg divbyzero_pipe_dffe_12;
reg divbyzero_pipe_dffe_13;
reg divbyzero_pipe_dffe_14;
reg divbyzero_pipe_dffe_15;
reg divbyzero_pipe_dffe_16;
reg divbyzero_pipe_dffe_17;
reg divbyzero_pipe_dffe_18;
reg divbyzero_pipe_dffe_19;
reg divbyzero_pipe_dffe_2;
reg divbyzero_pipe_dffe_20;
reg divbyzero_pipe_dffe_21;
reg divbyzero_pipe_dffe_22;
reg divbyzero_pipe_dffe_3;
reg divbyzero_pipe_dffe_4;
reg divbyzero_pipe_dffe_5;
reg divbyzero_pipe_dffe_6;
reg divbyzero_pipe_dffe_7;
reg divbyzero_pipe_dffe_8;
reg divbyzero_pipe_dffe_9;
reg [16:0] e1_dffe_0;
reg [16:0] e1_dffe_1;
reg [16:0] e1_dffe_2;
reg [16:0] e1_dffe_3;
reg [16:0] e1_dffe_4;
reg [16:0] e1_dffe_5;
reg [16:0] e1_dffe_perf_0;
reg [16:0] e1_dffe_perf_1;
reg [16:0] e1_dffe_perf_10;
reg [16:0] e1_dffe_perf_11;
reg [16:0] e1_dffe_perf_2;
reg [16:0] e1_dffe_perf_3;
reg [16:0] e1_dffe_perf_4;
reg [16:0] e1_dffe_perf_5;
reg [16:0] e1_dffe_perf_6;
reg [16:0] e1_dffe_perf_7;
reg [16:0] e1_dffe_perf_8;
reg [16:0] e1_dffe_perf_9;
reg [10:0] exp_result_dffe_0;
reg [10:0] exp_result_dffe_1;
reg [10:0] exp_result_dffe_10;
reg [10:0] exp_result_dffe_11;
reg [10:0] exp_result_dffe_12;
reg [10:0] exp_result_dffe_13;
reg [10:0] exp_result_dffe_14;
reg [10:0] exp_result_dffe_15;
reg [10:0] exp_result_dffe_16;
reg [10:0] exp_result_dffe_17;
reg [10:0] exp_result_dffe_18;
reg [10:0] exp_result_dffe_19;
reg [10:0] exp_result_dffe_2;
reg [10:0] exp_result_dffe_20;
reg [10:0] exp_result_dffe_21;
reg [10:0] exp_result_dffe_3;
reg [10:0] exp_result_dffe_4;
reg [10:0] exp_result_dffe_5;
reg [10:0] exp_result_dffe_6;
reg [10:0] exp_result_dffe_7;
reg [10:0] exp_result_dffe_8;
reg [10:0] exp_result_dffe_9;
reg frac_a_smaller_dffe1;
reg [51:0] man_a_dffe1_dffe1;
reg [51:0] man_b_dffe1_dffe1;
reg [51:0] man_result_dffe;
reg nan_pipe_dffe_0;
reg nan_pipe_dffe_1;
reg nan_pipe_dffe_10;
reg nan_pipe_dffe_11;
reg nan_pipe_dffe_12;
reg nan_pipe_dffe_13;
reg nan_pipe_dffe_14;
reg nan_pipe_dffe_15;
reg nan_pipe_dffe_16;
reg nan_pipe_dffe_17;
reg nan_pipe_dffe_18;
reg nan_pipe_dffe_19;
reg nan_pipe_dffe_2;
reg nan_pipe_dffe_20;
reg nan_pipe_dffe_21;
reg nan_pipe_dffe_22;
reg nan_pipe_dffe_3;
reg nan_pipe_dffe_4;
reg nan_pipe_dffe_5;
reg nan_pipe_dffe_6;
reg nan_pipe_dffe_7;
reg nan_pipe_dffe_8;
reg nan_pipe_dffe_9;
reg over_under_dffe_0;
reg over_under_dffe_1;
reg over_under_dffe_10;
reg over_under_dffe_11;
reg over_under_dffe_12;
reg over_under_dffe_13;
reg over_under_dffe_14;
reg over_under_dffe_15;
reg over_under_dffe_16;
reg over_under_dffe_17;
reg over_under_dffe_18;
reg over_under_dffe_19;
reg over_under_dffe_2;
reg over_under_dffe_20;
reg over_under_dffe_3;
reg over_under_dffe_4;
reg over_under_dffe_5;
reg over_under_dffe_6;
reg over_under_dffe_7;
reg over_under_dffe_8;
reg over_under_dffe_9;
reg [33:0] q_partial_perf_dffe_0;
reg [33:0] q_partial_perf_dffe_1;
reg [33:0] q_partial_perf_dffe_2;
reg [33:0] q_partial_perf_dffe_3;
reg [16:0] quotient_j_dffe;
reg [16:0] quotient_k_dffe_0;
reg [30:0] quotient_k_dffe_1;
reg [44:0] quotient_k_dffe_2;
reg [16:0] quotient_k_dffe_perf_0;
reg [16:0] quotient_k_dffe_perf_1;
reg [44:0] quotient_k_dffe_perf_10;
reg [44:0] quotient_k_dffe_perf_11;
reg [16:0] quotient_k_dffe_perf_2;
reg [16:0] quotient_k_dffe_perf_3;
reg [30:0] quotient_k_dffe_perf_4;
reg [30:0] quotient_k_dffe_perf_5;
reg [30:0] quotient_k_dffe_perf_6;
reg [30:0] quotient_k_dffe_perf_7;
reg [44:0] quotient_k_dffe_perf_8;
reg [44:0] quotient_k_dffe_perf_9;
reg [78:0] remainder_j_dffe_0;
reg [78:0] remainder_j_dffe_1;
reg [78:0] remainder_j_dffe_2;
reg [78:0] remainder_j_dffe_3;
reg [78:0] remainder_j_dffe_4;
reg [78:0] remainder_j_dffe_5;
reg [78:0] remainder_j_dffe_perf_0;
reg [78:0] remainder_j_dffe_perf_1;
reg [78:0] remainder_j_dffe_perf_2;
reg [78:0] remainder_j_dffe_perf_3;
reg [78:0] remainder_j_dffe_perf_4;
reg [78:0] remainder_j_dffe_perf_5;
reg [78:0] remainder_j_dffe_perf_6;
reg [78:0] remainder_j_dffe_perf_7;
reg [78:0] remainder_j_dffe_perf_8;
reg sign_pipe_dffe_0;
reg sign_pipe_dffe_1;
reg sign_pipe_dffe_10;
reg sign_pipe_dffe_11;
reg sign_pipe_dffe_12;
reg sign_pipe_dffe_13;
reg sign_pipe_dffe_14;
reg sign_pipe_dffe_15;
reg sign_pipe_dffe_16;
reg sign_pipe_dffe_17;
reg sign_pipe_dffe_18;
reg sign_pipe_dffe_19;
reg sign_pipe_dffe_2;
reg sign_pipe_dffe_20;
reg sign_pipe_dffe_21;
reg sign_pipe_dffe_22;
reg sign_pipe_dffe_23;
reg sign_pipe_dffe_3;
reg sign_pipe_dffe_4;
reg sign_pipe_dffe_5;
reg sign_pipe_dffe_6;
reg sign_pipe_dffe_7;
reg sign_pipe_dffe_8;
reg sign_pipe_dffe_9;
wire wire_bias_addition_overflow;
wire [11:0] wire_bias_addition_result;
wire [11:0] wire_exp_sub_result;
wire [30:0] wire_quotient_accumulate_0_result;
wire [44:0] wire_quotient_accumulate_1_result;
wire [58:0] wire_quotient_process_result;
wire [78:0] wire_remainder_sub_0_result;
wire [78:0] wire_remainder_sub_1_result;
wire [78:0] wire_remainder_sub_2_result;
wire wire_cmpr2_alb;
wire [63:0] wire_a1_prod_result;
wire [62:0] wire_b1_prod_result;
wire [33:0] wire_q_partial_0_result;
wire [33:0] wire_q_partial_1_result;
wire [33:0] wire_q_partial_2_result;
wire [33:0] wire_q_partial_3_result;
wire [79:0] wire_remainder_mult_0_result;
wire [79:0] wire_remainder_mult_1_result;
wire [79:0] wire_remainder_mult_2_result;
wire [10:0]wire_exp_result_muxa_dataout;
wire [53:0]wire_man_a_adjusteda_dataout;
wire [51:0]wire_man_result_muxa_dataout;
wire [11:0]wire_select_bias_2a_dataout;
wire [11:0]wire_select_biasa_dataout;
wire a_is_infinity_w;
wire a_is_nan_w;
wire a_zero_b_not;
wire [188:0] b1_dffe_w;
wire b_is_infinity_w;
wire b_is_nan_w;
wire bias_addition_overf_w;
wire [10:0] bias_addition_w;
wire both_exp_zeros;
wire [8:0] e0_dffe1_wo;
wire [8:0] e0_w;
wire [118:0] e1_w;
wire [10:0] exp_a_all_one_w;
wire [10:0] exp_a_not_zero_w;
wire [10:0] exp_add_output_all_one;
wire [10:0] exp_add_output_not_zero;
wire [10:0] exp_b_all_one_w;
wire [10:0] exp_b_not_zero_w;
wire [10:0] exp_result_mux_out;
wire exp_result_mux_sel_w;
wire [10:0] exp_result_w;
wire exp_sign_w;
wire [11:0] exp_sub_a_w;
wire [11:0] exp_sub_b_w;
wire [11:0] exp_sub_w;
wire frac_a_smaller_dffe1_wi;
wire frac_a_smaller_dffe1_wo;
wire frac_a_smaller_w;
wire guard_bit;
wire [53:0] man_a_adjusted_w;
wire [51:0] man_a_dffe1_wi;
wire [51:0] man_a_dffe1_wo;
wire [51:0] man_a_not_zero_w;
wire [52:0] man_b_adjusted_w;
wire [51:0] man_b_dffe1_wi;
wire [51:0] man_b_dffe1_wo;
wire [51:0] man_b_not_zero_w;
wire [51:0] man_result_dffe_wi;
wire [51:0] man_result_dffe_wo;
wire man_result_mux_select;
wire [51:0] man_result_w;
wire [51:0] man_zeros_w;
wire [10:0] overflow_ones_w;
wire overflow_underflow;
wire overflow_w;
wire [235:0] quotient_accumulate_w;
wire quotient_process_cin_w;
wire [315:0] remainder_j_w;
wire round_bit;
wire [11:0] select_bias_out_2_w;
wire [11:0] select_bias_out_w;
wire [3:0] sticky_bits;
wire underflow_w;
wire [10:0] underflow_zeros_w;
wire [11:0] value_add_one_w;
wire [11:0] value_normal_w;
wire [11:0] value_zero_w;
altsyncram altsyncram3
(
.address_a(datab[51:43]),
.clock0(clock),
.clocken0(clk_en),
.eccstatus(),
.q_a(wire_altsyncram3_q_a),
.q_b()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({9{1'b1}}),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram3.init_file = "acl_fp_div_s5_double.hex",
altsyncram3.operation_mode = "ROM",
altsyncram3.width_a = 9,
altsyncram3.widthad_a = 9,
altsyncram3.intended_device_family = "Stratix V",
altsyncram3.lpm_type = "altsyncram";
// synopsys translate_off
initial
a_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_0 <= a_is_infinity_w;
// synopsys translate_off
initial
a_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
// synopsys translate_off
initial
a_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_10 <= a_is_infinity_dffe_9;
// synopsys translate_off
initial
a_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_11 <= a_is_infinity_dffe_10;
// synopsys translate_off
initial
a_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_12 <= a_is_infinity_dffe_11;
// synopsys translate_off
initial
a_is_infinity_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_13 <= a_is_infinity_dffe_12;
// synopsys translate_off
initial
a_is_infinity_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_14 <= a_is_infinity_dffe_13;
// synopsys translate_off
initial
a_is_infinity_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_15 <= a_is_infinity_dffe_14;
// synopsys translate_off
initial
a_is_infinity_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_16 <= a_is_infinity_dffe_15;
// synopsys translate_off
initial
a_is_infinity_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_17 <= a_is_infinity_dffe_16;
// synopsys translate_off
initial
a_is_infinity_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_18 <= a_is_infinity_dffe_17;
// synopsys translate_off
initial
a_is_infinity_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_19 <= a_is_infinity_dffe_18;
// synopsys translate_off
initial
a_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
// synopsys translate_off
initial
a_is_infinity_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_20 <= a_is_infinity_dffe_19;
// synopsys translate_off
initial
a_is_infinity_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_21 <= a_is_infinity_dffe_20;
// synopsys translate_off
initial
a_is_infinity_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_22 <= a_is_infinity_dffe_21;
// synopsys translate_off
initial
a_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
// synopsys translate_off
initial
a_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
// synopsys translate_off
initial
a_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_5 <= a_is_infinity_dffe_4;
// synopsys translate_off
initial
a_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_6 <= a_is_infinity_dffe_5;
// synopsys translate_off
initial
a_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_7 <= a_is_infinity_dffe_6;
// synopsys translate_off
initial
a_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_8 <= a_is_infinity_dffe_7;
// synopsys translate_off
initial
a_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_9 <= a_is_infinity_dffe_8;
// synopsys translate_off
initial
a_zero_b_not_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_0 <= a_zero_b_not;
// synopsys translate_off
initial
a_zero_b_not_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
// synopsys translate_off
initial
a_zero_b_not_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_10 <= a_zero_b_not_dffe_9;
// synopsys translate_off
initial
a_zero_b_not_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_11 <= a_zero_b_not_dffe_10;
// synopsys translate_off
initial
a_zero_b_not_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_12 <= a_zero_b_not_dffe_11;
// synopsys translate_off
initial
a_zero_b_not_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_13 <= a_zero_b_not_dffe_12;
// synopsys translate_off
initial
a_zero_b_not_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_14 <= a_zero_b_not_dffe_13;
// synopsys translate_off
initial
a_zero_b_not_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_15 <= a_zero_b_not_dffe_14;
// synopsys translate_off
initial
a_zero_b_not_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_16 <= a_zero_b_not_dffe_15;
// synopsys translate_off
initial
a_zero_b_not_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_17 <= a_zero_b_not_dffe_16;
// synopsys translate_off
initial
a_zero_b_not_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_18 <= a_zero_b_not_dffe_17;
// synopsys translate_off
initial
a_zero_b_not_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_19 <= a_zero_b_not_dffe_18;
// synopsys translate_off
initial
a_zero_b_not_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
// synopsys translate_off
initial
a_zero_b_not_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_20 <= a_zero_b_not_dffe_19;
// synopsys translate_off
initial
a_zero_b_not_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_21 <= a_zero_b_not_dffe_20;
// synopsys translate_off
initial
a_zero_b_not_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_22 <= a_zero_b_not_dffe_21;
// synopsys translate_off
initial
a_zero_b_not_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
// synopsys translate_off
initial
a_zero_b_not_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
// synopsys translate_off
initial
a_zero_b_not_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_5 <= a_zero_b_not_dffe_4;
// synopsys translate_off
initial
a_zero_b_not_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_6 <= a_zero_b_not_dffe_5;
// synopsys translate_off
initial
a_zero_b_not_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_7 <= a_zero_b_not_dffe_6;
// synopsys translate_off
initial
a_zero_b_not_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_8 <= a_zero_b_not_dffe_7;
// synopsys translate_off
initial
a_zero_b_not_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_9 <= a_zero_b_not_dffe_8;
// synopsys translate_off
initial
b1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_0 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_0 <= wire_b1_prod_result;
// synopsys translate_off
initial
b1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_1 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_1 <= b1_dffe_0;
// synopsys translate_off
initial
b1_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_10 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_10 <= b1_dffe_9;
// synopsys translate_off
initial
b1_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_11 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_11 <= b1_dffe_10;
// synopsys translate_off
initial
b1_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_12 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_12 <= b1_dffe_11;
// synopsys translate_off
initial
b1_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_13 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_13 <= b1_dffe_12;
// synopsys translate_off
initial
b1_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_2 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_2 <= b1_dffe_1;
// synopsys translate_off
initial
b1_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_3 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_3 <= b1_dffe_2;
// synopsys translate_off
initial
b1_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_4 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_4 <= b1_dffe_3;
// synopsys translate_off
initial
b1_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_5 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_5 <= b1_dffe_4;
// synopsys translate_off
initial
b1_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_6 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_6 <= b1_dffe_5;
// synopsys translate_off
initial
b1_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_7 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_7 <= b1_dffe_6;
// synopsys translate_off
initial
b1_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_8 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_8 <= b1_dffe_7;
// synopsys translate_off
initial
b1_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_9 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_9 <= b1_dffe_8;
// synopsys translate_off
initial
b_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_0 <= b_is_infinity_w;
// synopsys translate_off
initial
b_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_10 <= b_is_infinity_dffe_9;
// synopsys translate_off
initial
b_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_11 <= b_is_infinity_dffe_10;
// synopsys translate_off
initial
b_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_12 <= b_is_infinity_dffe_11;
// synopsys translate_off
initial
b_is_infinity_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_13 <= b_is_infinity_dffe_12;
// synopsys translate_off
initial
b_is_infinity_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_14 <= b_is_infinity_dffe_13;
// synopsys translate_off
initial
b_is_infinity_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_15 <= b_is_infinity_dffe_14;
// synopsys translate_off
initial
b_is_infinity_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_16 <= b_is_infinity_dffe_15;
// synopsys translate_off
initial
b_is_infinity_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_17 <= b_is_infinity_dffe_16;
// synopsys translate_off
initial
b_is_infinity_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_18 <= b_is_infinity_dffe_17;
// synopsys translate_off
initial
b_is_infinity_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_19 <= b_is_infinity_dffe_18;
// synopsys translate_off
initial
b_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
// synopsys translate_off
initial
b_is_infinity_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_20 <= b_is_infinity_dffe_19;
// synopsys translate_off
initial
b_is_infinity_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_21 <= b_is_infinity_dffe_20;
// synopsys translate_off
initial
b_is_infinity_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_22 <= b_is_infinity_dffe_21;
// synopsys translate_off
initial
b_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
// synopsys translate_off
initial
b_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
// synopsys translate_off
initial
b_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_5 <= b_is_infinity_dffe_4;
// synopsys translate_off
initial
b_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_6 <= b_is_infinity_dffe_5;
// synopsys translate_off
initial
b_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_7 <= b_is_infinity_dffe_6;
// synopsys translate_off
initial
b_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_8 <= b_is_infinity_dffe_7;
// synopsys translate_off
initial
b_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_9 <= b_is_infinity_dffe_8;
// synopsys translate_off
initial
both_exp_zeros_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_exp_zeros_dffe <= 1'b0;
else if (clk_en == 1'b1) both_exp_zeros_dffe <= ((~ exp_b_not_zero_w[10]) & (~ exp_a_not_zero_w[10]));
// synopsys translate_off
initial
divbyzero_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_0 <= ((((~ exp_b_not_zero_w[10]) & (~ a_is_nan_w)) & exp_a_not_zero_w[10]) & (~ a_is_infinity_w));
// synopsys translate_off
initial
divbyzero_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
// synopsys translate_off
initial
divbyzero_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_10 <= divbyzero_pipe_dffe_9;
// synopsys translate_off
initial
divbyzero_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_11 <= divbyzero_pipe_dffe_10;
// synopsys translate_off
initial
divbyzero_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_12 <= divbyzero_pipe_dffe_11;
// synopsys translate_off
initial
divbyzero_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_13 <= divbyzero_pipe_dffe_12;
// synopsys translate_off
initial
divbyzero_pipe_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_14 <= divbyzero_pipe_dffe_13;
// synopsys translate_off
initial
divbyzero_pipe_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_15 <= divbyzero_pipe_dffe_14;
// synopsys translate_off
initial
divbyzero_pipe_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_16 <= divbyzero_pipe_dffe_15;
// synopsys translate_off
initial
divbyzero_pipe_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_17 <= divbyzero_pipe_dffe_16;
// synopsys translate_off
initial
divbyzero_pipe_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_18 <= divbyzero_pipe_dffe_17;
// synopsys translate_off
initial
divbyzero_pipe_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_19 <= divbyzero_pipe_dffe_18;
// synopsys translate_off
initial
divbyzero_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
// synopsys translate_off
initial
divbyzero_pipe_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_20 <= divbyzero_pipe_dffe_19;
// synopsys translate_off
initial
divbyzero_pipe_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_21 <= divbyzero_pipe_dffe_20;
// synopsys translate_off
initial
divbyzero_pipe_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_22 <= divbyzero_pipe_dffe_21;
// synopsys translate_off
initial
divbyzero_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
// synopsys translate_off
initial
divbyzero_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
// synopsys translate_off
initial
divbyzero_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_5 <= divbyzero_pipe_dffe_4;
// synopsys translate_off
initial
divbyzero_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_6 <= divbyzero_pipe_dffe_5;
// synopsys translate_off
initial
divbyzero_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_7 <= divbyzero_pipe_dffe_6;
// synopsys translate_off
initial
divbyzero_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_8 <= divbyzero_pipe_dffe_7;
// synopsys translate_off
initial
divbyzero_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_9 <= divbyzero_pipe_dffe_8;
// synopsys translate_off
initial
e1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_0 <= e1_w[16:0];
// synopsys translate_off
initial
e1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_1 <= e1_w[33:17];
// synopsys translate_off
initial
e1_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_2 <= e1_w[50:34];
// synopsys translate_off
initial
e1_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_3 <= e1_w[67:51];
// synopsys translate_off
initial
e1_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_4 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_4 <= e1_w[84:68];
// synopsys translate_off
initial
e1_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_5 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_5 <= e1_w[101:85];
// synopsys translate_off
initial
e1_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_0 <= e1_dffe_0;
// synopsys translate_off
initial
e1_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_1 <= e1_dffe_perf_0;
// synopsys translate_off
initial
e1_dffe_perf_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_10 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_10 <= e1_dffe_perf_9;
// synopsys translate_off
initial
e1_dffe_perf_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_11 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_11 <= e1_dffe_perf_10;
// synopsys translate_off
initial
e1_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_2 <= e1_dffe_perf_1;
// synopsys translate_off
initial
e1_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_3 <= e1_dffe_perf_2;
// synopsys translate_off
initial
e1_dffe_perf_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_4 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_4 <= e1_dffe_2;
// synopsys translate_off
initial
e1_dffe_perf_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_5 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_5 <= e1_dffe_perf_4;
// synopsys translate_off
initial
e1_dffe_perf_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_6 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_6 <= e1_dffe_perf_5;
// synopsys translate_off
initial
e1_dffe_perf_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_7 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_7 <= e1_dffe_perf_6;
// synopsys translate_off
initial
e1_dffe_perf_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_8 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_8 <= e1_dffe_4;
// synopsys translate_off
initial
e1_dffe_perf_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_9 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_9 <= e1_dffe_perf_8;
// synopsys translate_off
initial
exp_result_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_0 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_0 <= exp_result_mux_out;
// synopsys translate_off
initial
exp_result_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_1 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_1 <= exp_result_dffe_0;
// synopsys translate_off
initial
exp_result_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_10 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_10 <= exp_result_dffe_9;
// synopsys translate_off
initial
exp_result_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_11 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_11 <= exp_result_dffe_10;
// synopsys translate_off
initial
exp_result_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_12 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_12 <= exp_result_dffe_11;
// synopsys translate_off
initial
exp_result_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_13 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_13 <= exp_result_dffe_12;
// synopsys translate_off
initial
exp_result_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_14 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_14 <= exp_result_dffe_13;
// synopsys translate_off
initial
exp_result_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_15 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_15 <= exp_result_dffe_14;
// synopsys translate_off
initial
exp_result_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_16 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_16 <= exp_result_dffe_15;
// synopsys translate_off
initial
exp_result_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_17 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_17 <= exp_result_dffe_16;
// synopsys translate_off
initial
exp_result_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_18 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_18 <= exp_result_dffe_17;
// synopsys translate_off
initial
exp_result_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_19 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_19 <= exp_result_dffe_18;
// synopsys translate_off
initial
exp_result_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_2 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_2 <= exp_result_dffe_1;
// synopsys translate_off
initial
exp_result_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_20 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_20 <= exp_result_dffe_19;
// synopsys translate_off
initial
exp_result_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_21 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_21 <= exp_result_dffe_20;
// synopsys translate_off
initial
exp_result_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_3 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_3 <= exp_result_dffe_2;
// synopsys translate_off
initial
exp_result_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_4 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_4 <= exp_result_dffe_3;
// synopsys translate_off
initial
exp_result_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_5 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_5 <= exp_result_dffe_4;
// synopsys translate_off
initial
exp_result_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_6 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_6 <= exp_result_dffe_5;
// synopsys translate_off
initial
exp_result_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_7 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_7 <= exp_result_dffe_6;
// synopsys translate_off
initial
exp_result_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_8 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_8 <= exp_result_dffe_7;
// synopsys translate_off
initial
exp_result_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_9 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_9 <= exp_result_dffe_8;
// synopsys translate_off
initial
frac_a_smaller_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) frac_a_smaller_dffe1 <= 1'b0;
else if (clk_en == 1'b1) frac_a_smaller_dffe1 <= frac_a_smaller_dffe1_wi;
// synopsys translate_off
initial
man_a_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_dffe1_dffe1 <= 52'b0;
else if (clk_en == 1'b1) man_a_dffe1_dffe1 <= man_a_dffe1_wi;
// synopsys translate_off
initial
man_b_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_dffe1_dffe1 <= 52'b0;
else if (clk_en == 1'b1) man_b_dffe1_dffe1 <= man_b_dffe1_wi;
// synopsys translate_off
initial
man_result_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_dffe <= 52'b0;
else if (clk_en == 1'b1) man_result_dffe <= man_result_dffe_wi;
// synopsys translate_off
initial
nan_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_0 <= (((a_is_nan_w | b_is_nan_w) | (a_is_infinity_w & b_is_infinity_w)) | ((~ exp_a_not_zero_w[10]) & (~ exp_b_not_zero_w[10])));
// synopsys translate_off
initial
nan_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_1 <= nan_pipe_dffe_0;
// synopsys translate_off
initial
nan_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_10 <= nan_pipe_dffe_9;
// synopsys translate_off
initial
nan_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_11 <= nan_pipe_dffe_10;
// synopsys translate_off
initial
nan_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_12 <= nan_pipe_dffe_11;
// synopsys translate_off
initial
nan_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_13 <= nan_pipe_dffe_12;
// synopsys translate_off
initial
nan_pipe_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_14 <= nan_pipe_dffe_13;
// synopsys translate_off
initial
nan_pipe_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_15 <= nan_pipe_dffe_14;
// synopsys translate_off
initial
nan_pipe_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_16 <= nan_pipe_dffe_15;
// synopsys translate_off
initial
nan_pipe_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_17 <= nan_pipe_dffe_16;
// synopsys translate_off
initial
nan_pipe_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_18 <= nan_pipe_dffe_17;
// synopsys translate_off
initial
nan_pipe_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_19 <= nan_pipe_dffe_18;
// synopsys translate_off
initial
nan_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_2 <= nan_pipe_dffe_1;
// synopsys translate_off
initial
nan_pipe_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_20 <= nan_pipe_dffe_19;
// synopsys translate_off
initial
nan_pipe_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_21 <= nan_pipe_dffe_20;
// synopsys translate_off
initial
nan_pipe_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_22 <= nan_pipe_dffe_21;
// synopsys translate_off
initial
nan_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_3 <= nan_pipe_dffe_2;
// synopsys translate_off
initial
nan_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_4 <= nan_pipe_dffe_3;
// synopsys translate_off
initial
nan_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_5 <= nan_pipe_dffe_4;
// synopsys translate_off
initial
nan_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_6 <= nan_pipe_dffe_5;
// synopsys translate_off
initial
nan_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_7 <= nan_pipe_dffe_6;
// synopsys translate_off
initial
nan_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_8 <= nan_pipe_dffe_7;
// synopsys translate_off
initial
nan_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_9 <= nan_pipe_dffe_8;
// synopsys translate_off
initial
over_under_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_0 <= overflow_underflow;
// synopsys translate_off
initial
over_under_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_1 <= over_under_dffe_0;
// synopsys translate_off
initial
over_under_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_10 <= over_under_dffe_9;
// synopsys translate_off
initial
over_under_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_11 <= over_under_dffe_10;
// synopsys translate_off
initial
over_under_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_12 <= over_under_dffe_11;
// synopsys translate_off
initial
over_under_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_13 <= over_under_dffe_12;
// synopsys translate_off
initial
over_under_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_14 <= over_under_dffe_13;
// synopsys translate_off
initial
over_under_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_15 <= over_under_dffe_14;
// synopsys translate_off
initial
over_under_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_16 <= over_under_dffe_15;
// synopsys translate_off
initial
over_under_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_17 <= over_under_dffe_16;
// synopsys translate_off
initial
over_under_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_18 <= over_under_dffe_17;
// synopsys translate_off
initial
over_under_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_19 <= over_under_dffe_18;
// synopsys translate_off
initial
over_under_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_2 <= over_under_dffe_1;
// synopsys translate_off
initial
over_under_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_20 <= over_under_dffe_19;
// synopsys translate_off
initial
over_under_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_3 <= over_under_dffe_2;
// synopsys translate_off
initial
over_under_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_4 <= over_under_dffe_3;
// synopsys translate_off
initial
over_under_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_5 <= over_under_dffe_4;
// synopsys translate_off
initial
over_under_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_6 <= over_under_dffe_5;
// synopsys translate_off
initial
over_under_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_7 <= over_under_dffe_6;
// synopsys translate_off
initial
over_under_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_8 <= over_under_dffe_7;
// synopsys translate_off
initial
over_under_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_9 <= over_under_dffe_8;
// synopsys translate_off
initial
q_partial_perf_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_0 <= wire_q_partial_0_result;
// synopsys translate_off
initial
q_partial_perf_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_1 <= wire_q_partial_1_result;
// synopsys translate_off
initial
q_partial_perf_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_2 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_2 <= wire_q_partial_2_result;
// synopsys translate_off
initial
q_partial_perf_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_3 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_3 <= wire_q_partial_3_result;
// synopsys translate_off
initial
quotient_j_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_j_dffe <= 17'b0;
else if (clk_en == 1'b1) quotient_j_dffe <= q_partial_perf_dffe_0[32:16];
// synopsys translate_off
initial
quotient_k_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_0 <= quotient_k_dffe_perf_3;
// synopsys translate_off
initial
quotient_k_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_1 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_1 <= quotient_k_dffe_perf_7;
// synopsys translate_off
initial
quotient_k_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_2 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_2 <= quotient_k_dffe_perf_11;
// synopsys translate_off
initial
quotient_k_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_0 <= quotient_accumulate_w[58:42];
// synopsys translate_off
initial
quotient_k_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_1 <= quotient_k_dffe_perf_0;
// synopsys translate_off
initial
quotient_k_dffe_perf_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_10 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_10 <= quotient_k_dffe_perf_9;
// synopsys translate_off
initial
quotient_k_dffe_perf_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_11 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_11 <= quotient_k_dffe_perf_10;
// synopsys translate_off
initial
quotient_k_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_2 <= quotient_k_dffe_perf_1;
// synopsys translate_off
initial
quotient_k_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_3 <= quotient_k_dffe_perf_2;
// synopsys translate_off
initial
quotient_k_dffe_perf_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_4 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_4 <= wire_quotient_accumulate_0_result;
// synopsys translate_off
initial
quotient_k_dffe_perf_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_5 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_5 <= quotient_k_dffe_perf_4;
// synopsys translate_off
initial
quotient_k_dffe_perf_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_6 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_6 <= quotient_k_dffe_perf_5;
// synopsys translate_off
initial
quotient_k_dffe_perf_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_7 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_7 <= quotient_k_dffe_perf_6;
// synopsys translate_off
initial
quotient_k_dffe_perf_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_8 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_8 <= wire_quotient_accumulate_1_result;
// synopsys translate_off
initial
quotient_k_dffe_perf_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_9 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_9 <= quotient_k_dffe_perf_8;
// synopsys translate_off
initial
remainder_j_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_0 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_0 <= remainder_j_w[78:0];
// synopsys translate_off
initial
remainder_j_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_1 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_1 <= remainder_j_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_2 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_2 <= remainder_j_w[157:79];
// synopsys translate_off
initial
remainder_j_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_3 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_3 <= remainder_j_dffe_perf_5;
// synopsys translate_off
initial
remainder_j_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_4 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_4 <= remainder_j_w[236:158];
// synopsys translate_off
initial
remainder_j_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_5 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_5 <= remainder_j_dffe_perf_8;
// synopsys translate_off
initial
remainder_j_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_0 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_0 <= remainder_j_dffe_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_1 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_1 <= remainder_j_dffe_perf_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_2 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_2 <= remainder_j_dffe_perf_1;
// synopsys translate_off
initial
remainder_j_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_3 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_3 <= remainder_j_dffe_2;
// synopsys translate_off
initial
remainder_j_dffe_perf_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_4 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_4 <= remainder_j_dffe_perf_3;
// synopsys translate_off
initial
remainder_j_dffe_perf_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_5 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_5 <= remainder_j_dffe_perf_4;
// synopsys translate_off
initial
remainder_j_dffe_perf_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_6 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_6 <= remainder_j_dffe_4;
// synopsys translate_off
initial
remainder_j_dffe_perf_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_7 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_7 <= remainder_j_dffe_perf_6;
// synopsys translate_off
initial
remainder_j_dffe_perf_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_8 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_8 <= remainder_j_dffe_perf_7;
// synopsys translate_off
initial
sign_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_0 <= (dataa[63] ^ datab[63]);
// synopsys translate_off
initial
sign_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_1 <= sign_pipe_dffe_0;
// synopsys translate_off
initial
sign_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_10 <= sign_pipe_dffe_9;
// synopsys translate_off
initial
sign_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_11 <= sign_pipe_dffe_10;
// synopsys translate_off
initial
sign_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_12 <= sign_pipe_dffe_11;
// synopsys translate_off
initial
sign_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_13 <= sign_pipe_dffe_12;
// synopsys translate_off
initial
sign_pipe_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_14 <= sign_pipe_dffe_13;
// synopsys translate_off
initial
sign_pipe_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_15 <= sign_pipe_dffe_14;
// synopsys translate_off
initial
sign_pipe_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_16 <= sign_pipe_dffe_15;
// synopsys translate_off
initial
sign_pipe_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_17 <= sign_pipe_dffe_16;
// synopsys translate_off
initial
sign_pipe_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_18 <= sign_pipe_dffe_17;
// synopsys translate_off
initial
sign_pipe_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_19 <= sign_pipe_dffe_18;
// synopsys translate_off
initial
sign_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_2 <= sign_pipe_dffe_1;
// synopsys translate_off
initial
sign_pipe_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_20 <= sign_pipe_dffe_19;
// synopsys translate_off
initial
sign_pipe_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_21 <= sign_pipe_dffe_20;
// synopsys translate_off
initial
sign_pipe_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_22 <= sign_pipe_dffe_21;
// synopsys translate_off
initial
sign_pipe_dffe_23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_23 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_23 <= sign_pipe_dffe_22;
// synopsys translate_off
initial
sign_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_3 <= sign_pipe_dffe_2;
// synopsys translate_off
initial
sign_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_4 <= sign_pipe_dffe_3;
// synopsys translate_off
initial
sign_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_5 <= sign_pipe_dffe_4;
// synopsys translate_off
initial
sign_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_6 <= sign_pipe_dffe_5;
// synopsys translate_off
initial
sign_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_7 <= sign_pipe_dffe_6;
// synopsys translate_off
initial
sign_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_8 <= sign_pipe_dffe_7;
// synopsys translate_off
initial
sign_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_9 <= sign_pipe_dffe_8;
lpm_add_sub bias_addition
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_w),
.datab(select_bias_out_2_w),
.overflow(wire_bias_addition_overflow),
.result(wire_bias_addition_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
bias_addition.lpm_direction = "ADD",
bias_addition.lpm_pipeline = 1,
bias_addition.lpm_representation = "SIGNED",
bias_addition.lpm_width = 12,
bias_addition.lpm_type = "lpm_add_sub";
lpm_add_sub exp_sub
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_a_w),
.datab(exp_sub_b_w),
.overflow(),
.result(wire_exp_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_sub.lpm_direction = "SUB",
exp_sub.lpm_pipeline = 1,
exp_sub.lpm_representation = "SIGNED",
exp_sub.lpm_width = 12,
exp_sub.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_accumulate_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[117:101], {14{1'b0}}}),
.datab({{14{1'b0}}, q_partial_perf_dffe_1[32:16]}),
.overflow(),
.result(wire_quotient_accumulate_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_accumulate_0.lpm_direction = "ADD",
quotient_accumulate_0.lpm_pipeline = 1,
quotient_accumulate_0.lpm_representation = "UNSIGNED",
quotient_accumulate_0.lpm_width = 31,
quotient_accumulate_0.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_accumulate_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[176:146], {14{1'b0}}}),
.datab({{28{1'b0}}, q_partial_perf_dffe_2[32:16]}),
.overflow(),
.result(wire_quotient_accumulate_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_accumulate_1.lpm_direction = "ADD",
quotient_accumulate_1.lpm_pipeline = 1,
quotient_accumulate_1.lpm_representation = "UNSIGNED",
quotient_accumulate_1.lpm_width = 45,
quotient_accumulate_1.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_process
(
.cin(quotient_process_cin_w),
.cout(),
.dataa({quotient_accumulate_w[235:191], {14{1'b0}}}),
.datab({{42{1'b0}}, q_partial_perf_dffe_3[32:21], {5{1'b1}}}),
.overflow(),
.result(wire_quotient_process_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_process.lpm_direction = "ADD",
quotient_process.lpm_representation = "UNSIGNED",
quotient_process.lpm_width = 59,
quotient_process.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_1[78:15], {15{1'b0}}}),
.datab(wire_remainder_mult_0_result[78:0]),
.overflow(),
.result(wire_remainder_sub_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_0.lpm_direction = "SUB",
remainder_sub_0.lpm_pipeline = 1,
remainder_sub_0.lpm_representation = "UNSIGNED",
remainder_sub_0.lpm_width = 79,
remainder_sub_0.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_3[78:15], {15{1'b0}}}),
.datab(wire_remainder_mult_1_result[78:0]),
.overflow(),
.result(wire_remainder_sub_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_1.lpm_direction = "SUB",
remainder_sub_1.lpm_pipeline = 1,
remainder_sub_1.lpm_representation = "UNSIGNED",
remainder_sub_1.lpm_width = 79,
remainder_sub_1.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_5[78:15], {15{1'b0}}}),
.datab(wire_remainder_mult_2_result[78:0]),
.overflow(),
.result(wire_remainder_sub_2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_2.lpm_direction = "SUB",
remainder_sub_2.lpm_pipeline = 1,
remainder_sub_2.lpm_representation = "UNSIGNED",
remainder_sub_2.lpm_width = 79,
remainder_sub_2.lpm_type = "lpm_add_sub";
lpm_compare cmpr2
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr2_alb),
.aleb(),
.aneb(),
.dataa(dataa[51:0]),
.datab(datab[51:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 52,
cmpr2.lpm_type = "lpm_compare";
lpm_mult a1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_a_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_a1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
a1_prod.lpm_pipeline = 2,
a1_prod.lpm_representation = "UNSIGNED",
a1_prod.lpm_widtha = 54,
a1_prod.lpm_widthb = 10,
a1_prod.lpm_widthp = 64,
a1_prod.lpm_type = "lpm_mult",
a1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult b1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_b_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_b1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
b1_prod.lpm_pipeline = 2,
b1_prod.lpm_representation = "UNSIGNED",
b1_prod.lpm_widtha = 53,
b1_prod.lpm_widthb = 10,
b1_prod.lpm_widthp = 63,
b1_prod.lpm_type = "lpm_mult",
b1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[78:62]),
.datab(e1_w[16:0]),
.result(wire_q_partial_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_0.lpm_pipeline = 1,
q_partial_0.lpm_representation = "UNSIGNED",
q_partial_0.lpm_widtha = 17,
q_partial_0.lpm_widthb = 17,
q_partial_0.lpm_widthp = 34,
q_partial_0.lpm_type = "lpm_mult",
q_partial_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[157:141]),
.datab(e1_w[50:34]),
.result(wire_q_partial_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_1.lpm_pipeline = 1,
q_partial_1.lpm_representation = "UNSIGNED",
q_partial_1.lpm_widtha = 17,
q_partial_1.lpm_widthb = 17,
q_partial_1.lpm_widthp = 34,
q_partial_1.lpm_type = "lpm_mult",
q_partial_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[236:220]),
.datab(e1_w[84:68]),
.result(wire_q_partial_2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_2.lpm_pipeline = 1,
q_partial_2.lpm_representation = "UNSIGNED",
q_partial_2.lpm_widtha = 17,
q_partial_2.lpm_widthb = 17,
q_partial_2.lpm_widthp = 34,
q_partial_2.lpm_type = "lpm_mult",
q_partial_2.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[315:299]),
.datab(e1_w[118:102]),
.result(wire_q_partial_3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_3.lpm_pipeline = 1,
q_partial_3.lpm_representation = "UNSIGNED",
q_partial_3.lpm_widtha = 17,
q_partial_3.lpm_widthb = 17,
q_partial_3.lpm_widthp = 34,
q_partial_3.lpm_type = "lpm_mult",
q_partial_3.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[62:0]),
.datab(q_partial_perf_dffe_0[32:16]),
.result(wire_remainder_mult_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_0.lpm_pipeline = 3,
remainder_mult_0.lpm_representation = "UNSIGNED",
remainder_mult_0.lpm_widtha = 63,
remainder_mult_0.lpm_widthb = 17,
remainder_mult_0.lpm_widthp = 80,
remainder_mult_0.lpm_type = "lpm_mult",
remainder_mult_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[125:63]),
.datab(q_partial_perf_dffe_1[32:16]),
.result(wire_remainder_mult_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_1.lpm_pipeline = 3,
remainder_mult_1.lpm_representation = "UNSIGNED",
remainder_mult_1.lpm_widtha = 63,
remainder_mult_1.lpm_widthb = 17,
remainder_mult_1.lpm_widthp = 80,
remainder_mult_1.lpm_type = "lpm_mult",
remainder_mult_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[188:126]),
.datab(q_partial_perf_dffe_2[32:16]),
.result(wire_remainder_mult_2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_2.lpm_pipeline = 3,
remainder_mult_2.lpm_representation = "UNSIGNED",
remainder_mult_2.lpm_widtha = 63,
remainder_mult_2.lpm_widthb = 17,
remainder_mult_2.lpm_widthp = 80,
remainder_mult_2.lpm_type = "lpm_mult",
remainder_mult_2.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign wire_exp_result_muxa_dataout = (exp_result_mux_sel_w === 1'b1) ? underflow_zeros_w : exp_result_w;
assign wire_man_a_adjusteda_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? {1'b1, man_a_dffe1_wo, 1'b0} : {1'b0, 1'b1, man_a_dffe1_wo};
assign wire_man_result_muxa_dataout = (man_result_mux_select === 1'b1) ? {nan_pipe_dffe_22, man_zeros_w[50:0]} : wire_quotient_process_result[56:5];
assign wire_select_bias_2a_dataout = (both_exp_zeros === 1'b1) ? value_zero_w : select_bias_out_w;
assign wire_select_biasa_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? value_normal_w : value_add_one_w;
assign
a_is_infinity_w = (exp_a_all_one_w[10] & (~ man_a_not_zero_w[51])),
a_is_nan_w = (exp_a_all_one_w[10] & man_a_not_zero_w[51]),
a_zero_b_not = (exp_b_not_zero_w[10] & (~ exp_a_not_zero_w[10])),
b1_dffe_w = {b1_dffe_13, b1_dffe_7, b1_dffe_1},
b_is_infinity_w = (exp_b_all_one_w[10] & (~ man_b_not_zero_w[51])),
b_is_nan_w = (exp_b_all_one_w[10] & man_b_not_zero_w[51]),
bias_addition_overf_w = wire_bias_addition_overflow,
bias_addition_w = wire_bias_addition_result[10:0],
both_exp_zeros = both_exp_zeros_dffe,
e0_dffe1_wo = e0_w,
e0_w = wire_altsyncram3_q_a,
e1_w = {e1_dffe_5, e1_dffe_perf_11, e1_dffe_3, e1_dffe_perf_7, e1_dffe_1, e1_dffe_perf_3, (~ wire_b1_prod_result[62:46])},
exp_a_all_one_w = {(dataa[62] & exp_a_all_one_w[9]), (dataa[61] & exp_a_all_one_w[8]), (dataa[60] & exp_a_all_one_w[7]), (dataa[59] & exp_a_all_one_w[6]), (dataa[58] & exp_a_all_one_w[5]), (dataa[57] & exp_a_all_one_w[4]), (dataa[56] & exp_a_all_one_w[3]), (dataa[55] & exp_a_all_one_w[2]), (dataa[54] & exp_a_all_one_w[1]), (dataa[53] & exp_a_all_one_w[0]), dataa[52]},
exp_a_not_zero_w = {(dataa[62] | exp_a_not_zero_w[9]), (dataa[61] | exp_a_not_zero_w[8]), (dataa[60] | exp_a_not_zero_w[7]), (dataa[59] | exp_a_not_zero_w[6]), (dataa[58] | exp_a_not_zero_w[5]), (dataa[57] | exp_a_not_zero_w[4]), (dataa[56] | exp_a_not_zero_w[3]), (dataa[55] | exp_a_not_zero_w[2]), (dataa[54] | exp_a_not_zero_w[1]), (dataa[53] | exp_a_not_zero_w[0]), dataa[52]},
exp_add_output_all_one = {(bias_addition_w[10] & exp_add_output_all_one[9]), (bias_addition_w[9] & exp_add_output_all_one[8]), (bias_addition_w[8] & exp_add_output_all_one[7]), (bias_addition_w[7] & exp_add_output_all_one[6]), (bias_addition_w[6] & exp_add_output_all_one[5]), (bias_addition_w[5] & exp_add_output_all_one[4]), (bias_addition_w[4] & exp_add_output_all_one[3]), (bias_addition_w[3] & exp_add_output_all_one[2]), (bias_addition_w[2] & exp_add_output_all_one[1]), (bias_addition_w[1] & exp_add_output_all_one[0]), bias_addition_w[0]},
exp_add_output_not_zero = {(bias_addition_w[10] | exp_add_output_not_zero[9]), (bias_addition_w[9] | exp_add_output_not_zero[8]), (bias_addition_w[8] | exp_add_output_not_zero[7]), (bias_addition_w[7] | exp_add_output_not_zero[6]), (bias_addition_w[6] | exp_add_output_not_zero[5]), (bias_addition_w[5] | exp_add_output_not_zero[4]), (bias_addition_w[4] | exp_add_output_not_zero[3]), (bias_addition_w[3] | exp_add_output_not_zero[2]), (bias_addition_w[2] | exp_add_output_not_zero[1]), (bias_addition_w[1] | exp_add_output_not_zero[0]), bias_addition_w[0]},
exp_b_all_one_w = {(datab[62] & exp_b_all_one_w[9]), (datab[61] & exp_b_all_one_w[8]), (datab[60] & exp_b_all_one_w[7]), (datab[59] & exp_b_all_one_w[6]), (datab[58] & exp_b_all_one_w[5]), (datab[57] & exp_b_all_one_w[4]), (datab[56] & exp_b_all_one_w[3]), (datab[55] & exp_b_all_one_w[2]), (datab[54] & exp_b_all_one_w[1]), (datab[53] & exp_b_all_one_w[0]), datab[52]},
exp_b_not_zero_w = {(datab[62] | exp_b_not_zero_w[9]), (datab[61] | exp_b_not_zero_w[8]), (datab[60] | exp_b_not_zero_w[7]), (datab[59] | exp_b_not_zero_w[6]), (datab[58] | exp_b_not_zero_w[5]), (datab[57] | exp_b_not_zero_w[4]), (datab[56] | exp_b_not_zero_w[3]), (datab[55] | exp_b_not_zero_w[2]), (datab[54] | exp_b_not_zero_w[1]), (datab[53] | exp_b_not_zero_w[0]), datab[52]},
exp_result_mux_out = wire_exp_result_muxa_dataout,
exp_result_mux_sel_w = ((((a_zero_b_not_dffe_1 | b_is_infinity_dffe_1) | ((~ bias_addition_overf_w) & exp_sign_w)) | (((~ exp_add_output_not_zero[10]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)),
exp_result_w = (({11{((~ bias_addition_overf_w) & (~ exp_sign_w))}} & bias_addition_w) | ({11{(((bias_addition_overf_w | divbyzero_pipe_dffe_1) | nan_pipe_dffe_1) | a_is_infinity_dffe_1)}} & overflow_ones_w)),
exp_sign_w = wire_bias_addition_result[11],
exp_sub_a_w = {1'b0, dataa[62:52]},
exp_sub_b_w = {1'b0, datab[62:52]},
exp_sub_w = wire_exp_sub_result,
frac_a_smaller_dffe1_wi = frac_a_smaller_w,
frac_a_smaller_dffe1_wo = frac_a_smaller_dffe1,
frac_a_smaller_w = wire_cmpr2_alb,
guard_bit = q_partial_perf_dffe_3[21],
man_a_adjusted_w = wire_man_a_adjusteda_dataout,
man_a_dffe1_wi = dataa[51:0],
man_a_dffe1_wo = man_a_dffe1_dffe1,
man_a_not_zero_w = {(dataa[51] | man_a_not_zero_w[50]), (dataa[50] | man_a_not_zero_w[49]), (dataa[49] | man_a_not_zero_w[48]), (dataa[48] | man_a_not_zero_w[47]), (dataa[47] | man_a_not_zero_w[46]), (dataa[46] | man_a_not_zero_w[45]), (dataa[45] | man_a_not_zero_w[44]), (dataa[44] | man_a_not_zero_w[43]), (dataa[43] | man_a_not_zero_w[42]), (dataa[42] | man_a_not_zero_w[41]), (dataa[41] | man_a_not_zero_w[40]), (dataa[40] | man_a_not_zero_w[39]), (dataa[39] | man_a_not_zero_w[38]), (dataa[38] | man_a_not_zero_w[37]), (dataa[37] | man_a_not_zero_w[36]), (dataa[36] | man_a_not_zero_w[35]), (dataa[35] | man_a_not_zero_w[34]), (dataa[34] | man_a_not_zero_w[33]), (dataa[33] | man_a_not_zero_w[32]), (dataa[32] | man_a_not_zero_w[31]), (dataa[31] | man_a_not_zero_w[30]), (dataa[30] | man_a_not_zero_w[29]), (dataa[29] | man_a_not_zero_w[28]), (dataa[28] | man_a_not_zero_w[27]), (dataa[27] | man_a_not_zero_w[26]), (dataa[26] | man_a_not_zero_w[25]), (dataa[25] | man_a_not_zero_w[24]), (dataa[24] | man_a_not_zero_w[23]), (dataa[23] | man_a_not_zero_w[22]), (dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_adjusted_w = {1'b1, man_b_dffe1_wo},
man_b_dffe1_wi = datab[51:0],
man_b_dffe1_wo = man_b_dffe1_dffe1,
man_b_not_zero_w = {(datab[51] | man_b_not_zero_w[50]), (datab[50] | man_b_not_zero_w[49]), (datab[49] | man_b_not_zero_w[48]), (datab[48] | man_b_not_zero_w[47]), (datab[47] | man_b_not_zero_w[46]), (datab[46] | man_b_not_zero_w[45]), (datab[45] | man_b_not_zero_w[44]), (datab[44] | man_b_not_zero_w[43]), (datab[43] | man_b_not_zero_w[42]), (datab[42] | man_b_not_zero_w[41]), (datab[41] | man_b_not_zero_w[40]), (datab[40] | man_b_not_zero_w[39]), (datab[39] | man_b_not_zero_w[38]), (datab[38] | man_b_not_zero_w[37]), (datab[37] | man_b_not_zero_w[36]), (datab[36] | man_b_not_zero_w[35]), (datab[35] | man_b_not_zero_w[34]), (datab[34] | man_b_not_zero_w[33]), (datab[33] | man_b_not_zero_w[32]), (datab[32] | man_b_not_zero_w[31]), (datab[31] | man_b_not_zero_w[30]), (datab[30] | man_b_not_zero_w[29]), (datab[29] | man_b_not_zero_w[28]), (datab[28] | man_b_not_zero_w[27]), (datab[27] | man_b_not_zero_w[26]), (datab[26] | man_b_not_zero_w[25]), (datab[25] | man_b_not_zero_w[24]), (datab[24] | man_b_not_zero_w[23]), (datab[23] | man_b_not_zero_w[22]), (datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_result_dffe_wi = man_result_w,
man_result_dffe_wo = man_result_dffe,
man_result_mux_select = (((((over_under_dffe_20 | a_zero_b_not_dffe_22) | nan_pipe_dffe_22) | b_is_infinity_dffe_22) | a_is_infinity_dffe_22) | divbyzero_pipe_dffe_22),
man_result_w = wire_man_result_muxa_dataout,
man_zeros_w = {52{1'b0}},
overflow_ones_w = {11{1'b1}},
overflow_underflow = (overflow_w | underflow_w),
overflow_w = ((bias_addition_overf_w | ((exp_add_output_all_one[10] & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (((~ nan_pipe_dffe_1) & (~ a_is_infinity_dffe_1)) & (~ divbyzero_pipe_dffe_1))),
quotient_accumulate_w = {quotient_k_dffe_2, {14{1'b0}}, quotient_k_dffe_1, {28{1'b0}}, quotient_k_dffe_0, {42{1'b0}}, quotient_j_dffe, {42{1'b0}}},
quotient_process_cin_w = (round_bit & (guard_bit | sticky_bits[3])),
remainder_j_w = {wire_remainder_sub_2_result[64:0], {14{1'b0}}, wire_remainder_sub_1_result[64:0], {14{1'b0}}, wire_remainder_sub_0_result[64:0], {14{1'b0}}, wire_a1_prod_result[63:0], {15{1'b0}}},
result = {sign_pipe_dffe_23, exp_result_dffe_21, man_result_dffe_wo},
round_bit = q_partial_perf_dffe_3[20],
select_bias_out_2_w = wire_select_bias_2a_dataout,
select_bias_out_w = wire_select_biasa_dataout,
sticky_bits = {(q_partial_perf_dffe_3[19] | sticky_bits[2]), (q_partial_perf_dffe_3[18] | sticky_bits[1]), (q_partial_perf_dffe_3[17] | sticky_bits[0]), q_partial_perf_dffe_3[16]},
underflow_w = ((((((~ bias_addition_overf_w) & exp_sign_w) | (((~ exp_add_output_not_zero[10]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)) & (~ a_zero_b_not_dffe_1)) & (~ b_is_infinity_dffe_1)),
underflow_zeros_w = {11{1'b0}},
value_add_one_w = 12'b001111111111,
value_normal_w = 12'b001111111110,
value_zero_w = {12{1'b0}};
endmodule //acl_fp_div_s5_double_altfp_div_pst_luf
//synthesis_resources = altsyncram 1 lpm_add_sub 8 lpm_compare 1 lpm_mult 9 mux21 141 reg 3551
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_s5_double_altfp_div_6th
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] wire_altfp_div_pst1_result;
wire aclr;
acl_fp_div_s5_double_altfp_div_pst_luf altfp_div_pst1
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(wire_altfp_div_pst1_result));
assign
aclr = 1'b0,
result = wire_altfp_div_pst1_result;
endmodule //acl_fp_div_s5_double_altfp_div_6th
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_div_s5_double (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_div_s5_double_altfp_div_6th acl_fp_div_s5_double_altfp_div_6th_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "24"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_double.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_double.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_double.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_double.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_double_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_s5_double_bb.v TRUE
|
//////////////////////////////////////////////////////////////////////////////////
// uProgROM for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: uProgROM
// Module Name: uProgROM
// File Name: uProgROM.v
//
// Version: v1.0.0
//
// Description: Dispatcher micro code ROM controller
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
// * v1.1.0
// - external brom interface
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module uProgROM
#
(
parameter ProgWordWidth = 64 ,
parameter UProgSize = 256
)
(
iClock ,
iReset ,
iNewProgCursor ,
iNewProgCursorValid ,
oProgData ,
oProgDataValid ,
iProgDataReady ,
oROMClock ,
oROMReset ,
oROMAddr ,
oROMRW ,
oROMEnable ,
oROMWData ,
iROMRData
);
input iClock ;
input iReset ;
input [$clog2(UProgSize) - 1:0] iNewProgCursor ;
input iNewProgCursorValid ;
output [ProgWordWidth - 1:0] oProgData ;
output oProgDataValid ;
input iProgDataReady ;
output oROMClock ;
output oROMReset ;
output [$clog2(UProgSize) - 1:0] oROMAddr ;
output oROMRW ;
output oROMEnable ;
output [ProgWordWidth - 1:0] oROMWData ;
input [ProgWordWidth - 1:0] iROMRData ;
wire [$clog2(UProgSize) - 1:0] wUProgReadAddr ;
wire [ProgWordWidth - 1:0] wUProgReadData ;
wire wUProgReadSig ;
BRAMPopControl
#
(
.BRAMAddressWidth ($clog2(UProgSize) ),
.DataWidth (ProgWordWidth )
)
Inst_BRAMPopControl
(
.iClock (iClock ),
.iReset (iReset ),
.iAddressInput (iNewProgCursor ),
.iAddressValid (iNewProgCursorValid),
.oDataOut (oProgData ),
.oDataValid (oProgDataValid ),
.iDataReady (iProgDataReady ),
.oMemReadAddress (wUProgReadAddr ),
.iMemReadData (wUProgReadData ),
.oMemDataReadSig (wUProgReadSig )
);
assign oROMClock = iClock ;
assign oROMReset = iReset ;
assign oROMAddr = wUProgReadAddr ;
assign oROMRW = 1'b0 ;
assign oROMEnable = wUProgReadSig ;
assign oROMWData = {(ProgWordWidth){1'b0}} ;
assign wUProgReadData = iROMRData ;
endmodule |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(125.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dexp_64ns_64ns_64_18_full_dsp
#(parameter
ID = 9,
NUM_STAGE = 18,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dexp_16_full_dsp_64 ANN_ap_dexp_16_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din1_buf1 <= din1;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
// 1.2 11/8/2010 Fixed the PRBS Address generation.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_cmd_prbs_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
function integer logb2;
input integer number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64)
begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
//endgenerate
//generate
else if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32)
begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1)
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
// BL8: 0,8
//BL4: incremnt by 4
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 0)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = 1'b0;// lfsr_q[i+1];
// 3 1
prbs[logb2(MEM_BURST_LEN)-3:0] = 'b0;//{logb2(MEM_BURST_LEN) -3{1'b0}};
// prbs[2:0] = {3{1'b0}};
end
end
end
//endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
//generate
// if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN")
else
begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin
prbs = {ZEROS[SEED_WIDTH - 1:6],lfsr_q[6:1]};
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|