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/* * File: pippo_if.v * Project: pippo * Designer: kiss@pwrsemi * Mainteiner: kiss@pwrsemi * Checker: * Assigner: * Description: Ò»£¬IF¶ÎµÄÖ÷Òª¹¦ÄÜÈçÏÂ 1£¬ Á¬½ÓÁ÷Ë®ÏßºÍi-side IMX²¿¼þ£º·¢ËÍÈ¡Ö¸µØÖ·ÒÔÈ¡»ØÖ¸Áî£»½«È¡»ØÖ¸ÁîºÍÖ¸ÁîµØÖ·ËÍÈëÁ÷Ë®Ïß¼Ä´æÆ÷£» 2£¬ ¸üÐÂºÍÎ¬»¤PCÖµ 3£¬ ´¦ÀíºóÐøÁ÷Ë®Ïß·¢³öµÄÌø×ªÇëÇó 4£¬ Èç¹ûIF¶ÎÓÐexception·¢Éú£¬½«Ïà¹ØÇëÇóÐÅºÅËÍÖÁºó¶ËÁ÷Ë®µÈ´ýexceptÄ£¿éÍ³Ò»´¦Àí ¶þ£¬Éè¼Æ¹æ·¶ NPCµÄÀ´Ô´·ÖÀà£º 1£¬ Ë³ÐòÈ¡Ö¸£¬PC+4 2£¬ ·ÖÖ§Ìø×ª£¬npc_branchÀ´×Ô·ÖÖ§´¦ÀíÄ£¿é(¸ù¾ÝEXE¶ÎÖ´ÐÐ½á¹û´ÓÌø×ªÄ¿±êµØÖ·»òSNIAÖÐÑ¡Ôñ) 3£¬ ÖÐ¶Ï´¦Àí£¬npc_exceptÀ´×ÔÖÐ¶Ï´¦ÀíÄ£¿é£¬ÎªÖÐ¶Ï´¦Àí³ÌÐòÈë¿ÚµØÖ· 4£¬ ÌØÊâÖ¸ÁîÖ´ÐÐ£¨rfi/rfciµÈ£©£¬npc_instÀ´×Ôsrr0/srr2¼Ä´æÆ÷£¨Î»ÓÚexceptÄ£¿é£©£» 5£¬ Í¬²½Ö¸ÁîÖ´ÐÐ£¨ÏÔÐÔÖ¸Áîisync/eieio/syncºÍmtmsrµÈÒþÐÔÖ¸Áî£©£¬npc_syncÀ´×ÔÍ¬²½Ö¸ÁîµÄSNIA£» PCÎ¬»¤ºÍ¸üÐÂ£º 1£¬ Õý³£Çé¿ö£Ë³ÐòÖ¸ÁîÁ÷£¬Ê¹ÓÃNPC¸üÐÂPC¼Ä´æÆ÷ 2£¬ Ë³ÐòÖ¸ÁîÁ÷Ë®Ïß¶³½áÊ±£¬±£³ÖÏÖÓÐPCÖµ£¬µÈ´ý¶³½á½â³ýºó¼ÌÐøÈ¡Ö¸ 3£¬ Ö¸ÁîÁ÷±ä»» 1£©ÖÐ¶Ï´¦Àí£ºEXE¶Î£¬ÖÐ¶Ï´¦Àí¿ªÊ¼£¨°üÀ¨rfi/rfci£©£¬·¢³öflush_exceptÐÅºÅ£»µÈ´ýnpc_exceptÓÐÐ§ºó¸üÐÂPC²¢È¡Ö¸ 2£©·ÖÖ§Ö¸Áî´¦Àí£ÏÖ²ÉÓÃa·½°¸ a£©²ÉÓÃ¾²Ì¬·ÖÖ§Ô¤²â¼¼Êõ£¬ËùÓÐ·ÖÖ§Ö¸Áî¶¼Ô¤²âÎªNT¡£µ±ÔÚEXE¶Î»ñÈ¡·ÖÖ§½á¹ûÎªTakenÊ±£¬·¢³öflush_branchÐÅºÅ£¬ È»ºóµÈ´ýnpc_branchÓÐÐ§ºó¸üÐÂPC²¢È¡Ö¸¡£µ±Ô¤²âÕýÈ·Ê±£¬°´ÕÕÈçÉÏË³ÐòÖ¸ÁîÁ÷´¦Àí·½·¨¡£ b£©ID¶Î·¢ÏÖ·ÖÖ§Ö¸Áî£¬·¢³öbp_stallÐÅºÅ£¬´ËÊ±ÏÂÒ»ÌõÖ¸ÁîµÄÈ¡Ö¸ÉÐÎ´Íê³É£¨Ëø´æ½øÈëÁ÷Ë®Ïß£©¡£ ¸ù¾ÝEXE¶Î½á¹û£º branch_taken Ìø×ª¡£Ê¹ÓÃnpc_branch¸üÐÂpc²¢È¡Ö¸ branch_nt ²»Ìø×ª¡£Ê¹ÓÃÏÖpcÈ¡Ö¸ ×¢£ºflushpipeÐÅºÅÎªÒÔÉÏÁ½ÖÖÇé¿öµÄ×ÛºÏ£¬ÓÉpipectrlÄ£¿é²úÉú IMX½Ó¿Ú´¦Àí£°üº¬¸´ÔÓµÄ·Ö²¼Ê½ÐÍ¬ È¡Ö¸ÇëÇóµÄ·¢ËÍ£¸ù¾Ý´¦ÀíÆ÷Á÷Ë®Ïß×´Ì¬ºÍIMX·µ»ØµÄ×´Ì¬£¬Í¬²½¸üÐÂÈ¡Ö¸ÇëÇóºÍÈ¡Ö¸µØÖ·£¨PC£© rqt_validÂß¼£È¡¾öÓÚÁ÷Ë®Ïß×´Ì¬ PC¸üÐÂÂß¼£È¡¾öÓÚÁ÷Ë®Ïß×´Ì¬ºÍIMX·µ»Ø×´Ì¬ È¡Ö¸ÏìÓ¦µÄ½ÓÊÕ£Í¬ÑùÐèÒª¸ù¾Ý´¦ÀíÆ÷Á÷Ë®Ïß×´Ì¬ºÍIMX·µ»ØµÄ×´Ì¬£¬¾ö¶¨ÊÇ·ñ¼Ä´æµ±Ç°ÏìÓ¦½øÈëÁ÷Ë®Ïß È¡Ö¸ÇëÇóµÄÈ¡ÏûºÍ±ä»»Çé¿öµÄ´¦Àí ÓÐÐ§·µ»Ø²¢²»Ò»¶¨»á½øÈëÁ÷Ë®Ïß Èý£¬IF/IDÁ÷Ë®¼Ä´æÆ÷Âß¼-Á÷Ë®Êä³ö°üÀ¨id_valid, id_inst, id_cia, id_snia£»Á÷Ë®Î¬»¤ºÍ¸üÐÂ²ßÂÔ²Î¿¼pipectrlÄ£¿é£¬»ù±¾ÈçÏÂ£º 1£¬ Õý³£Çé¿ö£È¡Ö¸³É¹¦£¬ÇÒÁ÷Ë®ÏßÕý³££º¼Ä´æ²¢ËÍ³öÈ¡»ØÖ¸Áî 2£¬ ÖÐ¶Ï´¦Àí¿ªÊ¼£¬exceptÄ£¿é·¢³öflushpipeÐÅºÅÒÔË¢ÐÂÁ÷Ë®Ïß£º²åÈëNOP£¬²¢ÖÃid_validÎªÎÞÐ§ 3£¬ µ±Á÷Ë®Ïß¶³½á£¨if_freeze»òid_freezeÓÐÐ§£©Ê±£¬IF/ID²åÈëNOP»òKCS bubble °üÀ¨µÈ´ý×ÜÏßÏìÓ¦£¨ack_i/err_iÎÞÐ§£¬¼´if_stall£©£¬¶øÆäËûÕý³£Ê±£» * Task.I: [TBD]imxÐÒéÑéÖ¤ºÍ¸Ä½ø Ä¿Ç°i-imx²ÉÓÃ·ÖÀëµÄµØÖ·ºÍÊý¾Ýtsc´«Êä£¬²¢Ö§³ÖÒ»¼¶pipeling·½Ê½£» Ä¿Ç°rqt_valid×ÜÊÇÓÐÐ§£³ýÁ÷Ë®ÏßË¢ÐÂ(flushpipe)ºÍ¶³½á(id_freeze)Ê±£» ÔÚslave·µ»ØµØÖ·ÏìÓ¦(!rty_i)ºó£¬PC¸üÐÂ£¬·¢³öÐÂµÄµØÖ·ÇëÇó£¼ä½Ó±£Ö¤²»»áÖØ¸´ËÍ³öÖ®Ç°µÄµØÖ·ÇëÇó Èç¹ûÔÚµØÖ·ÏìÓ¦ºÍÊý¾ÝÏìÓ¦Ö®¼ä²åÈëµÈ´ýÖÜÆÚ(¼´!rty_iºÍack_iÖ®¼ä)£¬slaveÐë±£Ö¤¹¤×÷Õý³££ÇëÇóÍê³ÉË³Ðò ¼õÉÙimc·µ»ØµÄaddrÎ»¿í£¬»òÕß[1:0]Ò²²»ÐèÒª£» µØÖ·ÇëÇóºÍÏìÓ¦£¨rqt->!rty_i£©Âß¼»ØÂ·£Ä£¿éÖ®¼ä¶¼ÊÇ×éºÏÂß¼£¨fetcherºÍbiu/imc£©£¬ÇÒÐè×¢ÒâÏßÑÓÊ±£» ¸´Î»Çé¿öµÄÑéÖ¤£slave±ØÐëÍ¬²½£¬±ÜÃâÈ¡»Ø¸´Î»Ö®Ç°ÇëÇóµÄÊý¾Ý£» IMXÏÂµØÖ·½×¶ÎºÍÊý¾Ý½×¶ÎÍ¬Ê±½áÊøµÄÇé¿ö´¦Àí£¬¼´(!rty)ºÍackÍ¬Ê±ÓÐÐ§ ºÍwbv4¹æ·¶µÄÒìÍ¬ ÊÇ·ñÉèÖÃtsc_busyÎ»±íÊ¾×ÜÏß´«Êä½øÐÐÖÐ£» ´ý±È½Ïwb¹æ·¶ÖÐ!rty_iµÄÊ±ÐòÎÊÌâ£ºÍack_iµÄ¹ØÏµ£» [TBV]È¡Ö¸Âß¼ÔÚÈ¡Ö¸¶³½á£¬Á÷Ë®ÏßË¢ÐÂ£¬if_stallºÍµ±Ç°È¡Ö¸Ëù´¦½×¶ÎµÈ¸÷ÖÖÇé¿ö½áºÏÏÂµÄ´¦ÀíºÍÉè¼ÆÑéÖ¤ ¼´PCµÄÎ¬»¤£¨°üÀ¨NPCÂß¼£©ºÍrqt_validµÄÍ¬²½¸üÐÂ±ØÐë±£Ö¤ 1£¬·¢³öÕýÈ·µÄÈ¡Ö¸ÇëÇó£¸ù¾Ýµ±Ç°Á÷Ë®Ïß×´Ì¬£» 2£¬½ö¼Ä´æÒ»´ÎÖ¸Áî½øÈëÁ÷Ë®Ïß£» 3£¬²»»á·¢ÉúÖØ¸´È¡Ö¸ºÍ²»»á¶ªÊ§È¡»ØµÄÖ¸Áî£» [TBD]µ±Á÷Ë®Ïß·µ»ØÈ¡Ö¸´íÎó£¨err_i£©Ê±£¬ÏàÓ¦exceptÇëÇóÔÚEXE¶Î½«µÃµ½´¦Àí£»ciaËÍÈëÁ÷Ë®Ïß£¬ÖÃid_validÎª0£» err_iÈ¡»ØµÄÊý¾ÝÊÇÊ²Ã´£¿ËÍÈëÁ÷Ë®Ïß»áÔÚid¶Î²úÉúÆäËûÐÐÎª£¿ ¿¼ÂÇ²åÈëNOPÒÔ±ÜÃâ´íÎóÊý¾ÝµÄ¸±×÷ÓÃ£¬»òÓÃid_validÖÃËùÓÐid¶ÎÊä³öÎªÎÞÐ§£» [TBV] imx, pipelining and PC bahavior 1. npc_branch, npc_except can't assert simultaneously 2. after recover from freezing, first fetch request from previous pc/npc? 3. the case of canceling fetch request(cache miss, and inst transfer event happened) processing by imx protocol: diassert rqt, then diassert ack. 4. check id_snia timing 5. coding style of pipelining register [TBD]make "itlb, immu" logic conditional * Task.II: * full synthesis & verification * rtl performance refactor-improve speed, reduce power and area. * to improve fetch performance, add buffer to register fetched instruction and address at some case */ // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "def_pippo.v" module pippo_if( clk, rst, iimx_adr_o, iimx_rqt_o, iimx_rty_i, iimx_ack_i, iimx_err_i, iimx_dat_i, iimx_adr_i, npc_branch, npc_except, npc_branch_valid, npc_except_valid, pc_freeze, if_stall, if_freeze, id_freeze, flushpipe, id_inst, id_cia, id_valid, id_snia, id_sig_ibuserr ); input clk; input rst; // IMX I/F to fetch instructions (from cache/ocm/memory controller) input [31:0] iimx_dat_i; input iimx_ack_i; input iimx_err_i; input [31:0] iimx_adr_i; input iimx_rty_i; output [31:0] iimx_adr_o; output iimx_rqt_o; // inst. flow transfer input [29:0] npc_branch; input npc_branch_valid; input [31:0] npc_except; // keep least two address bits to code ISR entrance easily. input npc_except_valid; // pipeline control input pc_freeze; input if_freeze; input id_freeze; input flushpipe; output if_stall; // pipeling register output id_valid; output [31:0] id_inst; output [29:0] id_cia; output [29:0] id_snia; // exception request output id_sig_ibuserr; // // // reg id_valid; reg [31:0] id_inst; reg [29:0] id_cia; reg [29:0] id_snia; reg id_sig_ibuserr; reg [31:0] npc_value; reg if_valid; reg [31:0] if_inst; reg [29:0] if_cia; reg if_sig_ibuserr; reg [31:0] pc; wire if_rqt_valid; wire [32:0] pcadd4; wire except_ibuserr; // // send fetch rqt to I-IMX // assign iimx_adr_o = pc; assign iimx_rqt_o = if_rqt_valid; // stall request, waiting for I-IMX response assign if_stall = ~iimx_ack_i; // // PC Register logic // // NPC source assign pcadd4={(pc[31:2]+31'd1), 2'b00}; // assign fetch_lost = id_freeze & iimx_ack_i; always @(npc_branch_valid or npc_except_valid or id_freeze or iimx_adr_i or fetch_lost or npc_branch or npc_except or pc or pcadd4) begin casex ({npc_branch_valid, npc_except_valid, id_freeze, fetch_lost}) // synopsys parallel_case 4'b0000: begin npc_value = pcadd4[31:0]; end 4'b0100: begin npc_value = npc_except; end 4'b1000: begin npc_value = {npc_branch, 2'b00}; end 4'b0010: begin // if pipeline(if_freeze & id_freeze) is freezon, keep current pc npc_value = pc; end 4'b0011: begin npc_value = iimx_adr_i; // fetch current fetched instruction again end default: begin npc_value = pc; end endcase end // // PC update policy // // 1. after hard reset, keep RESET_VECTOR (pcadd4[32]) to avoid overflow // 2. update pc when // a) flushpipe: flush pipeline, fetch with npc // b) !iimx_rty_i: current transaction is complete // c) fetch lost always @(posedge clk or posedge rst) begin if (rst) pc <= #1 `pippo_RESET_VECTOR; else if (pcadd4[32] & !flushpipe) // !flushpipe: keep normal when fetched first branch inst pc <= #1 `pippo_RESET_VECTOR; else if (flushpipe \| (!iimx_rty_i) \| fetch_lost) pc <= #1 npc_value; end // // inst. fetch request logic: if_rqt_valid signal // 1. when flushpipe assert(pc_freeze asserts), if_rqt_valid disassert // 2. when pipeline freeze(id_freeze freeze), if_rqt_valid disassert to reduce memory access // NOT use if_freeze signal to exclude if_stall deadlock, or additional logic is needed for biu // deadloack: if_freeze assert at wait state, if you diassert this request, system stop forever. // 3. hard-reset case: if_rqt_valid assert until RESET_VECTOR's ack(!iimx_rty_i) come, then keep disassertion. // At normal state, always send fetch request - if_rqt_valid keep assert, when address ack(!iimx_rty_i) assert // or disassert. including case that if_stall asserts, to avoid deadlock: no new fetch send out // deadlock: (if_stall raised -> if_freeze assert -> rqt_valid disassert forever) // after hard reset, to avoid fetch reset vector many times, // "!flushpipe" logic is to reduce one cycle delay after reset vector's branch reg rst_rqt_done; always @(posedge clk or posedge rst) begin if (rst) rst_rqt_done <= #1 1'b0; else if (flushpipe) rst_rqt_done <= #1 1'b0; else if (pcadd4[32] & !iimx_rty_i) rst_rqt_done <= #1 1'b1; end // to check the timing of rqt_valid signal - rqt_valid must have budget for addr_ack logic, i.e.: // at IMX address phase(cycle 1): // Master send out if_rqt_valid, slave check address and give back addr_ack; // Addr_ack(!iimx_rty_i) signal must satisfy the setup time, when inputting to master; // [TBD] register out if_rqt_valid signal to improve timing, add a pipeline bubble under some case // note: keep pace with pc update assign if_rqt_valid = !(pc_freeze \| id_freeze \| (pcadd4[32] & rst_rqt_done)); // // IF/ID pipelining logic // always @(iimx_ack_i or if_freeze or id_freeze or flushpipe or if_valid or if_inst or if_cia or id_valid or id_inst or id_cia or iimx_dat_i or iimx_adr_i or except_ibuserr or id_sig_ibuserr) begin casex ({iimx_ack_i, if_freeze, id_freeze, flushpipe}) // synopsys parallel_case 4'b1000: begin // Normal pipelining. I-IMX returns valid value if_valid = 1'b1; if_inst = iimx_dat_i; if_cia = iimx_adr_i[31:2]; if_sig_ibuserr = except_ibuserr; end 4'bxxx1: begin // flushpipe is asserted, insert NOP bubble if_valid = 1'b0; if_inst = `pippo_PWR_NOP; if_cia = id_cia; if_sig_ibuserr = 1'b0; end 4'bx100: begin // if_freeze is asserted, id_freeze is disasserted, insert NOP bubble if_valid = 1'b0; if_inst = `pippo_PWR_NOP; if_cia = id_cia; if_sig_ibuserr = 1'b0; end 4'bx110: begin // if_freeze/id_freeze is asserted, insert KCS bubble if_valid = id_valid; if_inst = id_inst; if_cia = id_cia; if_sig_ibuserr = id_sig_ibuserr; end default: begin // [TBV]iimx_err_i is asserted if_valid = 1'b0; if_inst = `pippo_PWR_NOP; if_cia = id_cia; if_sig_ibuserr = except_ibuserr; end endcase end always @(posedge clk or posedge rst) begin if(rst) begin id_valid <= #1 1'b0; id_inst <= #1 `pippo_PWR_NOP; id_cia <= #1 30'd0; id_snia <= #1 30'd0; id_sig_ibuserr = 1'b0; end else begin id_valid <= #1 if_valid; id_inst <= #1 if_inst; id_cia <= #1 if_cia; id_snia <= #1 pcadd4[31:2]; id_sig_ibuserr = if_sig_ibuserr; `ifdef pippo_VERBOSE // synopsys translate_off $display("%t: id_valid <= %h", $time, id_valid); $display("%t: id_inst <= %h", $time, id_inst); $display("%t: id_cia <= %h", $time, id_cia); $display("%t: id_snia <= %h", $time, id_snia); // synopsys translate_on `endif end end // // except request from IF stage // assign except_ibuserr = iimx_err_i & iimx_ack_i; // err valid only when ack assert endmodule
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014 // Date : Thu Jul 24 13:40:01 2014 // Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim // D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_funcsim.v // Design : fifo_generator_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7z020clg484-1 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* downgradeipidentifiedwarnings = "yes" ) ( x_core_info = "fifo_generator_v12_0,Vivado 2014.1" ) ( CHECK_LICENSE_TYPE = "fifo_generator_0,fifo_generator_v12_0,{}" ) ( core_generation_info = "fifo_generator_0,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=16,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=2,C_AXIS_TKEEP_WIDTH=2,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" ) ( NotValidForBitStream ) module fifo_generator_0 (wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, empty, valid); input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [9:0]din; ( x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" ) input wr_en; ( x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" ) input rd_en; output [9:0]dout; ( x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" ) output full; ( x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" ) output empty; output valid; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire rd_clk; wire rd_en; wire rd_rst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; wire NLW_U0_almost_empty_UNCONNECTED; wire NLW_U0_almost_full_UNCONNECTED; wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; wire NLW_U0_axi_ar_overflow_UNCONNECTED; wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; wire NLW_U0_axi_ar_prog_full_UNCONNECTED; wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; wire NLW_U0_axi_ar_underflow_UNCONNECTED; wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; wire NLW_U0_axi_aw_overflow_UNCONNECTED; wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; wire NLW_U0_axi_aw_prog_full_UNCONNECTED; wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; wire NLW_U0_axi_aw_underflow_UNCONNECTED; wire NLW_U0_axi_b_dbiterr_UNCONNECTED; wire NLW_U0_axi_b_overflow_UNCONNECTED; wire NLW_U0_axi_b_prog_empty_UNCONNECTED; wire NLW_U0_axi_b_prog_full_UNCONNECTED; wire NLW_U0_axi_b_sbiterr_UNCONNECTED; wire NLW_U0_axi_b_underflow_UNCONNECTED; wire NLW_U0_axi_r_dbiterr_UNCONNECTED; wire NLW_U0_axi_r_overflow_UNCONNECTED; wire NLW_U0_axi_r_prog_empty_UNCONNECTED; wire NLW_U0_axi_r_prog_full_UNCONNECTED; wire NLW_U0_axi_r_sbiterr_UNCONNECTED; wire NLW_U0_axi_r_underflow_UNCONNECTED; wire NLW_U0_axi_w_dbiterr_UNCONNECTED; wire NLW_U0_axi_w_overflow_UNCONNECTED; wire NLW_U0_axi_w_prog_empty_UNCONNECTED; wire NLW_U0_axi_w_prog_full_UNCONNECTED; wire NLW_U0_axi_w_sbiterr_UNCONNECTED; wire NLW_U0_axi_w_underflow_UNCONNECTED; wire NLW_U0_axis_dbiterr_UNCONNECTED; wire NLW_U0_axis_overflow_UNCONNECTED; wire NLW_U0_axis_prog_empty_UNCONNECTED; wire NLW_U0_axis_prog_full_UNCONNECTED; wire NLW_U0_axis_sbiterr_UNCONNECTED; wire NLW_U0_axis_underflow_UNCONNECTED; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_m_axi_arvalid_UNCONNECTED; wire NLW_U0_m_axi_awvalid_UNCONNECTED; wire NLW_U0_m_axi_bready_UNCONNECTED; wire NLW_U0_m_axi_rready_UNCONNECTED; wire NLW_U0_m_axi_wlast_UNCONNECTED; wire NLW_U0_m_axi_wvalid_UNCONNECTED; wire NLW_U0_m_axis_tlast_UNCONNECTED; wire NLW_U0_m_axis_tvalid_UNCONNECTED; wire NLW_U0_overflow_UNCONNECTED; wire NLW_U0_prog_empty_UNCONNECTED; wire NLW_U0_prog_full_UNCONNECTED; wire NLW_U0_rd_rst_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_s_axis_tready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire NLW_U0_underflow_UNCONNECTED; wire NLW_U0_wr_ack_UNCONNECTED; wire NLW_U0_wr_rst_busy_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; wire [3:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; wire [15:0]NLW_U0_m_axis_tdata_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; wire [1:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [1:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; wire [3:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; wire [3:0]NLW_U0_wr_data_count_UNCONNECTED; ( C_ADD_NGC_CONSTRAINT = "0" ) ( C_APPLICATION_TYPE_AXIS = "0" ) ( C_APPLICATION_TYPE_RACH = "0" ) ( C_APPLICATION_TYPE_RDCH = "0" ) ( C_APPLICATION_TYPE_WACH = "0" ) ( C_APPLICATION_TYPE_WDCH = "0" ) ( C_APPLICATION_TYPE_WRCH = "0" ) ( C_AXIS_TDATA_WIDTH = "16" ) ( C_AXIS_TDEST_WIDTH = "1" ) ( C_AXIS_TID_WIDTH = "1" ) ( C_AXIS_TKEEP_WIDTH = "2" ) ( C_AXIS_TSTRB_WIDTH = "2" ) ( C_AXIS_TUSER_WIDTH = "4" ) ( C_AXIS_TYPE = "0" ) ( C_AXI_ADDR_WIDTH = "32" ) ( C_AXI_ARUSER_WIDTH = "1" ) ( C_AXI_AWUSER_WIDTH = "1" ) ( C_AXI_BUSER_WIDTH = "1" ) ( C_AXI_DATA_WIDTH = "64" ) ( C_AXI_ID_WIDTH = "1" ) ( C_AXI_LEN_WIDTH = "8" ) ( C_AXI_LOCK_WIDTH = "1" ) ( C_AXI_RUSER_WIDTH = "1" ) ( C_AXI_TYPE = "1" ) ( C_AXI_WUSER_WIDTH = "1" ) ( C_COMMON_CLOCK = "0" ) ( C_COUNT_TYPE = "0" ) ( C_DATA_COUNT_WIDTH = "4" ) ( C_DEFAULT_VALUE = "BlankString" ) ( C_DIN_WIDTH = "10" ) ( C_DIN_WIDTH_AXIS = "1" ) ( C_DIN_WIDTH_RACH = "32" ) ( C_DIN_WIDTH_RDCH = "64" ) ( C_DIN_WIDTH_WACH = "32" ) ( C_DIN_WIDTH_WDCH = "64" ) ( C_DIN_WIDTH_WRCH = "2" ) ( C_DOUT_RST_VAL = "0" ) ( C_DOUT_WIDTH = "10" ) ( C_ENABLE_RLOCS = "0" ) ( C_ENABLE_RST_SYNC = "0" ) ( C_ERROR_INJECTION_TYPE = "0" ) ( C_ERROR_INJECTION_TYPE_AXIS = "0" ) ( C_ERROR_INJECTION_TYPE_RACH = "0" ) ( C_ERROR_INJECTION_TYPE_RDCH = "0" ) ( C_ERROR_INJECTION_TYPE_WACH = "0" ) ( C_ERROR_INJECTION_TYPE_WDCH = "0" ) ( C_ERROR_INJECTION_TYPE_WRCH = "0" ) ( C_FAMILY = "zynq" ) ( C_FULL_FLAGS_RST_VAL = "1" ) ( C_HAS_ALMOST_EMPTY = "0" ) ( C_HAS_ALMOST_FULL = "0" ) ( C_HAS_AXIS_TDATA = "1" ) ( C_HAS_AXIS_TDEST = "0" ) ( C_HAS_AXIS_TID = "0" ) ( C_HAS_AXIS_TKEEP = "0" ) ( C_HAS_AXIS_TLAST = "0" ) ( C_HAS_AXIS_TREADY = "1" ) ( C_HAS_AXIS_TSTRB = "0" ) ( C_HAS_AXIS_TUSER = "1" ) ( C_HAS_AXI_ARUSER = "0" ) ( C_HAS_AXI_AWUSER = "0" ) ( C_HAS_AXI_BUSER = "0" ) ( C_HAS_AXI_ID = "0" ) ( C_HAS_AXI_RD_CHANNEL = "1" ) ( C_HAS_AXI_RUSER = "0" ) ( C_HAS_AXI_WR_CHANNEL = "1" ) ( C_HAS_AXI_WUSER = "0" ) ( C_HAS_BACKUP = "0" ) ( C_HAS_DATA_COUNT = "0" ) ( C_HAS_DATA_COUNTS_AXIS = "0" ) ( C_HAS_DATA_COUNTS_RACH = "0" ) ( C_HAS_DATA_COUNTS_RDCH = "0" ) ( C_HAS_DATA_COUNTS_WACH = "0" ) ( C_HAS_DATA_COUNTS_WDCH = "0" ) ( C_HAS_DATA_COUNTS_WRCH = "0" ) ( C_HAS_INT_CLK = "0" ) ( C_HAS_MASTER_CE = "0" ) ( C_HAS_MEMINIT_FILE = "0" ) ( C_HAS_OVERFLOW = "0" ) ( C_HAS_PROG_FLAGS_AXIS = "0" ) ( C_HAS_PROG_FLAGS_RACH = "0" ) ( C_HAS_PROG_FLAGS_RDCH = "0" ) ( C_HAS_PROG_FLAGS_WACH = "0" ) ( C_HAS_PROG_FLAGS_WDCH = "0" ) ( C_HAS_PROG_FLAGS_WRCH = "0" ) ( C_HAS_RD_DATA_COUNT = "0" ) ( C_HAS_RD_RST = "0" ) ( C_HAS_RST = "1" ) ( C_HAS_SLAVE_CE = "0" ) ( C_HAS_SRST = "0" ) ( C_HAS_UNDERFLOW = "0" ) ( C_HAS_VALID = "1" ) ( C_HAS_WR_ACK = "0" ) ( C_HAS_WR_DATA_COUNT = "0" ) ( C_HAS_WR_RST = "0" ) ( C_IMPLEMENTATION_TYPE = "2" ) ( C_IMPLEMENTATION_TYPE_AXIS = "11" ) ( C_IMPLEMENTATION_TYPE_RACH = "12" ) ( C_IMPLEMENTATION_TYPE_RDCH = "11" ) ( C_IMPLEMENTATION_TYPE_WACH = "12" ) ( C_IMPLEMENTATION_TYPE_WDCH = "11" ) ( C_IMPLEMENTATION_TYPE_WRCH = "12" ) ( C_INIT_WR_PNTR_VAL = "0" ) ( C_INTERFACE_TYPE = "0" ) ( C_MEMORY_TYPE = "1" ) ( C_MIF_FILE_NAME = "BlankString" ) ( C_MSGON_VAL = "1" ) ( C_OPTIMIZATION_MODE = "0" ) ( C_OVERFLOW_LOW = "0" ) ( C_POWER_SAVING_MODE = "0" ) ( C_PRELOAD_LATENCY = "1" ) ( C_PRELOAD_REGS = "0" ) ( C_PRIM_FIFO_TYPE = "512x36" ) ( C_PRIM_FIFO_TYPE_AXIS = "1kx18" ) ( C_PRIM_FIFO_TYPE_RACH = "512x36" ) ( C_PRIM_FIFO_TYPE_RDCH = "1kx36" ) ( C_PRIM_FIFO_TYPE_WACH = "512x36" ) ( C_PRIM_FIFO_TYPE_WDCH = "1kx36" ) ( C_PRIM_FIFO_TYPE_WRCH = "512x36" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" ) ( C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" ) ( C_PROG_EMPTY_TYPE = "0" ) ( C_PROG_EMPTY_TYPE_AXIS = "0" ) ( C_PROG_EMPTY_TYPE_RACH = "0" ) ( C_PROG_EMPTY_TYPE_RDCH = "0" ) ( C_PROG_EMPTY_TYPE_WACH = "0" ) ( C_PROG_EMPTY_TYPE_WDCH = "0" ) ( C_PROG_EMPTY_TYPE_WRCH = "0" ) ( C_PROG_FULL_THRESH_ASSERT_VAL = "13" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" ) ( C_PROG_FULL_THRESH_NEGATE_VAL = "12" ) ( C_PROG_FULL_TYPE = "0" ) ( C_PROG_FULL_TYPE_AXIS = "0" ) ( C_PROG_FULL_TYPE_RACH = "0" ) ( C_PROG_FULL_TYPE_RDCH = "0" ) ( C_PROG_FULL_TYPE_WACH = "0" ) ( C_PROG_FULL_TYPE_WDCH = "0" ) ( C_PROG_FULL_TYPE_WRCH = "0" ) ( C_RACH_TYPE = "0" ) ( C_RDCH_TYPE = "0" ) ( C_RD_DATA_COUNT_WIDTH = "4" ) ( C_RD_DEPTH = "16" ) ( C_RD_FREQ = "1" ) ( C_RD_PNTR_WIDTH = "4" ) ( C_REG_SLICE_MODE_AXIS = "0" ) ( C_REG_SLICE_MODE_RACH = "0" ) ( C_REG_SLICE_MODE_RDCH = "0" ) ( C_REG_SLICE_MODE_WACH = "0" ) ( C_REG_SLICE_MODE_WDCH = "0" ) ( C_REG_SLICE_MODE_WRCH = "0" ) ( C_SYNCHRONIZER_STAGE = "2" ) ( C_UNDERFLOW_LOW = "0" ) ( C_USE_COMMON_OVERFLOW = "0" ) ( C_USE_COMMON_UNDERFLOW = "0" ) ( C_USE_DEFAULT_SETTINGS = "0" ) ( C_USE_DOUT_RST = "1" ) ( C_USE_ECC = "0" ) ( C_USE_ECC_AXIS = "0" ) ( C_USE_ECC_RACH = "0" ) ( C_USE_ECC_RDCH = "0" ) ( C_USE_ECC_WACH = "0" ) ( C_USE_ECC_WDCH = "0" ) ( C_USE_ECC_WRCH = "0" ) ( C_USE_EMBEDDED_REG = "0" ) ( C_USE_FIFO16_FLAGS = "0" ) ( C_USE_FWFT_DATA_COUNT = "0" ) ( C_USE_PIPELINE_REG = "0" ) ( C_VALID_LOW = "0" ) ( C_WACH_TYPE = "0" ) ( C_WDCH_TYPE = "0" ) ( C_WRCH_TYPE = "0" ) ( C_WR_ACK_LOW = "0" ) ( C_WR_DATA_COUNT_WIDTH = "4" ) ( C_WR_DEPTH = "16" ) ( C_WR_DEPTH_AXIS = "1024" ) ( C_WR_DEPTH_RACH = "16" ) ( C_WR_DEPTH_RDCH = "1024" ) ( C_WR_DEPTH_WACH = "16" ) ( C_WR_DEPTH_WDCH = "1024" ) ( C_WR_DEPTH_WRCH = "16" ) ( C_WR_FREQ = "1" ) ( C_WR_PNTR_WIDTH = "4" ) ( C_WR_PNTR_WIDTH_AXIS = "10" ) ( C_WR_PNTR_WIDTH_RACH = "4" ) ( C_WR_PNTR_WIDTH_RDCH = "10" ) ( C_WR_PNTR_WIDTH_WACH = "4" ) ( C_WR_PNTR_WIDTH_WDCH = "10" ) ( C_WR_PNTR_WIDTH_WRCH = "4" ) ( C_WR_RESPONSE_LATENCY = "1" ) fifo_generator_0fifo_generator_v12_0__parameterized0 U0 (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), .almost_full(NLW_U0_almost_full_UNCONNECTED), .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), .axi_ar_injectdbiterr(1'b0), .axi_ar_injectsbiterr(1'b0), .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), .axi_aw_injectdbiterr(1'b0), .axi_aw_injectsbiterr(1'b0), .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), .axi_b_injectdbiterr(1'b0), .axi_b_injectsbiterr(1'b0), .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), .axi_r_injectdbiterr(1'b0), .axi_r_injectsbiterr(1'b0), .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), .axi_w_injectdbiterr(1'b0), .axi_w_injectsbiterr(1'b0), .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), .axis_injectdbiterr(1'b0), .axis_injectsbiterr(1'b0), .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), .data_count(NLW_U0_data_count_UNCONNECTED[3:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), .empty(empty), .full(full), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .int_clk(1'b0), .m_aclk(1'b0), .m_aclk_en(1'b0), .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), .m_axi_arready(1'b0), .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), .m_axi_bid(1'b0), .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), .m_axi_bresp({1'b0,1'b0}), .m_axi_buser(1'b0), .m_axi_bvalid(1'b0), .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rid(1'b0), .m_axi_rlast(1'b0), .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), .m_axi_rresp({1'b0,1'b0}), .m_axi_ruser(1'b0), .m_axi_rvalid(1'b0), .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), .m_axi_wready(1'b0), .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[15:0]), .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[1:0]), .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), .m_axis_tready(1'b0), .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[1:0]), .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(NLW_U0_prog_empty_UNCONNECTED), .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0}), .prog_full(NLW_U0_prog_full_UNCONNECTED), .prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[3:0]), .rd_en(rd_en), .rd_rst(rd_rst), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), .rst(1'b0), .s_aclk(1'b0), .s_aclk_en(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_arid(1'b0), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_aruser(1'b0), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awuser(1'b0), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wid(1'b0), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser(1'b0), .s_axi_wvalid(1'b0), .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axis_tdest(1'b0), .s_axis_tid(1'b0), .s_axis_tkeep({1'b0,1'b0}), .s_axis_tlast(1'b0), .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), .s_axis_tstrb({1'b0,1'b0}), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .sleep(1'b0), .srst(1'b0), .underflow(NLW_U0_underflow_UNCONNECTED), .valid(valid), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[3:0]), .wr_en(wr_en), .wr_rst(wr_rst), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule ( ORIG_REF_NAME = "blk_mem_gen_generic_cstr" ) module fifo_generator_0blk_mem_gen_generic_cstr (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_prim_width \ramloop[0].ram.r (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule ( ORIG_REF_NAME = "blk_mem_gen_prim_width" ) module fifo_generator_0blk_mem_gen_prim_width (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_prim_wrapper \prim_noinit.ram (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule ( ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" ) module fifo_generator_0blk_mem_gen_prim_wrapper (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; ( box_type = "PRIMITIVE" ) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (.ADDRARDADDR({1'b0,1'b0,1'b0,1'b0,1'b0,O1,1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,I1,1'b0,1'b0,1'b0,1'b0,1'b0}), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[4:3],1'b0,1'b0,1'b0,1'b0,1'b0,din[2:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[9:8],1'b0,1'b0,1'b0,1'b0,1'b0,din[7:5]}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO({\n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[4:3],\n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[2:0]}), .DOBDO({\n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[9:8],\n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[7:5]}), .DOPADOP({\n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram }), .DOPBDOP({\n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram }), .ENARDEN(tmp_ram_rd_en), .ENBWREN(E), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(rd_rst), .RSTRAMB(rd_rst), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE({E,E,E,E})); endmodule ( ORIG_REF_NAME = "blk_mem_gen_top" ) module fifo_generator_0blk_mem_gen_top (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_generic_cstr \valid.cstr (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule ( ORIG_REF_NAME = "blk_mem_gen_v8_2" ) module fifo_generator_0blk_mem_gen_v8_2__parameterized0 (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_v8_2_synth inst_blk_mem_gen (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule ( ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" ) module fifo_generator_0blk_mem_gen_v8_2_synth (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_top \gnativebmg.native_blk_mem_gen (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule ( ORIG_REF_NAME = "clk_x_pntrs" ) module fifo_generator_0clk_x_pntrs (O1, O2, O3, rd_en, p_18_out, I1, I2, I3, I4, rd_clk, rd_rst, wr_clk, wr_rst, D); output O1; output O2; output [3:0]O3; input rd_en; input p_18_out; input [3:0]I1; input [3:0]I2; input [2:0]I3; input [3:0]I4; input rd_clk; input rd_rst; input wr_clk; input wr_rst; input [2:0]D; wire [2:0]D; wire [3:0]I1; wire [3:0]I2; wire [2:0]I3; wire [3:0]I4; wire O1; wire O2; wire [3:0]O3; wire [3:0]Q; wire \n_0_gsync_stage[1].wr_stg_inst ; wire \n_0_gsync_stage[2].wr_stg_inst ; wire n_0_ram_empty_i_i_2; wire n_0_ram_empty_i_i_3; wire n_0_ram_empty_i_i_4; wire n_0_ram_empty_i_i_5; wire \n_0_rd_pntr_bin[0]_i_1 ; wire \n_0_rd_pntr_bin[1]_i_1 ; wire \n_1_gsync_stage[1].wr_stg_inst ; wire \n_1_gsync_stage[2].wr_stg_inst ; wire \n_2_gsync_stage[1].wr_stg_inst ; wire \n_2_gsync_stage[2].rd_stg_inst ; wire \n_2_gsync_stage[2].wr_stg_inst ; wire \n_3_gsync_stage[1].wr_stg_inst ; wire \n_3_gsync_stage[2].rd_stg_inst ; wire \n_3_gsync_stage[2].wr_stg_inst ; wire \n_4_gsync_stage[2].rd_stg_inst ; wire \n_4_gsync_stage[2].wr_stg_inst ; wire [3:0]p_0_in; wire [2:0]p_0_in1_out; wire p_18_out; wire [3:0]p_1_out; wire rd_clk; wire rd_en; wire [3:0]rd_pntr_gc; wire rd_rst; wire wr_clk; wire [3:0]wr_pntr_gc; wire wr_rst; fifo_generator_0synchronizer_ff \gsync_stage[1].rd_stg_inst (.I1(wr_pntr_gc), .Q(Q), .rd_clk(rd_clk), .rd_rst(rd_rst)); fifo_generator_0synchronizer_ff_0 \gsync_stage[1].wr_stg_inst (.I1(rd_pntr_gc), .Q({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst }), .wr_clk(wr_clk), .wr_rst(wr_rst)); fifo_generator_0synchronizer_ff_1 \gsync_stage[2].rd_stg_inst (.D(p_0_in[3:2]), .I1(Q), .Q({\n_2_gsync_stage[2].rd_stg_inst ,\n_3_gsync_stage[2].rd_stg_inst ,\n_4_gsync_stage[2].rd_stg_inst }), .rd_clk(rd_clk), .rd_rst(rd_rst)); fifo_generator_0synchronizer_ff_2 \gsync_stage[2].wr_stg_inst (.D({\n_0_gsync_stage[2].wr_stg_inst ,\n_1_gsync_stage[2].wr_stg_inst }), .I1({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst }), .Q({\n_2_gsync_stage[2].wr_stg_inst ,\n_3_gsync_stage[2].wr_stg_inst ,\n_4_gsync_stage[2].wr_stg_inst }), .wr_clk(wr_clk), .wr_rst(wr_rst)); LUT6 #( .INIT(64'h0010FFFF00100010)) ram_empty_i_i_1 (.I0(n_0_ram_empty_i_i_2), .I1(n_0_ram_empty_i_i_3), .I2(rd_en), .I3(p_18_out), .I4(n_0_ram_empty_i_i_4), .I5(n_0_ram_empty_i_i_5), .O(O1)); LUT4 #( .INIT(16'h6FF6)) ram_empty_i_i_2 (.I0(p_1_out[1]), .I1(I2[1]), .I2(p_1_out[0]), .I3(I2[0]), .O(n_0_ram_empty_i_i_2)); LUT4 #( .INIT(16'h6FF6)) ram_empty_i_i_3 (.I0(p_1_out[2]), .I1(I2[2]), .I2(p_1_out[3]), .I3(I2[3]), .O(n_0_ram_empty_i_i_3)); LUT4 #( .INIT(16'h6FF6)) ram_empty_i_i_4 (.I0(p_1_out[0]), .I1(I1[0]), .I2(p_1_out[2]), .I3(I1[2]), .O(n_0_ram_empty_i_i_4)); LUT4 #( .INIT(16'h9009)) ram_empty_i_i_5 (.I0(p_1_out[1]), .I1(I1[1]), .I2(p_1_out[3]), .I3(I1[3]), .O(n_0_ram_empty_i_i_5)); LUT6 #( .INIT(64'h9009000000009009)) ram_full_i_i_5 (.I0(O3[2]), .I1(I3[2]), .I2(O3[1]), .I3(I3[1]), .I4(I3[0]), .I5(O3[0]), .O(O2)); ( SOFT_HLUTNM = "soft_lutpair0" ) LUT4 #( .INIT(16'h6996)) \rd_pntr_bin[0]_i_1 (.I0(\n_3_gsync_stage[2].wr_stg_inst ), .I1(\n_4_gsync_stage[2].wr_stg_inst ), .I2(\n_0_gsync_stage[2].wr_stg_inst ), .I3(\n_2_gsync_stage[2].wr_stg_inst ), .O(\n_0_rd_pntr_bin[0]_i_1 )); ( SOFT_HLUTNM = "soft_lutpair0" ) LUT3 #( .INIT(8'h96)) \rd_pntr_bin[1]_i_1 (.I0(\n_2_gsync_stage[2].wr_stg_inst ), .I1(\n_3_gsync_stage[2].wr_stg_inst ), .I2(\n_0_gsync_stage[2].wr_stg_inst ), .O(\n_0_rd_pntr_bin[1]_i_1 )); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_0_rd_pntr_bin[0]_i_1 ), .Q(O3[0])); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_0_rd_pntr_bin[1]_i_1 ), .Q(O3[1])); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_1_gsync_stage[2].wr_stg_inst ), .Q(O3[2])); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_0_gsync_stage[2].wr_stg_inst ), .Q(O3[3])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(D[0]), .Q(rd_pntr_gc[0])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(D[1]), .Q(rd_pntr_gc[1])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(D[2]), .Q(rd_pntr_gc[2])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[3]), .Q(rd_pntr_gc[3])); ( SOFT_HLUTNM = "soft_lutpair1" ) LUT4 #( .INIT(16'h6996)) \wr_pntr_bin[0]_i_1 (.I0(\n_3_gsync_stage[2].rd_stg_inst ), .I1(\n_4_gsync_stage[2].rd_stg_inst ), .I2(p_0_in[3]), .I3(\n_2_gsync_stage[2].rd_stg_inst ), .O(p_0_in[0])); ( SOFT_HLUTNM = "soft_lutpair1" ) LUT3 #( .INIT(8'h96)) \wr_pntr_bin[1]_i_1 (.I0(\n_2_gsync_stage[2].rd_stg_inst ), .I1(\n_3_gsync_stage[2].rd_stg_inst ), .I2(p_0_in[3]), .O(p_0_in[1])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[0]), .Q(p_1_out[0])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[1]), .Q(p_1_out[1])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[2]), .Q(p_1_out[2])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[3]), .Q(p_1_out[3])); LUT2 #( .INIT(4'h6)) \wr_pntr_gc[0]_i_1 (.I0(I4[0]), .I1(I4[1]), .O(p_0_in1_out[0])); ( SOFT_HLUTNM = "soft_lutpair2" ) LUT2 #( .INIT(4'h6)) \wr_pntr_gc[1]_i_1 (.I0(I4[1]), .I1(I4[2]), .O(p_0_in1_out[1])); ( SOFT_HLUTNM = "soft_lutpair2" ) LUT2 #( .INIT(4'h6)) \wr_pntr_gc[2]_i_1 (.I0(I4[2]), .I1(I4[3]), .O(p_0_in1_out[2])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(p_0_in1_out[0]), .Q(wr_pntr_gc[0])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(p_0_in1_out[1]), .Q(wr_pntr_gc[1])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(p_0_in1_out[2]), .Q(wr_pntr_gc[2])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I4[3]), .Q(wr_pntr_gc[3])); endmodule ( ORIG_REF_NAME = "fifo_generator_ramfifo" ) module fifo_generator_0fifo_generator_ramfifo (dout, empty, valid, full, wr_en, rd_clk, wr_clk, rd_rst, din, wr_rst, rd_en); output [9:0]dout; output empty; output valid; output full; input wr_en; input rd_clk; input wr_clk; input rd_rst; input [9:0]din; input wr_rst; input rd_en; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire \n_0_gntv_or_sync_fifo.gcx.clkx ; wire \n_10_gntv_or_sync_fifo.gl0.rd ; wire \n_1_gntv_or_sync_fifo.gcx.clkx ; wire \n_8_gntv_or_sync_fifo.gl0.rd ; wire \n_9_gntv_or_sync_fifo.gl0.rd ; wire [3:0]p_0_out; wire p_18_out; wire [3:0]p_20_out; wire p_3_out; wire [2:0]p_8_out; wire [3:0]p_9_out; wire rd_clk; wire rd_en; wire [3:0]rd_pntr_plus1; wire rd_rst; wire rst_d2; wire rst_full_gen_i; wire tmp_ram_rd_en; wire valid; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx (.D({\n_8_gntv_or_sync_fifo.gl0.rd ,\n_9_gntv_or_sync_fifo.gl0.rd ,\n_10_gntv_or_sync_fifo.gl0.rd }), .I1(p_20_out), .I2(rd_pntr_plus1), .I3(p_8_out), .I4(p_9_out), .O1(\n_0_gntv_or_sync_fifo.gcx.clkx ), .O2(\n_1_gntv_or_sync_fifo.gcx.clkx ), .O3(p_0_out), .p_18_out(p_18_out), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .wr_clk(wr_clk), .wr_rst(wr_rst)); fifo_generator_0rd_logic \gntv_or_sync_fifo.gl0.rd (.D({\n_8_gntv_or_sync_fifo.gl0.rd ,\n_9_gntv_or_sync_fifo.gl0.rd ,\n_10_gntv_or_sync_fifo.gl0.rd }), .I1(\n_0_gntv_or_sync_fifo.gcx.clkx ), .O1(p_20_out), .Q(rd_pntr_plus1), .empty(empty), .p_18_out(p_18_out), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .valid(valid)); fifo_generator_0wr_logic \gntv_or_sync_fifo.gl0.wr (.E(p_3_out), .I1(\n_1_gntv_or_sync_fifo.gcx.clkx ), .O1(p_9_out), .O3(p_0_out), .Q(p_8_out), .full(full), .rst_d2(rst_d2), .rst_full_gen_i(rst_full_gen_i), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); fifo_generator_0memory \gntv_or_sync_fifo.mem (.E(p_3_out), .I1(p_9_out), .O1(p_20_out), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fifo_generator_0reset_blk_ramfifo rstblk (.rst_d2(rst_d2), .rst_full_gen_i(rst_full_gen_i), .wr_clk(wr_clk), .wr_rst(wr_rst)); endmodule ( ORIG_REF_NAME = "fifo_generator_top" ) module fifo_generator_0fifo_generator_top (dout, empty, valid, full, wr_en, rd_clk, wr_clk, rd_rst, din, wr_rst, rd_en); output [9:0]dout; output empty; output valid; output full; input wr_en; input rd_clk; input wr_clk; input rd_rst; input [9:0]din; input wr_rst; input rd_en; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire rd_clk; wire rd_en; wire rd_rst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0fifo_generator_ramfifo \grf.rf (.din(din), .dout(dout), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .valid(valid), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule ( ORIG_REF_NAME = "fifo_generator_v12_0" ) ( C_COMMON_CLOCK = "0" ) ( C_COUNT_TYPE = "0" ) ( C_DATA_COUNT_WIDTH = "4" ) ( C_DEFAULT_VALUE = "BlankString" ) ( C_DIN_WIDTH = "10" ) ( C_DOUT_RST_VAL = "0" ) ( C_DOUT_WIDTH = "10" ) ( C_ENABLE_RLOCS = "0" ) ( C_FAMILY = "zynq" ) ( C_FULL_FLAGS_RST_VAL = "1" ) ( C_HAS_ALMOST_EMPTY = "0" ) ( C_HAS_ALMOST_FULL = "0" ) ( C_HAS_BACKUP = "0" ) ( C_HAS_DATA_COUNT = "0" ) ( C_HAS_INT_CLK = "0" ) ( C_HAS_MEMINIT_FILE = "0" ) ( C_HAS_OVERFLOW = "0" ) ( C_HAS_RD_DATA_COUNT = "0" ) ( C_HAS_RD_RST = "0" ) ( C_HAS_RST = "1" ) ( C_HAS_SRST = "0" ) ( C_HAS_UNDERFLOW = "0" ) ( C_HAS_VALID = "1" ) ( C_HAS_WR_ACK = "0" ) ( C_HAS_WR_DATA_COUNT = "0" ) ( C_HAS_WR_RST = "0" ) ( C_IMPLEMENTATION_TYPE = "2" ) ( C_INIT_WR_PNTR_VAL = "0" ) ( C_MEMORY_TYPE = "1" ) ( C_MIF_FILE_NAME = "BlankString" ) ( C_OPTIMIZATION_MODE = "0" ) ( C_OVERFLOW_LOW = "0" ) ( C_PRELOAD_LATENCY = "1" ) ( C_PRELOAD_REGS = "0" ) ( C_PRIM_FIFO_TYPE = "512x36" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" ) ( C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" ) ( C_PROG_EMPTY_TYPE = "0" ) ( C_PROG_FULL_THRESH_ASSERT_VAL = "13" ) ( C_PROG_FULL_THRESH_NEGATE_VAL = "12" ) ( C_PROG_FULL_TYPE = "0" ) ( C_RD_DATA_COUNT_WIDTH = "4" ) ( C_RD_DEPTH = "16" ) ( C_RD_FREQ = "1" ) ( C_RD_PNTR_WIDTH = "4" ) ( C_UNDERFLOW_LOW = "0" ) ( C_USE_DOUT_RST = "1" ) ( C_USE_ECC = "0" ) ( C_USE_EMBEDDED_REG = "0" ) ( C_USE_PIPELINE_REG = "0" ) ( C_POWER_SAVING_MODE = "0" ) ( C_USE_FIFO16_FLAGS = "0" ) ( C_USE_FWFT_DATA_COUNT = "0" ) ( C_VALID_LOW = "0" ) ( C_WR_ACK_LOW = "0" ) ( C_WR_DATA_COUNT_WIDTH = "4" ) ( C_WR_DEPTH = "16" ) ( C_WR_FREQ = "1" ) ( C_WR_PNTR_WIDTH = "4" ) ( C_WR_RESPONSE_LATENCY = "1" ) ( C_MSGON_VAL = "1" ) ( C_ENABLE_RST_SYNC = "0" ) ( C_ERROR_INJECTION_TYPE = "0" ) ( C_SYNCHRONIZER_STAGE = "2" ) ( C_INTERFACE_TYPE = "0" ) ( C_AXI_TYPE = "1" ) ( C_HAS_AXI_WR_CHANNEL = "1" ) ( C_HAS_AXI_RD_CHANNEL = "1" ) ( C_HAS_SLAVE_CE = "0" ) ( C_HAS_MASTER_CE = "0" ) ( C_ADD_NGC_CONSTRAINT = "0" ) ( C_USE_COMMON_OVERFLOW = "0" ) ( C_USE_COMMON_UNDERFLOW = "0" ) ( C_USE_DEFAULT_SETTINGS = "0" ) ( C_AXI_ID_WIDTH = "1" ) ( C_AXI_ADDR_WIDTH = "32" ) ( C_AXI_DATA_WIDTH = "64" ) ( C_AXI_LEN_WIDTH = "8" ) ( C_AXI_LOCK_WIDTH = "1" ) ( C_HAS_AXI_ID = "0" ) ( C_HAS_AXI_AWUSER = "0" ) ( C_HAS_AXI_WUSER = "0" ) ( C_HAS_AXI_BUSER = "0" ) ( C_HAS_AXI_ARUSER = "0" ) ( C_HAS_AXI_RUSER = "0" ) ( C_AXI_ARUSER_WIDTH = "1" ) ( C_AXI_AWUSER_WIDTH = "1" ) ( C_AXI_WUSER_WIDTH = "1" ) ( C_AXI_BUSER_WIDTH = "1" ) ( C_AXI_RUSER_WIDTH = "1" ) ( C_HAS_AXIS_TDATA = "1" ) ( C_HAS_AXIS_TID = "0" ) ( C_HAS_AXIS_TDEST = "0" ) ( C_HAS_AXIS_TUSER = "1" ) ( C_HAS_AXIS_TREADY = "1" ) ( C_HAS_AXIS_TLAST = "0" ) ( C_HAS_AXIS_TSTRB = "0" ) ( C_HAS_AXIS_TKEEP = "0" ) ( C_AXIS_TDATA_WIDTH = "16" ) ( C_AXIS_TID_WIDTH = "1" ) ( C_AXIS_TDEST_WIDTH = "1" ) ( C_AXIS_TUSER_WIDTH = "4" ) ( C_AXIS_TSTRB_WIDTH = "2" ) ( C_AXIS_TKEEP_WIDTH = "2" ) ( C_WACH_TYPE = "0" ) ( C_WDCH_TYPE = "0" ) ( C_WRCH_TYPE = "0" ) ( C_RACH_TYPE = "0" ) ( C_RDCH_TYPE = "0" ) ( C_AXIS_TYPE = "0" ) ( C_IMPLEMENTATION_TYPE_WACH = "12" ) ( C_IMPLEMENTATION_TYPE_WDCH = "11" ) ( C_IMPLEMENTATION_TYPE_WRCH = "12" ) ( C_IMPLEMENTATION_TYPE_RACH = "12" ) ( C_IMPLEMENTATION_TYPE_RDCH = "11" ) ( C_IMPLEMENTATION_TYPE_AXIS = "11" ) ( C_APPLICATION_TYPE_WACH = "0" ) ( C_APPLICATION_TYPE_WDCH = "0" ) ( C_APPLICATION_TYPE_WRCH = "0" ) ( C_APPLICATION_TYPE_RACH = "0" ) ( C_APPLICATION_TYPE_RDCH = "0" ) ( C_APPLICATION_TYPE_AXIS = "0" ) ( C_PRIM_FIFO_TYPE_WACH = "512x36" ) ( C_PRIM_FIFO_TYPE_WDCH = "1kx36" ) ( C_PRIM_FIFO_TYPE_WRCH = "512x36" ) ( C_PRIM_FIFO_TYPE_RACH = "512x36" ) ( C_PRIM_FIFO_TYPE_RDCH = "1kx36" ) ( C_PRIM_FIFO_TYPE_AXIS = "1kx18" ) ( C_USE_ECC_WACH = "0" ) ( C_USE_ECC_WDCH = "0" ) ( C_USE_ECC_WRCH = "0" ) ( C_USE_ECC_RACH = "0" ) ( C_USE_ECC_RDCH = "0" ) ( C_USE_ECC_AXIS = "0" ) ( C_ERROR_INJECTION_TYPE_WACH = "0" ) ( C_ERROR_INJECTION_TYPE_WDCH = "0" ) ( C_ERROR_INJECTION_TYPE_WRCH = "0" ) ( C_ERROR_INJECTION_TYPE_RACH = "0" ) ( C_ERROR_INJECTION_TYPE_RDCH = "0" ) ( C_ERROR_INJECTION_TYPE_AXIS = "0" ) ( C_DIN_WIDTH_WACH = "32" ) ( C_DIN_WIDTH_WDCH = "64" ) ( C_DIN_WIDTH_WRCH = "2" ) ( C_DIN_WIDTH_RACH = "32" ) ( C_DIN_WIDTH_RDCH = "64" ) ( C_DIN_WIDTH_AXIS = "1" ) ( C_WR_DEPTH_WACH = "16" ) ( C_WR_DEPTH_WDCH = "1024" ) ( C_WR_DEPTH_WRCH = "16" ) ( C_WR_DEPTH_RACH = "16" ) ( C_WR_DEPTH_RDCH = "1024" ) ( C_WR_DEPTH_AXIS = "1024" ) ( C_WR_PNTR_WIDTH_WACH = "4" ) ( C_WR_PNTR_WIDTH_WDCH = "10" ) ( C_WR_PNTR_WIDTH_WRCH = "4" ) ( C_WR_PNTR_WIDTH_RACH = "4" ) ( C_WR_PNTR_WIDTH_RDCH = "10" ) ( C_WR_PNTR_WIDTH_AXIS = "10" ) ( C_HAS_DATA_COUNTS_WACH = "0" ) ( C_HAS_DATA_COUNTS_WDCH = "0" ) ( C_HAS_DATA_COUNTS_WRCH = "0" ) ( C_HAS_DATA_COUNTS_RACH = "0" ) ( C_HAS_DATA_COUNTS_RDCH = "0" ) ( C_HAS_DATA_COUNTS_AXIS = "0" ) ( C_HAS_PROG_FLAGS_WACH = "0" ) ( C_HAS_PROG_FLAGS_WDCH = "0" ) ( C_HAS_PROG_FLAGS_WRCH = "0" ) ( C_HAS_PROG_FLAGS_RACH = "0" ) ( C_HAS_PROG_FLAGS_RDCH = "0" ) ( C_HAS_PROG_FLAGS_AXIS = "0" ) ( C_PROG_FULL_TYPE_WACH = "0" ) ( C_PROG_FULL_TYPE_WDCH = "0" ) ( C_PROG_FULL_TYPE_WRCH = "0" ) ( C_PROG_FULL_TYPE_RACH = "0" ) ( C_PROG_FULL_TYPE_RDCH = "0" ) ( C_PROG_FULL_TYPE_AXIS = "0" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" ) ( C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" ) ( C_PROG_EMPTY_TYPE_WACH = "0" ) ( C_PROG_EMPTY_TYPE_WDCH = "0" ) ( C_PROG_EMPTY_TYPE_WRCH = "0" ) ( C_PROG_EMPTY_TYPE_RACH = "0" ) ( C_PROG_EMPTY_TYPE_RDCH = "0" ) ( C_PROG_EMPTY_TYPE_AXIS = "0" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" ) ( C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" ) ( C_REG_SLICE_MODE_WACH = "0" ) ( C_REG_SLICE_MODE_WDCH = "0" ) ( C_REG_SLICE_MODE_WRCH = "0" ) ( C_REG_SLICE_MODE_RACH = "0" ) ( C_REG_SLICE_MODE_RDCH = "0" ) ( C_REG_SLICE_MODE_AXIS = "0" ) module fifo_generator_0fifo_generator_v12_0__parameterized0 (backup, backup_marker, clk, rst, srst, wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, prog_empty_thresh, prog_empty_thresh_assert, prog_empty_thresh_negate, prog_full_thresh, prog_full_thresh_assert, prog_full_thresh_negate, int_clk, injectdbiterr, injectsbiterr, sleep, dout, full, almost_full, wr_ack, overflow, empty, almost_empty, valid, underflow, data_count, rd_data_count, wr_data_count, prog_full, prog_empty, sbiterr, dbiterr, wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, s_aresetn, m_aclk_en, s_aclk_en, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awregion, s_axi_awuser, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wuser, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_buser, s_axi_bvalid, s_axi_bready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awregion, m_axi_awuser, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wuser, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_buser, m_axi_bvalid, m_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arregion, s_axi_aruser, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_ruser, s_axi_rvalid, s_axi_rready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arregion, m_axi_aruser, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_ruser, m_axi_rvalid, m_axi_rready, s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tstrb, s_axis_tkeep, s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tstrb, m_axis_tkeep, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser, axi_aw_injectsbiterr, axi_aw_injectdbiterr, axi_aw_prog_full_thresh, axi_aw_prog_empty_thresh, axi_aw_data_count, axi_aw_wr_data_count, axi_aw_rd_data_count, axi_aw_sbiterr, axi_aw_dbiterr, axi_aw_overflow, axi_aw_underflow, axi_aw_prog_full, axi_aw_prog_empty, axi_w_injectsbiterr, axi_w_injectdbiterr, axi_w_prog_full_thresh, axi_w_prog_empty_thresh, axi_w_data_count, axi_w_wr_data_count, axi_w_rd_data_count, axi_w_sbiterr, axi_w_dbiterr, axi_w_overflow, axi_w_underflow, axi_w_prog_full, axi_w_prog_empty, axi_b_injectsbiterr, axi_b_injectdbiterr, axi_b_prog_full_thresh, axi_b_prog_empty_thresh, axi_b_data_count, axi_b_wr_data_count, axi_b_rd_data_count, axi_b_sbiterr, axi_b_dbiterr, axi_b_overflow, axi_b_underflow, axi_b_prog_full, axi_b_prog_empty, axi_ar_injectsbiterr, axi_ar_injectdbiterr, axi_ar_prog_full_thresh, axi_ar_prog_empty_thresh, axi_ar_data_count, axi_ar_wr_data_count, axi_ar_rd_data_count, axi_ar_sbiterr, axi_ar_dbiterr, axi_ar_overflow, axi_ar_underflow, axi_ar_prog_full, axi_ar_prog_empty, axi_r_injectsbiterr, axi_r_injectdbiterr, axi_r_prog_full_thresh, axi_r_prog_empty_thresh, axi_r_data_count, axi_r_wr_data_count, axi_r_rd_data_count, axi_r_sbiterr, axi_r_dbiterr, axi_r_overflow, axi_r_underflow, axi_r_prog_full, axi_r_prog_empty, axis_injectsbiterr, axis_injectdbiterr, axis_prog_full_thresh, axis_prog_empty_thresh, axis_data_count, axis_wr_data_count, axis_rd_data_count, axis_sbiterr, axis_dbiterr, axis_overflow, axis_underflow, axis_prog_full, axis_prog_empty); input backup; input backup_marker; input clk; input rst; input srst; input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [9:0]din; input wr_en; input rd_en; input [3:0]prog_empty_thresh; input [3:0]prog_empty_thresh_assert; input [3:0]prog_empty_thresh_negate; input [3:0]prog_full_thresh; input [3:0]prog_full_thresh_assert; input [3:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; input sleep; output [9:0]dout; output full; output almost_full; output wr_ack; output overflow; output empty; output almost_empty; output valid; output underflow; output [3:0]data_count; output [3:0]rd_data_count; output [3:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; output dbiterr; output wr_rst_busy; output rd_rst_busy; input m_aclk; input s_aclk; input s_aresetn; input m_aclk_en; input s_aclk_en; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input [3:0]s_axi_awregion; input [0:0]s_axi_awuser; input s_axi_awvalid; output s_axi_awready; input [0:0]s_axi_wid; input [63:0]s_axi_wdata; input [7:0]s_axi_wstrb; input s_axi_wlast; input [0:0]s_axi_wuser; input s_axi_wvalid; output s_axi_wready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output [0:0]s_axi_buser; output s_axi_bvalid; input s_axi_bready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awqos; output [3:0]m_axi_awregion; output [0:0]m_axi_awuser; output m_axi_awvalid; input m_axi_awready; output [0:0]m_axi_wid; output [63:0]m_axi_wdata; output [7:0]m_axi_wstrb; output m_axi_wlast; output [0:0]m_axi_wuser; output m_axi_wvalid; input m_axi_wready; input [0:0]m_axi_bid; input [1:0]m_axi_bresp; input [0:0]m_axi_buser; input m_axi_bvalid; output m_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input [3:0]s_axi_arregion; input [0:0]s_axi_aruser; input s_axi_arvalid; output s_axi_arready; output [0:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output [0:0]s_axi_ruser; output s_axi_rvalid; input s_axi_rready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; output [3:0]m_axi_arregion; output [0:0]m_axi_aruser; output m_axi_arvalid; input m_axi_arready; input [0:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; input [0:0]m_axi_ruser; input m_axi_rvalid; output m_axi_rready; input s_axis_tvalid; output s_axis_tready; input [15:0]s_axis_tdata; input [1:0]s_axis_tstrb; input [1:0]s_axis_tkeep; input s_axis_tlast; input [0:0]s_axis_tid; input [0:0]s_axis_tdest; input [3:0]s_axis_tuser; output m_axis_tvalid; input m_axis_tready; output [15:0]m_axis_tdata; output [1:0]m_axis_tstrb; output [1:0]m_axis_tkeep; output m_axis_tlast; output [0:0]m_axis_tid; output [0:0]m_axis_tdest; output [3:0]m_axis_tuser; input axi_aw_injectsbiterr; input axi_aw_injectdbiterr; input [3:0]axi_aw_prog_full_thresh; input [3:0]axi_aw_prog_empty_thresh; output [4:0]axi_aw_data_count; output [4:0]axi_aw_wr_data_count; output [4:0]axi_aw_rd_data_count; output axi_aw_sbiterr; output axi_aw_dbiterr; output axi_aw_overflow; output axi_aw_underflow; output axi_aw_prog_full; output axi_aw_prog_empty; input axi_w_injectsbiterr; input axi_w_injectdbiterr; input [9:0]axi_w_prog_full_thresh; input [9:0]axi_w_prog_empty_thresh; output [10:0]axi_w_data_count; output [10:0]axi_w_wr_data_count; output [10:0]axi_w_rd_data_count; output axi_w_sbiterr; output axi_w_dbiterr; output axi_w_overflow; output axi_w_underflow; output axi_w_prog_full; output axi_w_prog_empty; input axi_b_injectsbiterr; input axi_b_injectdbiterr; input [3:0]axi_b_prog_full_thresh; input [3:0]axi_b_prog_empty_thresh; output [4:0]axi_b_data_count; output [4:0]axi_b_wr_data_count; output [4:0]axi_b_rd_data_count; output axi_b_sbiterr; output axi_b_dbiterr; output axi_b_overflow; output axi_b_underflow; output axi_b_prog_full; output axi_b_prog_empty; input axi_ar_injectsbiterr; input axi_ar_injectdbiterr; input [3:0]axi_ar_prog_full_thresh; input [3:0]axi_ar_prog_empty_thresh; output [4:0]axi_ar_data_count; output [4:0]axi_ar_wr_data_count; output [4:0]axi_ar_rd_data_count; output axi_ar_sbiterr; output axi_ar_dbiterr; output axi_ar_overflow; output axi_ar_underflow; output axi_ar_prog_full; output axi_ar_prog_empty; input axi_r_injectsbiterr; input axi_r_injectdbiterr; input [9:0]axi_r_prog_full_thresh; input [9:0]axi_r_prog_empty_thresh; output [10:0]axi_r_data_count; output [10:0]axi_r_wr_data_count; output [10:0]axi_r_rd_data_count; output axi_r_sbiterr; output axi_r_dbiterr; output axi_r_overflow; output axi_r_underflow; output axi_r_prog_full; output axi_r_prog_empty; input axis_injectsbiterr; input axis_injectdbiterr; input [9:0]axis_prog_full_thresh; input [9:0]axis_prog_empty_thresh; output [10:0]axis_data_count; output [10:0]axis_wr_data_count; output [10:0]axis_rd_data_count; output axis_sbiterr; output axis_dbiterr; output axis_overflow; output axis_underflow; output axis_prog_full; output axis_prog_empty; wire \<const0> ; wire \<const1> ; wire axi_ar_injectdbiterr; wire axi_ar_injectsbiterr; wire [3:0]axi_ar_prog_empty_thresh; wire [3:0]axi_ar_prog_full_thresh; wire axi_aw_injectdbiterr; wire axi_aw_injectsbiterr; wire [3:0]axi_aw_prog_empty_thresh; wire [3:0]axi_aw_prog_full_thresh; wire axi_b_injectdbiterr; wire axi_b_injectsbiterr; wire [3:0]axi_b_prog_empty_thresh; wire [3:0]axi_b_prog_full_thresh; wire axi_r_injectdbiterr; wire axi_r_injectsbiterr; wire [9:0]axi_r_prog_empty_thresh; wire [9:0]axi_r_prog_full_thresh; wire axi_w_injectdbiterr; wire axi_w_injectsbiterr; wire [9:0]axi_w_prog_empty_thresh; wire [9:0]axi_w_prog_full_thresh; wire axis_injectdbiterr; wire axis_injectsbiterr; wire [9:0]axis_prog_empty_thresh; wire [9:0]axis_prog_full_thresh; wire backup; wire backup_marker; wire clk; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire injectdbiterr; wire injectsbiterr; wire int_clk; wire m_aclk; wire m_aclk_en; wire m_axi_arready; wire m_axi_awready; wire [0:0]m_axi_bid; wire [1:0]m_axi_bresp; wire [0:0]m_axi_buser; wire m_axi_bvalid; wire [63:0]m_axi_rdata; wire [0:0]m_axi_rid; wire m_axi_rlast; wire [1:0]m_axi_rresp; wire [0:0]m_axi_ruser; wire m_axi_rvalid; wire m_axi_wready; wire m_axis_tready; wire [3:0]prog_empty_thresh; wire [3:0]prog_empty_thresh_assert; wire [3:0]prog_empty_thresh_negate; wire [3:0]prog_full_thresh; wire [3:0]prog_full_thresh_assert; wire [3:0]prog_full_thresh_negate; wire rd_clk; wire rd_en; wire rd_rst; wire rst; wire s_aclk; wire s_aclk_en; wire s_aresetn; wire [31:0]s_axi_araddr; wire [1:0]s_axi_arburst; wire [3:0]s_axi_arcache; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire [0:0]s_axi_arlock; wire [2:0]s_axi_arprot; wire [3:0]s_axi_arqos; wire [3:0]s_axi_arregion; wire [2:0]s_axi_arsize; wire [0:0]s_axi_aruser; wire s_axi_arvalid; wire [31:0]s_axi_awaddr; wire [1:0]s_axi_awburst; wire [3:0]s_axi_awcache; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire [0:0]s_axi_awlock; wire [2:0]s_axi_awprot; wire [3:0]s_axi_awqos; wire [3:0]s_axi_awregion; wire [2:0]s_axi_awsize; wire [0:0]s_axi_awuser; wire s_axi_awvalid; wire s_axi_bready; wire s_axi_rready; wire [63:0]s_axi_wdata; wire [0:0]s_axi_wid; wire s_axi_wlast; wire [7:0]s_axi_wstrb; wire [0:0]s_axi_wuser; wire s_axi_wvalid; wire [15:0]s_axis_tdata; wire [0:0]s_axis_tdest; wire [0:0]s_axis_tid; wire [1:0]s_axis_tkeep; wire s_axis_tlast; wire [1:0]s_axis_tstrb; wire [3:0]s_axis_tuser; wire s_axis_tvalid; wire srst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; assign almost_empty = \<const0> ; assign almost_full = \<const0> ; assign axi_ar_data_count[4] = \<const0> ; assign axi_ar_data_count[3] = \<const0> ; assign axi_ar_data_count[2] = \<const0> ; assign axi_ar_data_count[1] = \<const0> ; assign axi_ar_data_count[0] = \<const0> ; assign axi_ar_dbiterr = \<const0> ; assign axi_ar_overflow = \<const0> ; assign axi_ar_prog_empty = \<const1> ; assign axi_ar_prog_full = \<const0> ; assign axi_ar_rd_data_count[4] = \<const0> ; assign axi_ar_rd_data_count[3] = \<const0> ; assign axi_ar_rd_data_count[2] = \<const0> ; assign axi_ar_rd_data_count[1] = \<const0> ; assign axi_ar_rd_data_count[0] = \<const0> ; assign axi_ar_sbiterr = \<const0> ; assign axi_ar_underflow = \<const0> ; assign axi_ar_wr_data_count[4] = \<const0> ; assign axi_ar_wr_data_count[3] = \<const0> ; assign axi_ar_wr_data_count[2] = \<const0> ; assign axi_ar_wr_data_count[1] = \<const0> ; assign axi_ar_wr_data_count[0] = \<const0> ; assign axi_aw_data_count[4] = \<const0> ; assign axi_aw_data_count[3] = \<const0> ; assign axi_aw_data_count[2] = \<const0> ; assign axi_aw_data_count[1] = \<const0> ; assign axi_aw_data_count[0] = \<const0> ; assign axi_aw_dbiterr = \<const0> ; assign axi_aw_overflow = \<const0> ; assign axi_aw_prog_empty = \<const1> ; assign axi_aw_prog_full = \<const0> ; assign axi_aw_rd_data_count[4] = \<const0> ; assign axi_aw_rd_data_count[3] = \<const0> ; assign axi_aw_rd_data_count[2] = \<const0> ; assign axi_aw_rd_data_count[1] = \<const0> ; assign axi_aw_rd_data_count[0] = \<const0> ; assign axi_aw_sbiterr = \<const0> ; assign axi_aw_underflow = \<const0> ; assign axi_aw_wr_data_count[4] = \<const0> ; assign axi_aw_wr_data_count[3] = \<const0> ; assign axi_aw_wr_data_count[2] = \<const0> ; assign axi_aw_wr_data_count[1] = \<const0> ; assign axi_aw_wr_data_count[0] = \<const0> ; assign axi_b_data_count[4] = \<const0> ; assign axi_b_data_count[3] = \<const0> ; assign axi_b_data_count[2] = \<const0> ; assign axi_b_data_count[1] = \<const0> ; assign axi_b_data_count[0] = \<const0> ; assign axi_b_dbiterr = \<const0> ; assign axi_b_overflow = \<const0> ; assign axi_b_prog_empty = \<const1> ; assign axi_b_prog_full = \<const0> ; assign axi_b_rd_data_count[4] = \<const0> ; assign axi_b_rd_data_count[3] = \<const0> ; assign axi_b_rd_data_count[2] = \<const0> ; assign axi_b_rd_data_count[1] = \<const0> ; assign axi_b_rd_data_count[0] = \<const0> ; assign axi_b_sbiterr = \<const0> ; assign axi_b_underflow = \<const0> ; assign axi_b_wr_data_count[4] = \<const0> ; assign axi_b_wr_data_count[3] = \<const0> ; assign axi_b_wr_data_count[2] = \<const0> ; assign axi_b_wr_data_count[1] = \<const0> ; assign axi_b_wr_data_count[0] = \<const0> ; assign axi_r_data_count[10] = \<const0> ; assign axi_r_data_count[9] = \<const0> ; assign axi_r_data_count[8] = \<const0> ; assign axi_r_data_count[7] = \<const0> ; assign axi_r_data_count[6] = \<const0> ; assign axi_r_data_count[5] = \<const0> ; assign axi_r_data_count[4] = \<const0> ; assign axi_r_data_count[3] = \<const0> ; assign axi_r_data_count[2] = \<const0> ; assign axi_r_data_count[1] = \<const0> ; assign axi_r_data_count[0] = \<const0> ; assign axi_r_dbiterr = \<const0> ; assign axi_r_overflow = \<const0> ; assign axi_r_prog_empty = \<const1> ; assign axi_r_prog_full = \<const0> ; assign axi_r_rd_data_count[10] = \<const0> ; assign axi_r_rd_data_count[9] = \<const0> ; assign axi_r_rd_data_count[8] = \<const0> ; assign axi_r_rd_data_count[7] = \<const0> ; assign axi_r_rd_data_count[6] = \<const0> ; assign axi_r_rd_data_count[5] = \<const0> ; assign axi_r_rd_data_count[4] = \<const0> ; assign axi_r_rd_data_count[3] = \<const0> ; assign axi_r_rd_data_count[2] = \<const0> ; assign axi_r_rd_data_count[1] = \<const0> ; assign axi_r_rd_data_count[0] = \<const0> ; assign axi_r_sbiterr = \<const0> ; assign axi_r_underflow = \<const0> ; assign axi_r_wr_data_count[10] = \<const0> ; assign axi_r_wr_data_count[9] = \<const0> ; assign axi_r_wr_data_count[8] = \<const0> ; assign axi_r_wr_data_count[7] = \<const0> ; assign axi_r_wr_data_count[6] = \<const0> ; assign axi_r_wr_data_count[5] = \<const0> ; assign axi_r_wr_data_count[4] = \<const0> ; assign axi_r_wr_data_count[3] = \<const0> ; assign axi_r_wr_data_count[2] = \<const0> ; assign axi_r_wr_data_count[1] = \<const0> ; assign axi_r_wr_data_count[0] = \<const0> ; assign axi_w_data_count[10] = \<const0> ; assign axi_w_data_count[9] = \<const0> ; assign axi_w_data_count[8] = \<const0> ; assign axi_w_data_count[7] = \<const0> ; assign axi_w_data_count[6] = \<const0> ; assign axi_w_data_count[5] = \<const0> ; assign axi_w_data_count[4] = \<const0> ; assign axi_w_data_count[3] = \<const0> ; assign axi_w_data_count[2] = \<const0> ; assign axi_w_data_count[1] = \<const0> ; assign axi_w_data_count[0] = \<const0> ; assign axi_w_dbiterr = \<const0> ; assign axi_w_overflow = \<const0> ; assign axi_w_prog_empty = \<const1> ; assign axi_w_prog_full = \<const0> ; assign axi_w_rd_data_count[10] = \<const0> ; assign axi_w_rd_data_count[9] = \<const0> ; assign axi_w_rd_data_count[8] = \<const0> ; assign axi_w_rd_data_count[7] = \<const0> ; assign axi_w_rd_data_count[6] = \<const0> ; assign axi_w_rd_data_count[5] = \<const0> ; assign axi_w_rd_data_count[4] = \<const0> ; assign axi_w_rd_data_count[3] = \<const0> ; assign axi_w_rd_data_count[2] = \<const0> ; assign axi_w_rd_data_count[1] = \<const0> ; assign axi_w_rd_data_count[0] = \<const0> ; assign axi_w_sbiterr = \<const0> ; assign axi_w_underflow = \<const0> ; assign axi_w_wr_data_count[10] = \<const0> ; assign axi_w_wr_data_count[9] = \<const0> ; assign axi_w_wr_data_count[8] = \<const0> ; assign axi_w_wr_data_count[7] = \<const0> ; assign axi_w_wr_data_count[6] = \<const0> ; assign axi_w_wr_data_count[5] = \<const0> ; assign axi_w_wr_data_count[4] = \<const0> ; assign axi_w_wr_data_count[3] = \<const0> ; assign axi_w_wr_data_count[2] = \<const0> ; assign axi_w_wr_data_count[1] = \<const0> ; assign axi_w_wr_data_count[0] = \<const0> ; assign axis_data_count[10] = \<const0> ; assign axis_data_count[9] = \<const0> ; assign axis_data_count[8] = \<const0> ; assign axis_data_count[7] = \<const0> ; assign axis_data_count[6] = \<const0> ; assign axis_data_count[5] = \<const0> ; assign axis_data_count[4] = \<const0> ; assign axis_data_count[3] = \<const0> ; assign axis_data_count[2] = \<const0> ; assign axis_data_count[1] = \<const0> ; assign axis_data_count[0] = \<const0> ; assign axis_dbiterr = \<const0> ; assign axis_overflow = \<const0> ; assign axis_prog_empty = \<const1> ; assign axis_prog_full = \<const0> ; assign axis_rd_data_count[10] = \<const0> ; assign axis_rd_data_count[9] = \<const0> ; assign axis_rd_data_count[8] = \<const0> ; assign axis_rd_data_count[7] = \<const0> ; assign axis_rd_data_count[6] = \<const0> ; assign axis_rd_data_count[5] = \<const0> ; assign axis_rd_data_count[4] = \<const0> ; assign axis_rd_data_count[3] = \<const0> ; assign axis_rd_data_count[2] = \<const0> ; assign axis_rd_data_count[1] = \<const0> ; assign axis_rd_data_count[0] = \<const0> ; assign axis_sbiterr = \<const0> ; assign axis_underflow = \<const0> ; assign axis_wr_data_count[10] = \<const0> ; assign axis_wr_data_count[9] = \<const0> ; assign axis_wr_data_count[8] = \<const0> ; assign axis_wr_data_count[7] = \<const0> ; assign axis_wr_data_count[6] = \<const0> ; assign axis_wr_data_count[5] = \<const0> ; assign axis_wr_data_count[4] = \<const0> ; assign axis_wr_data_count[3] = \<const0> ; assign axis_wr_data_count[2] = \<const0> ; assign axis_wr_data_count[1] = \<const0> ; assign axis_wr_data_count[0] = \<const0> ; assign data_count[3] = \<const0> ; assign data_count[2] = \<const0> ; assign data_count[1] = \<const0> ; assign data_count[0] = \<const0> ; assign dbiterr = \<const0> ; assign m_axi_araddr[31] = \<const0> ; assign m_axi_araddr[30] = \<const0> ; assign m_axi_araddr[29] = \<const0> ; assign m_axi_araddr[28] = \<const0> ; assign m_axi_araddr[27] = \<const0> ; assign m_axi_araddr[26] = \<const0> ; assign m_axi_araddr[25] = \<const0> ; assign m_axi_araddr[24] = \<const0> ; assign m_axi_araddr[23] = \<const0> ; assign m_axi_araddr[22] = \<const0> ; assign m_axi_araddr[21] = \<const0> ; assign m_axi_araddr[20] = \<const0> ; assign m_axi_araddr[19] = \<const0> ; assign m_axi_araddr[18] = \<const0> ; assign m_axi_araddr[17] = \<const0> ; assign m_axi_araddr[16] = \<const0> ; assign m_axi_araddr[15] = \<const0> ; assign m_axi_araddr[14] = \<const0> ; assign m_axi_araddr[13] = \<const0> ; assign m_axi_araddr[12] = \<const0> ; assign m_axi_araddr[11] = \<const0> ; assign m_axi_araddr[10] = \<const0> ; assign m_axi_araddr[9] = \<const0> ; assign m_axi_araddr[8] = \<const0> ; assign m_axi_araddr[7] = \<const0> ; assign m_axi_araddr[6] = \<const0> ; assign m_axi_araddr[5] = \<const0> ; assign m_axi_araddr[4] = \<const0> ; assign m_axi_araddr[3] = \<const0> ; assign m_axi_araddr[2] = \<const0> ; assign m_axi_araddr[1] = \<const0> ; assign m_axi_araddr[0] = \<const0> ; assign m_axi_arburst[1] = \<const0> ; assign m_axi_arburst[0] = \<const0> ; assign m_axi_arcache[3] = \<const0> ; assign m_axi_arcache[2] = \<const0> ; assign m_axi_arcache[1] = \<const0> ; assign m_axi_arcache[0] = \<const0> ; assign m_axi_arid[0] = \<const0> ; assign m_axi_arlen[7] = \<const0> ; assign m_axi_arlen[6] = \<const0> ; assign m_axi_arlen[5] = \<const0> ; assign m_axi_arlen[4] = \<const0> ; assign m_axi_arlen[3] = \<const0> ; assign m_axi_arlen[2] = \<const0> ; assign m_axi_arlen[1] = \<const0> ; assign m_axi_arlen[0] = \<const0> ; assign m_axi_arlock[0] = \<const0> ; assign m_axi_arprot[2] = \<const0> ; assign m_axi_arprot[1] = \<const0> ; assign m_axi_arprot[0] = \<const0> ; assign m_axi_arqos[3] = \<const0> ; assign m_axi_arqos[2] = \<const0> ; assign m_axi_arqos[1] = \<const0> ; assign m_axi_arqos[0] = \<const0> ; assign m_axi_arregion[3] = \<const0> ; assign m_axi_arregion[2] = \<const0> ; assign m_axi_arregion[1] = \<const0> ; assign m_axi_arregion[0] = \<const0> ; assign m_axi_arsize[2] = \<const0> ; assign m_axi_arsize[1] = \<const0> ; assign m_axi_arsize[0] = \<const0> ; assign m_axi_aruser[0] = \<const0> ; assign m_axi_arvalid = \<const0> ; assign m_axi_awaddr[31] = \<const0> ; assign m_axi_awaddr[30] = \<const0> ; assign m_axi_awaddr[29] = \<const0> ; assign m_axi_awaddr[28] = \<const0> ; assign m_axi_awaddr[27] = \<const0> ; assign m_axi_awaddr[26] = \<const0> ; assign m_axi_awaddr[25] = \<const0> ; assign m_axi_awaddr[24] = \<const0> ; assign m_axi_awaddr[23] = \<const0> ; assign m_axi_awaddr[22] = \<const0> ; assign m_axi_awaddr[21] = \<const0> ; assign m_axi_awaddr[20] = \<const0> ; assign m_axi_awaddr[19] = \<const0> ; assign m_axi_awaddr[18] = \<const0> ; assign m_axi_awaddr[17] = \<const0> ; assign m_axi_awaddr[16] = \<const0> ; assign m_axi_awaddr[15] = \<const0> ; assign m_axi_awaddr[14] = \<const0> ; assign m_axi_awaddr[13] = \<const0> ; assign m_axi_awaddr[12] = \<const0> ; assign m_axi_awaddr[11] = \<const0> ; assign m_axi_awaddr[10] = \<const0> ; assign m_axi_awaddr[9] = \<const0> ; assign m_axi_awaddr[8] = \<const0> ; assign m_axi_awaddr[7] = \<const0> ; assign m_axi_awaddr[6] = \<const0> ; assign m_axi_awaddr[5] = \<const0> ; assign m_axi_awaddr[4] = \<const0> ; assign m_axi_awaddr[3] = \<const0> ; assign m_axi_awaddr[2] = \<const0> ; assign m_axi_awaddr[1] = \<const0> ; assign m_axi_awaddr[0] = \<const0> ; assign m_axi_awburst[1] = \<const0> ; assign m_axi_awburst[0] = \<const0> ; assign m_axi_awcache[3] = \<const0> ; assign m_axi_awcache[2] = \<const0> ; assign m_axi_awcache[1] = \<const0> ; assign m_axi_awcache[0] = \<const0> ; assign m_axi_awid[0] = \<const0> ; assign m_axi_awlen[7] = \<const0> ; assign m_axi_awlen[6] = \<const0> ; assign m_axi_awlen[5] = \<const0> ; assign m_axi_awlen[4] = \<const0> ; assign m_axi_awlen[3] = \<const0> ; assign m_axi_awlen[2] = \<const0> ; assign m_axi_awlen[1] = \<const0> ; assign m_axi_awlen[0] = \<const0> ; assign m_axi_awlock[0] = \<const0> ; assign m_axi_awprot[2] = \<const0> ; assign m_axi_awprot[1] = \<const0> ; assign m_axi_awprot[0] = \<const0> ; assign m_axi_awqos[3] = \<const0> ; assign m_axi_awqos[2] = \<const0> ; assign m_axi_awqos[1] = \<const0> ; assign m_axi_awqos[0] = \<const0> ; assign m_axi_awregion[3] = \<const0> ; assign m_axi_awregion[2] = \<const0> ; assign m_axi_awregion[1] = \<const0> ; assign m_axi_awregion[0] = \<const0> ; assign m_axi_awsize[2] = \<const0> ; assign m_axi_awsize[1] = \<const0> ; assign m_axi_awsize[0] = \<const0> ; assign m_axi_awuser[0] = \<const0> ; assign m_axi_awvalid = \<const0> ; assign m_axi_bready = \<const0> ; assign m_axi_rready = \<const0> ; assign m_axi_wdata[63] = \<const0> ; assign m_axi_wdata[62] = \<const0> ; assign m_axi_wdata[61] = \<const0> ; assign m_axi_wdata[60] = \<const0> ; assign m_axi_wdata[59] = \<const0> ; assign m_axi_wdata[58] = \<const0> ; assign m_axi_wdata[57] = \<const0> ; assign m_axi_wdata[56] = \<const0> ; assign m_axi_wdata[55] = \<const0> ; assign m_axi_wdata[54] = \<const0> ; assign m_axi_wdata[53] = \<const0> ; assign m_axi_wdata[52] = \<const0> ; assign m_axi_wdata[51] = \<const0> ; assign m_axi_wdata[50] = \<const0> ; assign m_axi_wdata[49] = \<const0> ; assign m_axi_wdata[48] = \<const0> ; assign m_axi_wdata[47] = \<const0> ; assign m_axi_wdata[46] = \<const0> ; assign m_axi_wdata[45] = \<const0> ; assign m_axi_wdata[44] = \<const0> ; assign m_axi_wdata[43] = \<const0> ; assign m_axi_wdata[42] = \<const0> ; assign m_axi_wdata[41] = \<const0> ; assign m_axi_wdata[40] = \<const0> ; assign m_axi_wdata[39] = \<const0> ; assign m_axi_wdata[38] = \<const0> ; assign m_axi_wdata[37] = \<const0> ; assign m_axi_wdata[36] = \<const0> ; assign m_axi_wdata[35] = \<const0> ; assign m_axi_wdata[34] = \<const0> ; assign m_axi_wdata[33] = \<const0> ; assign m_axi_wdata[32] = \<const0> ; assign m_axi_wdata[31] = \<const0> ; assign m_axi_wdata[30] = \<const0> ; assign m_axi_wdata[29] = \<const0> ; assign m_axi_wdata[28] = \<const0> ; assign m_axi_wdata[27] = \<const0> ; assign m_axi_wdata[26] = \<const0> ; assign m_axi_wdata[25] = \<const0> ; assign m_axi_wdata[24] = \<const0> ; assign m_axi_wdata[23] = \<const0> ; assign m_axi_wdata[22] = \<const0> ; assign m_axi_wdata[21] = \<const0> ; assign m_axi_wdata[20] = \<const0> ; assign m_axi_wdata[19] = \<const0> ; assign m_axi_wdata[18] = \<const0> ; assign m_axi_wdata[17] = \<const0> ; assign m_axi_wdata[16] = \<const0> ; assign m_axi_wdata[15] = \<const0> ; assign m_axi_wdata[14] = \<const0> ; assign m_axi_wdata[13] = \<const0> ; assign m_axi_wdata[12] = \<const0> ; assign m_axi_wdata[11] = \<const0> ; assign m_axi_wdata[10] = \<const0> ; assign m_axi_wdata[9] = \<const0> ; assign m_axi_wdata[8] = \<const0> ; assign m_axi_wdata[7] = \<const0> ; assign m_axi_wdata[6] = \<const0> ; assign m_axi_wdata[5] = \<const0> ; assign m_axi_wdata[4] = \<const0> ; assign m_axi_wdata[3] = \<const0> ; assign m_axi_wdata[2] = \<const0> ; assign m_axi_wdata[1] = \<const0> ; assign m_axi_wdata[0] = \<const0> ; assign m_axi_wid[0] = \<const0> ; assign m_axi_wlast = \<const0> ; assign m_axi_wstrb[7] = \<const0> ; assign m_axi_wstrb[6] = \<const0> ; assign m_axi_wstrb[5] = \<const0> ; assign m_axi_wstrb[4] = \<const0> ; assign m_axi_wstrb[3] = \<const0> ; assign m_axi_wstrb[2] = \<const0> ; assign m_axi_wstrb[1] = \<const0> ; assign m_axi_wstrb[0] = \<const0> ; assign m_axi_wuser[0] = \<const0> ; assign m_axi_wvalid = \<const0> ; assign m_axis_tdata[15] = \<const0> ; assign m_axis_tdata[14] = \<const0> ; assign m_axis_tdata[13] = \<const0> ; assign m_axis_tdata[12] = \<const0> ; assign m_axis_tdata[11] = \<const0> ; assign m_axis_tdata[10] = \<const0> ; assign m_axis_tdata[9] = \<const0> ; assign m_axis_tdata[8] = \<const0> ; assign m_axis_tdata[7] = \<const0> ; assign m_axis_tdata[6] = \<const0> ; assign m_axis_tdata[5] = \<const0> ; assign m_axis_tdata[4] = \<const0> ; assign m_axis_tdata[3] = \<const0> ; assign m_axis_tdata[2] = \<const0> ; assign m_axis_tdata[1] = \<const0> ; assign m_axis_tdata[0] = \<const0> ; assign m_axis_tdest[0] = \<const0> ; assign m_axis_tid[0] = \<const0> ; assign m_axis_tkeep[1] = \<const0> ; assign m_axis_tkeep[0] = \<const0> ; assign m_axis_tlast = \<const0> ; assign m_axis_tstrb[1] = \<const0> ; assign m_axis_tstrb[0] = \<const0> ; assign m_axis_tuser[3] = \<const0> ; assign m_axis_tuser[2] = \<const0> ; assign m_axis_tuser[1] = \<const0> ; assign m_axis_tuser[0] = \<const0> ; assign m_axis_tvalid = \<const0> ; assign overflow = \<const0> ; assign prog_empty = \<const0> ; assign prog_full = \<const0> ; assign rd_data_count[3] = \<const0> ; assign rd_data_count[2] = \<const0> ; assign rd_data_count[1] = \<const0> ; assign rd_data_count[0] = \<const0> ; assign rd_rst_busy = \<const0> ; assign s_axi_arready = \<const0> ; assign s_axi_awready = \<const0> ; assign s_axi_bid[0] = \<const0> ; assign s_axi_bresp[1] = \<const0> ; assign s_axi_bresp[0] = \<const0> ; assign s_axi_buser[0] = \<const0> ; assign s_axi_bvalid = \<const0> ; assign s_axi_rdata[63] = \<const0> ; assign s_axi_rdata[62] = \<const0> ; assign s_axi_rdata[61] = \<const0> ; assign s_axi_rdata[60] = \<const0> ; assign s_axi_rdata[59] = \<const0> ; assign s_axi_rdata[58] = \<const0> ; assign s_axi_rdata[57] = \<const0> ; assign s_axi_rdata[56] = \<const0> ; assign s_axi_rdata[55] = \<const0> ; assign s_axi_rdata[54] = \<const0> ; assign s_axi_rdata[53] = \<const0> ; assign s_axi_rdata[52] = \<const0> ; assign s_axi_rdata[51] = \<const0> ; assign s_axi_rdata[50] = \<const0> ; assign s_axi_rdata[49] = \<const0> ; assign s_axi_rdata[48] = \<const0> ; assign s_axi_rdata[47] = \<const0> ; assign s_axi_rdata[46] = \<const0> ; assign s_axi_rdata[45] = \<const0> ; assign s_axi_rdata[44] = \<const0> ; assign s_axi_rdata[43] = \<const0> ; assign s_axi_rdata[42] = \<const0> ; assign s_axi_rdata[41] = \<const0> ; assign s_axi_rdata[40] = \<const0> ; assign s_axi_rdata[39] = \<const0> ; assign s_axi_rdata[38] = \<const0> ; assign s_axi_rdata[37] = \<const0> ; assign s_axi_rdata[36] = \<const0> ; assign s_axi_rdata[35] = \<const0> ; assign s_axi_rdata[34] = \<const0> ; assign s_axi_rdata[33] = \<const0> ; assign s_axi_rdata[32] = \<const0> ; assign s_axi_rdata[31] = \<const0> ; assign s_axi_rdata[30] = \<const0> ; assign s_axi_rdata[29] = \<const0> ; assign s_axi_rdata[28] = \<const0> ; assign s_axi_rdata[27] = \<const0> ; assign s_axi_rdata[26] = \<const0> ; assign s_axi_rdata[25] = \<const0> ; assign s_axi_rdata[24] = \<const0> ; assign s_axi_rdata[23] = \<const0> ; assign s_axi_rdata[22] = \<const0> ; assign s_axi_rdata[21] = \<const0> ; assign s_axi_rdata[20] = \<const0> ; assign s_axi_rdata[19] = \<const0> ; assign s_axi_rdata[18] = \<const0> ; assign s_axi_rdata[17] = \<const0> ; assign s_axi_rdata[16] = \<const0> ; assign s_axi_rdata[15] = \<const0> ; assign s_axi_rdata[14] = \<const0> ; assign s_axi_rdata[13] = \<const0> ; assign s_axi_rdata[12] = \<const0> ; assign s_axi_rdata[11] = \<const0> ; assign s_axi_rdata[10] = \<const0> ; assign s_axi_rdata[9] = \<const0> ; assign s_axi_rdata[8] = \<const0> ; assign s_axi_rdata[7] = \<const0> ; assign s_axi_rdata[6] = \<const0> ; assign s_axi_rdata[5] = \<const0> ; assign s_axi_rdata[4] = \<const0> ; assign s_axi_rdata[3] = \<const0> ; assign s_axi_rdata[2] = \<const0> ; assign s_axi_rdata[1] = \<const0> ; assign s_axi_rdata[0] = \<const0> ; assign s_axi_rid[0] = \<const0> ; assign s_axi_rlast = \<const0> ; assign s_axi_rresp[1] = \<const0> ; assign s_axi_rresp[0] = \<const0> ; assign s_axi_ruser[0] = \<const0> ; assign s_axi_rvalid = \<const0> ; assign s_axi_wready = \<const0> ; assign s_axis_tready = \<const0> ; assign sbiterr = \<const0> ; assign underflow = \<const0> ; assign wr_ack = \<const0> ; assign wr_data_count[3] = \<const0> ; assign wr_data_count[2] = \<const0> ; assign wr_data_count[1] = \<const0> ; assign wr_data_count[0] = \<const0> ; assign wr_rst_busy = \<const0> ; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); fifo_generator_0fifo_generator_v12_0_synth inst_fifo_gen (.din(din), .dout(dout), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .valid(valid), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule ( ORIG_REF_NAME = "fifo_generator_v12_0_synth" ) module fifo_generator_0fifo_generator_v12_0_synth (dout, empty, valid, full, wr_en, rd_clk, wr_clk, rd_rst, din, wr_rst, rd_en); output [9:0]dout; output empty; output valid; output full; input wr_en; input rd_clk; input wr_clk; input rd_rst; input [9:0]din; input wr_rst; input rd_en; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire rd_clk; wire rd_en; wire rd_rst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0fifo_generator_top \gconvfifo.rf (.din(din), .dout(dout), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .valid(valid), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule ( ORIG_REF_NAME = "memory" ) module fifo_generator_0memory (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_v8_2__parameterized0 \gbm.gbmg.gbmga.ngecc.bmg (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule ( ORIG_REF_NAME = "rd_bin_cntr" ) module fifo_generator_0rd_bin_cntr (Q, D, O1, E, rd_clk, rd_rst); output [3:0]Q; output [2:0]D; output [3:0]O1; input [0:0]E; input rd_clk; input rd_rst; wire [2:0]D; wire [0:0]E; wire [3:0]O1; wire [3:0]Q; wire [3:0]plusOp; wire rd_clk; wire rd_rst; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1 (.I0(Q[0]), .O(plusOp[0])); LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(plusOp[1])); ( SOFT_HLUTNM = "soft_lutpair4" ) LUT3 #( .INIT(8'h6A)) \gc0.count[2]_i_1 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .O(plusOp[2])); ( SOFT_HLUTNM = "soft_lutpair4" ) LUT4 #( .INIT(16'h6AAA)) \gc0.count[3]_i_1 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .O(plusOp[3])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[0]), .Q(O1[0])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[1]), .Q(O1[1])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[2]), .Q(O1[2])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[3]), .Q(O1[3])); ( counter = "2" ) FDPE #( .INIT(1'b1)) \gc0.count_reg[0] (.C(rd_clk), .CE(E), .D(plusOp[0]), .PRE(rd_rst), .Q(Q[0])); ( counter = "2" ) FDCE #( .INIT(1'b0)) \gc0.count_reg[1] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(plusOp[1]), .Q(Q[1])); ( counter = "2" ) FDCE #( .INIT(1'b0)) \gc0.count_reg[2] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(plusOp[2]), .Q(Q[2])); ( counter = "2" ) FDCE #( .INIT(1'b0)) \gc0.count_reg[3] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(plusOp[3]), .Q(Q[3])); ( SOFT_HLUTNM = "soft_lutpair5" ) LUT2 #( .INIT(4'h6)) \rd_pntr_gc[0]_i_1 (.I0(O1[1]), .I1(O1[0]), .O(D[0])); ( SOFT_HLUTNM = "soft_lutpair5" ) LUT2 #( .INIT(4'h6)) \rd_pntr_gc[1]_i_1 (.I0(O1[1]), .I1(O1[2]), .O(D[1])); LUT2 #( .INIT(4'h6)) \rd_pntr_gc[2]_i_1 (.I0(O1[2]), .I1(O1[3]), .O(D[2])); endmodule ( ORIG_REF_NAME = "rd_handshaking_flags" ) module fifo_generator_0rd_handshaking_flags (valid, ram_valid_i, rd_clk, rd_rst); output valid; input ram_valid_i; input rd_clk; input rd_rst; wire ram_valid_i; wire rd_clk; wire rd_rst; wire valid; FDCE #( .INIT(1'b0)) \gv.ram_valid_d1_reg (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(ram_valid_i), .Q(valid)); endmodule ( ORIG_REF_NAME = "rd_logic" ) module fifo_generator_0rd_logic (empty, p_18_out, valid, Q, tmp_ram_rd_en, D, O1, I1, rd_clk, rd_rst, rd_en); output empty; output p_18_out; output valid; output [3:0]Q; output tmp_ram_rd_en; output [2:0]D; output [3:0]O1; input I1; input rd_clk; input rd_rst; input rd_en; wire [2:0]D; wire I1; wire [3:0]O1; wire [3:0]Q; wire empty; wire p_14_out; wire p_18_out; wire ram_valid_i; wire rd_clk; wire rd_en; wire rd_rst; wire tmp_ram_rd_en; wire valid; fifo_generator_0rd_status_flags_as \gras.rsts (.E(p_14_out), .I1(I1), .empty(empty), .p_18_out(p_18_out), .ram_valid_i(ram_valid_i), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en)); fifo_generator_0rd_handshaking_flags \grhf.rhf (.ram_valid_i(ram_valid_i), .rd_clk(rd_clk), .rd_rst(rd_rst), .valid(valid)); fifo_generator_0rd_bin_cntr rpntr (.D(D), .E(p_14_out), .O1(O1), .Q(Q), .rd_clk(rd_clk), .rd_rst(rd_rst)); endmodule ( ORIG_REF_NAME = "rd_status_flags_as" ) module fifo_generator_0rd_status_flags_as (empty, p_18_out, tmp_ram_rd_en, E, ram_valid_i, I1, rd_clk, rd_rst, rd_en); output empty; output p_18_out; output tmp_ram_rd_en; output [0:0]E; output ram_valid_i; input I1; input rd_clk; input rd_rst; input rd_en; wire [0:0]E; wire I1; wire empty; wire p_18_out; wire ram_valid_i; wire rd_clk; wire rd_en; wire rd_rst; wire tmp_ram_rd_en; LUT3 #( .INIT(8'hBA)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1 (.I0(rd_rst), .I1(p_18_out), .I2(rd_en), .O(tmp_ram_rd_en)); ( SOFT_HLUTNM = "soft_lutpair3" ) LUT2 #( .INIT(4'h2)) \gc0.count_d1[3]_i_1 (.I0(rd_en), .I1(p_18_out), .O(E)); ( SOFT_HLUTNM = "soft_lutpair3" ) LUT2 #( .INIT(4'h2)) \gv.ram_valid_d1_i_1 (.I0(rd_en), .I1(empty), .O(ram_valid_i)); ( equivalent_register_removal = "no" ) FDPE #( .INIT(1'b1)) ram_empty_fb_i_reg (.C(rd_clk), .CE(1'b1), .D(I1), .PRE(rd_rst), .Q(p_18_out)); ( equivalent_register_removal = "no" ) FDPE #( .INIT(1'b1)) ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(I1), .PRE(rd_rst), .Q(empty)); endmodule ( ORIG_REF_NAME = "reset_blk_ramfifo" ) module fifo_generator_0reset_blk_ramfifo (rst_full_gen_i, rst_d2, wr_clk, wr_rst); output rst_full_gen_i; output rst_d2; input wr_clk; input wr_rst; wire rst_d1; wire rst_d2; wire rst_d3; wire rst_full_gen_i; wire wr_clk; wire wr_rst; FDCE #( .INIT(1'b0)) \grstd1.grst_full.grst_f.RST_FULL_GEN_reg (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(rst_d3), .Q(rst_full_gen_i)); ( ASYNC_REG ) ( msgon = "true" ) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d1_reg (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(wr_rst), .Q(rst_d1)); ( ASYNC_REG ) ( msgon = "true" ) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d2_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1), .PRE(wr_rst), .Q(rst_d2)); ( ASYNC_REG ) ( msgon = "true" ) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d3_reg (.C(wr_clk), .CE(1'b1), .D(rst_d2), .PRE(wr_rst), .Q(rst_d3)); endmodule ( ORIG_REF_NAME = "synchronizer_ff" ) module fifo_generator_0synchronizer_ff (Q, I1, rd_clk, rd_rst); output [3:0]Q; input [3:0]I1; input rd_clk; input rd_rst; wire [3:0]I1; wire [3:0]Q; wire rd_clk; wire rd_rst; ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[0]), .Q(Q[0])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[1]), .Q(Q[1])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[2]), .Q(Q[2])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[3]), .Q(Q[3])); endmodule ( ORIG_REF_NAME = "synchronizer_ff" ) module fifo_generator_0synchronizer_ff_0 (Q, I1, wr_clk, wr_rst); output [3:0]Q; input [3:0]I1; input wr_clk; input wr_rst; wire [3:0]I1; wire [3:0]Q; wire wr_clk; wire wr_rst; ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[0]), .Q(Q[0])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[1]), .Q(Q[1])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[2]), .Q(Q[2])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[3]), .Q(Q[3])); endmodule ( ORIG_REF_NAME = "synchronizer_ff" ) module fifo_generator_0synchronizer_ff_1 (D, Q, I1, rd_clk, rd_rst); output [1:0]D; output [2:0]Q; input [3:0]I1; input rd_clk; input rd_rst; wire [1:0]D; wire [3:0]I1; wire [2:0]Q; wire rd_clk; wire rd_rst; ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[0]), .Q(Q[0])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[1]), .Q(Q[1])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[2]), .Q(Q[2])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[3]), .Q(D[1])); LUT2 #( .INIT(4'h6)) \wr_pntr_bin[2]_i_1 (.I0(Q[2]), .I1(D[1]), .O(D[0])); endmodule ( ORIG_REF_NAME = "synchronizer_ff" ) module fifo_generator_0synchronizer_ff_2 (D, Q, I1, wr_clk, wr_rst); output [1:0]D; output [2:0]Q; input [3:0]I1; input wr_clk; input wr_rst; wire [1:0]D; wire [3:0]I1; wire [2:0]Q; wire wr_clk; wire wr_rst; ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[0]), .Q(Q[0])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[1]), .Q(Q[1])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[2]), .Q(Q[2])); ( ASYNC_REG ) ( msgon = "true" ) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[3]), .Q(D[1])); LUT2 #( .INIT(4'h6)) \rd_pntr_bin[2]_i_1 (.I0(Q[2]), .I1(D[1]), .O(D[0])); endmodule ( ORIG_REF_NAME = "wr_bin_cntr" ) module fifo_generator_0wr_bin_cntr (ram_full_i, Q, O1, O3, rst_full_gen_i, wr_en, p_0_out, I1, E, wr_clk, wr_rst); output ram_full_i; output [2:0]Q; output [3:0]O1; input [3:0]O3; input rst_full_gen_i; input wr_en; input p_0_out; input I1; input [0:0]E; input wr_clk; input wr_rst; wire [0:0]E; wire I1; wire [3:0]O1; wire [3:0]O3; wire [2:0]Q; wire n_0_ram_full_i_i_2; wire n_0_ram_full_i_i_3; wire n_0_ram_full_i_i_4; wire p_0_out; wire [3:3]p_8_out; wire [3:0]plusOp__0; wire ram_full_i; wire rst_full_gen_i; wire wr_clk; wire wr_en; wire [3:0]wr_pntr_plus2; wire wr_rst; ( RETAIN_INVERTER ) ( SOFT_HLUTNM = "soft_lutpair7" ) LUT1 #( .INIT(2'h1)) \gic0.gc0.count[0]_i_1 (.I0(wr_pntr_plus2[0]), .O(plusOp__0[0])); LUT2 #( .INIT(4'h6)) \gic0.gc0.count[1]_i_1 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .O(plusOp__0[1])); ( SOFT_HLUTNM = "soft_lutpair6" ) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[2]_i_1 (.I0(wr_pntr_plus2[1]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[2]), .O(plusOp__0[2])); ( SOFT_HLUTNM = "soft_lutpair7" ) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[3]_i_1 (.I0(wr_pntr_plus2[2]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[1]), .I3(wr_pntr_plus2[3]), .O(plusOp__0[3])); FDPE #( .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), .CE(E), .D(wr_pntr_plus2[0]), .PRE(wr_rst), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(wr_pntr_plus2[1]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(wr_pntr_plus2[2]), .Q(Q[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(wr_pntr_plus2[3]), .Q(p_8_out)); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(Q[0]), .Q(O1[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(Q[1]), .Q(O1[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(Q[2]), .Q(O1[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(p_8_out), .Q(O1[3])); ( counter = "3" ) FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(plusOp__0[0]), .Q(wr_pntr_plus2[0])); ( counter = "3" ) FDPE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), .CE(E), .D(plusOp__0[1]), .PRE(wr_rst), .Q(wr_pntr_plus2[1])); ( counter = "3" ) FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(plusOp__0[2]), .Q(wr_pntr_plus2[2])); ( counter = "3" ) FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(plusOp__0[3]), .Q(wr_pntr_plus2[3])); LUT6 #( .INIT(64'hFFFF800880088008)) ram_full_i_i_1 (.I0(n_0_ram_full_i_i_2), .I1(n_0_ram_full_i_i_3), .I2(O3[1]), .I3(wr_pntr_plus2[1]), .I4(n_0_ram_full_i_i_4), .I5(I1), .O(ram_full_i)); ( SOFT_HLUTNM = "soft_lutpair6" ) LUT4 #( .INIT(16'h9009)) ram_full_i_i_2 (.I0(wr_pntr_plus2[2]), .I1(O3[2]), .I2(wr_pntr_plus2[0]), .I3(O3[0]), .O(n_0_ram_full_i_i_2)); LUT5 #( .INIT(32'h00000900)) ram_full_i_i_3 (.I0(wr_pntr_plus2[3]), .I1(O3[3]), .I2(rst_full_gen_i), .I3(wr_en), .I4(p_0_out), .O(n_0_ram_full_i_i_3)); LUT3 #( .INIT(8'h09)) ram_full_i_i_4 (.I0(p_8_out), .I1(O3[3]), .I2(rst_full_gen_i), .O(n_0_ram_full_i_i_4)); endmodule ( ORIG_REF_NAME = "wr_logic" ) module fifo_generator_0wr_logic (full, E, Q, O1, wr_clk, rst_d2, O3, rst_full_gen_i, wr_en, I1, wr_rst); output full; output [0:0]E; output [2:0]Q; output [3:0]O1; input wr_clk; input rst_d2; input [3:0]O3; input rst_full_gen_i; input wr_en; input I1; input wr_rst; wire [0:0]E; wire I1; wire [3:0]O1; wire [3:0]O3; wire [2:0]Q; wire full; wire p_0_out; wire ram_full_i; wire rst_d2; wire rst_full_gen_i; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0wr_status_flags_as \gwas.wsts (.E(E), .full(full), .p_0_out(p_0_out), .ram_full_i(ram_full_i), .rst_d2(rst_d2), .wr_clk(wr_clk), .wr_en(wr_en)); fifo_generator_0wr_bin_cntr wpntr (.E(E), .I1(I1), .O1(O1), .O3(O3), .Q(Q), .p_0_out(p_0_out), .ram_full_i(ram_full_i), .rst_full_gen_i(rst_full_gen_i), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule ( ORIG_REF_NAME = "wr_status_flags_as" ) module fifo_generator_0wr_status_flags_as (full, p_0_out, E, ram_full_i, wr_clk, rst_d2, wr_en); output full; output p_0_out; output [0:0]E; input ram_full_i; input wr_clk; input rst_d2; input wr_en; wire [0:0]E; wire full; wire p_0_out; wire ram_full_i; wire rst_d2; wire wr_clk; wire wr_en; LUT2 #( .INIT(4'h2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2 (.I0(wr_en), .I1(p_0_out), .O(E)); ( equivalent_register_removal = "no" ) FDPE #( .INIT(1'b1)) ram_full_fb_i_reg (.C(wr_clk), .CE(1'b1), .D(ram_full_i), .PRE(rst_d2), .Q(p_0_out)); ( equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(ram_full_i), .PRE(rst_d2), .Q(full)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif
/** * This is written by Zhiyang Ong * for EE577b Extra Credit Homework , Question 2 * * Behavioral model for the large XOR gate / module large_xor (a,b,out); // Output vector output reg [14:0] out; // Input vector input [14:0] a; // Another input vector input [15:1] b; // Declare "reg" signals... //reg [3:0] in_bar; // Declare "wire" signals... // Defining constants: parameter [name_of_constant] = value; always @() begin out[0]=a[0]^b[1]; out[1]=a[1]^b[2]; out[2]=a[2]^b[3]; out[3]=a[3]^b[4]; out[4]=a[4]^b[5]; out[5]=a[5]^b[6]; out[6]=a[6]^b[7]; out[7]=a[7]^b[8]; out[8]=a[8]^b[9]; out[9]=a[9]^b[10]; out[10]=a[10]^b[11]; out[11]=a[11]^b[12]; out[12]=a[12]^b[13]; out[13]=a[13]^b[14]; out[14]=a[14]^b[15]; end endmodule module parity_stripper (in,out); // Output vector output reg [10:0] out; // Input vector input [14:0] in; // Declare "reg" signals... //reg [3:0] in_bar; // Declare "wire" signals... // Defining constants: parameter [name_of_constant] = value; always @(*) begin out[0]=in[2]; out[1]=in[4]; out[2]=in[5]; out[3]=in[6]; out[4]=in[8]; out[5]=in[9]; out[6]=in[10]; out[7]=in[11]; out[8]=in[12]; out[9]=in[13]; out[10]=in[14]; end endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V `define SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V /* * sdfstp: Scan delay flop, inverted set, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_dff_ps/sky130_fd_sc_ms__udp_dff_ps.v" `include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v" `celldefine module sky130_fd_sc_ms__sdfstp ( Q , CLK , D , SCD , SCE , SET_B ); // Module ports output Q ; input CLK ; input D ; input SCD ; input SCE ; input SET_B; // Local signals wire buf_Q ; wire SET ; wire mux_out; // Delay Name Output Other arguments not not0 (SET , SET_B ); sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); sky130_fd_sc_ms__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET); buf buf0 (Q , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V `define SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V /* * dlxtn: Delay latch, inverted enable, single output. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none ( blackbox *) module sky130_fd_sc_lp__dlxtn ( //# {{data\|Data Signals}} input D , output Q , //# {{clocks\|Clocking}} input GATE_N, //# {{power\|Power}} input VPB , input VPWR , input VGND , input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V
// megafunction wizard: %ALTPLL%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: ddr3_int_phy_alt_mem_phy_pll.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // // ============================================================ // ********************************************************** // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 10.0 Build 262 08/18/2010 SP 1 SJ Full Version // ********************************************************** //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module ddr3_int_phy_alt_mem_phy_pll ( areset, inclk0, phasecounterselect, phasestep, phaseupdown, scanclk, c0, c1, c2, c3, c4, c5, locked, phasedone); input areset; input inclk0; input [3:0] phasecounterselect; input phasestep; input phaseupdown; input scanclk; output c0; output c1; output c2; output c3; output c4; output c5; output locked; output phasedone; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 areset; tri0 [3:0] phasecounterselect; tri0 phasestep; tri0 phaseupdown; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "3" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "300.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg" // Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000" // Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" // Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK5 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLK4 STRING "1" // Retrieval info: PRIVATE: USE_CLK5 STRING "1" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833" // Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" // Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" // Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" // Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF" // Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE" // Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7" // Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]" // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" // Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]" // Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone" // Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep" // Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown" // Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0 // Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0 // Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0 // Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 // Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_bb.v TRUE
// $Id: rtr_flit_type_check.v 5188 2012-08-30 00:31:31Z dub $ /* Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ //============================================================================== // flit type checker module //============================================================================== module rtr_flit_type_check (clk, reset, active, flit_valid, flit_head, flit_tail, error); `include "c_constants.v" //--------------------------------------------------------------------------- // parameters //--------------------------------------------------------------------------- parameter reset_type = `RESET_TYPE_ASYNC; //--------------------------------------------------------------------------- // interface //--------------------------------------------------------------------------- input clk; input reset; input active; input flit_valid; input flit_head; input flit_tail; output error; wire error; //--------------------------------------------------------------------------- // implementation //--------------------------------------------------------------------------- wire packet_active_s, packet_active_q; assign packet_active_s = flit_valid ? ((packet_active_q \| flit_head) & ~flit_tail) : packet_active_q; c_dff #(.width(1), .reset_type(reset_type)) packet_activeq (.clk(clk), .reset(reset), .active(active), .d(packet_active_s), .q(packet_active_q)); assign error = flit_valid & (flit_head ~^ packet_active_q); // synopsys translate_off always @(posedge clk) begin if(error) $display("ERROR: Received flit with unexpected type in module %m."); end // synopsys translate_on endmodule
// $Id: c_encoder.v 1534 2009-09-16 16:10:23Z dub $ /* Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the Stanford University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ // encoder from one-hot to binary module c_encoder (data_in, data_out); `include "c_functions.v" // number of input ports (i.e., decoded width) parameter num_ports = 8; localparam width = clogb(num_ports); // one-hot input data input [0:num_ports-1] data_in; // binary encoded output data output [0:width-1] data_out; wire [0:width-1] data_out; generate genvar level; for(level = 0; level < width; level = level + 1) begin:levels wire [0:num_ports-1] bits; genvar position; for(position = 0; position < num_ports; position = position + 1) begin:positions if(position & (1 << level)) assign bits[position] = data_in[position]; else assign bits[position] = 1'b0; end assign data_out[(width-1)-level] = \|bits; end endgenerate endmodule
//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_core_pcie_pipe_pipeline.v // Version : 1.10 // // Description: PIPE module for Virtex7 PCIe Block // // // //-------------------------------------------------------------------------------- `timescale 1ps/1ps module pcie_core_pcie_pipe_pipeline # ( parameter LINK_CAP_MAX_LINK_WIDTH = 8, parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages ) ( // Pipe Per-Link Signals input wire pipe_tx_rcvr_det_i , input wire pipe_tx_reset_i , input wire pipe_tx_rate_i , input wire pipe_tx_deemph_i , input wire [2:0] pipe_tx_margin_i , input wire pipe_tx_swing_i , output wire pipe_tx_rcvr_det_o , output wire pipe_tx_reset_o , output wire pipe_tx_rate_o , output wire pipe_tx_deemph_o , output wire [2:0] pipe_tx_margin_o , output wire pipe_tx_swing_o , // Pipe Per-Lane Signals - Lane 0 output wire [ 1:0] pipe_rx0_char_is_k_o , output wire [15:0] pipe_rx0_data_o , output wire pipe_rx0_valid_o , output wire pipe_rx0_chanisaligned_o , output wire [ 2:0] pipe_rx0_status_o , output wire pipe_rx0_phy_status_o , output wire pipe_rx0_elec_idle_o , input wire pipe_rx0_polarity_i , input wire pipe_tx0_compliance_i , input wire [ 1:0] pipe_tx0_char_is_k_i , input wire [15:0] pipe_tx0_data_i , input wire pipe_tx0_elec_idle_i , input wire [ 1:0] pipe_tx0_powerdown_i , input wire [ 1:0] pipe_rx0_char_is_k_i , input wire [15:0] pipe_rx0_data_i , input wire pipe_rx0_valid_i , input wire pipe_rx0_chanisaligned_i , input wire [ 2:0] pipe_rx0_status_i , input wire pipe_rx0_phy_status_i , input wire pipe_rx0_elec_idle_i , output wire pipe_rx0_polarity_o , output wire pipe_tx0_compliance_o , output wire [ 1:0] pipe_tx0_char_is_k_o , output wire [15:0] pipe_tx0_data_o , output wire pipe_tx0_elec_idle_o , output wire [ 1:0] pipe_tx0_powerdown_o , // Pipe Per-Lane Signals - Lane 1 output wire [ 1:0] pipe_rx1_char_is_k_o , output wire [15:0] pipe_rx1_data_o , output wire pipe_rx1_valid_o , output wire pipe_rx1_chanisaligned_o , output wire [ 2:0] pipe_rx1_status_o , output wire pipe_rx1_phy_status_o , output wire pipe_rx1_elec_idle_o , input wire pipe_rx1_polarity_i , input wire pipe_tx1_compliance_i , input wire [ 1:0] pipe_tx1_char_is_k_i , input wire [15:0] pipe_tx1_data_i , input wire pipe_tx1_elec_idle_i , input wire [ 1:0] pipe_tx1_powerdown_i , input wire [ 1:0] pipe_rx1_char_is_k_i , input wire [15:0] pipe_rx1_data_i , input wire pipe_rx1_valid_i , input wire pipe_rx1_chanisaligned_i , input wire [ 2:0] pipe_rx1_status_i , input wire pipe_rx1_phy_status_i , input wire pipe_rx1_elec_idle_i , output wire pipe_rx1_polarity_o , output wire pipe_tx1_compliance_o , output wire [ 1:0] pipe_tx1_char_is_k_o , output wire [15:0] pipe_tx1_data_o , output wire pipe_tx1_elec_idle_o , output wire [ 1:0] pipe_tx1_powerdown_o , // Pipe Per-Lane Signals - Lane 2 output wire [ 1:0] pipe_rx2_char_is_k_o , output wire [15:0] pipe_rx2_data_o , output wire pipe_rx2_valid_o , output wire pipe_rx2_chanisaligned_o , output wire [ 2:0] pipe_rx2_status_o , output wire pipe_rx2_phy_status_o , output wire pipe_rx2_elec_idle_o , input wire pipe_rx2_polarity_i , input wire pipe_tx2_compliance_i , input wire [ 1:0] pipe_tx2_char_is_k_i , input wire [15:0] pipe_tx2_data_i , input wire pipe_tx2_elec_idle_i , input wire [ 1:0] pipe_tx2_powerdown_i , input wire [ 1:0] pipe_rx2_char_is_k_i , input wire [15:0] pipe_rx2_data_i , input wire pipe_rx2_valid_i , input wire pipe_rx2_chanisaligned_i , input wire [ 2:0] pipe_rx2_status_i , input wire pipe_rx2_phy_status_i , input wire pipe_rx2_elec_idle_i , output wire pipe_rx2_polarity_o , output wire pipe_tx2_compliance_o , output wire [ 1:0] pipe_tx2_char_is_k_o , output wire [15:0] pipe_tx2_data_o , output wire pipe_tx2_elec_idle_o , output wire [ 1:0] pipe_tx2_powerdown_o , // Pipe Per-Lane Signals - Lane 3 output wire [ 1:0] pipe_rx3_char_is_k_o , output wire [15:0] pipe_rx3_data_o , output wire pipe_rx3_valid_o , output wire pipe_rx3_chanisaligned_o , output wire [ 2:0] pipe_rx3_status_o , output wire pipe_rx3_phy_status_o , output wire pipe_rx3_elec_idle_o , input wire pipe_rx3_polarity_i , input wire pipe_tx3_compliance_i , input wire [ 1:0] pipe_tx3_char_is_k_i , input wire [15:0] pipe_tx3_data_i , input wire pipe_tx3_elec_idle_i , input wire [ 1:0] pipe_tx3_powerdown_i , input wire [ 1:0] pipe_rx3_char_is_k_i , input wire [15:0] pipe_rx3_data_i , input wire pipe_rx3_valid_i , input wire pipe_rx3_chanisaligned_i , input wire [ 2:0] pipe_rx3_status_i , input wire pipe_rx3_phy_status_i , input wire pipe_rx3_elec_idle_i , output wire pipe_rx3_polarity_o , output wire pipe_tx3_compliance_o , output wire [ 1:0] pipe_tx3_char_is_k_o , output wire [15:0] pipe_tx3_data_o , output wire pipe_tx3_elec_idle_o , output wire [ 1:0] pipe_tx3_powerdown_o , // Pipe Per-Lane Signals - Lane 4 output wire [ 1:0] pipe_rx4_char_is_k_o , output wire [15:0] pipe_rx4_data_o , output wire pipe_rx4_valid_o , output wire pipe_rx4_chanisaligned_o , output wire [ 2:0] pipe_rx4_status_o , output wire pipe_rx4_phy_status_o , output wire pipe_rx4_elec_idle_o , input wire pipe_rx4_polarity_i , input wire pipe_tx4_compliance_i , input wire [ 1:0] pipe_tx4_char_is_k_i , input wire [15:0] pipe_tx4_data_i , input wire pipe_tx4_elec_idle_i , input wire [ 1:0] pipe_tx4_powerdown_i , input wire [ 1:0] pipe_rx4_char_is_k_i , input wire [15:0] pipe_rx4_data_i , input wire pipe_rx4_valid_i , input wire pipe_rx4_chanisaligned_i , input wire [ 2:0] pipe_rx4_status_i , input wire pipe_rx4_phy_status_i , input wire pipe_rx4_elec_idle_i , output wire pipe_rx4_polarity_o , output wire pipe_tx4_compliance_o , output wire [ 1:0] pipe_tx4_char_is_k_o , output wire [15:0] pipe_tx4_data_o , output wire pipe_tx4_elec_idle_o , output wire [ 1:0] pipe_tx4_powerdown_o , // Pipe Per-Lane Signals - Lane 5 output wire [ 1:0] pipe_rx5_char_is_k_o , output wire [15:0] pipe_rx5_data_o , output wire pipe_rx5_valid_o , output wire pipe_rx5_chanisaligned_o , output wire [ 2:0] pipe_rx5_status_o , output wire pipe_rx5_phy_status_o , output wire pipe_rx5_elec_idle_o , input wire pipe_rx5_polarity_i , input wire pipe_tx5_compliance_i , input wire [ 1:0] pipe_tx5_char_is_k_i , input wire [15:0] pipe_tx5_data_i , input wire pipe_tx5_elec_idle_i , input wire [ 1:0] pipe_tx5_powerdown_i , input wire [ 1:0] pipe_rx5_char_is_k_i , input wire [15:0] pipe_rx5_data_i , input wire pipe_rx5_valid_i , input wire pipe_rx5_chanisaligned_i , input wire [ 2:0] pipe_rx5_status_i , input wire pipe_rx5_phy_status_i , input wire pipe_rx5_elec_idle_i , output wire pipe_rx5_polarity_o , output wire pipe_tx5_compliance_o , output wire [ 1:0] pipe_tx5_char_is_k_o , output wire [15:0] pipe_tx5_data_o , output wire pipe_tx5_elec_idle_o , output wire [ 1:0] pipe_tx5_powerdown_o , // Pipe Per-Lane Signals - Lane 6 output wire [ 1:0] pipe_rx6_char_is_k_o , output wire [15:0] pipe_rx6_data_o , output wire pipe_rx6_valid_o , output wire pipe_rx6_chanisaligned_o , output wire [ 2:0] pipe_rx6_status_o , output wire pipe_rx6_phy_status_o , output wire pipe_rx6_elec_idle_o , input wire pipe_rx6_polarity_i , input wire pipe_tx6_compliance_i , input wire [ 1:0] pipe_tx6_char_is_k_i , input wire [15:0] pipe_tx6_data_i , input wire pipe_tx6_elec_idle_i , input wire [ 1:0] pipe_tx6_powerdown_i , input wire [ 1:0] pipe_rx6_char_is_k_i , input wire [15:0] pipe_rx6_data_i , input wire pipe_rx6_valid_i , input wire pipe_rx6_chanisaligned_i , input wire [ 2:0] pipe_rx6_status_i , input wire pipe_rx6_phy_status_i , input wire pipe_rx6_elec_idle_i , output wire pipe_rx6_polarity_o , output wire pipe_tx6_compliance_o , output wire [ 1:0] pipe_tx6_char_is_k_o , output wire [15:0] pipe_tx6_data_o , output wire pipe_tx6_elec_idle_o , output wire [ 1:0] pipe_tx6_powerdown_o , // Pipe Per-Lane Signals - Lane 7 output wire [ 1:0] pipe_rx7_char_is_k_o , output wire [15:0] pipe_rx7_data_o , output wire pipe_rx7_valid_o , output wire pipe_rx7_chanisaligned_o , output wire [ 2:0] pipe_rx7_status_o , output wire pipe_rx7_phy_status_o , output wire pipe_rx7_elec_idle_o , input wire pipe_rx7_polarity_i , input wire pipe_tx7_compliance_i , input wire [ 1:0] pipe_tx7_char_is_k_i , input wire [15:0] pipe_tx7_data_i , input wire pipe_tx7_elec_idle_i , input wire [ 1:0] pipe_tx7_powerdown_i , input wire [ 1:0] pipe_rx7_char_is_k_i , input wire [15:0] pipe_rx7_data_i , input wire pipe_rx7_valid_i , input wire pipe_rx7_chanisaligned_i , input wire [ 2:0] pipe_rx7_status_i , input wire pipe_rx7_phy_status_i , input wire pipe_rx7_elec_idle_i , output wire pipe_rx7_polarity_o , output wire pipe_tx7_compliance_o , output wire [ 1:0] pipe_tx7_char_is_k_o , output wire [15:0] pipe_tx7_data_o , output wire pipe_tx7_elec_idle_o , output wire [ 1:0] pipe_tx7_powerdown_o , // Non PIPE signals input wire pipe_clk , input wire rst_n ); //****************************************************************// // Reality check. // //****************************************************************// //synthesis translate_off // initial begin // $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d PIPE_PIPELINE_STAGES %0d", // $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES); // end //synthesis translate_on generate pcie_core_pcie_pipe_misc # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_misc_i ( .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i), .pipe_tx_reset_i(pipe_tx_reset_i), .pipe_tx_rate_i(pipe_tx_rate_i), .pipe_tx_deemph_i(pipe_tx_deemph_i), .pipe_tx_margin_i(pipe_tx_margin_i), .pipe_tx_swing_i(pipe_tx_swing_i), .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o), .pipe_tx_reset_o(pipe_tx_reset_o), .pipe_tx_rate_o(pipe_tx_rate_o), .pipe_tx_deemph_o(pipe_tx_deemph_o), .pipe_tx_margin_o(pipe_tx_margin_o), .pipe_tx_swing_o(pipe_tx_swing_o) , .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_0_i ( .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o), .pipe_rx_data_o(pipe_rx0_data_o), .pipe_rx_valid_o(pipe_rx0_valid_o), .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o), .pipe_rx_status_o(pipe_rx0_status_o), .pipe_rx_phy_status_o(pipe_rx0_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o), .pipe_rx_polarity_i(pipe_rx0_polarity_i), .pipe_tx_compliance_i(pipe_tx0_compliance_i), .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i), .pipe_tx_data_i(pipe_tx0_data_i), .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx0_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i), .pipe_rx_data_i(pipe_rx0_data_i), .pipe_rx_valid_i(pipe_rx0_valid_i), .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i), .pipe_rx_status_i(pipe_rx0_status_i), .pipe_rx_phy_status_i(pipe_rx0_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i), .pipe_rx_polarity_o(pipe_rx0_polarity_o), .pipe_tx_compliance_o(pipe_tx0_compliance_o), .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o), .pipe_tx_data_o(pipe_tx0_data_o), .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx0_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_1_i ( .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o), .pipe_rx_data_o(pipe_rx1_data_o), .pipe_rx_valid_o(pipe_rx1_valid_o), .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o), .pipe_rx_status_o(pipe_rx1_status_o), .pipe_rx_phy_status_o(pipe_rx1_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o), .pipe_rx_polarity_i(pipe_rx1_polarity_i), .pipe_tx_compliance_i(pipe_tx1_compliance_i), .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i), .pipe_tx_data_i(pipe_tx1_data_i), .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx1_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i), .pipe_rx_data_i(pipe_rx1_data_i), .pipe_rx_valid_i(pipe_rx1_valid_i), .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i), .pipe_rx_status_i(pipe_rx1_status_i), .pipe_rx_phy_status_i(pipe_rx1_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i), .pipe_rx_polarity_o(pipe_rx1_polarity_o), .pipe_tx_compliance_o(pipe_tx1_compliance_o), .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o), .pipe_tx_data_o(pipe_tx1_data_o), .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx1_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); end // if (LINK_CAP_MAX_LINK_WIDTH >= 2) else begin assign pipe_rx1_char_is_k_o = 2'b00; assign pipe_rx1_data_o = 16'h0000; assign pipe_rx1_valid_o = 1'b0; assign pipe_rx1_chanisaligned_o = 1'b0; assign pipe_rx1_status_o = 3'b000; assign pipe_rx1_phy_status_o = 1'b0; assign pipe_rx1_elec_idle_o = 1'b1; assign pipe_rx1_polarity_o = 1'b0; assign pipe_tx1_compliance_o = 1'b0; assign pipe_tx1_char_is_k_o = 2'b00; assign pipe_tx1_data_o = 16'h0000; assign pipe_tx1_elec_idle_o = 1'b1; assign pipe_tx1_powerdown_o = 2'b00; end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2) if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_2_i ( .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o), .pipe_rx_data_o(pipe_rx2_data_o), .pipe_rx_valid_o(pipe_rx2_valid_o), .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o), .pipe_rx_status_o(pipe_rx2_status_o), .pipe_rx_phy_status_o(pipe_rx2_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o), .pipe_rx_polarity_i(pipe_rx2_polarity_i), .pipe_tx_compliance_i(pipe_tx2_compliance_i), .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i), .pipe_tx_data_i(pipe_tx2_data_i), .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx2_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i), .pipe_rx_data_i(pipe_rx2_data_i), .pipe_rx_valid_i(pipe_rx2_valid_i), .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i), .pipe_rx_status_i(pipe_rx2_status_i), .pipe_rx_phy_status_i(pipe_rx2_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i), .pipe_rx_polarity_o(pipe_rx2_polarity_o), .pipe_tx_compliance_o(pipe_tx2_compliance_o), .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o), .pipe_tx_data_o(pipe_tx2_data_o), .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx2_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_3_i ( .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o), .pipe_rx_data_o(pipe_rx3_data_o), .pipe_rx_valid_o(pipe_rx3_valid_o), .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o), .pipe_rx_status_o(pipe_rx3_status_o), .pipe_rx_phy_status_o(pipe_rx3_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o), .pipe_rx_polarity_i(pipe_rx3_polarity_i), .pipe_tx_compliance_i(pipe_tx3_compliance_i), .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i), .pipe_tx_data_i(pipe_tx3_data_i), .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx3_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i), .pipe_rx_data_i(pipe_rx3_data_i), .pipe_rx_valid_i(pipe_rx3_valid_i), .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i), .pipe_rx_status_i(pipe_rx3_status_i), .pipe_rx_phy_status_i(pipe_rx3_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i), .pipe_rx_polarity_o(pipe_rx3_polarity_o), .pipe_tx_compliance_o(pipe_tx3_compliance_o), .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o), .pipe_tx_data_o(pipe_tx3_data_o), .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx3_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); end // if (LINK_CAP_MAX_LINK_WIDTH >= 4) else begin assign pipe_rx2_char_is_k_o = 2'b00; assign pipe_rx2_data_o = 16'h0000; assign pipe_rx2_valid_o = 1'b0; assign pipe_rx2_chanisaligned_o = 1'b0; assign pipe_rx2_status_o = 3'b000; assign pipe_rx2_phy_status_o = 1'b0; assign pipe_rx2_elec_idle_o = 1'b1; assign pipe_rx2_polarity_o = 1'b0; assign pipe_tx2_compliance_o = 1'b0; assign pipe_tx2_char_is_k_o = 2'b00; assign pipe_tx2_data_o = 16'h0000; assign pipe_tx2_elec_idle_o = 1'b1; assign pipe_tx2_powerdown_o = 2'b00; assign pipe_rx3_char_is_k_o = 2'b00; assign pipe_rx3_data_o = 16'h0000; assign pipe_rx3_valid_o = 1'b0; assign pipe_rx3_chanisaligned_o = 1'b0; assign pipe_rx3_status_o = 3'b000; assign pipe_rx3_phy_status_o = 1'b0; assign pipe_rx3_elec_idle_o = 1'b1; assign pipe_rx3_polarity_o = 1'b0; assign pipe_tx3_compliance_o = 1'b0; assign pipe_tx3_char_is_k_o = 2'b00; assign pipe_tx3_data_o = 16'h0000; assign pipe_tx3_elec_idle_o = 1'b1; assign pipe_tx3_powerdown_o = 2'b00; end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4) if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_4_i ( .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o), .pipe_rx_data_o(pipe_rx4_data_o), .pipe_rx_valid_o(pipe_rx4_valid_o), .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o), .pipe_rx_status_o(pipe_rx4_status_o), .pipe_rx_phy_status_o(pipe_rx4_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o), .pipe_rx_polarity_i(pipe_rx4_polarity_i), .pipe_tx_compliance_i(pipe_tx4_compliance_i), .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i), .pipe_tx_data_i(pipe_tx4_data_i), .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx4_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i), .pipe_rx_data_i(pipe_rx4_data_i), .pipe_rx_valid_i(pipe_rx4_valid_i), .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i), .pipe_rx_status_i(pipe_rx4_status_i), .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i), .pipe_rx_polarity_o(pipe_rx4_polarity_o), .pipe_tx_compliance_o(pipe_tx4_compliance_o), .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o), .pipe_tx_data_o(pipe_tx4_data_o), .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx4_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_5_i ( .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o), .pipe_rx_data_o(pipe_rx5_data_o), .pipe_rx_valid_o(pipe_rx5_valid_o), .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o), .pipe_rx_status_o(pipe_rx5_status_o), .pipe_rx_phy_status_o(pipe_rx5_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o), .pipe_rx_polarity_i(pipe_rx5_polarity_i), .pipe_tx_compliance_i(pipe_tx5_compliance_i), .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i), .pipe_tx_data_i(pipe_tx5_data_i), .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx5_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i), .pipe_rx_data_i(pipe_rx5_data_i), .pipe_rx_valid_i(pipe_rx5_valid_i), .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i), .pipe_rx_status_i(pipe_rx5_status_i), .pipe_rx_phy_status_i(pipe_rx5_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i), .pipe_rx_polarity_o(pipe_rx5_polarity_o), .pipe_tx_compliance_o(pipe_tx5_compliance_o), .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o), .pipe_tx_data_o(pipe_tx5_data_o), .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx5_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_6_i ( .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o), .pipe_rx_data_o(pipe_rx6_data_o), .pipe_rx_valid_o(pipe_rx6_valid_o), .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o), .pipe_rx_status_o(pipe_rx6_status_o), .pipe_rx_phy_status_o(pipe_rx6_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o), .pipe_rx_polarity_i(pipe_rx6_polarity_i), .pipe_tx_compliance_i(pipe_tx6_compliance_i), .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i), .pipe_tx_data_i(pipe_tx6_data_i), .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx6_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i), .pipe_rx_data_i(pipe_rx6_data_i), .pipe_rx_valid_i(pipe_rx6_valid_i), .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i), .pipe_rx_status_i(pipe_rx6_status_i), .pipe_rx_phy_status_i(pipe_rx6_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i), .pipe_rx_polarity_o(pipe_rx6_polarity_o), .pipe_tx_compliance_o(pipe_tx6_compliance_o), .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o), .pipe_tx_data_o(pipe_tx6_data_o), .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx6_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_7_i ( .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o), .pipe_rx_data_o(pipe_rx7_data_o), .pipe_rx_valid_o(pipe_rx7_valid_o), .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o), .pipe_rx_status_o(pipe_rx7_status_o), .pipe_rx_phy_status_o(pipe_rx7_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o), .pipe_rx_polarity_i(pipe_rx7_polarity_i), .pipe_tx_compliance_i(pipe_tx7_compliance_i), .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i), .pipe_tx_data_i(pipe_tx7_data_i), .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx7_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i), .pipe_rx_data_i(pipe_rx7_data_i), .pipe_rx_valid_i(pipe_rx7_valid_i), .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i), .pipe_rx_status_i(pipe_rx7_status_i), .pipe_rx_phy_status_i(pipe_rx7_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i), .pipe_rx_polarity_o(pipe_rx7_polarity_o), .pipe_tx_compliance_o(pipe_tx7_compliance_o), .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o), .pipe_tx_data_o(pipe_tx7_data_o), .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx7_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); end // if (LINK_CAP_MAX_LINK_WIDTH >= 8) else begin assign pipe_rx4_char_is_k_o = 2'b00; assign pipe_rx4_data_o = 16'h0000; assign pipe_rx4_valid_o = 1'b0; assign pipe_rx4_chanisaligned_o = 1'b0; assign pipe_rx4_status_o = 3'b000; assign pipe_rx4_phy_status_o = 1'b0; assign pipe_rx4_elec_idle_o = 1'b1; assign pipe_rx4_polarity_o = 1'b0; assign pipe_tx4_compliance_o = 1'b0; assign pipe_tx4_char_is_k_o = 2'b00; assign pipe_tx4_data_o = 16'h0000; assign pipe_tx4_elec_idle_o = 1'b1; assign pipe_tx4_powerdown_o = 2'b00; assign pipe_rx5_char_is_k_o = 2'b00; assign pipe_rx5_data_o = 16'h0000; assign pipe_rx5_valid_o = 1'b0; assign pipe_rx5_chanisaligned_o = 1'b0; assign pipe_rx5_status_o = 3'b000; assign pipe_rx5_phy_status_o = 1'b0; assign pipe_rx5_elec_idle_o = 1'b1; assign pipe_rx5_polarity_o = 1'b0; assign pipe_tx5_compliance_o = 1'b0; assign pipe_tx5_char_is_k_o = 2'b00; assign pipe_tx5_data_o = 16'h0000; assign pipe_tx5_elec_idle_o = 1'b1; assign pipe_tx5_powerdown_o = 2'b00; assign pipe_rx6_char_is_k_o = 2'b00; assign pipe_rx6_data_o = 16'h0000; assign pipe_rx6_valid_o = 1'b0; assign pipe_rx6_chanisaligned_o = 1'b0; assign pipe_rx6_status_o = 3'b000; assign pipe_rx6_phy_status_o = 1'b0; assign pipe_rx6_elec_idle_o = 1'b1; assign pipe_rx6_polarity_o = 1'b0; assign pipe_tx6_compliance_o = 1'b0; assign pipe_tx6_char_is_k_o = 2'b00; assign pipe_tx6_data_o = 16'h0000; assign pipe_tx6_elec_idle_o = 1'b1; assign pipe_tx6_powerdown_o = 2'b00; assign pipe_rx7_char_is_k_o = 2'b00; assign pipe_rx7_data_o = 16'h0000; assign pipe_rx7_valid_o = 1'b0; assign pipe_rx7_chanisaligned_o = 1'b0; assign pipe_rx7_status_o = 3'b000; assign pipe_rx7_phy_status_o = 1'b0; assign pipe_rx7_elec_idle_o = 1'b1; assign pipe_rx7_polarity_o = 1'b0; assign pipe_tx7_compliance_o = 1'b0; assign pipe_tx7_char_is_k_o = 2'b00; assign pipe_tx7_data_o = 16'h0000; assign pipe_tx7_elec_idle_o = 1'b1; assign pipe_tx7_powerdown_o = 2'b00; end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8) endgenerate endmodule
module control_mult( clk , rst , lsb_B , init , z , done , sh , reset , add ); input clk; input rst; input lsb_B; input init; input z; output reg done; output reg sh; output reg reset; output reg add; parameter START = 3'b000; parameter CHECK = 3'b001; parameter SHIFT = 3'b010; parameter ADD = 3'b011; parameter END = 3'b100; reg [2:0] state; initial begin done = 0; sh = 0; reset = 0; add = 0; state = 0; end reg [3:0] count; always @(posedge clk) begin if (rst) begin state = START; end else begin case(state) START:begin count=0; if(init) state = CHECK; else state = START; end CHECK: if(lsb_B) state = SHIFT; else state = ADD; SHIFT: state = ADD; ADD: if(z) state = END; else state = CHECK; END:begin count = count + 1; state = (count>9) ? START : END ; // hace falta de 10 ciclos de reloj, para que lea el done y luego cargue el resultado end default: state = START; endcase end end always @(state) begin case(state) START:begin done = 0; sh = 0; reset = 1; add = 0; end CHECK:begin done = 0; sh = 0; reset = 0; add = 0; end SHIFT:begin done = 0; sh = 0; reset = 0; add = 1; end ADD:begin done = 0; sh = 1; reset = 0; add = 0; end END:begin done = 1; sh = 0; reset = 0; add = 0; end default:begin done = 0; sh = 0; reset = 0; add = 0; end endcase end endmodule
// Test constant functions. module main; localparam BYTESIZE = 8; localparam STRLEN = 4; function [STRLENBYTESIZE - 1 : 0] bits2text; input [STRLEN-1:0] use_map; integer idx; begin bits2text = 0; for (idx = 0 ; idx < STRLEN ; idx = idx+1) begin bits2text[(idxBYTESIZE) +: BYTESIZE] = (use_map[idx] == 1'b0)? "1" : "0"; end end endfunction localparam [STRLENBYTESIZE - 1 : 0] str0010 = bits2text(4'b0010); localparam [STRLENBYTESIZE - 1 : 0] str0100 = bits2text(4'b0100); localparam [STRLENBYTESIZE - 1 : 0] str0011 = bits2text(4'b0011); localparam [STRLENBYTESIZE - 1 : 0] str1100 = bits2text(4'b1100); reg [STRLEN*BYTESIZE - 1 : 0] tmp; initial begin tmp = bits2text(4'b0010); if (tmp !== str0010) begin $display("FAILED -- str0010=%h, expect %h", str0010, tmp); $finish; end tmp = bits2text(4'b0100); if (tmp !== str0100) begin $display("FAILED -- str0100=%h, expect %h", str0100, tmp); $finish; end tmp = bits2text(4'b0011); if (tmp !== str0011) begin $display("FAILED -- str0011=%h, expect %h", str0011, tmp); $finish; end tmp = bits2text(4'b1100); if (tmp !== str1100) begin $display("FAILED -- str1100=%h, expect %h", str1100, tmp); $finish; end $display("PASSED"); $finish; end endmodule // main
module test (input wire clk, output reg foo, bar, input wire foo_valid, foo_in, input wire bar_valid, bar_in /* */); always @(posedge clk) begin if (foo_valid) foo <= foo_in; if (bar_valid) bar <= bar_in; end endmodule // test module main; reg clk; wire foo, bar; reg foo_valid, foo_in; reg bar_valid, bar_in; test dut (.clk(clk), .foo(foo), .bar(bar), .foo_valid(foo_valid), .bar_valid(bar_valid), .foo_in(foo_in), .bar_in(bar_in)); task fail; begin $display("FAILED -- foo/bar=%b/%b, foo/bar_valid=%b/%b, foo/bar_in=%b/%b", foo, bar, foo_valid, bar_valid, foo_in, bar_in); $finish; end endtask // fail initial begin clk = 0; foo_valid = 1; bar_valid = 1; foo_in = 0; bar_in = 0; #1 clk = 1; #1 clk = 0; if (foo !== 0 \|\| bar !== 0) fail; bar_in = 1; #1 clk = 1; #1 clk = 0; if (foo !== 0 \|\| bar !== 1) fail; foo_in = 1; bar_in = 0; foo_valid = 1; bar_valid = 0; #1 clk = 1; #1 clk = 0; if (foo !== 1 \|\| bar !== 1) fail; $display("PASSED"); end endmodule // main
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. /////////////////////////////////////////////////////////////////////////////// // Title : DDR controller wrapper // // File : alt_ddrx_controller_wrapper.v // // Abstract : This file is a wrapper that configures DDRx controller /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps // module ddr3_int_alt_ddrx_controller_wrapper ( ctl_clk, ctl_reset_n, ctl_half_clk, ctl_half_clk_reset_n, local_ready, local_read_req, local_write_req, local_wdata_req, local_size, local_burstbegin, local_addr, local_rdata_valid, local_rdata_error, local_rdata, local_wdata, local_be, local_autopch_req, local_multicast, local_init_done, local_refresh_req, local_refresh_chip, local_refresh_ack, local_self_rfsh_req, local_self_rfsh_chip, local_self_rfsh_ack, local_power_down_ack, ctl_cal_success, ctl_cal_fail, ctl_cal_req, ctl_mem_clk_disable, ctl_cal_byte_lane_sel_n, afi_cke, afi_cs_n, afi_ras_n, afi_cas_n, afi_we_n, afi_ba, afi_addr, afi_odt, afi_rst_n, afi_dqs_burst, afi_wdata_valid, afi_wdata, afi_dm, afi_wlat, afi_doing_read, afi_rdata, afi_rdata_valid, csr_write_req, csr_read_req, csr_addr, csr_be, csr_wdata, csr_waitrequest, csr_rdata, csr_rdata_valid, ecc_interrupt, bank_information, bank_open ); //Inserted Generics localparam MEM_TYPE = "DDR3"; localparam LOCAL_SIZE_WIDTH = 6; localparam LOCAL_ADDR_WIDTH = 25; localparam LOCAL_DATA_WIDTH = 128; localparam LOCAL_IF_TYPE = "AVALON"; localparam MEM_IF_CS_WIDTH = 1; localparam MEM_IF_CHIP_BITS = 1; localparam MEM_IF_CKE_WIDTH = 1; localparam MEM_IF_ODT_WIDTH = 1; localparam MEM_IF_ADDR_WIDTH = 14; localparam MEM_IF_ROW_WIDTH = 14; localparam MEM_IF_COL_WIDTH = 10; localparam MEM_IF_BA_WIDTH = 3; localparam MEM_IF_DQS_WIDTH = 4; localparam MEM_IF_DQ_WIDTH = 32; localparam MEM_IF_DM_WIDTH = 4; localparam MEM_IF_CLK_PAIR_COUNT = 1; localparam MEM_IF_CS_PER_DIMM = 1; localparam DWIDTH_RATIO = 4; localparam CTL_LOOK_AHEAD_DEPTH = 8; localparam CTL_CMD_QUEUE_DEPTH = 8; localparam CTL_HRB_ENABLED = 0; localparam CTL_ECC_ENABLED = 0; localparam CTL_ECC_RMW_ENABLED = 0; localparam CTL_ECC_CSR_ENABLED = 0; localparam CTL_CSR_ENABLED = 0; localparam CTL_ODT_ENABLED = 1; localparam CSR_ADDR_WIDTH = 16; localparam CSR_DATA_WIDTH = 32; localparam CTL_OUTPUT_REGD = 0; localparam MEM_CAS_WR_LAT = 6; localparam MEM_ADD_LAT = 0; localparam MEM_TCL = 8; localparam MEM_TRRD = 2; localparam MEM_TFAW = 10; localparam MEM_TRFC = 34; localparam MEM_TREFI = 2341; localparam MEM_TRCD = 5; localparam MEM_TRP = 5; localparam MEM_TWR = 5; localparam MEM_TWTR = 4; localparam MEM_TRTP = 3; localparam MEM_TRAS = 11; localparam MEM_TRC = 15; localparam ADDR_ORDER = 0; localparam MEM_AUTO_PD_CYCLES = 0; localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 2; localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0; localparam CTL_ECC_MULTIPLES_40_72 = 0; localparam CTL_USR_REFRESH = 0; localparam CTL_REGDIMM_ENABLED = 0; localparam MULTICAST_WR_EN = 0; localparam LOW_LATENCY = 0; localparam CTL_DYNAMIC_BANK_ALLOCATION = 0; localparam CTL_DYNAMIC_BANK_NUM = 4; localparam ENABLE_BURST_MERGE = 0; input ctl_clk; input ctl_reset_n; input ctl_half_clk; input ctl_half_clk_reset_n; output local_ready; input local_read_req; input local_write_req; output local_wdata_req; input [LOCAL_SIZE_WIDTH-1:0] local_size; input local_burstbegin; input [LOCAL_ADDR_WIDTH-1:0] local_addr; output local_rdata_valid; output local_rdata_error; output [LOCAL_DATA_WIDTH-1:0] local_rdata; input [LOCAL_DATA_WIDTH-1:0] local_wdata; input [LOCAL_DATA_WIDTH/8-1:0] local_be; input local_autopch_req; input local_multicast; output local_init_done; input local_refresh_req; input [MEM_IF_CS_WIDTH-1:0] local_refresh_chip; output local_refresh_ack; input local_self_rfsh_req; input [MEM_IF_CS_WIDTH-1:0] local_self_rfsh_chip; output local_self_rfsh_ack; output local_power_down_ack; input ctl_cal_success; input ctl_cal_fail; output ctl_cal_req; output [MEM_IF_CLK_PAIR_COUNT - 1:0] ctl_mem_clk_disable; output [(MEM_IF_DQS_WIDTHMEM_IF_CS_WIDTH) - 1:0] ctl_cal_byte_lane_sel_n; output [(MEM_IF_CKE_WIDTH (DWIDTH_RATIO/2)) - 1:0] afi_cke; output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n; output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n; output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n; output [(DWIDTH_RATIO/2) - 1:0] afi_we_n; output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba; output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr; output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt; output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n; output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_dqs_burst; output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_wdata_valid; output [(MEM_IF_DQ_WIDTHDWIDTH_RATIO) - 1:0] afi_wdata; output [(MEM_IF_DM_WIDTHDWIDTH_RATIO) - 1:0] afi_dm; input [4:0] afi_wlat; output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_doing_read; input [(MEM_IF_DQ_WIDTH * DWIDTH_RATIO) - 1:0] afi_rdata; input [(DWIDTH_RATIO/2) - 1:0] afi_rdata_valid; input csr_write_req; input csr_read_req; input [CSR_ADDR_WIDTH - 1 : 0] csr_addr; input [(CSR_DATA_WIDTH / 8) - 1 : 0] csr_be; input [CSR_DATA_WIDTH - 1 : 0] csr_wdata; output csr_waitrequest; output [CSR_DATA_WIDTH - 1 : 0] csr_rdata; output csr_rdata_valid; output ecc_interrupt; output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) - 1:0] bank_information; output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH)) - 1:0] bank_open; alt_ddrx_controller # ( .MEM_TYPE ( MEM_TYPE ), .LOCAL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ), .LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ), .LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ), .LOCAL_IF_TYPE ( LOCAL_IF_TYPE ), .MEM_IF_CS_WIDTH ( MEM_IF_CS_WIDTH ), .MEM_IF_CHIP_BITS ( MEM_IF_CHIP_BITS ), .MEM_IF_CKE_WIDTH ( MEM_IF_CKE_WIDTH ), .MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ), .MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ), .MEM_IF_ROW_WIDTH ( MEM_IF_ROW_WIDTH ), .MEM_IF_COL_WIDTH ( MEM_IF_COL_WIDTH ), .MEM_IF_BA_WIDTH ( MEM_IF_BA_WIDTH ), .MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ), .MEM_IF_DQ_WIDTH ( MEM_IF_DQ_WIDTH ), .MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ), .MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ), .MEM_IF_CS_PER_DIMM ( MEM_IF_CS_PER_DIMM ), .DWIDTH_RATIO ( DWIDTH_RATIO ), .CTL_LOOK_AHEAD_DEPTH ( CTL_LOOK_AHEAD_DEPTH ), .CTL_CMD_QUEUE_DEPTH ( CTL_CMD_QUEUE_DEPTH ), .CTL_HRB_ENABLED ( CTL_HRB_ENABLED ), .CTL_ECC_ENABLED ( CTL_ECC_ENABLED ), .CTL_ECC_RMW_ENABLED ( CTL_ECC_RMW_ENABLED ), .CTL_ECC_CSR_ENABLED ( CTL_ECC_CSR_ENABLED ), .CTL_ECC_MULTIPLES_40_72 ( CTL_ECC_MULTIPLES_40_72 ), .CTL_CSR_ENABLED ( CTL_CSR_ENABLED ), .CTL_ODT_ENABLED ( CTL_ODT_ENABLED ), .CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ), .CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ), .CSR_DATA_WIDTH ( CSR_DATA_WIDTH ), .CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ), .CTL_USR_REFRESH ( CTL_USR_REFRESH ), .MEM_CAS_WR_LAT ( MEM_CAS_WR_LAT ), .MEM_ADD_LAT ( MEM_ADD_LAT ), .MEM_TCL ( MEM_TCL ), .MEM_TRRD ( MEM_TRRD ), .MEM_TFAW ( MEM_TFAW ), .MEM_TRFC ( MEM_TRFC ), .MEM_TREFI ( MEM_TREFI ), .MEM_TRCD ( MEM_TRCD ), .MEM_TRP ( MEM_TRP ), .MEM_TWR ( MEM_TWR ), .MEM_TWTR ( MEM_TWTR ), .MEM_TRTP ( MEM_TRTP ), .MEM_TRAS ( MEM_TRAS ), .MEM_TRC ( MEM_TRC ), .MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ), .MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ), .MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ), .ADDR_ORDER ( ADDR_ORDER ), .MULTICAST_WR_EN ( MULTICAST_WR_EN ), .LOW_LATENCY ( LOW_LATENCY ), .CTL_DYNAMIC_BANK_ALLOCATION ( CTL_DYNAMIC_BANK_ALLOCATION ), .CTL_DYNAMIC_BANK_NUM ( CTL_DYNAMIC_BANK_NUM ), .ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE ) ) alt_ddrx_controller_inst ( .ctl_clk ( ctl_clk ), .ctl_reset_n ( ctl_reset_n ), .ctl_half_clk ( ctl_half_clk ), .ctl_half_clk_reset_n ( ctl_half_clk_reset_n ), .local_ready ( local_ready ), .local_read_req ( local_read_req ), .local_write_req ( local_write_req ), .local_wdata_req ( local_wdata_req ), .local_size ( local_size ), .local_burstbegin ( local_burstbegin ), .local_addr ( local_addr ), .local_rdata_valid ( local_rdata_valid ), .local_rdata_error ( local_rdata_error ), .local_rdata ( local_rdata ), .local_wdata ( local_wdata ), .local_be ( local_be ), .local_autopch_req ( local_autopch_req ), .local_multicast ( local_multicast ), .local_init_done ( local_init_done ), .local_refresh_req ( local_refresh_req ), .local_refresh_chip ( local_refresh_chip ), .local_refresh_ack ( local_refresh_ack ), .local_self_rfsh_req ( local_self_rfsh_req ), .local_self_rfsh_chip ( local_self_rfsh_chip ), .local_self_rfsh_ack ( local_self_rfsh_ack ), .local_power_down_ack ( local_power_down_ack ), .ctl_cal_success ( ctl_cal_success ), .ctl_cal_fail ( ctl_cal_fail ), .ctl_cal_req ( ctl_cal_req ), .ctl_mem_clk_disable ( ctl_mem_clk_disable ), .ctl_cal_byte_lane_sel_n ( ctl_cal_byte_lane_sel_n ), .afi_cke ( afi_cke ), .afi_cs_n ( afi_cs_n ), .afi_ras_n ( afi_ras_n ), .afi_cas_n ( afi_cas_n ), .afi_we_n ( afi_we_n ), .afi_ba ( afi_ba ), .afi_addr ( afi_addr ), .afi_odt ( afi_odt ), .afi_rst_n ( afi_rst_n ), .afi_dqs_burst ( afi_dqs_burst ), .afi_wdata_valid ( afi_wdata_valid ), .afi_wdata ( afi_wdata ), .afi_dm ( afi_dm ), .afi_wlat ( afi_wlat ), .afi_doing_read ( afi_doing_read ), .afi_doing_read_full ( ), .afi_rdata ( afi_rdata ), .afi_rdata_valid ( afi_rdata_valid ), .csr_write_req ( csr_write_req ), .csr_read_req ( csr_read_req ), .csr_addr ( csr_addr ), .csr_be ( csr_be ), .csr_wdata ( csr_wdata ), .csr_waitrequest ( csr_waitrequest ), .csr_rdata ( csr_rdata ), .csr_rdata_valid ( csr_rdata_valid ), .ecc_interrupt ( ecc_interrupt ), .bank_information ( bank_information ), .bank_open ( bank_open ) ); endmodule
/****************************************************************************** * License Agreement * * * * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * * All rights reserved. * * * * Any megafunction design, and related net list (encrypted or decrypted), * * support information, device programming or simulation file, and any other * * associated documentation or information provided by Altera or a partner * * under Altera's Megafunction Partnership Program may be used only to * * program PLD devices (but not masked PLD devices) from Altera. Any other * * use of such megafunction design, net list, support information, device * * programming or simulation file, or any other related documentation or * * information is prohibited for any other purpose, including, but not * * limited to modification, reverse engineering, de-compiling, or use with * * any other silicon devices, unless such use is explicitly licensed under * * a separate agreement with Altera or a megafunction partner. Title to * * the intellectual property, including patents, copyrights, trademarks, * * trade secrets, or maskworks, embodied in any such megafunction design, * * net list, support information, device programming or simulation file, or * * any other related documentation or information provided by Altera or a * * megafunction partner, remains with Altera, the megafunction partner, or * * their respective licensors. No other licenses, including any licenses * * needed under any third party's intellectual property, are provided herein.* * Copying or modifying any file, or portion thereof, to which this notice * * is attached violates this copyright. * * * * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * * IN THIS FILE. * * * * This agreement shall be governed in all respects by the laws of the State * * of California and by the laws of the United States of America. * * * ****************************************************************************/ /**************************************************************************** * * * This module reads and writes data to the RS232 connectpr on Altera's * * DE1 and DE2 Development and Education Boards. * * * ****************************************************************************/ module altera_up_rs232_counters ( // Inputs clk, reset, reset_counters, // Bidirectionals // Outputs baud_clock_rising_edge, baud_clock_falling_edge, all_bits_transmitted ); /*************************************************************************** * Parameter Declarations * ***************************************************************************/ parameter CW = 9; // BAUD COUNTER WIDTH parameter BAUD_TICK_COUNT = 433; parameter HALF_BAUD_TICK_COUNT = 216; parameter TDW = 11; // TOTAL DATA WIDTH /*************************************************************************** * Port Declarations * ***************************************************************************/ // Inputs input clk; input reset; input reset_counters; // Bidirectionals // Outputs output reg baud_clock_rising_edge; output reg baud_clock_falling_edge; output reg all_bits_transmitted; /*************************************************************************** * Constant Declarations * ***************************************************************************/ /*************************************************************************** * Internal Wires and Registers Declarations * ***************************************************************************/ // Internal Wires // Internal Registers reg [(CW-1):0] baud_counter; reg [ 3: 0] bit_counter; // State Machine Registers /*************************************************************************** * Finite State Machine(s) * ***************************************************************************/ /*************************************************************************** * Sequential Logic * ***************************************************************************/ always @(posedge clk) begin if (reset) baud_counter <= {CW{1'b0}}; else if (reset_counters) baud_counter <= {CW{1'b0}}; else if (baud_counter == BAUD_TICK_COUNT) baud_counter <= {CW{1'b0}}; else baud_counter <= baud_counter + 1; end always @(posedge clk) begin if (reset) baud_clock_rising_edge <= 1'b0; else if (baud_counter == BAUD_TICK_COUNT) baud_clock_rising_edge <= 1'b1; else baud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin if (reset) baud_clock_falling_edge <= 1'b0; else if (baud_counter == HALF_BAUD_TICK_COUNT) baud_clock_falling_edge <= 1'b1; else baud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin if (reset) bit_counter <= 4'h0; else if (reset_counters) bit_counter <= 4'h0; else if (bit_counter == TDW) bit_counter <= 4'h0; else if (baud_counter == BAUD_TICK_COUNT) bit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin if (reset) all_bits_transmitted <= 1'b0; else if (bit_counter == TDW) all_bits_transmitted <= 1'b1; else all_bits_transmitted <= 1'b0; end /*************************************************************************** * Combinational Logic * ***************************************************************************/ /*************************************************************************** * Internal Modules * *****************************************************************************/ endmodule
`timescale 1ns / 1ps // Documented Verilog UART // Copyright (C) 2010 Timothy Goddard ([email protected]) // Distributed under the MIT licence. // // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal // in the Software without restriction, including without limitation the rights // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell // copies of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in // all copies or substantial portions of the Software. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // module uart( input clk, // The master clock for this module input rst, // Synchronous reset. input rx, // Incoming serial line output tx, // Outgoing serial line input transmit, // Signal to transmit input [7:0] tx_byte, // Byte to transmit output received, // Indicated that a byte has been received. output [7:0] rx_byte, // Byte received output is_receiving, // Low when receive line is idle. output is_transmitting, // Low when transmit line is idle. output recv_error // Indicates error in receiving packet. ); parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4) // States for the receiving state machine. // These are just constants, not parameters to override. parameter RX_IDLE = 0; parameter RX_CHECK_START = 1; parameter RX_READ_BITS = 2; parameter RX_CHECK_STOP = 3; parameter RX_DELAY_RESTART = 4; parameter RX_ERROR = 5; parameter RX_RECEIVED = 6; // States for the transmitting state machine. // Constants - do not override. parameter TX_IDLE = 0; parameter TX_SENDING = 1; parameter TX_DELAY_RESTART = 2; reg [10:0] rx_clk_divider = CLOCK_DIVIDE; reg [10:0] tx_clk_divider = CLOCK_DIVIDE; reg [2:0] recv_state = RX_IDLE; reg [5:0] rx_countdown; reg [3:0] rx_bits_remaining; reg [7:0] rx_data; reg tx_out = 1'b1; reg [1:0] tx_state = TX_IDLE; reg [5:0] tx_countdown; reg [3:0] tx_bits_remaining; reg [7:0] tx_data; assign received = recv_state == RX_RECEIVED; assign recv_error = recv_state == RX_ERROR; assign is_receiving = recv_state != RX_IDLE; assign rx_byte = rx_data; assign tx = tx_out; assign is_transmitting = tx_state != TX_IDLE; always @(posedge clk) begin if (rst) begin recv_state = RX_IDLE; tx_state = TX_IDLE; end // The clk_divider counter counts down from // the CLOCK_DIVIDE constant. Whenever it // reaches 0, 1/16 of the bit period has elapsed. // Countdown timers for the receiving and transmitting // state machines are decremented. rx_clk_divider = rx_clk_divider - 1; if (!rx_clk_divider) begin rx_clk_divider = CLOCK_DIVIDE; rx_countdown = rx_countdown - 1; end tx_clk_divider = tx_clk_divider - 1; if (!tx_clk_divider) begin tx_clk_divider = CLOCK_DIVIDE; tx_countdown = tx_countdown - 1; end // Receive state machine case (recv_state) RX_IDLE: begin // A low pulse on the receive line indicates the // start of data. if (!rx) begin // Wait half the period - should resume in the // middle of this first pulse. rx_clk_divider = CLOCK_DIVIDE; rx_countdown = 2; recv_state = RX_CHECK_START; end end RX_CHECK_START: begin if (!rx_countdown) begin // Check the pulse is still there if (!rx) begin // Pulse still there - good // Wait the bit period to resume half-way // through the first bit. rx_countdown = 4; rx_bits_remaining = 8; recv_state = RX_READ_BITS; end else begin // Pulse lasted less than half the period - // not a valid transmission. recv_state = RX_ERROR; end end end RX_READ_BITS: begin if (!rx_countdown) begin // Should be half-way through a bit pulse here. // Read this bit in, wait for the next if we // have more to get. rx_data = {rx, rx_data[7:1]}; rx_countdown = 4; rx_bits_remaining = rx_bits_remaining - 1; recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP; end end RX_CHECK_STOP: begin if (!rx_countdown) begin // Should resume half-way through the stop bit // This should be high - if not, reject the // transmission and signal an error. recv_state = rx ? RX_RECEIVED : RX_ERROR; end end RX_DELAY_RESTART: begin // Waits a set number of cycles before accepting // another transmission. recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE; end RX_ERROR: begin // There was an error receiving. // Raises the recv_error flag for one clock // cycle while in this state and then waits // 2 bit periods before accepting another // transmission. rx_countdown = 8; recv_state = RX_DELAY_RESTART; end RX_RECEIVED: begin // Successfully received a byte. // Raises the received flag for one clock // cycle while in this state. recv_state = RX_IDLE; end endcase // Transmit state machine case (tx_state) TX_IDLE: begin if (transmit) begin // If the transmit flag is raised in the idle // state, start transmitting the current content // of the tx_byte input. tx_data = tx_byte; // Send the initial, low pulse of 1 bit period // to signal the start, followed by the data tx_clk_divider = CLOCK_DIVIDE; tx_countdown = 4; tx_out = 0; tx_bits_remaining = 8; tx_state = TX_SENDING; end end TX_SENDING: begin if (!tx_countdown) begin if (tx_bits_remaining) begin tx_bits_remaining = tx_bits_remaining - 1; tx_out = tx_data[0]; tx_data = {1'b0, tx_data[7:1]}; tx_countdown = 4; tx_state = TX_SENDING; end else begin // Set delay to send out 2 stop bits. tx_out = 1; tx_countdown = 8; tx_state = TX_DELAY_RESTART; end end end TX_DELAY_RESTART: begin // Wait until tx_countdown reaches the end before // we send another transmission. This covers the // "stop bit" delay. tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE; end endcase end endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Case Western Reserve University // Engineer: Matt McConnell // // Create Date: 00:35:00 01/25/2017 // Project Name: EECS301 Digital Design // Design Name: Lab #2 Project // Module Name: CLS_PWM_Interval_Timer // Target Devices: Altera Cyclone V // Tool versions: Quartus v15.0 // Description: PWM Interval Timer // // Dependencies: // ////////////////////////////////////////////////////////////////////////////////// module CLS_PWM_Interval_Timer #( parameter CLK_RATE_HZ = 50000000, // Hz parameter DUTY_RATE_HZ = 1000 // Hz ) ( // Output Signals output reg PWM_TICK, // System Signals input CLK ); // Include Standard Functions header file (needed for bit_index()) `include "StdFunctions.vh" // Initial Parameters initial begin PWM_TICK <= 1'b0; end //!! Add Implementation Here !! // Compute the PWM Interval Counter Parameters localparam PWM_INV_TICKS = CLK_RATE_HZ / DUTY_RATE_HZ; localparam PWM_REG_WIDTH = bit_index(PWM_INV_TICKS); localparam [PWM_REG_WIDTH:0] PWM_INV_LOADVAL = {1'b1, {PWM_REG_WIDTH{1'b0}}} - PWM_INV_TICKS[PWM_REG_WIDTH:0] + 1'b1; wire pwm_inv_tick; reg [PWM_REG_WIDTH:0] pwm_inv_count_reg; // Initialize Registers initial begin pwm_inv_count_reg = PWM_INV_LOADVAL; end // PWM Interval Counter assign pwm_inv_tick = pwm_inv_count_reg[PWM_REG_WIDTH]; always @(*) begin PWM_TICK <= pwm_inv_tick; end always @(posedge CLK) begin if (pwm_inv_tick) pwm_inv_count_reg <= PWM_INV_LOADVAL; else pwm_inv_count_reg <= pwm_inv_count_reg + 1'b1; end endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V `define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V /* * dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage * gates on keep-alive power rail. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none ( blackbox *) module sky130_fd_sc_lp__dlybuf4s25kapwr ( //# {{data\|Data Signals}} input A , output X , //# {{power\|Power}} input KAPWR, input VPB , input VPWR , input VGND , input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t(/AUTOARG/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg [127:0] in; check #(48) check48 (.); check #(31) check31 (.); check #(32) check32 (.); check #(63) check63 (.); check #(64) check64 (.); check #(96) check96 (.); check #(128) check128 (.); always_comb begin if (crc[2:0] == 0) in = '0; else if (crc[2:0] == 1) in = ~'0; else if (crc[2:0] == 2) in = 128'b1; else if (crc[2:0] == 3) in = ~ 128'b1; else begin in = {crc, crc}; if (crc[3]) in[31:0] = '0; if (crc[4]) in[63:32] = '0; if (crc[5]) in[95:64] = '0; if (crc[6]) in[127:96] = '0; if (crc[7]) in[31:0] = ~'0; if (crc[8]) in[63:32] = ~'0; if (crc[9]) in[95:64] = ~'0; if (crc[10]) in[127:96] = ~'0; end end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x\n", $time, cyc, in); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc == 99) begin `checkr(check48.sum, 14574057015683440.000000); `checkr(check31.sum, 114141374814.000000); `checkr(check32.sum, 236547942750.000000); `checkr(check63.sum, 513694866079917670400.000000); `checkr(check64.sum, 1002533584033221181440.000000); `checkr(check96.sum, 4377373669974269260279175970816.000000); `checkr(check128.sum, 18358899571808044815012294240949812330496.000000); $write("-* All Finished -\n"); $finish; end end endmodule module check(/AUTOARG/ // Inputs in, clk, cyc ); parameter WIDTH = 128; input [127:0] in; wire [WIDTH-1:0] ci = in[WIDTH-1:0]; wire signed [WIDTH-1:0] cis = in[WIDTH-1:0]; real r; real rs; always_comb r = ci; always_comb rs = cis; input clk; input integer cyc; real sum; always_ff @ (negedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum); `endif if (cyc < 10) sum <= 0; else sum <= sum + r + rs; end endmodule
/*****************************************************************************/ / Test Bench for FPGA Sort on VC707 Ryohei Kobayashi / / 2016-08-01 / /***************************************************************************/ `default_nettype none `include "define.vh" `include "user_logic.v" `include "sorter.v" /**************************************************************************/ module tb_USER_LOGIC(); reg CLK, RST; wire chnl_rx_clk; wire chnl_rx; wire chnl_rx_ack; wire chnl_rx_last; wire [31:0] chnl_rx_len; wire [30:0] chnl_rx_off; wire [128-1:0] chnl_rx_data; wire chnl_rx_data_valid; wire chnl_rx_data_ren; wire chnl_tx_clk; wire chnl_tx; wire chnl_tx_ack; wire chnl_tx_last; wire [31:0] chnl_tx_len; wire [30:0] chnl_tx_off; wire [128-1:0] chnl_tx_data; wire chnl_tx_data_vaild; wire chnl_tx_data_ren = 1; wire d_busy; wire d_w; wire [`DRAMW-1:0] d_din; wire [`DRAMW-1:0] d_dout; wire d_douten; wire [1:0] d_req; // DRAM access request (read/write) wire [31:0] d_initadr; // dram initial address for the access wire [31:0] d_blocks; // the number of blocks per one access(read/write) reg sortdone; initial begin CLK=0; forever #50 CLK=~CLK; end initial begin RST=1; #400 RST=0; end reg [31:0] cnt; always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1; reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9; always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0; always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1; always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2; always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3; always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4; always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5; always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6; always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7; always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8; always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9; reg [31:0] rslt_cnt; always @(posedge CLK) begin if (RST) begin rslt_cnt <= 0; end else begin if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4; end end always @(posedge CLK) begin if (RST) sortdone <= 0; else if (rslt_cnt == `SORT_ELM) sortdone <= 1; end // Debug Info always @(posedge CLK) begin if (!RST) begin $write("%d\|%d\|Pa%dPb%d\|%d%d%d\|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a); $write("\|"); if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" "); // $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero); // if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" "); // $write("\|"); // if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" "); // $write("\|"); // if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" "); $write("\|"); $write("(%d)", u.core.state); $write("\| %d", u.core.decompressor.dmf_cnt); $write("\| %d %d %d %d %d %d %d %d\| %d %d %d %d %d %d %d %d", u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt, u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt, u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt, u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt); $write("\| %d %d", u.core.ob_a.compressor.tmp.cnt, u.core.ob_b.compressor.tmp.cnt); $write("\| %d %d\|", u.core.ob_a.OB_cnt, u.core.ob_b.OB_cnt); $write("(%d)", u.core.ob_a.buf_t_cnt); // if (u.core.stree_a.F01_emp) $write("------------------------------------ "); else $write("%08x %08x %08x %08x ", u.core.stree_a.F01_dot[127:96], u.core.stree_a.F01_dot[95:64], u.core.stree_a.F01_dot[63:32], u.core.stree_a.F01_dot[31:0]); if (u.core.decompressor.dmf_cnt > (1<<`IB_SIZE)) begin $write("\noverflow at dc"); $finish(); end if (u.core.im00_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_a"); $finish(); end if (u.core.im01_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_a"); $finish(); end if (u.core.im02_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_a"); $finish(); end if (u.core.im03_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_a"); $finish(); end if (u.core.im04_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im04_a"); $finish(); end if (u.core.im05_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im05_a"); $finish(); end if (u.core.im06_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im06_a"); $finish(); end if (u.core.im07_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im07_a"); $finish(); end if (u.core.im00_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_b"); $finish(); end if (u.core.im01_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_b"); $finish(); end if (u.core.im02_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_b"); $finish(); end if (u.core.im03_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_b"); $finish(); end if (u.core.im04_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im04_b"); $finish(); end if (u.core.im05_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im05_b"); $finish(); end if (u.core.im06_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im06_b"); $finish(); end if (u.core.im07_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im07_b"); $finish(); end if (u.core.ob_a.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_a.cmp"); $finish(); end if (u.core.ob_b.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_b.cmp"); $finish(); end if (u.core.ob_a.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_a"); $finish(); end if (u.core.ob_b.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_b"); $finish(); end // if (u.core.phase_b == 1 && u.core.elem_b == 2097136) $finish(); $write(" "); if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" "); if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" "); // $write("\| "); // $write("%d", u.core.dcnt); if (d.app_wdf_wren) $write(" \|M %08x %08x ", d_din[63:32], d_din[31:0]); $write("\n"); $fflush(); end end // checking the result generate if (`INITTYPE=="sorted" \|\| `INITTYPE=="reverse") begin reg [`MERGW-1:0] check_cnt; always @(posedge CLK) begin if (RST) begin check_cnt[31 : 0] <= 1; check_cnt[63 :32] <= 2; check_cnt[95 :64] <= 3; check_cnt[127:96] <= 4; end else begin if (chnl_tx_data_vaild) begin if (check_cnt != chnl_tx_data) begin $write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation $finish(); // for simulation end check_cnt[31 : 0] <= check_cnt[31 : 0] + 4; check_cnt[63 :32] <= check_cnt[63 :32] + 4; check_cnt[95 :64] <= check_cnt[95 :64] + 4; check_cnt[127:96] <= check_cnt[127:96] + 4; end end end end else if (`INITTYPE=="xorshift") begin integer fp; initial begin fp = $fopen("log.txt", "w"); end always @(posedge CLK) begin if (chnl_tx_data_vaild) begin $fwrite(fp, "%08x\n", chnl_tx_data[31:0]); $fwrite(fp, "%08x\n", chnl_tx_data[63:32]); $fwrite(fp, "%08x\n", chnl_tx_data[95:64]); $fwrite(fp, "%08x\n", chnl_tx_data[127:96]); $fflush(); end if (sortdone) $fclose(fp); end end else begin always @(posedge CLK) begin $write("Error! INITTYPE is wrong.\n"); $write("Please make sure src/define.vh\n"); $finish(); end end endgenerate // Show the elapsed cycles always @(posedge CLK) begin if(sortdone) begin : simulation_finish $write("\nIt takes %d cycles\n", cnt); $write("phase0: %d cycles\n", cnt0); $write("phase1: %d cycles\n", cnt1); $write("phase2: %d cycles\n", cnt2); $write("phase3: %d cycles\n", cnt3); $write("phase4: %d cycles\n", cnt4); $write("phase5: %d cycles\n", cnt5); $write("phase6: %d cycles\n", cnt6); $write("phase7: %d cycles\n", cnt7); $write("phase8: %d cycles\n", cnt8); $write("phase9: %d cycles\n", cnt9); $write("Sorting finished!\n"); $finish(); end end // Stub modules /******************************************************************************************/ Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len); DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy); /* Core Module Instantiation */ /******************************************************************************************/ USER_LOGIC u(CLK, RST, chnl_rx_clk, chnl_rx, chnl_rx_ack, chnl_rx_last, chnl_rx_len, chnl_rx_off, chnl_rx_data, chnl_rx_data_valid, chnl_rx_data_ren, chnl_tx_clk, chnl_tx, chnl_tx_ack, chnl_tx_last, chnl_tx_len, chnl_tx_off, chnl_tx_data, chnl_tx_data_vaild, chnl_tx_data_ren, d_busy, // DRAM busy d_din, // DRAM data in d_w, // DRAM write flag d_dout, // DRAM data out d_douten, // DRAM data out enable d_req, // DRAM REQ access request (read/write) d_initadr, // DRAM REQ initial address for the access d_blocks // DRAM REQ the number of blocks per one access ); endmodule /**********************************************************************************************/ /* Xorshift */ /**********************************************************************************************/ module XORSHIFT #(parameter WIDTH = 32, parameter SEED = 1) (input wire CLK, input wire RST, input wire EN, output wire [WIDTH-1:0] RAND_VAL); reg [WIDTH-1:0] x; reg [WIDTH-1:0] y; reg [WIDTH-1:0] z; reg [WIDTH-1:0] w; wire [WIDTH-1:0] t = x^(x<<11); // Mask MSB for not generating the maximum value assign RAND_VAL = {1'b0, w[WIDTH-2:0]}; reg ocen; always @(posedge CLK) ocen <= RST; always @(posedge CLK) begin if (RST) begin x <= 123456789; y <= 362436069; z <= 521288629; w <= 88675123 ^ SEED; end else begin if (EN \|\| ocen) begin x <= y; y <= z; z <= w; w <= (w^(w>>19))^(t^(t>>8)); end end end endmodule /**********************************************************************************************/ module Host_to_FPGA(input wire CLK, input wire RST, input wire ren, output reg chnl_rx, output wire [`MERGW-1:0] dot, output wire doten, output wire [31:0] length); reg rst_buf; always @(posedge CLK) rst_buf <= RST; wire enq; wire deq; wire [`MERGW-1:0] din; wire emp; wire ful; wire [4:0] cnt; reg [`SORTW-1:0] i_d,i_c,i_b,i_a; reg onetime; reg [31:0] enqcnt; reg enqstop; wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00; reg [1:0] selector; // wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} : // (selector == 1) ? {r07,r06,r05,r04} : // (selector == 2) ? {r11,r10,r09,r08} : // (selector == 3) ? {r15,r14,r13,r12} : 0; wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,(r01 % 32'd65536),(r00 % 32'd65536)} : (selector == 1) ? {r07,(r06 % 32'd65536),r05,(r04 % 32'd65536)} : (selector == 2) ? {r11,(r10 % 32'd65536),r09,(r08 % 32'd65536)} : (selector == 3) ? {(r15 % 32'd65536),(r14 % 32'd65536),r13,(r12 % 32'd65536)} : 0; SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt); assign enq = (!enqstop && !ful); assign deq = (ren && !emp); assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a}; assign doten = deq; assign length = `SORT_ELM; always @(posedge CLK) begin if (rst_buf) begin chnl_rx <= 0; onetime <= 1; end else begin chnl_rx <= onetime; onetime <= 0; end end always @(posedge CLK) begin if (rst_buf) enqcnt <= 0; else if (enq) enqcnt <= enqcnt + 4; end always @(posedge CLK) begin if (rst_buf) enqstop <= 0; else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1; end always @(posedge CLK) begin if (rst_buf) selector <= 0; else if (enq) selector <= selector + 1; end generate if (`INITTYPE=="sorted") begin always @(posedge CLK) begin if (rst_buf) begin i_a <= 1; i_b <= 2; i_c <= 3; i_d <= 4; end else begin if (enq) begin i_a <= i_a+4; i_b <= i_b+4; i_c <= i_c+4; i_d <= i_d+4; end end end end else if (`INITTYPE=="reverse") begin always @(posedge CLK) begin if (rst_buf) begin i_a <= `SORT_ELM; i_b <= `SORT_ELM-1; i_c <= `SORT_ELM-2; i_d <= `SORT_ELM-3; end else begin if (enq) begin i_a <= i_a-4; i_b <= i_b-4; i_c <= i_c-4; i_d <= i_d-4; end end end end else if (`INITTYPE=="xorshift") begin XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00); XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01); XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02); XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03); XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04); XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05); XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06); XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07); XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08); XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09); XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10); XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11); XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12); XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13); XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14); XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15); end endgenerate endmodule /**********************************************************************************************/ module DRAM(input wire CLK, // input wire RST, // input wire [1:0] D_REQ, // dram request, load or store input wire [31:0] D_INITADR, // dram request, initial address input wire [31:0] D_ELEM, // dram request, the number of elements input wire [`DRAMW-1:0] D_DIN, // output wire D_W, // output reg [`DRAMW-1:0] D_DOUT, // output reg D_DOUTEN, // output wire D_BUSY); // /*** DRAM **************************************************/ localparam M_REQ = 0; localparam M_WRITE = 1; localparam M_READ = 2; /////////////////////////////////////////////////////////////////////////////////// reg [`DDR3_CMD] app_cmd; reg app_en; wire [`DRAMW-1:0] app_wdf_data; reg app_wdf_wren; wire app_wdf_end = app_wdf_wren; // outputs of u_dram wire [`DRAMW-1:0] app_rd_data; wire app_rd_data_end; wire app_rd_data_valid=1; // in simulation, always ready !! wire app_rdy = 1; // in simulation, always ready !! wire app_wdf_rdy = 1; // in simulation, always ready !! wire ui_clk = CLK; reg [1:0] mode; reg [`DRAMW-1:0] app_wdf_data_buf; reg [31:0] caddr; // check address reg [31:0] remain, remain2; // reg [7:0] req_state; // /////////////////////////////////////////////////////////////////////////////////// reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0]; reg [31:0] app_addr; reg [31:0] dram_addr; always @(posedge CLK) dram_addr <= app_addr; always @(posedge CLK) begin /* DRAM WRITE */ if (RST) begin end else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data; end assign app_rd_data = mem[app_addr[27:3]]; assign app_wdf_data = D_DIN; assign D_BUSY = (mode!=M_REQ); // DRAM busy assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element ///// READ & WRITE PORT CONTROL (begin) //////////////////////////////////////////// always @(posedge ui_clk) begin if (RST) begin mode <= M_REQ; {app_addr, app_cmd, app_en, app_wdf_wren} <= 0; {D_DOUT, D_DOUTEN} <= 0; {caddr, remain, remain2, req_state} <= 0; end else begin case (mode) ///////////////////////////////////////////////////////////////// request M_REQ: begin D_DOUTEN <= 0; if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request app_cmd <= `DRAM_CMD_WRITE; mode <= M_WRITE; app_wdf_wren <= 0; app_en <= 1; app_addr <= D_INITADR; // param, initial address remain <= D_ELEM; // the number of blocks to be written end else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request app_cmd <= `DRAM_CMD_READ; mode <= M_READ; app_wdf_wren <= 0; app_en <= 1; app_addr <= D_INITADR; // param, initial address remain <= D_ELEM; // param, the number of blocks to be read remain2 <= D_ELEM; // param, the number of blocks to be read end else begin app_wdf_wren <= 0; app_en <= 0; end end //////////////////////////////////////////////////////////////////// read M_READ: begin if (app_rdy) begin // read request is accepted. app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8; remain2 <= remain2 - 1; if(remain2==1) app_en <= 0; end D_DOUTEN <= app_rd_data_valid; // dram data_out enable if (app_rd_data_valid) begin D_DOUT <= app_rd_data; caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8; remain <= remain - 1; if(remain==1) begin mode <= M_REQ; end end end /////////////////////////////////////////////////////////////////// write M_WRITE: begin if (app_rdy && app_wdf_rdy) begin app_wdf_wren <= 1; app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8; remain <= remain - 1; if(remain==1) begin mode <= M_REQ; app_en <= 0; end end else app_wdf_wren <= 0; end endcase end end ///// READ & WRITE PORT CONTROL (end) ////////////////////////////////////// endmodule /************************************************************************************************/ `default_nettype wire
/* salsaengine.v * * Copyright (c) 2013 kramble * Parts copyright (c) 2011 [email protected] * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. * / // NB HALFRAM no longer applies, configure via parameters ADDRBITS, THREADS // Bracket this config option in SIM so we don't accidentally leave it set in a live build `ifdef SIM //`define ONETHREAD // Start one thread only (for SIMULATION less confusing and faster startup) `endif `timescale 1ns/1ps module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result ); input hash_clk; input reset; // NB pbkdf_clk domain (need a long reset (at least THREADS+4) to initialize correctly, this is done in pbkdfengine input shift; input start; // NB pbkdf_clk domain output busy; output reg result = 1'b0; parameter SBITS = 8; // Shift data path width input [SBITS-1:0] din; output [SBITS-1:0] dout; // Configure ADDRBITS to allocate RAM for core (automatically sets LOOKAHEAD_GAP) // NB do not use ADDRBITS > 13 for THREADS=8 or ADDRBITS > 14 for THREADS=16 as this is more than // a full scratchpad and the calculation for INT_BITS will be invalid. // These settings are now overriden in ltcminer_icarus.v determined by LOCAL_MINERS ... // These values are for THREADS=8, scratchpad sizes are halved for THREADS=16 // parameter ADDRBITS = 14; // 16MBit RAM allocated to core, full scratchpad for THREADS=16(will not fit LX150) // parameter ADDRBITS = 13; // 8MBit RAM allocated to core, full scratchpad (will not fit LX150) parameter ADDRBITS = 12; // 4MBit RAM allocated to core, half scratchpad // parameter ADDRBITS = 11; // 2MBit RAM allocated to core, quarter scratchpad // parameter ADDRBITS = 10; // 1MBit RAM allocated to core, eighth scratchpad // Do not change THREADS - this must match the salsa pipeline (8 or 16 cycle latency for 8 or 16 threads) parameter THREADS = 16; // NB Phase has THREADS+1 cycles function integer clog2; // Courtesy of razorfishsl, replaces $clog2() input integer value; begin value = value-1; for (clog2=0; value>0; clog2=clog2+1) value = value>>1; end endfunction parameter THREADS_BITS = clog2(THREADS); reg [THREADS_BITS:0]phase = 0; reg [THREADS_BITS:0]phase_d = THREADS; reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0; always @ (posedge hash_clk) // Phase control and sync begin phase <= (phase == THREADS) ? 0 : phase + 1; phase_d <= phase; reset_d <= reset; // Synchronise to hash_clk domain fsmreset <= reset_d; start_d <= start; fsmstart <= start_d; end // Salsa Mix FSM (handles both loading of the scratchpad ROM and the subsequent processing) parameter XSmix = 0, XSload = 1, XSram = 2; // One-hot since these map directly to mux contrls reg [1:0] XCtl = XSmix; parameter R_IDLE=0, R_START=1, R_LOAD=2, R_WRITE=3, R_MIX=4, R_INT=5, R_WAIT=6; reg [2:0] mstate = R_IDLE; reg [10:0] cycle = 11'd0; reg doneROM = 1'd0; // Yes ROM, as its referred thus in the salsa docs reg addrwriteMix = 1'b0; reg addrreadInit = 1'b0; reg addrreadSave = 1'b0; reg xoren = 1'b0; // NB This caclulation does NOT work for ADDRBITS>13 with THREADS=8 or ADDRBITS>14 with THREADS=16 parameter INT_BITS = THREADS_BITS - ADDRBITS + 10; // Max intcycle value is 15 for THREADS=16 and ADDRBITS=10, needing 5 bits // Where INT_BITS==0 we have a full scratchpad and intcycles is not used (though a 1 bit reg[0:0] is still allocated) parameter INT_BITX = (INT_BITS > 0) ? INT_BITS : INT_BITS+1; // Workaround for compilation errors in unused code branches reg [INT_BITS:0] intcycles = 0; // Number of interpolation cycles required wire [511:0] Xmix; reg [511:0] X0; reg [511:0] X1; wire [511:0] X0in; wire [511:0] X1in; wire [511:0] X0out; reg [1023:0] salsaShiftReg; reg [31:0] nonce_sr; // In series with salsaShiftReg assign dout = salsaShiftReg[1023:1024-SBITS]; // sstate is implemented in ram (alternatively could use a rotating shift register) reg [INT_BITS+28:0] sstate [THREADS-1:0]; // NB initialized via a long reset (see pbkdfengine) // List components of sstate here for ease of maintenance ... wire [2:0] mstate_in; wire [10:0] cycle_in; wire [9:0] writeaddr_in; wire doneROM_in; wire addrwriteMix_in; wire addrreadInit_in; wire addrreadSave_in; wire [INT_BITS:0] intcycles_in; wire [9:0] writeaddr_next = writeaddr_in + 10'd1; reg [31:0] snonce [THREADS-1:0]; // Nonce store. Note bidirectional loading below, this will either implement // as registers or dual-port ram, so do NOT integrate with sstate. // NB There is no busy_in or result_in as these flags are NOT saved on a per-thread basis // Convert salsaShiftReg to little-endian word format to match scrypt.c as its easier to debug it // this way rather than recoding the SMix salsa to work with original buffer wire [1023:0] X; `define IDX(x) (((x)+1)(32)-1):((x)(32)) genvar i; generate for (i = 0; i < 32; i = i + 1) begin : Xrewire wire [31:0] tmp; assign tmp = salsaShiftReg[`IDX(i)]; assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] }; end endgenerate // NB writeaddr is cycle counter in R_WRITE so use full size regardless of RAM size ( S = "TRUE" ) reg [9:0] writeaddr = 10'd0; // ALTRAM Max is 256 bit width, so use four // Ram is registered on inputs vis ram_addr, ram_din and ram_wren // Output is unregistered, OLD data on write (less delay than NEW??) wire [9:0] Xaddr; wire [ADDRBITS-1:0]rd_addr; wire [ADDRBITS-1:0]wr_addr1; wire [ADDRBITS-1:0]wr_addr2; wire [ADDRBITS-1:0]wr_addr3; wire [ADDRBITS-1:0]wr_addr4; wire [255:0]ram1_din; wire [255:0]ram1_dout; wire [255:0]ram2_din; wire [255:0]ram2_dout; wire [255:0]ram3_din; wire [255:0]ram3_dout; wire [255:0]ram4_din; wire [255:0]ram4_dout; wire [1023:0]ramout; ( S = "TRUE" ) reg ram_wren = 1'b0; wire ram_clk; assign ram_clk = hash_clk; // Uses same clock as hasher for now // Top ram address is reserved for X0Save/X1save, so adjust wire [15:0] memtop = 16'hfffe; // One less than the top memory location (per THREAD bank) wire [9-INT_BITS:0] adj_addr; if (INT_BITS > 0) assign adj_addr = (Xaddr[9:INT_BITS] == memtop[9:INT_BITS]) ? memtop[9-INT_BITS:0] : Xaddr[9:INT_BITS]; else assign adj_addr = Xaddr; wire [THREADS_BITS-1:0] phase_addr; // Prefix for read address assign phase_addr = phase[THREADS_BITS-1:0]; reg [THREADS_BITS-1:0] phase_addr_d = 0; // Prefix for write address assign rd_addr = { phase_addr, (addrreadSave_in \| addrreadInit_in) ? (addrreadInit_in ? {ADDRBITS-THREADS_BITS{1'b0}} : memtop[ADDRBITS-THREADS_BITS:1]) : adj_addr }; wire [9:0] writeaddr_adj = addrwriteMix ? memtop[10:1] : writeaddr; assign wr_addr1 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; assign wr_addr2 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; assign wr_addr3 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; assign wr_addr4 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; // Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method) ( S = "TRUE" ) reg [ADDRBITS-1:0] rd_addr_z_1 = 0; ( S = "TRUE" ) reg [ADDRBITS-1:0] rd_addr_z_2 = 0; ( S = "TRUE" ) reg [ADDRBITS-1:0] rd_addr_z_3 = 0; ( S = "TRUE" ) reg [ADDRBITS-1:0] rd_addr_z_4 = 0; ( S = "TRUE" ) wire [ADDRBITS-1:0] rd_addr1 = rd_addr \| rd_addr_z_1; ( S = "TRUE" ) wire [ADDRBITS-1:0] rd_addr2 = rd_addr \| rd_addr_z_2; ( S = "TRUE" ) wire [ADDRBITS-1:0] rd_addr3 = rd_addr \| rd_addr_z_3; ( S = "TRUE" ) wire [ADDRBITS-1:0] rd_addr4 = rd_addr \| rd_addr_z_4; ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout); ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout); ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout); ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout); assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout }; // Unregistered output // Two ram data sources, the initial X value and the salsa output assign { ram4_din, ram3_din, ram2_din, ram1_din } = XCtl[0] ? X : { Xmix, X0out}; // Registered input // Salsa unit salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr); // Main multiplexer wire [511:0] Zbits; assign Zbits = {512{xoren}}; // xoren enables xor from ram (else we load from ram) // XSMix is now the default and the initial load is now done via RAM to simplify the pipeline assign X0in = XCtl[1] ? (X0out & Zbits) ^ ramout[511:0] : X0out; assign X1in = XCtl[1] ? (Xmix & Zbits) ^ ramout[1023:512] : Xmix; // Salsa FSM - TODO may want to move this into a separate function (for floorplanning), see hashvariant-C // Hold separate state for each thread (a bit of a kludge to avoid rewriting FSM from scratch) // NB must ensure shift and result do NOT overlap by carefully controlling timing of start signal // NB Phase has THREADS+1 cycles, but we do not save the state for (phase==THREADS) as it is never active assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrwriteMix_in, addrreadInit_in, addrreadSave_in, intcycles_in} = (phase == THREADS ) ? 0 : sstate[phase]; // Interface FSM ensures threads start evenly (required for correct salsa FSM operation) reg busy_flag = 1'b0; `ifdef ONETHREAD // TEST CONTROLLER ... just allow a single thread to run (busy is currently a common flag) // NB the thread automatically restarts after it completes, so its a slight misnomer to say it starts once. reg start_once = 1'b0; wire start_flag; assign start_flag = fsmstart & ~start_once; assign busy = busy_flag; // Ack to pbkdfengine `else // NB start_flag only has effect when a thread is at R_IDLE, ie after reset, normally a thread will automatically // restart on completion. We need to spread the R_IDLE starts evenly to ensure proper ooperation. NB the pbkdf // engine requires busy and result, but this looks alter itself in the salsa FSM, even though these are global // flags. Reset periodically (on loadnonce in pbkdfengine) to ensure it stays in sync. reg [15:0] start_count = 0; // For THREADS=8, lookup_gap=2 salsa takes on average 9(1024+(10241.5)) = 23040 clocks, generically 91024(lookup_gap/2+1.5) // For THREADS=16, use 171024(lookup_gap/2+1.5), where lookupgap is double that for THREADS=8 // This is OK, but only does ADDRBITS=10,11,12 ... // parameter START_INTERVAL = (THREADS==16) ? ((ADDRBITS==12) ? 60928 : (ADDRBITS==11) ? 95744 : 165376) / THREADS : // 16 threads // ((ADDRBITS==12) ? 23040 : (ADDRBITS==11) ? 36864 : 50688) / THREADS ; // 8 threads // This seems to work OK generically (TODO check full scratchpad) ... parameter START_INTERVAL = (THREADS+1) 1024 * ((1 << (15-ADDRBITS)) * THREADS / 32 + 3) / THREADS / 2; reg start_flag = 1'b0; assign busy = busy_flag; // Ack to pbkdfengine - this will toggle on transtion through R_START `endif always @ (posedge hash_clk) begin X0 <= X0in; X1 <= X1in; if (phase_d != THREADS) sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrwriteMix, addrreadInit, addrreadSave, intcycles }; mstate <= mstate_in; // Set defaults (overridden below as necessary) writeaddr <= writeaddr_in; cycle <= cycle_in; intcycles <= intcycles_in; doneROM <= doneROM_in; addrwriteMix <= addrwriteMix_in; addrreadInit <= addrreadInit_in; addrreadSave <= addrreadSave_in; // Overwritten below, but addrreadSave_in is used above // Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method) rd_addr_z_1 <= {ADDRBITS{fsmreset}}; rd_addr_z_2 <= {ADDRBITS{fsmreset}}; rd_addr_z_3 <= {ADDRBITS{fsmreset}}; rd_addr_z_4 <= {ADDRBITS{fsmreset}}; phase_addr_d <= phase[THREADS_BITS-1:0]; XCtl <= XSmix; // Default states addrreadInit <= 1'b0; // NB addrreadInit_in is the active control so this DOES need to be in sstate addrreadSave <= 1'b0; // Ditto ram_wren <= 1'b0; xoren <= 1'b1; // Interface FSM ensures threads start evenly (required for correct salsa FSM operation) `ifdef ONETHREAD if (fsmstart && phase!=THREADS) start_once <= 1'b1; if (fsmreset) start_once <= 1'b0; `else start_count <= start_count + 1; // start_flag <= 1'b0; // Done below when we transition out of R_IDLE if (fsmreset \|\| start_count == START_INTERVAL) begin start_count <= 0; if (~fsmreset && fsmstart) start_flag <= 1'b1; end `endif // Could use explicit mux for this ... if (shift) begin salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] }; nonce_sr <= { nonce_sr[31-SBITS:0], din}; end else if (XCtl[0] && phase_d != THREADS) // Set at end of previous hash - this is executed regardless of phase begin salsaShiftReg <= ramout; // Simultaneously with XSload nonce_sr <= snonce[phase_d]; // NB bidirectional load snonce[phase_d] <= nonce_sr; end if (fsmreset == 1'b1) begin mstate <= R_IDLE; // This will propagate to all sstate slots as we hold reset for 10 cycles busy_flag <= 1'b0; result <= 1'b0; end else begin case (mstate_in) R_IDLE: begin // R_IDLE only applies after reset. Normally each thread will reenter at S_START and // assumes that input data is waiting (this relies on the threads being started evenly, // hence the interface FSM at the top of this file) if (phase!=THREADS && start_flag) // Ensure (phase==THREADS) slot is never active begin `ifndef ONETHREAD start_flag <= 1'b0; `endif busy_flag <= 1'b0; // Toggle the busy flag low to ack pbkdfengine (its usually already set // since other threads are running) mstate <= R_START; // We cycle the initial data through the RAM to simplify the data path (costs 17 clocks) // Setup to write initial data to ram (on next clock) writeaddr <= 0; addrwriteMix <= 1'b0; ram_wren <= 1'b1; // Setup to read initial data back from ram (17 clocks later) XCtl <= XSload; addrreadInit <= 1'b1; end end R_START: begin // Reentry point after thread completion. ASSUMES new data is ready. XCtl <= XSram; // Load from ram next cycle xoren <= 1'b0; cycle <= 0; doneROM <= 1'b0; busy_flag <= 1'b1; result <= 1'b0; mstate <= R_LOAD; end R_LOAD: begin // Now loading initial data via RAM to simplify data path (costs 17 clocks) writeaddr <= writeaddr_next; if (INT_BITS == 0) ram_wren <= 1'b1; // Full scratchpad needs to write to addr=001 next cycle mstate <= R_WRITE; end R_WRITE: begin writeaddr <= writeaddr_next; if (writeaddr_in==1022) doneROM <= 1'b1; // Need to do one more cycle to update X0,X1 if (doneROM_in) begin addrwriteMix <= 1'b1; // Remains set for duration of R_MIX mstate <= R_MIX; XCtl <= XSram; // Load from ram next cycle (xor'd with XMix) // Need this to cover the case of the initial read being interpolated // NB CODE IS REPLICATED IN R_MIX if (INT_BITS > 0) begin intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] }; // Interpolated addresses if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) // Highest address reserved intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] }; if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) \|\| \|Xaddr[INT_BITX-1:0] ) begin ram_wren <= 1'b1; xoren <= 1'b0; // Will do direct load from ram, not xor mstate <= R_INT; // Interpolate end // If intcycles will be set to 1, need to preset for readback if ( ( Xaddr[INT_BITX-1:0] == 1 ) && !( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) ) addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) end // END REPLICATED BLOCK end else begin ram_wren <= (INT_BITS > 0) ? ~\|writeaddr_next[INT_BITX-1:0] : 1'b1; end end R_MIX: begin // NB There is an extra step here cf R_WRITE above to read ram data hence 9 not 8 stages. cycle <= cycle_in + 11'd1; if (cycle_in==1023) begin // We now ALWAYS write result to ram, thus simplifying the data path at the cost of 17 clock cycles mstate <= R_WAIT; addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) ram_wren <= 1'b1; // Save result end else begin XCtl <= XSram; // Load from ram next cycle (xor'd with XMix) // NB CODE IS REPLICATED IN R_WRITE if (INT_BITS > 0) begin intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] }; // Interpolated addresses if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) // Highest address reserved intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] }; if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) \|\| \|Xaddr[INT_BITX-1:0] ) begin ram_wren <= 1'b1; xoren <= 1'b0; // Will do direct load from ram, not xor mstate <= R_INT; // Interpolate end // If intcycles will be set to 1, need to preset for readback if ( ( Xaddr[INT_BITX-1:0] == 1 ) && !( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) ) addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) end // END REPLICATED BLOCK end end R_INT: begin // Interpolate scratchpad for odd addresses intcycles <= intcycles_in - 1; if (intcycles_in==2) addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) if (intcycles_in==1) begin XCtl <= XSram; // Setup to XOR from saved X0/X1 in ram at next cycle mstate <= R_MIX; end // Else mstate remains at R_INT so we continue interpolating end R_WAIT: begin if (fsmstart) // Check data input is ready begin // Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32 busy_flag <= 1'b0; // Will hold at 0 for 17 clocks until set at R_START result <= 1'b1; mstate <= R_START; // Restart immediately // We cycle the initial data through the RAM to simplify the data path (costs 17 clocks) // Setup to write initial data to ram (on next clock) writeaddr <= 0; // Preset to write X on next cycle addrwriteMix <= 1'b0; ram_wren <= 1'b1; // Setup to read initial data back from ram (17 clocks later) XCtl <= XSload; addrreadInit <= 1'b1; end else addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) end endcase end `ifdef SIM // Print the final Xmix for each cycle to compare with scrypt.c (debugging) // if (mstate==R_MIX) // $display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]); `endif end // always @(posedge hash_clk) endmodule
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module video_sys_CPU_test_bench ( // inputs: D_iw, D_iw_op, D_iw_opx, D_valid, E_alu_result, E_mem_byte_en, E_st_data, E_valid, F_pcb, F_valid, R_ctrl_exception, R_ctrl_ld, R_ctrl_ld_non_io, R_dst_regnum, R_wr_dst_reg, W_bstatus_reg, W_cmp_result, W_estatus_reg, W_ienable_reg, W_ipending_reg, W_mem_baddr, W_rf_wr_data, W_status_reg, W_valid, W_vinst, W_wr_data, av_ld_data_aligned_unfiltered, clk, d_address, d_byteenable, d_read, d_write_nxt, i_address, i_read, i_readdata, i_waitrequest, reset_n, // outputs: av_ld_data_aligned_filtered, d_write, test_has_ended ) ; output [ 31: 0] av_ld_data_aligned_filtered; output d_write; output test_has_ended; input [ 31: 0] D_iw; input [ 5: 0] D_iw_op; input [ 5: 0] D_iw_opx; input D_valid; input [ 31: 0] E_alu_result; input [ 3: 0] E_mem_byte_en; input [ 31: 0] E_st_data; input E_valid; input [ 24: 0] F_pcb; input F_valid; input R_ctrl_exception; input R_ctrl_ld; input R_ctrl_ld_non_io; input [ 4: 0] R_dst_regnum; input R_wr_dst_reg; input W_bstatus_reg; input W_cmp_result; input W_estatus_reg; input [ 31: 0] W_ienable_reg; input [ 31: 0] W_ipending_reg; input [ 24: 0] W_mem_baddr; input [ 31: 0] W_rf_wr_data; input W_status_reg; input W_valid; input [ 55: 0] W_vinst; input [ 31: 0] W_wr_data; input [ 31: 0] av_ld_data_aligned_unfiltered; input clk; input [ 24: 0] d_address; input [ 3: 0] d_byteenable; input d_read; input d_write_nxt; input [ 24: 0] i_address; input i_read; input [ 31: 0] i_readdata; input i_waitrequest; input reset_n; wire D_op_add; wire D_op_addi; wire D_op_and; wire D_op_andhi; wire D_op_andi; wire D_op_beq; wire D_op_bge; wire D_op_bgeu; wire D_op_blt; wire D_op_bltu; wire D_op_bne; wire D_op_br; wire D_op_break; wire D_op_bret; wire D_op_call; wire D_op_callr; wire D_op_cmpeq; wire D_op_cmpeqi; wire D_op_cmpge; wire D_op_cmpgei; wire D_op_cmpgeu; wire D_op_cmpgeui; wire D_op_cmplt; wire D_op_cmplti; wire D_op_cmpltu; wire D_op_cmpltui; wire D_op_cmpne; wire D_op_cmpnei; wire D_op_crst; wire D_op_custom; wire D_op_div; wire D_op_divu; wire D_op_eret; wire D_op_flushd; wire D_op_flushda; wire D_op_flushi; wire D_op_flushp; wire D_op_hbreak; wire D_op_initd; wire D_op_initda; wire D_op_initi; wire D_op_intr; wire D_op_jmp; wire D_op_jmpi; wire D_op_ldb; wire D_op_ldbio; wire D_op_ldbu; wire D_op_ldbuio; wire D_op_ldh; wire D_op_ldhio; wire D_op_ldhu; wire D_op_ldhuio; wire D_op_ldl; wire D_op_ldw; wire D_op_ldwio; wire D_op_mul; wire D_op_muli; wire D_op_mulxss; wire D_op_mulxsu; wire D_op_mulxuu; wire D_op_nextpc; wire D_op_nor; wire D_op_opx; wire D_op_or; wire D_op_orhi; wire D_op_ori; wire D_op_rdctl; wire D_op_rdprs; wire D_op_ret; wire D_op_rol; wire D_op_roli; wire D_op_ror; wire D_op_rsv02; wire D_op_rsv09; wire D_op_rsv10; wire D_op_rsv17; wire D_op_rsv18; wire D_op_rsv25; wire D_op_rsv26; wire D_op_rsv33; wire D_op_rsv34; wire D_op_rsv41; wire D_op_rsv42; wire D_op_rsv49; wire D_op_rsv57; wire D_op_rsv61; wire D_op_rsv62; wire D_op_rsv63; wire D_op_rsvx00; wire D_op_rsvx10; wire D_op_rsvx15; wire D_op_rsvx17; wire D_op_rsvx21; wire D_op_rsvx25; wire D_op_rsvx33; wire D_op_rsvx34; wire D_op_rsvx35; wire D_op_rsvx42; wire D_op_rsvx43; wire D_op_rsvx44; wire D_op_rsvx47; wire D_op_rsvx50; wire D_op_rsvx51; wire D_op_rsvx55; wire D_op_rsvx56; wire D_op_rsvx60; wire D_op_rsvx63; wire D_op_sll; wire D_op_slli; wire D_op_sra; wire D_op_srai; wire D_op_srl; wire D_op_srli; wire D_op_stb; wire D_op_stbio; wire D_op_stc; wire D_op_sth; wire D_op_sthio; wire D_op_stw; wire D_op_stwio; wire D_op_sub; wire D_op_sync; wire D_op_trap; wire D_op_wrctl; wire D_op_wrprs; wire D_op_xor; wire D_op_xorhi; wire D_op_xori; wire [ 31: 0] av_ld_data_aligned_filtered; wire av_ld_data_aligned_unfiltered_0_is_x; wire av_ld_data_aligned_unfiltered_10_is_x; wire av_ld_data_aligned_unfiltered_11_is_x; wire av_ld_data_aligned_unfiltered_12_is_x; wire av_ld_data_aligned_unfiltered_13_is_x; wire av_ld_data_aligned_unfiltered_14_is_x; wire av_ld_data_aligned_unfiltered_15_is_x; wire av_ld_data_aligned_unfiltered_16_is_x; wire av_ld_data_aligned_unfiltered_17_is_x; wire av_ld_data_aligned_unfiltered_18_is_x; wire av_ld_data_aligned_unfiltered_19_is_x; wire av_ld_data_aligned_unfiltered_1_is_x; wire av_ld_data_aligned_unfiltered_20_is_x; wire av_ld_data_aligned_unfiltered_21_is_x; wire av_ld_data_aligned_unfiltered_22_is_x; wire av_ld_data_aligned_unfiltered_23_is_x; wire av_ld_data_aligned_unfiltered_24_is_x; wire av_ld_data_aligned_unfiltered_25_is_x; wire av_ld_data_aligned_unfiltered_26_is_x; wire av_ld_data_aligned_unfiltered_27_is_x; wire av_ld_data_aligned_unfiltered_28_is_x; wire av_ld_data_aligned_unfiltered_29_is_x; wire av_ld_data_aligned_unfiltered_2_is_x; wire av_ld_data_aligned_unfiltered_30_is_x; wire av_ld_data_aligned_unfiltered_31_is_x; wire av_ld_data_aligned_unfiltered_3_is_x; wire av_ld_data_aligned_unfiltered_4_is_x; wire av_ld_data_aligned_unfiltered_5_is_x; wire av_ld_data_aligned_unfiltered_6_is_x; wire av_ld_data_aligned_unfiltered_7_is_x; wire av_ld_data_aligned_unfiltered_8_is_x; wire av_ld_data_aligned_unfiltered_9_is_x; reg d_write; wire test_has_ended; assign D_op_call = D_iw_op == 0; assign D_op_jmpi = D_iw_op == 1; assign D_op_ldbu = D_iw_op == 3; assign D_op_addi = D_iw_op == 4; assign D_op_stb = D_iw_op == 5; assign D_op_br = D_iw_op == 6; assign D_op_ldb = D_iw_op == 7; assign D_op_cmpgei = D_iw_op == 8; assign D_op_ldhu = D_iw_op == 11; assign D_op_andi = D_iw_op == 12; assign D_op_sth = D_iw_op == 13; assign D_op_bge = D_iw_op == 14; assign D_op_ldh = D_iw_op == 15; assign D_op_cmplti = D_iw_op == 16; assign D_op_initda = D_iw_op == 19; assign D_op_ori = D_iw_op == 20; assign D_op_stw = D_iw_op == 21; assign D_op_blt = D_iw_op == 22; assign D_op_ldw = D_iw_op == 23; assign D_op_cmpnei = D_iw_op == 24; assign D_op_flushda = D_iw_op == 27; assign D_op_xori = D_iw_op == 28; assign D_op_stc = D_iw_op == 29; assign D_op_bne = D_iw_op == 30; assign D_op_ldl = D_iw_op == 31; assign D_op_cmpeqi = D_iw_op == 32; assign D_op_ldbuio = D_iw_op == 35; assign D_op_muli = D_iw_op == 36; assign D_op_stbio = D_iw_op == 37; assign D_op_beq = D_iw_op == 38; assign D_op_ldbio = D_iw_op == 39; assign D_op_cmpgeui = D_iw_op == 40; assign D_op_ldhuio = D_iw_op == 43; assign D_op_andhi = D_iw_op == 44; assign D_op_sthio = D_iw_op == 45; assign D_op_bgeu = D_iw_op == 46; assign D_op_ldhio = D_iw_op == 47; assign D_op_cmpltui = D_iw_op == 48; assign D_op_initd = D_iw_op == 51; assign D_op_orhi = D_iw_op == 52; assign D_op_stwio = D_iw_op == 53; assign D_op_bltu = D_iw_op == 54; assign D_op_ldwio = D_iw_op == 55; assign D_op_rdprs = D_iw_op == 56; assign D_op_flushd = D_iw_op == 59; assign D_op_xorhi = D_iw_op == 60; assign D_op_rsv02 = D_iw_op == 2; assign D_op_rsv09 = D_iw_op == 9; assign D_op_rsv10 = D_iw_op == 10; assign D_op_rsv17 = D_iw_op == 17; assign D_op_rsv18 = D_iw_op == 18; assign D_op_rsv25 = D_iw_op == 25; assign D_op_rsv26 = D_iw_op == 26; assign D_op_rsv33 = D_iw_op == 33; assign D_op_rsv34 = D_iw_op == 34; assign D_op_rsv41 = D_iw_op == 41; assign D_op_rsv42 = D_iw_op == 42; assign D_op_rsv49 = D_iw_op == 49; assign D_op_rsv57 = D_iw_op == 57; assign D_op_rsv61 = D_iw_op == 61; assign D_op_rsv62 = D_iw_op == 62; assign D_op_rsv63 = D_iw_op == 63; assign D_op_eret = D_op_opx & (D_iw_opx == 1); assign D_op_roli = D_op_opx & (D_iw_opx == 2); assign D_op_rol = D_op_opx & (D_iw_opx == 3); assign D_op_flushp = D_op_opx & (D_iw_opx == 4); assign D_op_ret = D_op_opx & (D_iw_opx == 5); assign D_op_nor = D_op_opx & (D_iw_opx == 6); assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); assign D_op_bret = D_op_opx & (D_iw_opx == 9); assign D_op_ror = D_op_opx & (D_iw_opx == 11); assign D_op_flushi = D_op_opx & (D_iw_opx == 12); assign D_op_jmp = D_op_opx & (D_iw_opx == 13); assign D_op_and = D_op_opx & (D_iw_opx == 14); assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); assign D_op_slli = D_op_opx & (D_iw_opx == 18); assign D_op_sll = D_op_opx & (D_iw_opx == 19); assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); assign D_op_or = D_op_opx & (D_iw_opx == 22); assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); assign D_op_srli = D_op_opx & (D_iw_opx == 26); assign D_op_srl = D_op_opx & (D_iw_opx == 27); assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); assign D_op_callr = D_op_opx & (D_iw_opx == 29); assign D_op_xor = D_op_opx & (D_iw_opx == 30); assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); assign D_op_divu = D_op_opx & (D_iw_opx == 36); assign D_op_div = D_op_opx & (D_iw_opx == 37); assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); assign D_op_mul = D_op_opx & (D_iw_opx == 39); assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); assign D_op_initi = D_op_opx & (D_iw_opx == 41); assign D_op_trap = D_op_opx & (D_iw_opx == 45); assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); assign D_op_add = D_op_opx & (D_iw_opx == 49); assign D_op_break = D_op_opx & (D_iw_opx == 52); assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); assign D_op_sync = D_op_opx & (D_iw_opx == 54); assign D_op_sub = D_op_opx & (D_iw_opx == 57); assign D_op_srai = D_op_opx & (D_iw_opx == 58); assign D_op_sra = D_op_opx & (D_iw_opx == 59); assign D_op_intr = D_op_opx & (D_iw_opx == 61); assign D_op_crst = D_op_opx & (D_iw_opx == 62); assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); assign D_op_opx = D_iw_op == 58; assign D_op_custom = D_iw_op == 50; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d_write <= 0; else d_write <= d_write_nxt; end assign test_has_ended = 1'b0; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //Clearing 'X' data bits assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; always @(posedge clk) begin if (reset_n) if (^(F_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/F_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(D_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/D_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(E_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/E_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(W_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/W_valid is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid) if (^(R_wr_dst_reg) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/R_wr_dst_reg is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_wr_dst_reg) if (^(W_wr_data) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/W_wr_data is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_wr_dst_reg) if (^(R_dst_regnum) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/R_dst_regnum is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(d_write) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_write is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (d_write) if (^(d_byteenable) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_byteenable is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (d_write \| d_read) if (^(d_address) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_address is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(d_read) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_read is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(i_read) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/i_read is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (i_read) if (^(i_address) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/i_address is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (i_read & ~i_waitrequest) if (^(i_readdata) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/i_readdata is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_ctrl_ld) if (^(av_ld_data_aligned_unfiltered) === 1'bx) begin $write("%0d ns: WARNING: video_sys_CPU_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_wr_dst_reg) if (^(W_wr_data) === 1'bx) begin $write("%0d ns: WARNING: video_sys_CPU_test_bench/W_wr_data is 'x'\n", $time); end end reg [31:0] trace_handle; // for $fopen initial begin trace_handle = $fopen("video_sys_CPU.tr"); $fwrite(trace_handle, "version 3\nnumThreads 1\n"); end always @(posedge clk) begin if ((~reset_n \|\| (W_valid)) && ~test_has_ended) $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr \| D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0); end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // // assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; // //synthesis read_comments_as_HDL off endmodule
// megafunction wizard: %ROM: 1-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: pizza.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ********************************************************** // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.1.1 Build 166 11/26/2013 SJ Full Version // ********************************************************** //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module pizza ( address, clock, q); input [11:0] address; input clock; output [11:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "./sprites/pizza.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" // Retrieval info: PRIVATE: WidthData NUMERIC "12" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/pizza.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "12" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]" // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf
(** * Extraction: Extracting ML from Coq ) (* * Basic Extraction ) (* In its simplest form, program extraction from Coq is completely straightforward. ) (* First we say what language we want to extract into. Options are OCaml (the most mature), Haskell (which mostly works), and Scheme (a bit out of date). ) Extraction Language Ocaml. (* Now we load up the Coq environment with some definitions, either directly or by importing them from other modules. ) Require Import SfLib. Require Import ImpCEvalFun. (* Finally, we tell Coq the name of a definition to extract and the name of a file to put the extracted code into. ) Extraction "imp1.ml" ceval_step. (* When Coq processes this command, it generates a file [imp1.ml] containing an extracted version of [ceval_step], together with everything that it recursively depends on. Have a look at this file now. ) ( ############################################################## ) (* * Controlling Extraction of Specific Types ) (* We can tell Coq to extract certain [Inductive] definitions to specific OCaml types. For each one, we must say - how the Coq type itself should be represented in OCaml, and - how each constructor should be translated. ) Extract Inductive bool => "bool" [ "true" "false" ]. (* Also, for non-enumeration types (where the constructors take arguments), we give an OCaml expression that can be used as a "recursor" over elements of the type. (Think Church numerals.) ) Extract Inductive nat => "int" [ "0" "(fun x -> x + 1)" ] "(fun zero succ n -> if n=0 then zero () else succ (n-1))". (* We can also extract defined constants to specific OCaml terms or operators. ) Extract Constant plus => "( + )". Extract Constant mult => "( )". Extract Constant beq_nat => "( = )". (** Important: It is entirely _your responsibility_ to make sure that the translations you're proving make sense. For example, it might be tempting to include this one Extract Constant minus => "( - )". but doing so could lead to serious confusion! (Why?) ) Extraction "imp2.ml" ceval_step. (* Have a look at the file [imp2.ml]. Notice how the fundamental definitions have changed from [imp1.ml]. ) ( ############################################################## ) (* * A Complete Example ) (* To use our extracted evaluator to run Imp programs, all we need to add is a tiny driver program that calls the evaluator and somehow prints out the result. For simplicity, we'll print results by dumping out the first four memory locations in the final state. Also, to make it easier to type in examples, let's extract a parser from the [ImpParser] Coq module. To do this, we need a few more declarations to set up the right correspondence between Coq strings and lists of OCaml characters. ) Require Import Ascii String. Extract Inductive ascii => char [ "( If this appears, you're using Ascii internals. Please don't ) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))" ] "( If this appears, you're using Ascii internals. Please don't ) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))". Extract Constant zero => "'\000'". Extract Constant one => "'\001'". Extract Constant shift => "fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)". Extract Inlined Constant ascii_dec => "(=)". (* We also need one more variant of booleans. ) Extract Inductive sumbool => "bool" ["true" "false"]. (* The extraction is the same as always. ) Require Import Imp. Require Import ImpParser. Extraction "imp.ml" empty_state ceval_step parse. (* Now let's run our generated Imp evaluator. First, have a look at [impdriver.ml]. (This was written by hand, not extracted.) Next, compile the driver together with the extracted code and execute it, as follows. << ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml ./impdriver >> (The [-w] flags to [ocamlc] are just there to suppress a few spurious warnings.) ) ( ############################################################## ) (* * Discussion ) (* Since we've proved that the [ceval_step] function behaves the same as the [ceval] relation in an appropriate sense, the extracted program can be viewed as a _certified_ Imp interpreter. (Of course, the parser is not certified in any interesting sense, since we didn't prove anything about it.) ) (* $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
////////////////////////////////////////////////////////////////////////////////// // NPM_Toggle_POR for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Ilyong Jung <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Ilyong Jung <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: NPM_Toggle_POR // Module Name: NPM_Toggle_POR // File Name: NPM_Toggle_POR.v // // Version: v1.0.0 // // Description: NFC PM output module reset // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module NPM_Toggle_POR ( iSystemClock , iReset , oReady , oLastStep , iStart , oPO_Reset ); input iSystemClock ; input iReset ; output oReady ; output oLastStep ; input iStart ; output oPO_Reset ; // FSM Parameters/Wires/Regs parameter POR_FSM_BIT = 4; parameter POR_RESET = 4'b0001; parameter POR_READY = 4'b0010; parameter POR_RFRST = 4'b0100; // reset first parameter POR_RLOOP = 4'b1000; // reset loop reg [POR_FSM_BIT-1:0] rPOR_cur_state ; reg [POR_FSM_BIT-1:0] rPOR_nxt_state ; // Internal Wires/Regs reg rReady ; reg [3:0] rTimer ; wire wJOBDone ; reg rPO_Reset ; // Control Signals // Flow Control assign wJOBDone = (4'b1001 == rTimer[3:0]); // 1 + '9' = 10 cycles // FSM // update current state to next state always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rPOR_cur_state <= POR_RESET; end else begin rPOR_cur_state <= rPOR_nxt_state; end end // deside next state always @ ( * ) begin case (rPOR_cur_state) POR_RESET: begin rPOR_nxt_state <= POR_READY; end POR_READY: begin rPOR_nxt_state <= (iStart)? POR_RFRST:POR_READY; end POR_RFRST: begin rPOR_nxt_state <= POR_RLOOP; end POR_RLOOP: begin rPOR_nxt_state <= (wJOBDone)? ((iStart)? POR_RFRST:POR_READY):POR_RLOOP; end default: rPOR_nxt_state <= POR_READY; endcase end // state behaviour always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rReady <= 0; rTimer[3:0] <= 0; rPO_Reset <= 0; end else begin case (rPOR_nxt_state) POR_RESET: begin rReady <= 0; rTimer[3:0] <= 0; rPO_Reset <= 0; end POR_READY: begin rReady <= 1; rTimer[3:0] <= 0; rPO_Reset <= 0; end POR_RFRST: begin rReady <= 0; rTimer[3:0] <= 4'b0000; rPO_Reset <= 1; end POR_RLOOP: begin rReady <= 0; rTimer[3:0] <= rTimer[3:0] + 1'b1; rPO_Reset <= 1; end endcase end end // Output assign oReady = rReady \| wJOBDone ; assign oLastStep = wJOBDone ; assign oPO_Reset = rPO_Reset ; endmodule
// // Spartan-3E on-chip RAM interface. // // Author(s): // - Serge Vakulenko, [email protected] // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // either version 2.1 of the License, or (at your option) any // later version. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.opencores.org/lgpl.shtml // //---------------------- // CVS Revision History // // $Log: onchip_ram_top.v,v $ // Revision 1.3 2006-12-22 17:16:26 vak // Added comments and copyrights. // // Revision 1.2 2006/12/22 11:07:34 vak // Amount of on-chip RAM increased to 16 kbytes. // The generated bit file is successfully downloaded to the target board. // Debug interface is functioning (jp1) via Xilinx parallel cable III. // Hello-uart is running fine. // // Revision 1.1 2006/12/22 08:34:00 vak // The design is successfully compiled using on-chip RAM. // // synopsys translate_off `include "timescale.v" // synopsys translate_on module onchip_ram_top ( // // I/O Ports // input wb_clk_i, input wb_rst_i, // // WB slave i/f // input [31:0] wb_dat_i, output [31:0] wb_dat_o, input [31:0] wb_adr_i, input [3:0] wb_sel_i, input wb_we_i, input wb_cyc_i, input wb_stb_i, output wb_ack_o, output wb_err_o ); // // Paraneters // parameter AW = 12; // RAM size = 4 kwords (16 kbytes) // // Internal wires and regs // wire we; wire [3:0] be_i; reg ack_we; reg ack_re; // // Aliases and simple assignments // assign wb_ack_o = ack_re \| ack_we; assign wb_err_o = wb_cyc_i & wb_stb_i & (\| wb_adr_i[23:AW+2]); // If Access to > (8-bit leading prefix ignored) assign we = wb_cyc_i & wb_stb_i & wb_we_i & (\| wb_sel_i[3:0]); assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; // // Write acknowledge // always @ (negedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) ack_we <= 1'b0; else if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) ack_we <= #1 1'b1; else ack_we <= #1 1'b0; end // // Read acknowledge // always @ (posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) ack_re <= 1'b0; else if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) ack_re <= #1 1'b1; else ack_re <= #1 1'b0; end // // Generate 8 blocks of standard Xilinx library component: // 16K-Bit Data and 2K-Bit Parity Single Port Block RAM // RAMB16_S4 block_ram_00 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [3 : 0]), .DO (wb_dat_o [3 : 0]), .EN (be_i [0]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_01 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [7 : 4]), .DO (wb_dat_o [7 : 4]), .EN (be_i [0]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_10 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [11 : 8]), .DO (wb_dat_o [11 : 8]), .EN (be_i [1]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_11 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [15 : 12]), .DO (wb_dat_o [15 : 12]), .EN (be_i [1]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_20 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [19 : 16]), .DO (wb_dat_o [19 : 16]), .EN (be_i [2]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_21 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [23 : 20]), .DO (wb_dat_o [23 : 20]), .EN (be_i [2]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_30 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [27 : 24]), .DO (wb_dat_o [27 : 24]), .EN (be_i [3]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_31 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [31 : 28]), .DO (wb_dat_o [31 : 28]), .EN (be_i [3]), .WE (we), .SSR (0)); endmodule
// A restricted 27x27 bit multiplier. (The restriction is that if the // MSB bit of opa is set the three LSB bits of opa must be zero as we // will otherwise get an overflow in the pre-adder portion of the DSP // blocks.) module mult_27x27 (input wire clk, input wire [26:0] opa, opb, output reg [53:0] res); parameter LATENCY = 0; // Unused so far... // FIXME - sanity check for LATENCY! wire [26:0] multop_a; wire [26:0] multop_b; assign multop_a = opa; assign multop_b = opb; // Implementation of 27x27 using a 24x35 bit multiplier together with some LUTS: // // res_tmp = op_a(op_b[26:3] + op_a[2]) 8 // // Note: The clever detail when using this module for HRFP_16 is // that we know that if op_b[2] is set, op_b[26] can never be set, // which ensures that we can never get an overflow in the addition // above which would overflow the multiplier in the DSP48E1 block! // (Thus the method below is not going to work in the general case // for a 27x27 bit multiplier.) // // case(op_b[2:0]) // 3'b000: foo = 0; // 3'b001: foo = op_a; // 3'b010: foo = op_a << 1; // 3'b011: foo = op_a + op_a << 1; // 3'b100: foo = op_a << 2; // Eller möjligtvis op_a << 1 + op_a << 1 // 3'b101: foo = op_a + op_a << 1; // 3'b110: foo = op_a << 1; // 3'b111: foo = op_a; // endcase // if(op_b[2]) begin // res = res_tmp - foo; // end else begin // res = res_tmp + foo; // end `define INSTANTIATED `ifdef INSTANTIATED wire [47:0] p_low, p_high; reg [47:0] p_low_delay; wire [47:0] pcout_low; reg [47:0] c_in; reg carryin; reg dosub, dosub1; always @(posedge clk) begin dosub1 <= multop_a[2]; dosub <= dosub1; end DSP48E1 #(.AREG(1), .ADREG(0), // Hopefully isn't needed... .BREG(1), .ALUMODEREG(1), .CARRYINREG(1), .CARRYINSELREG(1), .CREG(1), .DREG(1), .INMODEREG(1), .MREG(1), .OPMODEREG(1), .PREG(1), .A_INPUT("DIRECT"), .B_INPUT("DIRECT"), .USE_DPORT("TRUE"), .USE_MULT("MULTIPLY"), .USE_SIMD("ONE48")) low( // Outputs .ACOUT (), .BCOUT (), .CARRYCASCOUT (), .CARRYOUT (), .MULTSIGNOUT (), .OVERFLOW (), .P (p_low), .PATTERNBDETECT (), .PATTERNDETECT (), .PCOUT (pcout_low), .UNDERFLOW (), // Inputs .A ({6'h0, multop_a[26:3]}), .ACIN (), .ALUMODE ({3'b000, dosub1}), .B ({1'b0, multop_b[16:0]}), .BCIN (), .C (c_in), .CARRYCASCIN (), .CARRYIN (carryin), // For subtract... .CARRYINSEL (3'h0), .CEA1 (1'b1), .CEA2 (1'b1), .CEAD (1'b1), .CEALUMODE (1'b1), .CEB1 (1'b1), .CEB2 (1'b1), .CEC (1'b1), .CECARRYIN (1'b1), .CECTRL (1'b1), .CED (1'b1), .CEINMODE (1'b1), .CEM (1'b1), .CEP (1'b1), .CLK (clk), .D ({24'h0, multop_a[2]}), .INMODE (5'b00101), .MULTSIGNIN (1'b0), .OPMODE (7'b0110101), // P = AB + C (or minus C depending on ALUMODE above) .PCIN (48'b0), .RSTA (1'b0), .RSTALLCARRYIN (1'b0), .RSTALUMODE (1'b0), .RSTB (1'b0), .RSTC (1'b0), .RSTCTRL (1'b0), .RSTD (1'b0), .RSTINMODE (1'b0), .RSTM (1'b0), .RSTP (1'b0)); reg [28:0] multfix; reg [28:0] add1, add2; always @ begin case(multop_a[2:0]) 3'b000: begin add1 <= 0; add2 <= 0; end 3'b001: begin add1 <= multop_b; add2 <= 0; end 3'b010: begin add1 <= 0; add2 <= multop_b << 1; end 3'b011: begin add1 <= multop_b; add2 <= multop_b << 1; end 3'b100: begin add1 <= multop_b <<1; add2 <= multop_b << 1; end 3'b101: begin add1 <= multop_b; add2 <= multop_b << 1; end 3'b110: begin add1 <= 0; add2 <= multop_b << 1; end 3'b111: begin add1 <= multop_b; add2 <= 0; end endcase multfix = add1 + add2; end // Generate carry the carry input to the DSP48E1 based adder always @(posedge clk) begin c_in <= multfix >> 3; // Final three LSB bits are calculated below using a lookup table... if(multop_a[2] == 0) begin carryin <= 0; end else begin carryin <= 0; if(~multfix[2:0] == 3'b111) begin carryin <= 1; end end end reg [2:0] lsbresult1, lsbresult2, lsbresult3, lsbresult4; always @(posedge clk) begin lsbresult1 <= multop_a[2:0]multop_b[2:0]; lsbresult2 <= lsbresult1; lsbresult3 <= lsbresult2; lsbresult4 <= lsbresult3; p_low_delay <= p_low; end DSP48E1 #(.AREG(2), .ADREG(0), // Hopefully isn't needed... .BREG(2), .ALUMODEREG(1), .CARRYINREG(1), .CARRYINSELREG(1), .CREG(1), .DREG(1), .INMODEREG(1), .MREG(1), .OPMODEREG(1), .PREG(1), .A_INPUT("DIRECT"), .B_INPUT("DIRECT"), .USE_DPORT("TRUE"), .USE_MULT("MULTIPLY"), .USE_SIMD("ONE48")) high( // Outputs .ACOUT (), .BCOUT (), .CARRYCASCOUT (), .CARRYOUT (), .MULTSIGNOUT (), .OVERFLOW (), .P (p_high), .PATTERNBDETECT (), .PATTERNDETECT (), .PCOUT (), .UNDERFLOW (), // Inputs .A ({6'h0, multop_a[26:3]}), .ACIN (), .ALUMODE ({4'b0000}), .B ({8'b0, multop_b[26:17]}), .BCIN (), .C (48'h0), .CARRYCASCIN (), .CARRYIN (1'b0), .CARRYINSEL (3'h0), .CEA1 (1'b1), .CEA2 (1'b1), .CEAD (1'b1), .CEALUMODE (1'b1), .CEB1 (1'b1), .CEB2 (1'b1), .CEC (1'b1), .CECARRYIN (1'b1), .CECTRL (1'b1), .CED (1'b1), .CEINMODE (1'b1), .CEM (1'b1), .CEP (1'b1), .CLK (clk), .D ({24'h0, dosub1}), .INMODE (5'b00100), .MULTSIGNIN (1'b0), .OPMODE (7'b1010101), // P = AB + PCIN >> 17 .PCIN (pcout_low), .RSTA (1'b0), .RSTALLCARRYIN (1'b0), .RSTALUMODE (1'b0), .RSTB (1'b0), .RSTC (1'b0), .RSTCTRL (1'b0), .RSTD (1'b0), .RSTINMODE (1'b0), .RSTM (1'b0), .RSTP (1'b0)); always @* begin res = {p_high, p_low_delay[16:0], lsbresult4}; end `endif endmodule
module tx_buffer_inband ( //System input wire usbclk, input wire bus_reset, input wire reset, input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, //output transmit signals output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, output wire [15:0] tx_i_1, output wire [15:0] tx_q_1, output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, input wire txclk, input wire txstrobe, input wire WR, input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, //command reader io output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, input wire rx_WR_enabled, //register io output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr, input wire [31:0] reg_data_out, //input characteristic signals input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, output wire [1:0] tx_underrun, //system stop output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1); /* Debug paramters / parameter STROBE_RATE_0 = 8'd1 ; parameter STROBE_RATE_1 = 8'd2 ; parameter NUM_CHAN = 2 ; / To generate channel readers / genvar i ; / These will eventually be external register / reg [31:0] adc_time ; wire datapattern_err; wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; wire [31:0] rssi [3:0]; assign rssi[0] = rssi_0; assign rssi[1] = rssi_1; assign rssi[2] = rssi_2; assign rssi[3] = rssi_3; always @(posedge txclk) if (reset) adc_time <= 0; else if (txstrobe) adc_time <= adc_time + 1; / Connections between tx_usb_fifo_reader and cnannel/command processing blocks / wire [31:0] tx_data_bus ; wire [NUM_CHAN:0] chan_WR ; wire [NUM_CHAN:0] chan_done ; / Connections between data block and the FX2/TX chains / wire [NUM_CHAN:0] chan_underrun; wire [NUM_CHAN:0] chan_txempty; / Conections between tx_data_packet_fifo and its reader + strobe generator / wire [31:0] chan_fifodata [NUM_CHAN:0] ; wire chan_pkt_waiting [NUM_CHAN:0] ; wire chan_rdreq [NUM_CHAN:0] ; wire chan_skip [NUM_CHAN:0] ; wire chan_have_space [NUM_CHAN:0] ; wire chan_txstrobe [NUM_CHAN-1:0] ; wire [14:0] debug [NUM_CHAN:0]; / Outputs to transmit chains / wire [15:0] tx_i [NUM_CHAN-1:0] ; wire [15:0] tx_q [NUM_CHAN-1:0] ; / TODO: Figure out how to write this genericly / assign have_space = chan_have_space[0];// & chan_have_space[1]; assign tx_empty = chan_txempty[0];// & chan_txempty[1] ; assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; assign datapattern_err = ((tx_i_0 != 16'h0000) \|\| (tx_q_0 != 16'hffff)) && !tx_empty; assign test_bit0 = datapattern_err; / Debug statement */ assign txstrobe_rate[0] = STROBE_RATE_0 ; assign txstrobe_rate[1] = STROBE_RATE_1 ; assign tx_q_2 = 16'b0 ; assign tx_i_2 = 16'b0 ; assign tx_q_3 = 16'b0 ; assign tx_i_3 = 16'b0 ; assign tx_i_3 = 16'b0 ; wire [31:0] usbdata_final; wire WR_final; assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, chan_pkt_waiting[0], chan_pkt_waiting[1], chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]}; tx_packer tx_usb_packer (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR), .usbdata(usbdata), .reset(reset), .txclk(txclk), .usbdata_final(usbdata_final), .WR_final(WR_final), .test_bit0(), .test_bit1(test_bit1)); channel_demux channel_demuxer (.usbdata_final(usbdata_final), .WR_final(WR_final), .reset(reset), .txclk(txclk), .WR_channel(chan_WR), .WR_done_channel(chan_done), .ram_data(tx_data_bus)); generate for (i = 0 ; i < NUM_CHAN; i = i + 1) begin : generate_channel_readers assign tx_underrun[i] = chan_underrun[i]; channel_ram tx_data_packet_fifo (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[i]), .WR_done(chan_done[i]), .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]), .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]), .RD_done(chan_skip[i])); chan_fifo_reader tx_chan_reader (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe), .adc_time(adc_time), .samples_format(4'b0), .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]), .skip(chan_skip[i]), .rdreq(chan_rdreq[i]), .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]), .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]), .threshhold(threshhold), .rssi_wait(rssi_wait)); end endgenerate channel_ram tx_cmd_packet_fifo (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]), .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]), .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]), .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN])); cmd_reader tx_cmd_reader (.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]), .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]), .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus), .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr), .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time)); endmodule // tx_buffer
// -- verilog -- // Copyright (c) 2012 Ben Reynwar // Released under MIT License (see LICENSE.txt) module message_slicer #( parameter N_SLICES = 2, parameter WIDTH = 32, parameter BUFFER_LENGTH = 32 ) ( input clk, input rst_n, input wire [WIDTHN_SLICES-1:0] in_data, input wire in_nd, output reg [WIDTH-1:0] out_data, output reg out_nd, output wire error ); function integer clog2; input integer value; begin value = value-1; for (clog2=0; value>0; clog2=clog2+1) value = value>>1; end endfunction localparam integer LOG_N_SLICES = clog2(N_SLICES); reg read_delete; wire [N_SLICESWIDTH-1:0] read_data; wire read_full; buffer_BB #(N_SLICESWIDTH, BUFFER_LENGTH) buffer_0 (.clk(clk), .rst_n(rst_n), .write_strobe(in_nd), .write_data(in_data), .read_delete(read_delete), .read_full(read_full), .read_data(read_data), .error(error) ); reg [LOG_N_SLICES-1:0] pos; wire [WIDTH-1:0] sliced_data[N_SLICES-1:0]; genvar i; generate for(i=0; i<N_SLICES; i=i+1) begin: loop_0 assign sliced_data[i] = read_data[WIDTH(i+1)-1 -:WIDTH]; end endgenerate // Send out data from the buffer. always @ (posedge clk) begin out_nd <= 1'b0; read_delete <= 1'b0; if (!rst_n) begin pos <= N_SLICES-1; end else if (read_full) begin out_nd <= 1'b1; out_data <= sliced_data[pos]; if (pos == 0) begin pos <= N_SLICES-1; read_delete <= 1'b1; end else pos <= pos - 1; end end endmodule
//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_app_7x.v // Version : 1.11 //-- //-- Description: PCI Express Endpoint sample application //-- design. //-- //------------------------------------------------------------------------------ `timescale 1ps / 1ps `define PCI_EXP_EP_OUI 24'h000A35 `define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI} `define PCI_EXP_EP_DSN_2 32'h00000001 module pcie_app_7x#( parameter C_DATA_WIDTH = 64, // RX/TX interface data width // Do not override parameters below this line parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width parameter TCQ = 1 )( input user_clk, input user_reset, input user_lnk_up, // Tx //input [5:0] tx_buf_av, //input tx_cfg_req, //input tx_err_drop, output tx_cfg_gnt, input s_axis_tx_tready, output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, output [3:0] s_axis_tx_tuser, output s_axis_tx_tlast, output s_axis_tx_tvalid, // Rx output rx_np_ok, output rx_np_req, input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, input m_axis_rx_tlast, input m_axis_rx_tvalid, output m_axis_rx_tready, input [21:0] m_axis_rx_tuser, // Flow Control //input [11:0] fc_cpld, //input [7:0] fc_cplh, //input [11:0] fc_npd, //input [7:0] fc_nph, //input [11:0] fc_pd, //input [7:0] fc_ph, output [2:0] fc_sel, // CFG output cfg_err_cor, output cfg_err_ur, output cfg_err_ecrc, output cfg_err_cpl_timeout, output cfg_err_cpl_unexpect, output cfg_err_cpl_abort, output cfg_err_atomic_egress_blocked, output cfg_err_internal_cor, output cfg_err_malformed, output cfg_err_mc_blocked, output cfg_err_poisoned, output cfg_err_norecovery, output cfg_err_acs, output cfg_err_internal_uncor, output cfg_pm_halt_aspm_l0s, output cfg_pm_halt_aspm_l1, output cfg_pm_force_state_en, output [1:0] cfg_pm_force_state, output cfg_err_posted, output cfg_err_locked, output [47:0] cfg_err_tlp_cpl_header, // input cfg_err_cpl_rdy, output cfg_interrupt, // input cfg_interrupt_rdy, output cfg_interrupt_assert, output [7:0] cfg_interrupt_di, // input [7:0] cfg_interrupt_do, // input [2:0] cfg_interrupt_mmenable, // input cfg_interrupt_msienable, // input cfg_interrupt_msixenable, // input cfg_interrupt_msixfm, output cfg_turnoff_ok, input cfg_to_turnoff, output cfg_trn_pending, output cfg_pm_wake, input [7:0] cfg_bus_number, input [4:0] cfg_device_number, input [2:0] cfg_function_number, // input [15:0] cfg_status, // input [15:0] cfg_command, // input [15:0] cfg_dstatus, // input [15:0] cfg_dcommand, // input [15:0] cfg_lstatus, // input [15:0] cfg_lcommand, // input [15:0] cfg_dcommand2, // input [2:0] cfg_pcie_link_state, output cfg_interrupt_stat, output [4:0] cfg_pciecap_interrupt_msgnum, output [1:0] pl_directed_link_change, // input [5:0] pl_ltssm_state, output [1:0] pl_directed_link_width, output pl_directed_link_speed, output pl_directed_link_auton, output pl_upstream_prefer_deemph, // input [1:0] pl_sel_lnk_width, // input pl_sel_lnk_rate, // input pl_link_gen2_cap, // input pl_link_partner_gen2_supported, // input [2:0] pl_initial_link_width, // input pl_link_upcfg_cap, // input [1:0] pl_lane_reversal_mode, // input pl_received_hot_rst, output [127:0] cfg_err_aer_headerlog, output [4:0] cfg_aer_interrupt_msgnum, // input cfg_err_aer_headerlog_set, // input cfg_aer_ecrc_check_en, // input cfg_aer_ecrc_gen_en, output [31:0] cfg_mgmt_di, output [3:0] cfg_mgmt_byte_en, output [9:0] cfg_mgmt_dwaddr, output cfg_mgmt_wr_en, output cfg_mgmt_rd_en, output cfg_mgmt_wr_readonly, output [63:0] cfg_dsn ); //----------------------------------------------------------------------------------------------------------------// // PCIe Block EP Tieoffs - Example PIO doesn't support the following inputs // //----------------------------------------------------------------------------------------------------------------// assign fc_sel = 3'b0; assign rx_np_ok = 1'b1; // Allow Reception of Non-posted Traffic assign rx_np_req = 1'b1; // Always request Non-posted Traffic if available assign s_axis_tx_tuser[0] = 1'b0; // Unused for V6 assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet assign s_axis_tx_tuser[2] = 1'b0; // Stream packet assign tx_cfg_gnt = 1'b1; // Always allow transmission of Config traffic within block assign cfg_err_cor = 1'b0; // Never report Correctable Error assign cfg_err_ur = 1'b0; // Never report UR assign cfg_err_ecrc = 1'b0; // Never report ECRC Error assign cfg_err_cpl_timeout = 1'b0; // Never report Completion Timeout assign cfg_err_cpl_abort = 1'b0; // Never report Completion Abort assign cfg_err_cpl_unexpect = 1'b0; // Never report unexpected completion assign cfg_err_posted = 1'b0; // Never qualify cfg_err_* inputs assign cfg_err_locked = 1'b0; // Never qualify cfg_err_ur or cfg_err_cpl_abort assign cfg_pm_wake = 1'b0; // Never direct the core to send a PM_PME Message assign cfg_trn_pending = 1'b0; // Never set the transaction pending bit in the Device Status Register assign cfg_err_atomic_egress_blocked = 1'b0; // Never report Atomic TLP blocked assign cfg_err_internal_cor = 1'b0; // Never report internal error occurred assign cfg_err_malformed = 1'b0; // Never report malformed error assign cfg_err_mc_blocked = 1'b0; // Never report multi-cast TLP blocked assign cfg_err_poisoned = 1'b0; // Never report poisoned TLP received assign cfg_err_norecovery = 1'b0; // Never qualify cfg_err_poisoned or cfg_err_cpl_timeout assign cfg_err_acs = 1'b0; // Never report an ACS violation assign cfg_err_internal_uncor = 1'b0; // Never report internal uncorrectable error assign cfg_pm_halt_aspm_l0s = 1'b0; // Allow entry into L0s assign cfg_pm_halt_aspm_l1 = 1'b0; // Allow entry into L1 assign cfg_pm_force_state_en = 1'b0; // Do not qualify cfg_pm_force_state assign cfg_pm_force_state = 2'b00; // Do not move force core into specific PM state assign cfg_err_aer_headerlog = 128'h0; // Zero out the AER Header Log assign cfg_aer_interrupt_msgnum = 5'b00000; // Zero out the AER Root Error Status Register assign cfg_interrupt_stat = 1'b0; // Never set the Interrupt Status bit assign cfg_pciecap_interrupt_msgnum = 5'b00000; // Zero out Interrupt Message Number assign cfg_interrupt_assert = 1'b0; // Always drive interrupt de-assert assign cfg_interrupt = 1'b0; // Never drive interrupt by qualifying cfg_interrupt_assert assign pl_directed_link_change = 2'b00; // Never initiate link change assign pl_directed_link_width = 2'b00; // Zero out directed link width assign pl_directed_link_speed = 1'b0; // Zero out directed link speed assign pl_directed_link_auton = 1'b0; // Zero out link autonomous input assign pl_upstream_prefer_deemph = 1'b1; // Zero out preferred de-emphasis of upstream port assign cfg_interrupt_di = 8'b0; // Do not set interrupt fields assign cfg_err_tlp_cpl_header = 48'h0; // Zero out the header information assign cfg_mgmt_di = 32'h0; // Zero out CFG MGMT input data bus assign cfg_mgmt_byte_en = 4'h0; // Zero out CFG MGMT byte enables assign cfg_mgmt_dwaddr = 10'h0; // Zero out CFG MGMT 10-bit address port assign cfg_mgmt_wr_en = 1'b0; // Do not write CFG space assign cfg_mgmt_rd_en = 1'b0; // Do not read CFG space assign cfg_mgmt_wr_readonly = 1'b0; // Never treat RO bit as RW assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1}; // Assign the input DSN //----------------------------------------------------------------------------------------------------------------// // Programmable I/O Module // //----------------------------------------------------------------------------------------------------------------// wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number }; // wire cfg_bus_mstr_enable = cfg_command[2]; reg s_axis_tx_tready_i ; always @(posedge user_clk) begin if (user_reset) s_axis_tx_tready_i <= #TCQ 1'b0; else s_axis_tx_tready_i <= #TCQ s_axis_tx_tready; end //----------------------------------------------------------------------------------------------------------------// PIO #( .C_DATA_WIDTH( C_DATA_WIDTH ), .KEEP_WIDTH( KEEP_WIDTH ), .TCQ( TCQ ) ) PIO ( .user_clk ( user_clk ), // I .user_reset ( user_reset ), // I .user_lnk_up ( user_lnk_up ), // I .s_axis_tx_tready ( s_axis_tx_tready_i ), // I .s_axis_tx_tdata ( s_axis_tx_tdata ), // O .s_axis_tx_tkeep ( s_axis_tx_tkeep ), // O .s_axis_tx_tlast ( s_axis_tx_tlast ), // O .s_axis_tx_tvalid ( s_axis_tx_tvalid ), // O .tx_src_dsc ( s_axis_tx_tuser[3] ), // O .m_axis_rx_tdata( m_axis_rx_tdata ), // I .m_axis_rx_tkeep( m_axis_rx_tkeep ), // I .m_axis_rx_tlast( m_axis_rx_tlast ), // I .m_axis_rx_tvalid( m_axis_rx_tvalid ), // I .m_axis_rx_tready( m_axis_rx_tready ), // O .m_axis_rx_tuser ( m_axis_rx_tuser ), // I .cfg_to_turnoff ( cfg_to_turnoff ), // I .cfg_turnoff_ok ( cfg_turnoff_ok ), // O .cfg_completer_id ( cfg_completer_id ) // I [15:0] ); endmodule // pcie_app
//////////////////////////////////////////////////////////////////////////////// // Original Author: Schuyler Eldridge // Contact Point: Schuyler Eldridge ([email protected]) // div_pipelined.v // Created: 4.3.2012 // Modified: 4.5.2012 // // Testbench for div_pipelined.v // // Copyright (C) 2012 Schuyler Eldridge, Boston University // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. //////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module t_div_pipelined(); reg clk, start, reset_n; reg [7:0] dividend, divisor; wire data_valid, div_by_zero; wire [7:0] quotient, quotient_correct; parameter BITS = 8; div_pipelined #( .BITS(BITS) ) div_pipelined ( .clk(clk), .reset_n(reset_n), .dividend(dividend), .divisor(divisor), .quotient(quotient), .div_by_zero(div_by_zero), // .quotient_correct(quotient_correct), .start(start), .data_valid(data_valid) ); initial begin #10 reset_n = 0; #50 reset_n = 1; #1 clk = 0; dividend = -1; divisor = 127; #1000 $finish; end // always // #20 dividend = dividend + 1; always begin #10 divisor = divisor - 1; start = 1; #10 start = 0; end always #5 clk = ~clk; endmodule
// Taken from http://www.europa.com/~celiac/fsm_samp.html // These are the symbolic names for states parameter [1:0] //synopsys enum state_info S0 = 2'h0, S1 = 2'h1, S2 = 2'h2, S3 = 2'h3; // These are the current state and next state variables reg [1:0] /* synopsys enum state_info / state; reg [1:0] / synopsys enum state_info */ next_state; // synopsys state_vector state always @ (state or y or x) begin next_state = state; case (state) // synopsys full_case parallel_case S0: begin if (x) begin next_state = S1; end else begin next_state = S2; end end S1: begin if (y) begin next_state = S2; end else begin next_state = S0; end end S2: begin if (x & y) begin next_state = S3; end else begin next_state = S0; end end S3: begin next_state = S0; end endcase end always @ (posedge clk or posedge reset) begin if (reset) begin state <= S0; end else begin state <= next_state; end end
/------------------------------------------------------------------------------ This code was generated by Spiral Multiplier Block Generator, www.spiral.net * Copyright (c) 2006, Carnegie Mellon University * All rights reserved. * The code is distributed under a BSD style license * (see http://www.opensource.org/licenses/bsd-license.php) ------------------------------------------------------------------------------ / /* ./multBlockGen.pl 16657 -fractionalBits 0*/ module multiplier_block ( i_data0, o_data0 ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; //Multipliers: wire [31:0] w1, w16384, w16385, w256, w16641, w16, w16657; assign w1 = i_data0; assign w16 = w1 << 4; assign w16384 = w1 << 14; assign w16385 = w1 + w16384; assign w16641 = w16385 + w256; assign w16657 = w16641 + w16; assign w256 = w1 << 8; assign o_data0 = w16657; //multiplier_block area estimate = 4770.05771526471; endmodule //multiplier_block module surround_with_regs( i_data0, o_data0, clk ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; reg [31:0] o_data0; input clk; reg [31:0] i_data0_reg; wire [30:0] o_data0_from_mult; always @(posedge clk) begin i_data0_reg <= i_data0; o_data0 <= o_data0_from_mult; end multiplier_block mult_blk( .i_data0(i_data0_reg), .o_data0(o_data0_from_mult) ); endmodule
// file: main_pll.v // // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //---------------------------------------------------------------------------- // User entered comments //---------------------------------------------------------------------------- // None // //---------------------------------------------------------------------------- // "Output Output Phase Duty Pk-to-Pk Phase" // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" //---------------------------------------------------------------------------- // CLK_OUT1____75.000______0.000______50.0______466.667_____50.000 // //---------------------------------------------------------------------------- // "Input Clock Freq (MHz) Input Jitter (UI)" //---------------------------------------------------------------------------- // __primary_________100.000____________0.010 `timescale 1ps/1ps (* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" ) module main_pll (// Clock in ports input CLK_IN1, // Clock out ports output CLK_OUT1 ); // Input buffering //------------------------------------ IBUFG clkin1_buf (.O (clkin1), .I (CLK_IN1)); // Clocking primitive //------------------------------------ // Instantiation of the DCM primitive // Unused inputs are tied off // * Unused outputs are labeled unused wire psdone_unused; wire locked_int; wire [7:0] status_int; wire clkfb; wire clk0; wire clkfx; DCM_SP #(.CLKDV_DIVIDE (2.000), .CLKFX_DIVIDE (10), .CLKFX_MULTIPLY (15), .CLKIN_DIVIDE_BY_2 ("FALSE"), .CLKIN_PERIOD (10.0), .CLKOUT_PHASE_SHIFT ("NONE"), .CLK_FEEDBACK ("NONE"), .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), .PHASE_SHIFT (0), .STARTUP_WAIT ("FALSE")) dcm_sp_inst // Input clock (.CLKIN (clkin1), .CLKFB (clkfb), // Output clocks .CLK0 (clk0), .CLK90 (), .CLK180 (), .CLK270 (), .CLK2X (), .CLK2X180 (), .CLKFX (clkfx), .CLKFX180 (), .CLKDV (), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (locked_int), .STATUS (status_int), .RST (1'b0), // Unused pin- tie low .DSSEN (1'b0)); // Output buffering //----------------------------------- // no phase alignment active, connect to ground assign clkfb = 1'b0; BUFG clkout1_buf (.O (CLK_OUT1), .I (clkfx)); endmodule
// (C) 2001-2014 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/14.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2014/10/06 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 \|\| (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) \| out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule
//*************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //************************************************************************* // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_mux.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //*************************************************************************** `timescale 1ps/1ps module mig_7series_v1_9_arb_mux # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_VECT_INDX = 11, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_VECT_INDX = 31, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs parameter nCS_PER_RANK = 1, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nSLOTS = 2, parameter nWR = 6, // Write recovery (CKs) parameter RANKS = 1, parameter RANK_VECT_INDX = 15, parameter RANK_WIDTH = 2, parameter ROW_VECT_INDX = 63, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010 ) (/AUTOARG/ // Outputs output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v output col_periodic_rd, // From arb_select0 of arb_select.v output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v output col_rmw, // From arb_select0 of arb_select.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v output col_size, // From arb_select0 of arb_select.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLKROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLKBANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTHnCS_PER_RANKnCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_pre, output sent_col, // From arb_row_col0 of arb_row_col.v output sent_col_r, // From arb_row_col0 of arb_row_col.v output sent_row, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_col, output rnk_config_strobe, output insert_maint_r1, output rnk_config_kill_rts_col, // Inputs input clk, input rst, input init_calib_complete, input [6RANKS-1:0] calib_rddata_offset, input [6RANKS-1:0] calib_rddata_offset_1, input [6RANKS-1:0] calib_rddata_offset_2, input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v input insert_maint_r, // To arb_row_col0 of arb_row_col.v input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v input maint_zq_r, // To arb_select0 of arb_select.v input maint_sre_r, // To arb_select0 of arb_select.v input maint_srx_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v input [7:0] slot_0_present, // To arb_select0 of arb_select.v input [7:0] slot_1_present // To arb_select0 of arb_select.v ); /AUTOINPUT/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /AUTOOUTPUT/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /AUTOWIRE/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire cs_en0; // From arb_row_col0 of arb_row_col.v wire cs_en1; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v wire send_cmd1_col; wire send_cmd2_row; wire send_cmd2_col; wire send_cmd2_pre; wire send_cmd3_col; wire [5:0] col_channel_offset; // End of automatics wire sent_col_i; assign sent_col = sent_col_i; mig_7series_v1_9_arb_row_col # (/AUTOINSTPARAM/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .CWL (CWL), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nRAS (nRAS), .nRCD (nRCD), .nWR (nWR)) arb_row_col0 (/AUTOINST/ // Outputs .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), .sent_row (sent_row), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col_i), .sent_col_r (sent_col_r), .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), .send_cmd0_row (send_cmd0_row), .send_cmd0_col (send_cmd0_col), .send_cmd1_row (send_cmd1_row), .send_cmd1_col (send_cmd1_col), .send_cmd2_row (send_cmd2_row), .send_cmd2_col (send_cmd2_col), .send_cmd2_pre (send_cmd2_pre), .send_cmd3_col (send_cmd3_col), .col_channel_offset (col_channel_offset), .cs_en0 (cs_en0), .cs_en1 (cs_en1), .cs_en2 (cs_en2), .cs_en3 (cs_en3), .insert_maint_r1 (insert_maint_r1), // Inputs .clk (clk), .rst (rst), .rts_row (rts_row[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .rts_col (rts_col[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0])); mig_7series_v1_9_arb_select # (/AUTOINSTPARAM/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .CKE_ODT_AUX (CKE_ODT_AUX), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nSLOTS (nSLOTS), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_select0 (/AUTOINST*/ // Outputs .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_size (col_size), .col_row (col_row[ROW_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .mc_cas_slot (mc_cas_slot), .col_channel_offset (col_channel_offset), .rnk_config (rnk_config), // Inputs .clk (clk), .rst (rst), .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .insert_maint_r1 (insert_maint_r1), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .col_addr (col_addr[ROW_VECT_INDX:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), .send_cmd0_row (send_cmd0_row), .send_cmd0_col (send_cmd0_col), .send_cmd1_row (send_cmd1_row), .send_cmd1_col (send_cmd1_col), .send_cmd2_row (send_cmd2_row), .send_cmd2_col (send_cmd2_col), .send_cmd2_pre (send_cmd2_pre), .send_cmd3_col (send_cmd3_col), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col), .cs_en0 (cs_en0), .cs_en1 (cs_en1), .cs_en2 (cs_en2), .cs_en3 (cs_en3), .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); endmodule
// ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH // DAMAGE. // ---------------------------------------------------------------------- // // Filename: tx_engine_classic.v // Version: 1.0 // Verilog Standard: Verilog-2001 // Description: The TX Engine takes unformatted request and completions, // formats these packets into "TLP's" or Transaction Layer Packets and abitrates // their sending over the PCIe bus. These packets must meet max-request, // max-payload, and payload termination requirements (see Read Completion // Boundary). The TX Engine does not check these requirements during operation, // but may do so during simulation. // // Valid packets are transmitted over the shared PCIe bus as determined // by the arbiter. // // This Engine is capable of operating at "line rate". // Author: Dustin Richmond (@darichmond) //----------------------------------------------------------------------------- `include "trellis.vh" `include "tlp.vh" module tx_engine_classic #(parameter C_PCI_DATA_WIDTH = 128, parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_OUTPUT = 1, parameter C_MAX_PAYLOAD_DWORDS = 256, parameter C_VENDOR = "ALTERA") (// Interface: Clocks input CLK, // Interface: Resets input RST_BUS, // Replacement for generic RST_IN input RST_LOGIC, // Addition for RIFFA_RST output DONE_TXC_RST, output DONE_TXR_RST, // Interface: Configuration input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, // Interface: TX Classic input TX_TLP_READY, output [C_PCI_DATA_WIDTH-1:0] TX_TLP, output TX_TLP_VALID, output TX_TLP_START_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET, output TX_TLP_END_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET, // Interface: TXC Engine input TXC_DATA_VALID, input [C_PCI_DATA_WIDTH-1:0] TXC_DATA, input TXC_DATA_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET, input TXC_DATA_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET, output TXC_DATA_READY, input TXC_META_VALID, input [`SIG_FBE_W-1:0] TXC_META_FDWBE, input [`SIG_LBE_W-1:0] TXC_META_LDWBE, input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR, input [`SIG_TYPE_W-1:0] TXC_META_TYPE, input [`SIG_LEN_W-1:0] TXC_META_LENGTH, input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT, input [`SIG_TAG_W-1:0] TXC_META_TAG, input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID, input [`SIG_TC_W-1:0] TXC_META_TC, input [`SIG_ATTR_W-1:0] TXC_META_ATTR, input TXC_META_EP, output TXC_META_READY, output TXC_SENT, // Interface: TXR Engine input TXR_DATA_VALID, input [C_PCI_DATA_WIDTH-1:0] TXR_DATA, input TXR_DATA_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET, input TXR_DATA_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET, output TXR_DATA_READY, input TXR_META_VALID, input [`SIG_FBE_W-1:0] TXR_META_FDWBE, input [`SIG_LBE_W-1:0] TXR_META_LDWBE, input [`SIG_ADDR_W-1:0] TXR_META_ADDR, input [`SIG_LEN_W-1:0] TXR_META_LENGTH, input [`SIG_TAG_W-1:0] TXR_META_TAG, input [`SIG_TC_W-1:0] TXR_META_TC, input [`SIG_ATTR_W-1:0] TXR_META_ATTR, input [`SIG_TYPE_W-1:0] TXR_META_TYPE, input TXR_META_EP, output TXR_META_READY, output TXR_SENT); localparam C_MUX_TYPE = "SHIFT"; localparam C_DEPTH_PACKETS = 10; localparam C_RST_COUNT = 10; /AUTOWIRE/ /AUTOINPUT/ wire [C_PCI_DATA_WIDTH-1:0] _TXC_DATA; wire [C_PCI_DATA_WIDTH-1:0] _TXR_DATA; wire [C_PCI_DATA_WIDTH-1:0] wTxcTlp; wire wTxcTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpEndOffset; wire wTxcTlpReady; wire wTxcTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpStartOffset; wire wTxcTlpValid; wire [C_PCI_DATA_WIDTH-1:0] wTxrTlp; wire wTxrTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpEndOffset; wire wTxrTlpReady; wire wTxrTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpStartOffset; wire wTxrTlpValid; wire [C_PCI_DATA_WIDTH-1:0] wTxTlp; wire wTxTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpEndOffset; wire wTxTlpReady; wire wTxTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpStartOffset; wire wTxTlpValid; wire wDoneTxcEngRst; wire wDoneTxrEngRst; wire wDoneRst; wire wRstWaiting; wire wRstRc; wire wRstEng; wire [C_RST_COUNT:0] wShiftRst; reg rTxValid; reg [`TLP_TYPE_W-1:0] rTxType; reg rTxEndFlag; reg rTxrSent; reg rTxcSent; assign DONE_TXC_RST = wDoneRst & wDoneTxcEngRst; assign DONE_TXR_RST = wDoneRst & wDoneTxrEngRst; assign TXC_SENT = rTxcSent; assign TXR_SENT = rTxrSent; assign wRstEng = wShiftRst[C_RST_COUNT-3]; assign wDoneEngRst = ~wShiftRst[C_RST_COUNT]; always @(posedge CLK) begin if(TX_TLP_START_FLAG) begin rTxType <= TX_TLP[`TLP_TYPE_R]; end rTxEndFlag <= TX_TLP_END_FLAG; rTxValid <= TX_TLP_VALID & TX_TLP_READY; rTxcSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_CPL); rTxrSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_REQ); end generate if(C_VENDOR == "XILINX") begin : xilinx_data if(C_PCI_DATA_WIDTH == 128) begin : x_be_swap128 assign _TXC_DATA = {TXC_DATA[103:96], TXC_DATA[111:104], TXC_DATA[119:112], TXC_DATA[127:120], TXC_DATA[71:64], TXC_DATA[79:72], TXC_DATA[87:80], TXC_DATA[95:88], TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56], TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]}; assign _TXR_DATA = {TXR_DATA[103:96], TXR_DATA[111:104], TXR_DATA[119:112], TXR_DATA[127:120], TXR_DATA[71:64], TXR_DATA[79:72], TXR_DATA[87:80], TXR_DATA[95:88], TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56], TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]}; end else if(C_PCI_DATA_WIDTH == 64) begin: x_be_swap64 assign _TXC_DATA = {TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56], TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]}; assign _TXR_DATA = {TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56], TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]}; end else if(C_PCI_DATA_WIDTH == 32) begin: x_be_swap32 assign _TXC_DATA = {TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]}; assign _TXR_DATA = {TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]}; end end else begin : altera_data assign _TXC_DATA = TXC_DATA; assign _TXR_DATA = TXR_DATA; end endgenerate txc_engine_classic #(.C_PIPELINE_OUTPUT (0), /AUTOINSTPARAM/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_INPUT (C_PIPELINE_INPUT), .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS), .C_DEPTH_PACKETS (C_DEPTH_PACKETS), .C_VENDOR (C_VENDOR)) txc_engine_inst (// Outputs .TXC_TLP (wTxcTlp[C_PCI_DATA_WIDTH-1:0] ), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_START_OFFSET (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXC_TLP_END_OFFSET (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .DONE_TXC_RST (wDoneTxcEngRst), // Inputs .TXC_TLP_READY (wTxcTlpReady), .TXC_DATA (_TXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RST_IN (wRstEng), /AUTOINST/ // Outputs .TXC_DATA_READY (TXC_DATA_READY), .TXC_META_READY (TXC_META_READY), // Inputs .CLK (CLK), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA_START_FLAG (TXC_DATA_START_FLAG), .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (TXC_DATA_END_FLAG), .TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (TXC_META_VALID), .TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]), .TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]), .TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]), .TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]), .TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]), .TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]), .TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]), .TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]), .TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]), .TXC_META_EP (TXC_META_EP)); txr_engine_classic #(.C_PIPELINE_OUTPUT (0), /AUTOINSTPARAM/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_INPUT (C_PIPELINE_INPUT), .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS), .C_DEPTH_PACKETS (C_DEPTH_PACKETS), .C_VENDOR (C_VENDOR)) txr_engine_inst (// Outputs .TXR_TLP (wTxrTlp[C_PCI_DATA_WIDTH-1:0]), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_START_OFFSET (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), .TXR_TLP_END_OFFSET (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA (_TXR_DATA[C_PCI_DATA_WIDTH-1:0]), .DONE_TXR_RST (wDoneTxrEngRst), // Inputs .TXR_TLP_READY (wTxrTlpReady), .RST_IN (wRstEng), /AUTOINST/ // Outputs .TXR_DATA_READY (TXR_DATA_READY), .TXR_META_READY (TXR_META_READY), // Inputs .CLK (CLK), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .TXR_DATA_VALID (TXR_DATA_VALID), .TXR_DATA_START_FLAG (TXR_DATA_START_FLAG), .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (TXR_DATA_END_FLAG), .TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (TXR_META_VALID), .TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]), .TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]), .TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]), .TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]), .TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]), .TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]), .TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]), .TXR_META_EP (TXR_META_EP)); tx_mux #(.C_PIPELINE_INPUT (0), /AUTOINSTPARAM/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT), .C_MUX_TYPE (C_MUX_TYPE), .C_VENDOR (C_VENDOR)) tx_mux_inst (// Inputs .TXC_TLP (wTxcTlp[C_PCI_DATA_WIDTH-1:0]), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_START_OFFSET (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXC_TLP_END_OFFSET (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_TLP (wTxrTlp[C_PCI_DATA_WIDTH-1:0]), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_START_OFFSET (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), .TXR_TLP_END_OFFSET (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RST_IN (wRstEng), // Outputs .TXC_TLP_READY (wTxcTlpReady), .TXR_TLP_READY (wTxrTlpReady), .TX_TLP (wTxTlp[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (wTxTlpValid), .TX_TLP_START_FLAG (wTxTlpStartFlag), .TX_TLP_START_OFFSET (wTxTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (wTxTlpEndFlag), .TX_TLP_END_OFFSET (wTxTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_READY (wTxTlpReady), /AUTOINST/ // Inputs .CLK (CLK)); shiftreg #(// Parameters .C_DEPTH (C_RST_COUNT), .C_WIDTH (1), .C_VALUE (1) /AUTOINSTPARAM/) rst_shiftreg (// Outputs .RD_DATA (wShiftRst), // Inputs .RST_IN (RST_BUS), .WR_DATA (wRstRc), /AUTOINST/ // Inputs .CLK (CLK)); reset_controller #(// Parameters .C_RST_COUNT (C_RST_COUNT) /AUTOINSTPARAM/) rc_inst (// Outputs .DONE_RST (wDoneRst), .WAITING_RESET (wRstWaiting), .RST_OUT (wRstRc), // Inputs .RST_IN (RST_BUS), .SIGNAL_RST (RST_LOGIC), .WAIT_RST (TX_TLP_VALID), .NEXT_CYC_RST (TX_TLP_END_FLAG & TX_TLP_READY), /AUTOINST/ // Inputs .CLK (CLK)); pipeline #(// Parameters .C_DEPTH (1), .C_WIDTH (C_PCI_DATA_WIDTH + 2(1 + clog2s(C_PCI_DATA_WIDTH/32))), .C_USE_MEMORY (0) /AUTOINSTPARAM/) output_reg_inst (// Outputs .WR_DATA_READY (wTxTlpReady), .RD_DATA ({TX_TLP, TX_TLP_START_FLAG, TX_TLP_START_OFFSET, TX_TLP_END_FLAG, TX_TLP_END_OFFSET}), .RD_DATA_VALID (TX_TLP_VALID), // Inputs .RST_IN (wRstRc), .WR_DATA ({wTxTlp, wTxTlpStartFlag, wTxTlpStartOffset, wTxTlpEndFlag, wTxTlpEndOffset}), .WR_DATA_VALID (wTxTlpValid & ~wRstWaiting), .RD_DATA_READY (TX_TLP_READY), /AUTOINST/ // Inputs .CLK (CLK)); // Put output pipeline stage here, OR, at TX Engine outputs endmodule // Local Variables: // verilog-library-directories:("." "../../common/") // End: / Filename: tx_mux.v Version: 1.0 Verilog Standard: Verilog-2001 Description: The tx_mux arbitrates access to the PCI TX interface between the the Request and Completion engines. The top level tx_mux module instantiates two sub-modules (also declared in this file): tx_arbiter and tx_phi. The arbiter choses the next packet that will be granted the TX interface, based on the priorities given to it. Each priority is the count of how many successive, back-to-back packets can be sent by either the TXC or TXR interface before granting time to the other engine. The mux is a simple multiplexer that uses the select signals from the arbiter. Notes: Any modifications to this file should meet the conditions set forth in the "Trellis Style Guide" - The pipeline stage at the start of the mux means that ready stays high for both TXC and TXR. This the behavior we want? Author: Dustin Richmond (@darichmond) Co-Authors: / `timescale 1ns/1ns `include "trellis.vh" module tx_mux #(parameter C_PCI_DATA_WIDTH = 128, parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_OUTPUT = 1, parameter C_MUX_TYPE = "SHIFT", parameter C_VENDOR = "ALTERA") (// Interface: Clocks input CLK, // Interface: Resets input RST_IN, // Interface: TXC input [C_PCI_DATA_WIDTH-1:0] TXC_TLP, output TXC_TLP_READY, input TXC_TLP_VALID, input TXC_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET, input TXC_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET, // Interface: TXR input [C_PCI_DATA_WIDTH-1:0] TXR_TLP, input TXR_TLP_VALID, input TXR_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET, input TXR_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET, output TXR_TLP_READY, // Interface: TX Classic input TX_TLP_READY, output [C_PCI_DATA_WIDTH-1:0] TX_TLP, output TX_TLP_VALID, output TX_TLP_START_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET, output TX_TLP_END_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET); localparam C_WIDTH = (C_PCI_DATA_WIDTH + 2 (clog2s(C_PCI_DATA_WIDTH/32) + 1)); localparam C_TXC_PRIORITY = 1; localparam C_TXR_PRIORITY = 2; /AUTOWIRE/ /AUTOINPUT/ /AUTOOUTPUT/ // Input Pipeline Stage to Mux wire [C_PCI_DATA_WIDTH-1:0] wTxcTlp; wire wTxcTlpReady; wire wTxcTlpValid; wire wTxcTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpStartOffset; wire wTxcTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpEndOffset; wire [C_PCI_DATA_WIDTH-1:0] wTxrTlp; wire wTxrTlpReady; wire wTxrTlpValid; wire wTxrTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpStartOffset; wire wTxrTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpEndOffset; // Output of Mux to wire [C_PCI_DATA_WIDTH-1:0] wTxTlp; wire wTxTlpReady; wire wTxTlpValid; wire wTxTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpStartOffset; wire wTxTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpEndOffset; pipeline #(// Parameters .C_DEPTH (C_PIPELINE_INPUT?1:0), .C_USE_MEMORY (0), /AUTOINSTPARAM/ // Parameters .C_WIDTH (C_WIDTH)) txr_capture_inst (// Outputs .WR_DATA_READY (TXR_TLP_READY), .RD_DATA ({wTxrTlp, wTxrTlpStartFlag, wTxrTlpStartOffset, wTxrTlpEndFlag, wTxrTlpEndOffset}), .RD_DATA_VALID (wTxrTlpValid), // Inputs .WR_DATA ({TXR_TLP, TXR_TLP_START_FLAG, TXR_TLP_START_OFFSET, TXR_TLP_END_FLAG, TXR_TLP_END_OFFSET}), .WR_DATA_VALID (TXR_TLP_VALID), .RD_DATA_READY (wTxrTlpReady), /AUTOINST/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); pipeline #(// Parameters .C_DEPTH (C_PIPELINE_INPUT?1:0), .C_USE_MEMORY (0), /AUTOINSTPARAM/ // Parameters .C_WIDTH (C_WIDTH)) txc_capture_inst (// Outputs .WR_DATA_READY (TXC_TLP_READY), .RD_DATA ({wTxcTlp, wTxcTlpStartFlag, wTxcTlpStartOffset, wTxcTlpEndFlag, wTxcTlpEndOffset}), .RD_DATA_VALID (wTxcTlpValid), // Inputs .WR_DATA ({TXC_TLP, TXC_TLP_START_FLAG, TXC_TLP_START_OFFSET, TXC_TLP_END_FLAG, TXC_TLP_END_OFFSET}), .WR_DATA_VALID (TXC_TLP_VALID), .RD_DATA_READY (wTxcTlpReady), /AUTOINST/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); tx_arbiter #(/AUTOINSTPARAM/ // Parameters .C_TXC_PRIORITY (C_TXC_PRIORITY), .C_TXR_PRIORITY (C_TXR_PRIORITY)) tx_arbiter_inst (// Outputs .TXR_TLP_READY (wTxrTlpReady), .TXC_TLP_READY (wTxcTlpReady), // Inputs .TX_TLP_READY (wTxTlpReady), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), /AUTOINST/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); // MUX Selector tx_phi #(/AUTOINSTPARAM/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_MUX_TYPE (C_MUX_TYPE), .C_WIDTH (C_WIDTH)) tx_phi_inst (// Outputs .TXC_TLP_READY (wTxcTlpReady), .TXR_TLP_READY (wTxrTlpReady), .TX_TLP (wTxTlp), .TX_TLP_VALID (wTxTlpValid), .TX_TLP_START_FLAG (wTxTlpStartFlag), .TX_TLP_START_OFFSET (wTxTlpStartOffset), .TX_TLP_END_FLAG (wTxTlpEndFlag), .TX_TLP_END_OFFSET (wTxTlpEndOffset), // Inputs .TXC_TLP (wTxcTlp), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_START_OFFSET (wTxcTlpStartOffset), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXC_TLP_END_OFFSET (wTxcTlpEndOffset), .TXR_TLP (wTxrTlp), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_START_OFFSET (wTxrTlpStartOffset), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), .TXR_TLP_END_OFFSET (wTxrTlpEndOffset), /AUTOINST/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); pipeline #(// Parameters .C_DEPTH (C_PIPELINE_OUTPUT?1:0), .C_USE_MEMORY (0), /AUTOINSTPARAM/ // Parameters .C_WIDTH (C_WIDTH)) tx_output_inst (// Outputs .WR_DATA_READY (wTxTlpReady), .RD_DATA ({TX_TLP, TX_TLP_START_FLAG, TX_TLP_START_OFFSET, TX_TLP_END_FLAG, TX_TLP_END_OFFSET}), .RD_DATA_VALID (TX_TLP_VALID), // Inputs .WR_DATA ({wTxTlp, wTxTlpStartFlag, wTxTlpStartOffset, wTxTlpEndFlag, wTxTlpEndOffset}), .WR_DATA_VALID (wTxTlpValid), .RD_DATA_READY (TX_TLP_READY), /AUTOINST/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); endmodule // Local Variables: // verilog-library-directories:("." "../../../common/") // End: /* Description: The tx_arbiter arbitrates between TXC and TXR channels. The C_TX_PRIORITY values are counters are the maximum number of uninterrupted TXR or TXC packets that can be transmitted without transmitting a packet of the other type. Notes: Any modifications to this file should meet the conditions set forth in the "Trellis Style Guide" Author: Dustin Richmond (@darichmond) Co-Authors: / module tx_arbiter #(parameter C_TXC_PRIORITY = 1, parameter C_TXR_PRIORITY = 1) ( // Interface: Clocks input CLK, // Interface: Resets input RST_IN, // Interface: TX Classic Flow Control input TX_TLP_READY, // Interface: TXR Flow Control output TXR_TLP_READY, input TXR_TLP_VALID, input TXR_TLP_START_FLAG, input TXR_TLP_END_FLAG, // Interface: TXC Flow Control output TXC_TLP_READY, input TXC_TLP_VALID, input TXC_TLP_START_FLAG, input TXC_TLP_END_FLAG); localparam S_TXARB_IDLE = 0; // STATE: Idle state for the arbiter (not currently used) localparam S_TXARB_TRANSMIT_TXR = 1; // STATE: Transmit TXR packets until the priority counter is reached localparam S_TXARB_TRANSMIT_TXC = 2; // STATE: Transmit TXC packets until the priority counter is reached // S_TXARB_PRIORITY is a special state that encodes the type (TXR/TXC) with // higher priority so that the state machine (below) is general. localparam S_TXARB_PRIORITY = (S_TXARB_TRANSMIT_TXR >= S_TXARB_TRANSMIT_TXC)? S_TXARB_TRANSMIT_TXR: S_TXARB_TRANSMIT_TXC; localparam C_NUM_STATES = S_TXARB_TRANSMIT_TXC; wire wTxrGrant; wire wTxrReq; wire wTxrDone; wire wTxcGrant; wire wTxcReq; wire wTxcDone; reg [clog2s(C_NUM_STATES):0] rArbState,_rArbState; reg rTxrLast,_rTxrLast; // Reset on RST_IN or TXC_TLP_READY reg rTxcLast,_rTxcLast; // Reset on RST_IN or TXR_TLP_READY reg rTxrActive,_rTxrActive; // Reset on RST_IN or TXC_TLP_READY reg rTxcActive,_rTxcActive; // Reset on RST_IN or TXR_TLP_READY reg [clog2s(C_TXC_PRIORITY)-1:0] rTxcCounter,_rTxcCounter; // Reset on RST_IN or TXC_TLP_READY reg [clog2s(C_TXR_PRIORITY)-1:0] rTxrCounter,_rTxrCounter; // Reset on RST_IN or TXR_TLP_READY assign TXR_TLP_READY = wTxrGrant & TX_TLP_READY; // TODO: Not great assign wTxrReq = TXR_TLP_START_FLAG & TXR_TLP_VALID; assign wTxrDone = TXR_TLP_END_FLAG & TXR_TLP_READY; assign wTxrGrant = (rArbState == S_TXARB_TRANSMIT_TXR); assign TXC_TLP_READY = wTxcGrant & TX_TLP_READY; // TODO: Not great assign wTxcReq = TXC_TLP_START_FLAG & TXC_TLP_VALID; assign wTxcDone = TXC_TLP_END_FLAG & TXC_TLP_READY; assign wTxcGrant = (rArbState == S_TXARB_TRANSMIT_TXC); always @() begin // Defaults _rTxcCounter = rTxcCounter; _rTxcActive = rTxcActive; _rTxcLast = rTxcLast; if(wTxrGrant) begin _rTxcCounter = 0; end else if(wTxcReq & wTxcGrant & ~rTxcLast) begin _rTxcCounter = _rTxcCounter + 1; end if(wTxcReq & wTxcGrant) begin _rTxcActive = 1; end else if(wTxcDone) begin _rTxcActive = 0; end if(wTxrGrant \| RST_IN) begin _rTxcLast = 0; end else if(wTxcReq & wTxcGrant) begin _rTxcLast = (rTxcCounter == (C_TXC_PRIORITY - 1)); end end // always @ () always @(posedge CLK) begin if(RST_IN) begin rTxcCounter <= #1 0; rTxcActive <= #1 0; rTxcLast <= #1 0; end else begin rTxcCounter <= #1 _rTxcCounter; rTxcActive <= #1 _rTxcActive; rTxcLast <= #1 _rTxcLast; end end always @() begin // Defaults _rTxrCounter = rTxrCounter; _rTxrActive = rTxrActive; _rTxrLast = rTxrLast; if(wTxcGrant) begin _rTxrCounter = 0; end else if(wTxrReq & wTxrGrant & ~rTxrLast) begin _rTxrCounter = _rTxrCounter + 1; end if(wTxrReq & wTxrGrant) begin _rTxrActive = 1; end else if(wTxrDone) begin _rTxrActive = 0; end if(wTxcGrant \| RST_IN) begin _rTxrLast = 0; end else if(wTxrReq & wTxrGrant) begin / verilator lint_off WIDTH / _rTxrLast = (rTxrCounter == (C_TXR_PRIORITY - 1)); / verilator lint_on WIDTH / end end always @(posedge CLK) begin if(RST_IN) begin rTxrCounter <= #1 0; rTxrActive <= #1 0; rTxrLast <= #1 0; end else begin rTxrCounter <= #1 _rTxrCounter; rTxrActive <= #1 _rTxrActive; rTxrLast <= #1 _rTxrLast; end end // User encoded state machine always @() begin _rArbState = rArbState; case(rArbState) S_TXARB_TRANSMIT_TXR: begin if((rTxrLast & wTxrDone & wTxcReq) \| (~rTxrActive & ~wTxrReq & wTxcReq)) begin _rArbState = S_TXARB_TRANSMIT_TXC; end end S_TXARB_TRANSMIT_TXC: begin if((rTxcLast & wTxcDone & wTxrReq) \| (~rTxcActive & ~wTxcReq & wTxrReq)) begin _rArbState = S_TXARB_TRANSMIT_TXR; end end default: begin // Error! This should never happen... end endcase end // always @ begin always @(posedge CLK) begin if(RST_IN) begin rArbState <= #1 S_TXARB_PRIORITY; end else begin rArbState <= #1 _rArbState; end end endmodule /* Description: The tx_phi wraps a mux instantiation for the tx_mux. It is controlled by the tx_arbiter Notes: Any modifications to this file should meet the conditions set forth in the "Trellis Style Guide" Author: Dustin Richmond (@darichmond) Co-Authors: / module tx_phi #(parameter C_PCI_DATA_WIDTH = 10'd128, parameter C_MUX_TYPE = "SHIFT", parameter C_WIDTH = (C_PCI_DATA_WIDTH + 2 (clog2s(C_PCI_DATA_WIDTH/32) + 1))) (// Interface: Clocks input CLK, // Interface: Resets input RST_IN, // Interface: TXC Flow Control input TXC_TLP_READY, // Interface: TXR Flow Control input TXR_TLP_READY, // Interface: TXC input [C_PCI_DATA_WIDTH-1:0] TXC_TLP, input TXC_TLP_VALID, input TXC_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET, input TXC_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET, // Interface: TXR input [C_PCI_DATA_WIDTH-1:0] TXR_TLP, input TXR_TLP_VALID, input TXR_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET, input TXR_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET, // Interface: TX Classic output [C_PCI_DATA_WIDTH-1:0] TX_TLP, output TX_TLP_VALID, output TX_TLP_START_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET, output TX_TLP_END_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET); // Width = 2 * (DATA WIDTH + VALID + START FLAG + START OFFSET + END FLAG + END OFFSET) localparam C_MUX_WIDTH = C_PCI_DATA_WIDTH + 3 + 2clog2s(C_PCI_DATA_WIDTH/32); wire [2C_MUX_WIDTH-1:0] wAggregate; assign wAggregate = {{TXR_TLP,TXR_TLP_VALID,TXR_TLP_START_FLAG, TXR_TLP_START_OFFSET,TXR_TLP_END_FLAG,TXR_TLP_END_OFFSET}, {TXC_TLP,TXC_TLP_VALID,TXC_TLP_START_FLAG, TXC_TLP_START_OFFSET,TXC_TLP_END_FLAG,TXC_TLP_END_OFFSET}}; mux #(// Parameters .C_NUM_INPUTS (2), .C_CLOG_NUM_INPUTS (1), .C_WIDTH (C_MUX_WIDTH), .C_MUX_TYPE ("SELECT") /AUTOINSTPARAM/) mux_inst (// Outputs .MUX_OUTPUT ({TX_TLP,TX_TLP_VALID,TX_TLP_START_FLAG, TX_TLP_START_OFFSET,TX_TLP_END_FLAG, TX_TLP_END_OFFSET}), // Inputs .MUX_INPUTS (wAggregate), .MUX_SELECT (TXR_TLP_READY) /AUTOINST/); endmodule
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_8_b2s_b_channel.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" ) module axi_protocol_converter_v2_1_8_b2s_b_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk, input wire reset, // AXI signals output wire [C_ID_WIDTH-1:0] s_bid, output wire [1:0] s_bresp, output wire s_bvalid, input wire s_bready, input wire [1:0] m_bresp, input wire m_bvalid, output wire m_bready, // Signals to/from the axi_protocol_converter_v2_1_8_b2s_aw_channel modules input wire b_push, input wire [C_ID_WIDTH-1:0] b_awid, input wire [7:0] b_awlen, input wire b_resp_rdy, output wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // AXI protocol responses: localparam [1:0] LP_RESP_OKAY = 2'b00; localparam [1:0] LP_RESP_EXOKAY = 2'b01; localparam [1:0] LP_RESP_SLVERROR = 2'b10; localparam [1:0] LP_RESP_DECERR = 2'b11; // FIFO settings localparam P_WIDTH = C_ID_WIDTH + 8; localparam P_DEPTH = 4; localparam P_AWIDTH = 2; localparam P_RWIDTH = 2; localparam P_RDEPTH = 4; localparam P_RAWIDTH = 2; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg bvalid_i; wire [C_ID_WIDTH-1:0] bid_i; wire shandshake; reg shandshake_r; wire mhandshake; reg mhandshake_r; wire b_empty; wire bresp_full; wire bresp_empty; wire [7:0] b_awlen_i; reg [7:0] bresp_cnt; reg [1:0] s_bresp_acc; wire [1:0] s_bresp_acc_r; reg [1:0] s_bresp_i; wire need_to_update_bresp; wire bresp_push; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // assign AXI outputs assign s_bid = bid_i; assign s_bresp = s_bresp_acc_r; assign s_bvalid = bvalid_i; assign shandshake = s_bvalid & s_bready; assign mhandshake = m_bvalid & m_bready; always @(posedge clk) begin if (reset \| shandshake) begin bvalid_i <= 1'b0; end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin bvalid_i <= 1'b1; end end always @(posedge clk) begin shandshake_r <= shandshake; mhandshake_r <= mhandshake; end axi_protocol_converter_v2_1_8_b2s_simple_fifo #( .C_WIDTH (P_WIDTH), .C_AWIDTH (P_AWIDTH), .C_DEPTH (P_DEPTH) ) bid_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( b_push ) , .rd_en ( shandshake_r ) , .din ( {b_awid, b_awlen} ) , .dout ( {bid_i, b_awlen_i}) , .a_full ( ) , .full ( b_full ) , .a_empty ( ) , .empty ( b_empty ) ); assign m_bready = ~mhandshake_r & bresp_empty; ///////////////////////////////////////////////////////////////////////////// // Update if more critical. assign need_to_update_bresp = ( m_bresp > s_bresp_acc ); // Select accumultated or direct depending on setting. always @( ) begin if ( need_to_update_bresp ) begin s_bresp_i = m_bresp; end else begin s_bresp_i = s_bresp_acc; end end ///////////////////////////////////////////////////////////////////////////// // Accumulate MI-side BRESP. always @ (posedge clk) begin if (reset \| bresp_push ) begin s_bresp_acc <= LP_RESP_OKAY; end else if ( mhandshake ) begin s_bresp_acc <= s_bresp_i; end end assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty; always @ (posedge clk) begin if (reset \| bresp_push ) begin bresp_cnt <= 8'h00; end else if ( mhandshake_r ) begin bresp_cnt <= bresp_cnt + 1'b1; end end axi_protocol_converter_v2_1_8_b2s_simple_fifo #( .C_WIDTH (P_RWIDTH), .C_AWIDTH (P_RAWIDTH), .C_DEPTH (P_RDEPTH) ) bresp_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( bresp_push ) , .rd_en ( shandshake_r ) , .din ( s_bresp_acc ) , .dout ( s_bresp_acc_r) , .a_full ( ) , .full ( bresp_full ) , .a_empty ( ) , .empty ( bresp_empty ) ); endmodule `default_nettype wire
/* * Titor - Byte-striped Memory Bank * Copyright (C) 2013 Sean Ryan Moore * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. / `ifdef INC_STRIPED_MEMORY `else `define INC_STRIPED_MEMORY module StripedMemory( dout, din, address, size, read_write, enable, clk, reset ); `include "definition/Definition.v" parameter MDIR = BLANKFILE; // interface output reg [WORD-1:0] dout; input [WORD-1:0] din; input [WORD-1:0] address; input [LOGWORDBYTE-1:0] size; // [0 to WORDBYTE-1] maps to [1 to WORDBYTE] input read_write; input enable; input clk; input reset; wire [WORD-1:0] stripe_dout [WORDBYTE-1:0]; reg [WORD-1:0] stripe_din [WORDBYTE-1:0]; reg [WORD-1:0] stripe_address [WORDBYTE-1:0]; //reg [0-1:0] stripe_size [WORDBYTE-1:0]; reg stripe_read_write [WORDBYTE-1:0]; reg stripe_enable [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] end_left; reg [LOGWORDBYTE-1:0] end_right; reg [LOGWORDBYTE-1:0] off_addr [WORDBYTE-1:0]; reg [WORD-1:0] div_addr [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] iselect [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] oselect [WORDBYTE-1:0]; reg [BYTE-1:0] breakout_din [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] d_size; reg [LOGWORDBYTE-1:0] d_oselect [WORDBYTE-1:0]; always @(posedge clk) begin if(reset) begin d_size <= 0; end else begin d_size <= size; end end always @() begin end_left <= ((address+0 ) % WORDBYTE); end_right <= ((address+size) % WORDBYTE); end genvar i; generate for(i=0; i<WORDBYTE; i=i+1) begin : MEMGEN if(MDIR != BLANKFILE) begin Memory #( .MWIDTH (BYTE ), // 8-bit word .LOGWORDBYTE (LOGWORDBYTE ), // with 32-bit interfaces .LOGMEM (LOGMEM-LOGWORDBYTE ) // divide by 8 for the 8 banks ) mem ( .dout (stripe_dout[i] ), .din (stripe_din[i] ), .address (stripe_address[i] ), .size (0 ), .read_write (stripe_read_write[i] ), .enable (stripe_enable[i] ), .clk (clk ), .reset (reset ) ); end else begin Memory #( .MFILE (BLANKFILE ), // no input file .MWIDTH (BYTE ), // 8-bit word .LOGWORDBYTE (LOGWORDBYTE ), // with 32-bit interfaces .LOGMEM (LOGMEM-LOGWORDBYTE ) // divide by 8 for the 8 banks ) mem ( .dout (stripe_dout[i] ), .din (stripe_din[i] ), .address (stripe_address[i] ), .size (0 ), .read_write (stripe_read_write[i] ), .enable (stripe_enable[i] ), .clk (clk ), .reset (reset ) ); end always @() begin stripe_address[i] <= div_addr[i]; stripe_read_write[i] <= read_write; stripe_enable[i] <= enable && ( (end_left <= end_right) ? ((end_left<=i) && (i<=end_right)) : ((end_left<=i) \|\| (i<=end_right)) ); off_addr[i] <= end_left <= i ? i-end_left : (WORDBYTE-end_left)+i; div_addr[i] <= (address+off_addr[i]) / WORDBYTE; stripe_din[i] <= breakout_din[iselect[i]]; iselect[i] <= (i + WORDBYTE - end_left) % WORDBYTE; oselect[i] <= (i + WORDBYTE + end_left) % WORDBYTE; breakout_din[i] <= din[ (BYTE(i+1))-1 : (BYTE(i+0)) ]; dout[ (BYTE(i+1))-1 : (BYTE*(i+0))-0 ] <= (i<=d_size) ? stripe_dout[d_oselect[i]] : 0; end always @(posedge clk) begin if(reset) begin d_oselect[i] <= 0; end else begin d_oselect[i] <= oselect[i]; end end end endgenerate endmodule `endif
// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. //////////////////////////////////////////////////////////////////// // // ALTERA_INT_OSC // // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // //////////////////////////////////////////////////////////////////// // synthesis VERILOG_INPUT_VERSION VERILOG_2001 `timescale 1 ps / 1 ps module altera_int_osc ( clkout, oscena); parameter DEVICE_FAMILY = "MAX 10"; parameter DEVICE_ID = "08"; parameter CLOCK_FREQUENCY = "dummy"; output clkout; input oscena; wire wire_clkout; assign clkout = wire_clkout; // ------------------------------------------------------------------- // Instantiate wysiwyg for chipidblock according to device family // ------------------------------------------------------------------- generate if (DEVICE_FAMILY == "MAX 10") begin fiftyfivenm_oscillator # ( //MAX 10 .device_id(DEVICE_ID), .clock_frequency(CLOCK_FREQUENCY) ) oscillator_dut ( .clkout(wire_clkout), .clkout1(), .oscena(oscena)); end endgenerate endmodule //altera_int_osc //VALID FILE
//Copyright (C) 1991-2012 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module acl_fp_custom_mul_op_s5 ( clock, resetn, mantissa_left, exponent_left, sign_left, mantissa_right, exponent_right, sign_right, result_mantissa, result_exponent, result_sign, // Used in HIGH_CAPACITY = 1 mode stall_in, valid_in, stall_out, valid_out, // Used in HIGH_CAPACITY = 0 mode enable); parameter HIGH_CAPACITY = 1; parameter FLUSH_DENORMS = 0; parameter REMOVE_STICKY = 1; parameter FINITE_MATH_ONLY = 1; parameter HIGH_LATENCY = 1; input clock, resetn; input [26:0] mantissa_left; input [8:0] exponent_left; input sign_left; input [26:0] mantissa_right; input [8:0] exponent_right; input sign_right; input enable; input stall_in, valid_in; output stall_out, valid_out; output [27:0] result_mantissa; output [8:0] result_exponent; output result_sign; wire [53:0] sub_wire0; wire enable_mult_stage; // The multiplier. -- CAUTION This only works for HIGH_LATENCY == 0 --> 2 cycles sv_mult27 the_multiplier(clock,enable_mult_stage,mantissa_left,mantissa_right,sub_wire0); reg [9:0] exponent_1; reg [8:0] exponent_2; reg [8:0] exponent_3; reg [5:0] man_a_clear; reg [5:0] man_b_clear; reg exp_zeroed; reg sign_1, sign_2, sign_3, exp_out_of_range, generate_inf, exp_left, exp_right; reg valid_1, valid_2, valid_3, flush_mantissa, make_nan, make_nan_r; wire stall_mult; assign enable_mult_stage = (HIGH_CAPACITY == 1) ? (~valid_2 \| ~stall_mult) : enable; assign stall_out = valid_2 & stall_mult; generate if (HIGH_LATENCY == 1) begin reg flush_mantissa_r; always@(posedge clock or negedge resetn) begin if (~resetn) begin exponent_1 <= 10'dx; exponent_2 <= 9'dx; exponent_3 <= 9'dx; exp_out_of_range <= 1'bx; sign_1 <= 1'bx; sign_2 <= 1'bx; sign_3 <= 1'bx; flush_mantissa_r <= 1'bx; flush_mantissa <= 1'bx; man_a_clear <= 6'dx; man_b_clear <= 6'dx; make_nan_r <= 1'bx; make_nan <= 1'bx; valid_1 <= 1'b0; valid_2 <= 1'b0; valid_3 <= 1'b0; exp_left <= 1'bx; exp_right <= 1'bx; exp_zeroed <= 1'bx; end else if (enable_mult_stage) begin valid_1 <= valid_in; valid_2 <= valid_1; sign_1 <= sign_left ^ sign_right; sign_2 <= sign_1; exp_left <= exponent_left[8]; exp_right <= exponent_right[8]; exp_out_of_range <= (exponent_left[8] \| exponent_right[8]); if ((exponent_left[8] \|\| exponent_right[8]) && (FINITE_MATH_ONLY == 0)) exponent_1 <= 10'h1ff; else exponent_1 <= exponent_left + exponent_right - 10'd127; man_a_clear <= {mantissa_left[26], \|mantissa_left[25:21], \|mantissa_left[20:15], \|mantissa_left[14:10], \|mantissa_left[9:5], \|mantissa_left[4:0]}; man_b_clear <= {mantissa_right[26], \|mantissa_right[25:21], \|mantissa_right[20:15], \|mantissa_right[14:10], \|mantissa_right[9:5], \|mantissa_right[4:0]}; // Second cycle. flush_mantissa_r <= 1'b0; make_nan_r <= 1'b0; if (exp_out_of_range && (FINITE_MATH_ONLY == 0)) begin exponent_2 <= 9'h1ff; if (((exp_left & (~\|man_a_clear[4:0])) & (~exp_right & (~\|man_b_clear))) \|\| ((exp_right & (~\|man_b_clear[4:0])) & (~exp_left & (~\|man_a_clear))) \|\| ((exp_left & (\|man_a_clear[4:0])) \|\| (exp_right & (\|man_b_clear[4:0])))) make_nan_r <= 1'b1; else flush_mantissa_r <= 1'b1; end else if (exponent_1[9]) // resulting exponent is less than zero. begin exponent_2 <= 9'd0; flush_mantissa_r <= 1'b1; end else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0))// resulting exponent is above max begin flush_mantissa_r <= 1'b1; exponent_2 <= 9'h1ff; end else exponent_2 <= exponent_1[8:0]; // Third cycle. exp_zeroed <= ~\|exponent_2; flush_mantissa <= flush_mantissa_r; exponent_3 <= exponent_2; sign_3 <= sign_2; valid_3 <= valid_2; make_nan <= make_nan_r; end end end else begin always@(posedge clock or negedge resetn) begin if (~resetn) begin exponent_1 <= 10'dx; exponent_2 <= 9'dx; exp_out_of_range <= 1'bx; sign_1 <= 1'bx; sign_2 <= 1'bx; flush_mantissa <= 1'bx; man_a_clear <= 5'dx; man_b_clear <= 5'dx; make_nan <= 1'bx; valid_1 <= 1'b0; valid_2 <= 1'b0; exp_left <= 1'bx; exp_right <= 1'bx; exp_zeroed <= 1'bx; end else if (enable_mult_stage) begin valid_1 <= valid_in; valid_2 <= valid_1; sign_1 <= sign_left ^ sign_right; sign_2 <= sign_1; exp_out_of_range <= exponent_left[8] \| exponent_right[8]; exp_left <= exponent_left[8]; exp_right <= exponent_right[8]; if ((exponent_left[8] \|\| exponent_right[8]) && (FINITE_MATH_ONLY == 0)) exponent_1 <= 10'h1ff; else exponent_1 <= exponent_left + exponent_right - 10'd127; man_a_clear <= {mantissa_left[26], \|mantissa_left[25:21], \|mantissa_left[20:15], \|mantissa_left[14:10], \|mantissa_left[9:5], \|mantissa_left[4:0]}; man_b_clear <= {mantissa_right[26], \|mantissa_right[25:21], \|mantissa_right[20:15], \|mantissa_right[14:10], \|mantissa_right[9:5], \|mantissa_right[4:0]}; // Second cycle. flush_mantissa <= 1'b0; make_nan <= 1'b0; if (exp_out_of_range && (FINITE_MATH_ONLY == 0)) begin exponent_2 <= 9'h1ff; if (((exp_left & (~\|man_a_clear[4:0])) & (~exp_right & (~\|man_b_clear))) \|\| ((exp_right & (~\|man_b_clear[4:0])) & (~exp_left & (~\|man_a_clear))) \|\| ((exp_left & (\|man_a_clear[4:0])) \|\| (exp_right & (\|man_b_clear[4:0])))) make_nan <= 1'b1; else flush_mantissa <= 1'b1; end else if (exponent_1[9]) // resulting exponent is less than zero. begin exponent_2 <= 9'd0; flush_mantissa <= 1'b1; end else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0)) // resulting exponent is above max begin flush_mantissa <= 1'b1; exponent_2 <= 9'h1ff; end else exponent_2 <= exponent_1[8:0]; exp_zeroed <= ~\|exponent_1; end end end endgenerate // Now collect results in registers. reg [27:0] mult_result_int; reg [8:0] mult_exp_int; reg mult_sign_int; reg mult_valid_int; reg [4:0] mult_tail_bits; reg exp_was_zero; reg clear_mantissa; reg is_nan; wire stall_post_int; wire enable_post_mult_stage_int; assign enable_post_mult_stage_int = (HIGH_CAPACITY == 1) ? (~mult_valid_int \| ~stall_post_int) : enable; assign stall_mult = mult_valid_int & stall_post_int; generate if (HIGH_LATENCY == 1) begin always@(posedge clock or negedge resetn) begin if (~resetn) begin mult_valid_int <= 1'b0; mult_result_int <= 28'dx; mult_exp_int <= 9'dx; clear_mantissa <= 1'bx; mult_tail_bits <= 5'dx; exp_was_zero <= 1'bx; is_nan <= 1'bx; mult_sign_int <= 1'bx; end else if (enable_post_mult_stage_int) begin mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2; is_nan <= make_nan; clear_mantissa <= flush_mantissa \| ((FLUSH_DENORMS == 1) & exp_zeroed & (~\|sub_wire0[53:52])); mult_result_int <= sub_wire0[53:26]; exp_was_zero <= exp_zeroed; mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2; mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2; if (REMOVE_STICKY == 1) mult_tail_bits <= 5'd0; else mult_tail_bits <= {\|sub_wire0[25:20],\|sub_wire0[19:15],\|sub_wire0[14:10],\|sub_wire0[9:5],\|sub_wire0[4:0]}; end end end else begin always@() begin mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2; is_nan <= make_nan; clear_mantissa <= flush_mantissa \| ((FLUSH_DENORMS == 1) & exp_zeroed & (~\|sub_wire0[53:52])); mult_result_int <= sub_wire0[53:26]; exp_was_zero <= exp_zeroed; mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2; mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2; if (REMOVE_STICKY == 1) mult_tail_bits <= 5'd0; else mult_tail_bits <= {\|sub_wire0[25:20],\|sub_wire0[19:15],\|sub_wire0[14:10],\|sub_wire0[9:5],\|sub_wire0[4:0]}; end end endgenerate // Now collect results in registers. reg [27:0] mult_result; reg [8:0] mult_exp; reg mult_sign; reg mult_valid; wire stall_post, enable_post_mult_stage; assign enable_post_mult_stage = (HIGH_CAPACITY == 1) ? (~mult_valid \| ~stall_post) : enable; assign stall_post_int = mult_valid & stall_post; generate if (HIGH_LATENCY == 1) begin always@(posedge clock or negedge resetn) begin if (~resetn) begin mult_valid <= 1'b0; mult_result <= 28'dx; mult_exp <= 9'dx; mult_sign <= 1'bx; end else if (enable_post_mult_stage) begin mult_valid <= mult_valid_int; if (REMOVE_STICKY == 1) begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:1]}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0]; end else begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:2], \|mult_result_int[1:0] \| (\|mult_tail_bits)}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] \| (\|mult_tail_bits)}; end if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa) mult_exp <= 9'd1; else mult_exp <= mult_exp_int; mult_sign <= mult_sign_int; end end end else begin always@() begin mult_valid <= mult_valid_int; if (REMOVE_STICKY == 1) begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:1]}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0]; end else begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:2], \|mult_result_int[1:0] \| (\|mult_tail_bits)}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] \| (\|mult_tail_bits)}; end if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa) mult_exp <= 9'd1; else mult_exp <= mult_exp_int; mult_sign <= mult_sign_int; end end endgenerate // Now put a staging register if we are in high-capacity mode generate if (HIGH_CAPACITY == 1) begin reg [27:0] result_mantissa_sr; reg [8:0] result_exponent_sr; reg result_sign_sr; reg result_sr_valid; always@(posedge clock or negedge resetn) begin if (~resetn) begin result_mantissa_sr <= 28'dx; result_exponent_sr <= 9'dx; result_sign_sr <= 1'bx; result_sr_valid <= 1'b0; end else begin if (~stall_in) result_sr_valid <= 1'b0; else if (~result_sr_valid) result_sr_valid <= mult_valid; if (~result_sr_valid) begin result_mantissa_sr <= mult_result; result_exponent_sr <= mult_exp; result_sign_sr <= mult_sign; end end end assign result_mantissa = result_sr_valid ? result_mantissa_sr : mult_result; assign result_exponent = result_sr_valid ? result_exponent_sr : mult_exp; assign result_sign = result_sr_valid ? result_sign_sr : mult_sign; assign valid_out = result_sr_valid \| mult_valid; assign stall_post = result_sr_valid; end else begin assign result_mantissa = mult_result; assign result_exponent = mult_exp; assign result_sign = mult_sign; assign valid_out = mult_valid; assign stall_post = stall_in; end endgenerate endmodule
//////////////////////////////////////////////////////////////////////////////// // Original Author: Schuyler Eldridge // Contact Point: Schuyler Eldridge ([email protected]) // t_sqrt_pipelined.v // Created: 4.2.2012 // Modified: 4.5.2012 // // Testbench for generic sqrt operation // // Copyright (C) 2012 Schuyler Eldridge, Boston University // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. //////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module t_sqrt_pipelined(); parameter INPUT_BITS = 4; localparam OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; reg [INPUT_BITS-1:0] radicand; reg clk, start, reset_n; wire [OUTPUT_BITS-1:0] root; wire data_valid; // wire [7:0] root_good; sqrt_pipelined #( .INPUT_BITS(INPUT_BITS) ) sqrt_pipelined ( .clk(clk), .reset_n(reset_n), .start(start), .radicand(radicand), .data_valid(data_valid), .root(root) ); initial begin radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;; #10 reset_n = 0; clk = 0; #50 reset_n = 1; radicand = 0; // #40 radicand = 81; start = 1; // #10 radicand = 16'bx; start = 0; #10000 $finish; end always #5 clk = ~clk; always begin #10 radicand = radicand + 1; start = 1; #10 start = 0; end // always begin // #80 start = 1; // #10 start = 0; // end endmodule
//`include "../../firmware/include/fpga_regs_common.v" //`include "../../firmware/include/fpga_regs_standard.v" module rx_buffer_inband ( input usbclk, input bus_reset, input reset, // DSP side reset (used here), do not reset registers input reset_regs, //Only reset registers output [15:0] usbdata, input RD, output wire have_pkt_rdy, output reg rx_overrun, input wire [3:0] channels, input wire [15:0] ch_0, input wire [15:0] ch_1, input wire [15:0] ch_2, input wire [15:0] ch_3, input wire [15:0] ch_4, input wire [15:0] ch_5, input wire [15:0] ch_6, input wire [15:0] ch_7, input rxclk, input rxstrobe, input clear_status, input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, output wire [15:0] debugbus, //Connection with tx_inband input rx_WR, input [15:0] rx_databus, input rx_WR_done, output reg rx_WR_enabled, //signal strength input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, input wire [31:0] rssi_3, input wire [1:0] tx_underrun ); parameter NUM_CHAN =1; genvar i ; // FX2 Bug Fix reg [8:0] read_count; always @(negedge usbclk) if(bus_reset) read_count <= #1 9'd0; else if(RD & ~read_count[8]) read_count <= #1 read_count + 9'd1; else read_count <= #1 RD ? read_count : 9'b0; // Time counter reg [31:0] adctime; always @(posedge rxclk) if (reset) adctime <= 0; else if (rxstrobe) adctime <= adctime + 1; // USB side fifo wire [11:0] rdusedw; wire [11:0] wrusedw; wire [15:0] fifodata; wire [15:0] fifodata_il; reg [15:0] fifodata_16; wire WR; wire have_space; assign fifodata_il = fifodata_16; fifo_4kx16_dc rx_usb_fifo ( .aclr ( reset ), .data ( fifodata ), .rdclk ( ~usbclk ), .rdreq ( RD & ~read_count[8] ), .wrclk ( rxclk ), .wrreq ( WR ), .q ( usbdata ), .rdempty ( ), .rdusedw ( rdusedw ), .wrfull ( ), .wrusedw ( wrusedw ) ); assign have_pkt_rdy = (rdusedw >= 12'd256); assign have_space = (wrusedw < 12'd760); // Rx side fifos wire chan_rdreq; wire [15:0] chan_fifodata; wire [9:0] chan_usedw; wire [NUM_CHAN:0] chan_empty; wire [3:0] rd_select; wire [NUM_CHAN:0] rx_full; wire [7:0] debug; packet_builder #(NUM_CHAN) rx_pkt_builer ( .rxclk ( rxclk ), .reset ( reset ), .adctime ( adctime ), .channels ( 4'd1 ), //need to be tested and changed to channels .chan_rdreq ( chan_rdreq ), .chan_fifodata ( chan_fifodata ), .chan_empty ( chan_empty ), .rd_select ( rd_select ), .chan_usedw ( chan_usedw ), .WR ( WR ), .fifodata ( fifodata ), .have_space ( have_space ), .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), .underrun(tx_underrun)); // Detect overrun always @(posedge rxclk) if(reset) rx_overrun <= 1'b0; else if(rx_full[0]) rx_overrun <= 1'b1; else if(clear_status) rx_overrun <= 1'b0; // TODO write this genericly //wire [15:0]ch[NUM_CHAN:0]; //assign ch[0] = ch_0; wire cmd_empty; always @(posedge rxclk) if(reset) rx_WR_enabled <= 1; else if(cmd_empty) rx_WR_enabled <= 1; else if(rx_WR_done) rx_WR_enabled <= 0; // Switching of channels reg [3:0] store_next; always @(posedge rxclk) if(reset) store_next <= #1 4'd0; else if(rxstrobe & (store_next == 0)) store_next <= #1 4'd1; else if(~rx_full & (store_next == 4'd2)) store_next <= #1 4'd0; else if(~rx_full & (store_next != 0)) store_next <= #1 store_next + 4'd1; always @* case(store_next) 4'd1 : fifodata_16 = ch_0; 4'd2 : fifodata_16 = ch_1; default: fifodata_16 = 16'hFFFF; endcase wire [15:0] dataout [0:NUM_CHAN]; wire [9:0] usedw [0:NUM_CHAN]; wire empty[0:NUM_CHAN]; generate for (i = 0 ; i < NUM_CHAN; i = i + 1) begin : generate_channel_fifos wire rdreq; assign rdreq = (rd_select == i) & chan_rdreq; fifo_1kx16 rx_chan_fifo ( .aclr ( reset ), .clock ( rxclk ), .data ( fifodata_il ), .rdreq ( rdreq ), .wrreq ( ~rx_full[i] & (store_next != 0)), .empty (empty[i]), .full (rx_full[i]), .q ( dataout[i]), .usedw ( usedw[i]), .almost_empty(chan_empty[i]) ); end endgenerate fifo_1kx16 rx_cmd_fifo ( .aclr ( reset ), .clock ( rxclk ), .data ( rx_databus ), .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), .wrreq ( rx_WR & rx_WR_enabled), .empty ( cmd_empty), .full ( rx_full[NUM_CHAN] ), .q ( dataout[NUM_CHAN]), .usedw ( usedw[NUM_CHAN] ) ); assign chan_empty[NUM_CHAN] = cmd_empty \| rx_WR_enabled; assign chan_fifodata = dataout[rd_select]; assign chan_usedw = usedw[rd_select]; assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]}; endmodule
module m_tera; // global section // specify clock LOW and reset HIGH initial values reg r_clock = 1'b0; reg r_reset = 1'b1; wire w_clock, w_reset; assign w_clock = r_clock; assign w_reset = r_reset; // end global section // program counter section reg r_pc_demux_channel = 1'b0; wire [7:0] w_bus_instr_mem_addr, w_bus_alu_out; wire w_jump_flag; m_program_counter pc (w_bus_instr_mem_addr, w_bus_alu_out, w_jump_flag, w_clock, w_reset); // end program counter section // memory section wire [7:0] w_bus_instr_mem_word, w_bus_data_mem_word, w_bus_data_mem_addr, w_bus_high_register_value, w_bus_low_register_value; wire w_data_mem_write_enable; m_instruction_memory instr_mem (w_bus_instr_mem_word, w_bus_instr_mem_addr); m_data_memory data_mem (w_bus_data_mem_word, w_bus_high_register_value, w_data_mem_write_enable, w_reset, w_clock); // end memory section // register file section wire [7:0] w_bus_write_back_value; wire [3:0] w_bus_write_back_reg; wire w_write_back_flag; m_register_file regfile (w_bus_high_register_value, w_bus_low_register_value, w_bus_instr_mem_word, w_bus_write_back_value, w_bus_write_back_reg, w_write_back_flag, w_clock, w_reset); // end register file section // instruction logic unit section wire w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_cf; // w_cf is comparison flag m_instruction_logic_unit ilu (w_jump_flag, w_data_mem_write_enable, w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_write_back_flag, w_bus_write_back_reg, w_bus_instr_mem_word, w_cf, w_clock); // end instruction logic unit section // arithmetic logic unit section m_arithmetic_logic_unit alu (w_bus_alu_out, w_cf, w_bus_instr_mem_word, w_bus_high_register_value, w_bus_low_register_value, w_clock); // end arithmetic logic unit section // mux/demux section wire [7:0] w_bus_demux_inter0, w_bus_mux_inter; m_1to2_8bit_demux store_demux (w_bus_demux_inter0, w_bus_data_mem_word, w_bus_alu_out, w_store_word_flag); m_2to1_8bit_mux load_mux (w_bus_mux_inter, w_bus_demux_inter0, w_bus_data_mem_word, w_load_word_flag); m_2to1_8bit_mux_with_add1 pc_mux (w_bus_write_back_value, w_bus_mux_inter, w_bus_instr_mem_addr, w_store_pc_flag); // end mux/demux section initial begin $dumpfile ("dumpfile.vcd"); $dumpvars (0, m_tera); $display ("\nStarting program (Program Counter = 0).\n"); #2 r_reset = 1'b0; end always #1 begin r_clock = ~w_clock; // send clock pulses if (w_bus_instr_mem_addr == 8'b11111111) begin $display ("\nReached EOF (Program Counter = 255). Closing program.\n"); $finish; end end endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V `define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V /* * or2b: 2-input OR, first input inverted. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_hd__or2b ( X , A , B_N , VPWR, VGND, VPB , VNB ); // Module ports output X ; input A ; input B_N ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire not0_out ; wire or0_out_X ; wire pwrgood_pp0_out_X; // Name Output Other arguments not not0 (not0_out , B_N ); or or0 (or0_out_X , not0_out, A ); sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND); buf buf0 (X , pwrgood_pp0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
//----------------------------------------------------------------- // System Generator version 2013.4 Verilog source file. // // Copyright(C) 2013 by Xilinx, Inc. All rights reserved. This // text/file contains proprietary, confidential information of Xilinx, // Inc., is distributed under license from Xilinx, Inc., and may be used, // copied and/or disclosed only pursuant to the terms of a valid license // agreement with Xilinx, Inc. Xilinx hereby grants you a license to use // this text/file solely for design, simulation, implementation and // creation of design files limited to Xilinx devices or technologies. // Use with non-Xilinx devices or technologies is expressly prohibited // and immediately terminates your license unless covered by a separate // agreement. // // Xilinx is providing this design, code, or information "as is" solely // for use in developing programs and solutions for Xilinx devices. By // providing this design, code, or information as one possible // implementation of this feature, application or standard, Xilinx is // making no representation that this implementation is free from any // claims of infringement. You are responsible for obtaining any rights // you may require for your implementation. Xilinx expressly disclaims // any warranty whatsoever with respect to the adequacy of the // implementation, including but not limited to warranties of // merchantability or fitness for a particular purpose. // // Xilinx products are not intended for use in life support appliances, // devices, or systems. Use in such applications is expressly prohibited. // // Any modifications that are made to the source code are done at the user's // sole risk and will be unsupported. // // This copyright and support notice must be retained as part of this // text at all times. (c) Copyright 1995-2013 Xilinx, Inc. All rights // reserved. //----------------------------------------------------------------- `include "conv_pkg.v" module xlconvert_ip_pid_controller (din, clk, ce, clr, en, dout); //Parameter Definitions parameter din_width= 16; parameter din_bin_pt= 4; parameter din_arith= `xlUnsigned; parameter dout_width= 8; parameter dout_bin_pt= 2; parameter dout_arith= `xlUnsigned; parameter en_width = 1; parameter en_bin_pt = 0; parameter en_arith = `xlUnsigned; parameter bool_conversion = 0; parameter latency = 0; parameter quantization= `xlTruncate; parameter overflow= `xlWrap; //Port Declartions input [din_width-1:0] din; input clk, ce, clr; input [en_width-1:0] en; output [dout_width-1:0] dout; //Wire Declartions wire [dout_width-1:0] result; wire internal_ce; assign internal_ce = ce & en[0]; generate if (bool_conversion == 1) begin:bool_converion_generate assign result = din; end else begin:std_conversion convert_type #(din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow) conv_udp (.inp(din), .res(result)); end endgenerate generate if (latency > 0) begin:latency_test synth_reg # (dout_width, latency) reg1 ( .i(result), .ce(internal_ce), .clr(clr), .clk(clk), .o(dout)); end else begin:latency0 assign dout = result; end endgenerate endmodule module sysgen_mcode_block_698c2b186c ( input [(32 - 1):0] x, output [(32 - 1):0] z, input clk, input ce, input clr); wire signed [(32 - 1):0] x_1_22; localparam [(11 - 1):0] const_value = 11'b10010000000; localparam [(11 - 1):0] const_value_x_000000 = 11'b11111111111; localparam [(11 - 1):0] const_value_x_000001 = 11'b10010000000; localparam signed [(32 - 1):0] const_value_x_000002 = 32'sb00000100100000000000000000000000; wire rel_3_6; localparam [(11 - 1):0] const_value_x_000003 = 11'b11111111111; localparam signed [(32 - 1):0] const_value_x_000004 = 32'sb00000111111111110000000000000000; wire rel_5_10; reg signed [(32 - 1):0] z_join_3_3; localparam signed [(32 - 1):0] const_value_x_000005 = 32'sb00000100100000000000000000000000; localparam signed [(32 - 1):0] const_value_x_000006 = 32'sb00000111111111110000000000000000; assign x_1_22 = x; assign rel_3_6 = x_1_22 < const_value_x_000002; assign rel_5_10 = x_1_22 > const_value_x_000004; always @(rel_3_6 or rel_5_10 or x_1_22) begin:proc_if_3_3 if (rel_3_6) begin z_join_3_3 = const_value_x_000005; end else if (rel_5_10) begin z_join_3_3 = const_value_x_000006; end else begin z_join_3_3 = x_1_22; end end assign z = z_join_3_3; endmodule module sysgen_constant_383443dd88 ( output [(8 - 1):0] op, input clk, input ce, input clr); assign op = 8'b00000000; endmodule module xldelay_ip_pid_controller #(parameter width = -1, latency = -1, reg_retiming = 0, reset = 0) (input [width-1:0] d, input ce, clk, en, rst, output [width-1:0] q); generate if ((latency == 0) \|\| ((reg_retiming == 0) && (reset == 0))) begin:srl_delay synth_reg # (width, latency) reg1 ( .i(d), .ce(ce & en), .clr(1'b0), .clk(clk), .o(q)); end if ((latency>=1) && ((reg_retiming) \|\| (reset))) begin:reg_delay synth_reg_reg # (width, latency) reg2 ( .i(d), .ce(ce & en), .clr(rst), .clk(clk), .o(q)); end endgenerate endmodule module sysgen_inverter_91fd45ca5a ( input [(1 - 1):0] ip, output [(1 - 1):0] op, input clk, input ce, input clr); wire ip_1_26; reg op_mem_22_20[0:(1 - 1)]; initial begin op_mem_22_20[0] = 1'b0; end wire op_mem_22_20_front_din; wire op_mem_22_20_back; wire op_mem_22_20_push_front_pop_back_en; localparam [(1 - 1):0] const_value = 1'b1; wire internal_ip_12_1_bitnot; assign ip_1_26 = ip; assign op_mem_22_20_back = op_mem_22_20[0]; always @(posedge clk) begin:proc_op_mem_22_20 integer i; if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1))) begin op_mem_22_20[0] <= op_mem_22_20_front_din; end end assign internal_ip_12_1_bitnot = ~ip_1_26; assign op_mem_22_20_front_din = internal_ip_12_1_bitnot; assign op_mem_22_20_push_front_pop_back_en = 1'b1; assign op = op_mem_22_20_back; endmodule module sysgen_logical_098c9fa070 ( input [(1 - 1):0] d0, input [(1 - 1):0] d1, output [(1 - 1):0] y, input clk, input ce, input clr); wire d0_1_24; wire d1_1_27; wire fully_2_1_bit; assign d0_1_24 = d0; assign d1_1_27 = d1; assign fully_2_1_bit = d0_1_24 & d1_1_27; assign y = fully_2_1_bit; endmodule module xlregister_ip_pid_controller (d, rst, en, ce, clk, q); parameter d_width = 5; parameter init_value = 'b0; input [d_width-1:0] d; input rst, en, ce, clk; output [d_width-1:0] q; wire internal_clr, internal_ce; assign internal_clr = rst & ce; assign internal_ce = ce & en; synth_reg_w_init #(.width(d_width), .init_index(2), .init_value(init_value), .latency(1)) synth_reg_inst(.i(d), .ce(internal_ce), .clr(internal_clr), .clk(clk), .o(q)); endmodule module sysgen_relational_0c5dbda85b ( input [(8 - 1):0] a, input [(8 - 1):0] b, output [(1 - 1):0] op, input clk, input ce, input clr); wire [(8 - 1):0] a_1_31; wire [(8 - 1):0] b_1_34; localparam [(1 - 1):0] const_value = 1'b1; wire result_12_3_rel; assign a_1_31 = a; assign b_1_34 = b; assign result_12_3_rel = a_1_31 == b_1_34; assign op = result_12_3_rel; endmodule module sysgen_constant_61a644b4c8 ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b01011111010111100001000000000000; endmodule module sysgen_accum_ac23432ab2 ( input [(32 - 1):0] b, input [(1 - 1):0] rst, input [(1 - 1):0] en, output [(32 - 1):0] q, input clk, input ce, input clr); wire signed [(32 - 1):0] b_17_24; wire rst_17_27; wire en_17_32; reg signed [(32 - 1):0] accum_reg_41_23 = 32'b00000000000000000000000000000000; wire accum_reg_41_23_rst; wire accum_reg_41_23_en; localparam [(1 - 1):0] const_value = 1'b0; localparam [(1 - 1):0] const_value_x_000000 = 1'b1; localparam [(1 - 1):0] const_value_x_000001 = 1'b0; localparam [(1 - 1):0] const_value_x_000002 = 1'b1; reg signed [(33 - 1):0] accum_reg_join_47_1; reg accum_reg_join_47_1_en; reg accum_reg_join_47_1_rst; assign b_17_24 = b; assign rst_17_27 = rst; assign en_17_32 = en; always @(posedge clk) begin:proc_accum_reg_41_23 if (((ce == 1'b1) && (accum_reg_41_23_rst == 1'b1))) begin accum_reg_41_23 <= 32'b00000000000000000000000000000000; end else if (((ce == 1'b1) && (accum_reg_41_23_en == 1'b1))) begin accum_reg_41_23 <= accum_reg_41_23 + b_17_24; end end always @(accum_reg_41_23 or b_17_24 or en_17_32 or rst_17_27) begin:proc_if_47_1 if (rst_17_27) begin accum_reg_join_47_1_rst = 1'b1; end else if (en_17_32) begin accum_reg_join_47_1_rst = 1'b0; end else begin accum_reg_join_47_1_rst = 1'b0; end if (en_17_32) begin accum_reg_join_47_1_en = 1'b1; end else begin accum_reg_join_47_1_en = 1'b0; end end assign accum_reg_41_23_rst = accum_reg_join_47_1_rst; assign accum_reg_41_23_en = accum_reg_join_47_1_en; assign q = accum_reg_41_23; endmodule module sysgen_constant_b4741603e8 ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b00000111111111110000000000000000; endmodule module sysgen_constant_a7c2a996dd ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b00000000000000000000000000000000; endmodule module sysgen_constant_bd840882a6 ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b00000100100000000000000000000000; endmodule module sysgen_logical_0c47d61908 ( input [(1 - 1):0] d0, input [(1 - 1):0] d1, output [(1 - 1):0] y, input clk, input ce, input clr); wire d0_1_24; wire d1_1_27; wire bit_2_27; wire fully_2_1_bitnot; assign d0_1_24 = d0; assign d1_1_27 = d1; assign bit_2_27 = d0_1_24 & d1_1_27; assign fully_2_1_bitnot = ~bit_2_27; assign y = fully_2_1_bitnot; endmodule module sysgen_logical_7913ccf482 ( input [(1 - 1):0] d0, input [(1 - 1):0] d1, input [(1 - 1):0] d2, output [(1 - 1):0] y, input clk, input ce, input clr); wire d0_1_24; wire d1_1_27; wire d2_1_30; wire fully_2_1_bit; assign d0_1_24 = d0; assign d1_1_27 = d1; assign d2_1_30 = d2; assign fully_2_1_bit = d0_1_24 & d1_1_27 & d2_1_30; assign y = fully_2_1_bit; endmodule module sysgen_relational_56046aa836 ( input [(32 - 1):0] a, input [(32 - 1):0] b, output [(1 - 1):0] op, input clk, input ce, input clr); wire signed [(32 - 1):0] a_1_31; wire signed [(32 - 1):0] b_1_34; localparam [(1 - 1):0] const_value = 1'b1; wire result_18_3_rel; assign a_1_31 = a; assign b_1_34 = b; assign result_18_3_rel = a_1_31 > b_1_34; assign op = result_18_3_rel; endmodule module sysgen_relational_860373682b ( input [(32 - 1):0] a, input [(32 - 1):0] b, output [(1 - 1):0] op, input clk, input ce, input clr); wire signed [(32 - 1):0] a_1_31; wire signed [(32 - 1):0] b_1_34; localparam [(1 - 1):0] const_value = 1'b1; wire result_16_3_rel; assign a_1_31 = a; assign b_1_34 = b; assign result_16_3_rel = a_1_31 < b_1_34; assign op = result_16_3_rel; endmodule module xladdsub_ip_pid_controller (a, b, c_in, ce, clr, clk, rst, en, c_out, s); parameter core_name0= ""; parameter a_width= 16; parameter signed a_bin_pt= 4; parameter a_arith= `xlUnsigned; parameter c_in_width= 16; parameter c_in_bin_pt= 4; parameter c_in_arith= `xlUnsigned; parameter c_out_width= 16; parameter c_out_bin_pt= 4; parameter c_out_arith= `xlUnsigned; parameter b_width= 8; parameter signed b_bin_pt= 2; parameter b_arith= `xlUnsigned; parameter s_width= 17; parameter s_bin_pt= 4; parameter s_arith= `xlUnsigned; parameter rst_width= 1; parameter rst_bin_pt= 0; parameter rst_arith= `xlUnsigned; parameter en_width= 1; parameter en_bin_pt= 0; parameter en_arith= `xlUnsigned; parameter full_s_width= 17; parameter full_s_arith= `xlUnsigned; parameter mode= `xlAddMode; parameter extra_registers= 0; parameter latency= 0; parameter quantization= `xlTruncate; parameter overflow= `xlWrap; parameter c_a_width= 16; parameter c_b_width= 8; parameter c_a_type= 1; parameter c_b_type= 1; parameter c_has_sclr= 0; parameter c_has_ce= 0; parameter c_latency= 0; parameter c_output_width= 17; parameter c_enable_rlocs= 1; parameter c_has_c_in= 0; parameter c_has_c_out= 0; input [a_width-1:0] a; input [b_width-1:0] b; input c_in, ce, clr, clk, rst, en; output c_out; output [s_width-1:0] s; parameter full_a_width = full_s_width; parameter full_b_width = full_s_width; parameter full_s_bin_pt = (a_bin_pt > b_bin_pt) ? a_bin_pt : b_bin_pt; wire [full_a_width-1:0] full_a; wire [full_b_width-1:0] full_b; wire [full_s_width-1:0] full_s; wire [full_s_width-1:0] core_s; wire [s_width-1:0] conv_s; wire temp_cout; wire real_a,real_b,real_s; wire internal_clr; wire internal_ce; wire extra_reg_ce; wire override; wire logic1; wire temp_cin; assign internal_clr = (clr \| rst) & ce; assign internal_ce = ce & en; assign logic1 = 1'b1; assign temp_cin = (c_has_c_in) ? c_in : 1'b0; align_input # (a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width) align_inp_a(.inp(a),.res(full_a)); align_input # (b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width) align_inp_b(.inp(b),.res(full_b)); convert_type # (full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow) conv_typ_s(.inp(core_s),.res(conv_s)); generate if (core_name0 == "ip_pid_controller_c_addsub_v12_0_0") begin:comp0 ip_pid_controller_c_addsub_v12_0_0 core_instance0 ( .A(full_a), .S(core_s), .B(full_b) ); end if (core_name0 == "ip_pid_controller_c_addsub_v12_0_1") begin:comp1 ip_pid_controller_c_addsub_v12_0_1 core_instance1 ( .A(full_a), .S(core_s), .B(full_b) ); end endgenerate generate if (extra_registers > 0) begin:latency_test if (c_latency > 1) begin:override_test synth_reg # (1, c_latency) override_pipe ( .i(logic1), .ce(internal_ce), .clr(internal_clr), .clk(clk), .o(override)); assign extra_reg_ce = ce & en & override; end // override_test if ((c_latency == 0) \|\| (c_latency == 1)) begin:no_override assign extra_reg_ce = ce & en; end // no_override synth_reg # (s_width, extra_registers) extra_reg ( .i(conv_s), .ce(extra_reg_ce), .clr(internal_clr), .clk(clk), .o(s)); if (c_has_c_out == 1) begin:cout_test synth_reg # (1, extra_registers) c_out_extra_reg ( .i(temp_cout), .ce(extra_reg_ce), .clr(internal_clr), .clk(clk), .o(c_out)); end // cout_test end // latency_test endgenerate generate if ((latency == 0) \|\| (extra_registers == 0)) begin:latency_s assign s = conv_s; end // latency_s endgenerate generate if (((latency == 0) \|\| (extra_registers == 0)) && (c_has_c_out == 1)) begin:latency0 assign c_out = temp_cout; end // latency0 endgenerate generate if (c_has_c_out == 0) begin:tie_dangling_cout assign c_out = 0; end // tie_dangling_cout endgenerate endmodule module xlcounter_limit_ip_pid_controller (ce, clr, clk, op, up, en, rst); parameter core_name0= ""; parameter op_width= 5; parameter op_arith= `xlSigned; parameter cnt_63_48 = 0; parameter cnt_47_32 = 0; parameter cnt_31_16 = 0; parameter cnt_15_0 = 0; parameter count_limited= 0; input ce, clr, clk; input rst, en; input up; output [op_width-1:0] op; parameter [63:0] cnt_to = { cnt_63_48[15:0], cnt_47_32[15:0], cnt_31_16[15:0], cnt_15_0[15:0]}; parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}}; reg op_thresh0; wire core_sinit, core_ce; wire rst_overrides_en; wire [op_width-1:0] op_net; assign op = op_net; assign core_ce = ce & en; assign rst_overrides_en = rst \| en; generate if (count_limited == 1) begin :limit always @(op_net) begin:eq_cnt_to op_thresh0 = (op_net == cnt_to[op_width-1:0])? 1'b1 : 1'b0; end assign core_sinit = (op_thresh0 \| clr \| rst) & ce & rst_overrides_en; end if (count_limited == 0) begin :no_limit assign core_sinit = (clr \| rst) & ce & rst_overrides_en; end if (core_name0 == "ip_pid_controller_c_counter_binary_v12_0_0") begin:comp0 ip_pid_controller_c_counter_binary_v12_0_0 core_instance0 ( .CLK(clk), .CE(core_ce), .SINIT(core_sinit), .Q(op_net) ); end endgenerate endmodule module xldivider_generator_c21cb25008addda87fe275acdfb605e1 (a,a_tvalid,b,b_tvalid,ce,clk,op); input[31:0] a; input a_tvalid; input[31:0] b; input b_tvalid; input ce; input clk; output[37:0] op; wire[39:0] m_axis_dout_tdata_net; wire[37:0] m_axis_dout_tdata_shift_in_net; wire[37:0] m_axis_dout_tdata_shift_out_net; wire result_tvalid; wire[31:0] s_axis_dividend_tdata_net; wire[31:0] s_axis_divisor_tdata_net; assign m_axis_dout_tdata_shift_in_net = m_axis_dout_tdata_net[37 : 0]; assign op = m_axis_dout_tdata_shift_out_net; assign s_axis_dividend_tdata_net[31 : 0] = a; assign s_axis_divisor_tdata_net[31 : 0] = b; shift_op # ( .inp_width(38), .result_width(38), .shift_value(6), .shift_dir(0)) shift_op_m_axis_dout_tdata_shift_in_net(.inp(m_axis_dout_tdata_shift_in_net), .res(m_axis_dout_tdata_shift_out_net)); ip_pid_controller_div_gen_v5_1_0 ip_pid_controller_div_gen_v5_1_0_instance( .aclk(clk), .m_axis_dout_tdata(m_axis_dout_tdata_net), .m_axis_dout_tvalid(result_tvalid), .s_axis_dividend_tdata(s_axis_dividend_tdata_net), .s_axis_dividend_tvalid(a_tvalid), .s_axis_divisor_tdata(s_axis_divisor_tdata_net), .s_axis_divisor_tvalid(b_tvalid) ); endmodule module xlmult_ip_pid_controller (a, b, ce, clr, clk, core_ce, core_clr,core_clk, rst, en,p); parameter core_name0 = ""; parameter a_width = 4; parameter a_bin_pt = 2; parameter a_arith = `xlSigned; parameter b_width = 4; parameter b_bin_pt = 1; parameter b_arith = `xlSigned; parameter p_width = 8; parameter p_bin_pt = 2; parameter p_arith = `xlSigned; parameter rst_width = 1; parameter rst_bin_pt = 0; parameter rst_arith = `xlUnsigned; parameter en_width = 1; parameter en_bin_pt = 0; parameter en_arith = `xlUnsigned; parameter quantization = `xlTruncate; parameter overflow = `xlWrap; parameter extra_registers = 0; parameter c_a_width = 7; parameter c_b_width = 7; parameter c_type = 0; parameter c_a_type = 0; parameter c_b_type = 0; parameter c_baat = 4; parameter oversample = 1; parameter multsign = `xlSigned; parameter c_output_width = 16; input [a_width - 1 : 0] a; input [b_width - 1 : 0] b; input ce, clr, clk; input core_ce, core_clr, core_clk; input en, rst; output [p_width - 1 : 0] p; wire [c_a_width - 1 : 0] tmp_a, conv_a; wire [c_b_width - 1 : 0] tmp_b, conv_b; wire [c_output_width - 1 : 0] tmp_p; wire [p_width - 1 : 0] conv_p; wire internal_ce, internal_clr, internal_core_ce; wire rfd, rdy, nd; assign internal_ce = ce & en; assign internal_core_ce = core_ce & en; assign internal_clr = (clr \| rst) & en; assign nd = ce & en; zero_ext # (a_width, c_a_width) zero_ext_a (.inp(a), .res(tmp_a)); zero_ext # (b_width, c_b_width) zero_ext_b (.inp(b), .res(tmp_b)); //Output Process convert_type # (c_output_width, a_bin_pt+b_bin_pt, multsign, p_width, p_bin_pt, p_arith, quantization, overflow) conv_udp (.inp(tmp_p), .res(conv_p)); generate if (core_name0 == "ip_pid_controller_mult_gen_v12_0_0") begin:comp0 ip_pid_controller_mult_gen_v12_0_0 core_instance0 ( .A(tmp_a), .B(tmp_b), .CLK(clk), .CE(internal_ce), .SCLR(internal_clr), .P(tmp_p) ); end if (extra_registers > 0) begin:latency_gt_0 synth_reg # (p_width, extra_registers) reg1 ( .i(conv_p), .ce(internal_ce), .clr(internal_clr), .clk(clk), .o(p)); end if (extra_registers == 0) begin:latency_eq_0 assign p = conv_p; end endgenerate endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Wilson Snyder. module t; integer p_i; reg [78:1] p_str; initial begin if ($test$plusargs("PLUS")!==1) $stop; if ($test$plusargs("PLUSNOT")!==0) $stop; if ($test$plusargs("PL")!==1) $stop; //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer if ($test$plusargs("NOTTHERE")!==0) $stop; p_i = 10; if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop; if (p_i !== 10) $stop; if ($value$plusargs("INT=%d", p_i)!==1) $stop; if (p_i !== 32'd1234) $stop; if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also if (p_i !== 32'h1234) $stop; if ($value$plusargs("INT=%o", p_i)!==1) $stop; if (p_i !== 32'o1234) $stop; if ($value$plusargs("IN%s", p_str)!==1) $stop; $display("str='%s'",p_str); if (p_str !== "T=1234") $stop; $write("-* All Finished -\n"); $finish; end endmodule
//----------------------------------------------------------------------------- // File : avalon_st_gen.v // Author : Altera Corporation //----------------------------------------------------------------------------- // Copyright 2008 Altera Corporation. All rights reserved. Altera products are // protected under numerous U.S. and foreign patents, maskwork rights, copyrights and // other intellectual property laws. // This reference design file, and your use thereof, is subject to and governed by // the terms and conditions of the applicable Altera Reference Design License Agreement. // By using this reference design file, you indicate your acceptance of such terms and // conditions between you and Altera Corporation. In the event that you do not agree with // such terms and conditions, you may not use the reference design file. Please promptly // destroy any copies you have made. // // This reference design file being provided on an "as-is" basis and as an accommodation // and therefore all warranties, representations or guarantees of any kind // (whether express, implied or statutory) including, without limitation, warranties of // merchantability, non-infringement, or fitness for a particular purpose, are // specifically disclaimed. By making this reference design file available, Altera // expressly does not recommend, suggest or require that this reference design file be // used in combination with any other product not provided by Altera // turn off bogus verilog processor warnings // altera message_off 10034 10035 10036 10037 10230 module avalon_st_gen ( input clk // TX FIFO Interface clock ,input reset // Reset signal ,input [7:0] address // Register Address ,input write // Register Write Strobe ,input read // Register Read Strobe ,output wire waitrequest ,input [31:0] writedata // Register Write Data ,output reg [31:0] readdata // Register Read Data ,input tx_ready // Avalon-ST Ready Input ,output reg [63:0] tx_data // Avalon-ST TX Data ,output reg tx_valid // Avalon-ST TX Valid ,output reg tx_sop // Avalon-ST TX StartOfPacket ,output reg tx_eop // Avalon-ST TX EndOfPacket ,output reg [2:0] tx_empty // Avalon-ST TX Empty ,output wire tx_error // Avalon-ST TX Error ); // ___________________________________________________________ // address parameters // ___________________________________________________________ parameter ADDR_NUMPKTS = 8'h0; parameter ADDR_RANDOMLENGTH = 8'h1; parameter ADDR_RANDOMPAYLOAD = 8'h2; parameter ADDR_START = 8'h3; parameter ADDR_STOP = 8'h4; parameter ADDR_MACSA0 = 8'h5; parameter ADDR_MACSA1 = 8'h6; parameter ADDR_MACDA0 = 8'h7; parameter ADDR_MACDA1 = 8'h8; parameter ADDR_TXPKTCNT = 8'h9; parameter ADDR_RNDSEED0 = 8'ha; parameter ADDR_RNDSEED1 = 8'hb; parameter ADDR_RNDSEED2 = 8'hc; parameter ADDR_PKTLENGTH = 8'hd; parameter ADDR_CNTDASA = 8'hf0; parameter ADDR_CNTSATLEN = 8'hf1; parameter ADDR_CNTDATA = 8'hf2; parameter ADDR_CNTTRNSTN = 8'hf3; // 10G Ethernet Control Registers reg start_reg; wire start; // Start operation of packet generator reg stop; // Stop operation of packet generator reg [31:0] number_packet; // Register to store number of packets to be transmitted reg [31:0] config_setting; // Register to configure settings: data pattern type, length reg [31:0] source_addr0; // Register to program the MAC source address [31:0] reg [31:0] source_addr1; // Register to program the MAC source address [47:32] reg [31:0] destination_addr0; // Register to program the MAC destination address [31:0] reg [31:0] destination_addr1; // Register to program the MAC destination address [47:32] reg [31:0] packet_tx_count; // Register to count the number of succesfully transmitted packets reg [31:0] rand_seed0; // Register to program seed number for prbs generator [31:0] reg [31:0] rand_seed1; // Register to program seed number for prbs generator [63:32] reg [31:0] rand_seed2; // Register to program seed number for prbs generator [91:64] reg random_payload; // Select what type of data pattern:0=incremental, 1=random reg random_length; // Select what type of packet length:0=fixed, 1=random reg [13:0] pkt_length; // Fixed payload length for every packet wire [7:0] DA5,DA4,DA3,DA2,DA1,DA0; wire [7:0] SA5,SA4,SA3,SA2,SA1,SA0; wire [91:0] random_seed; // Random seed number for PRBS generator wire S_IDLE; wire S_DEST_SRC; wire S_SRC_LEN_SEQ; wire S_DATA; wire S_TRANSITION; reg[31:0] cnt_dasa, cnt_satlen, cnt_data, cnt_trnstn; reg [2:0] ns; reg [2:0] ps; // State machine parameters // -------------------------- localparam state_idle = 3'b000; // Idle State localparam state_dest_src = 3'b001; // Dest(47:0) & Src(47:32) State localparam state_src_len_seq = 3'b010; // Src(31:0) & Length(15:0) & SeqNr(15:0) State localparam state_data = 3'b011; // Data Pattern State localparam state_transition = 3'b100; // Transition State wire [91:0] tx_prbs; reg [15:0] byte_count; reg [63:0] data_pattern; reg [15:0] length; reg [15:0] seq_num; // Avalon-ST signals to CRC generator // ----------------------------------- wire [3:0] empty; reg [63:0] tx_data_reg; reg tx_valid_reg; reg tx_sop_reg; reg tx_eop_reg; reg [2:0] tx_empty_reg; wire crc_valid; wire [31:0] crc; reg [31:0] crc_l1; reg [31:0] crc_l2; reg [31:0] crc_l3; reg [31:0] crc_l4; reg [2:0] crc_valid_count; wire [31:0] checksum; wire [63:0] tx_data_out; wire [5:0] tx_ctrl_out; reg add_extra_qword; reg valid_extended; reg eop_extended; reg [2:0] empty_extended; // ____________________________________________________________________________ // number packet register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) number_packet <= 32'h0; else if (write & address == ADDR_NUMPKTS) number_packet <= writedata; end // ____________________________________________________________________________ // packet length setting register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) pkt_length <= 14'd0; else if (write & address == ADDR_PKTLENGTH) pkt_length[13:0] <= writedata[13:0]; end // ____________________________________________________________________________ // payload pattern setting register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) random_payload <= 1'h0; else if (write & address == ADDR_RANDOMPAYLOAD) random_payload <= writedata[0]; end // ____________________________________________________________________________ // packet length type (fixed or random) setting register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) random_length <= 1'h0; else if (write & address == ADDR_RANDOMLENGTH) random_length <= writedata[0]; end // ____________________________________________________________________________ // start register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) start_reg <= 1'h0; else if (write & address == ADDR_START) start_reg <= writedata[0]; else if (start_reg) start_reg <= 1'b0; // clear itself end // used for edge detection because start_reg[0] assertion maybe > 1 clk long reg start_d; always @ (posedge reset or posedge clk) begin if (reset) start_d<= 1'd0; else start_d<= start_reg; end assign start = start_reg & ~start_d; // ____________________________________________________________________________ // stop register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) stop <= 1'h0; else if (write & address == ADDR_STOP) stop <= writedata[0]; end // ____________________________________________________________________________ // MAC source_addr0 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) source_addr0 <= 32'h0; else if (write & address == ADDR_MACSA0) source_addr0 <= writedata; end // ____________________________________________________________________________ // MAC dest_addr1 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) source_addr1 <= 32'h0; else if (write & address == ADDR_MACSA1) source_addr1[15:0] <= writedata[15:0]; end // ____________________________________________________________________________ // MAC dest_addr0 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) destination_addr0 <= 32'h0; else if (write & address == ADDR_MACDA0) destination_addr0 <= writedata; end // ____________________________________________________________________________ // MAC dest_addr1 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) destination_addr1 <= 32'h0; else if (write & address == ADDR_MACDA1) destination_addr1[15:0] <= writedata[15:0]; end assign {DA5,DA4,DA3,DA2,DA1,DA0} = {destination_addr1[15:0], destination_addr0[31:0]}; assign {SA5,SA4,SA3,SA2,SA1,SA0} = {source_addr1[15:0], source_addr0[31:0]}; // ____________________________________________________________________________ // packet_tx_count register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin packet_tx_count <= 32'h0; end else begin if (start) begin packet_tx_count <= 32'h0; end else if (tx_ready & S_SRC_LEN_SEQ) begin packet_tx_count <= packet_tx_count + 32'h1; end end end // ____________________________________________________________________________ // rand_seed0 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin // rand_seed0 <= 32'h0; // initialize with non zero seed so that // prbs works even when no random seed is // provided by the user - ajay dubey rand_seed0 <= 32'h5EED_0000; end else begin if (write & address == ADDR_RNDSEED0) begin rand_seed0 <= writedata; end end end // ____________________________________________________________________________ // rand_seed1 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin // rand_seed1 <= 32'h0; // initialize with non zero seed so that // prbs works even when no random seed is // provided by the user - ajay dubey rand_seed1 <= 32'h5EED_0001; end else begin if (write & address == ADDR_RNDSEED1) begin rand_seed1 <= writedata; end end end // ____________________________________________________________________________ // rand_seed2 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin //rand_seed2 <= 32'h0; // initialize with non zero seed so that // prbs works even when no random seed is // provided by the user - ajay dubey rand_seed2 <= 32'h0002_5EED; end else begin if (write & address == ADDR_RNDSEED2) begin rand_seed2[27:0] <= {5'd0,writedata[27:0]}; end end end assign random_seed = {rand_seed2[27:0], rand_seed1[31:0], rand_seed0[31:0]}; // Output MUX of registers into readdata bus always@(posedge clk or posedge reset) begin if(reset) readdata <= 32'h0; else if (read) begin case (address) ADDR_NUMPKTS: readdata <= number_packet; ADDR_RANDOMLENGTH: readdata <= random_length; ADDR_RANDOMPAYLOAD: readdata <= random_payload; ADDR_START: readdata <= start; ADDR_STOP: readdata <= stop; ADDR_MACSA0: readdata <= source_addr0; ADDR_MACSA1: readdata <= source_addr1; ADDR_MACDA0: readdata <= destination_addr0; ADDR_MACDA1: readdata <= destination_addr1; ADDR_TXPKTCNT: readdata <= packet_tx_count; ADDR_RNDSEED0: readdata <= rand_seed0; ADDR_RNDSEED1: readdata <= rand_seed1; ADDR_RNDSEED2: readdata <= rand_seed2; ADDR_CNTDASA: readdata <= cnt_dasa; ADDR_CNTSATLEN: readdata <= cnt_satlen; ADDR_CNTDATA: readdata <= cnt_data; ADDR_CNTTRNSTN: readdata <= cnt_trnstn; default: readdata <=32'h0; endcase end end // ____________________________________________________________ // reg rddly, wrdly; always@(posedge clk or posedge reset) begin if(reset) begin wrdly <= 1'b0; rddly <= 1'b0; end else begin wrdly <= write; rddly <= read; end end wire wredge = write& ~wrdly; wire rdedge = read & ~rddly; assign waitrequest = (wredge\|rdedge); // your design is done with transaction when this goes down // __________________________________________________________________________________ // PRBS Pattern Generator // -------------------------------- prbs23 prbs_tx0 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ \| S_DATA)), .seed (random_seed[22:0]), .d (tx_prbs[22:0]), .m (tx_prbs[22:0]) ); prbs23 prbs_tx1 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ \| S_DATA)), .seed (random_seed[45:23]), .d (tx_prbs[45:23]), .m (tx_prbs[45:23]) ); prbs23 prbs_tx2 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ \| S_DATA)), .seed (random_seed[68:46]), .d (tx_prbs[68:46]), .m (tx_prbs[68:46]) ); prbs23 prbs_tx3 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ \| S_DATA)), .seed (random_seed[91:69]), .d (tx_prbs[91:69]), .m (tx_prbs[91:69]) ); // FSM State Machine for Generator // -------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin ps <= state_idle; end else begin if (start) begin ps <= state_dest_src; end else begin ps <= ns; end end end always @ () begin ns = ps; case (ps) state_idle:begin if (start) begin ns = state_dest_src; end end state_dest_src:begin if (tx_ready) begin ns = state_src_len_seq; end end state_src_len_seq:begin if (tx_ready & (length == 16'h0)) begin ns = state_transition; end else if (tx_ready) begin ns = state_data; end end state_data:begin if (tx_ready & (byte_count[15] \| byte_count == 16'h0)) begin ns = state_transition; end end state_transition:begin if (stop \| packet_tx_count == number_packet) begin ns = state_idle; end else if (tx_ready) begin ns = state_dest_src; end end default: ns = state_idle; endcase end assign S_IDLE = (ns == state_idle) ? 1'b1 : 1'b0; assign S_DEST_SRC = (ns == state_dest_src) ? 1'b1 : 1'b0; assign S_SRC_LEN_SEQ = (ns == state_src_len_seq) ? 1'b1 : 1'b0; assign S_DATA = (ns == state_data) ? 1'b1 : 1'b0; assign S_TRANSITION = (ns == state_transition) ? 1'b1 : 1'b0; // Length is used to store the payload length size. Payload length smaller than 46 will have zeros data padded // Allowable fixed payload length: 6 -> 9582 // Allowable random payload length: 6 -> 1500 // -------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin length <= 16'h0; end else begin if (S_IDLE \| S_TRANSITION) begin if (~random_length & (pkt_length < 14'h0018)) begin length <= 16'h0; end else if (~random_length & (pkt_length > 14'h2580)) begin length <= 16'h2568; end else if (~random_length) begin length <= {2'b00, pkt_length - 14'h18}; end else if (random_length) begin length <= (tx_prbs[74:64] % 16'h05D7); end end end end // Byte_count is used to keep track of how many bytes of data payload being generated out // -------------------------------------------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin byte_count <= 16'h0; end else begin if (S_DEST_SRC) begin byte_count <= length; end else if (S_DATA & tx_ready) begin byte_count <= byte_count - 16'h8; end end end // Seq_num is inserted into the first 2 bytes of data payload of every packet // --------------------------------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin seq_num <= 16'h0; end else begin if (start) begin seq_num <= 16'h0; end else if (S_TRANSITION & tx_ready) begin seq_num <= seq_num + 16'h1; end end end // Generation of incremental data or pseudo random data // ----------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin data_pattern <= 64'h0; end else begin if (S_IDLE & ~random_payload) begin data_pattern <= 64'h0001020304050607; end else if (S_DATA & ~random_payload & tx_ready & data_pattern == 64'hF8F9FAFBFCFDFEFF) begin data_pattern <= 64'h0001020304050607; end else if (S_DATA & ~random_payload & tx_ready) begin data_pattern <= data_pattern + 64'h0808080808080808; end else if ((S_SRC_LEN_SEQ \| S_DATA) & random_payload & tx_ready) begin data_pattern <= tx_prbs[63:0]; end end end // Avalon-ST tx_data interface to CRC generator // --------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_data_reg <= 64'h0; end else begin if (S_DEST_SRC) begin tx_data_reg[63:32] <= {DA5,DA4,DA3,DA2}; tx_data_reg[31: 0] <= {DA1,DA0,SA5,SA4}; end else if (S_SRC_LEN_SEQ) begin tx_data_reg[63:32] <= {SA3,SA2,SA1,SA0}; tx_data_reg[31: 0] <= {length + 16'h6, seq_num}; end else if (S_DATA & tx_ready) begin tx_data_reg <= data_pattern; end end end // Avalon-ST tx_valid interface to CRC generator // ---------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_valid_reg <= 1'b0; end else begin if (S_IDLE \| S_TRANSITION) begin tx_valid_reg <= 1'b0; end else begin tx_valid_reg <= 1'b1; end end end // Avalon-ST tx_sop interface to CRC generator // -------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_sop_reg <= 1'b0; end else begin if (S_DEST_SRC) begin tx_sop_reg <= 1'b1; end else begin tx_sop_reg <= 1'b0; end end end // Avalon-ST tx_eop interface to CRC generator // -------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_eop_reg <= 1'b0; end else begin if (S_SRC_LEN_SEQ & (length == 0)) begin tx_eop_reg <= 1'b1; end else if (S_DATA & tx_ready & (byte_count <= 8)) begin tx_eop_reg <= 1'b1; end else if (S_TRANSITION) begin tx_eop_reg <= 1'b0; end end end // Avalon-ST tx_empty interface to CRC generator // ---------------------------------------------- assign empty = 4'h8 - length[2:0]; always @ (posedge reset or posedge clk) begin if (reset) begin tx_empty_reg <= 3'b000; end else begin if (S_DATA & tx_ready & (byte_count <= 8)) begin tx_empty_reg <= empty[2:0]; end else if (S_TRANSITION) begin tx_empty_reg <= 3'b000; end end end // Using CRC Compiler to generate checksum and append it to EOP // ------------------------------------------------------------- / crcgen crcgen_inst ( .clk (clk), .data (tx_data_reg), .datavalid (tx_valid_reg & tx_ready), .empty (tx_empty_reg), .endofpacket (tx_eop_reg), .reset_n (~reset), .startofpacket (tx_sop_reg), .checksum (crc), .crcvalid (crc_valid) ); / // Using RAM based shift register to delay packet payload sending to TSE TX FIFO // interface for CRC checksum merging at EOP // ------------------------------------------------------------------------------- shiftreg_data shiftreg_data_inst ( .aclr (reset), .clken (tx_ready), .clock (clk), .shiftin (tx_data_reg), .shiftout (tx_data_out), .taps () ); // Using RAM based shift register to store and delay control signals // ------------------------------------------------------------------ shiftreg_ctrl shiftreg_ctrl_inst ( .aclr (reset), .clken (tx_ready), .clock (clk), .shiftin ({tx_valid_reg, tx_sop_reg, tx_eop_reg, tx_empty_reg}), .shiftout (tx_ctrl_out), .taps () ); always @ (posedge reset or posedge clk) begin if (reset) begin crc_valid_count <= 2'b00; end else begin crc_valid_count <= crc_valid_count + (crc_valid) - (tx_ready & tx_eop); end end always @ (posedge reset or posedge clk) begin if (reset) begin crc_l1 <= 32'h0; crc_l2 <= 32'h0; end else begin if (crc_valid) begin crc_l1 <= crc; crc_l2 <= crc_l1; crc_l3 <= crc_l2; crc_l4 <= crc_l3; end end end assign checksum = (crc_valid_count == 3'b001) ? crc_l1 : (crc_valid_count == 3'b010) ? crc_l2 : (crc_valid_count == 3'b011) ? crc_l3 : (crc_valid_count == 3'b100) ? crc_l4 : 32'h0; // Extend packet by one cycle when not enough // space in last word to add in checksum // ------------------------------------------- always @ () begin add_extra_qword <= 1'b0; if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop if (tx_ctrl_out[2] == 1'b0) begin // Less than 4 empty bytes add_extra_qword <= 1'b1; end end end always @ (posedge reset or posedge clk) begin if (reset) begin valid_extended <= 1'b0; eop_extended <= 1'b0; empty_extended <= 3'b000; end else begin if (tx_ready) begin if (add_extra_qword) begin valid_extended <= 1'b1; eop_extended <= 1'b1; empty_extended[2] <= 1'b1; empty_extended[1:0] <= tx_ctrl_out[1:0]; end else begin valid_extended <= 1'b0; eop_extended <= 1'b0; empty_extended[2] <= 1'b0; empty_extended[1:0] <= 3'b000; end end end end always @ (posedge reset or posedge clk) begin if (reset) begin tx_valid <= 1'b0; tx_sop <= 1'b0; tx_eop <= 1'b0; tx_empty <= 1'b0; end else begin if (tx_ready) begin tx_valid <= tx_ctrl_out[5] \| valid_extended; end else begin //tx_valid <= 1'b0 ; tx_valid <= tx_valid ; // ajay: remain unchanged end if (tx_ready) begin //tx_valid <= tx_ctrl_out[5] \| valid_extended; // ajay: unnecessary: already defined above tx_sop <= tx_ctrl_out[4]; if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop tx_eop <= !add_extra_qword; // keep original end else begin tx_eop <= eop_extended; end if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop if (add_extra_qword) begin tx_empty <= 3'b000; end else begin tx_empty <= tx_ctrl_out[2:0] - 3'h4; end end else begin tx_empty <= empty_extended[2:0]; end end end end always @ (posedge reset or posedge clk) begin if (reset) begin tx_data <= 64'h0; end else begin if (tx_ready) begin tx_data <= tx_data_out; // By default if (tx_ctrl_out[3]) begin // Normal EOP field case (tx_ctrl_out[2:0]) 3'b000: tx_data <= tx_data_out[63:0]; 3'b001: tx_data <= {tx_data_out[63:8], checksum[31:24]}; 3'b010: tx_data <= {tx_data_out[63:16], checksum[31:16]}; 3'b011: tx_data <= {tx_data_out[63:24], checksum[31: 8]}; 3'b100: tx_data <= {tx_data_out[63:32], checksum[31: 0]}; 3'b101: tx_data <= {tx_data_out[63:40], checksum[31: 0], 8'h0}; 3'b110: tx_data <= {tx_data_out[63:48], checksum[31: 0], 16'h0}; 3'b111: tx_data <= {tx_data_out[63:56], checksum[31: 0], 24'h0}; default: tx_data <= tx_data_out; endcase end else if (eop_extended) begin case (empty_extended) 3'b100: tx_data <= {checksum[31:0], 32'h0}; 3'b101: tx_data <= {checksum[23:0], 40'h0}; 3'b110: tx_data <= {checksum[15:0], 48'h0}; 3'b111: tx_data <= {checksum[ 7:0], 56'h0}; default: tx_data <= 64'h0; endcase end end end end assign tx_error = 1'b0; // ___________________________________________________________________________________________ // Debug Logic // ___________________________________________________________________________________________ reg ppln_dasa, ppln_satlen, ppln_data, ppln_trnstn; always @ (posedge reset or posedge clk) begin if (reset) begin ppln_dasa <= 1'b0; ppln_satlen <= 1'b0; ppln_data <= 1'b0; ppln_trnstn <= 1'b0; end else begin ppln_dasa <= S_DEST_SRC; ppln_satlen <= S_SRC_LEN_SEQ; ppln_data <= S_DATA; ppln_trnstn <= S_TRANSITION; end end wire ena_dasa = S_DEST_SRC & ~ppln_dasa; wire ena_satlen = S_SRC_LEN_SEQ & ~ppln_satlen; wire ena_data = S_DATA & ~ppln_data; wire ena_trnstn = S_TRANSITION & ~ppln_trnstn; always @ (posedge reset or posedge clk) begin if (reset) begin cnt_dasa <= 32'd0; cnt_satlen <= 32'd0; cnt_data <= 32'd0; cnt_trnstn <= 32'd0; end else begin if (ena_dasa) cnt_dasa <= cnt_dasa + 32'd1; if (ena_satlen) cnt_satlen <= cnt_satlen + 32'd1; if (ena_data) cnt_data <= cnt_data + 32'd1; if (ena_trnstn) cnt_trnstn <= cnt_trnstn + 32'd1; end end endmodule // ___________________________________________________________________________________________________ // PRBS23 GENERATOR // ___________________________________________________________________________________________________ //----------------------------------------------------------------------------- // Functional Description: // This module is the Pseudo-Random Bit Sequence 23 Block // where g(x) = x^23 + x^18 + x^0 // // use lsb of m 1st first // k can be > N, but part of the sequence will be skipped // //------------------------------------------------------------------------------- // // Copyright 2007 Altera Corporation. All rights reserved. Altera products are // protected under numerous U.S. and foreign patents, maskwork rights, copyrights and // other intellectual property laws. // This reference design file, and your use thereof, is subject to and governed by // the terms and conditions of the applicable Altera Reference Design License Agreement. // By using this reference design file, you indicate your acceptance of such terms and // conditions between you and Altera Corporation. In the event that you do not agree with // such terms and conditions, you may not use the reference design file. Please promptly // destroy any copies you have made. // // This reference design file being provided on an "as-is" basis and as an accommodation // and therefore all warranties, representations or guarantees of any kind // (whether express, implied or statutory) including, without limitation, warranties of // merchantability, non-infringement, or fitness for a particular purpose, are // specifically disclaimed. By making this reference design file available, Altera // expressly does not recommend, suggest or require that this reference design file be // used in combination with any other product not provided by Altera // turn off bogus verilog processor warnings // altera message_off 10034 10035 10036 10037 10230 module prbs23 ( clk, rst_n, load, enable, seed, d, m); parameter k = 23; //step value = a^k parameter N = 23; input clk; input rst_n; input load; input enable; input [N-1:0] seed; input [N-1:0] d; output [N-1:0] m; reg [N-1:0] m; reg [N-1:0] tmpa; reg [N-1:0] tmpb; integer i,j; always @ (d) begin tmpa = d; for (i=0; i<k; i=i+1) begin for (j=0; j<(N-1); j=j+1) begin tmpb[j] = tmpa[j+1]; end tmpb[N-1] = tmpa[18] ^ tmpa[0]; //x^23 + x[18] + x[0] tmpa = tmpb; end end always @(posedge clk or negedge rst_n) begin begin if (!rst_n) m <= 0; else if (load) m <= seed; else if (enable) m <= tmpb; end end endmodule
// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: bw_io_ddr_sig_bot.v // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ module bw_io_ddr_sig_bot(dram_io_drive_enable_o_l ,se_o_l ,cbd_o_l , cbu_o_l ,cbu_o_r ,cbd_o_r ,cbd_i_l ,cbu_i_r ,cbd_i_r ,vrefcode_i_l ,vrefcode_i_r ,serial_in ,afo ,serial_out ,ps_select_i_r ,afi , spare_ddr_data ,spare_ddr_pin ,test_mode_i_l ,testmode_l_i_r , test_mode_i_r ,bypass_enable_i_l ,bypass_enable_i_r ,ps_select_i_l ,update_dr_o_l ,shift_dr_o_l ,clock_dr_o_l ,hiz_n_o_l , bypass_enable_o_l ,ps_select_o_r ,mode_ctrl_o_r ,update_dr_o_r , se_i_r ,mode_ctrl_i_r ,clock_dr_i_r ,mode_ctrl_o_l ,hiz_n_i_r , update_dr_i_r ,cbu_i_l ,shift_dr_o_r ,dram_io_drive_enable_i_r , clock_dr_o_r ,hiz_n_o_r ,ps_select_o_l ,rclk ,testmode_l_i_l , dram_io_ptr_clk_inv_i_l ,burst_length_four_i_l , dram_io_pad_enable_i_l ,dram_io_drive_enable_i_l ,rst_l_i_l , arst_l_i_l, arst_l_out, lpf_code_i_l ,strobe_i_l ,pad_pos_cnt_i_l , dram_io_channel_disabled_i_l ,pad_neg_cnt_i_l , dram_io_drive_data_i_l ,dram_io_channel_disabled_i_r , dram_io_write_en_l ,\dram_io_data_out[63] ,\dram_io_data_out[62] , \dram_io_data_out[61] ,\dram_io_data_out[60] ,\dram_io_data_out[59] ,\dram_io_data_out[58] ,\dram_io_data_out[57] , \dram_io_data_out[56] ,\dram_io_data_out[55] ,\dram_io_data_out[54] ,\dram_io_data_out[53] ,\dram_io_data_out[52] , \dram_io_data_out[51] ,\dram_io_data_out[50] ,\dram_io_data_out[49] ,\dram_io_data_out[48] ,\dram_io_data_out[47] , \dram_io_data_out[46] ,\dram_io_data_out[45] ,\dram_io_data_out[44] ,\dram_io_data_out[43] ,\dram_io_data_out[42] , \dram_io_data_out[41] ,\dram_io_data_out[40] ,\dram_io_data_out[39] ,\dram_io_data_out[38] ,\dram_io_data_out[37] , \dram_io_data_out[36] ,\dram_io_data_out[35] ,\dram_io_data_out[34] ,\dram_io_data_out[33] ,\dram_io_data_out[32] , \io_dram_data_in[255] ,\io_dram_data_in[254] ,\io_dram_data_in[253] ,\io_dram_data_in[252] ,\io_dram_data_in[251] , \io_dram_data_in[250] ,\io_dram_data_in[249] ,\io_dram_data_in[248] ,\io_dram_data_in[247] ,\io_dram_data_in[246] , \io_dram_data_in[245] ,\io_dram_data_in[244] ,\io_dram_data_in[243] ,\io_dram_data_in[242] ,\io_dram_data_in[241] , \io_dram_data_in[240] ,\io_dram_data_in[239] ,\io_dram_data_in[238] ,\io_dram_data_in[237] ,\io_dram_data_in[236] , \io_dram_data_in[235] ,\io_dram_data_in[234] ,\io_dram_data_in[233] ,\io_dram_data_in[232] ,\io_dram_data_in[231] , \io_dram_data_in[230] ,\io_dram_data_in[229] ,\io_dram_data_in[228] ,\io_dram_data_in[227] ,\io_dram_data_in[226] , \io_dram_data_in[225] ,\io_dram_data_in[224] ,dram_io_cas_l , dram_cs_l ,dram_we_l ,dram_cas_l ,\dram_dq[127] ,\dram_dq[126] , \dram_dq[125] ,\dram_dq[124] ,\dram_dq[123] ,\dram_dq[122] , \dram_dq[121] ,\dram_dq[120] ,\dram_dq[119] ,\dram_dq[118] , \dram_dq[117] ,\dram_dq[116] ,\dram_dq[115] ,\dram_dq[114] , \dram_dq[113] ,\dram_dq[112] ,\dram_dq[111] ,\dram_dq[110] , \dram_dq[109] ,\dram_dq[108] ,\dram_dq[107] ,\dram_dq[106] , \dram_dq[105] ,\dram_dq[104] ,\dram_dq[103] ,\dram_dq[102] , \dram_dq[101] ,\dram_dq[100] ,\dram_dq[99] ,\dram_dq[98] , \dram_dq[97] ,\dram_dq[96] ,\dram_io_data_out[287] , \dram_io_data_out[286] ,\dram_io_data_out[285] , \dram_io_data_out[284] ,\dram_io_data_out[283] , \dram_io_data_out[282] ,\dram_io_data_out[281] , \dram_io_data_out[280] ,\dram_io_data_out[143] , \dram_io_data_out[142] ,\dram_io_data_out[141] , \dram_io_data_out[140] ,\dram_io_data_out[139] , \dram_io_data_out[138] ,\dram_io_data_out[137] , \dram_io_data_out[136] ,\io_dram_ecc_in[31] ,\io_dram_ecc_in[30] , \io_dram_ecc_in[29] ,\io_dram_ecc_in[28] ,\io_dram_ecc_in[27] , \io_dram_ecc_in[26] ,\io_dram_ecc_in[25] ,\io_dram_ecc_in[24] , \io_dram_ecc_in[15] ,\io_dram_ecc_in[14] ,\io_dram_ecc_in[13] , \io_dram_ecc_in[12] ,\io_dram_ecc_in[11] ,\io_dram_ecc_in[10] , \io_dram_ecc_in[9] ,\io_dram_ecc_in[8] ,dram_cb , \dram_io_data_out[127] ,\dram_io_data_out[126] , \dram_io_data_out[125] ,\dram_io_data_out[124] , \dram_io_data_out[123] ,\dram_io_data_out[122] , \dram_io_data_out[121] ,\dram_io_data_out[120] , \dram_io_data_out[119] ,\dram_io_data_out[118] , \dram_io_data_out[117] ,\dram_io_data_out[116] , \dram_io_data_out[115] ,\dram_io_data_out[114] , \dram_io_data_out[113] ,\dram_io_data_out[112] , \dram_io_data_out[111] ,\dram_io_data_out[110] , \dram_io_data_out[109] ,\dram_io_data_out[108] , \dram_io_data_out[107] ,\dram_io_data_out[106] , \dram_io_data_out[105] ,\dram_io_data_out[104] , \dram_io_data_out[103] ,\dram_io_data_out[102] , \dram_io_data_out[101] ,\dram_io_data_out[100] , \dram_io_data_out[99] ,\dram_io_data_out[98] ,\dram_io_data_out[97] ,\dram_io_data_out[96] ,pad_neg_cnt_i_r ,\io_dram_data_in[191] , \io_dram_data_in[190] ,\io_dram_data_in[189] ,\io_dram_data_in[188] ,\io_dram_data_in[187] ,\io_dram_data_in[186] , \io_dram_data_in[185] ,\io_dram_data_in[184] ,\io_dram_data_in[183] ,\io_dram_data_in[182] ,\io_dram_data_in[181] , \io_dram_data_in[180] ,\io_dram_data_in[179] ,\io_dram_data_in[178] ,\io_dram_data_in[177] ,\io_dram_data_in[176] , \io_dram_data_in[175] ,\io_dram_data_in[174] ,\io_dram_data_in[173] ,\io_dram_data_in[172] ,\io_dram_data_in[171] , \io_dram_data_in[170] ,\io_dram_data_in[169] ,\io_dram_data_in[168] ,\io_dram_data_in[167] ,\io_dram_data_in[166] , \io_dram_data_in[165] ,\io_dram_data_in[164] ,\io_dram_data_in[163] ,\io_dram_data_in[162] ,\io_dram_data_in[161] , \io_dram_data_in[160] ,rst_l_i_r , arst_l_i_r, \io_dram_data_in[127] , \io_dram_data_in[126] ,\io_dram_data_in[125] ,\io_dram_data_in[124] ,\io_dram_data_in[123] ,\io_dram_data_in[122] , \io_dram_data_in[121] ,\io_dram_data_in[120] ,\io_dram_data_in[119] ,\io_dram_data_in[118] ,\io_dram_data_in[117] , \io_dram_data_in[116] ,\io_dram_data_in[115] ,\io_dram_data_in[114] ,\io_dram_data_in[113] ,\io_dram_data_in[112] , \io_dram_data_in[111] ,\io_dram_data_in[110] ,\io_dram_data_in[109] ,\io_dram_data_in[108] ,\io_dram_data_in[107] , \io_dram_data_in[106] ,\io_dram_data_in[105] ,\io_dram_data_in[104] ,\io_dram_data_in[103] ,\io_dram_data_in[102] , \io_dram_data_in[101] ,\io_dram_data_in[100] ,\io_dram_data_in[99] ,\io_dram_data_in[98] ,\io_dram_data_in[97] ,\io_dram_data_in[96] ,pad_clk_si ,dram_ras_l ,dram_io_pad_enable_i_r , \dram_io_data_out[271] ,\dram_io_data_out[270] , \dram_io_data_out[269] ,\dram_io_data_out[268] , \dram_io_data_out[267] ,\dram_io_data_out[266] , \dram_io_data_out[265] ,\dram_io_data_out[264] , \dram_io_data_out[263] ,\dram_io_data_out[262] , \dram_io_data_out[261] ,\dram_io_data_out[260] , \dram_io_data_out[259] ,\dram_io_data_out[258] , \dram_io_data_out[257] ,\dram_io_data_out[256] , \dram_io_data_out[255] ,\dram_io_data_out[254] , \dram_io_data_out[253] ,\dram_io_data_out[252] , \dram_io_data_out[251] ,\dram_io_data_out[250] , \dram_io_data_out[249] ,\dram_io_data_out[248] , \dram_io_data_out[247] ,\dram_io_data_out[246] , \dram_io_data_out[245] ,\dram_io_data_out[244] , \dram_io_data_out[243] ,\dram_io_data_out[242] , \dram_io_data_out[241] ,\dram_io_data_out[240] ,mode_ctrl_i_l , \dram_dqs[7] ,\dram_dqs[6] ,\dram_dqs[5] ,\dram_dqs[4] ,bsi ,bso , dram_io_bank ,dram_addr ,burst_length_four_i_r ,lpf_code_i_r , strobe_i_r ,update_dr_i_l ,hiz_n_i_l ,clock_dr_i_l ,shift_dr_i_l , se_i_l ,pad_clk_so ,dram_io_ptr_clk_inv_i_r ,dram_io_ras_l , dram_io_cs_l ,dram_ba ,\dram_dq[63] ,\dram_dq[62] ,\dram_dq[61] , \dram_dq[60] ,\dram_dq[59] ,\dram_dq[58] ,\dram_dq[57] , \dram_dq[56] ,\dram_dq[55] ,\dram_dq[54] ,\dram_dq[53] , \dram_dq[52] ,\dram_dq[51] ,\dram_dq[50] ,\dram_dq[49] , \dram_dq[48] ,\dram_dq[47] ,\dram_dq[46] ,\dram_dq[45] , \dram_dq[44] ,\dram_dq[43] ,\dram_dq[42] ,\dram_dq[41] , \dram_dq[40] ,\dram_dq[39] ,\dram_dq[38] ,\dram_dq[37] , \dram_dq[36] ,\dram_dq[35] ,\dram_dq[34] ,\dram_dq[33] , \dram_dq[32] ,\dram_dqs[35] ,\dram_dqs[34] ,\dram_dqs[33] , \dram_dqs[32] ,\dram_dqs[31] ,dram_io_addr ,\dram_dqs[16] , \dram_dqs[15] ,\dram_dqs[14] ,\dram_dqs[13] ,\dram_dqs[26] , \dram_dqs[25] ,\dram_dqs[24] ,\dram_dqs[23] ,\dram_dqs[22] , pad_pos_cnt_i_r ,dram_io_drive_data_i_r ,shift_dr_i_r , bypass_enable_o_r ,vdd_h ,\io_dram_data_in[63] , \io_dram_data_in[62] ,\io_dram_data_in[61] ,\io_dram_data_in[60] , \io_dram_data_in[59] ,\io_dram_data_in[58] ,\io_dram_data_in[57] , \io_dram_data_in[56] ,\io_dram_data_in[55] ,\io_dram_data_in[54] , \io_dram_data_in[53] ,\io_dram_data_in[52] ,\io_dram_data_in[51] , \io_dram_data_in[50] ,\io_dram_data_in[49] ,\io_dram_data_in[48] , \io_dram_data_in[47] ,\io_dram_data_in[46] ,\io_dram_data_in[45] , \io_dram_data_in[44] ,\io_dram_data_in[43] ,\io_dram_data_in[42] , \io_dram_data_in[41] ,\io_dram_data_in[40] ,\io_dram_data_in[39] , \io_dram_data_in[38] ,\io_dram_data_in[37] ,\io_dram_data_in[36] , \io_dram_data_in[35] ,\io_dram_data_in[34] ,\io_dram_data_in[33] , \io_dram_data_in[32] ,\dram_io_data_out[207] , \dram_io_data_out[206] ,\dram_io_data_out[205] , \dram_io_data_out[204] ,\dram_io_data_out[203] , \dram_io_data_out[202] ,\dram_io_data_out[201] , \dram_io_data_out[200] ,\dram_io_data_out[199] , \dram_io_data_out[198] ,\dram_io_data_out[197] , \dram_io_data_out[196] ,\dram_io_data_out[195] , \dram_io_data_out[194] ,\dram_io_data_out[193] , \dram_io_data_out[192] ,\dram_io_data_out[191] , \dram_io_data_out[190] ,\dram_io_data_out[189] , \dram_io_data_out[188] ,\dram_io_data_out[187] , \dram_io_data_out[186] ,\dram_io_data_out[185] , \dram_io_data_out[184] ,\dram_io_data_out[183] , \dram_io_data_out[182] ,\dram_io_data_out[181] , \dram_io_data_out[180] ,\dram_io_data_out[179] , \dram_io_data_out[178] ,\dram_io_data_out[177] , \dram_io_data_out[176] ); output arst_l_out ; output [8:1] cbd_o_l ; output [8:1] cbu_o_l ; output [8:1] cbu_o_r ; output [8:1] cbd_o_r ; output [143:72] serial_out ; output [143:72] afi ; input [8:1] cbd_i_l ; input [8:1] cbu_i_r ; input [8:1] cbd_i_r ; input [7:0] vrefcode_i_l ; input [7:0] vrefcode_i_r ; input [143:72] serial_in ; input [143:72] afo ; input [7:0] spare_ddr_data ; input [8:1] cbu_i_l ; input [1:0] dram_io_ptr_clk_inv_i_l ; input [4:0] lpf_code_i_l ; input [1:0] pad_pos_cnt_i_l ; input [1:0] pad_neg_cnt_i_l ; input [1:0] pad_neg_cnt_i_r ; input [1:0] dram_io_bank ; input [4:0] lpf_code_i_r ; input [1:0] dram_io_ptr_clk_inv_i_r ; input [3:0] dram_io_cs_l ; input [10:10] dram_io_addr ; input [1:0] pad_pos_cnt_i_r ; inout [7:0] spare_ddr_pin ; inout [3:0] dram_cs_l ; inout [15:8] dram_cb ; inout [10:10] dram_addr ; inout [1:0] dram_ba ; output dram_io_drive_enable_o_l ; output se_o_l ; output update_dr_o_l ; output shift_dr_o_l ; output clock_dr_o_l ; output hiz_n_o_l ; output bypass_enable_o_l ; output ps_select_o_r ; output mode_ctrl_o_r ; output update_dr_o_r ; output mode_ctrl_o_l ; output shift_dr_o_r ; output clock_dr_o_r ; output hiz_n_o_r ; output ps_select_o_l ; output \io_dram_data_in[255] ; output \io_dram_data_in[254] ; output \io_dram_data_in[253] ; output \io_dram_data_in[252] ; output \io_dram_data_in[251] ; output \io_dram_data_in[250] ; output \io_dram_data_in[249] ; output \io_dram_data_in[248] ; output \io_dram_data_in[247] ; output \io_dram_data_in[246] ; output \io_dram_data_in[245] ; output \io_dram_data_in[244] ; output \io_dram_data_in[243] ; output \io_dram_data_in[242] ; output \io_dram_data_in[241] ; output \io_dram_data_in[240] ; output \io_dram_data_in[239] ; output \io_dram_data_in[238] ; output \io_dram_data_in[237] ; output \io_dram_data_in[236] ; output \io_dram_data_in[235] ; output \io_dram_data_in[234] ; output \io_dram_data_in[233] ; output \io_dram_data_in[232] ; output \io_dram_data_in[231] ; output \io_dram_data_in[230] ; output \io_dram_data_in[229] ; output \io_dram_data_in[228] ; output \io_dram_data_in[227] ; output \io_dram_data_in[226] ; output \io_dram_data_in[225] ; output \io_dram_data_in[224] ; output \io_dram_ecc_in[31] ; output \io_dram_ecc_in[30] ; output \io_dram_ecc_in[29] ; output \io_dram_ecc_in[28] ; output \io_dram_ecc_in[27] ; output \io_dram_ecc_in[26] ; output \io_dram_ecc_in[25] ; output \io_dram_ecc_in[24] ; output \io_dram_ecc_in[15] ; output \io_dram_ecc_in[14] ; output \io_dram_ecc_in[13] ; output \io_dram_ecc_in[12] ; output \io_dram_ecc_in[11] ; output \io_dram_ecc_in[10] ; output \io_dram_ecc_in[9] ; output \io_dram_ecc_in[8] ; output \io_dram_data_in[191] ; output \io_dram_data_in[190] ; output \io_dram_data_in[189] ; output \io_dram_data_in[188] ; output \io_dram_data_in[187] ; output \io_dram_data_in[186] ; output \io_dram_data_in[185] ; output \io_dram_data_in[184] ; output \io_dram_data_in[183] ; output \io_dram_data_in[182] ; output \io_dram_data_in[181] ; output \io_dram_data_in[180] ; output \io_dram_data_in[179] ; output \io_dram_data_in[178] ; output \io_dram_data_in[177] ; output \io_dram_data_in[176] ; output \io_dram_data_in[175] ; output \io_dram_data_in[174] ; output \io_dram_data_in[173] ; output \io_dram_data_in[172] ; output \io_dram_data_in[171] ; output \io_dram_data_in[170] ; output \io_dram_data_in[169] ; output \io_dram_data_in[168] ; output \io_dram_data_in[167] ; output \io_dram_data_in[166] ; output \io_dram_data_in[165] ; output \io_dram_data_in[164] ; output \io_dram_data_in[163] ; output \io_dram_data_in[162] ; output \io_dram_data_in[161] ; output \io_dram_data_in[160] ; output \io_dram_data_in[127] ; output \io_dram_data_in[126] ; output \io_dram_data_in[125] ; output \io_dram_data_in[124] ; output \io_dram_data_in[123] ; output \io_dram_data_in[122] ; output \io_dram_data_in[121] ; output \io_dram_data_in[120] ; output \io_dram_data_in[119] ; output \io_dram_data_in[118] ; output \io_dram_data_in[117] ; output \io_dram_data_in[116] ; output \io_dram_data_in[115] ; output \io_dram_data_in[114] ; output \io_dram_data_in[113] ; output \io_dram_data_in[112] ; output \io_dram_data_in[111] ; output \io_dram_data_in[110] ; output \io_dram_data_in[109] ; output \io_dram_data_in[108] ; output \io_dram_data_in[107] ; output \io_dram_data_in[106] ; output \io_dram_data_in[105] ; output \io_dram_data_in[104] ; output \io_dram_data_in[103] ; output \io_dram_data_in[102] ; output \io_dram_data_in[101] ; output \io_dram_data_in[100] ; output \io_dram_data_in[99] ; output \io_dram_data_in[98] ; output \io_dram_data_in[97] ; output \io_dram_data_in[96] ; output bso ; output pad_clk_so ; output bypass_enable_o_r ; output \io_dram_data_in[63] ; output \io_dram_data_in[62] ; output \io_dram_data_in[61] ; output \io_dram_data_in[60] ; output \io_dram_data_in[59] ; output \io_dram_data_in[58] ; output \io_dram_data_in[57] ; output \io_dram_data_in[56] ; output \io_dram_data_in[55] ; output \io_dram_data_in[54] ; output \io_dram_data_in[53] ; output \io_dram_data_in[52] ; output \io_dram_data_in[51] ; output \io_dram_data_in[50] ; output \io_dram_data_in[49] ; output \io_dram_data_in[48] ; output \io_dram_data_in[47] ; output \io_dram_data_in[46] ; output \io_dram_data_in[45] ; output \io_dram_data_in[44] ; output \io_dram_data_in[43] ; output \io_dram_data_in[42] ; output \io_dram_data_in[41] ; output \io_dram_data_in[40] ; output \io_dram_data_in[39] ; output \io_dram_data_in[38] ; output \io_dram_data_in[37] ; output \io_dram_data_in[36] ; output \io_dram_data_in[35] ; output \io_dram_data_in[34] ; output \io_dram_data_in[33] ; output \io_dram_data_in[32] ; input ps_select_i_r ; input test_mode_i_l ; input testmode_l_i_r ; input test_mode_i_r ; input bypass_enable_i_l ; input bypass_enable_i_r ; input ps_select_i_l ; input se_i_r ; input mode_ctrl_i_r ; input clock_dr_i_r ; input hiz_n_i_r ; input update_dr_i_r ; input dram_io_drive_enable_i_r ; input rclk ; input testmode_l_i_l ; input burst_length_four_i_l ; input dram_io_pad_enable_i_l ; input dram_io_drive_enable_i_l ; input rst_l_i_l ; input arst_l_i_l ; input strobe_i_l ; input dram_io_channel_disabled_i_l ; input dram_io_drive_data_i_l ; input dram_io_channel_disabled_i_r ; input dram_io_write_en_l ; input \dram_io_data_out[63] ; input \dram_io_data_out[62] ; input \dram_io_data_out[61] ; input \dram_io_data_out[60] ; input \dram_io_data_out[59] ; input \dram_io_data_out[58] ; input \dram_io_data_out[57] ; input \dram_io_data_out[56] ; input \dram_io_data_out[55] ; input \dram_io_data_out[54] ; input \dram_io_data_out[53] ; input \dram_io_data_out[52] ; input \dram_io_data_out[51] ; input \dram_io_data_out[50] ; input \dram_io_data_out[49] ; input \dram_io_data_out[48] ; input \dram_io_data_out[47] ; input \dram_io_data_out[46] ; input \dram_io_data_out[45] ; input \dram_io_data_out[44] ; input \dram_io_data_out[43] ; input \dram_io_data_out[42] ; input \dram_io_data_out[41] ; input \dram_io_data_out[40] ; input \dram_io_data_out[39] ; input \dram_io_data_out[38] ; input \dram_io_data_out[37] ; input \dram_io_data_out[36] ; input \dram_io_data_out[35] ; input \dram_io_data_out[34] ; input \dram_io_data_out[33] ; input \dram_io_data_out[32] ; input dram_io_cas_l ; input \dram_io_data_out[287] ; input \dram_io_data_out[286] ; input \dram_io_data_out[285] ; input \dram_io_data_out[284] ; input \dram_io_data_out[283] ; input \dram_io_data_out[282] ; input \dram_io_data_out[281] ; input \dram_io_data_out[280] ; input \dram_io_data_out[143] ; input \dram_io_data_out[142] ; input \dram_io_data_out[141] ; input \dram_io_data_out[140] ; input \dram_io_data_out[139] ; input \dram_io_data_out[138] ; input \dram_io_data_out[137] ; input \dram_io_data_out[136] ; input \dram_io_data_out[127] ; input \dram_io_data_out[126] ; input \dram_io_data_out[125] ; input \dram_io_data_out[124] ; input \dram_io_data_out[123] ; input \dram_io_data_out[122] ; input \dram_io_data_out[121] ; input \dram_io_data_out[120] ; input \dram_io_data_out[119] ; input \dram_io_data_out[118] ; input \dram_io_data_out[117] ; input \dram_io_data_out[116] ; input \dram_io_data_out[115] ; input \dram_io_data_out[114] ; input \dram_io_data_out[113] ; input \dram_io_data_out[112] ; input \dram_io_data_out[111] ; input \dram_io_data_out[110] ; input \dram_io_data_out[109] ; input \dram_io_data_out[108] ; input \dram_io_data_out[107] ; input \dram_io_data_out[106] ; input \dram_io_data_out[105] ; input \dram_io_data_out[104] ; input \dram_io_data_out[103] ; input \dram_io_data_out[102] ; input \dram_io_data_out[101] ; input \dram_io_data_out[100] ; input \dram_io_data_out[99] ; input \dram_io_data_out[98] ; input \dram_io_data_out[97] ; input \dram_io_data_out[96] ; input rst_l_i_r ; input arst_l_i_r ; input pad_clk_si ; input dram_io_pad_enable_i_r ; input \dram_io_data_out[271] ; input \dram_io_data_out[270] ; input \dram_io_data_out[269] ; input \dram_io_data_out[268] ; input \dram_io_data_out[267] ; input \dram_io_data_out[266] ; input \dram_io_data_out[265] ; input \dram_io_data_out[264] ; input \dram_io_data_out[263] ; input \dram_io_data_out[262] ; input \dram_io_data_out[261] ; input \dram_io_data_out[260] ; input \dram_io_data_out[259] ; input \dram_io_data_out[258] ; input \dram_io_data_out[257] ; input \dram_io_data_out[256] ; input \dram_io_data_out[255] ; input \dram_io_data_out[254] ; input \dram_io_data_out[253] ; input \dram_io_data_out[252] ; input \dram_io_data_out[251] ; input \dram_io_data_out[250] ; input \dram_io_data_out[249] ; input \dram_io_data_out[248] ; input \dram_io_data_out[247] ; input \dram_io_data_out[246] ; input \dram_io_data_out[245] ; input \dram_io_data_out[244] ; input \dram_io_data_out[243] ; input \dram_io_data_out[242] ; input \dram_io_data_out[241] ; input \dram_io_data_out[240] ; input mode_ctrl_i_l ; input bsi ; input burst_length_four_i_r ; input strobe_i_r ; input update_dr_i_l ; input hiz_n_i_l ; input clock_dr_i_l ; input shift_dr_i_l ; input se_i_l ; input dram_io_ras_l ; input dram_io_drive_data_i_r ; input shift_dr_i_r ; input vdd_h ; input \dram_io_data_out[207] ; input \dram_io_data_out[206] ; input \dram_io_data_out[205] ; input \dram_io_data_out[204] ; input \dram_io_data_out[203] ; input \dram_io_data_out[202] ; input \dram_io_data_out[201] ; input \dram_io_data_out[200] ; input \dram_io_data_out[199] ; input \dram_io_data_out[198] ; input \dram_io_data_out[197] ; input \dram_io_data_out[196] ; input \dram_io_data_out[195] ; input \dram_io_data_out[194] ; input \dram_io_data_out[193] ; input \dram_io_data_out[192] ; input \dram_io_data_out[191] ; input \dram_io_data_out[190] ; input \dram_io_data_out[189] ; input \dram_io_data_out[188] ; input \dram_io_data_out[187] ; input \dram_io_data_out[186] ; input \dram_io_data_out[185] ; input \dram_io_data_out[184] ; input \dram_io_data_out[183] ; input \dram_io_data_out[182] ; input \dram_io_data_out[181] ; input \dram_io_data_out[180] ; input \dram_io_data_out[179] ; input \dram_io_data_out[178] ; input \dram_io_data_out[177] ; input \dram_io_data_out[176] ; inout dram_we_l ; inout dram_cas_l ; inout \dram_dq[127] ; inout \dram_dq[126] ; inout \dram_dq[125] ; inout \dram_dq[124] ; inout \dram_dq[123] ; inout \dram_dq[122] ; inout \dram_dq[121] ; inout \dram_dq[120] ; inout \dram_dq[119] ; inout \dram_dq[118] ; inout \dram_dq[117] ; inout \dram_dq[116] ; inout \dram_dq[115] ; inout \dram_dq[114] ; inout \dram_dq[113] ; inout \dram_dq[112] ; inout \dram_dq[111] ; inout \dram_dq[110] ; inout \dram_dq[109] ; inout \dram_dq[108] ; inout \dram_dq[107] ; inout \dram_dq[106] ; inout \dram_dq[105] ; inout \dram_dq[104] ; inout \dram_dq[103] ; inout \dram_dq[102] ; inout \dram_dq[101] ; inout \dram_dq[100] ; inout \dram_dq[99] ; inout \dram_dq[98] ; inout \dram_dq[97] ; inout \dram_dq[96] ; inout dram_ras_l ; inout \dram_dqs[7] ; inout \dram_dqs[6] ; inout \dram_dqs[5] ; inout \dram_dqs[4] ; inout \dram_dq[63] ; inout \dram_dq[62] ; inout \dram_dq[61] ; inout \dram_dq[60] ; inout \dram_dq[59] ; inout \dram_dq[58] ; inout \dram_dq[57] ; inout \dram_dq[56] ; inout \dram_dq[55] ; inout \dram_dq[54] ; inout \dram_dq[53] ; inout \dram_dq[52] ; inout \dram_dq[51] ; inout \dram_dq[50] ; inout \dram_dq[49] ; inout \dram_dq[48] ; inout \dram_dq[47] ; inout \dram_dq[46] ; inout \dram_dq[45] ; inout \dram_dq[44] ; inout \dram_dq[43] ; inout \dram_dq[42] ; inout \dram_dq[41] ; inout \dram_dq[40] ; inout \dram_dq[39] ; inout \dram_dq[38] ; inout \dram_dq[37] ; inout \dram_dq[36] ; inout \dram_dq[35] ; inout \dram_dq[34] ; inout \dram_dq[33] ; inout \dram_dq[32] ; inout \dram_dqs[35] ; inout \dram_dqs[34] ; inout \dram_dqs[33] ; inout \dram_dqs[32] ; inout \dram_dqs[31] ; inout \dram_dqs[16] ; inout \dram_dqs[15] ; inout \dram_dqs[14] ; inout \dram_dqs[13] ; inout \dram_dqs[26] ; inout \dram_dqs[25] ; inout \dram_dqs[24] ; inout \dram_dqs[23] ; inout \dram_dqs[22] ; wire [7:0] net0601 ; wire [7:0] net0324 ; wire [7:0] net0742 ; wire [7:0] net1106 ; wire [7:0] net0643 ; wire [1:0] net1118 ; wire [7:0] net0648 ; wire [7:0] net1290 ; wire [7:0] net997 ; wire [7:0] net857 ; wire [7:0] net856 ; wire [7:0] net0644 ; wire [7:0] net0945 ; wire [1:0] net1016 ; wire [7:0] net0845 ; wire [7:0] net0691 ; wire [1:0] net0373 ; wire [1:0] net0557 ; wire [7:0] net0844 ; wire [1:0] net0402 ; wire [7:0] net0699 ; wire [7:0] net1167 ; wire [7:0] net1122 ; wire [1:0] net1163 ; wire [7:0] net872 ; wire [1:0] net863 ; wire [7:0] net0895 ; wire [4:0] net0390 ; wire [4:0] net0565 ; wire [4:0] net1277 ; wire [7:0] net981 ; wire [4:0] net1007 ; wire [7:0] net1042 ; wire [4:0] net0399 ; wire [7:0] net1107 ; wire [7:0] net1145 ; wire [7:0] net0974 ; wire [7:0] net0602 ; wire [1:0] net0509 ; wire [1:0] net0558 ; wire [4:0] net1155 ; wire [4:0] net0517 ; wire [1:0] net868 ; wire [1:0] net0407 ; wire [1:0] net966 ; wire [1:0] net1286 ; wire [1:0] net1158 ; wire [1:0] net1164 ; wire [4:0] net1029 ; wire [1:0] net1038 ; wire [1:0] net1136 ; wire [4:0] net1103 ; wire [1:0] net1097 ; wire [1:0] net0371 ; wire [1:0] net0381 ; wire [1:0] net0408 ; wire [4:0] net977 ; wire [1:0] net1090 ; wire [1:0] net848 ; wire [1:0] net1015 ; wire [1:0] net0562 ; wire [1:0] net964 ; wire [1:0] net1280 ; wire [1:0] net0510 ; wire [1:0] net0514 ; wire [1:0] net1264 ; wire net875 ; wire net973 ; wire net1291 ; wire net1096 ; wire net0370 ; wire net1115 ; wire net974 ; wire net1017 ; wire net1293 ; wire net0372 ; wire net1294 ; wire net879 ; wire net0374 ; wire net1296 ; wire net0552 ; wire net0377 ; wire net0555 ; wire net0556 ; wire net1121 ; wire net1023 ; wire net0559 ; wire net982 ; wire net1025 ; wire net983 ; wire net1125 ; wire net1027 ; wire net1028 ; wire net0400 ; wire net0401 ; wire net1128 ; wire net0560 ; wire net0403 ; wire net0404 ; wire net0561 ; wire net0386 ; wire net0387 ; wire net0406 ; wire net0563 ; wire net0388 ; wire net0564 ; wire net0389 ; wire net0409 ; wire net0566 ; wire net1171 ; wire net991 ; wire net1270 ; wire net1271 ; wire net994 ; wire net1272 ; wire net1273 ; wire net1274 ; wire net1275 ; wire net999 ; wire net1278 ; wire net1279 ; wire net0831 ; wire net1001 ; wire net0832 ; wire net1100 ; wire net1002 ; wire net0735 ; wire bso0_bsi1 ; wire net1101 ; wire net1003 ; wire net0736 ; wire net0639 ; wire net1004 ; wire bso2_bsi3 ; wire net1104 ; wire net1281 ; wire net1006 ; wire net1008 ; wire net1284 ; wire net1089 ; wire net0640 ; wire net1287 ; wire net0543 ; wire net0544 ; wire net0368 ; wire net0369 ; wire net1150 ; wire net1151 ; wire net1154 ; wire net1254 ; wire net837 ; wire net1156 ; wire net0511 ; wire net1157 ; wire net0512 ; wire net0591 ; wire net839 ; wire net1159 ; wire net0513 ; wire net1257 ; wire net0592 ; wire net0515 ; wire pad_clk_so1_si2 ; wire net1259 ; wire net0516 ; wire net0518 ; wire pad_clk_so2_si3 ; wire net1160 ; wire net843 ; wire net1260 ; wire net844 ; wire net846 ; wire net847 ; wire net1166 ; wire pad_clk_so0_si1 ; wire net1266 ; wire net1169 ; wire net1030 ; wire net850 ; wire net1130 ; wire net1033 ; wire net852 ; wire net1036 ; wire net1134 ; wire net0410 ; wire pad_clk_so3_si4 ; wire net1137 ; wire net858 ; wire net0393 ; wire net0413 ; wire net0394 ; wire net0414 ; wire net0415 ; wire net0416 ; wire net0397 ; wire net0495 ; wire net0417 ; wire net0496 ; wire net0398 ; wire net0418 ; wire net0419 ; wire net862 ; wire net1043 ; wire bso1_bsi2 ; wire net1143 ; wire net1045 ; wire net1144 ; wire net963 ; wire net1046 ; wire net865 ; wire net1047 ; wire bso3_bsi4 ; wire net1049 ; wire net967 ; wire net0879 ; wire net968 ; wire net1149 ; wire net0504 ; wire net870 ; wire net0507 ; wire net0783 ; wire net871 ; wire net0508 ; wire net0784 ; wire net0687 ; wire net971 ; wire net0884 ; wire net0688 ; bw_io_ddr_6sig_x4 I0 ( .serial_in ({serial_in[87:72] } ), .afo ({afo[87:72] } ), .serial_out ({serial_out[87:72] } ), .afi ({afi[87:72] } ), .vrefcode_i_l ({net0324[0] ,net0324[1] ,net0324[2] ,net0324[3] , net0324[4] ,net0324[5] ,net0324[6] ,net0324[7] } ), .vrefcode_i_r ({net0691[0] ,net0691[1] ,net0691[2] ,net0691[3] , net0691[4] ,net0691[5] ,net0691[6] ,net0691[7] } ), .data_neg ({\dram_io_data_out[247] ,\dram_io_data_out[246] , \dram_io_data_out[245] ,\dram_io_data_out[244] , \dram_io_data_out[243] ,\dram_io_data_out[242] , \dram_io_data_out[241] ,\dram_io_data_out[240] , \dram_io_data_out[183] ,\dram_io_data_out[182] , \dram_io_data_out[181] ,\dram_io_data_out[180] , \dram_io_data_out[179] ,\dram_io_data_out[178] , \dram_io_data_out[177] ,\dram_io_data_out[176] } ), .data_pos ({\dram_io_data_out[103] ,\dram_io_data_out[102] , \dram_io_data_out[101] ,\dram_io_data_out[100] , \dram_io_data_out[99] ,\dram_io_data_out[98] , \dram_io_data_out[97] ,\dram_io_data_out[96] , \dram_io_data_out[39] ,\dram_io_data_out[38] , \dram_io_data_out[37] ,\dram_io_data_out[36] , \dram_io_data_out[35] ,\dram_io_data_out[34] , \dram_io_data_out[33] ,\dram_io_data_out[32] } ), .io_dram_data_in ({\io_dram_data_in[103] ,\io_dram_data_in[102] , \io_dram_data_in[101] ,\io_dram_data_in[100] , \io_dram_data_in[99] ,\io_dram_data_in[98] , \io_dram_data_in[97] ,\io_dram_data_in[96] , \io_dram_data_in[39] ,\io_dram_data_in[38] , \io_dram_data_in[37] ,\io_dram_data_in[36] , \io_dram_data_in[35] ,\io_dram_data_in[34] , \io_dram_data_in[33] ,\io_dram_data_in[32] } ), .io_dram_data_in_hi ({\io_dram_data_in[231] ,\io_dram_data_in[230] ,\io_dram_data_in[229] ,\io_dram_data_in[228] , \io_dram_data_in[227] ,\io_dram_data_in[226] , \io_dram_data_in[225] ,\io_dram_data_in[224] , \io_dram_data_in[167] ,\io_dram_data_in[166] , \io_dram_data_in[165] ,\io_dram_data_in[164] , \io_dram_data_in[163] ,\io_dram_data_in[162] , \io_dram_data_in[161] ,\io_dram_data_in[160] } ), .dq_pad ({\dram_dq[103] ,\dram_dq[102] ,\dram_dq[101] , \dram_dq[100] ,\dram_dq[99] ,\dram_dq[98] ,\dram_dq[97] , \dram_dq[96] ,\dram_dq[39] ,\dram_dq[38] ,\dram_dq[37] , \dram_dq[36] ,\dram_dq[35] ,\dram_dq[34] ,\dram_dq[33] , \dram_dq[32] } ), .lpf_code_i_r ({net0565[0] ,net0565[1] ,net0565[2] ,net0565[3] , net0565[4] } ), .dram_io_ptr_clk_inv_i_r ({net0562[0] ,net0562[1] } ), .pad_pos_cnt_i_r ({net0558[0] ,net0558[1] } ), .pad_neg_cnt_i_r ({net0557[0] ,net0557[1] } ), .cbu_i_r ({net0602[0] ,net0602[1] ,net0602[2] ,net0602[3] , net0602[4] ,net0602[5] ,net0602[6] ,net0602[7] } ), .cbd_i_r ({net0601[0] ,net0601[1] ,net0601[2] ,net0601[3] , net0601[4] ,net0601[5] ,net0601[6] ,net0601[7] } ), .dqs_pad ({\dram_dqs[31] ,\dram_dqs[22] ,\dram_dqs[13] , \dram_dqs[4] } ), .lpf_code_i_l ({net0517[0] ,net0517[1] ,net0517[2] ,net0517[3] , net0517[4] } ), .dram_io_ptr_clk_inv_i_l ({net0514[0] ,net0514[1] } ), .pad_pos_cnt_i_l ({net0510[0] ,net0510[1] } ), .pad_neg_cnt_i_l ({net0509[0] ,net0509[1] } ), .cbu_i_l ({net0644[0] ,net0644[1] ,net0644[2] ,net0644[3] , net0644[4] ,net0644[5] ,net0644[6] ,net0644[7] } ), .cbd_i_l ({net0643[0] ,net0643[1] ,net0643[2] ,net0643[3] , net0643[4] ,net0643[5] ,net0643[6] ,net0643[7] } ), .bypass_enable_i_r (net1130 ), .ps_select_i_r (net0544 ), .test_mode_i_l (net0495 ), .testmode_l_i_l (net0511 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0543 ), .strobe_i_r (net0566 ), .burst_length_four_i_r (net0563 ), .dram_io_pad_enable_i_r (net0561 ), .dram_io_drive_enable_i_r (net0560 ), .rst_l_i_r (net0564 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net0556 ), .dram_io_drive_data_i_r (net0555 ), .se_i_r (net0552 ), .mode_ctrl_i_r (net1125 ), .update_dr_i_r (net1293 ), .shift_dr_i_r (net1294 ), .clock_dr_i_r (net1128 ), .hiz_n_i_r (net1296 ), .pad_clk_si (pad_clk_si ), .pad_clk_so (pad_clk_so0_si1 ), .ctl_pad_0 (dram_addr[10] ), .ctl_pad_1 (dram_ba[1] ), .ctl_pad_3 (dram_ras_l ), .ctl_pad_2 (dram_ba[0] ), .ctl_data_0 (dram_io_addr[10] ), .ctl_data_1 (dram_io_bank[1] ), .ctl_data_2 (dram_io_bank[0] ), .ctl_data_3 (dram_io_ras_l ), .bsi (bsi ), .bso (bso0_bsi1 ), .strobe_i_l (net0518 ), .burst_length_four_i_l (net0515 ), .dram_io_pad_enable_i_l (net0513 ), .dram_io_drive_enable_i_l (net0512 ), .rst_l_i_l (net0516 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net0508 ), .dram_io_drive_data_i_l (net0507 ), .se_i_l (net0504 ), .mode_ctrl_i_l (net1270 ), .ps_select_i_l (net0496 ), .shift_dr_i_l (net1272 ), .clock_dr_i_l (net1273 ), .testmode_l_i_r (net0559 ), .hiz_n_i_l (net1274 ), .bypass_enable_i_l (net1275 ), .update_dr_i_l (net1271 ) ); bw_io_ddr_6sig_x4 I1 ( .serial_in ({serial_in[103:88] } ), .afo ({afo[103:88] } ), .serial_out ({serial_out[103:88] } ), .afi ({afi[103:88] } ), .vrefcode_i_l ({net0648[0] ,net0648[1] ,net0648[2] ,net0648[3] , net0648[4] ,net0648[5] ,net0648[6] ,net0648[7] } ), .vrefcode_i_r ({net0699[0] ,net0699[1] ,net0699[2] ,net0699[3] , net0699[4] ,net0699[5] ,net0699[6] ,net0699[7] } ), .data_neg ({\dram_io_data_out[255] ,\dram_io_data_out[254] , \dram_io_data_out[253] ,\dram_io_data_out[252] , \dram_io_data_out[251] ,\dram_io_data_out[250] , \dram_io_data_out[249] ,\dram_io_data_out[248] , \dram_io_data_out[191] ,\dram_io_data_out[190] , \dram_io_data_out[189] ,\dram_io_data_out[188] , \dram_io_data_out[187] ,\dram_io_data_out[186] , \dram_io_data_out[185] ,\dram_io_data_out[184] } ), .data_pos ({\dram_io_data_out[111] ,\dram_io_data_out[110] , \dram_io_data_out[109] ,\dram_io_data_out[108] , \dram_io_data_out[107] ,\dram_io_data_out[106] , \dram_io_data_out[105] ,\dram_io_data_out[104] , \dram_io_data_out[47] ,\dram_io_data_out[46] , \dram_io_data_out[45] ,\dram_io_data_out[44] , \dram_io_data_out[43] ,\dram_io_data_out[42] , \dram_io_data_out[41] ,\dram_io_data_out[40] } ), .io_dram_data_in ({\io_dram_data_in[111] ,\io_dram_data_in[110] , \io_dram_data_in[109] ,\io_dram_data_in[108] , \io_dram_data_in[107] ,\io_dram_data_in[106] , \io_dram_data_in[105] ,\io_dram_data_in[104] , \io_dram_data_in[47] ,\io_dram_data_in[46] , \io_dram_data_in[45] ,\io_dram_data_in[44] , \io_dram_data_in[43] ,\io_dram_data_in[42] , \io_dram_data_in[41] ,\io_dram_data_in[40] } ), .io_dram_data_in_hi ({\io_dram_data_in[239] ,\io_dram_data_in[238] ,\io_dram_data_in[237] ,\io_dram_data_in[236] , \io_dram_data_in[235] ,\io_dram_data_in[234] , \io_dram_data_in[233] ,\io_dram_data_in[232] , \io_dram_data_in[175] ,\io_dram_data_in[174] , \io_dram_data_in[173] ,\io_dram_data_in[172] , \io_dram_data_in[171] ,\io_dram_data_in[170] , \io_dram_data_in[169] ,\io_dram_data_in[168] } ), .dq_pad ({\dram_dq[111] ,\dram_dq[110] ,\dram_dq[109] , \dram_dq[108] ,\dram_dq[107] ,\dram_dq[106] ,\dram_dq[105] , \dram_dq[104] ,\dram_dq[47] ,\dram_dq[46] ,\dram_dq[45] , \dram_dq[44] ,\dram_dq[43] ,\dram_dq[42] ,\dram_dq[41] , \dram_dq[40] } ), .lpf_code_i_r ({net1277[0] ,net1277[1] ,net1277[2] ,net1277[3] , net1277[4] } ), .dram_io_ptr_clk_inv_i_r ({net1280[0] ,net1280[1] } ), .pad_pos_cnt_i_r ({net1118[0] ,net1118[1] } ), .pad_neg_cnt_i_r ({net1286[0] ,net1286[1] } ), .cbu_i_r ({net1290[0] ,net1290[1] ,net1290[2] ,net1290[3] , net1290[4] ,net1290[5] ,net1290[6] ,net1290[7] } ), .cbd_i_r ({net1122[0] ,net1122[1] ,net1122[2] ,net1122[3] , net1122[4] ,net1122[5] ,net1122[6] ,net1122[7] } ), .dqs_pad ({\dram_dqs[32] ,\dram_dqs[23] ,\dram_dqs[14] , \dram_dqs[5] } ), .lpf_code_i_l ({net1103[0] ,net1103[1] ,net1103[2] ,net1103[3] , net1103[4] } ), .dram_io_ptr_clk_inv_i_l ({net1097[0] ,net1097[1] } ), .pad_pos_cnt_i_l ({net1090[0] ,net1090[1] } ), .pad_neg_cnt_i_l ({net1264[0] ,net1264[1] } ), .cbu_i_l ({net1107[0] ,net1107[1] ,net1107[2] ,net1107[3] , net1107[4] ,net1107[5] ,net1107[6] ,net1107[7] } ), .cbd_i_l ({net1106[0] ,net1106[1] ,net1106[2] ,net1106[3] , net1106[4] ,net1106[5] ,net1106[6] ,net1106[7] } ), .bypass_enable_i_r (net1004 ), .ps_select_i_r (net0640 ), .test_mode_i_l (net0591 ), .testmode_l_i_l (net1100 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0639 ), .strobe_i_r (net1104 ), .burst_length_four_i_r (net1279 ), .dram_io_pad_enable_i_r (net1281 ), .dram_io_drive_enable_i_r (net1115 ), .rst_l_i_r (net1278 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net1287 ), .dram_io_drive_data_i_r (net1121 ), .se_i_r (net1291 ), .mode_ctrl_i_r (net999 ), .update_dr_i_r (net1171 ), .shift_dr_i_r (net1001 ), .clock_dr_i_r (net1002 ), .hiz_n_i_r (net1003 ), .pad_clk_si (pad_clk_so0_si1 ), .pad_clk_so (pad_clk_so1_si2 ), .ctl_pad_0 (spare_ddr_pin[7] ), .ctl_pad_1 (dram_we_l ), .ctl_pad_3 (dram_cs_l[0] ), .ctl_pad_2 (dram_cas_l ), .ctl_data_0 (spare_ddr_data[7] ), .ctl_data_1 (dram_io_write_en_l ), .ctl_data_2 (dram_io_cas_l ), .ctl_data_3 (dram_io_cs_l[0] ), .bsi (bso0_bsi1 ), .bso (bso1_bsi2 ), .strobe_i_l (net1254 ), .burst_length_four_i_l (net1257 ), .dram_io_pad_enable_i_l (net1259 ), .dram_io_drive_enable_i_l (net1260 ), .rst_l_i_l (net1101 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net1089 ), .dram_io_drive_data_i_l (net1266 ), .se_i_l (net1096 ), .mode_ctrl_i_l (net963 ), .ps_select_i_l (net0592 ), .shift_dr_i_l (net1150 ), .clock_dr_i_l (net1151 ), .testmode_l_i_r (net1284 ), .hiz_n_i_l (net982 ), .bypass_enable_i_l (net983 ), .update_dr_i_l (net1149 ) ); bw_io_ddr_6sig_x4 I2 ( .serial_in ({serial_in[119:104] } ), .afo ({afo[119:104] } ), .serial_out ({serial_out[119:104] } ), .afi ({afi[119:104] } ), .vrefcode_i_l ({net0895[0] ,net0895[1] ,net0895[2] ,net0895[3] , net0895[4] ,net0895[5] ,net0895[6] ,net0895[7] } ), .vrefcode_i_r ({net0844[0] ,net0844[1] ,net0844[2] ,net0844[3] , net0844[4] ,net0844[5] ,net0844[6] ,net0844[7] } ), .data_neg ({\dram_io_data_out[263] ,\dram_io_data_out[262] , \dram_io_data_out[261] ,\dram_io_data_out[260] , \dram_io_data_out[259] ,\dram_io_data_out[258] , \dram_io_data_out[257] ,\dram_io_data_out[256] , \dram_io_data_out[199] ,\dram_io_data_out[198] , \dram_io_data_out[197] ,\dram_io_data_out[196] , \dram_io_data_out[195] ,\dram_io_data_out[194] , \dram_io_data_out[193] ,\dram_io_data_out[192] } ), .data_pos ({\dram_io_data_out[119] ,\dram_io_data_out[118] , \dram_io_data_out[117] ,\dram_io_data_out[116] , \dram_io_data_out[115] ,\dram_io_data_out[114] , \dram_io_data_out[113] ,\dram_io_data_out[112] , \dram_io_data_out[55] ,\dram_io_data_out[54] , \dram_io_data_out[53] ,\dram_io_data_out[52] , \dram_io_data_out[51] ,\dram_io_data_out[50] , \dram_io_data_out[49] ,\dram_io_data_out[48] } ), .io_dram_data_in ({\io_dram_data_in[119] ,\io_dram_data_in[118] , \io_dram_data_in[117] ,\io_dram_data_in[116] , \io_dram_data_in[115] ,\io_dram_data_in[114] , \io_dram_data_in[113] ,\io_dram_data_in[112] , \io_dram_data_in[55] ,\io_dram_data_in[54] , \io_dram_data_in[53] ,\io_dram_data_in[52] , \io_dram_data_in[51] ,\io_dram_data_in[50] , \io_dram_data_in[49] ,\io_dram_data_in[48] } ), .io_dram_data_in_hi ({\io_dram_data_in[247] ,\io_dram_data_in[246] ,\io_dram_data_in[245] ,\io_dram_data_in[244] , \io_dram_data_in[243] ,\io_dram_data_in[242] , \io_dram_data_in[241] ,\io_dram_data_in[240] , \io_dram_data_in[183] ,\io_dram_data_in[182] , \io_dram_data_in[181] ,\io_dram_data_in[180] , \io_dram_data_in[179] ,\io_dram_data_in[178] , \io_dram_data_in[177] ,\io_dram_data_in[176] } ), .dq_pad ({\dram_dq[119] ,\dram_dq[118] ,\dram_dq[117] , \dram_dq[116] ,\dram_dq[115] ,\dram_dq[114] ,\dram_dq[113] , \dram_dq[112] ,\dram_dq[55] ,\dram_dq[54] ,\dram_dq[53] , \dram_dq[52] ,\dram_dq[51] ,\dram_dq[50] ,\dram_dq[49] , \dram_dq[48] } ), .lpf_code_i_r ({net1155[0] ,net1155[1] ,net1155[2] ,net1155[3] , net1155[4] } ), .dram_io_ptr_clk_inv_i_r ({net1158[0] ,net1158[1] } ), .pad_pos_cnt_i_r ({net1163[0] ,net1163[1] } ), .pad_neg_cnt_i_r ({net1164[0] ,net1164[1] } ), .cbu_i_r ({net997[0] ,net997[1] ,net997[2] ,net997[3] , net997[4] ,net997[5] ,net997[6] ,net997[7] } ), .cbd_i_r ({net1167[0] ,net1167[1] ,net1167[2] ,net1167[3] , net1167[4] ,net1167[5] ,net1167[6] ,net1167[7] } ), .dqs_pad ({\dram_dqs[33] ,\dram_dqs[24] ,\dram_dqs[15] , \dram_dqs[6] } ), .lpf_code_i_l ({net977[0] ,net977[1] ,net977[2] ,net977[3] , net977[4] } ), .dram_io_ptr_clk_inv_i_l ({net1136[0] ,net1136[1] } ), .pad_pos_cnt_i_l ({net966[0] ,net966[1] } ), .pad_neg_cnt_i_l ({net964[0] ,net964[1] } ), .cbu_i_l ({net981[0] ,net981[1] ,net981[2] ,net981[3] , net981[4] ,net981[5] ,net981[6] ,net981[7] } ), .cbd_i_l ({net1145[0] ,net1145[1] ,net1145[2] ,net1145[3] , net1145[4] ,net1145[5] ,net1145[6] ,net1145[7] } ), .bypass_enable_i_r (net1049 ), .ps_select_i_r (net0736 ), .test_mode_i_l (net0831 ), .testmode_l_i_l (net974 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0735 ), .strobe_i_r (net1154 ), .burst_length_four_i_r (net1157 ), .dram_io_pad_enable_i_r (net1159 ), .dram_io_drive_enable_i_r (net1160 ), .rst_l_i_r (net1156 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net994 ), .dram_io_drive_data_i_r (net1166 ), .se_i_r (net1169 ), .mode_ctrl_i_r (net875 ), .update_dr_i_r (net1045 ), .shift_dr_i_r (net1046 ), .clock_dr_i_r (net1047 ), .hiz_n_i_r (net879 ), .pad_clk_si (pad_clk_so1_si2 ), .pad_clk_so (pad_clk_so2_si3 ), .ctl_pad_0 (dram_cs_l[1] ), .ctl_pad_1 (dram_cs_l[2] ), .ctl_pad_3 (spare_ddr_pin[2] ), .ctl_pad_2 (dram_cs_l[3] ), .ctl_data_0 (dram_io_cs_l[1] ), .ctl_data_1 (dram_io_cs_l[2] ), .ctl_data_2 (dram_io_cs_l[3] ), .ctl_data_3 (spare_ddr_data[2] ), .bsi (bso1_bsi2 ), .bso (bso2_bsi3 ), .strobe_i_l (net973 ), .burst_length_four_i_l (net967 ), .dram_io_pad_enable_i_l (net1137 ), .dram_io_drive_enable_i_l (net968 ), .rst_l_i_l (net1134 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net1143 ), .dram_io_drive_data_i_l (net1144 ), .se_i_l (net971 ), .mode_ctrl_i_l (net839 ), .ps_select_i_l (net0832 ), .shift_dr_i_l (net837 ), .clock_dr_i_l (net1025 ), .testmode_l_i_r (net991 ), .hiz_n_i_l (net858 ), .bypass_enable_i_l (net1027 ), .update_dr_i_l (net1023 ) ); bw_io_ddr_6sig_x4 I3 ( .serial_in ({serial_in[135:120] } ), .afo ({afo[135:120] } ), .serial_out ({serial_out[135:120] } ), .afi ({afi[135:120] } ), .vrefcode_i_l ({net0742[0] ,net0742[1] ,net0742[2] ,net0742[3] , net0742[4] ,net0742[5] ,net0742[6] ,net0742[7] } ), .vrefcode_i_r ({net0845[0] ,net0845[1] ,net0845[2] ,net0845[3] , net0845[4] ,net0845[5] ,net0845[6] ,net0845[7] } ), .data_neg ({\dram_io_data_out[271] ,\dram_io_data_out[270] , \dram_io_data_out[269] ,\dram_io_data_out[268] , \dram_io_data_out[267] ,\dram_io_data_out[266] , \dram_io_data_out[265] ,\dram_io_data_out[264] , \dram_io_data_out[207] ,\dram_io_data_out[206] , \dram_io_data_out[205] ,\dram_io_data_out[204] , \dram_io_data_out[203] ,\dram_io_data_out[202] , \dram_io_data_out[201] ,\dram_io_data_out[200] } ), .data_pos ({\dram_io_data_out[127] ,\dram_io_data_out[126] , \dram_io_data_out[125] ,\dram_io_data_out[124] , \dram_io_data_out[123] ,\dram_io_data_out[122] , \dram_io_data_out[121] ,\dram_io_data_out[120] , \dram_io_data_out[63] ,\dram_io_data_out[62] , \dram_io_data_out[61] ,\dram_io_data_out[60] , \dram_io_data_out[59] ,\dram_io_data_out[58] , \dram_io_data_out[57] ,\dram_io_data_out[56] } ), .io_dram_data_in ({\io_dram_data_in[127] ,\io_dram_data_in[126] , \io_dram_data_in[125] ,\io_dram_data_in[124] , \io_dram_data_in[123] ,\io_dram_data_in[122] , \io_dram_data_in[121] ,\io_dram_data_in[120] , \io_dram_data_in[63] ,\io_dram_data_in[62] , \io_dram_data_in[61] ,\io_dram_data_in[60] , \io_dram_data_in[59] ,\io_dram_data_in[58] , \io_dram_data_in[57] ,\io_dram_data_in[56] } ), .io_dram_data_in_hi ({\io_dram_data_in[255] ,\io_dram_data_in[254] ,\io_dram_data_in[253] ,\io_dram_data_in[252] , \io_dram_data_in[251] ,\io_dram_data_in[250] , \io_dram_data_in[249] ,\io_dram_data_in[248] , \io_dram_data_in[191] ,\io_dram_data_in[190] , \io_dram_data_in[189] ,\io_dram_data_in[188] , \io_dram_data_in[187] ,\io_dram_data_in[186] , \io_dram_data_in[185] ,\io_dram_data_in[184] } ), .dq_pad ({\dram_dq[127] ,\dram_dq[126] ,\dram_dq[125] , \dram_dq[124] ,\dram_dq[123] ,\dram_dq[122] ,\dram_dq[121] , \dram_dq[120] ,\dram_dq[63] ,\dram_dq[62] ,\dram_dq[61] , \dram_dq[60] ,\dram_dq[59] ,\dram_dq[58] ,\dram_dq[57] , \dram_dq[56] } ), .lpf_code_i_r ({net1029[0] ,net1029[1] ,net1029[2] ,net1029[3] , net1029[4] } ), .dram_io_ptr_clk_inv_i_r ({net863[0] ,net863[1] } ), .pad_pos_cnt_i_r ({net868[0] ,net868[1] } ), .pad_neg_cnt_i_r ({net1038[0] ,net1038[1] } ), .cbu_i_r ({net1042[0] ,net1042[1] ,net1042[2] ,net1042[3] , net1042[4] ,net1042[5] ,net1042[6] ,net1042[7] } ), .cbd_i_r ({net872[0] ,net872[1] ,net872[2] ,net872[3] , net872[4] ,net872[5] ,net872[6] ,net872[7] } ), .dqs_pad ({\dram_dqs[34] ,\dram_dqs[25] ,\dram_dqs[16] , \dram_dqs[7] } ), .lpf_code_i_l ({net1007[0] ,net1007[1] ,net1007[2] ,net1007[3] , net1007[4] } ), .dram_io_ptr_clk_inv_i_l ({net848[0] ,net848[1] } ), .pad_pos_cnt_i_l ({net1015[0] ,net1015[1] } ), .pad_neg_cnt_i_l ({net1016[0] ,net1016[1] } ), .cbu_i_l ({net857[0] ,net857[1] ,net857[2] ,net857[3] , net857[4] ,net857[5] ,net857[6] ,net857[7] } ), .cbd_i_l ({net856[0] ,net856[1] ,net856[2] ,net856[3] , net856[4] ,net856[5] ,net856[6] ,net856[7] } ), .bypass_enable_i_r (net0419 ), .ps_select_i_r (net0784 ), .test_mode_i_l (net0687 ), .testmode_l_i_l (net850 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0783 ), .strobe_i_r (net1028 ), .burst_length_four_i_r (net862 ), .dram_io_pad_enable_i_r (net1033 ), .dram_io_drive_enable_i_r (net865 ), .rst_l_i_r (net1030 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net870 ), .dram_io_drive_data_i_r (net871 ), .se_i_r (net1043 ), .mode_ctrl_i_r (net0414 ), .update_dr_i_r (net0415 ), .shift_dr_i_r (net0416 ), .clock_dr_i_r (net0417 ), .hiz_n_i_r (net0418 ), .pad_clk_si (pad_clk_so2_si3 ), .pad_clk_so (pad_clk_so3_si4 ), .ctl_pad_0 (spare_ddr_pin[3] ), .ctl_pad_1 (spare_ddr_pin[4] ), .ctl_pad_3 (spare_ddr_pin[6] ), .ctl_pad_2 (spare_ddr_pin[5] ), .ctl_data_0 (spare_ddr_data[3] ), .ctl_data_1 (spare_ddr_data[4] ), .ctl_data_2 (spare_ddr_data[5] ), .ctl_data_3 (spare_ddr_data[6] ), .bsi (bso2_bsi3 ), .bso (bso3_bsi4 ), .strobe_i_l (net1006 ), .burst_length_four_i_l (net843 ), .dram_io_pad_enable_i_l (net852 ), .dram_io_drive_enable_i_l (net844 ), .rst_l_i_l (net1008 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net1017 ), .dram_io_drive_data_i_l (net846 ), .se_i_l (net847 ), .mode_ctrl_i_l (net0370 ), .ps_select_i_l (net0688 ), .shift_dr_i_l (net0368 ), .clock_dr_i_l (net0369 ), .testmode_l_i_r (net1036 ), .hiz_n_i_l (net0397 ), .bypass_enable_i_l (net0398 ), .update_dr_i_l (net0394 ) ); bw_io_ddr_rptr_b I358 ( .out14 ({cbd_o_l } ), .out13 ({cbu_o_l } ), .out10 ({net0509[0] ,net0509[1] } ), .out9 ({net0510[0] ,net0510[1] } ), .out4 ({net0514[0] ,net0514[1] } ), .in14 ({net0643[0] ,net0643[1] ,net0643[2] ,net0643[3] , net0643[4] ,net0643[5] ,net0643[6] ,net0643[7] } ), .in13 ({net0644[0] ,net0644[1] ,net0644[2] ,net0644[3] , net0644[4] ,net0644[5] ,net0644[6] ,net0644[7] } ), .out1 ({net0517[0] ,net0517[1] ,net0517[2] ,net0517[3] , net0517[4] } ), .in10 ({pad_neg_cnt_i_l } ), .out25 ({net0324[0] ,net0324[1] ,net0324[2] ,net0324[3] , net0324[4] ,net0324[5] ,net0324[6] ,net0324[7] } ), .in25 ({vrefcode_i_l } ), .in1 ({lpf_code_i_l } ), .in4 ({dram_io_ptr_clk_inv_i_l } ), .in9 ({pad_pos_cnt_i_l } ), .out21 (bypass_enable_o_l ), .out20 (hiz_n_o_l ), .out19 (clock_dr_o_l ), .out18 (shift_dr_o_l ), .out17 (update_dr_o_l ), .out16 (mode_ctrl_o_l ), .out15 (net0504 ), .out12 (net0507 ), .out8 (net0511 ), .out6 (net0512 ), .out5 (net0513 ), .out3 (net0515 ), .out2 (net0516 ), .in21 (net1275 ), .in20 (net1274 ), .in19 (net1273 ), .in18 (net1272 ), .in17 (net1271 ), .in16 (net1270 ), .in15 (se_i_l ), .in12 (dram_io_drive_data_i_l ), .out0 (net0518 ), .in22 (net0496 ), .out22 (ps_select_o_l ), .in24 (test_mode_i_l ), .out24 (net0495 ), .vdd18 (vdd_h ), .in2 (rst_l_i_l ), .in5 (dram_io_pad_enable_i_l ), .out11 (net0508 ), .in3 (burst_length_four_i_l ), .in11 (dram_io_channel_disabled_i_l ), .in0 (strobe_i_l ), .in6 (dram_io_drive_enable_i_l ), .in8 (testmode_l_i_l ) ); bw_io_ddr_rptr_b I359 ( .out14 ({cbd_o_r } ), .out13 ({cbu_o_r } ), .out10 ({net0557[0] ,net0557[1] } ), .out9 ({net0558[0] ,net0558[1] } ), .out4 ({net0562[0] ,net0562[1] } ), .in14 ({net0601[0] ,net0601[1] ,net0601[2] ,net0601[3] , net0601[4] ,net0601[5] ,net0601[6] ,net0601[7] } ), .in13 ({net0602[0] ,net0602[1] ,net0602[2] ,net0602[3] , net0602[4] ,net0602[5] ,net0602[6] ,net0602[7] } ), .out1 ({net0565[0] ,net0565[1] ,net0565[2] ,net0565[3] , net0565[4] } ), .in10 ({pad_neg_cnt_i_r } ), .out25 ({net0691[0] ,net0691[1] ,net0691[2] ,net0691[3] , net0691[4] ,net0691[5] ,net0691[6] ,net0691[7] } ), .in25 ({vrefcode_i_r } ), .in1 ({lpf_code_i_r } ), .in4 ({dram_io_ptr_clk_inv_i_r } ), .in9 ({pad_pos_cnt_i_r } ), .out21 (bypass_enable_o_r ), .out20 (hiz_n_o_r ), .out19 (clock_dr_o_r ), .out18 (shift_dr_o_r ), .out17 (update_dr_o_r ), .out16 (mode_ctrl_o_r ), .out15 (net0552 ), .out12 (net0555 ), .out8 (net0559 ), .out6 (net0560 ), .out5 (net0561 ), .out3 (net0563 ), .out2 (net0564 ), .in21 (net1130 ), .in20 (net1296 ), .in19 (net1128 ), .in18 (net1294 ), .in17 (net1293 ), .in16 (net1125 ), .in15 (se_i_r ), .in12 (dram_io_drive_data_i_r ), .out0 (net0566 ), .in22 (net0544 ), .out22 (ps_select_o_r ), .in24 (test_mode_i_r ), .out24 (net0543 ), .vdd18 (vdd_h ), .in2 (rst_l_i_r ), .in5 (dram_io_pad_enable_i_r ), .out11 (net0556 ), .in3 (burst_length_four_i_r ), .in11 (dram_io_channel_disabled_i_r ), .in0 (strobe_i_r ), .in6 (dram_io_drive_enable_i_r ), .in8 (testmode_l_i_r ) ); bw_io_ddr_rptr_b I277 ( .out14 ({net0643[0] ,net0643[1] ,net0643[2] ,net0643[3] , net0643[4] ,net0643[5] ,net0643[6] ,net0643[7] } ), .out13 ({net0644[0] ,net0644[1] ,net0644[2] ,net0644[3] , net0644[4] ,net0644[5] ,net0644[6] ,net0644[7] } ), .out10 ({net1264[0] ,net1264[1] } ), .out9 ({net1090[0] ,net1090[1] } ), .out4 ({net1097[0] ,net1097[1] } ), .in14 ({net1106[0] ,net1106[1] ,net1106[2] ,net1106[3] , net1106[4] ,net1106[5] ,net1106[6] ,net1106[7] } ), .in13 ({net1107[0] ,net1107[1] ,net1107[2] ,net1107[3] , net1107[4] ,net1107[5] ,net1107[6] ,net1107[7] } ), .out1 ({net1103[0] ,net1103[1] ,net1103[2] ,net1103[3] , net1103[4] } ), .in10 ({net0509[0] ,net0509[1] } ), .out25 ({net0648[0] ,net0648[1] ,net0648[2] ,net0648[3] , net0648[4] ,net0648[5] ,net0648[6] ,net0648[7] } ), .in25 ({net0324[0] ,net0324[1] ,net0324[2] ,net0324[3] , net0324[4] ,net0324[5] ,net0324[6] ,net0324[7] } ), .in1 ({net0517[0] ,net0517[1] ,net0517[2] ,net0517[3] , net0517[4] } ), .in4 ({net0514[0] ,net0514[1] } ), .in9 ({net0510[0] ,net0510[1] } ), .out21 (net1275 ), .out20 (net1274 ), .out19 (net1273 ), .out18 (net1272 ), .out17 (net1271 ), .out16 (net1270 ), .out15 (net1096 ), .out12 (net1266 ), .out8 (net1100 ), .out6 (net1260 ), .out5 (net1259 ), .out3 (net1257 ), .out2 (net1101 ), .in21 (net983 ), .in20 (net982 ), .in19 (net1151 ), .in18 (net1150 ), .in17 (net1149 ), .in16 (net963 ), .in15 (net0504 ), .in12 (net0507 ), .out0 (net1254 ), .in22 (net0592 ), .out22 (net0496 ), .in24 (net0495 ), .out24 (net0591 ), .vdd18 (vdd_h ), .in2 (net0516 ), .in5 (net0513 ), .out11 (net1089 ), .in3 (net0515 ), .in11 (net0508 ), .in0 (net0518 ), .in6 (net0512 ), .in8 (net0511 ) ); bw_io_ddr_rptr_b I278 ( .out14 ({net0601[0] ,net0601[1] ,net0601[2] ,net0601[3] , net0601[4] ,net0601[5] ,net0601[6] ,net0601[7] } ), .out13 ({net0602[0] ,net0602[1] ,net0602[2] ,net0602[3] , net0602[4] ,net0602[5] ,net0602[6] ,net0602[7] } ), .out10 ({net1286[0] ,net1286[1] } ), .out9 ({net1118[0] ,net1118[1] } ), .out4 ({net1280[0] ,net1280[1] } ), .in14 ({net1122[0] ,net1122[1] ,net1122[2] ,net1122[3] , net1122[4] ,net1122[5] ,net1122[6] ,net1122[7] } ), .in13 ({net1290[0] ,net1290[1] ,net1290[2] ,net1290[3] , net1290[4] ,net1290[5] ,net1290[6] ,net1290[7] } ), .out1 ({net1277[0] ,net1277[1] ,net1277[2] ,net1277[3] , net1277[4] } ), .in10 ({net0557[0] ,net0557[1] } ), .out25 ({net0699[0] ,net0699[1] ,net0699[2] ,net0699[3] , net0699[4] ,net0699[5] ,net0699[6] ,net0699[7] } ), .in25 ({net0691[0] ,net0691[1] ,net0691[2] ,net0691[3] , net0691[4] ,net0691[5] ,net0691[6] ,net0691[7] } ), .in1 ({net0565[0] ,net0565[1] ,net0565[2] ,net0565[3] , net0565[4] } ), .in4 ({net0562[0] ,net0562[1] } ), .in9 ({net0558[0] ,net0558[1] } ), .out21 (net1130 ), .out20 (net1296 ), .out19 (net1128 ), .out18 (net1294 ), .out17 (net1293 ), .out16 (net1125 ), .out15 (net1291 ), .out12 (net1121 ), .out8 (net1284 ), .out6 (net1115 ), .out5 (net1281 ), .out3 (net1279 ), .out2 (net1278 ), .in21 (net1004 ), .in20 (net1003 ), .in19 (net1002 ), .in18 (net1001 ), .in17 (net1171 ), .in16 (net999 ), .in15 (net0552 ), .in12 (net0555 ), .out0 (net1104 ), .in22 (net0640 ), .out22 (net0544 ), .in24 (net0543 ), .out24 (net0639 ), .vdd18 (vdd_h ), .in2 (net0564 ), .in5 (net0561 ), .out11 (net1287 ), .in3 (net0563 ), .in11 (net0556 ), .in0 (net0566 ), .in6 (net0560 ), .in8 (net0559 ) ); bw_io_ddr_rptr_b I279 ( .out14 ({net1106[0] ,net1106[1] ,net1106[2] ,net1106[3] , net1106[4] ,net1106[5] ,net1106[6] ,net1106[7] } ), .out13 ({net1107[0] ,net1107[1] ,net1107[2] ,net1107[3] , net1107[4] ,net1107[5] ,net1107[6] ,net1107[7] } ), .out10 ({net964[0] ,net964[1] } ), .out9 ({net966[0] ,net966[1] } ), .out4 ({net1136[0] ,net1136[1] } ), .in14 ({net1145[0] ,net1145[1] ,net1145[2] ,net1145[3] , net1145[4] ,net1145[5] ,net1145[6] ,net1145[7] } ), .in13 ({net981[0] ,net981[1] ,net981[2] ,net981[3] , net981[4] ,net981[5] ,net981[6] ,net981[7] } ), .out1 ({net977[0] ,net977[1] ,net977[2] ,net977[3] , net977[4] } ), .in10 ({net1264[0] ,net1264[1] } ), .out25 ({net0895[0] ,net0895[1] ,net0895[2] ,net0895[3] , net0895[4] ,net0895[5] ,net0895[6] ,net0895[7] } ), .in25 ({net0648[0] ,net0648[1] ,net0648[2] ,net0648[3] , net0648[4] ,net0648[5] ,net0648[6] ,net0648[7] } ), .in1 ({net1103[0] ,net1103[1] ,net1103[2] ,net1103[3] , net1103[4] } ), .in4 ({net1097[0] ,net1097[1] } ), .in9 ({net1090[0] ,net1090[1] } ), .out21 (net983 ), .out20 (net982 ), .out19 (net1151 ), .out18 (net1150 ), .out17 (net1149 ), .out16 (net963 ), .out15 (net971 ), .out12 (net1144 ), .out8 (net974 ), .out6 (net968 ), .out5 (net1137 ), .out3 (net967 ), .out2 (net1134 ), .in21 (net1027 ), .in20 (net858 ), .in19 (net1025 ), .in18 (net837 ), .in17 (net1023 ), .in16 (net839 ), .in15 (net1096 ), .in12 (net1266 ), .out0 (net973 ), .in22 (net0832 ), .out22 (net0592 ), .in24 (net0591 ), .out24 (net0831 ), .vdd18 (vdd_h ), .in2 (net1101 ), .in5 (net1259 ), .out11 (net1143 ), .in3 (net1257 ), .in11 (net1089 ), .in0 (net1254 ), .in6 (net1260 ), .in8 (net1100 ) ); bw_io_ddr_6sig_x2_async I181 ( .serial_out ({serial_out[143:136] } ), .serial_in ({serial_in[143:136] } ), .afo ({afo[143:136] } ), .afi ({afi[143:136] } ), .vrefcode_i_l ({net0974[0] ,net0974[1] ,net0974[2] ,net0974[3] , net0974[4] ,net0974[5] ,net0974[6] ,net0974[7] } ), .vrefcode_i_r ({net0945[0] ,net0945[1] ,net0945[2] ,net0945[3] , net0945[4] ,net0945[5] ,net0945[6] ,net0945[7] } ), .dq_pad ({dram_cb } ), .io_dram_data_in ({\io_dram_ecc_in[15] ,\io_dram_ecc_in[14] , \io_dram_ecc_in[13] ,\io_dram_ecc_in[12] , \io_dram_ecc_in[11] ,\io_dram_ecc_in[10] ,\io_dram_ecc_in[9] ,\io_dram_ecc_in[8] } ), .io_dram_data_in_hi ({\io_dram_ecc_in[31] ,\io_dram_ecc_in[30] , \io_dram_ecc_in[29] ,\io_dram_ecc_in[28] , \io_dram_ecc_in[27] ,\io_dram_ecc_in[26] , \io_dram_ecc_in[25] ,\io_dram_ecc_in[24] } ), .data_neg ({\dram_io_data_out[287] ,\dram_io_data_out[286] , \dram_io_data_out[285] ,\dram_io_data_out[284] , \dram_io_data_out[283] ,\dram_io_data_out[282] , \dram_io_data_out[281] ,\dram_io_data_out[280] } ), .data_pos ({\dram_io_data_out[143] ,\dram_io_data_out[142] , \dram_io_data_out[141] ,\dram_io_data_out[140] , \dram_io_data_out[139] ,\dram_io_data_out[138] , \dram_io_data_out[137] ,\dram_io_data_out[136] } ), .dqs_pad ({\dram_dqs[35] ,\dram_dqs[26] } ), .lpf_code_i_r ({net0399[0] ,net0399[1] ,net0399[2] ,net0399[3] , net0399[4] } ), .dram_io_ptr_clk_inv_i_r ({net0402[0] ,net0402[1] } ), .pad_pos_cnt_i_r ({net0407[0] ,net0407[1] } ), .pad_neg_cnt_i_r ({net0408[0] ,net0408[1] } ), .cbu_i_r ({cbu_i_r } ), .cbd_i_r ({cbd_i_r } ), .lpf_code_i_l ({net0390[0] ,net0390[1] ,net0390[2] ,net0390[3] , net0390[4] } ), .dram_io_ptr_clk_inv_i_l ({net0381[0] ,net0381[1] } ), .pad_pos_cnt_i_l ({net0373[0] ,net0373[1] } ), .pad_neg_cnt_i_l ({net0371[0] ,net0371[1] } ), .cbu_i_l ({cbu_i_l } ), .cbd_i_l ({cbd_i_l } ), .ps_select_i_l (ps_select_i_l ), .testmode_l_i_l (net0387 ), .test_mode_i_l (net0879 ), .testmode_l_i_r (net0406 ), .test_mode_i_r (net0884 ), .pad_clk_so (pad_clk_so ), .async_pad_0 (spare_ddr_pin[1] ), .async_pad_1 (spare_ddr_pin[0] ), .ps_select_i_r (ps_select_i_r ), .bso (bso ), .ctl_data_0 (spare_ddr_data[1] ), .pad_clk_si (pad_clk_so3_si4 ), .bypass_enable_i_l (bypass_enable_i_l ), .vdd_h (vdd_h ), .strobe_i_r (net0393 ), .burst_length_four_i_r (net0401 ), .dram_io_pad_enable_i_r (net0403 ), .dram_io_drive_enable_i_r (net0404 ), .rst_l_i_r (net0400 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net0409 ), .dram_io_drive_data_i_r (net0410 ), .se_i_r (net0413 ), .mode_ctrl_i_r (mode_ctrl_i_r ), .shift_dr_i_r (shift_dr_i_r ), .clock_dr_i_r (clock_dr_i_r ), .hiz_n_i_r (hiz_n_i_r ), .update_dr_i_r (update_dr_i_r ), .strobe_i_l (net0386 ), .burst_length_four_i_l (net0374 ), .dram_io_pad_enable_i_l (net0389 ), .dram_io_drive_enable_i_l (dram_io_drive_enable_o_l ), .ctl_data_1 (spare_ddr_data[0] ), .rst_l_i_l (net0388 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net0372 ), .dram_io_drive_data_i_l (net0377 ), .se_i_l (se_o_l ), .mode_ctrl_i_l (mode_ctrl_i_l ), .shift_dr_i_l (shift_dr_i_l ), .clock_dr_i_l (clock_dr_i_l ), .hiz_n_i_l (hiz_n_i_l ), .update_dr_i_l (update_dr_i_l ), .rclk (rclk ), .bypass_enable_i_r (bypass_enable_i_r ), .bsi (bso3_bsi4 ) ); bw_io_ddr_rptr_b I280 ( .out14 ({net1122[0] ,net1122[1] ,net1122[2] ,net1122[3] , net1122[4] ,net1122[5] ,net1122[6] ,net1122[7] } ), .out13 ({net1290[0] ,net1290[1] ,net1290[2] ,net1290[3] , net1290[4] ,net1290[5] ,net1290[6] ,net1290[7] } ), .out10 ({net1164[0] ,net1164[1] } ), .out9 ({net1163[0] ,net1163[1] } ), .out4 ({net1158[0] ,net1158[1] } ), .in14 ({net1167[0] ,net1167[1] ,net1167[2] ,net1167[3] , net1167[4] ,net1167[5] ,net1167[6] ,net1167[7] } ), .in13 ({net997[0] ,net997[1] ,net997[2] ,net997[3] , net997[4] ,net997[5] ,net997[6] ,net997[7] } ), .out1 ({net1155[0] ,net1155[1] ,net1155[2] ,net1155[3] , net1155[4] } ), .in10 ({net1286[0] ,net1286[1] } ), .out25 ({net0844[0] ,net0844[1] ,net0844[2] ,net0844[3] , net0844[4] ,net0844[5] ,net0844[6] ,net0844[7] } ), .in25 ({net0699[0] ,net0699[1] ,net0699[2] ,net0699[3] , net0699[4] ,net0699[5] ,net0699[6] ,net0699[7] } ), .in1 ({net1277[0] ,net1277[1] ,net1277[2] ,net1277[3] , net1277[4] } ), .in4 ({net1280[0] ,net1280[1] } ), .in9 ({net1118[0] ,net1118[1] } ), .out21 (net1004 ), .out20 (net1003 ), .out19 (net1002 ), .out18 (net1001 ), .out17 (net1171 ), .out16 (net999 ), .out15 (net1169 ), .out12 (net1166 ), .out8 (net991 ), .out6 (net1160 ), .out5 (net1159 ), .out3 (net1157 ), .out2 (net1156 ), .in21 (net1049 ), .in20 (net879 ), .in19 (net1047 ), .in18 (net1046 ), .in17 (net1045 ), .in16 (net875 ), .in15 (net1291 ), .in12 (net1121 ), .out0 (net1154 ), .in22 (net0736 ), .out22 (net0640 ), .in24 (net0639 ), .out24 (net0735 ), .vdd18 (vdd_h ), .in2 (net1278 ), .in5 (net1281 ), .out11 (net994 ), .in3 (net1279 ), .in11 (net1287 ), .in0 (net1104 ), .in6 (net1115 ), .in8 (net1284 ) ); bw_io_ddr_rptr_b I281 ( .out14 ({net1145[0] ,net1145[1] ,net1145[2] ,net1145[3] , net1145[4] ,net1145[5] ,net1145[6] ,net1145[7] } ), .out13 ({net981[0] ,net981[1] ,net981[2] ,net981[3] , net981[4] ,net981[5] ,net981[6] ,net981[7] } ), .out10 ({net1016[0] ,net1016[1] } ), .out9 ({net1015[0] ,net1015[1] } ), .out4 ({net848[0] ,net848[1] } ), .in14 ({net856[0] ,net856[1] ,net856[2] ,net856[3] , net856[4] ,net856[5] ,net856[6] ,net856[7] } ), .in13 ({net857[0] ,net857[1] ,net857[2] ,net857[3] , net857[4] ,net857[5] ,net857[6] ,net857[7] } ), .out1 ({net1007[0] ,net1007[1] ,net1007[2] ,net1007[3] , net1007[4] } ), .in10 ({net964[0] ,net964[1] } ), .out25 ({net0742[0] ,net0742[1] ,net0742[2] ,net0742[3] , net0742[4] ,net0742[5] ,net0742[6] ,net0742[7] } ), .in25 ({net0895[0] ,net0895[1] ,net0895[2] ,net0895[3] , net0895[4] ,net0895[5] ,net0895[6] ,net0895[7] } ), .in1 ({net977[0] ,net977[1] ,net977[2] ,net977[3] , net977[4] } ), .in4 ({net1136[0] ,net1136[1] } ), .in9 ({net966[0] ,net966[1] } ), .out21 (net1027 ), .out20 (net858 ), .out19 (net1025 ), .out18 (net837 ), .out17 (net1023 ), .out16 (net839 ), .out15 (net847 ), .out12 (net846 ), .out8 (net850 ), .out6 (net844 ), .out5 (net852 ), .out3 (net843 ), .out2 (net1008 ), .in21 (net0398 ), .in20 (net0397 ), .in19 (net0369 ), .in18 (net0368 ), .in17 (net0394 ), .in16 (net0370 ), .in15 (net971 ), .in12 (net1144 ), .out0 (net1006 ), .in22 (net0688 ), .out22 (net0832 ), .in24 (net0831 ), .out24 (net0687 ), .vdd18 (vdd_h ), .in2 (net1134 ), .in5 (net1137 ), .out11 (net1017 ), .in3 (net967 ), .in11 (net1143 ), .in0 (net973 ), .in6 (net968 ), .in8 (net974 ) ); bw_io_ddr_rptr_b I282 ( .out14 ({net1167[0] ,net1167[1] ,net1167[2] ,net1167[3] , net1167[4] ,net1167[5] ,net1167[6] ,net1167[7] } ), .out13 ({net997[0] ,net997[1] ,net997[2] ,net997[3] , net997[4] ,net997[5] ,net997[6] ,net997[7] } ), .out10 ({net1038[0] ,net1038[1] } ), .out9 ({net868[0] ,net868[1] } ), .out4 ({net863[0] ,net863[1] } ), .in14 ({net872[0] ,net872[1] ,net872[2] ,net872[3] , net872[4] ,net872[5] ,net872[6] ,net872[7] } ), .in13 ({net1042[0] ,net1042[1] ,net1042[2] ,net1042[3] , net1042[4] ,net1042[5] ,net1042[6] ,net1042[7] } ), .out1 ({net1029[0] ,net1029[1] ,net1029[2] ,net1029[3] , net1029[4] } ), .in10 ({net1164[0] ,net1164[1] } ), .out25 ({net0845[0] ,net0845[1] ,net0845[2] ,net0845[3] , net0845[4] ,net0845[5] ,net0845[6] ,net0845[7] } ), .in25 ({net0844[0] ,net0844[1] ,net0844[2] ,net0844[3] , net0844[4] ,net0844[5] ,net0844[6] ,net0844[7] } ), .in1 ({net1155[0] ,net1155[1] ,net1155[2] ,net1155[3] , net1155[4] } ), .in4 ({net1158[0] ,net1158[1] } ), .in9 ({net1163[0] ,net1163[1] } ), .out21 (net1049 ), .out20 (net879 ), .out19 (net1047 ), .out18 (net1046 ), .out17 (net1045 ), .out16 (net875 ), .out15 (net1043 ), .out12 (net871 ), .out8 (net1036 ), .out6 (net865 ), .out5 (net1033 ), .out3 (net862 ), .out2 (net1030 ), .in21 (net0419 ), .in20 (net0418 ), .in19 (net0417 ), .in18 (net0416 ), .in17 (net0415 ), .in16 (net0414 ), .in15 (net1169 ), .in12 (net1166 ), .out0 (net1028 ), .in22 (net0784 ), .out22 (net0736 ), .in24 (net0735 ), .out24 (net0783 ), .vdd18 (vdd_h ), .in2 (net1156 ), .in5 (net1159 ), .out11 (net870 ), .in3 (net1157 ), .in11 (net994 ), .in0 (net1154 ), .in6 (net1160 ), .in8 (net991 ) ); bw_io_ddr_rptr_b I283 ( .out14 ({net856[0] ,net856[1] ,net856[2] ,net856[3] , net856[4] ,net856[5] ,net856[6] ,net856[7] } ), .out13 ({net857[0] ,net857[1] ,net857[2] ,net857[3] , net857[4] ,net857[5] ,net857[6] ,net857[7] } ), .out10 ({net0371[0] ,net0371[1] } ), .out9 ({net0373[0] ,net0373[1] } ), .out4 ({net0381[0] ,net0381[1] } ), .in14 ({cbd_i_l } ), .in13 ({cbu_i_l } ), .out1 ({net0390[0] ,net0390[1] ,net0390[2] ,net0390[3] , net0390[4] } ), .in10 ({net1016[0] ,net1016[1] } ), .out25 ({net0974[0] ,net0974[1] ,net0974[2] ,net0974[3] , net0974[4] ,net0974[5] ,net0974[6] ,net0974[7] } ), .in25 ({net0742[0] ,net0742[1] ,net0742[2] ,net0742[3] , net0742[4] ,net0742[5] ,net0742[6] ,net0742[7] } ), .in1 ({net1007[0] ,net1007[1] ,net1007[2] ,net1007[3] , net1007[4] } ), .in4 ({net848[0] ,net848[1] } ), .in9 ({net1015[0] ,net1015[1] } ), .out21 (net0398 ), .out20 (net0397 ), .out19 (net0369 ), .out18 (net0368 ), .out17 (net0394 ), .out16 (net0370 ), .out15 (se_o_l ), .out12 (net0377 ), .out8 (net0387 ), .out6 (dram_io_drive_enable_o_l ), .out5 (net0389 ), .out3 (net0374 ), .out2 (net0388 ), .in21 (bypass_enable_i_l ), .in20 (hiz_n_i_l ), .in19 (clock_dr_i_l ), .in18 (shift_dr_i_l ), .in17 (update_dr_i_l ), .in16 (mode_ctrl_i_l ), .in15 (net847 ), .in12 (net846 ), .out0 (net0386 ), .in22 (ps_select_i_l ), .out22 (net0688 ), .in24 (net0687 ), .out24 (net0879 ), .vdd18 (vdd_h ), .in2 (net1008 ), .in5 (net852 ), .out11 (net0372 ), .in3 (net843 ), .in11 (net1017 ), .in0 (net1006 ), .in6 (net844 ), .in8 (net850 ) ); bw_io_ddr_rptr_b I284 ( .out14 ({net872[0] ,net872[1] ,net872[2] ,net872[3] , net872[4] ,net872[5] ,net872[6] ,net872[7] } ), .out13 ({net1042[0] ,net1042[1] ,net1042[2] ,net1042[3] , net1042[4] ,net1042[5] ,net1042[6] ,net1042[7] } ), .out10 ({net0408[0] ,net0408[1] } ), .out9 ({net0407[0] ,net0407[1] } ), .out4 ({net0402[0] ,net0402[1] } ), .in14 ({cbd_i_r } ), .in13 ({cbu_i_r } ), .out1 ({net0399[0] ,net0399[1] ,net0399[2] ,net0399[3] , net0399[4] } ), .in10 ({net1038[0] ,net1038[1] } ), .out25 ({net0945[0] ,net0945[1] ,net0945[2] ,net0945[3] , net0945[4] ,net0945[5] ,net0945[6] ,net0945[7] } ), .in25 ({net0845[0] ,net0845[1] ,net0845[2] ,net0845[3] , net0845[4] ,net0845[5] ,net0845[6] ,net0845[7] } ), .in1 ({net1029[0] ,net1029[1] ,net1029[2] ,net1029[3] , net1029[4] } ), .in4 ({net863[0] ,net863[1] } ), .in9 ({net868[0] ,net868[1] } ), .out21 (net0419 ), .out20 (net0418 ), .out19 (net0417 ), .out18 (net0416 ), .out17 (net0415 ), .out16 (net0414 ), .out15 (net0413 ), .out12 (net0410 ), .out8 (net0406 ), .out6 (net0404 ), .out5 (net0403 ), .out3 (net0401 ), .out2 (net0400 ), .in21 (bypass_enable_i_r ), .in20 (hiz_n_i_r ), .in19 (clock_dr_i_r ), .in18 (shift_dr_i_r ), .in17 (update_dr_i_r ), .in16 (mode_ctrl_i_r ), .in15 (net1043 ), .in12 (net871 ), .out0 (net0393 ), .in22 (ps_select_i_r ), .out22 (net0784 ), .in24 (net0783 ), .out24 (net0884 ), .vdd18 (vdd_h ), .in2 (net1030 ), .in5 (net1033 ), .out11 (net0409 ), .in3 (net862 ), .in11 (net870 ), .in0 (net1028 ), .in6 (net865 ), .in8 (net1036 ) ); assign arst_l_out = arst_l_i_l; endmodule
/*********************************************************************************************************************** * Copyright (C) 2016 Andrew Zonenberg and contributors * * * * This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General * * Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) * * any later version. * * * * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied * * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for * * more details. * * * * You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may * * find one here: * * https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt * * or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software * * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA * ********************************************************************************************************************/ `default_nettype none / @brief HiL test case for GP_LFOSC OUTPUTS: Oscillator output, divided by 2 (should be ~865 Hz) / module LFOsc(clkout); //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // I/O declarations ( LOC = "P13" *) output wire clkout; //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // The oscillator GP_LFOSC #( .PWRDN_EN(0), .AUTO_PWRDN(0), .OUT_DIV(2) ) lfosc ( .PWRDN(1'b0), .CLKOUT(clkout) ); endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Read Data Response AXI3 Slave Converter // Forwards and re-assembles split transactions. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // r_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_r_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire cmd_split, output wire cmd_ready, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Throttling help signals. wire cmd_ready_i; wire pop_si_data; wire si_stalling; // Internal MI-side control signals. wire M_AXI_RREADY_I; // Internal signals for SI-side. wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I; wire [2-1:0] S_AXI_RRESP_I; wire S_AXI_RLAST_I; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I; wire S_AXI_RVALID_I; wire S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from MI-Side to SI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign M_AXI_RREADY_I = ~si_stalling & cmd_valid; assign M_AXI_RREADY = M_AXI_RREADY_I; // Indicate when there is data available @ SI-side. assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid; // Get SI-side data. assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Simple AXI signal forwarding: // // USER, ID, DATA and RRESP passes through untouched. // // LAST has to be filtered to remove any intermediate LAST (due to split // trasactions). LAST is only removed for the first parts of a split // transaction. When splitting is unsupported is the LAST filtering completely // completely removed. // ///////////////////////////////////////////////////////////////////////////// // Calculate last, i.e. mask from split transactions. assign S_AXI_RLAST_I = M_AXI_RLAST & ( ~cmd_split \| ( C_SUPPORT_SPLITTING == 0 ) ); // Data is passed through. assign S_AXI_RID_I = M_AXI_RID; assign S_AXI_RUSER_I = M_AXI_RUSER; assign S_AXI_RDATA_I = M_AXI_RDATA; assign S_AXI_RRESP_I = M_AXI_RRESP; ///////////////////////////////////////////////////////////////////////////// // SI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign S_AXI_RREADY_I = S_AXI_RREADY; assign S_AXI_RVALID = S_AXI_RVALID_I; assign S_AXI_RID = S_AXI_RID_I; assign S_AXI_RDATA = S_AXI_RDATA_I; assign S_AXI_RRESP = S_AXI_RRESP_I; assign S_AXI_RLAST = S_AXI_RLAST_I; assign S_AXI_RUSER = S_AXI_RUSER_I; endmodule
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PCÎ¬»¤ºÍ¸üÐÂ PCÎ¬»¤ºÍ¸üÐÂÓÐÁ½ÖÖÇé¿öÐèÒª·Ö¿ª´¦Àí £¨1£©Á÷Ë®Ïß¶³½áÊ±£¬±£³ÖÏÖÓÐÈ¡Ö¸µØÖ·PC£¬´ý¶³½á½â³ýºó¼ÌÐøÈ¡Ö¸ £¨2£©Á÷Ë®ÏßË¢ÐÂÊ±£¬ÐèÒª·ÅÆúÏÖÓÐPC£¬´ýË¢ÐÂÍê³Éºó·Ö±ðÊ¹ÓÃnpc_xxxÖØÐÂÈ¡Ö¸ pc_freezeÔÚ´ÓÓÐÐ§×´Ì¬»Ö¸´Ê±£¬ * List2do: * [TBV] timing relationship between flushpipe and freeze. * / // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "def_pippo.v" module pippo_pipectrl( flush_except, flush_branch, flushpipe, if_stall, lsu_stall, multicycle_cnt, asyn_stall, pc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze ); // // I/O // // stall request from pipeline stages input if_stall; input lsu_stall; input asyn_stall; input [1:0] multicycle_cnt; // freeze command to pipeline stages output pc_freeze; output if_freeze; output id_freeze; output ex_freeze; output wb_freeze; // flush control input flush_except; input flush_branch; output flushpipe; // // Internal wires and regs // wire multicycle_stall; // // flush pipelining // at the last cycle of flushpipe assertion, new fetch address will send to pc register // 1. when flush is raised by except processing, assert for two cycles. // 2. when flush is raised by branch processing, assert for one cycle. // assign flushpipe = flush_except \| flush_branch; // // PC freeze signal // // pc_freeze is just for dis-asserting fetch request assign pc_freeze = flushpipe; // // Pipeline freeze generation: // assign multicycle_stall = \|multicycle_cnt; // notes for asyn_stall: see except module assign if_freeze = if_stall \| id_freeze; assign id_freeze = ex_freeze; assign ex_freeze = wb_freeze \| asyn_stall; assign wb_freeze = lsu_stall \| multicycle_stall; / Implementation: Memory access instructions with update, under 3r1w rf design a. Load with update instructions pipectrl.v ×¢Òâ£ºmulticycle_stallÌõ¼þÒ²Ðë±ä»¯£¬µ±wb_twiceÓÐÐ§Ê±£¬ÏÂÒ»ÌõÖ¸ÁîÒýÆðmulticycle_stall²»ÄÜÖÃÆð rf.v we & (~wb_freeze \| wb_at_fze) //write enable logic wb_twice come from rfwbop, and more to do: 1. logic for write address and source 2. write order of EA and loaded data? 3. wb_atfzeÓÐÐ§Ê±¼äÖ»ÄÜÒ»ÅÄ b. Store with update instructions ×¢ÒâÐèÒªÍ¬²½storeµÄÍê³ÉºÍupdate£¨Ð´EA»ØRA£©µÄÍê³É Logic.a: ¿ÉÒÔÐ´»ØÊ±£¬¶³½áwb£¬Ð´»ØÒ»´Î£¬ÔÙ½â¶³Íê³ÉµÚ¶þ´ÎÐ´»Ø£» pipectrl.v //wb_atfze means: wb_freeze is asserted by wb_twice only, at this case, write-back can go. assign wb_freeze_a = lsu_stall \| multicycle_stall; assign wb_freeze = wb_freeze_a \| wb_atfze; always @(posedge clk or posedge rst) begin if (rst) wb_atfze <= #1 1'b0; else if(wb_freeze_a) wb_atfze <= #1 rfwb_uops[0] & rfwb_uops[1]; else wb_atfze <= #1 1'b0; end reg_gprs.v assign rf_we = (~flushpipe) & ((wea & ~wb_freeze) \|(wea & wb_atfze) \| (web & ~wb_freeze)) ; assign rf_addrw = wea & (!web \| wb_atfze) ? addrwa : web ? addrwb : 5'd0; assign rf_dataw = wea & (!web \| wb_atfze) ? datawa : web ? datawb : 32'd0; operandmux.v/wbmux.v Èç¹ûÊ¹ÓÃ×ª·¢Âß¼£¬ÔòwraºÍwrbµÄ×ª·¢ÐèÒªÔö¼ÓÓÐÐ§Âß¼£»¼Æ»®ÊµÏÖÓÚwbmuxÄ£¿é (gpr_addr_rda == ex_gpr_addr_wra) && (ex_rfwb_uops[0] & !ex_rfwb_uops[1]) (gpr_addr_rda == ex_gpr_addr_wrb) && (ex_rfwb_uops[1] & !wb_atfze) Logic.b: ÏÈÐ´»ØÒ»´Î£¬ÔÙ¶³½áwb¶ÎÍê³ÉµÚ¶þ´ÎÐ´»Ø£»µ¼ÖÂÎÊÌâ£º 1£¬ÏÂÒ»ÌõÖ¸ÁîÒÑ¾½øÈëexe¶Î£¬Èç¹ûÊÇ¶àÖÜÆÚÖ¸ÁîÔò»áµ¼ÖÂwb_atfze±£³ÖÓÐÐ§ 2£¬ÐèÒª¼Ä´æaddr_wrºÍeaµÈ assign wb_freeze_a = lsu_stall \| multicycle_stall; assign wb_freeze = wb_freeze_a \| wb_atfze; always @(posedge clk or posedge rst) begin if (rst) wb_atfze <= #1 1'b0; else if(!wb_freeze_a) wb_atfze <= #1 rfwb_uops[0] & rfwb_uops[1]; end */ endmodule
module iir (clk, reset, start, din, params, dout, ready,iir_start,iir_done); input clk, reset, start; input [7:0] din; input [15:0] params; output [7:0] dout; reg [7:0] dout; output ready; reg ready; reg temp_ready; reg [6:0] finite_counter; wire count0; input iir_start; output iir_done; wire iir_done; reg del_count0; reg [15:0] a1, a2, b0, b1, b2, yk1, yk2; reg [7:0] uk, uk1, uk2 ; reg [28:0] ysum ; reg [26:0] yk ; reg [22:0] utmp; reg [3:0] wait_counter ; // temporary variable wire [31:0] yo1, yo2; //wire [23:0] b0t, b1t, b2t; wire [22:0] b0t, b1t, b2t; wire [22:0] b0tpaj, b1tpaj, b2tpaj; reg [3:0] obf_state, obf_next_state ; reg [7:0] temp_uk, temp_uk1, temp_uk2 ; reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2; reg [28:0] temp_ysum ; reg [26:0] temp_yk ; reg [22:0] temp_utmp; reg [7:0] temp_dout; reg [3:0] temp_wait_counter ; parameter idle = 4'b0001 , load_a2 = 4'b0010 , load_b0 = 4'b0011 , load_b1 = 4'b0100 , load_b2 = 4'b0101 , wait4_start = 4'b0110 , latch_din = 4'b0111 , compute_a = 4'b1000 , compute_b = 4'b1001 , compute_yk = 4'b1010 , wait4_count = 4'b1011 , latch_dout = 4'b1100 ; always @(obf_state or start or din or wait_counter or iir_start or count0) begin case (obf_state ) idle : begin if (iir_start) obf_next_state = load_a2 ; else obf_next_state = idle; temp_a1 = params ; end load_a2 : begin obf_next_state = load_b0 ; temp_a2 = params ; end load_b0 : begin obf_next_state = load_b1 ; temp_b0 = params ; end load_b1 : begin obf_next_state = load_b2 ; temp_b1 = params ; end load_b2 : begin obf_next_state = wait4_start ; temp_b2 = params ; end wait4_start : begin if (start) begin obf_next_state = latch_din ; temp_uk = din ; end else begin obf_next_state = wait4_start ; temp_uk = uk; end temp_ready = wait4_start; end latch_din : begin obf_next_state = compute_a ; end compute_a : begin obf_next_state = compute_b ; temp_ysum = yo1[31:3] + yo2[31:3]; end compute_b : begin obf_next_state = compute_yk ; // temp_utmp = b0t[23:0] + b1t[23:0] + b2t[23:0]; temp_utmp = b0t + b1t + b2t; end compute_yk : begin obf_next_state = wait4_count ; temp_uk1 = uk ; temp_uk2 = uk1 ; temp_yk = ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp}; temp_wait_counter = 4 ; end wait4_count : begin if (wait_counter==0 ) begin obf_next_state = latch_dout ; temp_dout = yk[26:19]; temp_yk1 = yk[26:11] ; temp_yk2 = yk1 ; end else begin obf_next_state = wait4_count ; temp_dout = dout; temp_yk1 = yk1; //temp_yk2 = yk2; end temp_wait_counter = wait_counter - 1; end latch_dout : if (count0) obf_next_state = idle; else obf_next_state = wait4_start ; endcase end //assign yo1 = mul_tc_16_16(yk1, a1, clk); assign yo1 = yk1 * a1; //assign yo2 = mul_tc_16_16(yk2, a2, clk); assign yo2 = yk2a2; //assign b0t = mul_tc_8_16(uk, b0, clk); //assign b1t = mul_tc_8_16(uk1, b1, clk); //assign b2t = mul_tc_8_16(uk2, b2, clk); assign b0t = ukb0; assign b1t = uk1b1; assign b2t = uk2b2; // paj added to solve unused high order bit assign b0tpaj = b0t; assign b1tpaj = b1t; assign b2tpaj = b2t; // A COEFFICENTS always @(posedge clk or posedge reset) begin if (reset ) begin uk <= 0 ; uk1 <= 0 ; uk2 <= 0 ; yk1 <= 0 ; yk2 <= 0 ; yk <= 0 ; ysum <= 0 ; utmp <= 0 ; a1 <= 0 ; a2 <= 0 ; b0 <= 0 ; b1 <= 0 ; b2 <= 0 ; dout <= 0 ; obf_state <= idle ; ready <= 0; end else begin obf_state <= obf_next_state ; uk1 <= temp_uk1; uk2 <= temp_uk2; yk <= temp_yk; uk <= temp_uk ; a1 <= temp_a1 ; a2 <= temp_a2 ; b0 <= temp_b0 ; b1 <= temp_b1 ; b2 <= temp_b2 ; ysum <= temp_ysum; utmp <= temp_utmp; dout <= temp_dout; yk1 <= temp_yk1; yk2 <= temp_yk2; ready <= temp_ready; end end // wait counter, count 4 clock after sum is calculated, to // time outputs are ready, and filter is ready to accept next // input always @(posedge clk or posedge reset ) begin if (reset ) wait_counter <= 0 ; else begin wait_counter <= temp_wait_counter ; end end always @(posedge clk) begin if (reset) finite_counter<=100; else if (iir_start) finite_counter<=finite_counter -1; else finite_counter<=finite_counter; end assign count0=finite_counter==7'b0; always @(posedge clk) begin del_count0 <= count0; end assign iir_done = (count0 && ~del_count0); endmodule
`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:38:39 08/19/2014 // Design Name: satadd // Module Name: C:/ece4743/projects/lab2_solution_part1/tb_satadd.v // Project Name: lab2_solution_part1 // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: satadd // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module tb_satadd; // Inputs reg [11:0] a; reg [11:0] b; reg [1:0] mode; // Outputs wire [11:0] y; reg[8*100:1] aline; integer fd; integer count,status; integer i_a, i_b, i_mode, i_result; integer errors; // Instantiate the Unit Under Test (UUT) satadd uut ( .a(a), .b(b), .mode(mode), .y(y) ); initial begin // Initialize Inputs a = 0; b = 0; mode = 0; fd = $fopen("test_out.txt","w"); $fclose(fd); fd = $fopen("satadd_vectors.txt","r"); count = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here errors = 0; while ($fgets(aline,fd)) begin status = $sscanf(aline,"%x %x %x %x",i_mode, i_a, i_b, i_result); a = i_a; b = i_b; mode = i_mode; #10 //delay if (i_result == y) begin $display("PASS, mode: %x, a: %x, b: %x, y: %x\n",mode,a,b,y); end else begin $display("FAIL, mode: %x, a: %x, b: %x, y (actual): %x, y (expected): %x\n",mode,a,b,y,i_result); errors = errors + 1; end end //end while if (errors == 0) $display("PASS: All vectors pased.\n"); else $display ("FAIL: %d vectors failed\n",errors); end endmodule
// hps_sdram.v // This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes // will probably be lost. // // Generated using ACDS version 16.1 196 `timescale 1 ps / 1 ps module hps_sdram ( input wire pll_ref_clk, // pll_ref_clk.clk input wire global_reset_n, // global_reset.reset_n input wire soft_reset_n, // soft_reset.reset_n output wire [14:0] mem_a, // memory.mem_a output wire [2:0] mem_ba, // .mem_ba output wire [0:0] mem_ck, // .mem_ck output wire [0:0] mem_ck_n, // .mem_ck_n output wire [0:0] mem_cke, // .mem_cke output wire [0:0] mem_cs_n, // .mem_cs_n output wire [3:0] mem_dm, // .mem_dm output wire [0:0] mem_ras_n, // .mem_ras_n output wire [0:0] mem_cas_n, // .mem_cas_n output wire [0:0] mem_we_n, // .mem_we_n output wire mem_reset_n, // .mem_reset_n inout wire [31:0] mem_dq, // .mem_dq inout wire [3:0] mem_dqs, // .mem_dqs inout wire [3:0] mem_dqs_n, // .mem_dqs_n output wire [0:0] mem_odt, // .mem_odt input wire oct_rzqin // oct.rzqin ); wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk] wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk] wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl hps_sdram_pll pll ( .global_reset_n (global_reset_n), // global_reset.reset_n .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk .pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk .pll_locked (pll_pll_sharing_pll_locked), // .pll_locked .pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk .pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk .pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk .pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk .afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk .pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk ); hps_sdram_p0 p0 ( .global_reset_n (global_reset_n), // global_reset.reset_n .soft_reset_n (soft_reset_n), // soft_reset.reset_n .afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n .afi_reset_export_n (), // afi_reset_export.reset_n .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk .avl_clk (), // avl_clk.clk .avl_reset_n (), // avl_reset.reset_n .scc_clk (), // scc_clk.clk .scc_reset_n (), // scc_reset.reset_n .avl_address (), // avl.address .avl_write (), // .write .avl_writedata (), // .writedata .avl_read (), // .read .avl_readdata (), // .readdata .avl_waitrequest (), // .waitrequest .dll_clk (p0_dll_clk_clk), // dll_clk.clk .afi_addr (c0_afi_afi_addr), // afi.afi_addr .afi_ba (c0_afi_afi_ba), // .afi_ba .afi_cke (c0_afi_afi_cke), // .afi_cke .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n .afi_we_n (c0_afi_afi_we_n), // .afi_we_n .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n .afi_odt (c0_afi_afi_odt), // .afi_odt .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid .afi_wdata (c0_afi_afi_wdata), // .afi_wdata .afi_dm (c0_afi_afi_dm), // .afi_dm .afi_rdata (p0_afi_afi_rdata), // .afi_rdata .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid .afi_wlat (p0_afi_afi_wlat), // .afi_wlat .afi_rlat (p0_afi_afi_rlat), // .afi_rlat .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail .scc_data (), // scc.scc_data .scc_dqs_ena (), // .scc_dqs_ena .scc_dqs_io_ena (), // .scc_dqs_io_ena .scc_dq_ena (), // .scc_dq_ena .scc_dm_ena (), // .scc_dm_ena .capture_strobe_tracking (), // .capture_strobe_tracking .scc_upd (), // .scc_upd .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable .pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk .pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk .pll_locked (pll_pll_sharing_pll_locked), // .pll_locked .pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk .pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk .pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk .pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk .afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk .pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked .dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl .seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol .parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol .mem_a (mem_a), // memory.mem_a .mem_ba (mem_ba), // .mem_ba .mem_ck (mem_ck), // .mem_ck .mem_ck_n (mem_ck_n), // .mem_ck_n .mem_cke (mem_cke), // .mem_cke .mem_cs_n (mem_cs_n), // .mem_cs_n .mem_dm (mem_dm), // .mem_dm .mem_ras_n (mem_ras_n), // .mem_ras_n .mem_cas_n (mem_cas_n), // .mem_cas_n .mem_we_n (mem_we_n), // .mem_we_n .mem_reset_n (mem_reset_n), // .mem_reset_n .mem_dq (mem_dq), // .mem_dq .mem_dqs (mem_dqs), // .mem_dqs .mem_dqs_n (mem_dqs_n), // .mem_dqs_n .mem_odt (mem_odt), // .mem_odt .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess .csr_soft_reset_req (1'b0), // (terminated) .io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intbadout (12'b000000000000), // (terminated) .io_intcasndout (4'b0000), // (terminated) .io_intckdout (4'b0000), // (terminated) .io_intckedout (8'b00000000), // (terminated) .io_intckndout (4'b0000), // (terminated) .io_intcsndout (8'b00000000), // (terminated) .io_intdmdout (20'b00000000000000000000), // (terminated) .io_intdqdin (), // (terminated) .io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intdqsbdout (20'b00000000000000000000), // (terminated) .io_intdqsboe (10'b0000000000), // (terminated) .io_intdqsdout (20'b00000000000000000000), // (terminated) .io_intdqslogicdqsena (10'b0000000000), // (terminated) .io_intdqslogicfiforeset (5'b00000), // (terminated) .io_intdqslogicincrdataen (10'b0000000000), // (terminated) .io_intdqslogicincwrptr (10'b0000000000), // (terminated) .io_intdqslogicoct (10'b0000000000), // (terminated) .io_intdqslogicrdatavalid (), // (terminated) .io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated) .io_intdqsoe (10'b0000000000), // (terminated) .io_intodtdout (8'b00000000), // (terminated) .io_intrasndout (4'b0000), // (terminated) .io_intresetndout (4'b0000), // (terminated) .io_intwendout (4'b0000), // (terminated) .io_intafirlat (), // (terminated) .io_intafiwlat () // (terminated) ); altera_mem_if_hhp_qseq_synth_top #( .MEM_IF_DM_WIDTH (4), .MEM_IF_DQS_WIDTH (4), .MEM_IF_CS_WIDTH (1), .MEM_IF_DQ_WIDTH (32) ) seq ( ); altera_mem_if_hard_memory_controller_top_cyclonev #( .MEM_IF_DQS_WIDTH (4), .MEM_IF_CS_WIDTH (1), .MEM_IF_CHIP_BITS (1), .MEM_IF_CLK_PAIR_COUNT (1), .CSR_ADDR_WIDTH (10), .CSR_DATA_WIDTH (8), .CSR_BE_WIDTH (1), .AVL_ADDR_WIDTH (27), .AVL_DATA_WIDTH (64), .AVL_SIZE_WIDTH (3), .AVL_DATA_WIDTH_PORT_0 (1), .AVL_ADDR_WIDTH_PORT_0 (1), .AVL_NUM_SYMBOLS_PORT_0 (1), .LSB_WFIFO_PORT_0 (5), .MSB_WFIFO_PORT_0 (5), .LSB_RFIFO_PORT_0 (5), .MSB_RFIFO_PORT_0 (5), .AVL_DATA_WIDTH_PORT_1 (1), .AVL_ADDR_WIDTH_PORT_1 (1), .AVL_NUM_SYMBOLS_PORT_1 (1), .LSB_WFIFO_PORT_1 (5), .MSB_WFIFO_PORT_1 (5), .LSB_RFIFO_PORT_1 (5), .MSB_RFIFO_PORT_1 (5), .AVL_DATA_WIDTH_PORT_2 (1), .AVL_ADDR_WIDTH_PORT_2 (1), .AVL_NUM_SYMBOLS_PORT_2 (1), .LSB_WFIFO_PORT_2 (5), .MSB_WFIFO_PORT_2 (5), .LSB_RFIFO_PORT_2 (5), .MSB_RFIFO_PORT_2 (5), .AVL_DATA_WIDTH_PORT_3 (1), .AVL_ADDR_WIDTH_PORT_3 (1), .AVL_NUM_SYMBOLS_PORT_3 (1), .LSB_WFIFO_PORT_3 (5), .MSB_WFIFO_PORT_3 (5), .LSB_RFIFO_PORT_3 (5), .MSB_RFIFO_PORT_3 (5), .AVL_DATA_WIDTH_PORT_4 (1), .AVL_ADDR_WIDTH_PORT_4 (1), .AVL_NUM_SYMBOLS_PORT_4 (1), .LSB_WFIFO_PORT_4 (5), .MSB_WFIFO_PORT_4 (5), .LSB_RFIFO_PORT_4 (5), .MSB_RFIFO_PORT_4 (5), .AVL_DATA_WIDTH_PORT_5 (1), .AVL_ADDR_WIDTH_PORT_5 (1), .AVL_NUM_SYMBOLS_PORT_5 (1), .LSB_WFIFO_PORT_5 (5), .MSB_WFIFO_PORT_5 (5), .LSB_RFIFO_PORT_5 (5), .MSB_RFIFO_PORT_5 (5), .ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"), .ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"), .ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"), .ENUM_CAL_REQ ("DISABLED"), .ENUM_CFG_BURST_LENGTH ("BL_8"), .ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"), .ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"), .ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"), .ENUM_CFG_TYPE ("DDR3"), .ENUM_CLOCK_OFF_0 ("DISABLED"), .ENUM_CLOCK_OFF_1 ("DISABLED"), .ENUM_CLOCK_OFF_2 ("DISABLED"), .ENUM_CLOCK_OFF_3 ("DISABLED"), .ENUM_CLOCK_OFF_4 ("DISABLED"), .ENUM_CLOCK_OFF_5 ("DISABLED"), .ENUM_CLR_INTR ("NO_CLR_INTR"), .ENUM_CMD_PORT_IN_USE_0 ("FALSE"), .ENUM_CMD_PORT_IN_USE_1 ("FALSE"), .ENUM_CMD_PORT_IN_USE_2 ("FALSE"), .ENUM_CMD_PORT_IN_USE_3 ("FALSE"), .ENUM_CMD_PORT_IN_USE_4 ("FALSE"), .ENUM_CMD_PORT_IN_USE_5 ("FALSE"), .ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT0_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT0_TYPE ("DISABLE"), .ENUM_CPORT0_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT1_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT1_TYPE ("DISABLE"), .ENUM_CPORT1_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT2_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT2_TYPE ("DISABLE"), .ENUM_CPORT2_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT3_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT3_TYPE ("DISABLE"), .ENUM_CPORT3_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT4_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT4_TYPE ("DISABLE"), .ENUM_CPORT4_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT5_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT5_TYPE ("DISABLE"), .ENUM_CPORT5_WFIFO_MAP ("FIFO_0"), .ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"), .ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"), .ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"), .ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"), .ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"), .ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"), .ENUM_DELAY_BONDING ("BONDING_LATENCY_0"), .ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"), .ENUM_DISABLE_MERGING ("MERGING_ENABLED"), .ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"), .ENUM_ENABLE_ATPG ("DISABLED"), .ENUM_ENABLE_BONDING_0 ("DISABLED"), .ENUM_ENABLE_BONDING_1 ("DISABLED"), .ENUM_ENABLE_BONDING_2 ("DISABLED"), .ENUM_ENABLE_BONDING_3 ("DISABLED"), .ENUM_ENABLE_BONDING_4 ("DISABLED"), .ENUM_ENABLE_BONDING_5 ("DISABLED"), .ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"), .ENUM_ENABLE_DQS_TRACKING ("ENABLED"), .ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"), .ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"), .ENUM_ENABLE_INTR ("DISABLED"), .ENUM_ENABLE_NO_DM ("DISABLED"), .ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"), .ENUM_GANGED_ARF ("DISABLED"), .ENUM_GEN_DBE ("GEN_DBE_DISABLED"), .ENUM_GEN_SBE ("GEN_SBE_DISABLED"), .ENUM_INC_SYNC ("FIFO_SET_2"), .ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"), .ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"), .ENUM_MASK_DBE_INTR ("DISABLED"), .ENUM_MASK_SBE_INTR ("DISABLED"), .ENUM_MEM_IF_AL ("AL_0"), .ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"), .ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"), .ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"), .ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"), .ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"), .ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"), .ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"), .ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"), .ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"), .ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"), .ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"), .ENUM_MEM_IF_TCCD ("TCCD_4"), .ENUM_MEM_IF_TCL ("TCL_7"), .ENUM_MEM_IF_TCWL ("TCWL_7"), .ENUM_MEM_IF_TFAW ("TFAW_15"), .ENUM_MEM_IF_TMRD ("TMRD_4"), .ENUM_MEM_IF_TRAS ("TRAS_14"), .ENUM_MEM_IF_TRC ("TRC_20"), .ENUM_MEM_IF_TRCD ("TRCD_6"), .ENUM_MEM_IF_TRP ("TRP_6"), .ENUM_MEM_IF_TRRD ("TRRD_3"), .ENUM_MEM_IF_TRTP ("TRTP_3"), .ENUM_MEM_IF_TWR ("TWR_6"), .ENUM_MEM_IF_TWTR ("TWTR_4"), .ENUM_MMR_CFG_MEM_BL ("MP_BL_8"), .ENUM_OUTPUT_REGD ("DISABLED"), .ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"), .ENUM_PORT0_WIDTH ("PORT_32_BIT"), .ENUM_PORT1_WIDTH ("PORT_32_BIT"), .ENUM_PORT2_WIDTH ("PORT_32_BIT"), .ENUM_PORT3_WIDTH ("PORT_32_BIT"), .ENUM_PORT4_WIDTH ("PORT_32_BIT"), .ENUM_PORT5_WIDTH ("PORT_32_BIT"), .ENUM_PRIORITY_0_0 ("WEIGHT_0"), .ENUM_PRIORITY_0_1 ("WEIGHT_0"), .ENUM_PRIORITY_0_2 ("WEIGHT_0"), .ENUM_PRIORITY_0_3 ("WEIGHT_0"), .ENUM_PRIORITY_0_4 ("WEIGHT_0"), .ENUM_PRIORITY_0_5 ("WEIGHT_0"), .ENUM_PRIORITY_1_0 ("WEIGHT_0"), .ENUM_PRIORITY_1_1 ("WEIGHT_0"), .ENUM_PRIORITY_1_2 ("WEIGHT_0"), .ENUM_PRIORITY_1_3 ("WEIGHT_0"), .ENUM_PRIORITY_1_4 ("WEIGHT_0"), .ENUM_PRIORITY_1_5 ("WEIGHT_0"), .ENUM_PRIORITY_2_0 ("WEIGHT_0"), .ENUM_PRIORITY_2_1 ("WEIGHT_0"), .ENUM_PRIORITY_2_2 ("WEIGHT_0"), .ENUM_PRIORITY_2_3 ("WEIGHT_0"), .ENUM_PRIORITY_2_4 ("WEIGHT_0"), .ENUM_PRIORITY_2_5 ("WEIGHT_0"), .ENUM_PRIORITY_3_0 ("WEIGHT_0"), .ENUM_PRIORITY_3_1 ("WEIGHT_0"), .ENUM_PRIORITY_3_2 ("WEIGHT_0"), .ENUM_PRIORITY_3_3 ("WEIGHT_0"), .ENUM_PRIORITY_3_4 ("WEIGHT_0"), .ENUM_PRIORITY_3_5 ("WEIGHT_0"), .ENUM_PRIORITY_4_0 ("WEIGHT_0"), .ENUM_PRIORITY_4_1 ("WEIGHT_0"), .ENUM_PRIORITY_4_2 ("WEIGHT_0"), .ENUM_PRIORITY_4_3 ("WEIGHT_0"), .ENUM_PRIORITY_4_4 ("WEIGHT_0"), .ENUM_PRIORITY_4_5 ("WEIGHT_0"), .ENUM_PRIORITY_5_0 ("WEIGHT_0"), .ENUM_PRIORITY_5_1 ("WEIGHT_0"), .ENUM_PRIORITY_5_2 ("WEIGHT_0"), .ENUM_PRIORITY_5_3 ("WEIGHT_0"), .ENUM_PRIORITY_5_4 ("WEIGHT_0"), .ENUM_PRIORITY_5_5 ("WEIGHT_0"), .ENUM_PRIORITY_6_0 ("WEIGHT_0"), .ENUM_PRIORITY_6_1 ("WEIGHT_0"), .ENUM_PRIORITY_6_2 ("WEIGHT_0"), .ENUM_PRIORITY_6_3 ("WEIGHT_0"), .ENUM_PRIORITY_6_4 ("WEIGHT_0"), .ENUM_PRIORITY_6_5 ("WEIGHT_0"), .ENUM_PRIORITY_7_0 ("WEIGHT_0"), .ENUM_PRIORITY_7_1 ("WEIGHT_0"), .ENUM_PRIORITY_7_2 ("WEIGHT_0"), .ENUM_PRIORITY_7_3 ("WEIGHT_0"), .ENUM_PRIORITY_7_4 ("WEIGHT_0"), .ENUM_PRIORITY_7_5 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"), .ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"), .ENUM_RD_DWIDTH_0 ("DWIDTH_0"), .ENUM_RD_DWIDTH_1 ("DWIDTH_0"), .ENUM_RD_DWIDTH_2 ("DWIDTH_0"), .ENUM_RD_DWIDTH_3 ("DWIDTH_0"), .ENUM_RD_DWIDTH_4 ("DWIDTH_0"), .ENUM_RD_DWIDTH_5 ("DWIDTH_0"), .ENUM_RD_FIFO_IN_USE_0 ("FALSE"), .ENUM_RD_FIFO_IN_USE_1 ("FALSE"), .ENUM_RD_FIFO_IN_USE_2 ("FALSE"), .ENUM_RD_FIFO_IN_USE_3 ("FALSE"), .ENUM_RD_PORT_INFO_0 ("USE_NO"), .ENUM_RD_PORT_INFO_1 ("USE_NO"), .ENUM_RD_PORT_INFO_2 ("USE_NO"), .ENUM_RD_PORT_INFO_3 ("USE_NO"), .ENUM_RD_PORT_INFO_4 ("USE_NO"), .ENUM_RD_PORT_INFO_5 ("USE_NO"), .ENUM_READ_ODT_CHIP ("ODT_DISABLED"), .ENUM_REORDER_DATA ("DATA_REORDERING"), .ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"), .ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"), .ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"), .ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"), .ENUM_TEST_MODE ("NORMAL_MODE"), .ENUM_THLD_JAR1_0 ("THRESHOLD_32"), .ENUM_THLD_JAR1_1 ("THRESHOLD_32"), .ENUM_THLD_JAR1_2 ("THRESHOLD_32"), .ENUM_THLD_JAR1_3 ("THRESHOLD_32"), .ENUM_THLD_JAR1_4 ("THRESHOLD_32"), .ENUM_THLD_JAR1_5 ("THRESHOLD_32"), .ENUM_THLD_JAR2_0 ("THRESHOLD_16"), .ENUM_THLD_JAR2_1 ("THRESHOLD_16"), .ENUM_THLD_JAR2_2 ("THRESHOLD_16"), .ENUM_THLD_JAR2_3 ("THRESHOLD_16"), .ENUM_THLD_JAR2_4 ("THRESHOLD_16"), .ENUM_THLD_JAR2_5 ("THRESHOLD_16"), .ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"), .ENUM_USER_ECC_EN ("DISABLE"), .ENUM_USER_PRIORITY_0 ("PRIORITY_1"), .ENUM_USER_PRIORITY_1 ("PRIORITY_1"), .ENUM_USER_PRIORITY_2 ("PRIORITY_1"), .ENUM_USER_PRIORITY_3 ("PRIORITY_1"), .ENUM_USER_PRIORITY_4 ("PRIORITY_1"), .ENUM_USER_PRIORITY_5 ("PRIORITY_1"), .ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WR_DWIDTH_0 ("DWIDTH_0"), .ENUM_WR_DWIDTH_1 ("DWIDTH_0"), .ENUM_WR_DWIDTH_2 ("DWIDTH_0"), .ENUM_WR_DWIDTH_3 ("DWIDTH_0"), .ENUM_WR_DWIDTH_4 ("DWIDTH_0"), .ENUM_WR_DWIDTH_5 ("DWIDTH_0"), .ENUM_WR_FIFO_IN_USE_0 ("FALSE"), .ENUM_WR_FIFO_IN_USE_1 ("FALSE"), .ENUM_WR_FIFO_IN_USE_2 ("FALSE"), .ENUM_WR_FIFO_IN_USE_3 ("FALSE"), .ENUM_WR_PORT_INFO_0 ("USE_NO"), .ENUM_WR_PORT_INFO_1 ("USE_NO"), .ENUM_WR_PORT_INFO_2 ("USE_NO"), .ENUM_WR_PORT_INFO_3 ("USE_NO"), .ENUM_WR_PORT_INFO_4 ("USE_NO"), .ENUM_WR_PORT_INFO_5 ("USE_NO"), .ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"), .INTG_MEM_AUTO_PD_CYCLES (0), .INTG_CYC_TO_RLD_JARS_0 (1), .INTG_CYC_TO_RLD_JARS_1 (1), .INTG_CYC_TO_RLD_JARS_2 (1), .INTG_CYC_TO_RLD_JARS_3 (1), .INTG_CYC_TO_RLD_JARS_4 (1), .INTG_CYC_TO_RLD_JARS_5 (1), .INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0), .INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0), .INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0), .INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0), .INTG_EXTRA_CTL_CLK_ARF_PERIOD (0), .INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0), .INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0), .INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0), .INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0), .INTG_EXTRA_CTL_CLK_PDN_PERIOD (0), .INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0), .INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0), .INTG_EXTRA_CTL_CLK_RD_TO_PCH (0), .INTG_EXTRA_CTL_CLK_RD_TO_RD (0), .INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0), .INTG_EXTRA_CTL_CLK_RD_TO_WR (2), .INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2), .INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2), .INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0), .INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0), .INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0), .INTG_EXTRA_CTL_CLK_WR_TO_PCH (0), .INTG_EXTRA_CTL_CLK_WR_TO_RD (3), .INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3), .INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3), .INTG_EXTRA_CTL_CLK_WR_TO_WR (0), .INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0), .INTG_MEM_IF_TREFI (3120), .INTG_MEM_IF_TRFC (120), .INTG_RCFG_SUM_WT_PRIORITY_0 (0), .INTG_RCFG_SUM_WT_PRIORITY_1 (0), .INTG_RCFG_SUM_WT_PRIORITY_2 (0), .INTG_RCFG_SUM_WT_PRIORITY_3 (0), .INTG_RCFG_SUM_WT_PRIORITY_4 (0), .INTG_RCFG_SUM_WT_PRIORITY_5 (0), .INTG_RCFG_SUM_WT_PRIORITY_6 (0), .INTG_RCFG_SUM_WT_PRIORITY_7 (0), .INTG_SUM_WT_PRIORITY_0 (0), .INTG_SUM_WT_PRIORITY_1 (0), .INTG_SUM_WT_PRIORITY_2 (0), .INTG_SUM_WT_PRIORITY_3 (0), .INTG_SUM_WT_PRIORITY_4 (0), .INTG_SUM_WT_PRIORITY_5 (0), .INTG_SUM_WT_PRIORITY_6 (0), .INTG_SUM_WT_PRIORITY_7 (0), .INTG_POWER_SAVING_EXIT_CYCLES (5), .INTG_MEM_CLK_ENTRY_CYCLES (10), .ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"), .ENUM_ENABLE_BURST_TERMINATE ("DISABLED"), .AFI_RATE_RATIO (1), .AFI_ADDR_WIDTH (15), .AFI_BANKADDR_WIDTH (3), .AFI_CONTROL_WIDTH (1), .AFI_CS_WIDTH (1), .AFI_DM_WIDTH (8), .AFI_DQ_WIDTH (64), .AFI_ODT_WIDTH (1), .AFI_WRITE_DQS_WIDTH (4), .AFI_RLAT_WIDTH (6), .AFI_WLAT_WIDTH (6), .HARD_PHY (1) ) c0 ( .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk .local_init_done (), // status.local_init_done .local_cal_success (), // .local_cal_success .local_cal_fail (), // .local_cal_fail .afi_addr (c0_afi_afi_addr), // afi.afi_addr .afi_ba (c0_afi_afi_ba), // .afi_ba .afi_cke (c0_afi_afi_cke), // .afi_cke .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n .afi_we_n (c0_afi_afi_we_n), // .afi_we_n .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n .afi_odt (c0_afi_afi_odt), // .afi_odt .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable .afi_init_req (), // .afi_init_req .afi_cal_req (), // .afi_cal_req .afi_seq_busy (), // .afi_seq_busy .afi_ctl_refresh_done (), // .afi_ctl_refresh_done .afi_ctl_long_idle (), // .afi_ctl_long_idle .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid .afi_wdata (c0_afi_afi_wdata), // .afi_wdata .afi_dm (c0_afi_afi_dm), // .afi_dm .afi_rdata (p0_afi_afi_rdata), // .afi_rdata .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid .afi_wlat (p0_afi_afi_wlat), // .afi_wlat .afi_rlat (p0_afi_afi_rlat), // .afi_rlat .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess .mp_cmd_clk_0 (1'b0), // (terminated) .mp_cmd_reset_n_0 (1'b1), // (terminated) .mp_cmd_clk_1 (1'b0), // (terminated) .mp_cmd_reset_n_1 (1'b1), // (terminated) .mp_cmd_clk_2 (1'b0), // (terminated) .mp_cmd_reset_n_2 (1'b1), // (terminated) .mp_cmd_clk_3 (1'b0), // (terminated) .mp_cmd_reset_n_3 (1'b1), // (terminated) .mp_cmd_clk_4 (1'b0), // (terminated) .mp_cmd_reset_n_4 (1'b1), // (terminated) .mp_cmd_clk_5 (1'b0), // (terminated) .mp_cmd_reset_n_5 (1'b1), // (terminated) .mp_rfifo_clk_0 (1'b0), // (terminated) .mp_rfifo_reset_n_0 (1'b1), // (terminated) .mp_wfifo_clk_0 (1'b0), // (terminated) .mp_wfifo_reset_n_0 (1'b1), // (terminated) .mp_rfifo_clk_1 (1'b0), // (terminated) .mp_rfifo_reset_n_1 (1'b1), // (terminated) .mp_wfifo_clk_1 (1'b0), // (terminated) .mp_wfifo_reset_n_1 (1'b1), // (terminated) .mp_rfifo_clk_2 (1'b0), // (terminated) .mp_rfifo_reset_n_2 (1'b1), // (terminated) .mp_wfifo_clk_2 (1'b0), // (terminated) .mp_wfifo_reset_n_2 (1'b1), // (terminated) .mp_rfifo_clk_3 (1'b0), // (terminated) .mp_rfifo_reset_n_3 (1'b1), // (terminated) .mp_wfifo_clk_3 (1'b0), // (terminated) .mp_wfifo_reset_n_3 (1'b1), // (terminated) .csr_clk (1'b0), // (terminated) .csr_reset_n (1'b1), // (terminated) .avl_ready_0 (), // (terminated) .avl_burstbegin_0 (1'b0), // (terminated) .avl_addr_0 (1'b0), // (terminated) .avl_rdata_valid_0 (), // (terminated) .avl_rdata_0 (), // (terminated) .avl_wdata_0 (1'b0), // (terminated) .avl_be_0 (1'b0), // (terminated) .avl_read_req_0 (1'b0), // (terminated) .avl_write_req_0 (1'b0), // (terminated) .avl_size_0 (3'b000), // (terminated) .avl_ready_1 (), // (terminated) .avl_burstbegin_1 (1'b0), // (terminated) .avl_addr_1 (1'b0), // (terminated) .avl_rdata_valid_1 (), // (terminated) .avl_rdata_1 (), // (terminated) .avl_wdata_1 (1'b0), // (terminated) .avl_be_1 (1'b0), // (terminated) .avl_read_req_1 (1'b0), // (terminated) .avl_write_req_1 (1'b0), // (terminated) .avl_size_1 (3'b000), // (terminated) .avl_ready_2 (), // (terminated) .avl_burstbegin_2 (1'b0), // (terminated) .avl_addr_2 (1'b0), // (terminated) .avl_rdata_valid_2 (), // (terminated) .avl_rdata_2 (), // (terminated) .avl_wdata_2 (1'b0), // (terminated) .avl_be_2 (1'b0), // (terminated) .avl_read_req_2 (1'b0), // (terminated) .avl_write_req_2 (1'b0), // (terminated) .avl_size_2 (3'b000), // (terminated) .avl_ready_3 (), // (terminated) .avl_burstbegin_3 (1'b0), // (terminated) .avl_addr_3 (1'b0), // (terminated) .avl_rdata_valid_3 (), // (terminated) .avl_rdata_3 (), // (terminated) .avl_wdata_3 (1'b0), // (terminated) .avl_be_3 (1'b0), // (terminated) .avl_read_req_3 (1'b0), // (terminated) .avl_write_req_3 (1'b0), // (terminated) .avl_size_3 (3'b000), // (terminated) .avl_ready_4 (), // (terminated) .avl_burstbegin_4 (1'b0), // (terminated) .avl_addr_4 (1'b0), // (terminated) .avl_rdata_valid_4 (), // (terminated) .avl_rdata_4 (), // (terminated) .avl_wdata_4 (1'b0), // (terminated) .avl_be_4 (1'b0), // (terminated) .avl_read_req_4 (1'b0), // (terminated) .avl_write_req_4 (1'b0), // (terminated) .avl_size_4 (3'b000), // (terminated) .avl_ready_5 (), // (terminated) .avl_burstbegin_5 (1'b0), // (terminated) .avl_addr_5 (1'b0), // (terminated) .avl_rdata_valid_5 (), // (terminated) .avl_rdata_5 (), // (terminated) .avl_wdata_5 (1'b0), // (terminated) .avl_be_5 (1'b0), // (terminated) .avl_read_req_5 (1'b0), // (terminated) .avl_write_req_5 (1'b0), // (terminated) .avl_size_5 (3'b000), // (terminated) .csr_write_req (1'b0), // (terminated) .csr_read_req (1'b0), // (terminated) .csr_waitrequest (), // (terminated) .csr_addr (10'b0000000000), // (terminated) .csr_be (1'b0), // (terminated) .csr_wdata (8'b00000000), // (terminated) .csr_rdata (), // (terminated) .csr_rdata_valid (), // (terminated) .local_multicast (1'b0), // (terminated) .local_refresh_req (1'b0), // (terminated) .local_refresh_chip (1'b0), // (terminated) .local_refresh_ack (), // (terminated) .local_self_rfsh_req (1'b0), // (terminated) .local_self_rfsh_chip (1'b0), // (terminated) .local_self_rfsh_ack (), // (terminated) .local_deep_powerdn_req (1'b0), // (terminated) .local_deep_powerdn_chip (1'b0), // (terminated) .local_deep_powerdn_ack (), // (terminated) .local_powerdn_ack (), // (terminated) .local_priority (1'b0), // (terminated) .bonding_in_1 (4'b0000), // (terminated) .bonding_in_2 (6'b000000), // (terminated) .bonding_in_3 (6'b000000), // (terminated) .bonding_out_1 (), // (terminated) .bonding_out_2 (), // (terminated) .bonding_out_3 () // (terminated) ); altera_mem_if_oct_cyclonev #( .OCT_TERM_CONTROL_WIDTH (16) ) oct ( .oct_rzqin (oct_rzqin), // oct.rzqin .seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol .parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol ); altera_mem_if_dll_cyclonev #( .DLL_DELAY_CTRL_WIDTH (7), .DLL_OFFSET_CTRL_WIDTH (6), .DELAY_BUFFER_MODE ("HIGH"), .DELAY_CHAIN_LENGTH (8), .DLL_INPUT_FREQUENCY_PS_STR ("2500 ps") ) dll ( .clk (p0_dll_clk_clk), // clk.clk .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked .dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl ); endmodule
// (C) 2001-2017 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License Subscription // Agreement, Intel FPGA IP License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Intel and sold by // Intel or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/17.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2017/08/13 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 \|\| (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) \| out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_LP__O311A_TB_V `define SKY130_FD_SC_LP__O311A_TB_V /* * o311a: 3-input OR into 3-input AND. * * X = ((A1 \| A2 \| A3) & B1 & C1) * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_lp__o311a.v" module top(); // Inputs are registered reg A1; reg A2; reg A3; reg B1; reg C1; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire X; initial begin // Initial state is x for all inputs. A1 = 1'bX; A2 = 1'bX; A3 = 1'bX; B1 = 1'bX; C1 = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 A1 = 1'b0; #40 A2 = 1'b0; #60 A3 = 1'b0; #80 B1 = 1'b0; #100 C1 = 1'b0; #120 VGND = 1'b0; #140 VNB = 1'b0; #160 VPB = 1'b0; #180 VPWR = 1'b0; #200 A1 = 1'b1; #220 A2 = 1'b1; #240 A3 = 1'b1; #260 B1 = 1'b1; #280 C1 = 1'b1; #300 VGND = 1'b1; #320 VNB = 1'b1; #340 VPB = 1'b1; #360 VPWR = 1'b1; #380 A1 = 1'b0; #400 A2 = 1'b0; #420 A3 = 1'b0; #440 B1 = 1'b0; #460 C1 = 1'b0; #480 VGND = 1'b0; #500 VNB = 1'b0; #520 VPB = 1'b0; #540 VPWR = 1'b0; #560 VPWR = 1'b1; #580 VPB = 1'b1; #600 VNB = 1'b1; #620 VGND = 1'b1; #640 C1 = 1'b1; #660 B1 = 1'b1; #680 A3 = 1'b1; #700 A2 = 1'b1; #720 A1 = 1'b1; #740 VPWR = 1'bx; #760 VPB = 1'bx; #780 VNB = 1'bx; #800 VGND = 1'bx; #820 C1 = 1'bx; #840 B1 = 1'bx; #860 A3 = 1'bx; #880 A2 = 1'bx; #900 A1 = 1'bx; end sky130_fd_sc_lp__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X)); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__O311A_TB_V
//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_7x_v1_3_pipe_rate.v // Version : 1.3 //------------------------------------------------------------------------------ // Filename : pipe_rate.v // Description : PIPE Rate Module for 7 Series Transceiver // Version : 11.4 //------------------------------------------------------------------------------ `timescale 1ns / 1ps //---------- PIPE Rate Module -------------------------------------------------- module pcie_7x_v1_3_pipe_rate # ( parameter PCIE_USE_MODE = "1.1", // PCIe use mode parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max ) ( //---------- Input ------------------------------------- input RATE_CLK, input RATE_RST_N, input RATE_RST_IDLE, input [ 1:0] RATE_RATE_IN, input RATE_CPLLLOCK, input RATE_QPLLLOCK, input RATE_MMCM_LOCK, input RATE_DRP_DONE, input RATE_TXRESETDONE, input RATE_RXRESETDONE, input RATE_TXRATEDONE, input RATE_RXRATEDONE, input RATE_PHYSTATUS, input RATE_RESETOVRD_DONE, input RATE_TXSYNC_DONE, input RATE_RXSYNC_DONE, //---------- Output ------------------------------------ output RATE_CPLLPD, output RATE_QPLLPD, output RATE_CPLLRESET, output RATE_QPLLRESET, output RATE_TXPMARESET, output RATE_RXPMARESET, output RATE_DRP_START, output [ 1:0] RATE_SYSCLKSEL, output RATE_PCLK_SEL, output RATE_GEN3, output [ 2:0] RATE_RATE_OUT, output RATE_RESETOVRD_START, output RATE_TXSYNC_START, output RATE_DONE, output RATE_RXSYNC_START, output RATE_RXSYNC, output RATE_IDLE, output [23:0] RATE_FSM ); //---------- Input FF or Buffer ------------------------ reg rst_idle_reg1; reg [ 1:0] rate_in_reg1; reg cplllock_reg1; reg qplllock_reg1; reg mmcm_lock_reg1; reg drp_done_reg1; reg txresetdone_reg1; reg rxresetdone_reg1; reg txratedone_reg1; reg rxratedone_reg1; reg phystatus_reg1; reg resetovrd_done_reg1; reg txsync_done_reg1; reg rxsync_done_reg1; reg rst_idle_reg2; reg [ 1:0] rate_in_reg2; reg cplllock_reg2; reg qplllock_reg2; reg mmcm_lock_reg2; reg drp_done_reg2; reg txresetdone_reg2; reg rxresetdone_reg2; reg txratedone_reg2; reg rxratedone_reg2; reg phystatus_reg2; reg resetovrd_done_reg2; reg txsync_done_reg2; reg rxsync_done_reg2; //---------- Internal Signals -------------------------- wire pll_lock; wire [ 2:0] rate; reg [ 3:0] txdata_wait_cnt = 4'd0; reg txratedone = 1'd0; reg rxratedone = 1'd0; reg phystatus = 1'd0; reg ratedone = 1'd0; reg gen3_exit = 1'd0; //---------- Output FF or Buffer ----------------------- reg cpllpd = 1'd0; reg qpllpd = 1'd0; reg cpllreset = 1'd0; reg qpllreset = 1'd0; reg txpmareset = 1'd0; reg rxpmareset = 1'd0; reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; reg gen3 = 1'd0; reg pclk_sel = 1'd0; reg [ 2:0] rate_out = 3'd0; reg [23:0] fsm = 24'd0; //---------- FSM --------------------------------------- localparam FSM_IDLE = 24'b000000000000000000000001; localparam FSM_PLL_PU = 24'b000000000000000000000010; // Gen 3 only localparam FSM_PLL_PURESET = 24'b000000000000000000000100; // Gen 3 only localparam FSM_PLL_LOCK = 24'b000000000000000000001000; // Gen 3 or reset only localparam FSM_PMARESET_HOLD = 24'b000000000000000000010000; // Gen 3 or reset only localparam FSM_PLL_SEL = 24'b000000000000000000100000; // Gen 3 or reset only localparam FSM_MMCM_LOCK = 24'b000000000000000001000000; // Gen 3 or reset only localparam FSM_DRP_START = 24'b000000000000000010000000; // Gen 3 or reset only localparam FSM_DRP_DONE = 24'b000000000000000100000000; // Gen 3 or reset only localparam FSM_PMARESET_RELEASE = 24'b000000000000001000000000; // Gen 3 only localparam FSM_PMARESET_DONE = 24'b000000000000010000000000; // Gen 3 only localparam FSM_TXDATA_WAIT = 24'b000000000000100000000000; localparam FSM_PCLK_SEL = 24'b000000000001000000000000; localparam FSM_RATE_SEL = 24'b000000000010000000000000; localparam FSM_RATE_DONE = 24'b000000000100000000000000; localparam FSM_RESETOVRD_START = 24'b000000001000000000000000; // PCIe use mode 1.0 only localparam FSM_RESETOVRD_DONE = 24'b000000010000000000000000; // PCIe use mode 1.0 only localparam FSM_PLL_PDRESET = 24'b000000100000000000000000; localparam FSM_PLL_PD = 24'b000001000000000000000000; localparam FSM_TXSYNC_START = 24'b000010000000000000000000; localparam FSM_TXSYNC_DONE = 24'b000100000000000000000000; localparam FSM_DONE = 24'b001000000000000000000000; // Must sync value to pipe_user.v localparam FSM_RXSYNC_START = 24'b010000000000000000000000; // Gen 3 only localparam FSM_RXSYNC_DONE = 24'b100000000000000000000000; // Gen 3 only //---------- Input FF ---------------------------------------------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) begin //---------- 1st Stage FF -------------------------- rst_idle_reg1 <= 1'd0; rate_in_reg1 <= 2'd0; cplllock_reg1 <= 1'd0; qplllock_reg1 <= 1'd0; mmcm_lock_reg1 <= 1'd0; drp_done_reg1 <= 1'd0; txresetdone_reg1 <= 1'd0; rxresetdone_reg1 <= 1'd0; txratedone_reg1 <= 1'd0; rxratedone_reg1 <= 1'd0; phystatus_reg1 <= 1'd0; resetovrd_done_reg1 <= 1'd0; txsync_done_reg1 <= 1'd0; rxsync_done_reg1 <= 1'd0; //---------- 2nd Stage FF -------------------------- rst_idle_reg2 <= 1'd0; rate_in_reg2 <= 2'd0; cplllock_reg2 <= 1'd0; qplllock_reg2 <= 1'd0; mmcm_lock_reg2 <= 1'd0; drp_done_reg2 <= 1'd0; txresetdone_reg2 <= 1'd0; rxresetdone_reg2 <= 1'd0; txratedone_reg2 <= 1'd0; rxratedone_reg2 <= 1'd0; phystatus_reg2 <= 1'd0; resetovrd_done_reg2 <= 1'd0; txsync_done_reg2 <= 1'd0; rxsync_done_reg2 <= 1'd0; end else begin //---------- 1st Stage FF -------------------------- rst_idle_reg1 <= RATE_RST_IDLE; rate_in_reg1 <= RATE_RATE_IN; cplllock_reg1 <= RATE_CPLLLOCK; qplllock_reg1 <= RATE_QPLLLOCK; mmcm_lock_reg1 <= RATE_MMCM_LOCK; drp_done_reg1 <= RATE_DRP_DONE; txresetdone_reg1 <= RATE_TXRESETDONE; rxresetdone_reg1 <= RATE_RXRESETDONE; txratedone_reg1 <= RATE_TXRATEDONE; rxratedone_reg1 <= RATE_RXRATEDONE; phystatus_reg1 <= RATE_PHYSTATUS; resetovrd_done_reg1 <= RATE_RESETOVRD_DONE; txsync_done_reg1 <= RATE_TXSYNC_DONE; rxsync_done_reg1 <= RATE_RXSYNC_DONE; //---------- 2nd Stage FF -------------------------- rst_idle_reg2 <= rst_idle_reg1; rate_in_reg2 <= rate_in_reg1; cplllock_reg2 <= cplllock_reg1; qplllock_reg2 <= qplllock_reg1; mmcm_lock_reg2 <= mmcm_lock_reg1; drp_done_reg2 <= drp_done_reg1; txresetdone_reg2 <= txresetdone_reg1; rxresetdone_reg2 <= rxresetdone_reg1; txratedone_reg2 <= txratedone_reg1; rxratedone_reg2 <= rxratedone_reg1; phystatus_reg2 <= phystatus_reg1; resetovrd_done_reg2 <= resetovrd_done_reg1; txsync_done_reg2 <= txsync_done_reg1; rxsync_done_reg2 <= rxsync_done_reg1; end end //---------- Select CPLL or QPLL Lock ------------------------------------------ // Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock // Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock // Gen3 : Wait for QPLL lock //------------------------------------------------------------------------------ assign pll_lock = (rate_in_reg2 == 2'd2) \|\| (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2; //---------- Select Rate ------------------------------------------------------- // Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2 // Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1 // Gen3 : Div 1 using [TX/RX]OUT_DIV = 1 //------------------------------------------------------------------------------ assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 : (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0; //---------- TXDATA Wait Counter ----------------------------------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) txdata_wait_cnt <= 4'd0; else //---------- Increment Wait Counter ---------------- if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX)) txdata_wait_cnt <= txdata_wait_cnt + 4'd1; //---------- Hold Wait Counter --------------------- else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX)) txdata_wait_cnt <= txdata_wait_cnt; //---------- Reset Wait Counter -------------------- else txdata_wait_cnt <= 4'd0; end //---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS ----------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) begin txratedone <= 1'd0; rxratedone <= 1'd0; phystatus <= 1'd0; ratedone <= 1'd0; end else begin if (fsm == FSM_RATE_DONE) begin //---------- Latch TXRATEDONE ------------------ if (txratedone_reg2) txratedone <= 1'd1; else txratedone <= txratedone; //---------- Latch RXRATEDONE ------------------ if (rxratedone_reg2) rxratedone <= 1'd1; else rxratedone <= rxratedone; //---------- Latch PHYSTATUS ------------------- if (phystatus_reg2) phystatus <= 1'd1; else phystatus <= phystatus; //---------- Latch Rate Done ------------------- if (rxratedone && txratedone && phystatus) ratedone <= 1'd1; else ratedone <= ratedone; end else begin txratedone <= 1'd0; rxratedone <= 1'd0; phystatus <= 1'd0; ratedone <= 1'd0; end end end //---------- PIPE Rate FSM ----------------------------------------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) begin fsm <= FSM_PLL_LOCK; gen3_exit <= 1'd0; cpllpd <= 1'd0; qpllpd <= 1'd0; cpllreset <= 1'd0; qpllreset <= 1'd0; txpmareset <= 1'd0; rxpmareset <= 1'd0; sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; pclk_sel <= 1'd0; gen3 <= 1'd0; rate_out <= 3'd0; end else begin case (fsm) //---------- Idle State ---------------------------- FSM_IDLE : begin //---------- Detect Rate Change ---------------- if (rate_in_reg2 != rate_in_reg1) begin fsm <= ((rate_in_reg2 == 2'd2) \|\| (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT; gen3_exit <= (rate_in_reg2 == 2'd2); cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end else begin fsm <= FSM_IDLE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end end //---------- Power-up PLL -------------------------- FSM_PLL_PU : begin fsm <= FSM_PLL_PURESET; gen3_exit <= gen3_exit; cpllpd <= (PCIE_PLL_SEL == "QPLL"); qpllpd <= 1'd0; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Release PLL Resets -------------------- FSM_PLL_PURESET : begin fsm <= FSM_PLL_LOCK; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= (PCIE_PLL_SEL == "QPLL"); qpllreset <= 1'd0; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for PLL Lock --------------------- FSM_PLL_LOCK : begin fsm <= (pll_lock ? FSM_PMARESET_HOLD : FSM_PLL_LOCK); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Hold both PMA in Reset ---------------- // Gen1 : Release PMA Reset // Gen2 : Release PMA Reset // Gen3 : Hold PMA Reset //-------------------------------------------------- FSM_PMARESET_HOLD : begin fsm <= FSM_PLL_SEL; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= ((rate_in_reg2 == 2'd2) \|\| gen3_exit); rxpmareset <= ((rate_in_reg2 == 2'd2) \|\| gen3_exit); sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Select PLL ---------------------------- // Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL // Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL // Gen3 : QPLL //-------------------------------------------------- FSM_PLL_SEL : begin fsm <= FSM_MMCM_LOCK; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= ((rate_in_reg2 == 2'd2) \|\| (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Check for MMCM Lock ------------------- FSM_MMCM_LOCK : begin fsm <= (mmcm_lock_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Start DRP ----------------------------- FSM_DRP_START: begin fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= ((rate_in_reg2 == 2'd1) \|\| (rate_in_reg2 == 2'd2)); gen3 <= (rate_in_reg2 == 2'd2); rate_out <= (((rate_in_reg2 == 2'd2) \|\| gen3_exit) ? rate : rate_out); end //---------- Wait for DRP Done --------------------- FSM_DRP_DONE : begin fsm <= (drp_done_reg2 ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Release PMA Resets -------------------- FSM_PMARESET_RELEASE : begin fsm <= FSM_PMARESET_DONE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= 1'd0; rxpmareset <= 1'd0; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion FSM_PMARESET_DONE : begin fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2)) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for TXDATA to TX[P/N] Latency ---- FSM_TXDATA_WAIT : begin fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Select PCLK Frequency ----------------- // Gen1 : PCLK = 125 MHz // Gen2 : PCLK = 250 MHz // Gen3 : PCLK = 250 MHz //-------------------------------------------------- FSM_PCLK_SEL : begin fsm <= FSM_RATE_SEL; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= ((rate_in_reg2 == 2'd1) \|\| (rate_in_reg2 == 2'd2)); gen3 <= gen3; rate_out <= rate_out; end //---------- Select Rate --------------------------- FSM_RATE_SEL : begin fsm <= FSM_RATE_DONE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate; // Update [TX/RX]RATE end //---------- Wait for Rate Change Done ------------- FSM_RATE_DONE : begin if (ratedone \|\| (rate_in_reg2 == 2'd2) \|\| (gen3_exit)) if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit)) fsm <= FSM_RESETOVRD_START; else fsm <= FSM_PLL_PDRESET; else fsm <= FSM_RATE_DONE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Reset Override Start ------------------ FSM_RESETOVRD_START: begin fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Reset Override Done ------------------- FSM_RESETOVRD_DONE : begin fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Hold PLL Not Used in Reset ------------ FSM_PLL_PDRESET : begin fsm <= FSM_PLL_PD; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2); qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2); txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Power-Down PLL Not Used --------------- FSM_PLL_PD : begin fsm <= (((rate_in_reg2 == 2'd2) \|\| (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE); gen3_exit <= gen3_exit; cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2); qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2); cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Start TX Sync ------------------------- FSM_TXSYNC_START: begin fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for TX Sync Done ----------------- FSM_TXSYNC_DONE: begin fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Rate Change Done ---------------------- FSM_DONE : begin fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Start RX Sync ------------------------- FSM_RXSYNC_START: begin fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for RX Sync Done ----------------- FSM_RXSYNC_DONE: begin fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Default State ------------------------- default : begin fsm <= FSM_IDLE; gen3_exit <= 1'd0; cpllpd <= 1'd0; qpllpd <= 1'd0; cpllreset <= 1'd0; qpllreset <= 1'd0; txpmareset <= 1'd0; rxpmareset <= 1'd0; sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; pclk_sel <= 1'd0; gen3 <= 1'd0; rate_out <= 3'd0; end endcase end end //---------- PIPE Rate Output -------------------------------------------------- assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd); assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd); assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset); assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset); assign RATE_TXPMARESET = txpmareset; assign RATE_RXPMARESET = rxpmareset; assign RATE_SYSCLKSEL = sysclksel; assign RATE_DRP_START = (fsm == FSM_DRP_START); assign RATE_PCLK_SEL = pclk_sel; assign RATE_GEN3 = gen3; assign RATE_RATE_OUT = rate_out; assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START); assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START); assign RATE_DONE = (fsm == FSM_DONE); assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START); assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) \|\| (fsm == FSM_RXSYNC_DONE)); assign RATE_IDLE = (fsm == FSM_IDLE); assign RATE_FSM = fsm; endmodule
(** * Hoare2: Hoare Logic, Part II ) Require Export Hoare. ( ####################################################### ) (* * Decorated Programs ) (* The beauty of Hoare Logic is that it is _compositional_ -- the structure of proofs exactly follows the structure of programs. This suggests that we can record the essential ideas of a proof informally (leaving out some low-level calculational details) by decorating programs with appropriate assertions around each statement. Such a _decorated program_ carries with it an (informal) proof of its own correctness. ) (* For example, here is a complete decorated program: ) (* {{ True }} ->> {{ m = m }} X ::= m;; {{ X = m }} ->> {{ X = m /\ p = p }} Z ::= p; {{ X = m /\ Z = p }} ->> {{ Z - X = p - m }} WHILE X <> 0 DO {{ Z - X = p - m /\ X <> 0 }} ->> {{ (Z - 1) - (X - 1) = p - m }} Z ::= Z - 1;; {{ Z - (X - 1) = p - m }} X ::= X - 1 {{ Z - X = p - m }} END; {{ Z - X = p - m /\ ~ (X <> 0) }} ->> {{ Z = p - m }} ) (* Concretely, a decorated program consists of the program text interleaved with assertions. To check that a decorated program represents a valid proof, we check that each individual command is _locally consistent_ with its accompanying assertions in the following sense: ) (* - [SKIP] is locally consistent if its precondition and postcondition are the same: {{ P }} SKIP {{ P }} ) (* - The sequential composition of [c1] and [c2] is locally consistent (with respect to assertions [P] and [R]) if [c1] is locally consistent (with respect to [P] and [Q]) and [c2] is locally consistent (with respect to [Q] and [R]): {{ P }} c1;; {{ Q }} c2 {{ R }} ) (* - An assignment is locally consistent if its precondition is the appropriate substitution of its postcondition: {{ P [X \|-> a] }} X ::= a {{ P }} ) (* - A conditional is locally consistent (with respect to assertions [P] and [Q]) if the assertions at the top of its "then" and "else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then" branch is locally consistent (with respect to [P /\ b] and [Q]) and its "else" branch is locally consistent (with respect to [P /\ ~b] and [Q]): {{ P }} IFB b THEN {{ P /\ b }} c1 {{ Q }} ELSE {{ P /\ ~b }} c2 {{ Q }} FI {{ Q }} ) (* - A while loop with precondition [P] is locally consistent if its postcondition is [P /\ ~b] and if the pre- and postconditions of its body are exactly [P /\ b] and [P]: {{ P }} WHILE b DO {{ P /\ b }} c1 {{ P }} END {{ P /\ ~b }} ) (* - A pair of assertions separated by [->>] is locally consistent if the first implies the second (in all states): {{ P }} ->> {{ P' }} This corresponds to the application of [hoare_consequence] and is the only place in a decorated program where checking if decorations are correct is not fully mechanical and syntactic, but involves logical and/or arithmetic reasoning. ) (* We have seen above how _verifying_ the correctness of a given proof involves checking that every single command is locally consistent with the accompanying assertions. If we are instead interested in _finding_ a proof for a given specification we need to discover the right assertions. This can be done in an almost automatic way, with the exception of finding loop invariants, which is the subject of in the next section. In the reminder of this section we explain in detail how to construct decorations for several simple programs that don't involve non-trivial loop invariants. ) ( ####################################################### ) (* ** Example: Swapping Using Addition and Subtraction ) (* Here is a program that swaps the values of two variables using addition and subtraction (instead of by assigning to a temporary variable). X ::= X + Y;; Y ::= X - Y;; X ::= X - Y We can prove using decorations that this program is correct -- i.e., it always swaps the values of variables [X] and [Y]. ) (* (1) {{ X = m /\ Y = n }} ->> (2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }} X ::= X + Y;; (3) {{ X - (X - Y) = n /\ X - Y = m }} Y ::= X - Y;; (4) {{ X - Y = n /\ Y = m }} X ::= X - Y (5) {{ X = n /\ Y = m }} The decorations were constructed as follows: - We begin with the undecorated program (the unnumbered lines). - We then add the specification -- i.e., the outer precondition (1) and postcondition (5). In the precondition we use auxiliary variables (parameters) [m] and [n] to remember the initial values of variables [X] and respectively [Y], so that we can refer to them in the postcondition (5). - We work backwards mechanically starting from (5) all the way to (2). At each step, we obtain the precondition of the assignment from its postcondition by substituting the assigned variable with the right-hand-side of the assignment. For instance, we obtain (4) by substituting [X] with [X - Y] in (5), and (3) by substituting [Y] with [X - Y] in (4). - Finally, we verify that (1) logically implies (2) -- i.e., that the step from (1) to (2) is a valid use of the law of consequence. For this we substitute [X] by [m] and [Y] by [n] and calculate as follows: (m + n) - ((m + n) - n) = n /\ (m + n) - n = m (m + n) - m = n /\ m = m n = n /\ m = m (Note that, since we are working with natural numbers, not fixed-size machine integers, we don't need to worry about the possibility of arithmetic overflow anywhere in this argument.) ) ( ####################################################### ) (* ** Example: Simple Conditionals ) (* Here is a simple decorated program using conditionals: (1) {{True}} IFB X <= Y THEN (2) {{True /\ X <= Y}} ->> (3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}} Z ::= Y - X (4) {{Z + X = Y \/ Z + Y = X}} ELSE (5) {{True /\ ~(X <= Y) }} ->> (6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}} Z ::= X - Y (7) {{Z + X = Y \/ Z + Y = X}} FI (8) {{Z + X = Y \/ Z + Y = X}} These decorations were constructed as follows: - We start with the outer precondition (1) and postcondition (8). - We follow the format dictated by the [hoare_if] rule and copy the postcondition (8) to (4) and (7). We conjoin the precondition (1) with the guard of the conditional to obtain (2). We conjoin (1) with the negated guard of the conditional to obtain (5). - In order to use the assignment rule and obtain (3), we substitute [Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y] in (7). - Finally, we verify that (2) implies (3) and (5) implies (6). Both of these implications crucially depend on the ordering of [X] and [Y] obtained from the guard. For instance, knowing that [X <= Y] ensures that subtracting [X] from [Y] and then adding back [X] produces [Y], as required by the first disjunct of (3). Similarly, knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and then adding back [Y] produces [X], as needed by the second disjunct of (6). Note that [n - m + m = n] does _not_ hold for arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 = 5]). ) (* **** Exercise: 2 stars (if_minus_plus_reloaded) ) (* Fill in valid decorations for the following program: {{ True }} IFB X <= Y THEN {{ }} ->> {{ }} Z ::= Y - X {{ }} ELSE {{ }} ->> {{ }} Y ::= X + Z {{ }} FI {{ Y = X + Z }} ) (* [] ) ( ####################################################### ) (* ** Example: Reduce to Zero (Trivial Loop) ) (* Here is a [WHILE] loop that is so simple it needs no invariant (i.e., the invariant [True] will do the job). (1) {{ True }} WHILE X <> 0 DO (2) {{ True /\ X <> 0 }} ->> (3) {{ True }} X ::= X - 1 (4) {{ True }} END (5) {{ True /\ X = 0 }} ->> (6) {{ X = 0 }} The decorations can be constructed as follows: - Start with the outer precondition (1) and postcondition (6). - Following the format dictated by the [hoare_while] rule, we copy (1) to (4). We conjoin (1) with the guard to obtain (2) and with the negation of the guard to obtain (5). Note that, because the outer postcondition (6) does not syntactically match (5), we need a trivial use of the consequence rule from (5) to (6). - Assertion (3) is the same as (4), because [X] does not appear in [4], so the substitution in the assignment rule is trivial. - Finally, the implication between (2) and (3) is also trivial. ) (* From this informal proof, it is easy to read off a formal proof using the Coq versions of the Hoare rules. Note that we do _not_ unfold the definition of [hoare_triple] anywhere in this proof -- the idea is to use the Hoare rules as a "self-contained" logic for reasoning about programs. ) Definition reduce_to_zero' : com := WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= AMinus (AId X) (ANum 1) END. Theorem reduce_to_zero_correct' : {{fun st => True}} reduce_to_zero' {{fun st => st X = 0}}. Proof. unfold reduce_to_zero'. ( First we need to transform the postcondition so that hoare_while will apply. ) eapply hoare_consequence_post. apply hoare_while. Case "Loop body preserves invariant". ( Need to massage precondition before [hoare_asgn] applies ) eapply hoare_consequence_pre. apply hoare_asgn. ( Proving trivial implication (2) ->> (3) ) intros st [HT Hbp]. unfold assn_sub. apply I. Case "Invariant and negated guard imply postcondition". intros st [Inv GuardFalse]. unfold bassn in GuardFalse. simpl in GuardFalse. ( SearchAbout helps to find the right lemmas ) SearchAbout [not true]. rewrite not_true_iff_false in GuardFalse. SearchAbout [negb false]. rewrite negb_false_iff in GuardFalse. SearchAbout [beq_nat true]. apply beq_nat_true in GuardFalse. apply GuardFalse. Qed. ( ####################################################### ) (* ** Example: Division ) (* The following Imp program calculates the integer division and remainder of two numbers [m] and [n] that are arbitrary constants in the program. X ::= m;; Y ::= 0;; WHILE n <= X DO X ::= X - n;; Y ::= Y + 1 END; In other words, if we replace [m] and [n] by concrete numbers and execute the program, it will terminate with the variable [X] set to the remainder when [m] is divided by [n] and [Y] set to the quotient. ) (* In order to give a specification to this program we need to remember that dividing [m] by [n] produces a reminder [X] and a quotient [Y] so that [n * Y + X = m /\ X < n]. It turns out that we get lucky with this program and don't have to think very hard about the loop invariant: the invariant is the just first conjunct [n * Y + X = m], so we use that to decorate the program. (1) {{ True }} ->> (2) {{ n * 0 + m = m }} X ::= m;; (3) {{ n * 0 + X = m }} Y ::= 0;; (4) {{ n * Y + X = m }} WHILE n <= X DO (5) {{ n * Y + X = m /\ n <= X }} ->> (6) {{ n * (Y + 1) + (X - n) = m }} X ::= X - n;; (7) {{ n * (Y + 1) + X = m }} Y ::= Y + 1 (8) {{ n * Y + X = m }} END (9) {{ n * Y + X = m /\ X < n }} Assertions (4), (5), (8), and (9) are derived mechanically from the invariant and the loop's guard. Assertions (8), (7), and (6) are derived using the assignment rule going backwards from (8) to (6). Assertions (4), (3), and (2) are again backwards applications of the assignment rule. Now that we've decorated the program it only remains to check that the two uses of the consequence rule are correct -- i.e., that (1) implies (2) and that (5) implies (6). This is indeed the case, so we have a valid decorated program. ) ( ####################################################### ) (* * Finding Loop Invariants ) (* Once the outermost precondition and postcondition are chosen, the only creative part in verifying programs with Hoare Logic is finding the right loop invariants. The reason this is difficult is the same as the reason that doing inductive mathematical proofs requires creativity: strengthening the loop invariant (or the induction hypothesis) means that you have a stronger assumption to work with when trying to establish the postcondition of the loop body (complete the induction step of the proof), but it also means that the loop body postcondition itself is harder to prove! This section is dedicated to teaching you how to approach the challenge of finding loop invariants using a series of examples and exercises. ) (* ** Example: Slow Subtraction ) (* The following program subtracts the value of [X] from the value of [Y] by repeatedly decrementing both [X] and [Y]. We want to verify its correctness with respect to the following specification: {{ X = m /\ Y = n }} WHILE X <> 0 DO Y ::= Y - 1;; X ::= X - 1 END {{ Y = n - m }} To verify this program we need to find an invariant [I] for the loop. As a first step we can leave [I] as an unknown and build a _skeleton_ for the proof by applying backward the rules for local consistency. This process leads to the following skeleton: (1) {{ X = m /\ Y = n }} ->> (a) (2) {{ I }} WHILE X <> 0 DO (3) {{ I /\ X <> 0 }} ->> (c) (4) {{ I[X \|-> X-1][Y \|-> Y-1] }} Y ::= Y - 1;; (5) {{ I[X \|-> X-1] }} X ::= X - 1 (6) {{ I }} END (7) {{ I /\ ~(X <> 0) }} ->> (b) (8) {{ Y = n - m }} By examining this skeleton, we can see that any valid [I] will have to respect three conditions: - (a) it must be weak enough to be implied by the loop's precondition, i.e. (1) must imply (2); - (b) it must be strong enough to imply the loop's postcondition, i.e. (7) must imply (8); - (c) it must be preserved by one iteration of the loop, i.e. (3) must imply (4). ) (* These conditions are actually independent of the particular program and specification we are considering. Indeed, every loop invariant has to satisfy them. One way to find an invariant that simultaneously satisfies these three conditions is by using an iterative process: start with a "candidate" invariant (e.g. a guess or a heuristic choice) and check the three conditions above; if any of the checks fails, try to use the information that we get from the failure to produce another (hopefully better) candidate invariant, and repeat the process. For instance, in the reduce-to-zero example above, we saw that, for a very simple loop, choosing [True] as an invariant did the job. So let's try it again here! I.e., let's instantiate [I] with [True] in the skeleton above see what we get... (1) {{ X = m /\ Y = n }} ->> (a - OK) (2) {{ True }} WHILE X <> 0 DO (3) {{ True /\ X <> 0 }} ->> (c - OK) (4) {{ True }} Y ::= Y - 1;; (5) {{ True }} X ::= X - 1 (6) {{ True }} END (7) {{ True /\ X = 0 }} ->> (b - WRONG!) (8) {{ Y = n - m }} While conditions (a) and (c) are trivially satisfied, condition (b) is wrong, i.e. it is not the case that (7) [True /\ X = 0] implies (8) [Y = n - m]. In fact, the two assertions are completely unrelated and it is easy to find a counterexample (say, [Y = X = m = 0] and [n = 1]). If we want (b) to hold, we need to strengthen the invariant so that it implies the postcondition (8). One very simple way to do this is to let the invariant _be_ the postcondition. So let's return to our skeleton, instantiate [I] with [Y = n - m], and check conditions (a) to (c) again. (1) {{ X = m /\ Y = n }} ->> (a - WRONG!) (2) {{ Y = n - m }} WHILE X <> 0 DO (3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!) (4) {{ Y - 1 = n - m }} Y ::= Y - 1;; (5) {{ Y = n - m }} X ::= X - 1 (6) {{ Y = n - m }} END (7) {{ Y = n - m /\ X = 0 }} ->> (b - OK) (8) {{ Y = n - m }} This time, condition (b) holds trivially, but (a) and (c) are broken. Condition (a) requires that (1) [X = m /\ Y = n] implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to show that [n = n - m] for arbitrary [m] and [n], which does not hold (for instance, when [m = n = 1]). Condition (c) requires that [n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m = 0]. So, although [Y = n - m] holds at the end of the loop, it does not hold from the start, and it doesn't hold on each iteration; it is not a correct invariant. This failure is not very surprising: the variable [Y] changes during the loop, while [m] and [n] are constant, so the assertion we chose didn't have much chance of being an invariant! To do better, we need to generalize (8) to some statement that is equivalent to (8) when [X] is [0], since this will be the case when the loop terminates, and that "fills the gap" in some appropriate way when [X] is nonzero. Looking at how the loop works, we can observe that [X] and [Y] are decremented together until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially, after one iteration of the loop we obtain [X = 1] and [Y = 4]; after two iterations [X = 0] and [Y = 3]; and then the loop stops. Notice that the difference between [Y] and [X] stays constant between iterations; initially, [Y = n] and [X = m], so this difference is always [n - m]. So let's try instantiating [I] in the skeleton above with [Y - X = n - m]. (1) {{ X = m /\ Y = n }} ->> (a - OK) (2) {{ Y - X = n - m }} WHILE X <> 0 DO (3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK) (4) {{ (Y - 1) - (X - 1) = n - m }} Y ::= Y - 1;; (5) {{ Y - (X - 1) = n - m }} X ::= X - 1 (6) {{ Y - X = n - m }} END (7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK) (8) {{ Y = n - m }} Success! Conditions (a), (b) and (c) all hold now. (To verify (c), we need to check that, under the assumption that [X <> 0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all natural numbers [X] and [Y].) ) ( ####################################################### ) (* ** Exercise: Slow Assignment ) (* **** Exercise: 2 stars (slow_assignment) ) (* A roundabout way of assigning a number currently stored in [X] to the variable [Y] is to start [Y] at [0], then decrement [X] until it hits [0], incrementing [Y] at each step. Here is a program that implements this idea: {{ X = m }} Y ::= 0;; WHILE X <> 0 DO X ::= X - 1;; Y ::= Y + 1 END {{ Y = m }} Write an informal decorated program showing that this is correct. ) ( FILL IN HERE ) (* [] ) ( ####################################################### ) (* ** Exercise: Slow Addition ) (* **** Exercise: 3 stars, optional (add_slowly_decoration) ) (* The following program adds the variable X into the variable Z by repeatedly decrementing X and incrementing Z. WHILE X <> 0 DO Z ::= Z + 1;; X ::= X - 1 END Following the pattern of the [subtract_slowly] example above, pick a precondition and postcondition that give an appropriate specification of [add_slowly]; then (informally) decorate the program accordingly. ) ( FILL IN HERE ) (* [] ) ( ####################################################### ) (* ** Example: Parity ) (* Here is a cute little program for computing the parity of the value initially stored in [X] (due to Daniel Cristofani). {{ X = m }} WHILE 2 <= X DO X ::= X - 2 END {{ X = parity m }} The mathematical [parity] function used in the specification is defined in Coq as follows: ) Fixpoint parity x := match x with \| 0 => 0 \| 1 => 1 \| S (S x') => parity x' end. (* The postcondition does not hold at the beginning of the loop, since [m = parity m] does not hold for an arbitrary [m], so we cannot use that as an invariant. To find an invariant that works, let's think a bit about what this loop does. On each iteration it decrements [X] by [2], which preserves the parity of [X]. So the parity of [X] does not change, i.e. it is invariant. The initial value of [X] is [m], so the parity of [X] is always equal to the parity of [m]. Using [parity X = parity m] as an invariant we obtain the following decorated program: {{ X = m }} ->> (a - OK) {{ parity X = parity m }} WHILE 2 <= X DO {{ parity X = parity m /\ 2 <= X }} ->> (c - OK) {{ parity (X-2) = parity m }} X ::= X - 2 {{ parity X = parity m }} END {{ parity X = parity m /\ X < 2 }} ->> (b - OK) {{ X = parity m }} With this invariant, conditions (a), (b), and (c) are all satisfied. For verifying (b), we observe that, when [X < 2], we have [parity X = X] (we can easily see this in the definition of [parity]). For verifying (c), we observe that, when [2 <= X], we have [parity X = parity (X-2)]. ) (* **** Exercise: 3 stars, optional (parity_formal) ) (* Translate this proof to Coq. Refer to the reduce-to-zero example for ideas. You may find the following two lemmas useful: ) Lemma parity_ge_2 : forall x, 2 <= x -> parity (x - 2) = parity x. Proof. induction x; intro. reflexivity. destruct x. inversion H. inversion H1. simpl. rewrite <- minus_n_O. reflexivity. Qed. Lemma parity_lt_2 : forall x, ~ 2 <= x -> parity (x) = x. Proof. intros. induction x. reflexivity. destruct x. reflexivity. apply ex_falso_quodlibet. apply H. omega. Qed. Theorem parity_correct : forall m, {{ fun st => st X = m }} WHILE BLe (ANum 2) (AId X) DO X ::= AMinus (AId X) (ANum 2) END {{ fun st => st X = parity m }}. Proof. ( FILL IN HERE ) Admitted. (* [] ) ( ####################################################### ) (* ** Example: Finding Square Roots ) (* The following program computes the square root of [X] by naive iteration: {{ X=m }} Z ::= 0;; WHILE (Z+1)(Z+1) <= X DO Z ::= Z+1 END {{ ZZ<=m /\ m<(Z+1)(Z+1) }} ) (** As above, we can try to use the postcondition as a candidate invariant, obtaining the following decorated program: (1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!) (2) {{ 00 <= m /\ m<11 }} Z ::= 0;; (3) {{ ZZ <= m /\ m<(Z+1)(Z+1) }} WHILE (Z+1)(Z+1) <= X DO (4) {{ ZZ<=m /\ (Z+1)(Z+1)<=X }} ->> (c - WRONG!) (5) {{ (Z+1)(Z+1)<=m /\ m<(Z+2)(Z+2) }} Z ::= Z+1 (6) {{ ZZ<=m /\ m<(Z+1)(Z+1) }} END (7) {{ ZZ<=m /\ m<(Z+1)(Z+1) /\ X<(Z+1)(Z+1) }} ->> (b - OK) (8) {{ ZZ<=m /\ m<(Z+1)(Z+1) }} This didn't work very well: both conditions (a) and (c) failed. Looking at condition (c), we see that the second conjunct of (4) is almost the same as the first conjunct of (5), except that (4) mentions [X] while (5) mentions [m]. But note that [X] is never assigned in this program, so we should have [X=m], but we didn't propagate this information from (1) into the loop invariant. Also, looking at the second conjunct of (8), it seems quite hopeless as an invariant -- and we don't even need it, since we can obtain it from the negation of the guard (third conjunct in (7)), again under the assumption that [X=m]. So we now try [X=m /\ ZZ <= m] as the loop invariant: {{ X=m }} ->> (a - OK) {{ X=m /\ 00 <= m }} Z ::= 0; {{ X=m /\ ZZ <= m }} WHILE (Z+1)(Z+1) <= X DO {{ X=m /\ ZZ<=m /\ (Z+1)(Z+1)<=X }} ->> (c - OK) {{ X=m /\ (Z+1)(Z+1)<=m }} Z ::= Z+1 {{ X=m /\ ZZ<=m }} END {{ X=m /\ ZZ<=m /\ X<(Z+1)(Z+1) }} ->> (b - OK) {{ ZZ<=m /\ m<(Z+1)(Z+1) }} This works, since conditions (a), (b), and (c) are now all trivially satisfied. Very often, if a variable is used in a loop in a read-only fashion (i.e., it is referred to by the program or by the specification and it is not changed by the loop) it is necessary to add the fact that it doesn't change to the loop invariant. ) ( ####################################################### ) (* ** Example: Squaring ) (* Here is a program that squares [X] by repeated addition: {{ X = m }} Y ::= 0;; Z ::= 0;; WHILE Y <> X DO Z ::= Z + X;; Y ::= Y + 1 END {{ Z = mm }} ) (** The first thing to note is that the loop reads [X] but doesn't change its value. As we saw in the previous example, in such cases it is a good idea to add [X = m] to the invariant. The other thing we often use in the invariant is the postcondition, so let's add that too, leading to the invariant candidate [Z = m * m /\ X = m]. {{ X = m }} ->> (a - WRONG) {{ 0 = mm /\ X = m }} Y ::= 0;; {{ 0 = mm /\ X = m }} Z ::= 0;; {{ Z = mm /\ X = m }} WHILE Y <> X DO {{ Z = Ym /\ X = m /\ Y <> X }} ->> (c - WRONG) {{ Z+X = mm /\ X = m }} Z ::= Z + X;; {{ Z = mm /\ X = m }} Y ::= Y + 1 {{ Z = mm /\ X = m }} END {{ Z = mm /\ X = m /\ Y = X }} ->> (b - OK) {{ Z = mm }} Conditions (a) and (c) fail because of the [Z = mm] part. While [Z] starts at [0] and works itself up to [mm], we can't expect [Z] to be [mm] from the start. If we look at how [Z] progesses in the loop, after the 1st iteration [Z = m], after the 2nd iteration [Z = 2m], and at the end [Z = mm]. Since the variable [Y] tracks how many times we go through the loop, we derive the new invariant candidate [Z = Ym /\ X = m]. {{ X = m }} ->> (a - OK) {{ 0 = 0m /\ X = m }} Y ::= 0;; {{ 0 = Ym /\ X = m }} Z ::= 0;; {{ Z = Ym /\ X = m }} WHILE Y <> X DO {{ Z = Ym /\ X = m /\ Y <> X }} ->> (c - OK) {{ Z+X = (Y+1)m /\ X = m }} Z ::= Z + X; {{ Z = (Y+1)m /\ X = m }} Y ::= Y + 1 {{ Z = Ym /\ X = m }} END {{ Z = Ym /\ X = m /\ Y = X }} ->> (b - OK) {{ Z = mm }} This new invariant makes the proof go through: all three conditions are easy to check. It is worth comparing the postcondition [Z = mm] and the [Z = Ym] conjunct of the invariant. It is often the case that one has to replace auxiliary variabes (parameters) with variables -- or with expressions involving both variables and parameters (like [m - Y]) -- when going from postconditions to invariants. ) ( ####################################################### ) (* ** Exercise: Factorial ) (* **** Exercise: 3 stars (factorial) ) (* Recall that [n!] denotes the factorial of [n] (i.e. [n! = 12...n]). Here is an Imp program that calculates the factorial of the number initially stored in the variable [X] and puts it in the variable [Y]: {{ X = m }} Y ::= 1 ;; WHILE X <> 0 DO Y ::= Y X ;; X ::= X - 1 END {{ Y = m! }} Fill in the blanks in following decorated program: {{ X = m }} ->> {{ }} Y ::= 1;; {{ }} WHILE X <> 0 DO {{ }} ->> {{ }} Y ::= Y * X;; {{ }} X ::= X - 1 {{ }} END {{ }} ->> {{ Y = m! }} ) (* [] ) ( ####################################################### ) (* ** Exercise: Min ) (* **** Exercise: 3 stars (Min_Hoare) ) (* Fill in valid decorations for the following program. For the => steps in your annotations, you may rely (silently) on the following facts about min Lemma lemma1 : forall x y, (x=0 \/ y=0) -> min x y = 0. Lemma lemma2 : forall x y, min (x-1) (y-1) = (min x y) - 1. plus, as usual, standard high-school algebra. {{ True }} ->> {{ }} X ::= a;; {{ }} Y ::= b;; {{ }} Z ::= 0;; {{ }} WHILE (X <> 0 /\ Y <> 0) DO {{ }} ->> {{ }} X := X - 1;; {{ }} Y := Y - 1;; {{ }} Z := Z + 1 {{ }} END {{ }} ->> {{ Z = min a b }} ) (* [] ) (* **** Exercise: 3 stars (two_loops) ) (* Here is a very inefficient way of adding 3 numbers: X ::= 0;; Y ::= 0;; Z ::= c;; WHILE X <> a DO X ::= X + 1;; Z ::= Z + 1 END;; WHILE Y <> b DO Y ::= Y + 1;; Z ::= Z + 1 END Show that it does what it should by filling in the blanks in the following decorated program. {{ True }} ->> {{ }} X ::= 0;; {{ }} Y ::= 0;; {{ }} Z ::= c;; {{ }} WHILE X <> a DO {{ }} ->> {{ }} X ::= X + 1;; {{ }} Z ::= Z + 1 {{ }} END;; {{ }} ->> {{ }} WHILE Y <> b DO {{ }} ->> {{ }} Y ::= Y + 1;; {{ }} Z ::= Z + 1 {{ }} END {{ }} ->> {{ Z = a + b + c }} ) (* [] ) ( ####################################################### ) (* ** Exercise: Power Series ) (* **** Exercise: 4 stars, optional (dpow2_down) ) (* Here is a program that computes the series: [1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1] X ::= 0;; Y ::= 1;; Z ::= 1;; WHILE X <> m DO Z ::= 2 * Z;; Y ::= Y + Z;; X ::= X + 1 END Write a decorated program for this. ) ( FILL IN HERE ) ( ####################################################### ) (* * Weakest Preconditions (Advanced) ) (* Some Hoare triples are more interesting than others. For example, {{ False }} X ::= Y + 1 {{ X <= 5 }} is _not_ very interesting: although it is perfectly valid, it tells us nothing useful. Since the precondition isn't satisfied by any state, it doesn't describe any situations where we can use the command [X ::= Y + 1] to achieve the postcondition [X <= 5]. By contrast, {{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }} is useful: it tells us that, if we can somehow create a situation in which we know that [Y <= 4 /\ Z = 0], then running this command will produce a state satisfying the postcondition. However, this triple is still not as useful as it could be, because the [Z = 0] clause in the precondition actually has nothing to do with the postcondition [X <= 5]. The _most_ useful triple (for a given command and postcondition) is this one: {{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }} In other words, [Y <= 4] is the _weakest_ valid precondition of the command [X ::= Y + 1] for the postcondition [X <= 5]. ) (* In general, we say that "[P] is the weakest precondition of command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if, whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have [P' st] implies [P st] for all states [st]. ) Definition is_wp P c Q := {{P}} c {{Q}} /\ forall P', {{P'}} c {{Q}} -> (P' ->> P). (* That is, [P] is the weakest precondition of [c] for [Q] if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the _weakest_ (easiest to satisfy) assertion that guarantees [Q] after executing [c]. ) (* **** Exercise: 1 star, optional (wp) ) (* What are the weakest preconditions of the following commands for the following postconditions? 1) {{ ? }} SKIP {{ X = 5 }} 2) {{ ? }} X ::= Y + Z {{ X = 5 }} 3) {{ ? }} X ::= Y {{ X = Y }} 4) {{ ? }} IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI {{ Y = 5 }} 5) {{ ? }} X ::= 5 {{ X = 0 }} 6) {{ ? }} WHILE True DO X ::= 0 END {{ X = 0 }} ) ( FILL IN HERE ) (* [] ) (* **** Exercise: 3 stars, advanced, optional (is_wp_formal) ) (* Prove formally using the definition of [hoare_triple] that [Y <= 4] is indeed the weakest precondition of [X ::= Y + 1] with respect to postcondition [X <= 5]. ) Theorem is_wp_example : is_wp (fun st => st Y <= 4) (X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5). Proof. ( FILL IN HERE ) Admitted. (* [] ) (* **** Exercise: 2 stars, advanced (hoare_asgn_weakest) ) (* Show that the precondition in the rule [hoare_asgn] is in fact the weakest precondition. ) Theorem hoare_asgn_weakest : forall Q X a, is_wp (Q [X \|-> a]) (X ::= a) Q. Proof. ( FILL IN HERE ) Admitted. (* [] ) (* **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) ) (* Show that your [havoc_pre] rule from the [himp_hoare] exercise in the [Hoare] chapter returns the weakest precondition. ) Module Himp2. Import Himp. Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id), {{ P }} HAVOC X {{ Q }} -> P ->> havoc_pre X Q. Proof. ( FILL IN HERE ) Admitted. End Himp2. (* [] ) ( ####################################################### ) (* * Formal Decorated Programs (Advanced) ) (* The informal conventions for decorated programs amount to a way of displaying Hoare triples in which commands are annotated with enough embedded assertions that checking the validity of the triple is reduced to simple logical and algebraic calculations showing that some assertions imply others. In this section, we show that this informal presentation style can actually be made completely formal and indeed that checking the validity of decorated programs can mostly be automated. ) (* ** Syntax ) (* The first thing we need to do is to formalize a variant of the syntax of commands with embedded assertions. We call the new commands _decorated commands_, or [dcom]s. ) Inductive dcom : Type := \| DCSkip : Assertion -> dcom \| DCSeq : dcom -> dcom -> dcom \| DCAsgn : id -> aexp -> Assertion -> dcom \| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom -> Assertion-> dcom \| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom \| DCPre : Assertion -> dcom -> dcom \| DCPost : dcom -> Assertion -> dcom. Tactic Notation "dcom_cases" tactic(first) ident(c) := first; [ Case_aux c "Skip" \| Case_aux c "Seq" \| Case_aux c "Asgn" \| Case_aux c "If" \| Case_aux c "While" \| Case_aux c "Pre" \| Case_aux c "Post" ]. Notation "'SKIP' {{ P }}" := (DCSkip P) (at level 10) : dcom_scope. Notation "l '::=' a {{ P }}" := (DCAsgn l a P) (at level 60, a at next level) : dcom_scope. Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}" := (DCWhile b Pbody d Ppost) (at level 80, right associativity) : dcom_scope. Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}" := (DCIf b P d P' d' Q) (at level 80, right associativity) : dcom_scope. Notation "'->>' {{ P }} d" := (DCPre P d) (at level 90, right associativity) : dcom_scope. Notation "{{ P }} d" := (DCPre P d) (at level 90) : dcom_scope. Notation "d '->>' {{ P }}" := (DCPost d P) (at level 80, right associativity) : dcom_scope. Notation " d ;; d' " := (DCSeq d d') (at level 80, right associativity) : dcom_scope. Delimit Scope dcom_scope with dcom. (* To avoid clashing with the existing [Notation] definitions for ordinary [com]mands, we introduce these notations in a special scope called [dcom_scope], and we wrap examples with the declaration [% dcom] to signal that we want the notations to be interpreted in this scope. Careful readers will note that we've defined two notations for the [DCPre] constructor, one with and one without a [->>]. The "without" version is intended to be used to supply the initial precondition at the very top of the program. ) Example dec_while : dcom := ( {{ fun st => True }} WHILE (BNot (BEq (AId X) (ANum 0))) DO {{ fun st => True /\ st X <> 0}} X ::= (AMinus (AId X) (ANum 1)) {{ fun _ => True }} END {{ fun st => True /\ st X = 0}} ->> {{ fun st => st X = 0 }} ) % dcom. (* It is easy to go from a [dcom] to a [com] by erasing all annotations. ) Fixpoint extract (d:dcom) : com := match d with \| DCSkip _ => SKIP \| DCSeq d1 d2 => (extract d1 ;; extract d2) \| DCAsgn X a _ => X ::= a \| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI \| DCWhile b _ d _ => WHILE b DO extract d END \| DCPre _ d => extract d \| DCPost d _ => extract d end. (* The choice of exactly where to put assertions in the definition of [dcom] is a bit subtle. The simplest thing to do would be to annotate every [dcom] with a precondition and postcondition. But this would result in very verbose programs with a lot of repeated annotations: for example, a program like [SKIP;SKIP] would have to be annotated as {{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}}, with pre- and post-conditions on each [SKIP], plus identical pre- and post-conditions on the semicolon! Instead, the rule we've followed is this: - The _post_-condition expected by each [dcom] [d] is embedded in [d] - The _pre_-condition is supplied by the context. ) (* In other words, the invariant of the representation is that a [dcom] [d] together with a precondition [P] determines a Hoare triple [{{P}} (extract d) {{post d}}], where [post] is defined as follows: ) Fixpoint post (d:dcom) : Assertion := match d with \| DCSkip P => P \| DCSeq d1 d2 => post d2 \| DCAsgn X a Q => Q \| DCIf _ _ d1 _ d2 Q => Q \| DCWhile b Pbody c Ppost => Ppost \| DCPre _ d => post d \| DCPost c Q => Q end. (* Similarly, we can extract the "initial precondition" from a decorated program. ) Fixpoint pre (d:dcom) : Assertion := match d with \| DCSkip P => fun st => True \| DCSeq c1 c2 => pre c1 \| DCAsgn X a Q => fun st => True \| DCIf _ _ t _ e _ => fun st => True \| DCWhile b Pbody c Ppost => fun st => True \| DCPre P c => P \| DCPost c Q => pre c end. (* This function is not doing anything sophisticated like calculating a weakest precondition; it just recursively searches for an explicit annotation at the very beginning of the program, returning default answers for programs that lack an explicit precondition (like a bare assignment or [SKIP]). ) (* Using [pre] and [post], and assuming that we adopt the convention of always supplying an explicit precondition annotation at the very beginning of our decorated programs, we can express what it means for a decorated program to be correct as follows: ) Definition dec_correct (d:dcom) := {{pre d}} (extract d) {{post d}}. (* To check whether this Hoare triple is _valid_, we need a way to extract the "proof obligations" from a decorated program. These obligations are often called _verification conditions_, because they are the facts that must be verified to see that the decorations are logically consistent and thus add up to a complete proof of correctness. ) (* ** Extracting Verification Conditions ) (* The function [verification_conditions] takes a [dcom] [d] together with a precondition [P] and returns a _proposition_ that, if it can be proved, implies that the triple [{{P}} (extract d) {{post d}}] is valid. ) (* It does this by walking over [d] and generating a big conjunction including all the "local checks" that we listed when we described the informal rules for decorated programs. (Strictly speaking, we need to massage the informal rules a little bit to add some uses of the rule of consequence, but the correspondence should be clear.) ) Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop := match d with \| DCSkip Q => (P ->> Q) \| DCSeq d1 d2 => verification_conditions P d1 /\ verification_conditions (post d1) d2 \| DCAsgn X a Q => (P ->> Q [X \|-> a]) \| DCIf b P1 d1 P2 d2 Q => ((fun st => P st /\ bassn b st) ->> P1) /\ ((fun st => P st /\ ~ (bassn b st)) ->> P2) /\ (Q <<->> post d1) /\ (Q <<->> post d2) /\ verification_conditions P1 d1 /\ verification_conditions P2 d2 \| DCWhile b Pbody d Ppost => ( post d is the loop invariant and the initial precondition ) (P ->> post d) /\ (Pbody <<->> (fun st => post d st /\ bassn b st)) /\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st))) /\ verification_conditions Pbody d \| DCPre P' d => (P ->> P') /\ verification_conditions P' d \| DCPost d Q => verification_conditions P d /\ (post d ->> Q) end. (* And now, the key theorem, which states that [verification_conditions] does its job correctly. Not surprisingly, we need to use each of the Hoare Logic rules at some point in the proof. ) (* We have used _in_ variants of several tactics before to apply them to values in the context rather than the goal. An extension of this idea is the syntax [tactic in ], which applies [tactic] in the goal and every hypothesis in the context. We most commonly use this facility in conjunction with the [simpl] tactic, as below. ) Theorem verification_correct : forall d P, verification_conditions P d -> {{P}} (extract d) {{post d}}. Proof. dcom_cases (induction d) Case; intros P H; simpl in . Case "Skip". eapply hoare_consequence_pre. apply hoare_skip. assumption. Case "Seq". inversion H as [H1 H2]. clear H. eapply hoare_seq. apply IHd2. apply H2. apply IHd1. apply H1. Case "Asgn". eapply hoare_consequence_pre. apply hoare_asgn. assumption. Case "If". inversion H as [HPre1 [HPre2 [[Hd11 Hd12] [[Hd21 Hd22] [HThen HElse]]]]]. clear H. apply IHd1 in HThen. clear IHd1. apply IHd2 in HElse. clear IHd2. apply hoare_if. eapply hoare_consequence_pre; eauto. eapply hoare_consequence_post; eauto. eapply hoare_consequence_pre; eauto. eapply hoare_consequence_post; eauto. Case "While". inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]]; subst; clear H. eapply hoare_consequence_pre; eauto. eapply hoare_consequence_post; eauto. apply hoare_while. eapply hoare_consequence_pre; eauto. Case "Pre". inversion H as [HP Hd]; clear H. eapply hoare_consequence_pre. apply IHd. apply Hd. assumption. Case "Post". inversion H as [Hd HQ]; clear H. eapply hoare_consequence_post. apply IHd. apply Hd. assumption. Qed. (* ** Examples ) (* The propositions generated by [verification_conditions] are fairly big, and they contain many conjuncts that are essentially trivial. ) Eval simpl in (verification_conditions (fun st => True) dec_while). (* ==> (((fun _ : state => True) ->> (fun _ : state => True)) /\ ((fun _ : state => True) ->> (fun _ : state => True)) /\ (fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) = (fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\ (fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) = (fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\ (fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->> (fun _ : state => True) [X \|-> AMinus (AId X) (ANum 1)]) /\ (fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->> (fun st : state => st X = 0) ) (* In principle, we could certainly work with them using just the tactics we have so far, but we can make things much smoother with a bit of automation. We first define a custom [verify] tactic that applies splitting repeatedly to turn all the conjunctions into separate subgoals and then uses [omega] and [eauto] (a handy general-purpose automation tactic that we'll discuss in detail later) to deal with as many of them as possible. ) Lemma ble_nat_true_iff : forall n m : nat, ble_nat n m = true <-> n <= m. Proof. intros n m. split. apply ble_nat_true. generalize dependent m. induction n; intros m H. reflexivity. simpl. destruct m. inversion H. apply le_S_n in H. apply IHn. assumption. Qed. Lemma ble_nat_false_iff : forall n m : nat, ble_nat n m = false <-> ~(n <= m). Proof. intros n m. split. apply ble_nat_false. generalize dependent m. induction n; intros m H. apply ex_falso_quodlibet. apply H. apply le_0_n. simpl. destruct m. reflexivity. apply IHn. intro Hc. apply H. apply le_n_S. assumption. Qed. Tactic Notation "verify" := apply verification_correct; repeat split; simpl; unfold assert_implies; unfold bassn in ; unfold beval in ; unfold aeval in ; unfold assn_sub; intros; repeat rewrite update_eq; repeat (rewrite update_neq; [\| (intro X; inversion X)]); simpl in ; repeat match goal with [H : _ /\ _ \|- _] => destruct H end; repeat rewrite not_true_iff_false in ; repeat rewrite not_false_iff_true in ; repeat rewrite negb_true_iff in ; repeat rewrite negb_false_iff in ; repeat rewrite beq_nat_true_iff in ; repeat rewrite beq_nat_false_iff in ; repeat rewrite ble_nat_true_iff in ; repeat rewrite ble_nat_false_iff in ; try subst; repeat match goal with [st : state \|- _] => match goal with [H : st _ = _ \|- _] => rewrite -> H in ; clear H \| [H : _ = st _ \|- _] => rewrite <- H in ; clear H end end; try eauto; try omega. (* What's left after [verify] does its thing is "just the interesting parts" of checking that the decorations are correct. For very simple examples [verify] immediately solves the goal (provided that the annotations are correct). ) Theorem dec_while_correct : dec_correct dec_while. Proof. verify. Qed. (* Another example (formalizing a decorated program we've seen before): ) Example subtract_slowly_dec (m:nat) (p:nat) : dcom := ( {{ fun st => st X = m /\ st Z = p }} ->> {{ fun st => st Z - st X = p - m }} WHILE BNot (BEq (AId X) (ANum 0)) DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->> {{ fun st => (st Z - 1) - (st X - 1) = p - m }} Z ::= AMinus (AId Z) (ANum 1) {{ fun st => st Z - (st X - 1) = p - m }} ;; X ::= AMinus (AId X) (ANum 1) {{ fun st => st Z - st X = p - m }} END {{ fun st => st Z - st X = p - m /\ st X = 0 }} ->> {{ fun st => st Z = p - m }} ) % dcom. Theorem subtract_slowly_dec_correct : forall m p, dec_correct (subtract_slowly_dec m p). Proof. intros m p. verify. ( this grinds for a bit! ) Qed. (* **** Exercise: 3 stars, advanced (slow_assignment_dec) ) (* In the [slow_assignment] exercise above, we saw a roundabout way of assigning a number currently stored in [X] to the variable [Y]: start [Y] at [0], then decrement [X] until it hits [0], incrementing [Y] at each step. Write a _formal_ version of this decorated program and prove it correct. ) Example slow_assignment_dec (m:nat) : dcom := ( FILL IN HERE ) admit. Theorem slow_assignment_dec_correct : forall m, dec_correct (slow_assignment_dec m). Proof. ( FILL IN HERE ) Admitted. (* [] ) (* **** Exercise: 4 stars, advanced (factorial_dec) ) (* Remember the factorial function we worked with before: ) Fixpoint real_fact (n:nat) : nat := match n with \| O => 1 \| S n' => n (real_fact n') end. (** Following the pattern of [subtract_slowly_dec], write a decorated program [factorial_dec] that implements the factorial function and prove it correct as [factorial_dec_correct]. ) ( FILL IN HERE ) (* [] ) (* $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2004 by Wilson Snyder. module t (/AUTOARG/ // Outputs ign, // Inputs clk ); input clk; output [31:0] ign; reg [31:0] right; reg [31:0] left; reg [63:0] qright; reg [63:0] qleft; reg [31:0] amt; assign ign = {31'h0, clk} >>> 4'bx; // bug760 always @* begin right = 32'h819b018a >> amt; left = 32'h819b018a << amt; qright = 64'hf784bf8f_12734089 >> amt; qleft = 64'hf784bf8f_12734089 >> amt; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright); `endif if (cyc==1) begin amt <= 32'd0; if (5'b10110>>2 != 5'b00101) $stop; if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness if (5'b10110<<2 != 5'b11000) $stop; if (5'b10110<<<2 != 5'b11000) $stop; if (5'sb10110>>2 != 5'sb00101) $stop; if (5'sb10110>>>2 != 5'sb11101) $stop; if (5'sb10110<<2 != 5'sb11000) $stop; if (5'sb10110<<<2 != 5'sb11000) $stop; // Allow >64 bit shifts if the shift amount is a constant if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; end if (cyc==2) begin amt <= 32'd28; if (left != 32'h819b018a) $stop; if (right != 32'h819b018a) $stop; if (qleft != 64'hf784bf8f_12734089) $stop; if (qright != 64'hf784bf8f_12734089) $stop; end if (cyc==3) begin amt <= 32'd31; if (left != 32'ha0000000) $stop; if (right != 32'h8) $stop; if (qleft != 64'h0000000f784bf8f1) $stop; if (qright != 64'h0000000f784bf8f1) $stop; end if (cyc==4) begin amt <= 32'd32; if (left != 32'h0) $stop; if (right != 32'h1) $stop; if (qleft != 64'h00000001ef097f1e) $stop; if (qright != 64'h00000001ef097f1e) $stop; end if (cyc==5) begin amt <= 32'd33; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h00000000f784bf8f) $stop; if (qright != 64'h00000000f784bf8f) $stop; end if (cyc==6) begin amt <= 32'd64; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h000000007bc25fc7) $stop; if (qright != 64'h000000007bc25fc7) $stop; end if (cyc==7) begin amt <= 32'd128; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==8) begin if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==9) begin $write("- All Finished -\n"); $finish; end end end endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Wilson Snyder. module t; function int int123(); int123 = 32'h123; endfunction function bit f_bit ; input bit i; f_bit = ~i; endfunction function int f_int ; input int i; f_int = ~i; endfunction function byte f_byte ; input byte i; f_byte = ~i; endfunction function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction function longint f_longint ; input longint i; f_longint = ~i; endfunction function chandle f_chandle ; input chandle i; f_chandle = i; endfunction // Note there's no "input" here vvvv, it's the default function bit g_bit (bit i); g_bit = ~i; endfunction function int g_int (int i); g_int = ~i; endfunction function byte g_byte (byte i); g_byte = ~i; endfunction function shortint g_shortint(shortint i); g_shortint = ~i; endfunction function longint g_longint (longint i); g_longint = ~i; endfunction function chandle g_chandle (chandle i); g_chandle = i; endfunction chandle c; initial begin if (int123() !== 32'h123) $stop; if (f_bit(1'h1) !== 1'h0) $stop; if (f_bit(1'h0) !== 1'h1) $stop; if (f_int(32'h1) !== 32'hfffffffe) $stop; if (f_byte(8'h1) !== 8'hfe) $stop; if (f_shortint(16'h1) !== 16'hfffe) $stop; if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (f_chandle(c) !== c) $stop; if (g_bit(1'h1) !== 1'h0) $stop; if (g_bit(1'h0) !== 1'h1) $stop; if (g_int(32'h1) !== 32'hfffffffe) $stop; if (g_byte(8'h1) !== 8'hfe) $stop; if (g_shortint(16'h1) !== 16'hfffe) $stop; if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (g_chandle(c) !== c) $stop; $write("- All Finished -\n"); $finish; end endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:09:39 08/25/2015 // Design Name: // Module Name: FSM_Add_Subtract // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module FSM_Add_Subtract ( //INPUTS input wire clk, //system clock input wire rst, //system reset input wire rst_FSM, input wire beg_FSM, //Begin Finite State Machine //REVISAD ////////////////////////////////////////////////////////////////////////////// //Oper_Start_In evaluation signals input wire zero_flag_i, //Exp_operation evaluation signals input wire norm_iteration_i, //Barrel_Shifter evaluation signals //None //Add_Subt_Sgf evaluation signals input wire add_overflow_i, //LZA evaluation signals //None //Deco_round evaluation Signals input wire round_i, //Final_result evaluation signals //None //OUTPUT SIGNALS //////////////////////////////////////////////////////////////////////////////////// //Oper_Start_In control signals output wire load_1_o,//Enable input registers output wire load_2_o,//Enable output registers //Exp_operation control signals output reg load_3_o, //Enable Output registers output reg load_8_o, output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift) //Barrel shifter control signals output reg load_4_o, //Enable Output registers output reg left_right_o, //Select direction shift (right=0, left=1) output reg bit_shift_o, //bit input for shifts fills //Add_Subt_sgf control signals output reg load_5_o, //Enables Output registers //LZA control signals output reg load_6_o, //Enables Output registers //Deco_Round control signals //None //Final_Result control signals output reg load_7_o, ///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ //Multiplexer selector for Exp_operation's OPER_A output reg ctrl_a_o, //Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value output reg [1:0] ctrl_b_o, output reg ctrl_b_load_o, //Multiplexer selector for Data shift output reg ctrl_c_o, //Multiplexer selector for Add_Subt_Sgf's inputs output reg ctrl_d_o, //Internal reset signal output reg rst_int, //Ready Signal output reg ready ); localparam [3:0] //First I'm going to declarate the registers of the first phase of execution start = 4'd0, //This state evaluates the beg_FSM to begin operations load_oper = 4'd1, //This state enables the registers that contains //both operands and the operator zero_info_state = 4'd2, //Evaluate zero condition load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first //result normalization extra1_64= 4'd4, norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the //second time (result normalization) add_subt = 4'd6, //Enable the add_subt_sgf's registers add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition overflow_add = 4'd8, round_sgf = 4'd9, //Evaluate the significand round condition overflow_add_r = 4'd10, extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition load_final_result = 4'd13, //Load the final_result's register with the result ready_flag = 4'd14; //Enable the ready flag with the final result //*******************REVISADO reg [3:0] state_reg, state_next ; //state registers declaration ////////////////////////Logic outputs///////////////77 assign load_1_o= (state_reg==load_oper); assign load_2_o= (state_reg==zero_info_state); //// always @(posedge clk, posedge rst) if (rst) begin state_reg <= start; end else begin state_reg <= state_next; end /// always @ begin state_next = state_reg; rst_int = 0; //Oper_Start_In control signals //load_1_o=0; //load_2_o=0; //Exp_operation control signals load_3_o=0; load_8_o=0; A_S_op_o=1; //Barrel shifter control signals load_4_o=0; left_right_o=0; bit_shift_o=0; //bit input for shifts fills //Add_Subt_sgf control signals load_5_o=0; //LZA control signals load_6_o=0; //Deco_Round control signals //None //Final_Result control signals load_7_o=0; ///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ //Multiplexer selector for Exp_operation's OPER_A ctrl_a_o=0; //Multiplexer selector for Exp_operation's OPER_B ctrl_b_o=2'b00; ctrl_b_load_o=0; //Multiplexer selector for Barrel_Shifter's Data shift ctrl_c_o=0; //Multiplexer selector for Barrel_Shifter's Shift value //Multiplexer selector for Add_Subt_Sgf's inputs ctrl_d_o=0; //Ready Phase ready = 0; //*REVISADO rst_int = 0; case(state_reg) //FPU reset start: begin rst_int=1; if(beg_FSM) begin state_next = load_oper; end end load_oper: //Load input registers for Oper_star in evaluation begin // load_1_o = 1; state_next = zero_info_state; end zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation begin if (zero_flag_i)begin state_next = ready_flag;end else begin //load_2_o = 1; state_next = load_diff_exp;end end load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in begin load_3_o = 1; / if ()*/ state_next = extra1_64; end extra1_64: begin load_3_o = 1; if (norm_iteration_i)begin load_8_o=1; if(add_overflow_i)begin A_S_op_o=0; left_right_o=0; bit_shift_o=1; end else begin A_S_op_o=1; left_right_o=1; bit_shift_o=0; end end state_next = norm_sgf_first; end norm_sgf_first: // begin load_4_o = 1; if (norm_iteration_i)begin if(add_overflow_i)begin left_right_o=0; bit_shift_o=1; state_next = round_sgf; end else begin left_right_o=1; bit_shift_o=0; state_next = round_sgf;end end else state_next = add_subt; end add_subt: begin //Reg enables load_5_o = 1; ctrl_c_o = 1; state_next = overflow_add; end overflow_add: begin //Reg enables/Disables load_6_o=1; ctrl_b_load_o=1; if ( add_overflow_i)begin ctrl_b_o=2'b10; end else begin A_S_op_o=1; ctrl_b_o=2'b01; end //state_next = load_exp_oper_over; state_next = extra1_64; end round_sgf: begin load_4_o = 0; if(round_i) begin ctrl_d_o =1; ctrl_a_o = 1; state_next = add_subt_r; end else begin state_next = load_final_result; end end add_subt_r: begin load_5_o = 1; state_next = overflow_add_r; end overflow_add_r: begin ctrl_b_load_o=1; if ( add_overflow_i)begin ctrl_b_o=2'b10; end else begin ctrl_b_o=2'b11; end state_next = extra2_64; end extra2_64: begin load_3_o = 1; load_8_o = 1; if ( add_overflow_i)begin A_S_op_o=0; bit_shift_o=1; end state_next = norm_sgf_r; end norm_sgf_r: begin load_4_o = 1; if ( add_overflow_i)begin left_right_o=0; bit_shift_o=1; end state_next = load_final_result; end load_final_result: begin load_7_o = 1; state_next = ready_flag; end ready_flag: begin ready = 1; if(rst_FSM) begin state_next = start;end end default: begin state_next =start;end endcase end endmodule
`timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_9_b2s_aw_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Write Address Ports input wire [C_ID_WIDTH-1:0] s_awid , input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr , input wire [7:0] s_awlen , input wire [2:0] s_awsize , input wire [1:0] s_awburst , input wire s_awvalid , output wire s_awready , output wire m_awvalid , output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr , input wire m_awready , // Connections to/from axi_protocol_converter_v2_1_9_b2s_b_channel module output wire b_push , output wire [C_ID_WIDTH-1:0] b_awid , output wire [7:0] b_awlen , input wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire next ; wire next_pending ; wire a_push; wire incr_burst; reg [C_ID_WIDTH-1:0] s_awid_r; reg [7:0] s_awlen_r; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // Translate the AXI transaction to the MC transaction(s) axi_protocol_converter_v2_1_9_b2s_cmd_translator # ( .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ) cmd_translator_0 ( .clk ( clk ) , .reset ( reset ) , .s_axaddr ( s_awaddr ) , .s_axlen ( s_awlen ) , .s_axsize ( s_awsize ) , .s_axburst ( s_awburst ) , .s_axhandshake ( s_awvalid & a_push ) , .m_axaddr ( m_awaddr ) , .incr_burst ( incr_burst ) , .next ( next ) , .next_pending ( next_pending ) ); axi_protocol_converter_v2_1_9_b2s_wr_cmd_fsm aw_cmd_fsm_0 ( .clk ( clk ) , .reset ( reset ) , .s_awready ( s_awready ) , .s_awvalid ( s_awvalid ) , .m_awvalid ( m_awvalid ) , .m_awready ( m_awready ) , .next ( next ) , .next_pending ( next_pending ) , .b_push ( b_push ) , .b_full ( b_full ) , .a_push ( a_push ) ); assign b_awid = s_awid_r; assign b_awlen = s_awlen_r; always @(posedge clk) begin s_awid_r <= s_awid ; s_awlen_r <= s_awlen ; end endmodule `default_nettype wire
// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal // in the Software without restriction, including without limitation the rights // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell // copies of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: // The above copyright notice and this permission notice shall be included in // all copies or substantial portions of the Software. // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // // $Revision: 29455 $ // $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif // A synchronization module for resets. Output resets are held for // RSTDELAY+1 cycles, RSTDELAY >= 0. Both assertion and deassertions is // synchronized to the clock. module PositiveReset ( IN_RST, CLK, OUT_RST ); parameter RSTDELAY = 1 ; // Width of reset shift reg input CLK ; input IN_RST ; output OUT_RST ; (* ASYNC_REG = "true" *) reg reset_meta ; reg [RSTDELAY:1] reset_hold ; wire [RSTDELAY+1:0] next_reset = {reset_hold, reset_meta, 1'b0} ; assign OUT_RST = reset_hold[RSTDELAY] ; always @( posedge CLK ) // reset is read synchronous with clock begin if (IN_RST == `BSV_RESET_VALUE) begin reset_meta <= 1; end else begin reset_meta <= 0; end if (reset_meta == 1) begin reset_hold <= `BSV_ASSIGNMENT_DELAY -1 ; end else begin reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:1]; end end // always @ ( posedge CLK ) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off initial begin #0 ; // initialize out of reset forcing the designer to do one reset_hold = 0 ; end // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS endmodule // PositiveReset
// (C) 2001-2016 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License Subscription // Agreement, Intel MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Intel and sold by // Intel or its authorized distributors. Please refer to the applicable // agreement for further details. `timescale 1 ps / 1 ps (* altera_attribute = "-name GLOBAL_SIGNAL OFF" ) module hps_sdram_p0_reset( seq_reset_mem_stable, pll_afi_clk, pll_addr_cmd_clk, pll_dqs_ena_clk, seq_clk, scc_clk, pll_avl_clk, reset_n_scc_clk, reset_n_avl_clk, read_capture_clk, pll_locked, global_reset_n, soft_reset_n, ctl_reset_n, ctl_reset_export_n, reset_n_afi_clk, reset_n_addr_cmd_clk, reset_n_resync_clk, reset_n_seq_clk, reset_n_read_capture_clk ); parameter MEM_READ_DQS_WIDTH = ""; parameter NUM_AFI_RESET = 1; input seq_reset_mem_stable; input pll_afi_clk; input pll_addr_cmd_clk; input pll_dqs_ena_clk; input seq_clk; input scc_clk; input pll_avl_clk; output reset_n_scc_clk; output reset_n_avl_clk; input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk; input pll_locked; input global_reset_n; input soft_reset_n; output ctl_reset_n; output ctl_reset_export_n; output [NUM_AFI_RESET-1:0] reset_n_afi_clk; output reset_n_addr_cmd_clk; output reset_n_resync_clk; output reset_n_seq_clk; output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk; // Apply the synthesis keep attribute on the synchronized reset wires // so that these names can be constrained using QSF settings to keep // the resets on local routing. wire phy_reset_n / synthesis keep = 1 /; wire phy_reset_mem_stable_n / synthesis keep = 1*/; wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture; assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable; assign reset_n_read_capture_clk = reset_n_read_capture; assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n; hps_sdram_p0_reset_sync ureset_afi_clk( .reset_n (phy_reset_n), .clk (pll_afi_clk), .reset_n_sync (reset_n_afi_clk) ); defparam ureset_afi_clk.RESET_SYNC_STAGES = 15; defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET; hps_sdram_p0_reset_sync ureset_ctl_reset_clk( .reset_n (phy_reset_n), .clk (pll_afi_clk), .reset_n_sync ({ctl_reset_n, ctl_reset_export_n}) ); defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15; defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2; hps_sdram_p0_reset_sync ureset_addr_cmd_clk( .reset_n (phy_reset_n), .clk (pll_addr_cmd_clk), .reset_n_sync (reset_n_addr_cmd_clk) ); defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15; defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_resync_clk( .reset_n (phy_reset_n), .clk (pll_dqs_ena_clk), .reset_n_sync (reset_n_resync_clk) ); defparam ureset_resync_clk.RESET_SYNC_STAGES = 15; defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_seq_clk( .reset_n (phy_reset_n), .clk (seq_clk), .reset_n_sync (reset_n_seq_clk) ); defparam ureset_seq_clk.RESET_SYNC_STAGES = 15; defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_scc_clk( .reset_n (phy_reset_n), .clk (scc_clk), .reset_n_sync (reset_n_scc_clk) ); defparam ureset_scc_clk.RESET_SYNC_STAGES = 15; defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_avl_clk( .reset_n (phy_reset_n), .clk (pll_avl_clk), .reset_n_sync (reset_n_avl_clk) ); defparam ureset_avl_clk.RESET_SYNC_STAGES = 2; defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1; generate genvar i; for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1) begin: read_capture_reset hps_sdram_p0_reset_sync #( .RESET_SYNC_STAGES(15), .NUM_RESET_OUTPUT(1) ) ureset_read_capture_clk( .reset_n (phy_reset_mem_stable_n), .clk (read_capture_clk[i]), .reset_n_sync (reset_n_read_capture[i]) ); end endgenerate endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Wilson Snyder. module t (/AUTOARG/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off MULTIDRIVEN /AUTOWIRE/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v wire [15:0] out2; // From test of Test.v // End of automatics // verilator lint_on MULTIDRIVEN Test test ( .en (crc[21:20]), .a1 (crc[19:18]), .a0 (crc[17:16]), .d1 (crc[15:8]), .d0 (crc[7:0]), /AUTOINST/ // Outputs .out (out[31:0]), .out2 (out2[15:0]), // Inputs .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {out2, 16'h0, out}; // Test loop `ifdef TEST_VERBOSE always @ (negedge clk) begin $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); end `endif always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; test.clear(); end else if (cyc<10) begin sum <= 64'h0; test.clear(); end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc68a94a34ec970aa if (sum !== `EXPECTED_SUM) $stop; $write("- All Finished -\n"); $finish; end end endmodule module Test (/AUTOARG/ // Outputs out, out2, // Inputs clk, en, a0, a1, d0, d1 ); input clk; input [1:0] en; input [1:0] a0; input [1:0] a1; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; // verilator lint_off MULTIDRIVEN reg [7:0] mem [4]; // verilator lint_on MULTIDRIVEN task clear(); for (int i=0; i<4; ++i) mem[i] = 0; endtask always @(posedge clk) begin if (en[0]) begin mem[a0] <= d0; out2[7:0] <= d0; end end always @(negedge clk) begin if (en[1]) begin mem[a1] <= d1; out2[15:8] <= d0; end end assign out = {mem[3],mem[2],mem[1],mem[0]}; endmodule
(** * Maps: Total and Partial Maps ) (* Maps (or dictionaries) are ubiquitous data structures, both in software construction generally and in the theory of programming languages in particular; we're going to need them in many places in the coming chapters. They also make a nice case study using ideas we've seen in previous chapters, including building data structures out of higher-order functions (from [Basics] and [Poly]) and the use of reflection to streamline proofs (from [IndProp]). We'll define two flavors of maps: _total_ maps, which include a "default" element to be returned when a key being looked up doesn't exist, and _partial_ maps, which return an [option] to indicate success or failure. The latter is defined in terms of the former, using [None] as the default element. ) ( ###################################################################### ) (* * The Coq Standard Library ) (* One small digression before we start. Unlike the chapters we have seen so far, this one does not [Require Import] the chapter before it (and, transitively, all the earlier chapters). Instead, in this chapter and from now, on we're going to import the definitions and theorems we need directly from Coq's standard library stuff. You should not notice much difference, though, because we've been careful to name our own definitions and theorems the same as their counterparts in the standard library, wherever they overlap. ) Require Import Coq.Arith.Arith. Require Import Coq.Bool.Bool. Require Import Coq.Logic.FunctionalExtensionality. (* Documentation for the standard library can be found at http://coq.inria.fr/library/. The [SearchAbout] command is a good way to look for theorems involving objects of specific types. ) ( ###################################################################### ) (* * Identifiers ) (* First, we need a type for the keys that we use to index into our maps. For this purpose, we again use the type [id] from the [Lists] chapter. To make this chapter self contained, we repeat its definition here, together with the equality comparison function for [id]s and its fundamental property. ) Inductive id : Type := \| Id : nat -> id. Definition beq_id id1 id2 := match id1,id2 with \| Id n1, Id n2 => beq_nat n1 n2 end. Theorem beq_id_refl : forall id, true = beq_id id id. Proof. intros [n]. simpl. rewrite <- beq_nat_refl. reflexivity. Qed. (* The following useful property of [beq_id] follows from an analogous lemma about numbers: ) Theorem beq_id_true_iff : forall id1 id2 : id, beq_id id1 id2 = true <-> id1 = id2. Proof. intros [n1] [n2]. unfold beq_id. rewrite beq_nat_true_iff. split. - ( -> ) intros H. rewrite H. reflexivity. - ( <- ) intros H. inversion H. reflexivity. Qed. (* Similarly: ) Theorem beq_id_false_iff : forall x y : id, beq_id x y = false <-> x <> y. Proof. intros x y. rewrite <- beq_id_true_iff. rewrite not_true_iff_false. reflexivity. Qed. (* This useful variant follows just by rewriting: ) Theorem false_beq_id : forall x y : id, x <> y -> beq_id x y = false. Proof. intros x y. rewrite beq_id_false_iff. intros H. apply H. Qed. ( ###################################################################### ) (* * Total Maps ) (* Our main job in this chapter will be to build a definition of partial maps that is similar in behavior to the one we saw in the [Lists] chapter, plus accompanying lemmas about their behavior. This time around, though, we're going to use _functions_, rather than lists of key-value pairs, to build maps. The advantage of this representation is that it offers a more _extensional_ view of maps, where two maps that respond to queries in the same way will be represented as literally the same thing (the same function), rather than just "equivalent" data structures. This, in turn, simplifies proofs that use maps. We build partial maps in two steps. First, we define a type of _total maps_ that return a default value when we look up a key that is not present in the map. ) Definition total_map (A:Type) := id -> A. (* Intuitively, a total map over an element type [A] _is_ just a function that can be used to look up [id]s, yielding [A]s. The function [t_empty] yields an empty total map, given a default element; this map always returns the default element when applied to any id. ) Definition t_empty {A:Type} (v : A) : total_map A := (fun _ => v). (* More interesting is the [update] function, which (as before) takes a map [m], a key [x], and a value [v] and returns a new map that takes [x] to [v] and takes every other key to whatever [m] does. ) Definition t_update {A:Type} (m : total_map A) (x : id) (v : A) := fun x' => if beq_id x x' then v else m x'. (* This definition is a nice example of higher-order programming. The [t_update] function takes a _function_ [m] and yields a new function [fun x' => ...] that behaves like the desired map. For example, we can build a map taking [id]s to [bool]s, where [Id 3] is mapped to [true] and every other key is mapped to [false], like this: ) Definition examplemap := t_update (t_update (t_empty false) (Id 1) false) (Id 3) true. (* This completes the definition of total maps. Note that we don't need to define a [find] operation because it is just function application! ) Example update_example1 : examplemap (Id 0) = false. Proof. reflexivity. Qed. Example update_example2 : examplemap (Id 1) = false. Proof. reflexivity. Qed. Example update_example3 : examplemap (Id 2) = false. Proof. reflexivity. Qed. Example update_example4 : examplemap (Id 3) = true. Proof. reflexivity. Qed. (* To use maps in later chapters, we'll need several fundamental facts about how they behave. Even if you don't work the following exercises, make sure you thoroughly understand the statements of the lemmas! (Some of the proofs require the functional extensionality axiom discussed in the [Logic] chapter, which is also included in the standard library.) ) (* **** Exercise: 2 stars, optional (t_update_eq) ) (* First, if we update a map [m] at a key [x] with a new value [v] and then look up [x] in the map resulting from the [update], we get back [v]: ) Lemma t_update_eq : forall A (m: total_map A) x v, (t_update m x v) x = v. Proof. intros. unfold t_update. rewrite <- beq_id_refl. reflexivity. Qed. (* [] ) (* **** Exercise: 2 stars, optional (t_update_neq) ) (* On the other hand, if we update a map [m] at a key [x1] and then look up a _different_ key [x2] in the resulting map, we get the same result that [m] would have given: ) Theorem t_update_neq : forall (X:Type) v x1 x2 (m : total_map X), x1 <> x2 -> (t_update m x1 v) x2 = m x2. Proof. intros. unfold t_update. apply false_beq_id in H. rewrite H. reflexivity. Qed. (* [] ) (* **** Exercise: 2 stars, optional (t_update_shadow) ) (* If we update a map [m] at a key [x] with a value [v1] and then update again with the same key [x] and another value [v2], the resulting map behaves the same (gives the same result when applied to any key) as the simpler map obtained by performing just the second [update] on [m]: ) Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x, t_update (t_update m x v1) x v2 = t_update m x v2. Proof. intros. unfold t_update. apply functional_extensionality. intros. destruct (beq_id x x0). - reflexivity. - reflexivity. Qed. (* [] ) (* For the final two lemmas about total maps, it's convenient to use the reflection idioms introduced in chapter [IndProp]. We begin by proving a fundamental _reflection lemma_ relating the equality proposition on [id]s with the boolean function [beq_id]. ) (* **** Exercise: 2 stars (beq_idP) ) (* Use the proof of [beq_natP] in chapter [IndProp] as a template to prove the following: ) Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y). Proof. intros x y. apply iff_reflect. rewrite beq_id_true_iff. reflexivity. Qed. (* [] ) (* Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP x1 x2)] to simultaneously perform case analysis on the result of [beq_id x1 x2] and generate hypotheses about the equality (in the sense of [=]) of [x1] and [x2]. ) (* **** Exercise: 2 stars (t_update_same) ) (* Using the example in chapter [IndProp] as a template, use [beq_idP] to prove the following theorem, which states that if we update a map to assign key [x] the same value as it already has in [m], then the result is equal to [m]: ) Theorem t_update_same : forall X x (m : total_map X), t_update m x (m x) = m. Proof. intros. unfold t_update. apply functional_extensionality. intros. destruct (beq_idP x x0) as [H \| H']. - rewrite H. reflexivity. - reflexivity. Qed. (* [] ) (* **** Exercise: 3 stars, recommended (t_update_permute) ) (* Use [beq_idP] to prove one final property of the [update] function: If we update a map [m] at two distinct keys, it doesn't matter in which order we do the updates. ) Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2 (m : total_map X), x2 <> x1 -> (t_update (t_update m x2 v2) x1 v1) = (t_update (t_update m x1 v1) x2 v2). Proof. intros. unfold t_update. apply functional_extensionality. intros. destruct (beq_idP x1 x). - destruct (beq_idP x2 x). destruct H. rewrite e. rewrite e0. reflexivity. * reflexivity. - destruct (beq_idP x2 x). * reflexivity. * reflexivity. Qed. (** [] ) ( ###################################################################### ) (* * Partial maps ) (* Finally, we define _partial maps_ on top of total maps. A partial map with elements of type [A] is simply a total map with elements of type [option A] and default element [None]. ) Definition partial_map (A:Type) := total_map (option A). Definition empty {A:Type} : partial_map A := t_empty None. Definition update {A:Type} (m : partial_map A) (x : id) (v : A) := t_update m x (Some v). (* We can now lift all of the basic lemmas about total maps to partial maps. ) Lemma update_eq : forall A (m: partial_map A) x v, (update m x v) x = Some v. Proof. intros. unfold update. rewrite t_update_eq. reflexivity. Qed. Theorem update_neq : forall (X:Type) v x1 x2 (m : partial_map X), x2 <> x1 -> (update m x2 v) x1 = m x1. Proof. intros X v x1 x2 m H. unfold update. rewrite t_update_neq. reflexivity. apply H. Qed. Lemma update_shadow : forall A (m: partial_map A) v1 v2 x, update (update m x v1) x v2 = update m x v2. Proof. intros A m v1 v2 x1. unfold update. rewrite t_update_shadow. reflexivity. Qed. Theorem update_same : forall X v x (m : partial_map X), m x = Some v -> update m x v = m. Proof. intros X v x m H. unfold update. rewrite <- H. apply t_update_same. Qed. Theorem update_permute : forall (X:Type) v1 v2 x1 x2 (m : partial_map X), x2 <> x1 -> (update (update m x2 v2) x1 v1) = (update (update m x1 v1) x2 v2). Proof. intros X v1 v2 x1 x2 m. unfold update. apply t_update_permute. Qed. (* $Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $ *)
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_0_oci_test_bench ( // inputs: dct_buffer, dct_count, test_ending, test_has_ended ) ; input [ 29: 0] dct_buffer; input [ 3: 0] dct_count; input test_ending; input test_has_ended; endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V `define SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V /* * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none ( blackbox *) module sky130_fd_sc_hdll__dlygate4sd3 ( //# {{data\|Data Signals}} input A , output X , //# {{power\|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V
// megafunction wizard: %ALTGX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: alt_c3gxb // ============================================================ // File Name: altera_tse_altgx_civgx_gige.v // Megafunction Name(s): // alt_c3gxb // // Simulation Library Files(s): // altera_mf;cycloneiv_hssi // ============================================================ // ********************************************************** // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.1 Build 345 02/24/2010 SP 2 SJ Full Version // ********************************************************** //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk gxb_powerdown pll_inclk reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX" //VERSION_BEGIN 9.1SP2 cbx_alt_c3gxb 2010:02:24:21:06:43:SJ cbx_altpll 2010:02:24:21:06:43:SJ cbx_cycloneii 2010:02:24:21:06:43:SJ cbx_mgl 2010:02:24:21:13:40:SJ cbx_stingray 2010:02:24:21:06:43:SJ cbx_stratixii 2010:02:24:21:06:43:SJ cbx_util_mgl 2010:02:24:21:06:43:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 //synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module altera_tse_altgx_civgx_gige_alt_c3gxb_vs07 ( cal_blk_clk, gxb_powerdown, pll_inclk, reconfig_clk, reconfig_fromgxb, reconfig_togxb, rx_analogreset, rx_ctrldetect, rx_datain, rx_dataout, rx_digitalreset, rx_disperr, rx_errdetect, rx_patterndetect, rx_rlv, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_runningdisp, rx_syncstatus, tx_clkout, tx_ctrlenable, tx_datain, tx_dataout, tx_digitalreset) ; input cal_blk_clk; input [0:0] gxb_powerdown; input pll_inclk; input reconfig_clk; output [4:0] reconfig_fromgxb; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; output [0:0] rx_ctrldetect; input [0:0] rx_datain; output [7:0] rx_dataout; input [0:0] rx_digitalreset; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_patterndetect; output [0:0] rx_rlv; output [0:0] rx_rmfifodatadeleted; output [0:0] rx_rmfifodatainserted; output [0:0] rx_runningdisp; output [0:0] rx_syncstatus; output [0:0] tx_clkout; input [0:0] tx_ctrlenable; input [7:0] tx_datain; output [0:0] tx_dataout; input [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 cal_blk_clk; tri0 [0:0] gxb_powerdown; tri0 reconfig_clk; tri0 [0:0] rx_analogreset; tri0 [0:0] rx_digitalreset; tri0 [0:0] tx_ctrlenable; tri0 [7:0] tx_datain; tri0 [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif parameter starting_channel_number = 0; wire [5:0] wire_pll0_clk; wire wire_pll0_fref; wire wire_pll0_icdrclk; wire wire_cal_blk0_nonusertocmu; wire wire_cent_unit0_dprioout; wire wire_cent_unit0_quadresetout; wire [3:0] wire_cent_unit0_rxanalogresetout; wire [3:0] wire_cent_unit0_rxcrupowerdown; wire [3:0] wire_cent_unit0_rxdigitalresetout; wire [3:0] wire_cent_unit0_rxibpowerdown; wire [3:0] wire_cent_unit0_txanalogresetout; wire [3:0] wire_cent_unit0_txdetectrxpowerdown; wire [3:0] wire_cent_unit0_txdigitalresetout; wire [3:0] wire_cent_unit0_txdividerpowerdown; wire [3:0] wire_cent_unit0_txobpowerdown; wire wire_receive_pcs0_cdrctrllocktorefclkout; wire [1:0] wire_receive_pcs0_ctrldetect; wire [19:0] wire_receive_pcs0_dataout; wire [1:0] wire_receive_pcs0_disperr; wire [1:0] wire_receive_pcs0_errdetect; wire [1:0] wire_receive_pcs0_patterndetect; wire wire_receive_pcs0_rlv; wire [1:0] wire_receive_pcs0_rmfifodatadeleted; wire [1:0] wire_receive_pcs0_rmfifodatainserted; wire [1:0] wire_receive_pcs0_runningdisp; wire wire_receive_pcs0_signaldetect; wire [1:0] wire_receive_pcs0_syncstatus; wire [7:0] wire_receive_pma0_analogtestbus; wire wire_receive_pma0_clockout; wire wire_receive_pma0_locktorefout; wire [9:0] wire_receive_pma0_recoverdataout; wire wire_receive_pma0_signaldetect; wire wire_transmit_pcs0_clkout; wire [9:0] wire_transmit_pcs0_dataout; wire wire_transmit_pcs0_forceelecidleout; wire wire_transmit_pcs0_txdetectrx; wire wire_transmit_pma0_clockout; wire wire_transmit_pma0_dataout; wire wire_transmit_pma0_seriallpbkout; wire cal_blk_powerdown; wire [0:0] cent_unit_quadresetout; wire [3:0] cent_unit_rxcrupowerdn; wire [3:0] cent_unit_rxibpowerdn; wire [3:0] cent_unit_txdetectrxpowerdn; wire [3:0] cent_unit_txdividerpowerdown; wire [3:0] cent_unit_txobpowerdn; wire [3:0] fixedclk_to_cmu; wire [0:0] nonusertocmu_out; wire [0:0] pll_powerdown; wire [0:0] reconfig_togxb_busy; wire [0:0] reconfig_togxb_disable; wire [0:0] reconfig_togxb_in; wire [0:0] reconfig_togxb_load; wire [3:0] rx_analogreset_in; wire [3:0] rx_analogreset_out; wire [0:0] rx_coreclk_in; wire [0:0] rx_deserclock_in; wire [3:0] rx_digitalreset_in; wire [3:0] rx_digitalreset_out; wire [0:0] rx_enapatternalign; wire [0:0] rx_locktodata; wire [0:0] rx_locktorefclk; wire [0:0] rx_locktorefclk_wire; wire [7:0] rx_out_wire; wire [0:0] rx_phfifordenable; wire [0:0] rx_phfiforeset; wire [0:0] rx_phfifowrdisable; wire [0:0] rx_pll_pfdrefclkout_wire; wire [4:0] rx_pma_analogtestbus; wire [0:0] rx_pma_clockout; wire [9:0] rx_pma_recoverdataout_wire; wire [0:0] rx_powerdown; wire [3:0] rx_powerdown_in; wire [0:0] rx_prbscidenable; wire [0:0] rx_rmfiforeset; wire [0:0] rx_signaldetect_wire; wire [3:0] tx_analogreset_out; wire [0:0] tx_clkout_int_wire; wire [0:0] tx_core_clkout_wire; wire [0:0] tx_coreclk_in; wire [7:0] tx_datain_wire; wire [9:0] tx_dataout_pcs_to_pma; wire [3:0] tx_digitalreset_in; wire [3:0] tx_digitalreset_out; wire [0:0] tx_forcedisp_wire; wire [0:0] tx_invpolarity; wire [0:0] tx_localrefclk; wire [0:0] tx_phfiforeset; wire [0:0] tx_pma_fastrefclk0in; wire [0:0] tx_pma_refclk0in; wire [0:0] tx_pma_refclk0inpulse; wire [0:0] tx_serialloopbackout; wire [0:0] txdataout; wire [0:0] txdetectrxout; altpll pll0 ( .activeclock(), .areset(pll_powerdown[0]), .clk(wire_pll0_clk), .clkbad(), .clkloss(), .enable0(), .enable1(), .extclk(), .fbout(), .fref(wire_pll0_fref), .icdrclk(wire_pll0_icdrclk), .inclk({{1{1'b0}}, pll_inclk}), .locked(), .phasedone(), .scandataout(), .scandone(), .sclkout0(), .sclkout1(), .vcooverrange(), .vcounderrange() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clkena({6{1'b1}}), .clkswitch(1'b0), .configupdate(1'b0), .extclkena({4{1'b1}}), .fbin(1'b1), .pfdena(1'b1), .phasecounterselect({4{1'b1}}), .phasestep(1'b1), .phaseupdown(1'b1), .pllena(1'b1), .scanaclr(1'b0), .scanclk(1'b0), .scanclkena(1'b1), .scandata(1'b0), .scanread(1'b0), .scanwrite(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam pll0.bandwidth_type = "HIGH", pll0.clk0_divide_by = 1, pll0.clk0_multiply_by = 5, pll0.clk1_divide_by = 5, pll0.clk1_multiply_by = 5, pll0.clk2_divide_by = 5, pll0.clk2_duty_cycle = 20, pll0.clk2_multiply_by = 5, pll0.dpa_divide_by = 1, pll0.dpa_multiply_by = 5, pll0.inclk0_input_frequency = 8000, pll0.operation_mode = "no_compensation", pll0.intended_device_family = "Cyclone IV GX", pll0.lpm_type = "altpll"; cycloneiv_hssi_calibration_block cal_blk0 ( .calibrationstatus(), .clk(cal_blk_clk), .nonusertocmu(wire_cal_blk0_nonusertocmu), .powerdn(cal_blk_powerdown) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .testctrl(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); cycloneiv_hssi_cmu cent_unit0 ( .alignstatus(), .coreclkout(), .digitaltestout(), .dpclk(reconfig_clk), .dpriodisable(reconfig_togxb_disable), .dpriodisableout(), .dprioin(reconfig_togxb_in), .dprioload(reconfig_togxb_load), .dpriooe(), .dprioout(wire_cent_unit0_dprioout), .enabledeskew(), .fiforesetrd(), .fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}), .nonuserfromcal(nonusertocmu_out[0]), .quadreset(gxb_powerdown[0]), .quadresetout(wire_cent_unit0_quadresetout), .refclkout(), .rxanalogreset({rx_analogreset_in[3:0]}), .rxanalogresetout(wire_cent_unit0_rxanalogresetout), .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown), .rxctrlout(), .rxdataout(), .rxdigitalreset({rx_digitalreset_in[3:0]}), .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout), .rxibpowerdown(wire_cent_unit0_rxibpowerdown), .rxphfifox4byteselout(), .rxphfifox4rdenableout(), .rxphfifox4wrclkout(), .rxphfifox4wrenableout(), .rxpowerdown({rx_powerdown_in[3:0]}), .testout(), .txanalogresetout(wire_cent_unit0_txanalogresetout), .txctrlout(), .txdataout(), .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown), .txdigitalreset({tx_digitalreset_in[3:0]}), .txdigitalresetout(wire_cent_unit0_txdigitalresetout), .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown), .txobpowerdown(wire_cent_unit0_txobpowerdown), .txphfifox4byteselout(), .txphfifox4rdclkout(), .txphfifox4rdenableout(), .txphfifox4wrenableout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .adet({4{1'b0}}), .pmacramtest(1'b0), .rdalign({4{1'b0}}), .rdenablesync(1'b1), .recovclk(1'b0), .refclkdig(1'b0), .rxcoreclk(1'b0), .rxctrl({4{1'b0}}), .rxdatain({32{1'b0}}), .rxdatavalid({4{1'b0}}), .rxphfifordenable(1'b1), .rxphfiforeset(1'b0), .rxphfifowrdisable(1'b0), .rxrunningdisp({4{1'b0}}), .scanclk(1'b0), .scanmode(1'b0), .scanshift(1'b0), .syncstatus({4{1'b0}}), .testin({2000{1'b0}}), .txclk(1'b0), .txcoreclk(1'b0), .txctrl({4{1'b0}}), .txdatain({32{1'b0}}), .txphfiforddisable(1'b0), .txphfiforeset(1'b0), .txphfifowrenable(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8, cent_unit0.auto_spd_phystatus_notify_count = 0, cent_unit0.in_xaui_mode = "false", cent_unit0.rx0_channel_bonding = "none", cent_unit0.rx0_clk1_mux_select = "recovered clock", cent_unit0.rx0_clk2_mux_select = "local reference clock", cent_unit0.rx0_ph_fifo_reg_mode = "false", cent_unit0.rx0_rd_clk_mux_select = "core clock", cent_unit0.rx0_recovered_clk_mux_select = "recovered clock", cent_unit0.rx0_reset_clock_output_during_digital_reset = "false", cent_unit0.rx0_use_double_data_mode = "false", cent_unit0.tx0_channel_bonding = "none", cent_unit0.tx0_rd_clk_mux_select = "central", cent_unit0.tx0_reset_clock_output_during_digital_reset = "false", cent_unit0.tx0_use_double_data_mode = "false", cent_unit0.tx0_wr_clk_mux_select = "core_clk", cent_unit0.use_coreclk_out_post_divider = "false", cent_unit0.use_deskew_fifo = "false", cent_unit0.lpm_type = "cycloneiv_hssi_cmu"; cycloneiv_hssi_rx_pcs receive_pcs0 ( .a1a2size(1'b0), .a1a2sizeout(), .a1detect(), .a2detect(), .adetectdeskew(), .alignstatussyncout(), .bistdone(), .bisterr(), .bitslipboundaryselectout(), .byteorderalignstatus(), .cdrctrlearlyeios(), .cdrctrllocktorefcl((reconfig_togxb_busy \| rx_locktorefclk[0])), .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout), .clkout(), .coreclk(rx_coreclk_in[0]), .coreclkout(), .ctrldetect(wire_receive_pcs0_ctrldetect), .datain(rx_pma_recoverdataout_wire[9:0]), .dataout(wire_receive_pcs0_dataout), .dataoutfull(), .digitalreset(rx_digitalreset_out[0]), .disperr(wire_receive_pcs0_disperr), .enabyteord(1'b0), .enapatternalign(rx_enapatternalign[0]), .errdetect(wire_receive_pcs0_errdetect), .fifordout(), .hipdataout(), .hipdatavalid(), .hipelecidle(), .hipphydonestatus(), .hipstatus(), .invpol(1'b0), .k1detect(), .k2detect(), .localrefclk(tx_localrefclk[0]), .parallelfdbk({20{1'b0}}), .patterndetect(wire_receive_pcs0_patterndetect), .phfifooverflow(), .phfifordenable(rx_phfifordenable[0]), .phfifordenableout(), .phfiforeset(rx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrdisable(rx_phfifowrdisable[0]), .phfifowrdisableout(), .pipebufferstat(), .pipedatavalid(), .pipeelecidle(), .pipephydonestatus(), .pipepowerdown({2{1'b0}}), .pipepowerstate({4{1'b0}}), .pipestatus(), .prbscidenable(rx_prbscidenable[0]), .quadreset(cent_unit_quadresetout[0]), .rdalign(), .recoveredclk(rx_pma_clockout[0]), .revbitorderwa(1'b0), .revparallelfdbkdata(), .rlv(wire_receive_pcs0_rlv), .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted), .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted), .rmfifoempty(), .rmfifofull(), .rmfifordena(1'b0), .rmfiforeset(rx_rmfiforeset[0]), .rmfifowrena(1'b0), .runningdisp(wire_receive_pcs0_runningdisp), .rxdetectvalid(1'b0), .rxfound({2{1'b0}}), .signaldetect(wire_receive_pcs0_signaldetect), .signaldetected(rx_signaldetect_wire[0]), .syncstatus(wire_receive_pcs0_syncstatus), .syncstatusdeskew(), .xauidelcondmetout(), .xauififoovrout(), .xauiinsertincompleteout(), .xauilatencycompout(), .xgmctrldet(), .xgmdataout(), .xgmdatavalid(), .xgmrunningdisp() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .alignstatus(1'b0), .alignstatussync(1'b0), .bitslip(1'b0), .elecidleinfersel({3{1'b0}}), .enabledeskew(1'b0), .fifordin(1'b0), .fiforesetrd(1'b0), .grayelecidleinferselfromtx({3{1'b0}}), .hip8b10binvpolarity(1'b0), .hipelecidleinfersel({3{1'b0}}), .hippowerdown({2{1'b0}}), .masterclk(1'b0), .phfifox4bytesel(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrclk(1'b0), .phfifox4wrenable(1'b0), .pipe8b10binvpolarity(1'b0), .pipeenrevparallellpbkfromtx(1'b0), .pmatestbusin({8{1'b0}}), .powerdn({2{1'b0}}), .refclk(1'b0), .wareset(1'b0), .xauidelcondmet(1'b0), .xauififoovr(1'b0), .xauiinsertincomplete(1'b0), .xauilatencycomp(1'b0), .xgmctrlin(1'b0), .xgmdatain({8{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pcs0.align_pattern = "0101111100", receive_pcs0.align_pattern_length = 10, receive_pcs0.allow_align_polarity_inversion = "false", receive_pcs0.allow_pipe_polarity_inversion = "false", receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8, receive_pcs0.auto_spd_phystatus_notify_count = 0, receive_pcs0.bit_slip_enable = "false", receive_pcs0.byte_order_mode = "none", receive_pcs0.byte_order_pad_pattern = "0", receive_pcs0.byte_order_pattern = "0", receive_pcs0.byte_order_pld_ctrl_enable = "false", receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000, receive_pcs0.cdrctrl_enable = "false", receive_pcs0.cdrctrl_mask_cycle = 800, receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63, receive_pcs0.cdrctrl_rxvalid_mask = "false", receive_pcs0.channel_bonding = "none", receive_pcs0.channel_number = ((starting_channel_number + 0) % 4), receive_pcs0.channel_width = 8, receive_pcs0.clk1_mux_select = "recovered clock", receive_pcs0.clk2_mux_select = "local reference clock", receive_pcs0.datapath_low_latency_mode = "false", receive_pcs0.datapath_protocol = "basic", receive_pcs0.dec_8b_10b_compatibility_mode = "true", receive_pcs0.dec_8b_10b_mode = "normal", receive_pcs0.deskew_pattern = "0", receive_pcs0.disable_auto_idle_insertion = "true", receive_pcs0.disable_running_disp_in_word_align = "false", receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false", receive_pcs0.elec_idle_infer_enable = "false", receive_pcs0.elec_idle_num_com_detect = 3, receive_pcs0.enable_bit_reversal = "false", receive_pcs0.enable_self_test_mode = "false", receive_pcs0.force_signal_detect_dig = "true", receive_pcs0.hip_enable = "false", receive_pcs0.infiniband_invalid_code = 0, receive_pcs0.insert_pad_on_underflow = "false", receive_pcs0.num_align_code_groups_in_ordered_set = 1, receive_pcs0.num_align_cons_good_data = 4, receive_pcs0.num_align_cons_pat = 3, receive_pcs0.num_align_loss_sync_error = 4, receive_pcs0.ph_fifo_low_latency_enable = "true", receive_pcs0.ph_fifo_reg_mode = "false", receive_pcs0.protocol_hint = "gige", receive_pcs0.rate_match_back_to_back = "true", receive_pcs0.rate_match_delete_threshold = 13, receive_pcs0.rate_match_empty_threshold = 5, receive_pcs0.rate_match_fifo_mode = "true", receive_pcs0.rate_match_full_threshold = 20, receive_pcs0.rate_match_insert_threshold = 11, receive_pcs0.rate_match_ordered_set_based = "true", receive_pcs0.rate_match_pattern1 = "10100010010101111100", receive_pcs0.rate_match_pattern2 = "10101011011010000011", receive_pcs0.rate_match_pattern_size = 20, receive_pcs0.rate_match_reset_enable = "false", receive_pcs0.rate_match_skip_set_based = "false", receive_pcs0.rate_match_start_threshold = 7, receive_pcs0.rd_clk_mux_select = "core clock", receive_pcs0.recovered_clk_mux_select = "recovered clock", receive_pcs0.run_length = 5, receive_pcs0.run_length_enable = "true", receive_pcs0.rx_detect_bypass = "false", receive_pcs0.rx_phfifo_wait_cnt = 15, receive_pcs0.rxstatus_error_report_mode = 0, receive_pcs0.self_test_mode = "incremental", receive_pcs0.use_alignment_state_machine = "true", receive_pcs0.use_deskew_fifo = "false", receive_pcs0.use_double_data_mode = "false", receive_pcs0.use_parallel_loopback = "false", receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs"; cycloneiv_hssi_rx_pma receive_pma0 ( .analogtestbus(wire_receive_pma0_analogtestbus), .clockout(wire_receive_pma0_clockout), .crupowerdn(cent_unit_rxcrupowerdn[0]), .datain(rx_datain[0]), .datastrobeout(), .deserclock(rx_deserclock_in[0]), .diagnosticlpbkout(), .freqlocked(), .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])), .locktoref(rx_locktorefclk_wire[0]), .locktorefout(wire_receive_pma0_locktorefout), .powerdn(cent_unit_rxibpowerdn[0]), .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]), .recoverdataout(wire_receive_pma0_recoverdataout), .reverselpbkout(), .rxpmareset(rx_analogreset_out[0]), .seriallpbkin(tx_serialloopbackout[0]), .signaldetect(wire_receive_pma0_signaldetect), .testbussel(4'b0110) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .dpashift(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pma0.allow_serial_loopback = "true", receive_pma0.channel_number = ((starting_channel_number + 0) % 4), receive_pma0.common_mode = "0.82V", receive_pma0.deserialization_factor = 10, receive_pma0.effective_data_rate = "1250 Mbps", receive_pma0.enable_ltd = "false", receive_pma0.enable_ltr = "false", receive_pma0.eq_dc_gain = 0, receive_pma0.eq_setting = 1, receive_pma0.force_signal_detect = "true", receive_pma0.offset_cancellation = 1, receive_pma0.ppm_gen1_2_xcnt_en = 1, receive_pma0.ppm_post_eidle = 0, receive_pma0.ppmselect = 32, receive_pma0.protocol_hint = "gige", receive_pma0.signal_detect_hysteresis = 2, receive_pma0.signal_detect_hysteresis_valid_threshold = 1, receive_pma0.signal_detect_loss_threshold = 1, receive_pma0.termination = "OCT 100 Ohms", receive_pma0.use_external_termination = "false", receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma"; cycloneiv_hssi_tx_pcs transmit_pcs0 ( .clkout(wire_transmit_pcs0_clkout), .coreclk(tx_coreclk_in[0]), .coreclkout(), .ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}), .datain({{12{1'b0}}, tx_datain_wire[7:0]}), .datainfull({22{1'b0}}), .dataout(wire_transmit_pcs0_dataout), .detectrxloop(1'b0), .digitalreset(tx_digitalreset_out[0]), .enrevparallellpbk(1'b0), .forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}), .forceelecidleout(wire_transmit_pcs0_forceelecidleout), .grayelecidleinferselout(), .hiptxclkout(), .invpol(tx_invpolarity[0]), .localrefclk(tx_localrefclk[0]), .parallelfdbkout(), .phfifooverflow(), .phfiforddisable(1'b0), .phfiforddisableout(), .phfiforeset(tx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrenable(1'b1), .phfifowrenableout(), .pipeenrevparallellpbkout(), .pipepowerdownout(), .pipepowerstateout(), .powerdn({2{1'b0}}), .quadreset(cent_unit_quadresetout[0]), .rdenablesync(), .revparallelfdbk({20{1'b0}}), .txdetectrx(wire_transmit_pcs0_txdetectrx), .xgmctrlenable(), .xgmdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .bitslipboundaryselect({5{1'b0}}), .dispval({2{1'b0}}), .elecidleinfersel({3{1'b0}}), .forceelecidle(1'b0), .hipdatain({10{1'b0}}), .hipdetectrxloop(1'b0), .hipelecidleinfersel({3{1'b0}}), .hipforceelecidle(1'b0), .hippowerdn({2{1'b0}}), .phfifox4bytesel(1'b0), .phfifox4rdclk(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrenable(1'b0), .pipetxswing(1'b0), .prbscidenable(1'b0), .refclk(1'b0), .xgmctrl(1'b0), .xgmdatain({8{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pcs0.allow_polarity_inversion = "false", transmit_pcs0.bitslip_enable = "false", transmit_pcs0.channel_bonding = "none", transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4), transmit_pcs0.channel_width = 8, transmit_pcs0.datapath_low_latency_mode = "false", transmit_pcs0.datapath_protocol = "basic", transmit_pcs0.disable_ph_low_latency_mode = "false", transmit_pcs0.disparity_mode = "none", transmit_pcs0.elec_idle_delay = 6, transmit_pcs0.enable_bit_reversal = "false", transmit_pcs0.enable_idle_selection = "true", transmit_pcs0.enable_reverse_parallel_loopback = "false", transmit_pcs0.enable_self_test_mode = "false", transmit_pcs0.enc_8b_10b_compatibility_mode = "true", transmit_pcs0.enc_8b_10b_mode = "normal", transmit_pcs0.hip_enable = "false", transmit_pcs0.ph_fifo_reg_mode = "false", transmit_pcs0.prbs_cid_pattern = "false", transmit_pcs0.protocol_hint = "gige", transmit_pcs0.refclk_select = "local", transmit_pcs0.self_test_mode = "incremental", transmit_pcs0.use_double_data_mode = "false", transmit_pcs0.wr_clk_mux_select = "core_clk", transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs"; cycloneiv_hssi_tx_pma transmit_pma0 ( .cgbpowerdn(cent_unit_txdividerpowerdown[0]), .clockout(wire_transmit_pma0_clockout), .datain({tx_dataout_pcs_to_pma[9:0]}), .dataout(wire_transmit_pma0_dataout), .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]), .fastrefclk0in(tx_pma_fastrefclk0in[0]), .forceelecidle(1'b0), .powerdn(cent_unit_txobpowerdn[0]), .refclk0in(tx_pma_refclk0in[0]), .refclk0inpulse(tx_pma_refclk0inpulse[0]), .reverselpbkin(1'b0), .rxdetecten(txdetectrxout[0]), .rxdetectvalidout(), .rxfoundout(), .seriallpbkout(wire_transmit_pma0_seriallpbkout), .txpmareset(tx_analogreset_out[0]) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .diagnosticlpbkin(1'b0), .rxdetectclk(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pma0.channel_number = ((starting_channel_number + 0) % 4), transmit_pma0.common_mode = "0.65V", transmit_pma0.effective_data_rate = "1250 Mbps", transmit_pma0.enable_reverse_serial_loopback = "false", transmit_pma0.preemp_tap_1 = 1, transmit_pma0.protocol_hint = "gige", transmit_pma0.rx_detect = 0, transmit_pma0.serialization_factor = 10, transmit_pma0.slew_rate = "medium", transmit_pma0.termination = "OCT 100 Ohms", transmit_pma0.use_external_termination = "false", transmit_pma0.use_rx_detect = "false", transmit_pma0.vod_selection = 1, transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma"; assign cal_blk_powerdown = 1'b0, cent_unit_quadresetout = {wire_cent_unit0_quadresetout}, cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]}, cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]}, cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]}, cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]}, cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]}, fixedclk_to_cmu = {4{reconfig_clk}}, nonusertocmu_out = {wire_cal_blk0_nonusertocmu}, pll_powerdown = 1'b0, reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout}, reconfig_togxb_busy = reconfig_togxb[3], reconfig_togxb_disable = reconfig_togxb[1], reconfig_togxb_in = reconfig_togxb[0], reconfig_togxb_load = reconfig_togxb[2], rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])}, rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]}, rx_coreclk_in = {tx_core_clkout_wire[0]}, rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]}, rx_dataout = {rx_out_wire[7:0]}, rx_deserclock_in = {wire_pll0_icdrclk}, rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]}, rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]}, rx_disperr = {wire_receive_pcs0_disperr[0]}, rx_enapatternalign = 1'b0, rx_errdetect = {wire_receive_pcs0_errdetect[0]}, rx_locktodata = 1'b0, rx_locktorefclk = 1'b0, rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout}, rx_out_wire = {wire_receive_pcs0_dataout[7:0]}, rx_patterndetect = {wire_receive_pcs0_patterndetect[0]}, rx_phfifordenable = 1'b1, rx_phfiforeset = 1'b0, rx_phfifowrdisable = 1'b0, rx_pll_pfdrefclkout_wire = {wire_pll0_fref}, rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]}, rx_pma_clockout = {wire_receive_pma0_clockout}, rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]}, rx_powerdown = 1'b0, rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]}, rx_prbscidenable = 1'b0, rx_rlv = {wire_receive_pcs0_rlv}, rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]}, rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]}, rx_rmfiforeset = 1'b0, rx_runningdisp = {wire_receive_pcs0_runningdisp[0]}, rx_signaldetect_wire = {wire_receive_pma0_signaldetect}, rx_syncstatus = {wire_receive_pcs0_syncstatus[0]}, tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]}, tx_clkout = {tx_core_clkout_wire[0]}, tx_clkout_int_wire = {wire_transmit_pcs0_clkout}, tx_core_clkout_wire = {tx_clkout_int_wire[0]}, tx_coreclk_in = {tx_clkout_int_wire[0]}, tx_datain_wire = {tx_datain[7:0]}, tx_dataout = {txdataout[0]}, tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]}, tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]}, tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]}, tx_forcedisp_wire = {1'b0}, tx_invpolarity = 1'b0, tx_localrefclk = {wire_transmit_pma0_clockout}, tx_phfiforeset = 1'b0, tx_pma_fastrefclk0in = {wire_pll0_clk[0]}, tx_pma_refclk0in = {wire_pll0_clk[1]}, tx_pma_refclk0inpulse = {wire_pll0_clk[2]}, tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout}, txdataout = {wire_transmit_pma0_dataout}, txdetectrxout = {wire_transmit_pcs0_txdetectrx}; endmodule //altera_tse_altgx_civgx_gige_alt_c3gxb_vs07 //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module altera_tse_altgx_civgx_gige ( cal_blk_clk, gxb_powerdown, pll_inclk, reconfig_clk, reconfig_togxb, rx_analogreset, rx_datain, rx_digitalreset, tx_ctrlenable, tx_datain, tx_digitalreset, reconfig_fromgxb, rx_ctrldetect, rx_dataout, rx_disperr, rx_errdetect, rx_patterndetect, rx_rlv, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_runningdisp, rx_syncstatus, tx_clkout, tx_dataout); input cal_blk_clk; input [0:0] gxb_powerdown; input pll_inclk; input reconfig_clk; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; input [0:0] rx_datain; input [0:0] rx_digitalreset; input [0:0] tx_ctrlenable; input [7:0] tx_datain; input [0:0] tx_digitalreset; output [4:0] reconfig_fromgxb; output [0:0] rx_ctrldetect; output [7:0] rx_dataout; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_patterndetect; output [0:0] rx_rlv; output [0:0] rx_rmfifodatadeleted; output [0:0] rx_rmfifodatainserted; output [0:0] rx_runningdisp; output [0:0] rx_syncstatus; output [0:0] tx_clkout; output [0:0] tx_dataout; parameter starting_channel_number = 0; wire [0:0] sub_wire0; wire [0:0] sub_wire1; wire [0:0] sub_wire2; wire [0:0] sub_wire3; wire [0:0] sub_wire4; wire [0:0] sub_wire5; wire [0:0] sub_wire6; wire [0:0] sub_wire7; wire [0:0] sub_wire8; wire [0:0] sub_wire9; wire [0:0] sub_wire10; wire [4:0] sub_wire11; wire [7:0] sub_wire12; wire [0:0] rx_disperr = sub_wire0[0:0]; wire [0:0] rx_rlv = sub_wire1[0:0]; wire [0:0] rx_patterndetect = sub_wire2[0:0]; wire [0:0] rx_ctrldetect = sub_wire3[0:0]; wire [0:0] rx_errdetect = sub_wire4[0:0]; wire [0:0] rx_rmfifodatadeleted = sub_wire5[0:0]; wire [0:0] rx_runningdisp = sub_wire6[0:0]; wire [0:0] tx_dataout = sub_wire7[0:0]; wire [0:0] rx_rmfifodatainserted = sub_wire8[0:0]; wire [0:0] rx_syncstatus = sub_wire9[0:0]; wire [0:0] tx_clkout = sub_wire10[0:0]; wire [4:0] reconfig_fromgxb = sub_wire11[4:0]; wire [7:0] rx_dataout = sub_wire12[7:0]; altera_tse_altgx_civgx_gige_alt_c3gxb_vs07 altera_tse_altgx_civgx_gige_alt_c3gxb_vs07_component ( .pll_inclk (pll_inclk), .gxb_powerdown (gxb_powerdown), .tx_datain (tx_datain), .cal_blk_clk (cal_blk_clk), .reconfig_clk (reconfig_clk), .rx_datain (rx_datain), .reconfig_togxb (reconfig_togxb), .tx_ctrlenable (tx_ctrlenable), .rx_analogreset (rx_analogreset), .rx_digitalreset (rx_digitalreset), .tx_digitalreset (tx_digitalreset), .rx_disperr (sub_wire0), .rx_rlv (sub_wire1), .rx_patterndetect (sub_wire2), .rx_ctrldetect (sub_wire3), .rx_errdetect (sub_wire4), .rx_rmfifodatadeleted (sub_wire5), .rx_runningdisp (sub_wire6), .tx_dataout (sub_wire7), .rx_rmfifodatainserted (sub_wire8), .rx_syncstatus (sub_wire9), .tx_clkout (sub_wire10), .reconfig_fromgxb (sub_wire11), .rx_dataout (sub_wire12)); defparam altera_tse_altgx_civgx_gige_alt_c3gxb_vs07_component.starting_channel_number = starting_channel_number; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" // Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0" // Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC" // Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none" // Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0" // Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250" // Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0" // Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0" // Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0" // Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250" // Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0" // Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None" // Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0" // Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0" // Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250 Mbps" // Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false" // Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true" // Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true" // Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0" // Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false" // Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "" // Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" // Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6" // Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY" // Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb" // Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb" // Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1" // Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex" // Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "High" // Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1" // Retrieval info: CONSTANT: PROTOCOL STRING "gige" // Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0" // Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10" // Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false" // Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE" // Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v" // Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true" // Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32" // Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20" // Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5" // Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true" // Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2" // Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true" // Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false" // Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false" // Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false" // Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v" // Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High" // Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU" // Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium" // Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true" // Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1" // Retrieval info: CONSTANT: equalization_setting NUMERIC "1" // Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1" // Retrieval info: CONSTANT: number_of_quads NUMERIC "1" // Retrieval info: CONSTANT: pll_divide_by STRING "1" // Retrieval info: CONSTANT: pll_multiply_by STRING "5" // Retrieval info: CONSTANT: reconfig_calibration STRING "true" // Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5" // Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4" // Retrieval info: CONSTANT: rx_deskew_pattern STRING "0" // Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1" // Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1" // Retrieval info: CONSTANT: rx_use_external_termination STRING "false" // Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1" // Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: tx_use_external_termination STRING "false" // Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk" // Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]" // Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk" // Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk" // Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]" // Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]" // Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]" // Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]" // Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]" // Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]" // Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]" // Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]" // Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]" // Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]" // Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]" // Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]" // Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]" // Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]" // Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]" // Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]" // Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]" // Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]" // Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]" // Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]" // Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0 // Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0 // Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0 // Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0 // Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0 // Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0 // Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0 // Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0 // Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0 // Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0 // Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0 // Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 // Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0 // Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0 // Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0 // Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 // Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0 // Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0 // Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0 // Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0 // Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0 // Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0 // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: LIB_FILE: cycloneiv_hssi
// megafunction wizard: %ROM: 1-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: frac_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ********************************************************** // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition // ********************************************************** //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module frac_rom ( address, clock, q); input [3:0] address; input clock; output [7:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "qrom.hex" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "4" // Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "qrom.hex" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL "address[3..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" // Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.bsf TRUE FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_syn.v TRUE // Retrieval info: LIB_FILE: altera_mf
// UC Berkeley CS251 // Spring 2018 // Arya Reais-Parsi ([email protected]) `include "const.vh" module no_cache_mem #( parameter CPU_WIDTH = `CPU_INST_BITS, parameter WORD_ADDR_BITS = `CPU_ADDR_BITS-`ceilLog2(`CPU_INST_BITS/8) ) ( input clk, input reset, input cpu_req_val, output cpu_req_rdy, input [WORD_ADDR_BITS-1:0] cpu_req_addr, input [CPU_WIDTH-1:0] cpu_req_data, input [3:0] cpu_req_write, output reg cpu_resp_val, output reg [CPU_WIDTH-1:0] cpu_resp_data ); localparam DEPTH = 2512512; localparam WORDS = `MEM_DATA_BITS/CPU_WIDTH; reg [`MEM_DATA_BITS-1:0] ram [DEPTH-1:0]; wire [WORD_ADDR_BITS-`ceilLog2(WORDS)-1:0] upper_addr; assign upper_addr = cpu_req_addr[WORD_ADDR_BITS-1:`ceilLog2(WORDS)]; wire [`ceilLog2(WORDS)-1:0] lower_addr; assign lower_addr = cpu_req_addr[`ceilLog2(WORDS)-1:0]; wire [`MEM_DATA_BITS-1:0] read_data; assign read_data = (ram[upper_addr] >> CPU_WIDTHlower_addr); assign cpu_req_rdy = 1'b1; wire [CPU_WIDTH-1:0] wmask; assign wmask = {{8{cpu_req_write[3]}},{8{cpu_req_write[2]}},{8{cpu_req_write[1]}},{8{cpu_req_write[0]}}}; wire [`MEM_DATA_BITS-1:0] write_data; assign write_data = (ram[upper_addr] & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}},wmask} << CPU_WIDTHlower_addr)) \| ((cpu_req_data & wmask) << CPU_WIDTH*lower_addr); always @(posedge clk) begin if (reset) cpu_resp_val <= 1'b0; else if (cpu_req_val && cpu_req_rdy) begin if (cpu_req_write) begin cpu_resp_val <= 1'b0; ram[upper_addr] <= write_data; end else begin cpu_resp_val <= 1'b1; cpu_resp_data <= read_data[CPU_WIDTH-1:0]; end end else cpu_resp_val <= 1'b0; end initial begin : zero integer i; for (i = 0; i < DEPTH; i = i + 1) ram[i] = 0; end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_unused_ports.v * * Date : 2012-11 * * Description : Semantic checks for unused ports. * ****************************************************************************/ / CAN / assign CAN0_PHY_TX = 0; assign CAN1_PHY_TX = 0; always @(CAN0_PHY_RX or CAN1_PHY_RX) begin if(CAN0_PHY_RX \| CAN1_PHY_RX) $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / ETHERNET / / ------------------------------------------- / assign ENET0_GMII_TX_EN = 0; assign ENET0_GMII_TX_ER = 0; assign ENET0_MDIO_MDC = 0; assign ENET0_MDIO_O = 0; /// confirm assign ENET0_MDIO_T = 0; assign ENET0_PTP_DELAY_REQ_RX = 0; assign ENET0_PTP_DELAY_REQ_TX = 0; assign ENET0_PTP_PDELAY_REQ_RX = 0; assign ENET0_PTP_PDELAY_REQ_TX = 0; assign ENET0_PTP_PDELAY_RESP_RX = 0; assign ENET0_PTP_PDELAY_RESP_TX = 0; assign ENET0_PTP_SYNC_FRAME_RX = 0; assign ENET0_PTP_SYNC_FRAME_TX = 0; assign ENET0_SOF_RX = 0; assign ENET0_SOF_TX = 0; assign ENET0_GMII_TXD = 0; always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD) begin if(ENET0_GMII_COL \| ENET0_GMII_CRS \| ENET0_EXT_INTIN \| ENET0_GMII_RX_CLK \| ENET0_GMII_RX_DV \| ENET0_GMII_RX_ER \| ENET0_GMII_TX_CLK \| ENET0_MDIO_I ) $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); end assign ENET1_GMII_TX_EN = 0; assign ENET1_GMII_TX_ER = 0; assign ENET1_MDIO_MDC = 0; assign ENET1_MDIO_O = 0;/// confirm assign ENET1_MDIO_T = 0; assign ENET1_PTP_DELAY_REQ_RX = 0; assign ENET1_PTP_DELAY_REQ_TX = 0; assign ENET1_PTP_PDELAY_REQ_RX = 0; assign ENET1_PTP_PDELAY_REQ_TX = 0; assign ENET1_PTP_PDELAY_RESP_RX = 0; assign ENET1_PTP_PDELAY_RESP_TX = 0; assign ENET1_PTP_SYNC_FRAME_RX = 0; assign ENET1_PTP_SYNC_FRAME_TX = 0; assign ENET1_SOF_RX = 0; assign ENET1_SOF_TX = 0; assign ENET1_GMII_TXD = 0; always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD) begin if(ENET1_GMII_COL \| ENET1_GMII_CRS \| ENET1_EXT_INTIN \| ENET1_GMII_RX_CLK \| ENET1_GMII_RX_DV \| ENET1_GMII_RX_ER \| ENET1_GMII_TX_CLK \| ENET1_MDIO_I ) $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / GPIO / / ------------------------------------------- / assign GPIO_O = 0; assign GPIO_T = 0; always@(GPIO_I) begin if(GPIO_I !== 0) $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / I2C / / ------------------------------------------- / assign I2C0_SDA_O = 0; assign I2C0_SDA_T = 0; assign I2C0_SCL_O = 0; assign I2C0_SCL_T = 0; assign I2C1_SDA_O = 0; assign I2C1_SDA_T = 0; assign I2C1_SCL_O = 0; assign I2C1_SCL_T = 0; always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I ) begin if(I2C0_SDA_I \| I2C0_SCL_I \| I2C1_SDA_I \| I2C1_SCL_I) $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / JTAG / / ------------------------------------------- / assign PJTAG_TD_T = 0; assign PJTAG_TD_O = 0; always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I) begin if(PJTAG_TCK \| PJTAG_TMS \| PJTAG_TD_I) $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / SDIO / / ------------------------------------------- / assign SDIO0_CLK = 0; assign SDIO0_CMD_O = 0; assign SDIO0_CMD_T = 0; assign SDIO0_DATA_O = 0; assign SDIO0_DATA_T = 0; assign SDIO0_LED = 0; assign SDIO0_BUSPOW = 0; assign SDIO0_BUSVOLT = 0; always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP ) begin if(SDIO0_CLK_FB \| SDIO0_CMD_I \| SDIO0_CDN \| SDIO0_WP ) $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); end assign SDIO1_CLK = 0; assign SDIO1_CMD_O = 0; assign SDIO1_CMD_T = 0; assign SDIO1_DATA_O = 0; assign SDIO1_DATA_T = 0; assign SDIO1_LED = 0; assign SDIO1_BUSPOW = 0; assign SDIO1_BUSVOLT = 0; always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP ) begin if(SDIO1_CLK_FB \| SDIO1_CMD_I \| SDIO1_CDN \| SDIO1_WP ) $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / SPI / / ------------------------------------------- / assign SPI0_SCLK_O = 0; assign SPI0_SCLK_T = 0; assign SPI0_MOSI_O = 0; assign SPI0_MOSI_T = 0; assign SPI0_MISO_O = 0; assign SPI0_MISO_T = 0; assign SPI0_SS_O = 0; /// confirm assign SPI0_SS1_O = 0;/// confirm assign SPI0_SS2_O = 0;/// confirm assign SPI0_SS_T = 0; always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I) begin if(SPI0_SCLK_I \| SPI0_MOSI_I \| SPI0_MISO_I \| SPI0_SS_I) $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); end assign SPI1_SCLK_O = 0; assign SPI1_SCLK_T = 0; assign SPI1_MOSI_O = 0; assign SPI1_MOSI_T = 0; assign SPI1_MISO_O = 0; assign SPI1_MISO_T = 0; assign SPI1_SS_O = 0; assign SPI1_SS1_O = 0; assign SPI1_SS2_O = 0; assign SPI1_SS_T = 0; always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I) begin if(SPI1_SCLK_I \| SPI1_MOSI_I \| SPI1_MISO_I \| SPI1_SS_I) $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / UART / / ------------------------------------------- / /// confirm assign UART0_DTRN = 0; assign UART0_RTSN = 0; assign UART0_TX = 0; always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX) begin if(UART0_CTSN \| UART0_DCDN \| UART0_DSRN \| UART0_RIN \| UART0_RX) $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); end assign UART1_DTRN = 0; assign UART1_RTSN = 0; assign UART1_TX = 0; always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX) begin if(UART1_CTSN \| UART1_DCDN \| UART1_DSRN \| UART1_RIN \| UART1_RX) $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / TTC / / ------------------------------------------- / assign TTC0_WAVE0_OUT = 0; assign TTC0_WAVE1_OUT = 0; assign TTC0_WAVE2_OUT = 0; always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN) begin if(TTC0_CLK0_IN \| TTC0_CLK1_IN \| TTC0_CLK2_IN) $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); end assign TTC1_WAVE0_OUT = 0; assign TTC1_WAVE1_OUT = 0; assign TTC1_WAVE2_OUT = 0; always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN) begin if(TTC1_CLK0_IN \| TTC1_CLK1_IN \| TTC1_CLK2_IN) $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / WDT / / ------------------------------------------- / assign WDT_RST_OUT = 0; always@(WDT_CLK_IN) begin if(WDT_CLK_IN) $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / TRACE / / ------------------------------------------- / assign TRACE_CTL = 0; assign TRACE_DATA = 0; always@(TRACE_CLK) begin if(TRACE_CLK) $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / USB / / ------------------------------------------- / assign USB0_PORT_INDCTL = 0; assign USB0_VBUS_PWRSELECT = 0; always@(USB0_VBUS_PWRFAULT) begin if(USB0_VBUS_PWRFAULT) $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); end assign USB1_PORT_INDCTL = 0; assign USB1_VBUS_PWRSELECT = 0; always@(USB1_VBUS_PWRFAULT) begin if(USB1_VBUS_PWRFAULT) $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); end always@(SRAM_INTIN) begin if(SRAM_INTIN) $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / DMA / / ------------------------------------------- / assign DMA0_DATYPE = 0; assign DMA0_DAVALID = 0; assign DMA0_DRREADY = 0; assign DMA0_RSTN = 0; always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE) begin if(DMA0_ACLK \| DMA0_DAREADY \| DMA0_DRLAST \| DMA0_DRVALID \| DMA0_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end assign DMA1_DATYPE = 0; assign DMA1_DAVALID = 0; assign DMA1_DRREADY = 0; assign DMA1_RSTN = 0; always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE) begin if(DMA1_ACLK \| DMA1_DAREADY \| DMA1_DRLAST \| DMA1_DRVALID \| DMA1_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end assign DMA2_DATYPE = 0; assign DMA2_DAVALID = 0; assign DMA2_DRREADY = 0; assign DMA2_RSTN = 0; always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE) begin if(DMA2_ACLK \| DMA2_DAREADY \| DMA2_DRLAST \| DMA2_DRVALID \| DMA2_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end assign DMA3_DATYPE = 0; assign DMA3_DAVALID = 0; assign DMA3_DRREADY = 0; assign DMA3_RSTN = 0; always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE) begin if(DMA3_ACLK \| DMA3_DAREADY \| DMA3_DRLAST \| DMA3_DRVALID \| DMA3_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / FTM / / ------------------------------------------- / assign FTMT_F2P_TRIGACK = 0; assign FTMT_P2F_TRIG = 0; assign FTMT_P2F_DEBUG = 0; always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK) begin if(FTMD_TRACEIN_DATA \| FTMD_TRACEIN_VALID \| FTMD_TRACEIN_CLK \| FTMD_TRACEIN_ATID \| FTMT_F2P_TRIG \| FTMT_F2P_DEBUG \| FTMT_P2F_TRIGACK) $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / EVENT / / ------------------------------------------- / assign EVENT_EVENTO = 0; assign EVENT_STANDBYWFE = 0; assign EVENT_STANDBYWFI = 0; always@(EVENT_EVENTI) begin if(EVENT_EVENTI) $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / MIO / / ------------------------------------------- / always@(MIO) begin if(MIO !== 0) $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / FCLK_TRIG / / ------------------------------------------- / always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N ) begin if(FCLK_CLKTRIG3_N \| FCLK_CLKTRIG2_N \| FCLK_CLKTRIG1_N \| FCLK_CLKTRIG0_N ) $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / MISC / / ------------------------------------------- / always@(FPGA_IDLE_N) begin if(FPGA_IDLE_N) $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR); end always@(DDR_ARB) begin if(DDR_ARB !== 0) $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR); end always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ ) begin if(Core0_nFIQ \| Core0_nIRQ \| Core1_nFIQ \| Core1_nIRQ) $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / DDR / / ------------------------------------------- / assign DDR_WEB = 0; always@(DDR_Clk or DDR_CS_n) begin if(!DDR_CS_n) $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR); end / ------------------------------------------- / / IRQ_P2F / / ------------------------------------------- */ assign IRQ_P2F_DMAC_ABORT = 0; assign IRQ_P2F_DMAC0 = 0; assign IRQ_P2F_DMAC1 = 0; assign IRQ_P2F_DMAC2 = 0; assign IRQ_P2F_DMAC3 = 0; assign IRQ_P2F_DMAC4 = 0; assign IRQ_P2F_DMAC5 = 0; assign IRQ_P2F_DMAC6 = 0; assign IRQ_P2F_DMAC7 = 0; assign IRQ_P2F_SMC = 0; assign IRQ_P2F_QSPI = 0; assign IRQ_P2F_CTI = 0; assign IRQ_P2F_GPIO = 0; assign IRQ_P2F_USB0 = 0; assign IRQ_P2F_ENET0 = 0; assign IRQ_P2F_ENET_WAKE0 = 0; assign IRQ_P2F_SDIO0 = 0; assign IRQ_P2F_I2C0 = 0; assign IRQ_P2F_SPI0 = 0; assign IRQ_P2F_UART0 = 0; assign IRQ_P2F_CAN0 = 0; assign IRQ_P2F_USB1 = 0; assign IRQ_P2F_ENET1 = 0; assign IRQ_P2F_ENET_WAKE1 = 0; assign IRQ_P2F_SDIO1 = 0; assign IRQ_P2F_I2C1 = 0; assign IRQ_P2F_SPI1 = 0; assign IRQ_P2F_UART1 = 0; assign IRQ_P2F_CAN1 = 0;
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_HD__SDFSTP_TB_V `define SKY130_FD_SC_HD__SDFSTP_TB_V /* * sdfstp: Scan delay flop, inverted set, non-inverted clock, * single output. * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__sdfstp.v" module top(); // Inputs are registered reg D; reg SCD; reg SCE; reg SET_B; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire Q; initial begin // Initial state is x for all inputs. D = 1'bX; SCD = 1'bX; SCE = 1'bX; SET_B = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 D = 1'b0; #40 SCD = 1'b0; #60 SCE = 1'b0; #80 SET_B = 1'b0; #100 VGND = 1'b0; #120 VNB = 1'b0; #140 VPB = 1'b0; #160 VPWR = 1'b0; #180 D = 1'b1; #200 SCD = 1'b1; #220 SCE = 1'b1; #240 SET_B = 1'b1; #260 VGND = 1'b1; #280 VNB = 1'b1; #300 VPB = 1'b1; #320 VPWR = 1'b1; #340 D = 1'b0; #360 SCD = 1'b0; #380 SCE = 1'b0; #400 SET_B = 1'b0; #420 VGND = 1'b0; #440 VNB = 1'b0; #460 VPB = 1'b0; #480 VPWR = 1'b0; #500 VPWR = 1'b1; #520 VPB = 1'b1; #540 VNB = 1'b1; #560 VGND = 1'b1; #580 SET_B = 1'b1; #600 SCE = 1'b1; #620 SCD = 1'b1; #640 D = 1'b1; #660 VPWR = 1'bx; #680 VPB = 1'bx; #700 VNB = 1'bx; #720 VGND = 1'bx; #740 SET_B = 1'bx; #760 SCE = 1'bx; #780 SCD = 1'bx; #800 D = 1'bx; end // Create a clock reg CLK; initial begin CLK = 1'b0; end always begin #5 CLK = ~CLK; end sky130_fd_sc_hd__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK)); endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__SDFSTP_TB_V
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/AUTOARG/ // Inputs clk ); input clk; sub #(.IDX(0), .CHK(10)) i0; sub #(.IDX(2), .CHK(12)) i2; sub #(.IDX(7), .CHK(17)) i7; always @ (posedge clk) begin $write("- All Finished -\n"); $finish; end endmodule module sub (); function integer get_element; input integer index; input integer array_arg[7:0]; get_element = array_arg[index]; endfunction parameter integer IDX = 5; parameter integer CHK = 5; localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; localparam element1 = array[IDX]; localparam elementf = get_element(IDX, array); initial begin `checkh (element1, CHK); `checkh (elementf, CHK); end endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V `define SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V /* * clkbuf: Clock tree buffer. * * Verilog stub definition (black box without power pins). * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none ( blackbox *) module sky130_fd_sc_lp__clkbuf ( X, A ); output X; input A; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/AUTOARG/ // Inputs clk ); input clk; parameter [31:0] TWENTY4 = 24; parameter [31:0] PA = TWENTY4/8; parameter [1:0] VALUE = 2'b10; parameter [5:0] REPL = {PA{VALUE}}; parameter [7:0] CONC = {REPL,VALUE}; parameter DBITS = 32; parameter INIT_BYTE = 8'h1F; parameter DWORDS_LOG2 = 7; parameter DWORDS = (1<<DWORDS_LOG2); parameter DBYTES=DBITS/8; // verilator lint_off LITENDIAN reg [DBITS-1:0] mem [0:DWORDS-1]; // verilator lint_on LITENDIAN integer i; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if (REPL != {2'b10,2'b10,2'b10}) $stop; if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop; end if (cyc==2) begin for (i = 0; i < DWORDS; i = i + 1) mem[i] = {DBYTES{INIT_BYTE}}; end if (cyc==3) begin for (i = 0; i < DWORDS; i = i + 1) if (mem[i] != {DBYTES{INIT_BYTE}}) $stop; end if (cyc==9) begin $write("- All Finished -\n"); $finish; end end endmodule
//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: P.20131013 // \ \ Application: netgen // / / Filename: ApBrC.v // /___/ /\ Timestamp: Thu Mar 26 21:09:09 2015 // \ \ / \ // \___\/\___\ // // Command : -w -sim -ofmt verilog /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.ngc /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.v // Device : 3s500efg320-4 // Input file : /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.ngc // Output file : /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.v // # of Modules : 1 // Design Name : ApBrC // Xilinx : /mnt/data/Xilinx/14.7/ISE_DS/ISE/ // // Purpose: // This verilog netlist is a verification model and uses simulation // primitives which may not represent the true implementation of the // device, however the netlist is functionally correct and should not // be modified. This file cannot be synthesized and should only be used // with supported simulation tools. // // Reference: // Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ps module ApBrC ( clk, ce, p, a, b )/* synthesis syn_black_box syn_noprune=1 */; input clk; input ce; output [37 : 0] p; input [18 : 0] a; input [18 : 0] b; // synthesis translate_off wire \blk00000001/sig00000171 ; wire \blk00000001/sig00000170 ; wire \blk00000001/sig0000016f ; wire \blk00000001/sig0000016e ; wire \blk00000001/sig0000016d ; wire \blk00000001/sig0000016c ; wire \blk00000001/sig0000016b ; wire \blk00000001/sig0000016a ; wire \blk00000001/sig00000169 ; wire \blk00000001/sig00000168 ; wire \blk00000001/sig00000167 ; wire \blk00000001/sig00000166 ; wire \blk00000001/sig00000165 ; wire \blk00000001/sig00000164 ; wire \blk00000001/sig00000163 ; wire \blk00000001/sig00000162 ; wire \blk00000001/sig00000161 ; wire \blk00000001/sig00000160 ; wire \blk00000001/sig0000015f ; wire \blk00000001/sig0000015e ; wire \blk00000001/sig0000015d ; wire \blk00000001/sig0000015c ; wire \blk00000001/sig0000015b ; wire \blk00000001/sig0000015a ; wire \blk00000001/sig00000159 ; wire \blk00000001/sig00000158 ; wire \blk00000001/sig00000157 ; wire \blk00000001/sig00000156 ; wire \blk00000001/sig00000155 ; wire \blk00000001/sig00000154 ; wire \blk00000001/sig00000153 ; wire \blk00000001/sig00000152 ; wire \blk00000001/sig00000151 ; wire \blk00000001/sig00000150 ; wire \blk00000001/sig0000014f ; wire \blk00000001/sig0000014e ; wire \blk00000001/sig0000014d ; wire \blk00000001/sig0000014c ; wire \blk00000001/sig0000014b ; wire \blk00000001/sig0000014a ; wire \blk00000001/sig00000149 ; wire \blk00000001/sig00000148 ; wire \blk00000001/sig00000147 ; wire \blk00000001/sig00000146 ; wire \blk00000001/sig00000145 ; wire \blk00000001/sig00000144 ; wire \blk00000001/sig00000143 ; wire \blk00000001/sig00000142 ; wire \blk00000001/sig00000141 ; wire \blk00000001/sig00000140 ; wire \blk00000001/sig0000013f ; wire \blk00000001/sig0000013e ; wire \blk00000001/sig0000013d ; wire \blk00000001/sig0000013c ; wire \blk00000001/sig0000013b ; wire \blk00000001/sig0000013a ; wire \blk00000001/sig00000139 ; wire \blk00000001/sig00000138 ; wire \blk00000001/sig00000137 ; wire \blk00000001/sig00000136 ; wire \blk00000001/sig00000135 ; wire \blk00000001/sig00000134 ; wire \blk00000001/sig00000133 ; wire \blk00000001/sig00000132 ; wire \blk00000001/sig00000131 ; wire \blk00000001/sig00000130 ; wire \blk00000001/sig0000012f ; wire \blk00000001/sig0000012e ; wire \blk00000001/sig0000012d ; wire \blk00000001/sig0000012c ; wire \blk00000001/sig0000012b ; wire \blk00000001/sig0000012a ; wire \blk00000001/sig00000129 ; wire \blk00000001/sig00000128 ; wire \blk00000001/sig00000127 ; wire \blk00000001/sig00000126 ; wire \blk00000001/sig00000125 ; wire \blk00000001/sig00000124 ; wire \blk00000001/sig00000123 ; wire \blk00000001/sig00000122 ; wire \blk00000001/sig00000121 ; wire \blk00000001/sig00000120 ; wire \blk00000001/sig0000011f ; wire \blk00000001/sig0000011e ; wire \blk00000001/sig0000011d ; wire \blk00000001/sig0000011c ; wire \blk00000001/sig0000011b ; wire \blk00000001/sig0000011a ; wire \blk00000001/sig00000119 ; wire \blk00000001/sig00000118 ; wire \blk00000001/sig00000117 ; wire \blk00000001/sig00000116 ; wire \blk00000001/sig00000115 ; wire \blk00000001/sig00000114 ; wire \blk00000001/sig00000113 ; wire \blk00000001/sig00000112 ; wire \blk00000001/sig00000111 ; wire \blk00000001/sig00000110 ; wire \blk00000001/sig0000010f ; wire \blk00000001/sig0000010e ; wire \blk00000001/sig0000010d ; wire \blk00000001/sig0000010c ; wire \blk00000001/sig0000010b ; wire \blk00000001/sig0000010a ; wire \blk00000001/sig00000109 ; wire \blk00000001/sig00000108 ; wire \blk00000001/sig00000107 ; wire \blk00000001/sig00000106 ; wire \blk00000001/sig00000105 ; wire \blk00000001/sig00000104 ; wire \blk00000001/sig00000103 ; wire \blk00000001/sig00000102 ; wire \blk00000001/sig00000101 ; wire \blk00000001/sig00000100 ; wire \blk00000001/sig000000ff ; wire \blk00000001/sig000000fe ; wire \blk00000001/sig000000fd ; wire \blk00000001/sig000000fc ; wire \blk00000001/sig000000fb ; wire \blk00000001/sig000000fa ; wire \blk00000001/sig000000f9 ; wire \blk00000001/sig000000f8 ; wire \blk00000001/sig000000f7 ; wire \blk00000001/sig000000f6 ; wire \blk00000001/sig000000f5 ; wire \blk00000001/sig000000f4 ; wire \blk00000001/sig000000f3 ; wire \blk00000001/sig000000f2 ; wire \blk00000001/sig000000f1 ; wire \blk00000001/sig000000f0 ; wire \blk00000001/sig000000ef ; wire \blk00000001/sig000000ee ; wire \blk00000001/sig000000ed ; wire \blk00000001/sig000000ec ; wire \blk00000001/sig000000eb ; wire \blk00000001/sig000000ea ; wire \blk00000001/sig000000e9 ; wire \blk00000001/sig000000e8 ; wire \blk00000001/sig000000e7 ; wire \blk00000001/sig000000e6 ; wire \blk00000001/sig000000e5 ; wire \blk00000001/sig000000e4 ; wire \blk00000001/sig000000e3 ; wire \blk00000001/sig000000e2 ; wire \blk00000001/sig000000e1 ; wire \blk00000001/sig000000e0 ; wire \blk00000001/sig000000df ; wire \blk00000001/sig000000de ; wire \blk00000001/sig000000dd ; wire \blk00000001/sig000000dc ; wire \blk00000001/sig000000db ; wire \blk00000001/sig000000da ; wire \blk00000001/sig000000d9 ; wire \blk00000001/sig000000d8 ; wire \blk00000001/sig000000d7 ; wire \blk00000001/sig000000d6 ; wire \blk00000001/sig000000d5 ; wire \blk00000001/sig000000d4 ; wire \blk00000001/sig000000d3 ; wire \blk00000001/sig000000d2 ; wire \blk00000001/sig000000d1 ; wire \blk00000001/sig000000d0 ; wire \blk00000001/sig000000cf ; wire \blk00000001/sig000000ce ; wire \blk00000001/sig000000cd ; wire \blk00000001/sig000000cc ; wire \blk00000001/sig000000cb ; wire \blk00000001/sig000000ca ; wire \blk00000001/sig000000c9 ; wire \blk00000001/sig000000c8 ; wire \blk00000001/sig000000c7 ; wire \blk00000001/sig000000c6 ; wire \blk00000001/sig000000c5 ; wire \blk00000001/sig000000c4 ; wire \blk00000001/sig000000c3 ; wire \blk00000001/sig000000c2 ; wire \blk00000001/sig000000c1 ; wire \blk00000001/sig000000c0 ; wire \blk00000001/sig000000bf ; wire \blk00000001/sig000000be ; wire \blk00000001/sig000000bd ; wire \blk00000001/sig000000bc ; wire \blk00000001/sig000000bb ; wire \blk00000001/sig000000ba ; wire \blk00000001/sig000000b9 ; wire \blk00000001/sig000000b8 ; wire \blk00000001/sig000000b7 ; wire \blk00000001/sig000000b6 ; wire \blk00000001/sig000000b5 ; wire \blk00000001/sig000000b4 ; wire \blk00000001/sig000000b3 ; wire \blk00000001/sig000000b2 ; wire \blk00000001/sig000000b1 ; wire \blk00000001/sig000000b0 ; wire \blk00000001/sig000000af ; wire \blk00000001/sig000000ae ; wire \blk00000001/sig000000ad ; wire \blk00000001/sig000000ac ; wire \blk00000001/sig000000ab ; wire \blk00000001/sig000000aa ; wire \blk00000001/sig000000a9 ; wire \blk00000001/sig000000a8 ; wire \blk00000001/sig000000a7 ; wire \blk00000001/sig000000a6 ; wire \blk00000001/sig000000a5 ; wire \blk00000001/sig000000a4 ; wire \blk00000001/sig000000a3 ; wire \blk00000001/sig000000a2 ; wire \blk00000001/sig000000a1 ; wire \blk00000001/sig000000a0 ; wire \blk00000001/sig0000009f ; wire \blk00000001/sig0000009e ; wire \blk00000001/sig0000009d ; wire \blk00000001/sig0000009c ; wire \blk00000001/sig0000009b ; wire \blk00000001/sig0000009a ; wire \blk00000001/sig00000099 ; wire \blk00000001/sig00000098 ; wire \blk00000001/sig00000097 ; wire \blk00000001/sig00000096 ; wire \blk00000001/sig00000095 ; wire \blk00000001/sig00000094 ; wire \blk00000001/sig00000093 ; wire \blk00000001/sig00000092 ; wire \blk00000001/sig00000091 ; wire \blk00000001/sig00000090 ; wire \blk00000001/sig0000008f ; wire \blk00000001/sig0000008e ; wire \blk00000001/sig0000008d ; wire \blk00000001/sig0000008c ; wire \blk00000001/sig0000008b ; wire \blk00000001/sig0000008a ; wire \blk00000001/sig00000089 ; wire \blk00000001/sig00000088 ; wire \blk00000001/sig00000087 ; wire \blk00000001/sig00000086 ; wire \blk00000001/sig00000085 ; wire \blk00000001/sig00000084 ; wire \blk00000001/sig00000083 ; wire \blk00000001/sig00000082 ; wire \blk00000001/sig00000081 ; wire \blk00000001/sig00000080 ; wire \blk00000001/sig0000007f ; wire \blk00000001/sig0000007e ; wire \blk00000001/sig0000007d ; wire \blk00000001/sig0000007c ; wire \blk00000001/sig0000007b ; wire \blk00000001/sig0000007a ; wire \blk00000001/sig00000079 ; wire \blk00000001/sig00000078 ; wire \blk00000001/sig00000077 ; wire \blk00000001/sig00000076 ; wire \blk00000001/sig00000075 ; wire \blk00000001/sig00000074 ; wire \blk00000001/sig00000073 ; wire \blk00000001/sig00000072 ; wire \blk00000001/sig00000071 ; wire \blk00000001/sig00000070 ; wire \blk00000001/sig0000006f ; wire \blk00000001/sig0000006e ; wire \blk00000001/sig0000006d ; wire \blk00000001/sig0000006c ; wire \blk00000001/sig0000006b ; wire \blk00000001/sig0000006a ; wire \blk00000001/sig00000069 ; wire \blk00000001/sig00000068 ; wire \blk00000001/sig00000067 ; wire \blk00000001/sig00000066 ; wire \blk00000001/sig00000065 ; wire \blk00000001/sig00000064 ; wire \blk00000001/sig00000063 ; wire \blk00000001/sig00000062 ; wire \blk00000001/sig00000061 ; wire \blk00000001/sig00000060 ; wire \blk00000001/sig0000005f ; wire \blk00000001/sig0000005e ; wire \blk00000001/sig0000005d ; wire \blk00000001/sig0000005c ; wire \blk00000001/sig0000005b ; wire \blk00000001/sig0000005a ; wire \blk00000001/sig00000059 ; wire \blk00000001/sig00000058 ; wire \blk00000001/sig00000057 ; wire \blk00000001/sig00000056 ; wire \blk00000001/sig00000055 ; wire \blk00000001/sig00000054 ; wire \blk00000001/sig00000053 ; wire \blk00000001/sig00000052 ; wire \blk00000001/sig00000051 ; wire \blk00000001/sig00000050 ; wire \blk00000001/sig0000004f ; wire \blk00000001/sig0000004e ; wire \blk00000001/sig0000004d ; wire \blk00000001/sig0000004c ; wire \blk00000001/sig0000004b ; wire \blk00000001/sig0000004a ; wire \blk00000001/sig00000049 ; wire \blk00000001/sig00000048 ; wire \blk00000001/sig00000047 ; wire \blk00000001/sig00000046 ; wire \blk00000001/sig00000045 ; wire \blk00000001/sig00000044 ; wire \blk00000001/sig00000043 ; wire \blk00000001/sig00000042 ; wire \blk00000001/sig00000041 ; wire \blk00000001/sig00000040 ; wire \blk00000001/sig0000003f ; wire \blk00000001/sig0000003e ; wire \blk00000001/sig0000003d ; wire \blk00000001/sig0000003c ; wire \blk00000001/sig0000003b ; wire \blk00000001/sig0000003a ; wire \blk00000001/sig00000039 ; wire \blk00000001/sig00000038 ; wire \blk00000001/sig00000037 ; wire \blk00000001/sig00000036 ; wire \blk00000001/sig00000035 ; wire \blk00000001/sig00000034 ; wire \blk00000001/sig00000033 ; wire \blk00000001/sig00000032 ; wire \blk00000001/sig00000031 ; wire \blk00000001/sig00000030 ; wire \blk00000001/sig0000002f ; wire \blk00000001/sig0000002e ; wire \blk00000001/sig0000002d ; wire \blk00000001/sig0000002c ; wire \blk00000001/sig0000002b ; wire \blk00000001/sig0000002a ; wire \blk00000001/sig00000029 ; wire \NLW_blk00000001/blk00000006_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<0>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<21>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<0>_UNCONNECTED ; FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000127 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000095 ), .Q(\blk00000001/sig000000a6 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000126 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ed ), .Q(\blk00000001/sig00000095 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000125 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000096 ), .Q(\blk00000001/sig000000a7 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000124 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f7 ), .Q(\blk00000001/sig00000096 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000123 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009e ), .Q(\blk00000001/sig000000af ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000122 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f8 ), .Q(\blk00000001/sig0000009e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000121 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009f ), .Q(\blk00000001/sig000000b0 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000120 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f9 ), .Q(\blk00000001/sig0000009f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000011f ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a0 ), .Q(\blk00000001/sig000000b1 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000011e ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fa ), .Q(\blk00000001/sig000000a0 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000011d ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a1 ), .Q(\blk00000001/sig000000b2 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000011c ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fb ), .Q(\blk00000001/sig000000a1 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000011b ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a2 ), .Q(\blk00000001/sig000000b3 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000011a ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fc ), .Q(\blk00000001/sig000000a2 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000119 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a3 ), .Q(\blk00000001/sig000000b4 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000118 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fd ), .Q(\blk00000001/sig000000a3 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000117 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a4 ), .Q(\blk00000001/sig000000b5 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000116 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fe ), .Q(\blk00000001/sig000000a4 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000115 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a5 ), .Q(\blk00000001/sig000000b6 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000114 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ff ), .Q(\blk00000001/sig000000a5 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000113 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000097 ), .Q(\blk00000001/sig000000a8 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000112 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ee ), .Q(\blk00000001/sig00000097 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000111 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000098 ), .Q(\blk00000001/sig000000a9 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000110 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ef ), .Q(\blk00000001/sig00000098 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000010f ( .C(clk), .CE(ce), .D(\blk00000001/sig00000099 ), .Q(\blk00000001/sig000000aa ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000010e ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f0 ), .Q(\blk00000001/sig00000099 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000010d ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009a ), .Q(\blk00000001/sig000000ab ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000010c ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f1 ), .Q(\blk00000001/sig0000009a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000010b ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009c ), .Q(\blk00000001/sig000000ad ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000010a ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f3 ), .Q(\blk00000001/sig0000009c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000109 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009d ), .Q(\blk00000001/sig000000ae ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000108 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f4 ), .Q(\blk00000001/sig0000009d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000107 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009b ), .Q(\blk00000001/sig000000ac ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000106 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f2 ), .Q(\blk00000001/sig0000009b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000105 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000029 ), .Q(p[0]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000104 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000b7 ), .Q(\blk00000001/sig00000029 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000103 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002a ), .Q(p[1]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000102 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000c2 ), .Q(\blk00000001/sig0000002a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000101 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000032 ), .Q(p[2]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000100 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000cd ), .Q(\blk00000001/sig00000032 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ff ( .C(clk), .CE(ce), .D(\blk00000001/sig00000033 ), .Q(p[3]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000fe ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d3 ), .Q(\blk00000001/sig00000033 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000fd ( .C(clk), .CE(ce), .D(\blk00000001/sig00000034 ), .Q(p[4]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000fc ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d4 ), .Q(\blk00000001/sig00000034 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000fb ( .C(clk), .CE(ce), .D(\blk00000001/sig00000035 ), .Q(p[5]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000fa ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d5 ), .Q(\blk00000001/sig00000035 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000036 ), .Q(p[6]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f8 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d6 ), .Q(\blk00000001/sig00000036 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000037 ), .Q(p[7]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f6 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d7 ), .Q(\blk00000001/sig00000037 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f5 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000038 ), .Q(p[8]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f4 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d8 ), .Q(\blk00000001/sig00000038 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f3 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000039 ), .Q(p[9]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f2 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d9 ), .Q(\blk00000001/sig00000039 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f1 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002b ), .Q(p[10]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f0 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000b8 ), .Q(\blk00000001/sig0000002b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ef ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002c ), .Q(p[11]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000ee ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000b9 ), .Q(\blk00000001/sig0000002c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ed ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002d ), .Q(p[12]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000ec ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ba ), .Q(\blk00000001/sig0000002d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000eb ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002e ), .Q(p[13]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000ea ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000bb ), .Q(\blk00000001/sig0000002e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000030 ), .Q(p[15]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000e8 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000bd ), .Q(\blk00000001/sig00000030 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000031 ), .Q(p[16]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000e6 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000be ), .Q(\blk00000001/sig00000031 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e5 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002f ), .Q(p[14]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000e4 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000bc ), .Q(\blk00000001/sig0000002f ) ); VCC \blk00000001/blk000000e3 ( .P(\blk00000001/sig0000003a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e2 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000bf ), .Q(\blk00000001/sig00000104 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e1 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c0 ), .Q(\blk00000001/sig00000105 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e0 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c1 ), .Q(\blk00000001/sig00000106 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000df ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c3 ), .Q(\blk00000001/sig00000107 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000de ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c4 ), .Q(\blk00000001/sig00000108 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000dd ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c5 ), .Q(\blk00000001/sig00000109 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000dc ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c6 ), .Q(\blk00000001/sig0000010a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000db ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c7 ), .Q(\blk00000001/sig0000010b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000da ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c8 ), .Q(\blk00000001/sig0000010c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d9 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c9 ), .Q(\blk00000001/sig0000010d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d8 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ca ), .Q(\blk00000001/sig0000010e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d7 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000cb ), .Q(\blk00000001/sig0000010f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d6 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000cc ), .Q(\blk00000001/sig00000110 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d5 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ce ), .Q(\blk00000001/sig00000111 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d4 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000cf ), .Q(\blk00000001/sig00000112 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d3 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000d0 ), .Q(\blk00000001/sig00000113 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d2 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000d1 ), .Q(\blk00000001/sig00000114 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d1 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000d2 ), .Q(\blk00000001/sig00000115 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d0 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000da ), .Q(\blk00000001/sig00000116 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cf ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e4 ), .Q(\blk00000001/sig00000117 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ce ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e5 ), .Q(\blk00000001/sig00000121 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cd ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e6 ), .Q(\blk00000001/sig00000122 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cc ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e7 ), .Q(\blk00000001/sig00000123 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cb ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e8 ), .Q(\blk00000001/sig00000124 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ca ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e9 ), .Q(\blk00000001/sig00000125 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c9 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ea ), .Q(\blk00000001/sig00000126 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c8 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000eb ), .Q(\blk00000001/sig00000127 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c7 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ec ), .Q(\blk00000001/sig00000128 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c6 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000db ), .Q(\blk00000001/sig00000118 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c5 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000dc ), .Q(\blk00000001/sig00000119 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c4 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000dd ), .Q(\blk00000001/sig0000011a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c3 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000de ), .Q(\blk00000001/sig0000011b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c2 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000df ), .Q(\blk00000001/sig0000011c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c1 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e0 ), .Q(\blk00000001/sig0000011d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c0 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e1 ), .Q(\blk00000001/sig0000011e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bf ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e2 ), .Q(\blk00000001/sig0000011f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000be ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e3 ), .Q(\blk00000001/sig00000120 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bd ( .C(clk), .CE(ce), .D(\blk00000001/sig000000f5 ), .Q(\blk00000001/sig00000129 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bc ( .C(clk), .CE(ce), .D(\blk00000001/sig000000f6 ), .Q(\blk00000001/sig0000012a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bb ( .C(clk), .CE(ce), .D(\blk00000001/sig00000100 ), .Q(\blk00000001/sig0000012b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ba ( .C(clk), .CE(ce), .D(\blk00000001/sig00000101 ), .Q(\blk00000001/sig0000012c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000102 ), .Q(\blk00000001/sig0000012d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b8 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000103 ), .Q(\blk00000001/sig0000012e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000155 ), .Q(\blk00000001/sig00000159 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b6 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000156 ), .Q(\blk00000001/sig0000015a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b5 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000157 ), .Q(\blk00000001/sig0000015b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b4 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000158 ), .Q(\blk00000001/sig0000015c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b3 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000012f ), .Q(\blk00000001/sig00000142 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b2 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000139 ), .Q(\blk00000001/sig00000143 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b1 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013a ), .Q(\blk00000001/sig0000014d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b0 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013b ), .Q(\blk00000001/sig0000014e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000af ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013c ), .Q(\blk00000001/sig0000014f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ae ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013d ), .Q(\blk00000001/sig00000150 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ad ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013e ), .Q(\blk00000001/sig00000151 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ac ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013f ), .Q(\blk00000001/sig00000152 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ab ( .C(clk), .CE(ce), .D(\blk00000001/sig00000140 ), .Q(\blk00000001/sig00000153 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000aa ( .C(clk), .CE(ce), .D(\blk00000001/sig00000141 ), .Q(\blk00000001/sig00000154 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000130 ), .Q(\blk00000001/sig00000144 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a8 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000131 ), .Q(\blk00000001/sig00000145 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000132 ), .Q(\blk00000001/sig00000146 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a6 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000133 ), .Q(\blk00000001/sig00000147 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a5 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000134 ), .Q(\blk00000001/sig00000148 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a4 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000135 ), .Q(\blk00000001/sig00000149 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a3 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000136 ), .Q(\blk00000001/sig0000014a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a2 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000137 ), .Q(\blk00000001/sig0000014b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a1 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000138 ), .Q(\blk00000001/sig0000014c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a0 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000015d ), .Q(p[17]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009f ( .C(clk), .CE(ce), .D(\blk00000001/sig00000168 ), .Q(p[18]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009e ( .C(clk), .CE(ce), .D(\blk00000001/sig00000169 ), .Q(p[19]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009d ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016a ), .Q(p[20]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009c ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016b ), .Q(p[21]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009b ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016d ), .Q(p[22]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009a ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016e ), .Q(p[23]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000099 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016f ), .Q(p[24]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000098 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000170 ), .Q(p[25]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000097 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000171 ), .Q(p[26]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000096 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000015e ), .Q(p[27]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000095 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000015f ), .Q(p[28]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000094 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000160 ), .Q(p[29]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000093 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000161 ), .Q(p[30]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000092 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000162 ), .Q(p[31]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000091 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000163 ), .Q(p[32]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000090 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000164 ), .Q(p[33]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008f ( .C(clk), .CE(ce), .D(\blk00000001/sig00000165 ), .Q(p[34]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008e ( .C(clk), .CE(ce), .D(\blk00000001/sig00000166 ), .Q(p[35]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008d ( .C(clk), .CE(ce), .D(\blk00000001/sig00000167 ), .Q(p[36]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008c ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016c ), .Q(p[37]) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000008b ( .I0(\blk00000001/sig00000129 ), .I1(\blk00000001/sig0000012b ), .O(\blk00000001/sig00000064 ) ); MUXCY \blk00000001/blk0000008a ( .CI(\blk00000001/sig0000003b ), .DI(\blk00000001/sig00000129 ), .S(\blk00000001/sig00000064 ), .O(\blk00000001/sig00000061 ) ); XORCY \blk00000001/blk00000089 ( .CI(\blk00000001/sig0000003b ), .LI(\blk00000001/sig00000064 ), .O(\blk00000001/sig00000155 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000088 ( .I0(\blk00000001/sig0000012a ), .I1(\blk00000001/sig0000012c ), .O(\blk00000001/sig00000065 ) ); MUXCY \blk00000001/blk00000087 ( .CI(\blk00000001/sig00000061 ), .DI(\blk00000001/sig0000012a ), .S(\blk00000001/sig00000065 ), .O(\blk00000001/sig00000062 ) ); XORCY \blk00000001/blk00000086 ( .CI(\blk00000001/sig00000061 ), .LI(\blk00000001/sig00000065 ), .O(\blk00000001/sig00000156 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000085 ( .I0(\blk00000001/sig0000012a ), .I1(\blk00000001/sig0000012d ), .O(\blk00000001/sig00000066 ) ); MUXCY \blk00000001/blk00000084 ( .CI(\blk00000001/sig00000062 ), .DI(\blk00000001/sig0000012a ), .S(\blk00000001/sig00000066 ), .O(\blk00000001/sig00000063 ) ); XORCY \blk00000001/blk00000083 ( .CI(\blk00000001/sig00000062 ), .LI(\blk00000001/sig00000066 ), .O(\blk00000001/sig00000157 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000082 ( .I0(\blk00000001/sig0000012a ), .I1(\blk00000001/sig0000012e ), .O(\blk00000001/sig00000067 ) ); XORCY \blk00000001/blk00000081 ( .CI(\blk00000001/sig00000063 ), .LI(\blk00000001/sig00000067 ), .O(\blk00000001/sig00000158 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000080 ( .I0(\blk00000001/sig00000104 ), .I1(\blk00000001/sig00000116 ), .O(\blk00000001/sig0000004e ) ); MUXCY \blk00000001/blk0000007f ( .CI(\blk00000001/sig0000003b ), .DI(\blk00000001/sig00000104 ), .S(\blk00000001/sig0000004e ), .O(\blk00000001/sig0000003c ) ); XORCY \blk00000001/blk0000007e ( .CI(\blk00000001/sig0000003b ), .LI(\blk00000001/sig0000004e ), .O(\blk00000001/sig0000012f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000007d ( .I0(\blk00000001/sig00000105 ), .I1(\blk00000001/sig00000117 ), .O(\blk00000001/sig00000058 ) ); MUXCY \blk00000001/blk0000007c ( .CI(\blk00000001/sig0000003c ), .DI(\blk00000001/sig00000105 ), .S(\blk00000001/sig00000058 ), .O(\blk00000001/sig00000045 ) ); XORCY \blk00000001/blk0000007b ( .CI(\blk00000001/sig0000003c ), .LI(\blk00000001/sig00000058 ), .O(\blk00000001/sig00000139 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000007a ( .I0(\blk00000001/sig00000106 ), .I1(\blk00000001/sig00000121 ), .O(\blk00000001/sig00000059 ) ); MUXCY \blk00000001/blk00000079 ( .CI(\blk00000001/sig00000045 ), .DI(\blk00000001/sig00000106 ), .S(\blk00000001/sig00000059 ), .O(\blk00000001/sig00000046 ) ); XORCY \blk00000001/blk00000078 ( .CI(\blk00000001/sig00000045 ), .LI(\blk00000001/sig00000059 ), .O(\blk00000001/sig0000013a ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000077 ( .I0(\blk00000001/sig00000107 ), .I1(\blk00000001/sig00000122 ), .O(\blk00000001/sig0000005a ) ); MUXCY \blk00000001/blk00000076 ( .CI(\blk00000001/sig00000046 ), .DI(\blk00000001/sig00000107 ), .S(\blk00000001/sig0000005a ), .O(\blk00000001/sig00000047 ) ); XORCY \blk00000001/blk00000075 ( .CI(\blk00000001/sig00000046 ), .LI(\blk00000001/sig0000005a ), .O(\blk00000001/sig0000013b ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000074 ( .I0(\blk00000001/sig00000108 ), .I1(\blk00000001/sig00000123 ), .O(\blk00000001/sig0000005b ) ); MUXCY \blk00000001/blk00000073 ( .CI(\blk00000001/sig00000047 ), .DI(\blk00000001/sig00000108 ), .S(\blk00000001/sig0000005b ), .O(\blk00000001/sig00000048 ) ); XORCY \blk00000001/blk00000072 ( .CI(\blk00000001/sig00000047 ), .LI(\blk00000001/sig0000005b ), .O(\blk00000001/sig0000013c ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000071 ( .I0(\blk00000001/sig00000109 ), .I1(\blk00000001/sig00000124 ), .O(\blk00000001/sig0000005c ) ); MUXCY \blk00000001/blk00000070 ( .CI(\blk00000001/sig00000048 ), .DI(\blk00000001/sig00000109 ), .S(\blk00000001/sig0000005c ), .O(\blk00000001/sig00000049 ) ); XORCY \blk00000001/blk0000006f ( .CI(\blk00000001/sig00000048 ), .LI(\blk00000001/sig0000005c ), .O(\blk00000001/sig0000013d ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000006e ( .I0(\blk00000001/sig0000010a ), .I1(\blk00000001/sig00000125 ), .O(\blk00000001/sig0000005d ) ); MUXCY \blk00000001/blk0000006d ( .CI(\blk00000001/sig00000049 ), .DI(\blk00000001/sig0000010a ), .S(\blk00000001/sig0000005d ), .O(\blk00000001/sig0000004a ) ); XORCY \blk00000001/blk0000006c ( .CI(\blk00000001/sig00000049 ), .LI(\blk00000001/sig0000005d ), .O(\blk00000001/sig0000013e ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000006b ( .I0(\blk00000001/sig0000010b ), .I1(\blk00000001/sig00000126 ), .O(\blk00000001/sig0000005e ) ); MUXCY \blk00000001/blk0000006a ( .CI(\blk00000001/sig0000004a ), .DI(\blk00000001/sig0000010b ), .S(\blk00000001/sig0000005e ), .O(\blk00000001/sig0000004b ) ); XORCY \blk00000001/blk00000069 ( .CI(\blk00000001/sig0000004a ), .LI(\blk00000001/sig0000005e ), .O(\blk00000001/sig0000013f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000068 ( .I0(\blk00000001/sig0000010c ), .I1(\blk00000001/sig00000127 ), .O(\blk00000001/sig0000005f ) ); MUXCY \blk00000001/blk00000067 ( .CI(\blk00000001/sig0000004b ), .DI(\blk00000001/sig0000010c ), .S(\blk00000001/sig0000005f ), .O(\blk00000001/sig0000004c ) ); XORCY \blk00000001/blk00000066 ( .CI(\blk00000001/sig0000004b ), .LI(\blk00000001/sig0000005f ), .O(\blk00000001/sig00000140 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000065 ( .I0(\blk00000001/sig0000010d ), .I1(\blk00000001/sig00000128 ), .O(\blk00000001/sig00000060 ) ); MUXCY \blk00000001/blk00000064 ( .CI(\blk00000001/sig0000004c ), .DI(\blk00000001/sig0000010d ), .S(\blk00000001/sig00000060 ), .O(\blk00000001/sig0000004d ) ); XORCY \blk00000001/blk00000063 ( .CI(\blk00000001/sig0000004c ), .LI(\blk00000001/sig00000060 ), .O(\blk00000001/sig00000141 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000062 ( .I0(\blk00000001/sig0000010e ), .I1(\blk00000001/sig00000118 ), .O(\blk00000001/sig0000004f ) ); MUXCY \blk00000001/blk00000061 ( .CI(\blk00000001/sig0000004d ), .DI(\blk00000001/sig0000010e ), .S(\blk00000001/sig0000004f ), .O(\blk00000001/sig0000003d ) ); XORCY \blk00000001/blk00000060 ( .CI(\blk00000001/sig0000004d ), .LI(\blk00000001/sig0000004f ), .O(\blk00000001/sig00000130 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000005f ( .I0(\blk00000001/sig0000010f ), .I1(\blk00000001/sig00000119 ), .O(\blk00000001/sig00000050 ) ); MUXCY \blk00000001/blk0000005e ( .CI(\blk00000001/sig0000003d ), .DI(\blk00000001/sig0000010f ), .S(\blk00000001/sig00000050 ), .O(\blk00000001/sig0000003e ) ); XORCY \blk00000001/blk0000005d ( .CI(\blk00000001/sig0000003d ), .LI(\blk00000001/sig00000050 ), .O(\blk00000001/sig00000131 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000005c ( .I0(\blk00000001/sig00000110 ), .I1(\blk00000001/sig0000011a ), .O(\blk00000001/sig00000051 ) ); MUXCY \blk00000001/blk0000005b ( .CI(\blk00000001/sig0000003e ), .DI(\blk00000001/sig00000110 ), .S(\blk00000001/sig00000051 ), .O(\blk00000001/sig0000003f ) ); XORCY \blk00000001/blk0000005a ( .CI(\blk00000001/sig0000003e ), .LI(\blk00000001/sig00000051 ), .O(\blk00000001/sig00000132 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000059 ( .I0(\blk00000001/sig00000111 ), .I1(\blk00000001/sig0000011b ), .O(\blk00000001/sig00000052 ) ); MUXCY \blk00000001/blk00000058 ( .CI(\blk00000001/sig0000003f ), .DI(\blk00000001/sig00000111 ), .S(\blk00000001/sig00000052 ), .O(\blk00000001/sig00000040 ) ); XORCY \blk00000001/blk00000057 ( .CI(\blk00000001/sig0000003f ), .LI(\blk00000001/sig00000052 ), .O(\blk00000001/sig00000133 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000056 ( .I0(\blk00000001/sig00000112 ), .I1(\blk00000001/sig0000011c ), .O(\blk00000001/sig00000053 ) ); MUXCY \blk00000001/blk00000055 ( .CI(\blk00000001/sig00000040 ), .DI(\blk00000001/sig00000112 ), .S(\blk00000001/sig00000053 ), .O(\blk00000001/sig00000041 ) ); XORCY \blk00000001/blk00000054 ( .CI(\blk00000001/sig00000040 ), .LI(\blk00000001/sig00000053 ), .O(\blk00000001/sig00000134 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000053 ( .I0(\blk00000001/sig00000113 ), .I1(\blk00000001/sig0000011d ), .O(\blk00000001/sig00000054 ) ); MUXCY \blk00000001/blk00000052 ( .CI(\blk00000001/sig00000041 ), .DI(\blk00000001/sig00000113 ), .S(\blk00000001/sig00000054 ), .O(\blk00000001/sig00000042 ) ); XORCY \blk00000001/blk00000051 ( .CI(\blk00000001/sig00000041 ), .LI(\blk00000001/sig00000054 ), .O(\blk00000001/sig00000135 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000050 ( .I0(\blk00000001/sig00000114 ), .I1(\blk00000001/sig0000011e ), .O(\blk00000001/sig00000055 ) ); MUXCY \blk00000001/blk0000004f ( .CI(\blk00000001/sig00000042 ), .DI(\blk00000001/sig00000114 ), .S(\blk00000001/sig00000055 ), .O(\blk00000001/sig00000043 ) ); XORCY \blk00000001/blk0000004e ( .CI(\blk00000001/sig00000042 ), .LI(\blk00000001/sig00000055 ), .O(\blk00000001/sig00000136 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000004d ( .I0(\blk00000001/sig00000115 ), .I1(\blk00000001/sig0000011f ), .O(\blk00000001/sig00000056 ) ); MUXCY \blk00000001/blk0000004c ( .CI(\blk00000001/sig00000043 ), .DI(\blk00000001/sig00000115 ), .S(\blk00000001/sig00000056 ), .O(\blk00000001/sig00000044 ) ); XORCY \blk00000001/blk0000004b ( .CI(\blk00000001/sig00000043 ), .LI(\blk00000001/sig00000056 ), .O(\blk00000001/sig00000137 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000004a ( .I0(\blk00000001/sig00000115 ), .I1(\blk00000001/sig00000120 ), .O(\blk00000001/sig00000057 ) ); XORCY \blk00000001/blk00000049 ( .CI(\blk00000001/sig00000044 ), .LI(\blk00000001/sig00000057 ), .O(\blk00000001/sig00000138 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000048 ( .I0(\blk00000001/sig00000142 ), .I1(\blk00000001/sig000000a6 ), .O(\blk00000001/sig0000007e ) ); MUXCY \blk00000001/blk00000047 ( .CI(\blk00000001/sig0000003b ), .DI(\blk00000001/sig00000142 ), .S(\blk00000001/sig0000007e ), .O(\blk00000001/sig00000068 ) ); XORCY \blk00000001/blk00000046 ( .CI(\blk00000001/sig0000003b ), .LI(\blk00000001/sig0000007e ), .O(\blk00000001/sig0000015d ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000045 ( .I0(\blk00000001/sig00000143 ), .I1(\blk00000001/sig000000a7 ), .O(\blk00000001/sig00000089 ) ); MUXCY \blk00000001/blk00000044 ( .CI(\blk00000001/sig00000068 ), .DI(\blk00000001/sig00000143 ), .S(\blk00000001/sig00000089 ), .O(\blk00000001/sig00000073 ) ); XORCY \blk00000001/blk00000043 ( .CI(\blk00000001/sig00000068 ), .LI(\blk00000001/sig00000089 ), .O(\blk00000001/sig00000168 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000042 ( .I0(\blk00000001/sig0000014d ), .I1(\blk00000001/sig000000af ), .O(\blk00000001/sig0000008d ) ); MUXCY \blk00000001/blk00000041 ( .CI(\blk00000001/sig00000073 ), .DI(\blk00000001/sig0000014d ), .S(\blk00000001/sig0000008d ), .O(\blk00000001/sig00000076 ) ); XORCY \blk00000001/blk00000040 ( .CI(\blk00000001/sig00000073 ), .LI(\blk00000001/sig0000008d ), .O(\blk00000001/sig00000169 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000003f ( .I0(\blk00000001/sig0000014e ), .I1(\blk00000001/sig000000b0 ), .O(\blk00000001/sig0000008e ) ); MUXCY \blk00000001/blk0000003e ( .CI(\blk00000001/sig00000076 ), .DI(\blk00000001/sig0000014e ), .S(\blk00000001/sig0000008e ), .O(\blk00000001/sig00000077 ) ); XORCY \blk00000001/blk0000003d ( .CI(\blk00000001/sig00000076 ), .LI(\blk00000001/sig0000008e ), .O(\blk00000001/sig0000016a ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000003c ( .I0(\blk00000001/sig0000014f ), .I1(\blk00000001/sig000000b1 ), .O(\blk00000001/sig0000008f ) ); MUXCY \blk00000001/blk0000003b ( .CI(\blk00000001/sig00000077 ), .DI(\blk00000001/sig0000014f ), .S(\blk00000001/sig0000008f ), .O(\blk00000001/sig00000078 ) ); XORCY \blk00000001/blk0000003a ( .CI(\blk00000001/sig00000077 ), .LI(\blk00000001/sig0000008f ), .O(\blk00000001/sig0000016b ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000039 ( .I0(\blk00000001/sig00000150 ), .I1(\blk00000001/sig000000b2 ), .O(\blk00000001/sig00000090 ) ); MUXCY \blk00000001/blk00000038 ( .CI(\blk00000001/sig00000078 ), .DI(\blk00000001/sig00000150 ), .S(\blk00000001/sig00000090 ), .O(\blk00000001/sig00000079 ) ); XORCY \blk00000001/blk00000037 ( .CI(\blk00000001/sig00000078 ), .LI(\blk00000001/sig00000090 ), .O(\blk00000001/sig0000016d ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000036 ( .I0(\blk00000001/sig00000151 ), .I1(\blk00000001/sig000000b3 ), .O(\blk00000001/sig00000091 ) ); MUXCY \blk00000001/blk00000035 ( .CI(\blk00000001/sig00000079 ), .DI(\blk00000001/sig00000151 ), .S(\blk00000001/sig00000091 ), .O(\blk00000001/sig0000007a ) ); XORCY \blk00000001/blk00000034 ( .CI(\blk00000001/sig00000079 ), .LI(\blk00000001/sig00000091 ), .O(\blk00000001/sig0000016e ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000033 ( .I0(\blk00000001/sig00000152 ), .I1(\blk00000001/sig000000b4 ), .O(\blk00000001/sig00000092 ) ); MUXCY \blk00000001/blk00000032 ( .CI(\blk00000001/sig0000007a ), .DI(\blk00000001/sig00000152 ), .S(\blk00000001/sig00000092 ), .O(\blk00000001/sig0000007b ) ); XORCY \blk00000001/blk00000031 ( .CI(\blk00000001/sig0000007a ), .LI(\blk00000001/sig00000092 ), .O(\blk00000001/sig0000016f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000030 ( .I0(\blk00000001/sig00000153 ), .I1(\blk00000001/sig000000b5 ), .O(\blk00000001/sig00000093 ) ); MUXCY \blk00000001/blk0000002f ( .CI(\blk00000001/sig0000007b ), .DI(\blk00000001/sig00000153 ), .S(\blk00000001/sig00000093 ), .O(\blk00000001/sig0000007c ) ); XORCY \blk00000001/blk0000002e ( .CI(\blk00000001/sig0000007b ), .LI(\blk00000001/sig00000093 ), .O(\blk00000001/sig00000170 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000002d ( .I0(\blk00000001/sig00000154 ), .I1(\blk00000001/sig000000b6 ), .O(\blk00000001/sig00000094 ) ); MUXCY \blk00000001/blk0000002c ( .CI(\blk00000001/sig0000007c ), .DI(\blk00000001/sig00000154 ), .S(\blk00000001/sig00000094 ), .O(\blk00000001/sig0000007d ) ); XORCY \blk00000001/blk0000002b ( .CI(\blk00000001/sig0000007c ), .LI(\blk00000001/sig00000094 ), .O(\blk00000001/sig00000171 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000002a ( .I0(\blk00000001/sig00000144 ), .I1(\blk00000001/sig000000a8 ), .O(\blk00000001/sig0000007f ) ); MUXCY \blk00000001/blk00000029 ( .CI(\blk00000001/sig0000007d ), .DI(\blk00000001/sig00000144 ), .S(\blk00000001/sig0000007f ), .O(\blk00000001/sig00000069 ) ); XORCY \blk00000001/blk00000028 ( .CI(\blk00000001/sig0000007d ), .LI(\blk00000001/sig0000007f ), .O(\blk00000001/sig0000015e ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000027 ( .I0(\blk00000001/sig00000145 ), .I1(\blk00000001/sig000000a9 ), .O(\blk00000001/sig00000080 ) ); MUXCY \blk00000001/blk00000026 ( .CI(\blk00000001/sig00000069 ), .DI(\blk00000001/sig00000145 ), .S(\blk00000001/sig00000080 ), .O(\blk00000001/sig0000006a ) ); XORCY \blk00000001/blk00000025 ( .CI(\blk00000001/sig00000069 ), .LI(\blk00000001/sig00000080 ), .O(\blk00000001/sig0000015f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000024 ( .I0(\blk00000001/sig00000146 ), .I1(\blk00000001/sig000000aa ), .O(\blk00000001/sig00000081 ) ); MUXCY \blk00000001/blk00000023 ( .CI(\blk00000001/sig0000006a ), .DI(\blk00000001/sig00000146 ), .S(\blk00000001/sig00000081 ), .O(\blk00000001/sig0000006b ) ); XORCY \blk00000001/blk00000022 ( .CI(\blk00000001/sig0000006a ), .LI(\blk00000001/sig00000081 ), .O(\blk00000001/sig00000160 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000021 ( .I0(\blk00000001/sig00000147 ), .I1(\blk00000001/sig000000ab ), .O(\blk00000001/sig00000082 ) ); MUXCY \blk00000001/blk00000020 ( .CI(\blk00000001/sig0000006b ), .DI(\blk00000001/sig00000147 ), .S(\blk00000001/sig00000082 ), .O(\blk00000001/sig0000006c ) ); XORCY \blk00000001/blk0000001f ( .CI(\blk00000001/sig0000006b ), .LI(\blk00000001/sig00000082 ), .O(\blk00000001/sig00000161 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000001e ( .I0(\blk00000001/sig00000148 ), .I1(\blk00000001/sig000000ac ), .O(\blk00000001/sig00000083 ) ); MUXCY \blk00000001/blk0000001d ( .CI(\blk00000001/sig0000006c ), .DI(\blk00000001/sig00000148 ), .S(\blk00000001/sig00000083 ), .O(\blk00000001/sig0000006d ) ); XORCY \blk00000001/blk0000001c ( .CI(\blk00000001/sig0000006c ), .LI(\blk00000001/sig00000083 ), .O(\blk00000001/sig00000162 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000001b ( .I0(\blk00000001/sig00000149 ), .I1(\blk00000001/sig000000ad ), .O(\blk00000001/sig00000084 ) ); MUXCY \blk00000001/blk0000001a ( .CI(\blk00000001/sig0000006d ), .DI(\blk00000001/sig00000149 ), .S(\blk00000001/sig00000084 ), .O(\blk00000001/sig0000006e ) ); XORCY \blk00000001/blk00000019 ( .CI(\blk00000001/sig0000006d ), .LI(\blk00000001/sig00000084 ), .O(\blk00000001/sig00000163 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000018 ( .I0(\blk00000001/sig0000014a ), .I1(\blk00000001/sig000000ae ), .O(\blk00000001/sig00000085 ) ); MUXCY \blk00000001/blk00000017 ( .CI(\blk00000001/sig0000006e ), .DI(\blk00000001/sig0000014a ), .S(\blk00000001/sig00000085 ), .O(\blk00000001/sig0000006f ) ); XORCY \blk00000001/blk00000016 ( .CI(\blk00000001/sig0000006e ), .LI(\blk00000001/sig00000085 ), .O(\blk00000001/sig00000164 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000015 ( .I0(\blk00000001/sig0000014b ), .I1(\blk00000001/sig00000159 ), .O(\blk00000001/sig00000086 ) ); MUXCY \blk00000001/blk00000014 ( .CI(\blk00000001/sig0000006f ), .DI(\blk00000001/sig0000014b ), .S(\blk00000001/sig00000086 ), .O(\blk00000001/sig00000070 ) ); XORCY \blk00000001/blk00000013 ( .CI(\blk00000001/sig0000006f ), .LI(\blk00000001/sig00000086 ), .O(\blk00000001/sig00000165 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000012 ( .I0(\blk00000001/sig0000015a ), .I1(\blk00000001/sig0000014c ), .O(\blk00000001/sig00000087 ) ); MUXCY \blk00000001/blk00000011 ( .CI(\blk00000001/sig00000070 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig00000087 ), .O(\blk00000001/sig00000071 ) ); XORCY \blk00000001/blk00000010 ( .CI(\blk00000001/sig00000070 ), .LI(\blk00000001/sig00000087 ), .O(\blk00000001/sig00000166 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000000f ( .I0(\blk00000001/sig0000015b ), .I1(\blk00000001/sig0000014c ), .O(\blk00000001/sig00000088 ) ); MUXCY \blk00000001/blk0000000e ( .CI(\blk00000001/sig00000071 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig00000088 ), .O(\blk00000001/sig00000072 ) ); XORCY \blk00000001/blk0000000d ( .CI(\blk00000001/sig00000071 ), .LI(\blk00000001/sig00000088 ), .O(\blk00000001/sig00000167 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000000c ( .I0(\blk00000001/sig0000014c ), .I1(\blk00000001/sig0000015c ), .O(\blk00000001/sig0000008a ) ); MUXCY \blk00000001/blk0000000b ( .CI(\blk00000001/sig00000072 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig0000008a ), .O(\blk00000001/sig00000074 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000000a ( .I0(\blk00000001/sig0000014c ), .I1(\blk00000001/sig0000015c ), .O(\blk00000001/sig0000008b ) ); MUXCY \blk00000001/blk00000009 ( .CI(\blk00000001/sig00000074 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig0000008b ), .O(\blk00000001/sig00000075 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000008 ( .I0(\blk00000001/sig0000014c ), .I1(\blk00000001/sig0000015c ), .O(\blk00000001/sig0000008c ) ); XORCY \blk00000001/blk00000007 ( .CI(\blk00000001/sig00000075 ), .LI(\blk00000001/sig0000008c ), .O(\blk00000001/sig0000016c ) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000006 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({\blk00000001/sig0000003b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({\blk00000001/sig0000003b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000006_P<35>_UNCONNECTED , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , \blk00000001/sig000000cf , \blk00000001/sig000000ce , \blk00000001/sig000000cc , \blk00000001/sig000000cb , \blk00000001/sig000000ca , \blk00000001/sig000000c9 , \blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , \blk00000001/sig000000c5 , \blk00000001/sig000000c4 , \blk00000001/sig000000c3 , \blk00000001/sig000000c1 , \blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc , \blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , \blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000cd , \blk00000001/sig000000c2 , \blk00000001/sig000000b7 }), .BCOUT({\NLW_blk00000001/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<0>_UNCONNECTED }) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000005 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({\blk00000001/sig0000003b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[17]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000005_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000ec , \blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 , \blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000da }), .BCOUT({\NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED }) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000004 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[17]}), .B({\blk00000001/sig0000003b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED , \blk00000001/sig000000f6 , \blk00000001/sig000000f5 , \blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig000000f2 , \blk00000001/sig000000f1 , \blk00000001/sig000000f0 , \blk00000001/sig000000ef , \blk00000001/sig000000ee , \blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd , \blk00000001/sig000000fc , \blk00000001/sig000000fb , \blk00000001/sig000000fa , \blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000ed }), .BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000003 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[17]}), .B({b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[17]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<14>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<13>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<12>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<11>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<10>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<9>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<8>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<7>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<6>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<5>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<4>_UNCONNECTED , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 }), .BCOUT({\NLW_blk00000001/blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<0>_UNCONNECTED }) ); GND \blk00000001/blk00000002 ( .G(\blk00000001/sig0000003b ) ); // synthesis translate_on endmodule // synthesis translate_off `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif // synthesis translate_on
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_1_V `define SKY130_FD_SC_HD__DLYMETAL6S2S_1_V /* * dlymetal6s2s: 6-inverter delay with output from 2nd stage on * horizontal route. * * Verilog wrapper for dlymetal6s2s with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__dlymetal6s2s.v" `ifdef USE_POWER_PINS /******************************************************/ `celldefine module sky130_fd_sc_hd__dlymetal6s2s_1 ( X , A , VPWR, VGND, VPB , VNB ); output X ; input A ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hd__dlymetal6s2s base ( .X(X), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*****************************************************/ `else // If not USE_POWER_PINS /*****************************************************/ `celldefine module sky130_fd_sc_hd__dlymetal6s2s_1 ( X, A ); output X; input A; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hd__dlymetal6s2s base ( .X(X), .A(A) ); endmodule `endcelldefine /*******************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V `define SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V /* * sedfxtp: Scan delay flop, data enable, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v" `include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v" `celldefine module sky130_fd_sc_ms__sedfxtp ( Q , CLK , D , DE , SCD , SCE , VPWR, VGND, VPB , VNB ); // Module ports output Q ; input CLK ; input D ; input DE ; input SCD ; input SCE ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire buf_Q ; wire mux_out; wire de_d ; // Delay Name Output Other arguments sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE ); sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE ); sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND); buf buf0 (Q , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V
// // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // // // // // Ports: // Name I/O size props // m_near_mem_io_addr_base O 64 const // m_near_mem_io_addr_size O 64 const // m_near_mem_io_addr_lim O 64 const // m_plic_addr_base O 64 const // m_plic_addr_size O 64 const // m_plic_addr_lim O 64 const // m_uart0_addr_base O 64 const // m_uart0_addr_size O 64 const // m_uart0_addr_lim O 64 const // m_boot_rom_addr_base O 64 const // m_boot_rom_addr_size O 64 const // m_boot_rom_addr_lim O 64 const // m_mem0_controller_addr_base O 64 const // m_mem0_controller_addr_size O 64 const // m_mem0_controller_addr_lim O 64 const // m_tcm_addr_base O 64 const // m_tcm_addr_size O 64 const // m_tcm_addr_lim O 64 const // m_is_mem_addr O 1 // m_is_IO_addr O 1 // m_is_near_mem_IO_addr O 1 // m_pc_reset_value O 64 const // m_mtvec_reset_value O 64 const // m_nmivec_reset_value O 64 const // CLK I 1 unused // RST_N I 1 unused // m_is_mem_addr_addr I 64 // m_is_IO_addr_addr I 64 // m_is_near_mem_IO_addr_addr I 64 // // Combinational paths from inputs to outputs: // m_is_mem_addr_addr -> m_is_mem_addr // m_is_IO_addr_addr -> m_is_IO_addr // m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkSoC_Map(CLK, RST_N, m_near_mem_io_addr_base, m_near_mem_io_addr_size, m_near_mem_io_addr_lim, m_plic_addr_base, m_plic_addr_size, m_plic_addr_lim, m_uart0_addr_base, m_uart0_addr_size, m_uart0_addr_lim, m_boot_rom_addr_base, m_boot_rom_addr_size, m_boot_rom_addr_lim, m_mem0_controller_addr_base, m_mem0_controller_addr_size, m_mem0_controller_addr_lim, m_tcm_addr_base, m_tcm_addr_size, m_tcm_addr_lim, m_is_mem_addr_addr, m_is_mem_addr, m_is_IO_addr_addr, m_is_IO_addr, m_is_near_mem_IO_addr_addr, m_is_near_mem_IO_addr, m_pc_reset_value, m_mtvec_reset_value, m_nmivec_reset_value); input CLK; input RST_N; // value method m_near_mem_io_addr_base output [63 : 0] m_near_mem_io_addr_base; // value method m_near_mem_io_addr_size output [63 : 0] m_near_mem_io_addr_size; // value method m_near_mem_io_addr_lim output [63 : 0] m_near_mem_io_addr_lim; // value method m_plic_addr_base output [63 : 0] m_plic_addr_base; // value method m_plic_addr_size output [63 : 0] m_plic_addr_size; // value method m_plic_addr_lim output [63 : 0] m_plic_addr_lim; // value method m_uart0_addr_base output [63 : 0] m_uart0_addr_base; // value method m_uart0_addr_size output [63 : 0] m_uart0_addr_size; // value method m_uart0_addr_lim output [63 : 0] m_uart0_addr_lim; // value method m_boot_rom_addr_base output [63 : 0] m_boot_rom_addr_base; // value method m_boot_rom_addr_size output [63 : 0] m_boot_rom_addr_size; // value method m_boot_rom_addr_lim output [63 : 0] m_boot_rom_addr_lim; // value method m_mem0_controller_addr_base output [63 : 0] m_mem0_controller_addr_base; // value method m_mem0_controller_addr_size output [63 : 0] m_mem0_controller_addr_size; // value method m_mem0_controller_addr_lim output [63 : 0] m_mem0_controller_addr_lim; // value method m_tcm_addr_base output [63 : 0] m_tcm_addr_base; // value method m_tcm_addr_size output [63 : 0] m_tcm_addr_size; // value method m_tcm_addr_lim output [63 : 0] m_tcm_addr_lim; // value method m_is_mem_addr input [63 : 0] m_is_mem_addr_addr; output m_is_mem_addr; // value method m_is_IO_addr input [63 : 0] m_is_IO_addr_addr; output m_is_IO_addr; // value method m_is_near_mem_IO_addr input [63 : 0] m_is_near_mem_IO_addr_addr; output m_is_near_mem_IO_addr; // value method m_pc_reset_value output [63 : 0] m_pc_reset_value; // value method m_mtvec_reset_value output [63 : 0] m_mtvec_reset_value; // value method m_nmivec_reset_value output [63 : 0] m_nmivec_reset_value; // signals for module outputs wire [63 : 0] m_boot_rom_addr_base, m_boot_rom_addr_lim, m_boot_rom_addr_size, m_mem0_controller_addr_base, m_mem0_controller_addr_lim, m_mem0_controller_addr_size, m_mtvec_reset_value, m_near_mem_io_addr_base, m_near_mem_io_addr_lim, m_near_mem_io_addr_size, m_nmivec_reset_value, m_pc_reset_value, m_plic_addr_base, m_plic_addr_lim, m_plic_addr_size, m_tcm_addr_base, m_tcm_addr_lim, m_tcm_addr_size, m_uart0_addr_base, m_uart0_addr_lim, m_uart0_addr_size; wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; // value method m_near_mem_io_addr_base assign m_near_mem_io_addr_base = 64'h0000000002000000 ; // value method m_near_mem_io_addr_size assign m_near_mem_io_addr_size = 64'h000000000000C000 ; // value method m_near_mem_io_addr_lim assign m_near_mem_io_addr_lim = 64'd33603584 ; // value method m_plic_addr_base assign m_plic_addr_base = 64'h000000000C000000 ; // value method m_plic_addr_size assign m_plic_addr_size = 64'h0000000000400000 ; // value method m_plic_addr_lim assign m_plic_addr_lim = 64'd205520896 ; // value method m_uart0_addr_base assign m_uart0_addr_base = 64'h00000000C0000000 ; // value method m_uart0_addr_size assign m_uart0_addr_size = 64'h0000000000000080 ; // value method m_uart0_addr_lim assign m_uart0_addr_lim = 64'h00000000C0000080 ; // value method m_boot_rom_addr_base assign m_boot_rom_addr_base = 64'h0000000000001000 ; // value method m_boot_rom_addr_size assign m_boot_rom_addr_size = 64'h0000000000001000 ; // value method m_boot_rom_addr_lim assign m_boot_rom_addr_lim = 64'd8192 ; // value method m_mem0_controller_addr_base assign m_mem0_controller_addr_base = 64'h0000000080000000 ; // value method m_mem0_controller_addr_size assign m_mem0_controller_addr_size = 64'h0000000010000000 ; // value method m_mem0_controller_addr_lim assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; // value method m_tcm_addr_base assign m_tcm_addr_base = 64'h0 ; // value method m_tcm_addr_size assign m_tcm_addr_size = 64'd0 ; // value method m_tcm_addr_lim assign m_tcm_addr_lim = 64'd0 ; // value method m_is_mem_addr assign m_is_mem_addr = m_is_mem_addr_addr >= 64'h0000000000001000 && m_is_mem_addr_addr < 64'd8192 \|\| m_is_mem_addr_addr >= 64'h0000000080000000 && m_is_mem_addr_addr < 64'h0000000090000000 ; // value method m_is_IO_addr assign m_is_IO_addr = m_is_IO_addr_addr >= 64'h0000000002000000 && m_is_IO_addr_addr < 64'd33603584 \|\| m_is_IO_addr_addr >= 64'h000000000C000000 && m_is_IO_addr_addr < 64'd205520896 \|\| m_is_IO_addr_addr >= 64'h00000000C0000000 && m_is_IO_addr_addr < 64'h00000000C0000080 ; // value method m_is_near_mem_IO_addr assign m_is_near_mem_IO_addr = m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && m_is_near_mem_IO_addr_addr < 64'd33603584 ; // value method m_pc_reset_value assign m_pc_reset_value = 64'h0000000000001000 ; // value method m_mtvec_reset_value assign m_mtvec_reset_value = 64'h0000000000001000 ; // value method m_nmivec_reset_value assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; endmodule // mkSoC_Map
//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module acl_fp_tan_s5 ( enable, clock, dataa, result); input enable; input clock; input [31:0] dataa; output [31:0] result; wire [31:0] sub_wire0; wire [31:0] result = sub_wire0[31:0]; fp_tan_s5 inst( .en (enable), .clk (clock), .a (dataa), .q (sub_wire0), .areset(1'b0)); endmodule
/------------------------------------------------------------------------------ This code was generated by Spiral Multiplier Block Generator, www.spiral.net * Copyright (c) 2006, Carnegie Mellon University * All rights reserved. * The code is distributed under a BSD style license * (see http://www.opensource.org/licenses/bsd-license.php) ------------------------------------------------------------------------------ / /* ./multBlockGen.pl 8789 -fractionalBits 0*/ module multiplier_block ( i_data0, o_data0 ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; //Multipliers: wire [31:0] w1, w512, w513, w4, w517, w8272, w8789; assign w1 = i_data0; assign w4 = w1 << 2; assign w512 = w1 << 9; assign w513 = w1 + w512; assign w517 = w513 + w4; assign w8272 = w517 << 4; assign w8789 = w517 + w8272; assign o_data0 = w8789; //multiplier_block area estimate = 4979.62092201029; endmodule //multiplier_block module surround_with_regs( i_data0, o_data0, clk ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; reg [31:0] o_data0; input clk; reg [31:0] i_data0_reg; wire [30:0] o_data0_from_mult; always @(posedge clk) begin i_data0_reg <= i_data0; o_data0 <= o_data0_from_mult; end multiplier_block mult_blk( .i_data0(i_data0_reg), .o_data0(o_data0_from_mult) ); endmodule
//*************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //************************************************************************* // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //************************************************************************* `timescale 1 ps / 1 ps module mig_7series_v1_9_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1 ) ( input rst, input clk, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLKROW_WIDTH-1:0] mux_address, input [nCK_PER_CLKBANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTHnCS_PER_RANKnCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2nCK_PER_CLKDQ_WIDTH-1:0] mux_wrdata, input [2nCK_PER_CLK(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2nCK_PER_CLKDQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTHnCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4v)+1(CK_BYTE_MAP[(v8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4v)+1(CK_BYTE_MAP[(v8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4v+1(CK_BYTE_MAP[(v8)+:4])] = 1'b1; end end endfunction function [(2CK_WIDTH8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g28)+:8] = (ck_byte_map[(g8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g2)+1)8)+:8] = (ck_byte_map[((g8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12DQ_PER_DQS-1:0], DATA16_MAP[12DQ_PER_DQS-1:0], DATA15_MAP[12DQ_PER_DQS-1:0], DATA14_MAP[12DQ_PER_DQS-1:0], DATA13_MAP[12DQ_PER_DQS-1:0], DATA12_MAP[12DQ_PER_DQS-1:0], DATA11_MAP[12DQ_PER_DQS-1:0], DATA10_MAP[12DQ_PER_DQS-1:0], DATA9_MAP[12DQ_PER_DQS-1:0], DATA8_MAP[12DQ_PER_DQS-1:0], DATA7_MAP[12DQ_PER_DQS-1:0], DATA6_MAP[12DQ_PER_DQS-1:0], DATA5_MAP[12DQ_PER_DQS-1:0], DATA4_MAP[12DQ_PER_DQS-1:0], DATA3_MAP[12DQ_PER_DQS-1:0], DATA2_MAP[12DQ_PER_DQS-1:0], DATA1_MAP[12DQ_PER_DQS-1:0], DATA0_MAP[12DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48data_mask_in[(12z+8)+:3] + 12data_mask_in[(12z+4)+:2] + data_mask_in[12z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //************************************************************************ // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //************************************************************************* //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) \|\| (tCK >= 3333)) ? "FALSE" : "TRUE"; //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK > 2500 ? "DIV2": "NONE"; localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? ((tCK > 2500) ? 8 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE10-1:0] mem_dq_in; wire [HIGHEST_LANE12-1:0] mem_dq_out; wire [HIGHEST_LANE12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTHnCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE80-1:0] phy_din; wire [HIGHEST_LANE80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; ( keep = "true", max_fanout = 3 ) wire phy_ctl_wr_of / synthesis syn_maxfan = 1 /; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; //************************************************************************ // Auxiliary output steering //************************************************************************* // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //************************************************************************* // Read data bit steering //************************************************************************* // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTHj + i] = phy_din[(320FULL_DATA_MAP[(12i+8)+:3]+ 80FULL_DATA_MAP[(12i+4)+:2] + 8FULL_DATA_MAP[12i+:4]) + j]; end end endgenerate //************************************************************************ // Control/address //************************************************************************* assign out_cas_n = mem_dq_out[48CAS_MAP[10:8] + 12CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320CAS_MAP[10:8] + 80CAS_MAP[5:4] + 8CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320CAS_MAP[10:8] + 80CAS_MAP[5:4] + 8(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48RAS_MAP[10:8] + 12RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320RAS_MAP[10:8] + 80RAS_MAP[5:4] + 8RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320RAS_MAP[10:8] + 80RAS_MAP[5:4] + 8(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48WE_MAP[10:8] + 12WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320WE_MAP[10:8] + 80WE_MAP[5:4] + 8WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320WE_MAP[10:8] + 80WE_MAP[5:4] + 8(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48PARITY_MAP[10:8] + 12PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320PARITY_MAP[10:8] + 80PARITY_MAP[5:4] + 8PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320PARITY_MAP[10:8] + 80PARITY_MAP[5:4] + 8(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //*************************************************************** generate genvar m, n,x; //************************************************************* // Control/address (multi-bit) buses //*************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48ADDR_MAP[(12m+8)+:3] + 12ADDR_MAP[(12m+4)+:2] + ADDR_MAP[12m+:4]]; if (ADDR_MAP[12m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320ADDR_MAP[(12m+8)+:3] + 80ADDR_MAP[(12m+4)+:2] + 8ADDR_MAP[12m+:4] + n] = mux_address[ROW_WIDTH(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320ADDR_MAP[(12m+8)+:3] + 80ADDR_MAP[(12m+4)+:2] + 8(ADDR_MAP[12m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48BANK_MAP[(12m+8)+:3] + 12BANK_MAP[(12m+4)+:2] + BANK_MAP[12m+:4]]; if (BANK_MAP[12m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320BANK_MAP[(12m+8)+:3] + 80BANK_MAP[(12m+4)+:2] + 8BANK_MAP[12m+:4] + n] = mux_bank[BANK_WIDTH(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320BANK_MAP[(12m+8)+:3] + 80BANK_MAP[(12m+4)+:2] + 8(BANK_MAP[12m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTHnCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48CS_MAP[(12m+8)+:3] + 12CS_MAP[(12m+4)+:2] + CS_MAP[12m+:4]]; if (CS_MAP[12m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320CS_MAP[(12m+8)+:3] + 80CS_MAP[(12m+4)+:2] + 8CS_MAP[12m+:4] + n] = mux_cs_n[CS_WIDTHnCS_PER_RANK(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320CS_MAP[(12m+8)+:3] + 80CS_MAP[(12m+4)+:2] + 8(CS_MAP[12m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTHnCS_PER_RANK(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTHnCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(xODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(xODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((xODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48ODT_MAP[(12m+8)+:3] + 12ODT_MAP[(12m+4)+:2] + ODT_MAP[12m+:4]]; if (ODT_MAP[12m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320ODT_MAP[(12m+8)+:3] + 80ODT_MAP[(12m+4)+:2] + 8ODT_MAP[12m+:4] + n] = mux_odt_remap[ODT_WIDTH(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320ODT_MAP[(12m+8)+:3] + 80ODT_MAP[(12m+4)+:2] + 8(ODT_MAP[12m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTHnCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(xCKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48CKE_MAP[(12m+8)+:3] + 12CKE_MAP[(12m+4)+:2] + CKE_MAP[12m+:4]]; if (CKE_MAP[12m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320CKE_MAP[(12m+8)+:3] + 80CKE_MAP[(12m+4)+:2] + 8CKE_MAP[12m+:4] + n] = mux_cke_remap[CKE_WIDTH(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320CKE_MAP[(12m+8)+:3] + 80CKE_MAP[(12m+4)+:2] + 8(CKE_MAP[12m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH(n/PHASE_DIV) + m]; end end end end //*************************************************************** // Data mask //*************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48FULL_MASK_MAP[(12m+8)+:3] + 12FULL_MASK_MAP[(12m+4)+:2] + FULL_MASK_MAP[12m+:4]]; assign ts_dm[m] = mem_dq_ts[48FULL_MASK_MAP[(12m+8)+:3] + 12FULL_MASK_MAP[(12m+4)+:2] + FULL_MASK_MAP[12m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320FULL_MASK_MAP[(12m+8)+:3] + 80FULL_MASK_MAP[(12m+4)+:2] + 8FULL_MASK_MAP[12m+:4] + n] = mux_wrdata_mask[DM_WIDTHn + m]; end end end //************************************************************** // Input and output DQ //*************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40FULL_DATA_MAP[(12m+8)+:3] + 10FULL_DATA_MAP[(12m+4)+:2] + FULL_DATA_MAP[12m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48FULL_DATA_MAP[(12m+8)+:3] + 12FULL_DATA_MAP[(12m+4)+:2] + FULL_DATA_MAP[12m+:4]]; assign ts_dq[m] = mem_dq_ts[48FULL_DATA_MAP[(12m+8)+:3] + 12FULL_DATA_MAP[(12m+4)+:2] + FULL_DATA_MAP[12m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320FULL_DATA_MAP[(12m+8)+:3] + 80FULL_DATA_MAP[(12m+4)+:2] + 8FULL_DATA_MAP[12m+:4] + n] = mux_wrdata[DQ_WIDTHn + m]; end end //*************************************************************** // Input and output DQS //*************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4DQS_BYTE_MAP[(8m+4)+:3] + DQS_BYTE_MAP[(8m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4DQS_BYTE_MAP[(8m+4)+:3] + DQS_BYTE_MAP[(8m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4DQS_BYTE_MAP[(8m+4)+:3] + DQS_BYTE_MAP[(8m)+:2]]; end endgenerate //************************************************************************ // Memory I/F output and I/O buffer instantiation //************************************************************************* // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTHnCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") \|\| (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); end end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v1_9_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v1_9_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v1_9_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //************************************************************************ // Hard PHY instantiation //************************************************************************* assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v1_9_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP) ,.PHY_1_IODELAY_GRP (IODELAY_GRP) ,.PHY_2_IODELAY_GRP (IODELAY_GRP) ,.BANK_TYPE (BANK_TYPE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_MS__A41OI_1_V `define SKY130_FD_SC_MS__A41OI_1_V /* * a41oi: 4-input AND into first input of 2-input NOR. * * Y = !((A1 & A2 & A3 & A4) \| B1) * * Verilog wrapper for a41oi with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_ms__a41oi.v" `ifdef USE_POWER_PINS /******************************************************/ `celldefine module sky130_fd_sc_ms__a41oi_1 ( Y , A1 , A2 , A3 , A4 , B1 , VPWR, VGND, VPB , VNB ); output Y ; input A1 ; input A2 ; input A3 ; input A4 ; input B1 ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_ms__a41oi base ( .Y(Y), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*****************************************************/ `else // If not USE_POWER_PINS /*****************************************************/ `celldefine module sky130_fd_sc_ms__a41oi_1 ( Y , A1, A2, A3, A4, B1 ); output Y ; input A1; input A2; input A3; input A4; input B1; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_ms__a41oi base ( .Y(Y), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1) ); endmodule `endcelldefine /*******************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_MS__A41OI_1_V
`default_nettype none //Parallel Adder - non pipeline module mul4( input [3 : 0] iSOURCE0, input [3 : 0] iSOURCE1, output [7 : 0] oOUTPUT); assign oOUTPUT = ((iSOURCE0[0])? iSOURCE1 : 7'h00) + ((iSOURCE0[1])? iSOURCE1 << 1 : 7'h00) + ((iSOURCE0[2])? iSOURCE1 << 2 : 7'h00) + ((iSOURCE0[3])? iSOURCE1 << 3 : 7'h00); endmodule //Parallel Adder - non pipeline module mul32( input [31 : 0] iSOURCE0, input [31 : 0] iSOURCE1, output [63 : 0] oDATA, output oHSF, output oHOF, output oHCF, output oHPF, output oHZF, output oLSF, output oLOF, output oLCF, output oLPF, output oLZF); wire [63:0] w_tmp_out; assign w_tmp_out = ((iSOURCE0[0])? iSOURCE1 : 64'h00) + ((iSOURCE0[1])? iSOURCE1 << 1 : 64'h00) + ((iSOURCE0[2])? iSOURCE1 << 2 : 64'h00) + ((iSOURCE0[3])? iSOURCE1 << 3 : 64'h00) +((iSOURCE0[4])? iSOURCE1 << 4 : 64'h00) + ((iSOURCE0[5])? iSOURCE1 << 5 : 64'h00) + ((iSOURCE0[6])? iSOURCE1 << 6 : 64'h00) + ((iSOURCE0[7])? iSOURCE1 << 7 : 64'h00) +((iSOURCE0[8])? iSOURCE1 << 8 : 64'h00) + ((iSOURCE0[9])? iSOURCE1 << 9 : 64'h00) + ((iSOURCE0[10])? iSOURCE1 << 10 : 64'h00) + ((iSOURCE0[11])? iSOURCE1 << 11 : 64'h00) +((iSOURCE0[12])? iSOURCE1 << 12 : 64'h00) + ((iSOURCE0[13])? iSOURCE1 << 13 : 64'h00) + ((iSOURCE0[14])? iSOURCE1 << 14 : 64'h00) + ((iSOURCE0[15])? iSOURCE1 << 15 : 64'h00) +((iSOURCE0[16])? iSOURCE1 << 16 : 64'h00) + ((iSOURCE0[17])? iSOURCE1 << 17 : 64'h00) + ((iSOURCE0[18])? iSOURCE1 << 18 : 64'h00) + ((iSOURCE0[19])? iSOURCE1 << 19 : 64'h00) +((iSOURCE0[20])? iSOURCE1 << 20 : 64'h00) + ((iSOURCE0[21])? iSOURCE1 << 21 : 64'h00) + ((iSOURCE0[22])? iSOURCE1 << 22 : 64'h00) + ((iSOURCE0[23])? iSOURCE1 << 23 : 64'h00) +((iSOURCE0[24])? iSOURCE1 << 24 : 64'h00) + ((iSOURCE0[25])? iSOURCE1 << 25 : 64'h00) + ((iSOURCE0[26])? iSOURCE1 << 26 : 64'h00) + ((iSOURCE0[27])? iSOURCE1 << 27 : 64'h00) +((iSOURCE0[28])? iSOURCE1 << 28 : 64'h00) + ((iSOURCE0[29])? iSOURCE1 << 29 : 64'h00) + ((iSOURCE0[30])? iSOURCE1 << 30 : 64'h00) + ((iSOURCE0[31])? iSOURCE1 << 31 : 64'h00); /************************************** Assign **************************************/ assign oDATA = w_tmp_out; assign oHSF = w_tmp_out[31]; assign oHOF = w_tmp_out[32] ^ w_tmp_out[31]; assign oHCF = w_tmp_out[32]; assign oHPF = w_tmp_out[0]; assign oHZF = (w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0; assign oLSF = w_tmp_out[32]; assign oLOF = w_tmp_out[63]; assign oLCF = 1'b0; assign oLPF = w_tmp_out[32]; assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; endmodule `default_nettype wire
// CONFIG: // NUM_COEFF = 51 // PIPLINED = 0 module fir ( clk, reset, clk_ena, i_valid, i_in, o_valid, o_out ); // Data Width parameter dw = 18; //Data input/output bits // Number of filter coefficients parameter N = 51; parameter N_UNIQ = 26; // ciel(N/2) assuming symmetric filter coefficients //Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers localparam N_VALID_REGS = 52; input clk; input reset; input clk_ena; input i_valid; input [dw-1:0] i_in; // signed output o_valid; output [dw-1:0] o_out; // signed // Data Width dervied parameters localparam dw_add_int = 18; //Internal adder precision bits localparam dw_mult_int = 36; //Internal multiplier precision bits localparam scale_factor = 17; //Multiplier normalization shift amount // Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders localparam N_INPUT_REGS = 51; // Debug // initial begin // $display ("Data Width: %d", dw); // $display ("Data Width Add Internal: %d", dw_add_int); // $display ("Data Width Mult Internal: %d", dw_mult_int); // $display ("Scale Factor: %d", scale_factor); // end reg [dw-1:0] COEFFICIENT_0; reg [dw-1:0] COEFFICIENT_1; reg [dw-1:0] COEFFICIENT_2; reg [dw-1:0] COEFFICIENT_3; reg [dw-1:0] COEFFICIENT_4; reg [dw-1:0] COEFFICIENT_5; reg [dw-1:0] COEFFICIENT_6; reg [dw-1:0] COEFFICIENT_7; reg [dw-1:0] COEFFICIENT_8; reg [dw-1:0] COEFFICIENT_9; reg [dw-1:0] COEFFICIENT_10; reg [dw-1:0] COEFFICIENT_11; reg [dw-1:0] COEFFICIENT_12; reg [dw-1:0] COEFFICIENT_13; reg [dw-1:0] COEFFICIENT_14; reg [dw-1:0] COEFFICIENT_15; reg [dw-1:0] COEFFICIENT_16; reg [dw-1:0] COEFFICIENT_17; reg [dw-1:0] COEFFICIENT_18; reg [dw-1:0] COEFFICIENT_19; reg [dw-1:0] COEFFICIENT_20; reg [dw-1:0] COEFFICIENT_21; reg [dw-1:0] COEFFICIENT_22; reg [dw-1:0] COEFFICIENT_23; reg [dw-1:0] COEFFICIENT_24; reg [dw-1:0] COEFFICIENT_25; always@(posedge clk) begin COEFFICIENT_0 <= 18'd88; COEFFICIENT_1 <= 18'd0; COEFFICIENT_2 <= -18'd97; COEFFICIENT_3 <= -18'd197; COEFFICIENT_4 <= -18'd294; COEFFICIENT_5 <= -18'd380; COEFFICIENT_6 <= -18'd447; COEFFICIENT_7 <= -18'd490; COEFFICIENT_8 <= -18'd504; COEFFICIENT_9 <= -18'd481; COEFFICIENT_10 <= -18'd420; COEFFICIENT_11 <= -18'd319; COEFFICIENT_12 <= -18'd178; COEFFICIENT_13 <= 18'd0; COEFFICIENT_14 <= 18'd212; COEFFICIENT_15 <= 18'd451; COEFFICIENT_16 <= 18'd710; COEFFICIENT_17 <= 18'd980; COEFFICIENT_18 <= 18'd1252; COEFFICIENT_19 <= 18'd1514; COEFFICIENT_20 <= 18'd1756; COEFFICIENT_21 <= 18'd1971; COEFFICIENT_22 <= 18'd2147; COEFFICIENT_23 <= 18'd2278; COEFFICIENT_24 <= 18'd2360; COEFFICIENT_25 <= 18'd2387; end ////****************************************************** // * // * Valid Delay Pipeline // * // *************************************************** //Input valid signal is pipelined to become output valid signal //Valid registers reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS; always@(posedge clk or posedge reset) begin if(reset) begin VALID_PIPELINE_REGS <= 0; end else begin if(clk_ena) begin VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid}; end else begin VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS; end end end ////**************************************************** // * // * Input Register Pipeline // * // *************************************************** //Pipelined input values //Input value registers wire [dw-1:0] INPUT_PIPELINE_REG_0; wire [dw-1:0] INPUT_PIPELINE_REG_1; wire [dw-1:0] INPUT_PIPELINE_REG_2; wire [dw-1:0] INPUT_PIPELINE_REG_3; wire [dw-1:0] INPUT_PIPELINE_REG_4; wire [dw-1:0] INPUT_PIPELINE_REG_5; wire [dw-1:0] INPUT_PIPELINE_REG_6; wire [dw-1:0] INPUT_PIPELINE_REG_7; wire [dw-1:0] INPUT_PIPELINE_REG_8; wire [dw-1:0] INPUT_PIPELINE_REG_9; wire [dw-1:0] INPUT_PIPELINE_REG_10; wire [dw-1:0] INPUT_PIPELINE_REG_11; wire [dw-1:0] INPUT_PIPELINE_REG_12; wire [dw-1:0] INPUT_PIPELINE_REG_13; wire [dw-1:0] INPUT_PIPELINE_REG_14; wire [dw-1:0] INPUT_PIPELINE_REG_15; wire [dw-1:0] INPUT_PIPELINE_REG_16; wire [dw-1:0] INPUT_PIPELINE_REG_17; wire [dw-1:0] INPUT_PIPELINE_REG_18; wire [dw-1:0] INPUT_PIPELINE_REG_19; wire [dw-1:0] INPUT_PIPELINE_REG_20; wire [dw-1:0] INPUT_PIPELINE_REG_21; wire [dw-1:0] INPUT_PIPELINE_REG_22; wire [dw-1:0] INPUT_PIPELINE_REG_23; wire [dw-1:0] INPUT_PIPELINE_REG_24; wire [dw-1:0] INPUT_PIPELINE_REG_25; wire [dw-1:0] INPUT_PIPELINE_REG_26; wire [dw-1:0] INPUT_PIPELINE_REG_27; wire [dw-1:0] INPUT_PIPELINE_REG_28; wire [dw-1:0] INPUT_PIPELINE_REG_29; wire [dw-1:0] INPUT_PIPELINE_REG_30; wire [dw-1:0] INPUT_PIPELINE_REG_31; wire [dw-1:0] INPUT_PIPELINE_REG_32; wire [dw-1:0] INPUT_PIPELINE_REG_33; wire [dw-1:0] INPUT_PIPELINE_REG_34; wire [dw-1:0] INPUT_PIPELINE_REG_35; wire [dw-1:0] INPUT_PIPELINE_REG_36; wire [dw-1:0] INPUT_PIPELINE_REG_37; wire [dw-1:0] INPUT_PIPELINE_REG_38; wire [dw-1:0] INPUT_PIPELINE_REG_39; wire [dw-1:0] INPUT_PIPELINE_REG_40; wire [dw-1:0] INPUT_PIPELINE_REG_41; wire [dw-1:0] INPUT_PIPELINE_REG_42; wire [dw-1:0] INPUT_PIPELINE_REG_43; wire [dw-1:0] INPUT_PIPELINE_REG_44; wire [dw-1:0] INPUT_PIPELINE_REG_45; wire [dw-1:0] INPUT_PIPELINE_REG_46; wire [dw-1:0] INPUT_PIPELINE_REG_47; wire [dw-1:0] INPUT_PIPELINE_REG_48; wire [dw-1:0] INPUT_PIPELINE_REG_49; wire [dw-1:0] INPUT_PIPELINE_REG_50; input_pipeline in_pipe( .clk(clk), .clk_ena(clk_ena), .in_stream(i_in), .pipeline_reg_0(INPUT_PIPELINE_REG_0), .pipeline_reg_1(INPUT_PIPELINE_REG_1), .pipeline_reg_2(INPUT_PIPELINE_REG_2), .pipeline_reg_3(INPUT_PIPELINE_REG_3), .pipeline_reg_4(INPUT_PIPELINE_REG_4), .pipeline_reg_5(INPUT_PIPELINE_REG_5), .pipeline_reg_6(INPUT_PIPELINE_REG_6), .pipeline_reg_7(INPUT_PIPELINE_REG_7), .pipeline_reg_8(INPUT_PIPELINE_REG_8), .pipeline_reg_9(INPUT_PIPELINE_REG_9), .pipeline_reg_10(INPUT_PIPELINE_REG_10), .pipeline_reg_11(INPUT_PIPELINE_REG_11), .pipeline_reg_12(INPUT_PIPELINE_REG_12), .pipeline_reg_13(INPUT_PIPELINE_REG_13), .pipeline_reg_14(INPUT_PIPELINE_REG_14), .pipeline_reg_15(INPUT_PIPELINE_REG_15), .pipeline_reg_16(INPUT_PIPELINE_REG_16), .pipeline_reg_17(INPUT_PIPELINE_REG_17), .pipeline_reg_18(INPUT_PIPELINE_REG_18), .pipeline_reg_19(INPUT_PIPELINE_REG_19), .pipeline_reg_20(INPUT_PIPELINE_REG_20), .pipeline_reg_21(INPUT_PIPELINE_REG_21), .pipeline_reg_22(INPUT_PIPELINE_REG_22), .pipeline_reg_23(INPUT_PIPELINE_REG_23), .pipeline_reg_24(INPUT_PIPELINE_REG_24), .pipeline_reg_25(INPUT_PIPELINE_REG_25), .pipeline_reg_26(INPUT_PIPELINE_REG_26), .pipeline_reg_27(INPUT_PIPELINE_REG_27), .pipeline_reg_28(INPUT_PIPELINE_REG_28), .pipeline_reg_29(INPUT_PIPELINE_REG_29), .pipeline_reg_30(INPUT_PIPELINE_REG_30), .pipeline_reg_31(INPUT_PIPELINE_REG_31), .pipeline_reg_32(INPUT_PIPELINE_REG_32), .pipeline_reg_33(INPUT_PIPELINE_REG_33), .pipeline_reg_34(INPUT_PIPELINE_REG_34), .pipeline_reg_35(INPUT_PIPELINE_REG_35), .pipeline_reg_36(INPUT_PIPELINE_REG_36), .pipeline_reg_37(INPUT_PIPELINE_REG_37), .pipeline_reg_38(INPUT_PIPELINE_REG_38), .pipeline_reg_39(INPUT_PIPELINE_REG_39), .pipeline_reg_40(INPUT_PIPELINE_REG_40), .pipeline_reg_41(INPUT_PIPELINE_REG_41), .pipeline_reg_42(INPUT_PIPELINE_REG_42), .pipeline_reg_43(INPUT_PIPELINE_REG_43), .pipeline_reg_44(INPUT_PIPELINE_REG_44), .pipeline_reg_45(INPUT_PIPELINE_REG_45), .pipeline_reg_46(INPUT_PIPELINE_REG_46), .pipeline_reg_47(INPUT_PIPELINE_REG_47), .pipeline_reg_48(INPUT_PIPELINE_REG_48), .pipeline_reg_49(INPUT_PIPELINE_REG_49), .pipeline_reg_50(INPUT_PIPELINE_REG_50), .reset(reset) ); defparam in_pipe.WIDTH = 18; // = dw ////**************************************************** // * // * Computation Pipeline // * // *************************************************** // ********************* LEVEL 0 ********************* \\ wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; wire [dw-1:0] L0_output_wires_3; wire [dw-1:0] L0_output_wires_4; wire [dw-1:0] L0_output_wires_5; wire [dw-1:0] L0_output_wires_6; wire [dw-1:0] L0_output_wires_7; wire [dw-1:0] L0_output_wires_8; wire [dw-1:0] L0_output_wires_9; wire [dw-1:0] L0_output_wires_10; wire [dw-1:0] L0_output_wires_11; wire [dw-1:0] L0_output_wires_12; wire [dw-1:0] L0_output_wires_13; wire [dw-1:0] L0_output_wires_14; wire [dw-1:0] L0_output_wires_15; wire [dw-1:0] L0_output_wires_16; wire [dw-1:0] L0_output_wires_17; wire [dw-1:0] L0_output_wires_18; wire [dw-1:0] L0_output_wires_19; wire [dw-1:0] L0_output_wires_20; wire [dw-1:0] L0_output_wires_21; wire [dw-1:0] L0_output_wires_22; wire [dw-1:0] L0_output_wires_23; wire [dw-1:0] L0_output_wires_24; wire [dw-1:0] L0_output_wires_25; adder_with_1_reg L0_adder_0and50( .dataa (INPUT_PIPELINE_REG_0), .datab (INPUT_PIPELINE_REG_50), .result(L0_output_wires_0) ); adder_with_1_reg L0_adder_1and49( .dataa (INPUT_PIPELINE_REG_1), .datab (INPUT_PIPELINE_REG_49), .result(L0_output_wires_1) ); adder_with_1_reg L0_adder_2and48( .dataa (INPUT_PIPELINE_REG_2), .datab (INPUT_PIPELINE_REG_48), .result(L0_output_wires_2) ); adder_with_1_reg L0_adder_3and47( .dataa (INPUT_PIPELINE_REG_3), .datab (INPUT_PIPELINE_REG_47), .result(L0_output_wires_3) ); adder_with_1_reg L0_adder_4and46( .dataa (INPUT_PIPELINE_REG_4), .datab (INPUT_PIPELINE_REG_46), .result(L0_output_wires_4) ); adder_with_1_reg L0_adder_5and45( .dataa (INPUT_PIPELINE_REG_5), .datab (INPUT_PIPELINE_REG_45), .result(L0_output_wires_5) ); adder_with_1_reg L0_adder_6and44( .dataa (INPUT_PIPELINE_REG_6), .datab (INPUT_PIPELINE_REG_44), .result(L0_output_wires_6) ); adder_with_1_reg L0_adder_7and43( .dataa (INPUT_PIPELINE_REG_7), .datab (INPUT_PIPELINE_REG_43), .result(L0_output_wires_7) ); adder_with_1_reg L0_adder_8and42( .dataa (INPUT_PIPELINE_REG_8), .datab (INPUT_PIPELINE_REG_42), .result(L0_output_wires_8) ); adder_with_1_reg L0_adder_9and41( .dataa (INPUT_PIPELINE_REG_9), .datab (INPUT_PIPELINE_REG_41), .result(L0_output_wires_9) ); adder_with_1_reg L0_adder_10and40( .dataa (INPUT_PIPELINE_REG_10), .datab (INPUT_PIPELINE_REG_40), .result(L0_output_wires_10) ); adder_with_1_reg L0_adder_11and39( .dataa (INPUT_PIPELINE_REG_11), .datab (INPUT_PIPELINE_REG_39), .result(L0_output_wires_11) ); adder_with_1_reg L0_adder_12and38( .dataa (INPUT_PIPELINE_REG_12), .datab (INPUT_PIPELINE_REG_38), .result(L0_output_wires_12) ); adder_with_1_reg L0_adder_13and37( .dataa (INPUT_PIPELINE_REG_13), .datab (INPUT_PIPELINE_REG_37), .result(L0_output_wires_13) ); adder_with_1_reg L0_adder_14and36( .dataa (INPUT_PIPELINE_REG_14), .datab (INPUT_PIPELINE_REG_36), .result(L0_output_wires_14) ); adder_with_1_reg L0_adder_15and35( .dataa (INPUT_PIPELINE_REG_15), .datab (INPUT_PIPELINE_REG_35), .result(L0_output_wires_15) ); adder_with_1_reg L0_adder_16and34( .dataa (INPUT_PIPELINE_REG_16), .datab (INPUT_PIPELINE_REG_34), .result(L0_output_wires_16) ); adder_with_1_reg L0_adder_17and33( .dataa (INPUT_PIPELINE_REG_17), .datab (INPUT_PIPELINE_REG_33), .result(L0_output_wires_17) ); adder_with_1_reg L0_adder_18and32( .dataa (INPUT_PIPELINE_REG_18), .datab (INPUT_PIPELINE_REG_32), .result(L0_output_wires_18) ); adder_with_1_reg L0_adder_19and31( .dataa (INPUT_PIPELINE_REG_19), .datab (INPUT_PIPELINE_REG_31), .result(L0_output_wires_19) ); adder_with_1_reg L0_adder_20and30( .dataa (INPUT_PIPELINE_REG_20), .datab (INPUT_PIPELINE_REG_30), .result(L0_output_wires_20) ); adder_with_1_reg L0_adder_21and29( .dataa (INPUT_PIPELINE_REG_21), .datab (INPUT_PIPELINE_REG_29), .result(L0_output_wires_21) ); adder_with_1_reg L0_adder_22and28( .dataa (INPUT_PIPELINE_REG_22), .datab (INPUT_PIPELINE_REG_28), .result(L0_output_wires_22) ); adder_with_1_reg L0_adder_23and27( .dataa (INPUT_PIPELINE_REG_23), .datab (INPUT_PIPELINE_REG_27), .result(L0_output_wires_23) ); adder_with_1_reg L0_adder_24and26( .dataa (INPUT_PIPELINE_REG_24), .datab (INPUT_PIPELINE_REG_26), .result(L0_output_wires_24) ); // (25 main tree Adders) // ***** Byes **** \\ one_register L0_byereg_for_25( .dataa (INPUT_PIPELINE_REG_25), .result(L0_output_wires_25) ); // (1 byes) // ********************* LEVEL 1 ********************* \\ // ************ Multipliers ************ \\ wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; wire [dw-1:0] L1_mult_wires_3; wire [dw-1:0] L1_mult_wires_4; wire [dw-1:0] L1_mult_wires_5; wire [dw-1:0] L1_mult_wires_6; wire [dw-1:0] L1_mult_wires_7; wire [dw-1:0] L1_mult_wires_8; wire [dw-1:0] L1_mult_wires_9; wire [dw-1:0] L1_mult_wires_10; wire [dw-1:0] L1_mult_wires_11; wire [dw-1:0] L1_mult_wires_12; wire [dw-1:0] L1_mult_wires_13; wire [dw-1:0] L1_mult_wires_14; wire [dw-1:0] L1_mult_wires_15; wire [dw-1:0] L1_mult_wires_16; wire [dw-1:0] L1_mult_wires_17; wire [dw-1:0] L1_mult_wires_18; wire [dw-1:0] L1_mult_wires_19; wire [dw-1:0] L1_mult_wires_20; wire [dw-1:0] L1_mult_wires_21; wire [dw-1:0] L1_mult_wires_22; wire [dw-1:0] L1_mult_wires_23; wire [dw-1:0] L1_mult_wires_24; wire [dw-1:0] L1_mult_wires_25; multiplier_with_reg L1_mul_0( .dataa (L0_output_wires_0), .datab (COEFFICIENT_0), .result(L1_mult_wires_0) ); multiplier_with_reg L1_mul_1( .dataa (L0_output_wires_1), .datab (COEFFICIENT_1), .result(L1_mult_wires_1) ); multiplier_with_reg L1_mul_2( .dataa (L0_output_wires_2), .datab (COEFFICIENT_2), .result(L1_mult_wires_2) ); multiplier_with_reg L1_mul_3( .dataa (L0_output_wires_3), .datab (COEFFICIENT_3), .result(L1_mult_wires_3) ); multiplier_with_reg L1_mul_4( .dataa (L0_output_wires_4), .datab (COEFFICIENT_4), .result(L1_mult_wires_4) ); multiplier_with_reg L1_mul_5( .dataa (L0_output_wires_5), .datab (COEFFICIENT_5), .result(L1_mult_wires_5) ); multiplier_with_reg L1_mul_6( .dataa (L0_output_wires_6), .datab (COEFFICIENT_6), .result(L1_mult_wires_6) ); multiplier_with_reg L1_mul_7( .dataa (L0_output_wires_7), .datab (COEFFICIENT_7), .result(L1_mult_wires_7) ); multiplier_with_reg L1_mul_8( .dataa (L0_output_wires_8), .datab (COEFFICIENT_8), .result(L1_mult_wires_8) ); multiplier_with_reg L1_mul_9( .dataa (L0_output_wires_9), .datab (COEFFICIENT_9), .result(L1_mult_wires_9) ); multiplier_with_reg L1_mul_10( .dataa (L0_output_wires_10), .datab (COEFFICIENT_10), .result(L1_mult_wires_10) ); multiplier_with_reg L1_mul_11( .dataa (L0_output_wires_11), .datab (COEFFICIENT_11), .result(L1_mult_wires_11) ); multiplier_with_reg L1_mul_12( .dataa (L0_output_wires_12), .datab (COEFFICIENT_12), .result(L1_mult_wires_12) ); multiplier_with_reg L1_mul_13( .dataa (L0_output_wires_13), .datab (COEFFICIENT_13), .result(L1_mult_wires_13) ); multiplier_with_reg L1_mul_14( .dataa (L0_output_wires_14), .datab (COEFFICIENT_14), .result(L1_mult_wires_14) ); multiplier_with_reg L1_mul_15( .dataa (L0_output_wires_15), .datab (COEFFICIENT_15), .result(L1_mult_wires_15) ); multiplier_with_reg L1_mul_16( .dataa (L0_output_wires_16), .datab (COEFFICIENT_16), .result(L1_mult_wires_16) ); multiplier_with_reg L1_mul_17( .dataa (L0_output_wires_17), .datab (COEFFICIENT_17), .result(L1_mult_wires_17) ); multiplier_with_reg L1_mul_18( .dataa (L0_output_wires_18), .datab (COEFFICIENT_18), .result(L1_mult_wires_18) ); multiplier_with_reg L1_mul_19( .dataa (L0_output_wires_19), .datab (COEFFICIENT_19), .result(L1_mult_wires_19) ); multiplier_with_reg L1_mul_20( .dataa (L0_output_wires_20), .datab (COEFFICIENT_20), .result(L1_mult_wires_20) ); multiplier_with_reg L1_mul_21( .dataa (L0_output_wires_21), .datab (COEFFICIENT_21), .result(L1_mult_wires_21) ); multiplier_with_reg L1_mul_22( .dataa (L0_output_wires_22), .datab (COEFFICIENT_22), .result(L1_mult_wires_22) ); multiplier_with_reg L1_mul_23( .dataa (L0_output_wires_23), .datab (COEFFICIENT_23), .result(L1_mult_wires_23) ); multiplier_with_reg L1_mul_24( .dataa (L0_output_wires_24), .datab (COEFFICIENT_24), .result(L1_mult_wires_24) ); multiplier_with_reg L1_mul_25( .dataa (L0_output_wires_25), .datab (COEFFICIENT_25), .result(L1_mult_wires_25) ); // (26 Multipliers) // ************ Adders ************ \\ wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; wire [dw-1:0] L1_output_wires_3; wire [dw-1:0] L1_output_wires_4; wire [dw-1:0] L1_output_wires_5; wire [dw-1:0] L1_output_wires_6; wire [dw-1:0] L1_output_wires_7; wire [dw-1:0] L1_output_wires_8; wire [dw-1:0] L1_output_wires_9; wire [dw-1:0] L1_output_wires_10; wire [dw-1:0] L1_output_wires_11; wire [dw-1:0] L1_output_wires_12; adder_with_1_reg L1_adder_0and1( .dataa (L1_mult_wires_0), .datab (L1_mult_wires_1), .result(L1_output_wires_0) ); adder_with_1_reg L1_adder_2and3( .dataa (L1_mult_wires_2), .datab (L1_mult_wires_3), .result(L1_output_wires_1) ); adder_with_1_reg L1_adder_4and5( .dataa (L1_mult_wires_4), .datab (L1_mult_wires_5), .result(L1_output_wires_2) ); adder_with_1_reg L1_adder_6and7( .dataa (L1_mult_wires_6), .datab (L1_mult_wires_7), .result(L1_output_wires_3) ); adder_with_1_reg L1_adder_8and9( .dataa (L1_mult_wires_8), .datab (L1_mult_wires_9), .result(L1_output_wires_4) ); adder_with_1_reg L1_adder_10and11( .dataa (L1_mult_wires_10), .datab (L1_mult_wires_11), .result(L1_output_wires_5) ); adder_with_1_reg L1_adder_12and13( .dataa (L1_mult_wires_12), .datab (L1_mult_wires_13), .result(L1_output_wires_6) ); adder_with_1_reg L1_adder_14and15( .dataa (L1_mult_wires_14), .datab (L1_mult_wires_15), .result(L1_output_wires_7) ); adder_with_1_reg L1_adder_16and17( .dataa (L1_mult_wires_16), .datab (L1_mult_wires_17), .result(L1_output_wires_8) ); adder_with_1_reg L1_adder_18and19( .dataa (L1_mult_wires_18), .datab (L1_mult_wires_19), .result(L1_output_wires_9) ); adder_with_1_reg L1_adder_20and21( .dataa (L1_mult_wires_20), .datab (L1_mult_wires_21), .result(L1_output_wires_10) ); adder_with_1_reg L1_adder_22and23( .dataa (L1_mult_wires_22), .datab (L1_mult_wires_23), .result(L1_output_wires_11) ); adder_with_1_reg L1_adder_24and25( .dataa (L1_mult_wires_24), .datab (L1_mult_wires_25), .result(L1_output_wires_12) ); // (13 main tree Adders) // ********************* LEVEL 2 ********************* \\ wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; wire [dw-1:0] L2_output_wires_3; wire [dw-1:0] L2_output_wires_4; wire [dw-1:0] L2_output_wires_5; wire [dw-1:0] L2_output_wires_6; adder_with_1_reg L2_adder_0and1( .dataa (L1_output_wires_0), .datab (L1_output_wires_1), .result(L2_output_wires_0) ); adder_with_1_reg L2_adder_2and3( .dataa (L1_output_wires_2), .datab (L1_output_wires_3), .result(L2_output_wires_1) ); adder_with_1_reg L2_adder_4and5( .dataa (L1_output_wires_4), .datab (L1_output_wires_5), .result(L2_output_wires_2) ); adder_with_1_reg L2_adder_6and7( .dataa (L1_output_wires_6), .datab (L1_output_wires_7), .result(L2_output_wires_3) ); adder_with_1_reg L2_adder_8and9( .dataa (L1_output_wires_8), .datab (L1_output_wires_9), .result(L2_output_wires_4) ); adder_with_1_reg L2_adder_10and11( .dataa (L1_output_wires_10), .datab (L1_output_wires_11), .result(L2_output_wires_5) ); // (6 main tree Adders) // ***** Byes **** \\ one_register L2_byereg_for_12( .dataa (L1_output_wires_12), .result(L2_output_wires_6) ); // (1 byes) // ********************* LEVEL 3 ********************* \\ wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; wire [dw-1:0] L3_output_wires_3; adder_with_1_reg L3_adder_0and1( .dataa (L2_output_wires_0), .datab (L2_output_wires_1), .result(L3_output_wires_0) ); adder_with_1_reg L3_adder_2and3( .dataa (L2_output_wires_2), .datab (L2_output_wires_3), .result(L3_output_wires_1) ); adder_with_1_reg L3_adder_4and5( .dataa (L2_output_wires_4), .datab (L2_output_wires_5), .result(L3_output_wires_2) ); // (3 main tree Adders) // ***** Byes **** \\ one_register L3_byereg_for_6( .dataa (L2_output_wires_6), .result(L3_output_wires_3) ); // (1 byes) // ********************* LEVEL 4 ********************* \\ wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; adder_with_1_reg L4_adder_0and1( .dataa (L3_output_wires_0), .datab (L3_output_wires_1), .result(L4_output_wires_0) ); adder_with_1_reg L4_adder_2and3( .dataa (L3_output_wires_2), .datab (L3_output_wires_3), .result(L4_output_wires_1) ); // (2 main tree Adders) // ********************* LEVEL 5 ********************* \\ wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( .dataa (L4_output_wires_0), .datab (L4_output_wires_1), .result(L5_output_wires_0) ); // (1 main tree Adders) ////**************************************************** // * // * Output Logic // * // ***************************************************** //Actual outputs reg [17:0] o_out; always @(posedge clk) begin if(clk_ena) begin o_out <= L5_output_wires_0; end end assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1]; endmodule module input_pipeline ( clk, clk_ena, in_stream, pipeline_reg_0, pipeline_reg_1, pipeline_reg_2, pipeline_reg_3, pipeline_reg_4, pipeline_reg_5, pipeline_reg_6, pipeline_reg_7, pipeline_reg_8, pipeline_reg_9, pipeline_reg_10, pipeline_reg_11, pipeline_reg_12, pipeline_reg_13, pipeline_reg_14, pipeline_reg_15, pipeline_reg_16, pipeline_reg_17, pipeline_reg_18, pipeline_reg_19, pipeline_reg_20, pipeline_reg_21, pipeline_reg_22, pipeline_reg_23, pipeline_reg_24, pipeline_reg_25, pipeline_reg_26, pipeline_reg_27, pipeline_reg_28, pipeline_reg_29, pipeline_reg_30, pipeline_reg_31, pipeline_reg_32, pipeline_reg_33, pipeline_reg_34, pipeline_reg_35, pipeline_reg_36, pipeline_reg_37, pipeline_reg_38, pipeline_reg_39, pipeline_reg_40, pipeline_reg_41, pipeline_reg_42, pipeline_reg_43, pipeline_reg_44, pipeline_reg_45, pipeline_reg_46, pipeline_reg_47, pipeline_reg_48, pipeline_reg_49, pipeline_reg_50, reset); parameter WIDTH = 1; //Input value registers input clk; input clk_ena; input [WIDTH-1:0] in_stream; output [WIDTH-1:0] pipeline_reg_0; output [WIDTH-1:0] pipeline_reg_1; output [WIDTH-1:0] pipeline_reg_2; output [WIDTH-1:0] pipeline_reg_3; output [WIDTH-1:0] pipeline_reg_4; output [WIDTH-1:0] pipeline_reg_5; output [WIDTH-1:0] pipeline_reg_6; output [WIDTH-1:0] pipeline_reg_7; output [WIDTH-1:0] pipeline_reg_8; output [WIDTH-1:0] pipeline_reg_9; output [WIDTH-1:0] pipeline_reg_10; output [WIDTH-1:0] pipeline_reg_11; output [WIDTH-1:0] pipeline_reg_12; output [WIDTH-1:0] pipeline_reg_13; output [WIDTH-1:0] pipeline_reg_14; output [WIDTH-1:0] pipeline_reg_15; output [WIDTH-1:0] pipeline_reg_16; output [WIDTH-1:0] pipeline_reg_17; output [WIDTH-1:0] pipeline_reg_18; output [WIDTH-1:0] pipeline_reg_19; output [WIDTH-1:0] pipeline_reg_20; output [WIDTH-1:0] pipeline_reg_21; output [WIDTH-1:0] pipeline_reg_22; output [WIDTH-1:0] pipeline_reg_23; output [WIDTH-1:0] pipeline_reg_24; output [WIDTH-1:0] pipeline_reg_25; output [WIDTH-1:0] pipeline_reg_26; output [WIDTH-1:0] pipeline_reg_27; output [WIDTH-1:0] pipeline_reg_28; output [WIDTH-1:0] pipeline_reg_29; output [WIDTH-1:0] pipeline_reg_30; output [WIDTH-1:0] pipeline_reg_31; output [WIDTH-1:0] pipeline_reg_32; output [WIDTH-1:0] pipeline_reg_33; output [WIDTH-1:0] pipeline_reg_34; output [WIDTH-1:0] pipeline_reg_35; output [WIDTH-1:0] pipeline_reg_36; output [WIDTH-1:0] pipeline_reg_37; output [WIDTH-1:0] pipeline_reg_38; output [WIDTH-1:0] pipeline_reg_39; output [WIDTH-1:0] pipeline_reg_40; output [WIDTH-1:0] pipeline_reg_41; output [WIDTH-1:0] pipeline_reg_42; output [WIDTH-1:0] pipeline_reg_43; output [WIDTH-1:0] pipeline_reg_44; output [WIDTH-1:0] pipeline_reg_45; output [WIDTH-1:0] pipeline_reg_46; output [WIDTH-1:0] pipeline_reg_47; output [WIDTH-1:0] pipeline_reg_48; output [WIDTH-1:0] pipeline_reg_49; output [WIDTH-1:0] pipeline_reg_50; reg [WIDTH-1:0] pipeline_reg_0; reg [WIDTH-1:0] pipeline_reg_1; reg [WIDTH-1:0] pipeline_reg_2; reg [WIDTH-1:0] pipeline_reg_3; reg [WIDTH-1:0] pipeline_reg_4; reg [WIDTH-1:0] pipeline_reg_5; reg [WIDTH-1:0] pipeline_reg_6; reg [WIDTH-1:0] pipeline_reg_7; reg [WIDTH-1:0] pipeline_reg_8; reg [WIDTH-1:0] pipeline_reg_9; reg [WIDTH-1:0] pipeline_reg_10; reg [WIDTH-1:0] pipeline_reg_11; reg [WIDTH-1:0] pipeline_reg_12; reg [WIDTH-1:0] pipeline_reg_13; reg [WIDTH-1:0] pipeline_reg_14; reg [WIDTH-1:0] pipeline_reg_15; reg [WIDTH-1:0] pipeline_reg_16; reg [WIDTH-1:0] pipeline_reg_17; reg [WIDTH-1:0] pipeline_reg_18; reg [WIDTH-1:0] pipeline_reg_19; reg [WIDTH-1:0] pipeline_reg_20; reg [WIDTH-1:0] pipeline_reg_21; reg [WIDTH-1:0] pipeline_reg_22; reg [WIDTH-1:0] pipeline_reg_23; reg [WIDTH-1:0] pipeline_reg_24; reg [WIDTH-1:0] pipeline_reg_25; reg [WIDTH-1:0] pipeline_reg_26; reg [WIDTH-1:0] pipeline_reg_27; reg [WIDTH-1:0] pipeline_reg_28; reg [WIDTH-1:0] pipeline_reg_29; reg [WIDTH-1:0] pipeline_reg_30; reg [WIDTH-1:0] pipeline_reg_31; reg [WIDTH-1:0] pipeline_reg_32; reg [WIDTH-1:0] pipeline_reg_33; reg [WIDTH-1:0] pipeline_reg_34; reg [WIDTH-1:0] pipeline_reg_35; reg [WIDTH-1:0] pipeline_reg_36; reg [WIDTH-1:0] pipeline_reg_37; reg [WIDTH-1:0] pipeline_reg_38; reg [WIDTH-1:0] pipeline_reg_39; reg [WIDTH-1:0] pipeline_reg_40; reg [WIDTH-1:0] pipeline_reg_41; reg [WIDTH-1:0] pipeline_reg_42; reg [WIDTH-1:0] pipeline_reg_43; reg [WIDTH-1:0] pipeline_reg_44; reg [WIDTH-1:0] pipeline_reg_45; reg [WIDTH-1:0] pipeline_reg_46; reg [WIDTH-1:0] pipeline_reg_47; reg [WIDTH-1:0] pipeline_reg_48; reg [WIDTH-1:0] pipeline_reg_49; reg [WIDTH-1:0] pipeline_reg_50; input reset; always@(posedge clk or posedge reset) begin if(reset) begin pipeline_reg_0 <= 0; pipeline_reg_1 <= 0; pipeline_reg_2 <= 0; pipeline_reg_3 <= 0; pipeline_reg_4 <= 0; pipeline_reg_5 <= 0; pipeline_reg_6 <= 0; pipeline_reg_7 <= 0; pipeline_reg_8 <= 0; pipeline_reg_9 <= 0; pipeline_reg_10 <= 0; pipeline_reg_11 <= 0; pipeline_reg_12 <= 0; pipeline_reg_13 <= 0; pipeline_reg_14 <= 0; pipeline_reg_15 <= 0; pipeline_reg_16 <= 0; pipeline_reg_17 <= 0; pipeline_reg_18 <= 0; pipeline_reg_19 <= 0; pipeline_reg_20 <= 0; pipeline_reg_21 <= 0; pipeline_reg_22 <= 0; pipeline_reg_23 <= 0; pipeline_reg_24 <= 0; pipeline_reg_25 <= 0; pipeline_reg_26 <= 0; pipeline_reg_27 <= 0; pipeline_reg_28 <= 0; pipeline_reg_29 <= 0; pipeline_reg_30 <= 0; pipeline_reg_31 <= 0; pipeline_reg_32 <= 0; pipeline_reg_33 <= 0; pipeline_reg_34 <= 0; pipeline_reg_35 <= 0; pipeline_reg_36 <= 0; pipeline_reg_37 <= 0; pipeline_reg_38 <= 0; pipeline_reg_39 <= 0; pipeline_reg_40 <= 0; pipeline_reg_41 <= 0; pipeline_reg_42 <= 0; pipeline_reg_43 <= 0; pipeline_reg_44 <= 0; pipeline_reg_45 <= 0; pipeline_reg_46 <= 0; pipeline_reg_47 <= 0; pipeline_reg_48 <= 0; pipeline_reg_49 <= 0; pipeline_reg_50 <= 0; end else begin if(clk_ena) begin pipeline_reg_0 <= in_stream; pipeline_reg_1 <= pipeline_reg_0; pipeline_reg_2 <= pipeline_reg_1; pipeline_reg_3 <= pipeline_reg_2; pipeline_reg_4 <= pipeline_reg_3; pipeline_reg_5 <= pipeline_reg_4; pipeline_reg_6 <= pipeline_reg_5; pipeline_reg_7 <= pipeline_reg_6; pipeline_reg_8 <= pipeline_reg_7; pipeline_reg_9 <= pipeline_reg_8; pipeline_reg_10 <= pipeline_reg_9; pipeline_reg_11 <= pipeline_reg_10; pipeline_reg_12 <= pipeline_reg_11; pipeline_reg_13 <= pipeline_reg_12; pipeline_reg_14 <= pipeline_reg_13; pipeline_reg_15 <= pipeline_reg_14; pipeline_reg_16 <= pipeline_reg_15; pipeline_reg_17 <= pipeline_reg_16; pipeline_reg_18 <= pipeline_reg_17; pipeline_reg_19 <= pipeline_reg_18; pipeline_reg_20 <= pipeline_reg_19; pipeline_reg_21 <= pipeline_reg_20; pipeline_reg_22 <= pipeline_reg_21; pipeline_reg_23 <= pipeline_reg_22; pipeline_reg_24 <= pipeline_reg_23; pipeline_reg_25 <= pipeline_reg_24; pipeline_reg_26 <= pipeline_reg_25; pipeline_reg_27 <= pipeline_reg_26; pipeline_reg_28 <= pipeline_reg_27; pipeline_reg_29 <= pipeline_reg_28; pipeline_reg_30 <= pipeline_reg_29; pipeline_reg_31 <= pipeline_reg_30; pipeline_reg_32 <= pipeline_reg_31; pipeline_reg_33 <= pipeline_reg_32; pipeline_reg_34 <= pipeline_reg_33; pipeline_reg_35 <= pipeline_reg_34; pipeline_reg_36 <= pipeline_reg_35; pipeline_reg_37 <= pipeline_reg_36; pipeline_reg_38 <= pipeline_reg_37; pipeline_reg_39 <= pipeline_reg_38; pipeline_reg_40 <= pipeline_reg_39; pipeline_reg_41 <= pipeline_reg_40; pipeline_reg_42 <= pipeline_reg_41; pipeline_reg_43 <= pipeline_reg_42; pipeline_reg_44 <= pipeline_reg_43; pipeline_reg_45 <= pipeline_reg_44; pipeline_reg_46 <= pipeline_reg_45; pipeline_reg_47 <= pipeline_reg_46; pipeline_reg_48 <= pipeline_reg_47; pipeline_reg_49 <= pipeline_reg_48; pipeline_reg_50 <= pipeline_reg_49; end //else begin //pipeline_reg_0 <= pipeline_reg_0; //pipeline_reg_1 <= pipeline_reg_1; //pipeline_reg_2 <= pipeline_reg_2; //pipeline_reg_3 <= pipeline_reg_3; //pipeline_reg_4 <= pipeline_reg_4; //pipeline_reg_5 <= pipeline_reg_5; //pipeline_reg_6 <= pipeline_reg_6; //pipeline_reg_7 <= pipeline_reg_7; //pipeline_reg_8 <= pipeline_reg_8; //pipeline_reg_9 <= pipeline_reg_9; //pipeline_reg_10 <= pipeline_reg_10; //pipeline_reg_11 <= pipeline_reg_11; //pipeline_reg_12 <= pipeline_reg_12; //pipeline_reg_13 <= pipeline_reg_13; //pipeline_reg_14 <= pipeline_reg_14; //pipeline_reg_15 <= pipeline_reg_15; //pipeline_reg_16 <= pipeline_reg_16; //pipeline_reg_17 <= pipeline_reg_17; //pipeline_reg_18 <= pipeline_reg_18; //pipeline_reg_19 <= pipeline_reg_19; //pipeline_reg_20 <= pipeline_reg_20; //pipeline_reg_21 <= pipeline_reg_21; //pipeline_reg_22 <= pipeline_reg_22; //pipeline_reg_23 <= pipeline_reg_23; //pipeline_reg_24 <= pipeline_reg_24; //pipeline_reg_25 <= pipeline_reg_25; //pipeline_reg_26 <= pipeline_reg_26; //pipeline_reg_27 <= pipeline_reg_27; //pipeline_reg_28 <= pipeline_reg_28; //pipeline_reg_29 <= pipeline_reg_29; //pipeline_reg_30 <= pipeline_reg_30; //pipeline_reg_31 <= pipeline_reg_31; //pipeline_reg_32 <= pipeline_reg_32; //pipeline_reg_33 <= pipeline_reg_33; //pipeline_reg_34 <= pipeline_reg_34; //pipeline_reg_35 <= pipeline_reg_35; //pipeline_reg_36 <= pipeline_reg_36; //pipeline_reg_37 <= pipeline_reg_37; //pipeline_reg_38 <= pipeline_reg_38; //pipeline_reg_39 <= pipeline_reg_39; //pipeline_reg_40 <= pipeline_reg_40; //pipeline_reg_41 <= pipeline_reg_41; //pipeline_reg_42 <= pipeline_reg_42; //pipeline_reg_43 <= pipeline_reg_43; //pipeline_reg_44 <= pipeline_reg_44; //pipeline_reg_45 <= pipeline_reg_45; //pipeline_reg_46 <= pipeline_reg_46; //pipeline_reg_47 <= pipeline_reg_47; //pipeline_reg_48 <= pipeline_reg_48; //pipeline_reg_49 <= pipeline_reg_49; //pipeline_reg_50 <= pipeline_reg_50; //end end end endmodule module adder_with_1_reg ( dataa, datab, result); input clk; input clk_ena; input [17:0] dataa; input [17:0] datab; output [17:0] result; assign result = dataa + datab; endmodule module multiplier_with_reg ( dataa, datab, result); input clk; input clk_ena; input [17:0] dataa; input [17:0] datab; output [17:0] result; assign result = dataa * datab; endmodule module one_register ( dataa, result); input clk; input clk_ena; input [17:0] dataa; output [17:0] result; assign result = dataa; endmodule
/***************************************************************************** * * * Module: Altera_UP_RS232_Counters * * Description: * * This module reads and writes data to the RS232 connector on Altera's * * DE1 and DE2 Development and Education Boards. * * * ***************************************************************************/ module Altera_UP_RS232_Counters ( // Inputs clk, reset, reset_counters, // Bidirectionals // Outputs baud_clock_rising_edge, baud_clock_falling_edge, all_bits_transmitted ); /*************************************************************************** * Parameter Declarations * ***************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; /*************************************************************************** * Port Declarations * ***************************************************************************/ // Inputs input clk; input reset; input reset_counters; // Bidirectionals // Outputs output reg baud_clock_rising_edge; output reg baud_clock_falling_edge; output reg all_bits_transmitted; /*************************************************************************** * Internal wires and registers Declarations * ***************************************************************************/ // Internal Wires // Internal Registers reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter; reg [3:0] bit_counter; // State Machine Registers /*************************************************************************** * Finite State Machine(s) * ***************************************************************************/ /*************************************************************************** * Sequential logic * ***************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (reset_counters) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (baud_counter == BAUD_TICK_COUNT) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else baud_counter <= baud_counter + BAUD_TICK_INCREMENT; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_rising_edge <= 1'b0; else if (baud_counter == BAUD_TICK_COUNT) baud_clock_rising_edge <= 1'b1; else baud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_falling_edge <= 1'b0; else if (baud_counter == HALF_BAUD_TICK_COUNT) baud_clock_falling_edge <= 1'b1; else baud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) bit_counter <= 4'h0; else if (reset_counters) bit_counter <= 4'h0; else if (bit_counter == TOTAL_DATA_WIDTH) bit_counter <= 4'h0; else if (baud_counter == BAUD_TICK_COUNT) bit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin if (reset == 1'b1) all_bits_transmitted <= 1'b0; else if (bit_counter == TOTAL_DATA_WIDTH) all_bits_transmitted <= 1'b1; else all_bits_transmitted <= 1'b0; end /*************************************************************************** * Combinational logic * ***************************************************************************/ /*************************************************************************** * Internal Modules * *****************************************************************************/ endmodule
module main(CLK,HSYNC,VSYNC,R,G,B,XCLK,PCLK,D,HIN,VIN); input CLK; output reg HSYNC; output reg VSYNC; output reg R; output reg G; output reg B; output reg XCLK; input PCLK; input [7:0] D; input HIN; input VIN; //hsync = 1589 //pulse = 191 //vsync = 834150 //pulse = 3200 reg [15:0] HCNT; reg [15:0] VCNT; reg drawH; reg drawV; reg [7:0] CAMDAT [1:0]; reg BCNT; reg [15:0] PXCNT; reg [15:0] PVCNT; reg [255:0] RDAT [127:0]; reg [255:0] GDAT [127:0]; reg [255:0] BDAT [127:0]; reg CR; reg CG; reg CB; always @(posedge PCLK)begin if(VIN) PVCNT <= 7'd0; else if(!HIN)begin if(PXCNT != 8'h0) PVCNT <= PVCNT + 7'd1; BCNT <= 1'b0; PXCNT <= 8'h0; end else begin BCNT <= !BCNT; if(BCNT) PXCNT <= PXCNT + 8'd1; end CAMDAT[BCNT] <= D; end always @(negedge CLK) begin XCLK <= ~XCLK; HCNT <= HCNT + 16'h1; if(HCNT == 16'd1588)begin HCNT <= 16'h0; drawH <= 1'b1; end else if(HCNT == 16'd1302)begin HSYNC <= 1'b0; VCNT <= VCNT + 16'h1; end else if(HCNT == 16'd1493)begin HSYNC <= 1'b1; end else if(HCNT == 16'd1270)begin drawH <= 1'b0; end if(VCNT == 16'd513)begin VSYNC <= 1'b0; end else if(VCNT == 16'd515)begin VSYNC <= 1'b1; end else if(VCNT == 16'd524)begin drawV <= 1'b1; VCNT <= 16'h0; end else if(VCNT == 16'd480)begin drawV <= 1'b0; end if(!BCNT && HIN && !VIN && PVCNT[15:8]==0 && PXCNT[15:9]==0) begin RDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][6]; GDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][7]; BDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][5]; end CR <= RDAT[VCNT[7:1]][HCNT[9:2]]; CG <= GDAT[VCNT[7:1]][HCNT[9:2]]; CB <= BDAT[VCNT[7:1]][HCNT[9:2]]; R <= drawH && drawV && CR; G <= drawH && drawV && CG; B <= drawH && drawV && CB; end endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V `define SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V /* * a22o: 2-input AND into both inputs of 2-input OR. * * X = ((A1 & A2) \| (B1 & B2)) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_hdll__a22o ( X , A1, A2, B1, B2 ); // Module ports output X ; input A1; input A2; input B1; input B2; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire and0_out ; wire and1_out ; wire or0_out_X; // Name Output Other arguments and and0 (and0_out , B1, B2 ); and and1 (and1_out , A1, A2 ); or or0 (or0_out_X, and1_out, and0_out); buf buf0 (X , or0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V
// bin2v output // module bin2v( input wire [ 9:0] in_addr, output reg [ 7:0] out_word ); always @* case( in_addr ) 10'h0: out_word = 8'h01; 10'h1: out_word = 8'hf7; 10'h2: out_word = 8'h3f; 10'h3: out_word = 8'h3e; 10'h4: out_word = 8'h80; 10'h5: out_word = 8'hED; 10'h6: out_word = 8'h79; // 3ff7<=BF 10'h7: out_word = 8'h00; 10'h8: out_word = 8'h06; 10'h9: out_word = 8'h7F; 10'hA: out_word = 8'h3e; 10'hB: out_word = 8'b01111010; 10'hC: out_word = 8'hED; 10'hD: out_word = 8'h79; 10'hE: out_word = 8'h06; 10'hF: out_word = 8'hBF; 10'h10: out_word = 8'h3E; 10'h11: out_word = 8'b01111101; 10'h12: out_word = 8'hED; 10'h13: out_word = 8'h79; 10'h14: out_word = 8'h06; 10'h15: out_word = 8'hFF; 10'h16: out_word = 8'h3E; 10'h17: out_word = 8'b01111111; 10'h18: out_word = 8'hED; 10'h19: out_word = 8'h79; 10'h1A: out_word = 8'h01; 10'h1B: out_word = 8'h77; 10'h1C: out_word = 8'hFD; 10'h1D: out_word = 8'h3E; 10'h1E: out_word = 8'hAB; 10'h1F: out_word = 8'hED; 10'h20: out_word = 8'h79; 10'h21: out_word = 8'h21; 10'h22: out_word = 8'h00; 10'h23: out_word = 8'h01; 10'h24: out_word = 8'h11; 10'h25: out_word = 8'h00; 10'h26: out_word = 8'h60; 10'h27: out_word = 8'h01; 10'h28: out_word = 8'h00; 10'h29: out_word = 8'h01; 10'h2A: out_word = 8'hED; 10'h2B: out_word = 8'hB0; 10'h2C: out_word = 8'hC3; 10'h2D: out_word = 8'h00; 10'h2E: out_word = 8'h60; 10'h100: out_word = 8'h01; 10'h101: out_word = 8'h77; 10'h102: out_word = 8'hff; 10'h103: out_word = 8'h3e; 10'h104: out_word = 8'hab; 10'h105: out_word = 8'hed; 10'h106: out_word = 8'h79; 10'h107: out_word = 8'h3e; 10'h108: out_word = 8'h01; 10'h109: out_word = 8'hd3; 10'h10a: out_word = 8'hbf; 10'h10b: out_word = 8'h01; 10'h10c: out_word = 8'hf7; 10'h10d: out_word = 8'hee; 10'h10e: out_word = 8'h3e; 10'h10f: out_word = 8'h80; 10'h110: out_word = 8'hed; 10'h111: out_word = 8'h79; 10'h112: out_word = 8'h06; 10'h113: out_word = 8'hde; 10'h114: out_word = 8'h3e; 10'h115: out_word = 8'h01; 10'h116: out_word = 8'hed; 10'h117: out_word = 8'h79; 10'h118: out_word = 8'h06; 10'h119: out_word = 8'hbe; 10'h11a: out_word = 8'h3e; 10'h11b: out_word = 8'h22; 10'h11c: out_word = 8'hed; 10'h11d: out_word = 8'h78; default: out_word = 8'hFF; endcase endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V `define SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V /* * nand2b: 2-input NAND, first input inverted. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_ms__nand2b ( Y , A_N, B ); // Module ports output Y ; input A_N; input B ; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire not0_out ; wire or0_out_Y; // Name Output Other arguments not not0 (not0_out , B ); or or0 (or0_out_Y, not0_out, A_N ); buf buf0 (Y , or0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V
module dyn_pll_ctrl # (parameter SPEED_MHZ = 25, parameter SPEED_LIMIT = 100, parameter SPEED_MIN = 25, parameter OSC_MHZ = 100) (clk, clk_valid, speed_in, start, progclk, progdata, progen, reset, locked, status); input clk; // NB Assumed to be 12.5MHz uart_clk input clk_valid; // Drive from LOCKED output of first dcm (ie uart_clk valid) input [7:0] speed_in; input start; output reg progclk = 0; output reg progdata = 0; output reg progen = 0; output reg reset = 0; input locked; input [2:1] status; // NB spec says to use (dval-1) and (mval-1), but I don't think we need to be that accurate // and this saves an adder. Feel free to amend it. reg [23:0] watchdog = 0; reg [7:0] state = 0; reg [7:0] dval = OSC_MHZ; // Osc clock speed (hence mval scales in MHz) reg [7:0] mval = SPEED_MHZ; reg start_d1 = 0; always @ (posedge clk) begin progclk <= ~progclk; start_d1 <= start; reset <= 1'b0; // Watchdog is just using locked, perhaps also need \| ~status[2] if (locked) watchdog <= 0; else watchdog <= watchdog + 1'b1; if (watchdog[23]) // Approx 670mS at 12.5MHz - NB spec is 5ms to lock at >50MHz CLKIN (50ms at <50MHz CLKIN) begin // but allow longer just in case watchdog <= 0; reset <= 1'b1; // One cycle at 12.5MHz should suffice (requirment is 3 CLKIN at 100MHz) end if (~clk_valid) // Try not to run while clk is unstable begin progen <= 0; progdata <= 0; state <= 0; end else begin // The documentation is unclear as to whether the DCM loads data on positive or negative edge. The timing // diagram unhelpfully shows data changing on the positive edge, which could mean either its sampled on // negative, or it was clocked on positive! However the following (WRONGLY) says NEGATIVE ... // http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-DCM-CLKGEN-does-PROGCLK-have-a-maximum-period-minimum/td-p/175642 // BUT this can lock up the DCM, positive clock seems more reliable (but it can still lock up for low values of M, eg 2). // Added SPEED_MIN to prevent this (and positive clock is correct, after looking at other implementations eg ztex/theseven) if ((start \|\| start_d1) && state==0 && speed_in >= SPEED_MIN && speed_in <= SPEED_LIMIT && progclk==1) // positive clock // if ((start \|\| start_d1) && state==0 && speed_in >= SPEED_MIN && speed_in <= SPEED_LIMIT && progclk==0) // negative clock begin progen <= 0; progdata <= 0; mval <= speed_in; dval <= OSC_MHZ; state <= 1; end if (state != 0) state <= state + 1'd1; case (state) // Even values to sync with progclk // Send D 2: begin progen <= 1; progdata <= 1; end 4: begin progdata <= 0; end 6,8,10,12,14,16,18,20: begin progdata <= dval[0]; dval[6:0] <= dval[7:1]; end 22: begin progen <= 0; progdata <= 0; end // Send M 32: begin progen <= 1; progdata <= 1; end 36,38,40,42,44,46,48,50: begin progdata <= mval[0]; mval[6:0] <= mval[7:1]; end 52: begin progen <= 0; progdata <= 0; end // Send GO - NB 1 clock cycle 62: begin progen <= 1; end 64: begin progen <= 0; end // We should wait on progdone/locked, but just go straight back to idle 254: begin state <= 0; end endcase end end endmodule
// Model of FIFO in Altera module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); parameter width = 32; parameter depth = 4096; //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req input [31:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [31:0] q; output rdfull; output rdempty; output [7:0] rdusedw; output wrfull; output wrempty; output [7:0] wrusedw; reg [width-1:0] mem [0:depth-1]; reg [7:0] rdptr; reg [7:0] wrptr; `ifdef rd_req reg [width-1:0] q; `else wire [width-1:0] q; `endif reg [7:0] rdusedw; reg [7:0] wrusedw; integer i; always @( aclr) begin wrptr <= #1 0; rdptr <= #1 0; for(i=0;i<depth;i=i+1) mem[i] <= #1 0; end always @(posedge wrclk) if(wrreq) begin wrptr <= #1 wrptr+1; mem[wrptr] <= #1 data; end always @(posedge rdclk) if(rdreq) begin rdptr <= #1 rdptr+1; `ifdef rd_req q <= #1 mem[rdptr]; `endif end `ifdef rd_req `else assign q = mem[rdptr]; `endif // Fix these always @(posedge wrclk) wrusedw <= #1 wrptr - rdptr; always @(posedge rdclk) rdusedw <= #1 wrptr - rdptr; endmodule // fifo_1c_4k
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_V `define SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_V /* * srsdfxtp: Scan flop with sleep mode, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v" `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v" `include "../../models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v" `celldefine module sky130_fd_sc_lp__srsdfxtp ( Q , CLK , D , SCD , SCE , SLEEP_B ); // Module ports output Q ; input CLK ; input D ; input SCD ; input SCE ; input SLEEP_B; // Module supplies supply1 KAPWR; supply1 VPWR ; supply0 VGND ; supply1 VPB ; supply0 VNB ; // Local signals wire buf_Q ; wire mux_out ; wire pwrgood_pp0_out_Q; // Delay Name Output Other arguments sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE ); sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SLEEP_B, , KAPWR, VGND, VPWR); sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND ); buf buf0 (Q , pwrgood_pp0_out_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_V
// ---------------------------------------------------------------------- // Copyright (c) 2015, The Regents of the University of California All // rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH // DAMAGE. // ---------------------------------------------------------------------- //---------------------------------------------------------------------------- // Filename: tx_port_monitor_64.v // Version: 1.00.a // Verilog Standard: Verilog-2001 // Description: Detects transaction open/close events from the stream // of data from the tx_port_channel_gate. Filters out events and passes data // onto the tx_port_buffer. // Author: Matt Jacobsen // History: @mattj: Version 2.0 //----------------------------------------------------------------------------- `define S_TXPORTMON64_NEXT 5'b0_0001 `define S_TXPORTMON64_TXN 5'b0_0010 `define S_TXPORTMON64_READ 5'b0_0100 `define S_TXPORTMON64_END_0 5'b0_1000 `define S_TXPORTMON64_END_1 5'b1_0000 `timescale 1ns/1ns module tx_port_monitor_64 #( parameter C_DATA_WIDTH = 9'd64, parameter C_FIFO_DEPTH = 512, // Local parameters parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4), parameter C_FIFO_DEPTH_WIDTH = clog2((2*clog2(C_FIFO_DEPTH))+1), parameter C_VALID_HIST = 1 ) ( input RST, input CLK, input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate input EVT_DATA_EMPTY, // Event data FIFO is empty output EVT_DATA_RD_EN, // Event data FIFO read enable output [C_DATA_WIDTH-1:0] WR_DATA, // Output data output WR_EN, // Write enable for output data input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count output TXN, // Transaction parameters are valid input ACK, // Transaction parameter read, continue output LAST, // Channel last write output [31:0] LEN, // Channel write length (in 32 bit words) output [30:0] OFF, // Channel write offset output [31:0] WORDS_RECVD, // Count of data words received in transaction output DONE, // Transaction is closed input TX_ERR // Transaction encountered an error ); `include "functions.vh" ( syn_encoding = "user" ) ( fsm_encoding = "user" ) reg [4:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT; reg rRead=0, _rRead=0; reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}}; reg rEvent=0, _rEvent=0; reg [63:0] rReadData=64'd0, _rReadData=64'd0; reg [31:0] rWordsRecvd=0, _rWordsRecvd=0; reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0; reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0; reg rAlmostFull=0, _rAlmostFull=0; reg rLenEQ0Hi=0, _rLenEQ0Hi=0; reg rLenEQ0Lo=0, _rLenEQ0Lo=0; reg rLenLE2Lo=0, _rLenLE2Lo=0; reg rTxErr=0, _rTxErr=0; wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]); wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON64_READ wire wAllWordsRecvd = ((rAlmostAllRecvd \| (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData); assign EVT_DATA_RD_EN = rRead; assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0]; assign WR_EN = wPayloadData; // S_TXPORTMON64_READ assign TXN = rState[1]; // S_TXPORTMON64_TXN assign LAST = rReadData[0]; assign OFF = rReadData[31:1]; assign LEN = rReadData[63:32]; assign WORDS_RECVD = rWordsRecvd; assign DONE = !rState[2]; // !S_TXPORTMON64_READ // Buffer the input signals that come from outside the tx_port. always @ (posedge CLK) begin rTxErr <= #1 (RST ? 1'd0 : _rTxErr); end always @ () begin _rTxErr = TX_ERR; end // Transaction monitoring FSM. always @ (posedge CLK) begin rState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState); end always @ () begin _rState = rState; case (rState) `S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event if (rEvent) _rState = `S_TXPORTMON64_TXN; end `S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged if (ACK) _rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ); end `S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data if (rEvent) _rState = `S_TXPORTMON64_END_1; else if (wAllWordsRecvd \| rTxErr) _rState = `S_TXPORTMON64_END_0; end `S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event if (rEvent) _rState = `S_TXPORTMON64_END_1; end `S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event if (rEvent) _rState = `S_TXPORTMON64_NEXT; end default: begin _rState = `S_TXPORTMON64_NEXT; end endcase end // Manage reading from the FIFO and tracking amounts read. always @ (posedge CLK) begin rRead <= #1 (RST ? 1'd0 : _rRead); rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid); rEvent <= #1 (RST ? 1'd0 : _rEvent); rReadData <= #1 _rReadData; rWordsRecvd <= #1 _rWordsRecvd; rWordsRecvdAdv <= #1 _rWordsRecvdAdv; rAlmostAllRecvd <= #1 _rAlmostAllRecvd; rAlmostFull <= #1 _rAlmostFull; rLenEQ0Hi <= #1 _rLenEQ0Hi; rLenEQ0Lo <= #1 _rLenEQ0Lo; rLenLE2Lo <= #1 _rLenLE2Lo; end always @ () begin // Don't get to the full point in the output FIFO _rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH); // Track read history so we know when data is valid _rDataValid = ((rDataValid<<1) \| (rRead & !EVT_DATA_EMPTY)); // Read until we get a (valid) event _rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN // Track detected events _rEvent = wEventData; // Save event data when valid if (wEventData) _rReadData = EVT_DATA[C_DATA_WIDTH-1:0]; else _rReadData = rReadData; // If LEN == 0, we don't want to send any data to the output _rLenEQ0Hi = (LEN[31:16] == 16'd0); _rLenEQ0Lo = (LEN[15:0] == 16'd0); // If LEN <= 2, we want to trigger the almost all received flag _rLenLE2Lo = (LEN[15:0] <= 16'd2); // Count received non-event data _rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1)); _rWordsRecvdAdv = (ACK ? 2(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1)); _rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData); end / wire [35:0] wControl0; chipscope_icon_1 cs_icon( .CONTROL0(wControl0) ); chipscope_ila_t8_512 a0( .CLK(CLK), .CONTROL(wControl0), .TRIG0({TXN, wPayloadData, wEventData, rState}), .DATA({297'd0, WR_COUNT, // 10 wPayloadData, // 1 EVT_DATA_RD_EN, // 1 RST, // 1 rTxErr, // 1 wEventData, // 1 rReadData, // 64 OFF, // 31 LEN, // 32 LAST, // 1 TXN, // 1 EVT_DATA_EMPTY, // 1 EVT_DATA, // 65 rState}) // 5 ); */ endmodule
/* * Copyright (c) 2003 Stephen Williams ([email protected]) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU * General Public License as published by the Free Software * Foundation; either version 2 of the License, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * * $Id: timer_tb.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $ */ `timescale 1us / 1us module main; wire rdy; reg reset, clk; timer dut(.rdy(rdy), .clk(clk), .reset(reset)); always begin #5 clk = 1; #5 clk = 0; end initial begin $dumpvars(0, main); #7 reset = 1; #1 if (rdy !== 0) begin $display("FAILED: reset did not clear rdy. rdy=%b", rdy); $finish; end #6 reset = 0; end always @(posedge clk) if (rdy === 1) begin $display("rdy=%b at time=%0d", rdy, $time); if ($time != 175) begin $display("FAILED: timer ran out incorrectly."); $finish; end $display("PASSED"); $finish; end endmodule // main
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 / `ifndef SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V `define SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V /* * xnor3: 3-input exclusive NOR. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! / `timescale 1ns / 1ps `default_nettype none ( blackbox *) module sky130_fd_sc_hs__xnor3 ( X , A , B , C , VPWR, VGND ); output X ; input A ; input B ; input C ; input VPWR; input VGND; endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V
////////////////////////////////////////////////////////////////////////////////// // BCHEncoderDataChannel for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Jinwoo Jeong <[email protected]> // Kibin Park <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Jinwoo Jeong <[email protected]> // Kibin Park <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: BCH encoder controller data channel // Module Name: BCHEncoderDataChannel // File Name: BCHEncoderDataChannel.v // // Version: v1.0.0 // // Description: BCH encoder controller data channel // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module BCHEncoderDataChannel # ( parameter DataWidth = 32 , parameter InnerIFLengthWidth = 16 ) ( iClock , iReset , iLength , iCmdType , iCmdValid , oCmdReady , oSrcReadData , oSrcReadValid , oSrcReadLast , iSrcReadReady , iDstReadData , iDstReadValid , iDstReadLast , oDstReadReady ); input iClock ; input iReset ; input [InnerIFLengthWidth - 1:0] iLength ; input [1:0] iCmdType ; input iCmdValid ; output oCmdReady ; output [DataWidth - 1:0] oSrcReadData ; output oSrcReadValid ; output oSrcReadLast ; input iSrcReadReady ; input [DataWidth - 1:0] iDstReadData ; input iDstReadValid ; input iDstReadLast ; output oDstReadReady ; reg [DataWidth - 1:0] rReadData ; reg rReadLast ; reg rReadValid ; wire wReadReady ; wire wReadFull ; wire wReadEmpty ; reg rDstReadReady ; parameter ECCCtrlCmdType_Bypass = 2'b00 ; parameter ECCCtrlCmdType_PageEncode = 2'b01 ; parameter ECCCtrlCmdType_SpareEncode = 2'b10 ; reg [1:0] rCmdType ; reg [InnerIFLengthWidth - 1:0] rLength ; reg [5:0] rCurLoopCount ; reg [5:0] rGoalLoopCount ; //reg [7:0] rCounter ; reg rCRCSpareSwitch ; wire wPageEncEnable ; wire wCRCEncEnable ; wire wCRCDataValid ; wire [DataWidth - 1:0] wCRCData ; reg rDstPageDataValid ; reg rDstPageDataLast ; reg [DataWidth - 1:0] rDstPageData ; reg rPageDataValid ; wire wCRCSpareSwitch ; wire wCRCParityLast ; wire wCRCParityValid ; wire [DataWidth - 1:0] wCRCParityOut ; wire wDownConverterReady ; wire wDownConvertedDataValid ; wire wDownConvertedDataLast ; wire [DataWidth/2 - 1:0] wDownConvertedData ; wire wEncoderReady ; wire wEncodeDataInReady ; wire wPageDataLast ; wire [DataWidth/2 - 1:0] wPageParityData ; wire wPageParityValid ; wire wPageParityLast ; wire wUpConverterReady ; wire wEncodeDataValid; wire [DataWidth/2 - 1:0] wEncodeData; wire wUpConvertDataValid; wire [DataWidth/2 - 1:0] wUpConvertData; wire wUpConvertedDataValid; wire wUpConvertedDataLast; reg rUpConvertedDataLast; wire wUpConvertedParityLast; wire [DataWidth - 1:0] wUpConvertedData; reg rReadReady; wire wDataBufferPopSignal ; wire wCRCAvailable ; wire wReset ; localparam State_Idle = 3'b000; localparam State_Forward = 3'b001; localparam State_Encode = 3'b011; localparam State_ParityOut = 3'b010; localparam State_LoopEnd = 3'b110; reg [2:0] rCurState ; reg [2:0] rNextState ; assign oCmdReady = (rCurState == State_Idle); assign wReadReady = !wReadFull; assign wEncodeDataValid = (rCurState == State_ParityOut) ? wPageParityValid : (rCurState == State_Encode) ? wDownConvertedDataValid : 1'b0; assign wEncodeData = (rCurState == State_ParityOut) ? wPageParityData : (rCurState == State_Encode) ? wDownConvertedData : {(DataWidth/2){1'b0}}; assign wUpConvertDataValid = (rUpConvertedDataLast \| wUpConvertedDataLast) ? 1'b0 : wEncodeDataValid; assign wEncodeDataInReady = (rCurState == State_Encode) && (wUpConverterReady & wEncoderReady); assign oDstReadReady = rDstReadReady; assign wCRCDataValid = rDstPageDataValid & wDownConverterReady; assign wCRCData = rDstPageData; assign wCRCEncEnable = (rCmdType == ECCCtrlCmdType_SpareEncode) ? 1'b0 : 1'b1; assign wPageEncEnable = 1'b1; assign wReset = (iReset) \|\| ((rCmdType == ECCCtrlCmdType_SpareEncode) && (rCurState == State_ParityOut)); always @ (posedge iClock) if (iReset) rCurState <= State_Idle; else rCurState <= rNextState; always @ (posedge iClock) if (iReset) rCRCSpareSwitch <= 0; else begin if (wCRCSpareSwitch) rCRCSpareSwitch <= 1'b1; else begin if (wPageDataLast && (rCmdType == ECCCtrlCmdType_SpareEncode)) rCRCSpareSwitch <= 1'b0; end end always @ () case (rCurState) State_Idle: if (iCmdValid) begin if (iCmdType == ECCCtrlCmdType_Bypass) rNextState <= State_Forward; else rNextState <= State_Encode; end else rNextState <= State_Idle; State_Forward: rNextState <= (iDstReadValid && iDstReadLast && oDstReadReady)?State_Idle:State_Forward; State_Encode: rNextState <= (wPageDataLast)?State_ParityOut:State_Encode; State_ParityOut: rNextState <= (wUpConvertedDataValid && wReadReady && wUpConvertedParityLast)?State_LoopEnd:State_ParityOut; State_LoopEnd: rNextState <= (rCurLoopCount == rGoalLoopCount)?State_Idle:State_Encode; default: rNextState <= State_Idle; endcase always @ (posedge iClock) if (iReset) rCmdType <= 2'b0; else case (rCurState) State_Idle: if (iCmdValid) rCmdType <= iCmdType; endcase always @ (posedge iClock) if (iReset) rLength <= {(InnerIFLengthWidth){1'b0}}; else case (rCurState) State_Idle: if (iCmdValid) rLength <= iLength; endcase /always @ (posedge iClock) if (iReset) rCounter <= {(8){1'b0}}; else case (rCurState) State_Encode: rCounter <= (iDstReadValid & oDstReadReady) ? rCounter + 1'b1 : rCounter; default: rCounter <= {(8){1'b0}}; endcase/ always @ (posedge iClock) if (iReset) rCurLoopCount <= {(6){1'b0}}; else case (rCurState) State_Idle: rCurLoopCount <= {(6){1'b0}}; State_LoopEnd: rCurLoopCount <= rCurLoopCount + 1'b1; endcase always @ (posedge iClock) if (iReset) rGoalLoopCount <= {(6){1'b0}}; else case (rCurState) State_Idle: if (iCmdValid) begin if (iCmdType == ECCCtrlCmdType_PageEncode) rGoalLoopCount <= 31; else rGoalLoopCount <= 0; end endcase /always @ () case (rCurState) State_Idle: rSpareCounter <= {(8){1'b0}}; State_Encode: if (rCRCSpareSwitch && iDstReadValid && wCRCParityLast && wDstReadReady) rSpareCounter <= rSpareCounter + 1'b1; endcase / always @ () case (rCurState) State_Encode: if (rCmdType == ECCCtrlCmdType_PageEncode) begin rDstPageData <= iDstReadData; rDstPageDataValid <= iDstReadValid; end else if (rCRCSpareSwitch) begin if (wCRCAvailable) begin rDstPageData <= {(DataWidth){1'b0}}; rDstPageDataValid <= 1'b1; end else begin rDstPageData <= wCRCParityOut; rDstPageDataValid <= wCRCParityValid; end end else begin rDstPageData <= iDstReadData; rDstPageDataValid <= iDstReadValid; end default: begin rDstPageData <= {(DataWidth){1'b0}}; rDstPageDataValid <= 1'b0; end endcase always @ (posedge iClock) if (iReset) rDstPageDataLast <= 0; else if (wCRCParityLast & rDstPageDataValid) rDstPageDataLast <= 1'b1; else rDstPageDataLast <= 1'b0; always @ (posedge iClock) if (iReset) rUpConvertedDataLast <= 0; else if (wUpConvertedDataLast) rUpConvertedDataLast <= wUpConvertedDataLast; else if (rCurState == State_ParityOut) rUpConvertedDataLast <= 0; always @ () case (rCurState) State_Forward: begin rReadData <= iDstReadData ; rReadValid <= iDstReadValid ; rReadLast <= iDstReadLast ; rDstReadReady <= wReadReady ; end State_Encode: begin rReadData <= wUpConvertedData ; rReadValid <= (rUpConvertedDataLast) ? 1'b0 : wUpConvertedDataValid ; rReadLast <= 1'b0 ; if (rCRCSpareSwitch & wCRCAvailable) rDstReadReady <= 1'b0; else rDstReadReady <= wDownConverterReady; end State_ParityOut: begin rReadData <= wUpConvertedData ; rReadValid <= wUpConvertedDataValid; rReadLast <= wUpConvertedParityLast && (rCurLoopCount == rGoalLoopCount) ; rDstReadReady <= 1'b0 ; end default: begin rReadData <= {(DataWidth){1'b0}} ; rReadValid <= 1'b0 ; rReadLast <= 1'b0 ; rDstReadReady <= 1'b0 ; end endcase CRC_Generator # ( .DATA_WIDTH (32), .HASH_LENGTH (64), .INPUT_COUNT_BITS (13), .INPUT_COUNT (4158), .OUTPUT_COUNT (2) ) CRCGenerator ( .i_clk (iClock), .i_nRESET (!iReset), .i_execute_crc_gen (wCRCEncEnable), .i_message_valid (wCRCDataValid), .i_message (wCRCData), .i_out_pause (!rDstReadReady), .o_crc_gen_start (), .o_last_message (), .o_crc_gen_complete (), .o_crc_spare_switch (wCRCSpareSwitch), .o_parity_out_strobe (wCRCParityValid), .o_parity_out_start (), .o_parity_out_complete (wCRCParityLast), .o_parity_out (wCRCParityOut), .o_crc_available (wCRCAvailable) ); EncWidthConverter32to16 #( .InputDataWidth(32), .OutputDataWidth(16) ) Inst_WidthDownConverter ( .iClock (iClock), .iReset (wReset), .iSrcDataValid (rDstPageDataValid), .iSrcDataLast (rDstPageDataLast), .iSrcData (rDstPageData), .oConverterReady (wDownConverterReady), .oConvertedDataValid (wDownConvertedDataValid), .oConvertedDataLast (wDownConvertedDataLast), .oConvertedData (wDownConvertedData), .iDstReady (wEncodeDataInReady) ); BCHEncoderX # ( .Multi(2) ) BCHPageEncoder ( .iClock (iClock), .iReset (iReset), .iEnable (wPageEncEnable), .iData (wEncodeData), .iDataValid (wEncodeDataValid), .oDataReady (wEncoderReady), .oDataLast (wPageDataLast), .oParityData (wPageParityData), .oParityValid (wPageParityValid), .oParityLast (wPageParityLast), .iParityReady (wUpConverterReady) ); EncWidthConverter16to32 #( .InputDataWidth(16), .OutputDataWidth(32) ) Inst_WidthUpConverter ( .iClock (iClock), .iReset (iReset), .iCurLoopCount (rCurLoopCount[0]), .iCmdType (rCmdType), .iSrcDataValid (wUpConvertDataValid), .iSrcDataLast (wDownConvertedDataLast), .iSrcParityLast (wPageParityLast), .iSrcData (wEncodeData), .oConverterReady (wUpConverterReady), .oConvertedDataValid (wUpConvertedDataValid), .oConvertedDataLast (wUpConvertedDataLast), .oConvertedParityLast (wUpConvertedParityLast), .oConvertedData (wUpConvertedData), .iDstReady (wReadReady) ); SCFIFO_64x64_withCount DataBuffer ( .iClock (iClock ), .iReset (iReset ), .iPushData ({rReadData, rReadLast} ), .iPushEnable (rReadValid && wReadReady ), .oIsFull (wReadFull ), .oPopData ({oSrcReadData, oSrcReadLast} ), .iPopEnable (wDataBufferPopSignal ), .oIsEmpty (wReadEmpty ), .oDataCount ( ) ); AutoFIFOPopControl DataBufferControl ( .iClock (iClock ), .iReset (iReset ), .oPopSignal (wDataBufferPopSignal ), .iEmpty (wReadEmpty ), .oValid (oSrcReadValid ), .iReady (iSrcReadReady ) ); endmodule
//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_7x_0_core_top_pipe_reset.v // Version : 3.0 //------------------------------------------------------------------------------ // Filename : pipe_reset.v // Description : PIPE Reset Module for 7 Series Transceiver // Version : 20.2 //------------------------------------------------------------------------------ `timescale 1ns / 1ps //---------- PIPE Reset Module ------------------------------------------------- (* DowngradeIPIdentifiedWarnings = "yes" ) module pcie_7x_0_core_top_pipe_reset # ( //---------- Global ------------------------------------ parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup parameter PCIE_GT_DEVICE = "GTX", parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable parameter PCIE_LANE = 1, // PCIe number of lanes //---------- Local ------------------------------------- parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK ) ( //---------- Input ------------------------------------- input RST_CLK, input RST_RXUSRCLK, input RST_DCLK, input RST_RST_N, input [PCIE_LANE-1:0] RST_DRP_DONE, input [PCIE_LANE-1:0] RST_RXPMARESETDONE, input [PCIE_LANE-1:0] RST_CPLLLOCK, input RST_QPLL_IDLE, input [PCIE_LANE-1:0] RST_RATE_IDLE, input [PCIE_LANE-1:0] RST_RXCDRLOCK, input RST_MMCM_LOCK, input [PCIE_LANE-1:0] RST_RESETDONE, input [PCIE_LANE-1:0] RST_PHYSTATUS, input [PCIE_LANE-1:0] RST_TXSYNC_DONE, //---------- Output ------------------------------------ output RST_CPLLRESET, output RST_CPLLPD, output reg RST_DRP_START, output reg RST_DRP_X16X20_MODE, output reg RST_DRP_X16, output RST_RXUSRCLK_RESET, output RST_DCLK_RESET, output RST_GTRESET, output RST_USERRDY, output RST_TXSYNC_START, output RST_IDLE, output [4:0] RST_FSM ); //---------- Input Register ---------------------------- ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] drp_done_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] cplllock_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg qpll_idle_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] rate_idle_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] rxcdrlock_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg mmcm_lock_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] resetdone_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] phystatus_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] txsync_done_reg1; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] drp_done_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] cplllock_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg qpll_idle_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] rate_idle_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] rxcdrlock_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg mmcm_lock_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] resetdone_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] phystatus_reg2; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg [PCIE_LANE-1:0] txsync_done_reg2; //---------- Internal Signal --------------------------- reg [ 5:0] cfg_wait_cnt = 6'd0; //---------- Output Register --------------------------- reg cpllreset = 1'd0; reg cpllpd = 1'd0; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg rxusrclk_rst_reg1 = 1'd0; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg rxusrclk_rst_reg2 = 1'd0; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" ) reg dclk_rst_reg1 = 1'd0; ( ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0; reg gtreset = 1'd0; reg userrdy = 1'd0; reg [4:0] fsm = 5'h2; //---------- FSM --------------------------------------- localparam FSM_IDLE = 5'h0; localparam FSM_CFG_WAIT = 5'h1; localparam FSM_CPLLRESET = 5'h2; localparam FSM_DRP_X16_START = 5'h3; localparam FSM_DRP_X16_DONE = 5'h4; localparam FSM_CPLLLOCK = 5'h5; localparam FSM_DRP = 5'h6; localparam FSM_GTRESET = 5'h7; localparam FSM_RXPMARESETDONE_1 = 5'h8; localparam FSM_RXPMARESETDONE_2 = 5'h9; localparam FSM_DRP_X20_START = 5'hA; localparam FSM_DRP_X20_DONE = 5'hB; localparam FSM_MMCM_LOCK = 5'hC; localparam FSM_RESETDONE = 5'hD; localparam FSM_CPLL_PD = 5'hE; localparam FSM_TXSYNC_START = 5'hF; localparam FSM_TXSYNC_DONE = 5'h10; //---------- Input FF ---------------------------------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) begin //---------- 1st Stage FF -------------------------- drp_done_reg1 <= {PCIE_LANE{1'd0}}; rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}}; cplllock_reg1 <= {PCIE_LANE{1'd0}}; qpll_idle_reg1 <= 1'd0; rate_idle_reg1 <= {PCIE_LANE{1'd0}}; rxcdrlock_reg1 <= {PCIE_LANE{1'd0}}; mmcm_lock_reg1 <= 1'd0; resetdone_reg1 <= {PCIE_LANE{1'd0}}; phystatus_reg1 <= {PCIE_LANE{1'd0}}; txsync_done_reg1 <= {PCIE_LANE{1'd0}}; //---------- 2nd Stage FF -------------------------- drp_done_reg2 <= {PCIE_LANE{1'd0}}; rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}}; cplllock_reg2 <= {PCIE_LANE{1'd0}}; qpll_idle_reg2 <= 1'd0; rate_idle_reg2 <= {PCIE_LANE{1'd0}}; rxcdrlock_reg2 <= {PCIE_LANE{1'd0}}; mmcm_lock_reg2 <= 1'd0; resetdone_reg2 <= {PCIE_LANE{1'd0}}; phystatus_reg2 <= {PCIE_LANE{1'd0}}; txsync_done_reg2 <= {PCIE_LANE{1'd0}}; end else begin //---------- 1st Stage FF -------------------------- drp_done_reg1 <= RST_DRP_DONE; rxpmaresetdone_reg1 <= RST_RXPMARESETDONE; cplllock_reg1 <= RST_CPLLLOCK; qpll_idle_reg1 <= RST_QPLL_IDLE; rate_idle_reg1 <= RST_RATE_IDLE; rxcdrlock_reg1 <= RST_RXCDRLOCK; mmcm_lock_reg1 <= RST_MMCM_LOCK; resetdone_reg1 <= RST_RESETDONE; phystatus_reg1 <= RST_PHYSTATUS; txsync_done_reg1 <= RST_TXSYNC_DONE; //---------- 2nd Stage FF -------------------------- drp_done_reg2 <= drp_done_reg1; rxpmaresetdone_reg2 <= rxpmaresetdone_reg1; cplllock_reg2 <= cplllock_reg1; qpll_idle_reg2 <= qpll_idle_reg1; rate_idle_reg2 <= rate_idle_reg1; rxcdrlock_reg2 <= rxcdrlock_reg1; mmcm_lock_reg2 <= mmcm_lock_reg1; resetdone_reg2 <= resetdone_reg1; phystatus_reg2 <= phystatus_reg1; txsync_done_reg2 <= txsync_done_reg1; end end //---------- Configuration Reset Wait Counter ---------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) cfg_wait_cnt <= 6'd0; else //---------- Increment Configuration Reset Wait Counter if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX)) cfg_wait_cnt <= cfg_wait_cnt + 6'd1; //---------- Hold Configuration Reset Wait Counter - else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX)) cfg_wait_cnt <= cfg_wait_cnt; //---------- Reset Configuration Reset Wait Counter else cfg_wait_cnt <= 6'd0; end //---------- PIPE Reset FSM ---------------------------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) begin fsm <= FSM_CFG_WAIT; cpllreset <= 1'd0; cpllpd <= 1'd0; gtreset <= 1'd0; userrdy <= 1'd0; end else begin case (fsm) //---------- Idle State ---------------------------- FSM_IDLE : begin if (!RST_RST_N) begin fsm <= FSM_CFG_WAIT; cpllreset <= 1'd0; cpllpd <= 1'd0; gtreset <= 1'd0; userrdy <= 1'd0; end else begin fsm <= FSM_IDLE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end end //---------- Wait for Configuration Reset Delay --- FSM_CFG_WAIT : begin fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Hold CPLL and GTX Channel in Reset ---- FSM_CPLLRESET : begin fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET); cpllreset <= 1'd1; cpllpd <= cpllpd; gtreset <= 1'd1; userrdy <= userrdy; end //---------- Wait for CPLL Lock -------------------- FSM_CPLLLOCK : begin fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK); cpllreset <= 1'd0; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for DRP Done to Setup Gen1 ------- FSM_DRP : begin fsm <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Start DRP x16 ------------------------- FSM_DRP_X16_START : begin fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for DRP x16 Done ----------------- FSM_DRP_X16_DONE : begin fsm <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Release GTX Channel Reset ------------- FSM_GTRESET : begin fsm <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= 1'b0; userrdy <= userrdy; end //---------- Wait for RXPMARESETDONE Assertion ----- FSM_RXPMARESETDONE_1 : begin fsm <= (&rxpmaresetdone_reg2 \|\| (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for RXPMARESETDONE De-assertion -- FSM_RXPMARESETDONE_2 : begin fsm <= (&(~rxpmaresetdone_reg2) \|\| (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Start DRP x20 ------------------------- FSM_DRP_X20_START : begin fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for DRP x20 Done ----------------- FSM_DRP_X20_DONE : begin fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for MMCM and RX CDR Lock --------- FSM_MMCM_LOCK : begin if (mmcm_lock_reg2 && (&rxcdrlock_reg2 \|\| (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 \|\| (PCIE_PLL_SEL == "CPLL"))) begin fsm <= FSM_RESETDONE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= 1'd1; end else begin fsm <= FSM_MMCM_LOCK; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= 1'd0; end end //---------- Wait for [TX/RX]RESETDONE and PHYSTATUS FSM_RESETDONE : begin fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2 FSM_CPLL_PD : begin fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START); cpllreset <= cpllreset; cpllpd <= (PCIE_PLL_SEL == "QPLL"); gtreset <= gtreset; userrdy <= userrdy; end //---------- Start TX Sync ------------------------- FSM_TXSYNC_START : begin fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for TX Sync Done ----------------- FSM_TXSYNC_DONE : begin fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Default State ------------------------- default : begin fsm <= FSM_CFG_WAIT; cpllreset <= 1'd0; cpllpd <= 1'd0; gtreset <= 1'd0; userrdy <= 1'd0; end endcase end end //---------- RXUSRCLK Reset Synchronizer --------------------------------------- always @ (posedge RST_RXUSRCLK) begin if (cpllreset) begin rxusrclk_rst_reg1 <= 1'd1; rxusrclk_rst_reg2 <= 1'd1; end else begin rxusrclk_rst_reg1 <= 1'd0; rxusrclk_rst_reg2 <= rxusrclk_rst_reg1; end end //---------- DCLK Reset Synchronizer ------------------------------------------- always @ (posedge RST_DCLK) begin if (fsm == FSM_CFG_WAIT) begin dclk_rst_reg1 <= 1'd1; dclk_rst_reg2 <= dclk_rst_reg1; end else begin dclk_rst_reg1 <= 1'd0; dclk_rst_reg2 <= dclk_rst_reg1; end end //---------- PIPE Reset Output ------------------------------------------------- assign RST_CPLLRESET = cpllreset; assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd); assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; assign RST_DCLK_RESET = dclk_rst_reg2; assign RST_GTRESET = gtreset; assign RST_USERRDY = userrdy; assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START); assign RST_IDLE = (fsm == FSM_IDLE); assign RST_FSM = fsm; //-------------------------------------------------------------------------------------------------- // Register Output //-------------------------------------------------------------------------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) begin RST_DRP_START <= 1'd0; RST_DRP_X16X20_MODE <= 1'd0; RST_DRP_X16 <= 1'd0; end else begin RST_DRP_START <= (fsm == FSM_DRP_X16_START) \|\| (fsm == FSM_DRP_X20_START); RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) \|\| (fsm == FSM_DRP_X16_DONE) \|\| (fsm == FSM_DRP_X20_START) \|\| (fsm == FSM_DRP_X20_DONE); RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) \|\| (fsm == FSM_DRP_X16_DONE); end end endmodule
////////////////////////////////////////////////////////////////////////////////// // NPM_Toggle_DO_tADL_DDR100 for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Ilyong Jung <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Ilyong Jung <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: NPM_Toggle_DO_tADL_DDR100 // Module Name: NPM_Toggle_DO_tADL_DDR100 // File Name: NPM_Toggle_DO_tADL_DDR100.v // // Version: v1.0.0 // // Description: NFC PM data out FSM // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module NPM_Toggle_DO_tADL_DDR100 # ( // support "serial execution" // Data Packet Width (DQ): 8 bit // iOption: set SDR/DDR mode // 0-SDR(WE#), 1-DDR(DQS) // NumOfData: 0 means 1 // -> unit: word (32 bit = 4 B) // _tADL.v // (original design: tCDQSS = 110 ns, tWPRE = 30 ns) // // tCDQSS = 250 ns => 25 cycles // tWPRE = 50 ns => 5 cycles // future -> add data buffer? parameter NumberOfWays = 4 ) ( iSystemClock , iReset , oReady , oLastStep , iStart , iOption , iTargetWay , iWriteData , iWriteLast , iWriteValid , oWriteReady , oPO_DQStrobe , oPO_DQ , oPO_ChipEnable , oPO_WriteEnable , oPO_AddressLatchEnable , oPO_CommandLatchEnable , oDQSOutEnable , oDQOutEnable ); input iSystemClock ; input iReset ; output oReady ; output oLastStep ; input iStart ; input iOption ; input [NumberOfWays - 1:0] iTargetWay ; input [31:0] iWriteData ; input iWriteLast ; input iWriteValid ; output oWriteReady ; output [7:0] oPO_DQStrobe ; output [31:0] oPO_DQ ; output [2NumberOfWays - 1:0] oPO_ChipEnable ; output [3:0] oPO_WriteEnable ; output [3:0] oPO_AddressLatchEnable ; output [3:0] oPO_CommandLatchEnable ; output oDQSOutEnable ; output oDQOutEnable ; // FSM Parameters/Wires/Regs localparam DTO_FSM_BIT = 9; // DaTa Out localparam DTO_RESET = 9'b000_000_001; localparam DTO_READY = 9'b000_000_010; localparam DTO_DQS01 = 9'b000_000_100; // info. capture, wait state for tCDQSS localparam DTO_DQS02 = 9'b000_001_000; // wait state for tCDQSS localparam DTO_WPRAM = 9'b000_010_000; // wait state for tWRPE localparam DTO_DQOUT = 9'b000_100_000; // DQ out: loop localparam DTO_PAUSE = 9'b001_000_000; // pause DQ out localparam DTO_DQLST = 9'b010_000_000; // DQ out: last localparam DTO_WPSAM = 9'b100_000_000; // wait state for tWPST localparam DTO_WPSA2 = 9'b110_000_000; // temp. state: will be removed reg [DTO_FSM_BIT-1:0] rDTO_cur_state ; reg [DTO_FSM_BIT-1:0] rDTO_nxt_state ; // Internal Wires/Regs reg rReady ; reg rLastStep ; reg rOption ; reg [4:0] rDTOSubCounter ; wire [2NumberOfWays - 1:0] wPO_ChipEnable ; wire wtCDQSSDone ; wire wtWPREDone ; wire wLoopDone ; wire wtWPSTDone ; reg [7:0] rPO_DQStrobe ; reg [31:0] rPO_DQ ; reg [2NumberOfWays - 1:0] rPO_ChipEnable ; reg [3:0] rPO_WriteEnable ; reg [3:0] rPO_AddressLatchEnable ; reg [3:0] rPO_CommandLatchEnable ; reg rDQSOutEnable ; reg rDQOutEnable ; reg rStageFlag ; // Control Signals // Target Way Decoder assign wPO_ChipEnable = { iTargetWay[NumberOfWays - 1:0], iTargetWay[NumberOfWays - 1:0] }; // Flow Control assign wtCDQSSDone = (rDTOSubCounter[4:0] == 5'd25); // 25 => 250 ns assign wtWPREDone = (rDTOSubCounter[4:0] == 5'd30); // 30 - 25 = 5 => 50 ns assign wLoopDone = iWriteLast & iWriteValid; assign wtWPSTDone = (rDTOSubCounter[4:0] == 5'd3); // 3 - 0 = 3 => 30 ns, tWPST = 6.5 ns // FSM: DaTa Out (DTO) // update current state to next state always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rDTO_cur_state <= DTO_RESET; end else begin rDTO_cur_state <= rDTO_nxt_state; end end // deside next state always @ ( ) begin case (rDTO_cur_state) DTO_RESET: begin rDTO_nxt_state <= DTO_READY; end DTO_READY: begin rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY; end DTO_DQS01: begin rDTO_nxt_state <= DTO_DQS02; end DTO_DQS02: begin rDTO_nxt_state <= (wtCDQSSDone)? DTO_WPRAM:DTO_DQS02; end DTO_WPRAM: begin rDTO_nxt_state <= (wtWPREDone)? ((iWriteValid)? DTO_DQOUT:DTO_PAUSE):DTO_WPRAM; end DTO_DQOUT: begin rDTO_nxt_state <= (rStageFlag)? (DTO_DQOUT):((wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE)); end DTO_PAUSE: begin rDTO_nxt_state <= (wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE); end DTO_DQLST: begin rDTO_nxt_state <= (rStageFlag)? DTO_DQLST:DTO_WPSAM; end DTO_WPSAM: begin rDTO_nxt_state <= (wtWPSTDone)? DTO_WPSA2:DTO_WPSAM; end DTO_WPSA2: begin rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY; end default: rDTO_nxt_state <= DTO_READY; endcase end // state behaviour always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rReady <= 0; rLastStep <= 0; rOption <= 0; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= 0; rPO_WriteEnable[3:0] <= 0; rPO_AddressLatchEnable[3:0] <= 0; rPO_CommandLatchEnable[3:0] <= 0; rDQSOutEnable <= 0; rDQOutEnable <= 0; rStageFlag <= 0; end else begin case (rDTO_nxt_state) DTO_RESET: begin rReady <= 0; rLastStep <= 0; rOption <= 0; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= 0; rPO_WriteEnable[3:0] <= 0; rPO_AddressLatchEnable[3:0] <= 0; rPO_CommandLatchEnable[3:0] <= 0; rDQSOutEnable <= 0; rDQOutEnable <= 0; rStageFlag <= 0; end DTO_READY: begin rReady <= 1; rLastStep <= 0; rOption <= 0; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= 0; rPO_WriteEnable[3:0] <= 0; rPO_AddressLatchEnable[3:0] <= 0; rPO_CommandLatchEnable[3:0] <= 0; rDQSOutEnable <= 0; rDQOutEnable <= 0; rStageFlag <= 0; end DTO_DQS01: begin rReady <= 0; rLastStep <= 0; rOption <= iOption; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= wPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b1111; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (iOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 0; end DTO_DQS02: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b1111; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 0; end DTO_WPRAM: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 1'b0; end DTO_DQOUT: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0]; rPO_DQStrobe[7:0] <= 8'b0110_0110; rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0]; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1001; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0; end DTO_PAUSE: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0]; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= { 4{rPO_DQ[31:24]} }; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 1'b0; end DTO_DQLST: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b0110_0110; rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0]; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b0001; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0; end DTO_WPSAM: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b0; rStageFlag <= 1'b0; end DTO_WPSA2: begin rReady <= 1; rLastStep <= 1; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0]; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b0; rStageFlag <= 1'b0; end endcase end end // Output assign oReady = rReady ; assign oLastStep = rLastStep ; assign oWriteReady = wtWPREDone & (~rStageFlag); assign oPO_DQStrobe = rPO_DQStrobe ; assign oPO_DQ = rPO_DQ ; assign oPO_ChipEnable = rPO_ChipEnable ; assign oPO_WriteEnable = rPO_WriteEnable ; assign oPO_AddressLatchEnable = rPO_AddressLatchEnable; assign oPO_CommandLatchEnable = rPO_CommandLatchEnable; assign oDQSOutEnable = rDQSOutEnable ; assign oDQOutEnable = rDQOutEnable ; endmodule

/* * File: pippo_if.v * Project: pippo * Designer: kiss@pwrsemi * Mainteiner: kiss@pwrsemi * Checker: * Assigner: * Description: Ò»£¬IF¶ÎµÄÖ÷Òª¹¦ÄÜÈçÏÂ 1£¬ Á¬½ÓÁ÷Ë®ÏßºÍi-side IMX²¿¼þ£º·¢ËÍÈ¡Ö¸µØÖ·ÒÔÈ¡»ØÖ¸Áî£»½«È¡»ØÖ¸ÁîºÍÖ¸ÁîµØÖ·ËÍÈëÁ÷Ë®Ïß¼Ä´æÆ÷£» 2£¬ ¸üÐÂºÍÎ¬»¤PCÖµ 3£¬ ´¦ÀíºóÐøÁ÷Ë®Ïß·¢³öµÄÌø×ªÇëÇó 4£¬ Èç¹ûIF¶ÎÓÐexception·¢Éú£¬½«Ïà¹ØÇëÇóÐÅºÅËÍÖÁºó¶ËÁ÷Ë®µÈ´ýexceptÄ£¿éÍ³Ò»´¦Àí ¶þ£¬Éè¼Æ¹æ·¶ NPCµÄÀ´Ô´·ÖÀà£º 1£¬ Ë³ÐòÈ¡Ö¸£¬PC+4 2£¬ ·ÖÖ§Ìø×ª£¬npc_branchÀ´×Ô·ÖÖ§´¦ÀíÄ£¿é(¸ù¾ÝEXE¶ÎÖ´ÐÐ½á¹û´ÓÌø×ªÄ¿±êµØÖ·»òSNIAÖÐÑ¡Ôñ) 3£¬ ÖÐ¶Ï´¦Àí£¬npc_exceptÀ´×ÔÖÐ¶Ï´¦ÀíÄ£¿é£¬ÎªÖÐ¶Ï´¦Àí³ÌÐòÈë¿ÚµØÖ· 4£¬ ÌØÊâÖ¸ÁîÖ´ÐÐ£¨rfi/rfciµÈ£©£¬npc_instÀ´×Ôsrr0/srr2¼Ä´æÆ÷£¨Î»ÓÚexceptÄ£¿é£©£» 5£¬ Í¬²½Ö¸ÁîÖ´ÐÐ£¨ÏÔÐÔÖ¸Áîisync/eieio/syncºÍmtmsrµÈÒþÐÔÖ¸Áî£©£¬npc_syncÀ´×ÔÍ¬²½Ö¸ÁîµÄSNIA£» PCÎ¬»¤ºÍ¸üÐÂ£º 1£¬ Õý³£Çé¿ö£Ë³ÐòÖ¸ÁîÁ÷£¬Ê¹ÓÃNPC¸üÐÂPC¼Ä´æÆ÷ 2£¬ Ë³ÐòÖ¸ÁîÁ÷Ë®Ïß¶³½áÊ±£¬±£³ÖÏÖÓÐPCÖµ£¬µÈ´ý¶³½á½â³ýºó¼ÌÐøÈ¡Ö¸ 3£¬ Ö¸ÁîÁ÷±ä»» 1£©ÖÐ¶Ï´¦Àí£ºEXE¶Î£¬ÖÐ¶Ï´¦Àí¿ªÊ¼£¨°üÀ¨rfi/rfci£©£¬·¢³öflush_exceptÐÅºÅ£»µÈ´ýnpc_exceptÓÐÐ§ºó¸üÐÂPC²¢È¡Ö¸ 2£©·ÖÖ§Ö¸Áî´¦Àí£ÏÖ²ÉÓÃa·½°¸ a£©²ÉÓÃ¾²Ì¬·ÖÖ§Ô¤²â¼¼Êõ£¬ËùÓÐ·ÖÖ§Ö¸Áî¶¼Ô¤²âÎªNT¡£µ±ÔÚEXE¶Î»ñÈ¡·ÖÖ§½á¹ûÎªTakenÊ±£¬·¢³öflush_branchÐÅºÅ£¬ È»ºóµÈ´ýnpc_branchÓÐÐ§ºó¸üÐÂPC²¢È¡Ö¸¡£µ±Ô¤²âÕýÈ·Ê±£¬°´ÕÕÈçÉÏË³ÐòÖ¸ÁîÁ÷´¦Àí·½·¨¡£ b£©ID¶Î·¢ÏÖ·ÖÖ§Ö¸Áî£¬·¢³öbp_stallÐÅºÅ£¬´ËÊ±ÏÂÒ»ÌõÖ¸ÁîµÄÈ¡Ö¸ÉÐÎ´Íê³É£¨Ëø´æ½øÈëÁ÷Ë®Ïß£©¡£ ¸ù¾ÝEXE¶Î½á¹û£º branch_taken Ìø×ª¡£Ê¹ÓÃnpc_branch¸üÐÂpc²¢È¡Ö¸ branch_nt ²»Ìø×ª¡£Ê¹ÓÃÏÖpcÈ¡Ö¸ ×¢£ºflushpipeÐÅºÅÎªÒÔÉÏÁ½ÖÖÇé¿öµÄ×ÛºÏ£¬ÓÉpipectrlÄ£¿é²úÉú IMX½Ó¿Ú´¦Àí£°üº¬¸´ÔÓµÄ·Ö²¼Ê½ÐÍ¬ È¡Ö¸ÇëÇóµÄ·¢ËÍ£¸ù¾Ý´¦ÀíÆ÷Á÷Ë®Ïß×´Ì¬ºÍIMX·µ»ØµÄ×´Ì¬£¬Í¬²½¸üÐÂÈ¡Ö¸ÇëÇóºÍÈ¡Ö¸µØÖ·£¨PC£© rqt_validÂß¼£È¡¾öÓÚÁ÷Ë®Ïß×´Ì¬ PC¸üÐÂÂß¼£È¡¾öÓÚÁ÷Ë®Ïß×´Ì¬ºÍIMX·µ»Ø×´Ì¬ È¡Ö¸ÏìÓ¦µÄ½ÓÊÕ£Í¬ÑùÐèÒª¸ù¾Ý´¦ÀíÆ÷Á÷Ë®Ïß×´Ì¬ºÍIMX·µ»ØµÄ×´Ì¬£¬¾ö¶¨ÊÇ·ñ¼Ä´æµ±Ç°ÏìÓ¦½øÈëÁ÷Ë®Ïß È¡Ö¸ÇëÇóµÄÈ¡ÏûºÍ±ä»»Çé¿öµÄ´¦Àí ÓÐÐ§·µ»Ø²¢²»Ò»¶¨»á½øÈëÁ÷Ë®Ïß Èý£¬IF/IDÁ÷Ë®¼Ä´æÆ÷Âß¼-Á÷Ë®Êä³ö°üÀ¨id_valid, id_inst, id_cia, id_snia£»Á÷Ë®Î¬»¤ºÍ¸üÐÂ²ßÂÔ²Î¿¼pipectrlÄ£¿é£¬»ù±¾ÈçÏÂ£º 1£¬ Õý³£Çé¿ö£È¡Ö¸³É¹¦£¬ÇÒÁ÷Ë®ÏßÕý³££º¼Ä´æ²¢ËÍ³öÈ¡»ØÖ¸Áî 2£¬ ÖÐ¶Ï´¦Àí¿ªÊ¼£¬exceptÄ£¿é·¢³öflushpipeÐÅºÅÒÔË¢ÐÂÁ÷Ë®Ïß£º²åÈëNOP£¬²¢ÖÃid_validÎªÎÞÐ§ 3£¬ µ±Á÷Ë®Ïß¶³½á£¨if_freeze»òid_freezeÓÐÐ§£©Ê±£¬IF/ID²åÈëNOP»òKCS bubble °üÀ¨µÈ´ý×ÜÏßÏìÓ¦£¨ack_i/err_iÎÞÐ§£¬¼´if_stall£©£¬¶øÆäËûÕý³£Ê±£» * Task.I: [TBD]imxÐÒéÑéÖ¤ºÍ¸Ä½ø Ä¿Ç°i-imx²ÉÓÃ·ÖÀëµÄµØÖ·ºÍÊý¾Ýtsc´«Êä£¬²¢Ö§³ÖÒ»¼¶pipeling·½Ê½£» Ä¿Ç°rqt_valid×ÜÊÇÓÐÐ§£³ýÁ÷Ë®ÏßË¢ÐÂ(flushpipe)ºÍ¶³½á(id_freeze)Ê±£» ÔÚslave·µ»ØµØÖ·ÏìÓ¦(!rty_i)ºó£¬PC¸üÐÂ£¬·¢³öÐÂµÄµØÖ·ÇëÇó£¼ä½Ó±£Ö¤²»»áÖØ¸´ËÍ³öÖ®Ç°µÄµØÖ·ÇëÇó Èç¹ûÔÚµØÖ·ÏìÓ¦ºÍÊý¾ÝÏìÓ¦Ö®¼ä²åÈëµÈ´ýÖÜÆÚ(¼´!rty_iºÍack_iÖ®¼ä)£¬slaveÐë±£Ö¤¹¤×÷Õý³££ÇëÇóÍê³ÉË³Ðò ¼õÉÙimc·µ»ØµÄaddrÎ»¿í£¬»òÕß[1:0]Ò²²»ÐèÒª£» µØÖ·ÇëÇóºÍÏìÓ¦£¨rqt->!rty_i£©Âß¼»ØÂ·£Ä£¿éÖ®¼ä¶¼ÊÇ×éºÏÂß¼£¨fetcherºÍbiu/imc£©£¬ÇÒÐè×¢ÒâÏßÑÓÊ±£» ¸´Î»Çé¿öµÄÑéÖ¤£slave±ØÐëÍ¬²½£¬±ÜÃâÈ¡»Ø¸´Î»Ö®Ç°ÇëÇóµÄÊý¾Ý£» IMXÏÂµØÖ·½×¶ÎºÍÊý¾Ý½×¶ÎÍ¬Ê±½áÊøµÄÇé¿ö´¦Àí£¬¼´(!rty)ºÍackÍ¬Ê±ÓÐÐ§ ºÍwbv4¹æ·¶µÄÒìÍ¬ ÊÇ·ñÉèÖÃtsc_busyÎ»±íÊ¾×ÜÏß´«Êä½øÐÐÖÐ£» ´ý±È½Ïwb¹æ·¶ÖÐ!rty_iµÄÊ±ÐòÎÊÌâ£ºÍack_iµÄ¹ØÏµ£» [TBV]È¡Ö¸Âß¼ÔÚÈ¡Ö¸¶³½á£¬Á÷Ë®ÏßË¢ÐÂ£¬if_stallºÍµ±Ç°È¡Ö¸Ëù´¦½×¶ÎµÈ¸÷ÖÖÇé¿ö½áºÏÏÂµÄ´¦ÀíºÍÉè¼ÆÑéÖ¤ ¼´PCµÄÎ¬»¤£¨°üÀ¨NPCÂß¼£©ºÍrqt_validµÄÍ¬²½¸üÐÂ±ØÐë±£Ö¤ 1£¬·¢³öÕýÈ·µÄÈ¡Ö¸ÇëÇó£¸ù¾Ýµ±Ç°Á÷Ë®Ïß×´Ì¬£» 2£¬½ö¼Ä´æÒ»´ÎÖ¸Áî½øÈëÁ÷Ë®Ïß£» 3£¬²»»á·¢ÉúÖØ¸´È¡Ö¸ºÍ²»»á¶ªÊ§È¡»ØµÄÖ¸Áî£» [TBD]µ±Á÷Ë®Ïß·µ»ØÈ¡Ö¸´íÎó£¨err_i£©Ê±£¬ÏàÓ¦exceptÇëÇóÔÚEXE¶Î½«µÃµ½´¦Àí£»ciaËÍÈëÁ÷Ë®Ïß£¬ÖÃid_validÎª0£» err_iÈ¡»ØµÄÊý¾ÝÊÇÊ²Ã´£¿ËÍÈëÁ÷Ë®Ïß»áÔÚid¶Î²úÉúÆäËûÐÐÎª£¿ ¿¼ÂÇ²åÈëNOPÒÔ±ÜÃâ´íÎóÊý¾ÝµÄ¸±×÷ÓÃ£¬»òÓÃid_validÖÃËùÓÐid¶ÎÊä³öÎªÎÞÐ§£» [TBV] imx, pipelining and PC bahavior 1. npc_branch, npc_except can't assert simultaneously 2. after recover from freezing, first fetch request from previous pc/npc? 3. the case of canceling fetch request(cache miss, and inst transfer event happened) processing by imx protocol: diassert rqt, then diassert ack. 4. check id_snia timing 5. coding style of pipelining register [TBD]make "itlb, immu" logic conditional * Task.II: * full synthesis & verification * rtl performance refactor-improve speed, reduce power and area. * to improve fetch performance, add buffer to register fetched instruction and address at some case */ // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "def_pippo.v" module pippo_if( clk, rst, iimx_adr_o, iimx_rqt_o, iimx_rty_i, iimx_ack_i, iimx_err_i, iimx_dat_i, iimx_adr_i, npc_branch, npc_except, npc_branch_valid, npc_except_valid, pc_freeze, if_stall, if_freeze, id_freeze, flushpipe, id_inst, id_cia, id_valid, id_snia, id_sig_ibuserr ); input clk; input rst; // IMX I/F to fetch instructions (from cache/ocm/memory controller) input [31:0] iimx_dat_i; input iimx_ack_i; input iimx_err_i; input [31:0] iimx_adr_i; input iimx_rty_i; output [31:0] iimx_adr_o; output iimx_rqt_o; // inst. flow transfer input [29:0] npc_branch; input npc_branch_valid; input [31:0] npc_except; // keep least two address bits to code ISR entrance easily. input npc_except_valid; // pipeline control input pc_freeze; input if_freeze; input id_freeze; input flushpipe; output if_stall; // pipeling register output id_valid; output [31:0] id_inst; output [29:0] id_cia; output [29:0] id_snia; // exception request output id_sig_ibuserr; // // // reg id_valid; reg [31:0] id_inst; reg [29:0] id_cia; reg [29:0] id_snia; reg id_sig_ibuserr; reg [31:0] npc_value; reg if_valid; reg [31:0] if_inst; reg [29:0] if_cia; reg if_sig_ibuserr; reg [31:0] pc; wire if_rqt_valid; wire [32:0] pcadd4; wire except_ibuserr; // // send fetch rqt to I-IMX // assign iimx_adr_o = pc; assign iimx_rqt_o = if_rqt_valid; // stall request, waiting for I-IMX response assign if_stall = ~iimx_ack_i; // // PC Register logic // // NPC source assign pcadd4={(pc[31:2]+31'd1), 2'b00}; // assign fetch_lost = id_freeze & iimx_ack_i; always @(npc_branch_valid or npc_except_valid or id_freeze or iimx_adr_i or fetch_lost or npc_branch or npc_except or pc or pcadd4) begin casex ({npc_branch_valid, npc_except_valid, id_freeze, fetch_lost}) // synopsys parallel_case 4'b0000: begin npc_value = pcadd4[31:0]; end 4'b0100: begin npc_value = npc_except; end 4'b1000: begin npc_value = {npc_branch, 2'b00}; end 4'b0010: begin // if pipeline(if_freeze & id_freeze) is freezon, keep current pc npc_value = pc; end 4'b0011: begin npc_value = iimx_adr_i; // fetch current fetched instruction again end default: begin npc_value = pc; end endcase end // // PC update policy // // 1. after hard reset, keep RESET_VECTOR (pcadd4[32]) to avoid overflow // 2. update pc when // a) flushpipe: flush pipeline, fetch with npc // b) !iimx_rty_i: current transaction is complete // c) fetch lost always @(posedge clk or posedge rst) begin if (rst) pc <= #1 `pippo_RESET_VECTOR; else if (pcadd4[32] & !flushpipe) // !flushpipe: keep normal when fetched first branch inst pc <= #1 `pippo_RESET_VECTOR; else if (flushpipe | (!iimx_rty_i) | fetch_lost) pc <= #1 npc_value; end // // inst. fetch request logic: if_rqt_valid signal // 1. when flushpipe assert(pc_freeze asserts), if_rqt_valid disassert // 2. when pipeline freeze(id_freeze freeze), if_rqt_valid disassert to reduce memory access // NOT use if_freeze signal to exclude if_stall deadlock, or additional logic is needed for biu // deadloack: if_freeze assert at wait state, if you diassert this request, system stop forever. // 3. hard-reset case: if_rqt_valid assert until RESET_VECTOR's ack(!iimx_rty_i) come, then keep disassertion. // At normal state, always send fetch request - if_rqt_valid keep assert, when address ack(!iimx_rty_i) assert // or disassert. including case that if_stall asserts, to avoid deadlock: no new fetch send out // deadlock: (if_stall raised -> if_freeze assert -> rqt_valid disassert forever) // after hard reset, to avoid fetch reset vector many times, // "!flushpipe" logic is to reduce one cycle delay after reset vector's branch reg rst_rqt_done; always @(posedge clk or posedge rst) begin if (rst) rst_rqt_done <= #1 1'b0; else if (flushpipe) rst_rqt_done <= #1 1'b0; else if (pcadd4[32] & !iimx_rty_i) rst_rqt_done <= #1 1'b1; end // to check the timing of rqt_valid signal - rqt_valid must have budget for addr_ack logic, i.e.: // at IMX address phase(cycle 1): // Master send out if_rqt_valid, slave check address and give back addr_ack; // Addr_ack(!iimx_rty_i) signal must satisfy the setup time, when inputting to master; // [TBD] register out if_rqt_valid signal to improve timing, add a pipeline bubble under some case // note: keep pace with pc update assign if_rqt_valid = !(pc_freeze | id_freeze | (pcadd4[32] & rst_rqt_done)); // // IF/ID pipelining logic // always @(iimx_ack_i or if_freeze or id_freeze or flushpipe or if_valid or if_inst or if_cia or id_valid or id_inst or id_cia or iimx_dat_i or iimx_adr_i or except_ibuserr or id_sig_ibuserr) begin casex ({iimx_ack_i, if_freeze, id_freeze, flushpipe}) // synopsys parallel_case 4'b1000: begin // Normal pipelining. I-IMX returns valid value if_valid = 1'b1; if_inst = iimx_dat_i; if_cia = iimx_adr_i[31:2]; if_sig_ibuserr = except_ibuserr; end 4'bxxx1: begin // flushpipe is asserted, insert NOP bubble if_valid = 1'b0; if_inst = `pippo_PWR_NOP; if_cia = id_cia; if_sig_ibuserr = 1'b0; end 4'bx100: begin // if_freeze is asserted, id_freeze is disasserted, insert NOP bubble if_valid = 1'b0; if_inst = `pippo_PWR_NOP; if_cia = id_cia; if_sig_ibuserr = 1'b0; end 4'bx110: begin // if_freeze/id_freeze is asserted, insert KCS bubble if_valid = id_valid; if_inst = id_inst; if_cia = id_cia; if_sig_ibuserr = id_sig_ibuserr; end default: begin // [TBV]iimx_err_i is asserted if_valid = 1'b0; if_inst = `pippo_PWR_NOP; if_cia = id_cia; if_sig_ibuserr = except_ibuserr; end endcase end always @(posedge clk or posedge rst) begin if(rst) begin id_valid <= #1 1'b0; id_inst <= #1 `pippo_PWR_NOP; id_cia <= #1 30'd0; id_snia <= #1 30'd0; id_sig_ibuserr = 1'b0; end else begin id_valid <= #1 if_valid; id_inst <= #1 if_inst; id_cia <= #1 if_cia; id_snia <= #1 pcadd4[31:2]; id_sig_ibuserr = if_sig_ibuserr; `ifdef pippo_VERBOSE // synopsys translate_off $display("%t: id_valid <= %h", $time, id_valid); $display("%t: id_inst <= %h", $time, id_inst); $display("%t: id_cia <= %h", $time, id_cia); $display("%t: id_snia <= %h", $time, id_snia); // synopsys translate_on `endif end end // // except request from IF stage // assign except_ibuserr = iimx_err_i & iimx_ack_i; // err valid only when ack assert endmodule

// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014 // Date : Thu Jul 24 13:40:01 2014 // Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim // D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_funcsim.v // Design : fifo_generator_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7z020clg484-1 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v12_0,Vivado 2014.1" *) (* CHECK_LICENSE_TYPE = "fifo_generator_0,fifo_generator_v12_0,{}" *) (* core_generation_info = "fifo_generator_0,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=16,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=2,C_AXIS_TKEEP_WIDTH=2,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* NotValidForBitStream *) module fifo_generator_0 (wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, empty, valid); input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [9:0]din; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; output [9:0]dout; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; output valid; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire rd_clk; wire rd_en; wire rd_rst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; wire NLW_U0_almost_empty_UNCONNECTED; wire NLW_U0_almost_full_UNCONNECTED; wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; wire NLW_U0_axi_ar_overflow_UNCONNECTED; wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; wire NLW_U0_axi_ar_prog_full_UNCONNECTED; wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; wire NLW_U0_axi_ar_underflow_UNCONNECTED; wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; wire NLW_U0_axi_aw_overflow_UNCONNECTED; wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; wire NLW_U0_axi_aw_prog_full_UNCONNECTED; wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; wire NLW_U0_axi_aw_underflow_UNCONNECTED; wire NLW_U0_axi_b_dbiterr_UNCONNECTED; wire NLW_U0_axi_b_overflow_UNCONNECTED; wire NLW_U0_axi_b_prog_empty_UNCONNECTED; wire NLW_U0_axi_b_prog_full_UNCONNECTED; wire NLW_U0_axi_b_sbiterr_UNCONNECTED; wire NLW_U0_axi_b_underflow_UNCONNECTED; wire NLW_U0_axi_r_dbiterr_UNCONNECTED; wire NLW_U0_axi_r_overflow_UNCONNECTED; wire NLW_U0_axi_r_prog_empty_UNCONNECTED; wire NLW_U0_axi_r_prog_full_UNCONNECTED; wire NLW_U0_axi_r_sbiterr_UNCONNECTED; wire NLW_U0_axi_r_underflow_UNCONNECTED; wire NLW_U0_axi_w_dbiterr_UNCONNECTED; wire NLW_U0_axi_w_overflow_UNCONNECTED; wire NLW_U0_axi_w_prog_empty_UNCONNECTED; wire NLW_U0_axi_w_prog_full_UNCONNECTED; wire NLW_U0_axi_w_sbiterr_UNCONNECTED; wire NLW_U0_axi_w_underflow_UNCONNECTED; wire NLW_U0_axis_dbiterr_UNCONNECTED; wire NLW_U0_axis_overflow_UNCONNECTED; wire NLW_U0_axis_prog_empty_UNCONNECTED; wire NLW_U0_axis_prog_full_UNCONNECTED; wire NLW_U0_axis_sbiterr_UNCONNECTED; wire NLW_U0_axis_underflow_UNCONNECTED; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_m_axi_arvalid_UNCONNECTED; wire NLW_U0_m_axi_awvalid_UNCONNECTED; wire NLW_U0_m_axi_bready_UNCONNECTED; wire NLW_U0_m_axi_rready_UNCONNECTED; wire NLW_U0_m_axi_wlast_UNCONNECTED; wire NLW_U0_m_axi_wvalid_UNCONNECTED; wire NLW_U0_m_axis_tlast_UNCONNECTED; wire NLW_U0_m_axis_tvalid_UNCONNECTED; wire NLW_U0_overflow_UNCONNECTED; wire NLW_U0_prog_empty_UNCONNECTED; wire NLW_U0_prog_full_UNCONNECTED; wire NLW_U0_rd_rst_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_s_axis_tready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire NLW_U0_underflow_UNCONNECTED; wire NLW_U0_wr_ack_UNCONNECTED; wire NLW_U0_wr_rst_busy_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; wire [3:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; wire [15:0]NLW_U0_m_axis_tdata_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; wire [1:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [1:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; wire [3:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; wire [3:0]NLW_U0_wr_data_count_UNCONNECTED; (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "16" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "2" *) (* C_AXIS_TSTRB_WIDTH = "2" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "4" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "10" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "10" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "1" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "11" *) (* C_IMPLEMENTATION_TYPE_RACH = "12" *) (* C_IMPLEMENTATION_TYPE_RDCH = "11" *) (* C_IMPLEMENTATION_TYPE_WACH = "12" *) (* C_IMPLEMENTATION_TYPE_WDCH = "11" *) (* C_IMPLEMENTATION_TYPE_WRCH = "12" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "13" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "12" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "4" *) (* C_RD_DEPTH = "16" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "4" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "4" *) (* C_WR_DEPTH = "16" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "4" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) fifo_generator_0fifo_generator_v12_0__parameterized0 U0 (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), .almost_full(NLW_U0_almost_full_UNCONNECTED), .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), .axi_ar_injectdbiterr(1'b0), .axi_ar_injectsbiterr(1'b0), .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), .axi_aw_injectdbiterr(1'b0), .axi_aw_injectsbiterr(1'b0), .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), .axi_b_injectdbiterr(1'b0), .axi_b_injectsbiterr(1'b0), .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), .axi_r_injectdbiterr(1'b0), .axi_r_injectsbiterr(1'b0), .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), .axi_w_injectdbiterr(1'b0), .axi_w_injectsbiterr(1'b0), .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), .axis_injectdbiterr(1'b0), .axis_injectsbiterr(1'b0), .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), .data_count(NLW_U0_data_count_UNCONNECTED[3:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), .empty(empty), .full(full), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .int_clk(1'b0), .m_aclk(1'b0), .m_aclk_en(1'b0), .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), .m_axi_arready(1'b0), .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), .m_axi_bid(1'b0), .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), .m_axi_bresp({1'b0,1'b0}), .m_axi_buser(1'b0), .m_axi_bvalid(1'b0), .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rid(1'b0), .m_axi_rlast(1'b0), .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), .m_axi_rresp({1'b0,1'b0}), .m_axi_ruser(1'b0), .m_axi_rvalid(1'b0), .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), .m_axi_wready(1'b0), .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[15:0]), .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[1:0]), .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), .m_axis_tready(1'b0), .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[1:0]), .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(NLW_U0_prog_empty_UNCONNECTED), .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0}), .prog_full(NLW_U0_prog_full_UNCONNECTED), .prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[3:0]), .rd_en(rd_en), .rd_rst(rd_rst), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), .rst(1'b0), .s_aclk(1'b0), .s_aclk_en(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_arid(1'b0), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_aruser(1'b0), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awuser(1'b0), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wid(1'b0), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser(1'b0), .s_axi_wvalid(1'b0), .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axis_tdest(1'b0), .s_axis_tid(1'b0), .s_axis_tkeep({1'b0,1'b0}), .s_axis_tlast(1'b0), .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), .s_axis_tstrb({1'b0,1'b0}), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .sleep(1'b0), .srst(1'b0), .underflow(NLW_U0_underflow_UNCONNECTED), .valid(valid), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[3:0]), .wr_en(wr_en), .wr_rst(wr_rst), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module fifo_generator_0blk_mem_gen_generic_cstr (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_prim_width \ramloop[0].ram.r (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fifo_generator_0blk_mem_gen_prim_width (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_prim_wrapper \prim_noinit.ram (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fifo_generator_0blk_mem_gen_prim_wrapper (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; (* box_type = "PRIMITIVE" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (.ADDRARDADDR({1'b0,1'b0,1'b0,1'b0,1'b0,O1,1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,I1,1'b0,1'b0,1'b0,1'b0,1'b0}), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[4:3],1'b0,1'b0,1'b0,1'b0,1'b0,din[2:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[9:8],1'b0,1'b0,1'b0,1'b0,1'b0,din[7:5]}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO({\n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[4:3],\n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[2:0]}), .DOBDO({\n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[9:8],\n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,dout[7:5]}), .DOPADOP({\n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram }), .DOPBDOP({\n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram }), .ENARDEN(tmp_ram_rd_en), .ENBWREN(E), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(rd_rst), .RSTRAMB(rd_rst), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE({E,E,E,E})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module fifo_generator_0blk_mem_gen_top (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_generic_cstr \valid.cstr (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) module fifo_generator_0blk_mem_gen_v8_2__parameterized0 (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_v8_2_synth inst_blk_mem_gen (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *) module fifo_generator_0blk_mem_gen_v8_2_synth (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_top \gnativebmg.native_blk_mem_gen (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "clk_x_pntrs" *) module fifo_generator_0clk_x_pntrs (O1, O2, O3, rd_en, p_18_out, I1, I2, I3, I4, rd_clk, rd_rst, wr_clk, wr_rst, D); output O1; output O2; output [3:0]O3; input rd_en; input p_18_out; input [3:0]I1; input [3:0]I2; input [2:0]I3; input [3:0]I4; input rd_clk; input rd_rst; input wr_clk; input wr_rst; input [2:0]D; wire [2:0]D; wire [3:0]I1; wire [3:0]I2; wire [2:0]I3; wire [3:0]I4; wire O1; wire O2; wire [3:0]O3; wire [3:0]Q; wire \n_0_gsync_stage[1].wr_stg_inst ; wire \n_0_gsync_stage[2].wr_stg_inst ; wire n_0_ram_empty_i_i_2; wire n_0_ram_empty_i_i_3; wire n_0_ram_empty_i_i_4; wire n_0_ram_empty_i_i_5; wire \n_0_rd_pntr_bin[0]_i_1 ; wire \n_0_rd_pntr_bin[1]_i_1 ; wire \n_1_gsync_stage[1].wr_stg_inst ; wire \n_1_gsync_stage[2].wr_stg_inst ; wire \n_2_gsync_stage[1].wr_stg_inst ; wire \n_2_gsync_stage[2].rd_stg_inst ; wire \n_2_gsync_stage[2].wr_stg_inst ; wire \n_3_gsync_stage[1].wr_stg_inst ; wire \n_3_gsync_stage[2].rd_stg_inst ; wire \n_3_gsync_stage[2].wr_stg_inst ; wire \n_4_gsync_stage[2].rd_stg_inst ; wire \n_4_gsync_stage[2].wr_stg_inst ; wire [3:0]p_0_in; wire [2:0]p_0_in1_out; wire p_18_out; wire [3:0]p_1_out; wire rd_clk; wire rd_en; wire [3:0]rd_pntr_gc; wire rd_rst; wire wr_clk; wire [3:0]wr_pntr_gc; wire wr_rst; fifo_generator_0synchronizer_ff \gsync_stage[1].rd_stg_inst (.I1(wr_pntr_gc), .Q(Q), .rd_clk(rd_clk), .rd_rst(rd_rst)); fifo_generator_0synchronizer_ff_0 \gsync_stage[1].wr_stg_inst (.I1(rd_pntr_gc), .Q({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst }), .wr_clk(wr_clk), .wr_rst(wr_rst)); fifo_generator_0synchronizer_ff_1 \gsync_stage[2].rd_stg_inst (.D(p_0_in[3:2]), .I1(Q), .Q({\n_2_gsync_stage[2].rd_stg_inst ,\n_3_gsync_stage[2].rd_stg_inst ,\n_4_gsync_stage[2].rd_stg_inst }), .rd_clk(rd_clk), .rd_rst(rd_rst)); fifo_generator_0synchronizer_ff_2 \gsync_stage[2].wr_stg_inst (.D({\n_0_gsync_stage[2].wr_stg_inst ,\n_1_gsync_stage[2].wr_stg_inst }), .I1({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst }), .Q({\n_2_gsync_stage[2].wr_stg_inst ,\n_3_gsync_stage[2].wr_stg_inst ,\n_4_gsync_stage[2].wr_stg_inst }), .wr_clk(wr_clk), .wr_rst(wr_rst)); LUT6 #( .INIT(64'h0010FFFF00100010)) ram_empty_i_i_1 (.I0(n_0_ram_empty_i_i_2), .I1(n_0_ram_empty_i_i_3), .I2(rd_en), .I3(p_18_out), .I4(n_0_ram_empty_i_i_4), .I5(n_0_ram_empty_i_i_5), .O(O1)); LUT4 #( .INIT(16'h6FF6)) ram_empty_i_i_2 (.I0(p_1_out[1]), .I1(I2[1]), .I2(p_1_out[0]), .I3(I2[0]), .O(n_0_ram_empty_i_i_2)); LUT4 #( .INIT(16'h6FF6)) ram_empty_i_i_3 (.I0(p_1_out[2]), .I1(I2[2]), .I2(p_1_out[3]), .I3(I2[3]), .O(n_0_ram_empty_i_i_3)); LUT4 #( .INIT(16'h6FF6)) ram_empty_i_i_4 (.I0(p_1_out[0]), .I1(I1[0]), .I2(p_1_out[2]), .I3(I1[2]), .O(n_0_ram_empty_i_i_4)); LUT4 #( .INIT(16'h9009)) ram_empty_i_i_5 (.I0(p_1_out[1]), .I1(I1[1]), .I2(p_1_out[3]), .I3(I1[3]), .O(n_0_ram_empty_i_i_5)); LUT6 #( .INIT(64'h9009000000009009)) ram_full_i_i_5 (.I0(O3[2]), .I1(I3[2]), .I2(O3[1]), .I3(I3[1]), .I4(I3[0]), .I5(O3[0]), .O(O2)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h6996)) \rd_pntr_bin[0]_i_1 (.I0(\n_3_gsync_stage[2].wr_stg_inst ), .I1(\n_4_gsync_stage[2].wr_stg_inst ), .I2(\n_0_gsync_stage[2].wr_stg_inst ), .I3(\n_2_gsync_stage[2].wr_stg_inst ), .O(\n_0_rd_pntr_bin[0]_i_1 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT3 #( .INIT(8'h96)) \rd_pntr_bin[1]_i_1 (.I0(\n_2_gsync_stage[2].wr_stg_inst ), .I1(\n_3_gsync_stage[2].wr_stg_inst ), .I2(\n_0_gsync_stage[2].wr_stg_inst ), .O(\n_0_rd_pntr_bin[1]_i_1 )); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_0_rd_pntr_bin[0]_i_1 ), .Q(O3[0])); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_0_rd_pntr_bin[1]_i_1 ), .Q(O3[1])); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_1_gsync_stage[2].wr_stg_inst ), .Q(O3[2])); FDCE #( .INIT(1'b0)) \rd_pntr_bin_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(\n_0_gsync_stage[2].wr_stg_inst ), .Q(O3[3])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(D[0]), .Q(rd_pntr_gc[0])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(D[1]), .Q(rd_pntr_gc[1])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(D[2]), .Q(rd_pntr_gc[2])); FDCE #( .INIT(1'b0)) \rd_pntr_gc_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[3]), .Q(rd_pntr_gc[3])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'h6996)) \wr_pntr_bin[0]_i_1 (.I0(\n_3_gsync_stage[2].rd_stg_inst ), .I1(\n_4_gsync_stage[2].rd_stg_inst ), .I2(p_0_in[3]), .I3(\n_2_gsync_stage[2].rd_stg_inst ), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT3 #( .INIT(8'h96)) \wr_pntr_bin[1]_i_1 (.I0(\n_2_gsync_stage[2].rd_stg_inst ), .I1(\n_3_gsync_stage[2].rd_stg_inst ), .I2(p_0_in[3]), .O(p_0_in[1])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[0]), .Q(p_1_out[0])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[1]), .Q(p_1_out[1])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[2]), .Q(p_1_out[2])); FDCE #( .INIT(1'b0)) \wr_pntr_bin_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(p_0_in[3]), .Q(p_1_out[3])); LUT2 #( .INIT(4'h6)) \wr_pntr_gc[0]_i_1 (.I0(I4[0]), .I1(I4[1]), .O(p_0_in1_out[0])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \wr_pntr_gc[1]_i_1 (.I0(I4[1]), .I1(I4[2]), .O(p_0_in1_out[1])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \wr_pntr_gc[2]_i_1 (.I0(I4[2]), .I1(I4[3]), .O(p_0_in1_out[2])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(p_0_in1_out[0]), .Q(wr_pntr_gc[0])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(p_0_in1_out[1]), .Q(wr_pntr_gc[1])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(p_0_in1_out[2]), .Q(wr_pntr_gc[2])); FDCE #( .INIT(1'b0)) \wr_pntr_gc_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I4[3]), .Q(wr_pntr_gc[3])); endmodule (* ORIG_REF_NAME = "fifo_generator_ramfifo" *) module fifo_generator_0fifo_generator_ramfifo (dout, empty, valid, full, wr_en, rd_clk, wr_clk, rd_rst, din, wr_rst, rd_en); output [9:0]dout; output empty; output valid; output full; input wr_en; input rd_clk; input wr_clk; input rd_rst; input [9:0]din; input wr_rst; input rd_en; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire \n_0_gntv_or_sync_fifo.gcx.clkx ; wire \n_10_gntv_or_sync_fifo.gl0.rd ; wire \n_1_gntv_or_sync_fifo.gcx.clkx ; wire \n_8_gntv_or_sync_fifo.gl0.rd ; wire \n_9_gntv_or_sync_fifo.gl0.rd ; wire [3:0]p_0_out; wire p_18_out; wire [3:0]p_20_out; wire p_3_out; wire [2:0]p_8_out; wire [3:0]p_9_out; wire rd_clk; wire rd_en; wire [3:0]rd_pntr_plus1; wire rd_rst; wire rst_d2; wire rst_full_gen_i; wire tmp_ram_rd_en; wire valid; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx (.D({\n_8_gntv_or_sync_fifo.gl0.rd ,\n_9_gntv_or_sync_fifo.gl0.rd ,\n_10_gntv_or_sync_fifo.gl0.rd }), .I1(p_20_out), .I2(rd_pntr_plus1), .I3(p_8_out), .I4(p_9_out), .O1(\n_0_gntv_or_sync_fifo.gcx.clkx ), .O2(\n_1_gntv_or_sync_fifo.gcx.clkx ), .O3(p_0_out), .p_18_out(p_18_out), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .wr_clk(wr_clk), .wr_rst(wr_rst)); fifo_generator_0rd_logic \gntv_or_sync_fifo.gl0.rd (.D({\n_8_gntv_or_sync_fifo.gl0.rd ,\n_9_gntv_or_sync_fifo.gl0.rd ,\n_10_gntv_or_sync_fifo.gl0.rd }), .I1(\n_0_gntv_or_sync_fifo.gcx.clkx ), .O1(p_20_out), .Q(rd_pntr_plus1), .empty(empty), .p_18_out(p_18_out), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .valid(valid)); fifo_generator_0wr_logic \gntv_or_sync_fifo.gl0.wr (.E(p_3_out), .I1(\n_1_gntv_or_sync_fifo.gcx.clkx ), .O1(p_9_out), .O3(p_0_out), .Q(p_8_out), .full(full), .rst_d2(rst_d2), .rst_full_gen_i(rst_full_gen_i), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); fifo_generator_0memory \gntv_or_sync_fifo.mem (.E(p_3_out), .I1(p_9_out), .O1(p_20_out), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fifo_generator_0reset_blk_ramfifo rstblk (.rst_d2(rst_d2), .rst_full_gen_i(rst_full_gen_i), .wr_clk(wr_clk), .wr_rst(wr_rst)); endmodule (* ORIG_REF_NAME = "fifo_generator_top" *) module fifo_generator_0fifo_generator_top (dout, empty, valid, full, wr_en, rd_clk, wr_clk, rd_rst, din, wr_rst, rd_en); output [9:0]dout; output empty; output valid; output full; input wr_en; input rd_clk; input wr_clk; input rd_rst; input [9:0]din; input wr_rst; input rd_en; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire rd_clk; wire rd_en; wire rd_rst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0fifo_generator_ramfifo \grf.rf (.din(din), .dout(dout), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .valid(valid), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule (* ORIG_REF_NAME = "fifo_generator_v12_0" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "4" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "10" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "10" *) (* C_ENABLE_RLOCS = "0" *) (* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "1" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "13" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "12" *) (* C_PROG_FULL_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "4" *) (* C_RD_DEPTH = "16" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "4" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_VALID_LOW = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "4" *) (* C_WR_DEPTH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* C_MSGON_VAL = "1" *) (* C_ENABLE_RST_SYNC = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_RUSER = "0" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_AXIS_TDATA_WIDTH = "16" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "2" *) (* C_AXIS_TKEEP_WIDTH = "2" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_AXIS_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_WACH = "12" *) (* C_IMPLEMENTATION_TYPE_WDCH = "11" *) (* C_IMPLEMENTATION_TYPE_WRCH = "12" *) (* C_IMPLEMENTATION_TYPE_RACH = "12" *) (* C_IMPLEMENTATION_TYPE_RDCH = "11" *) (* C_IMPLEMENTATION_TYPE_AXIS = "11" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_AXIS = "0" *) module fifo_generator_0fifo_generator_v12_0__parameterized0 (backup, backup_marker, clk, rst, srst, wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, prog_empty_thresh, prog_empty_thresh_assert, prog_empty_thresh_negate, prog_full_thresh, prog_full_thresh_assert, prog_full_thresh_negate, int_clk, injectdbiterr, injectsbiterr, sleep, dout, full, almost_full, wr_ack, overflow, empty, almost_empty, valid, underflow, data_count, rd_data_count, wr_data_count, prog_full, prog_empty, sbiterr, dbiterr, wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, s_aresetn, m_aclk_en, s_aclk_en, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awregion, s_axi_awuser, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wuser, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_buser, s_axi_bvalid, s_axi_bready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awregion, m_axi_awuser, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wuser, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_buser, m_axi_bvalid, m_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arregion, s_axi_aruser, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_ruser, s_axi_rvalid, s_axi_rready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arregion, m_axi_aruser, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_ruser, m_axi_rvalid, m_axi_rready, s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tstrb, s_axis_tkeep, s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tstrb, m_axis_tkeep, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser, axi_aw_injectsbiterr, axi_aw_injectdbiterr, axi_aw_prog_full_thresh, axi_aw_prog_empty_thresh, axi_aw_data_count, axi_aw_wr_data_count, axi_aw_rd_data_count, axi_aw_sbiterr, axi_aw_dbiterr, axi_aw_overflow, axi_aw_underflow, axi_aw_prog_full, axi_aw_prog_empty, axi_w_injectsbiterr, axi_w_injectdbiterr, axi_w_prog_full_thresh, axi_w_prog_empty_thresh, axi_w_data_count, axi_w_wr_data_count, axi_w_rd_data_count, axi_w_sbiterr, axi_w_dbiterr, axi_w_overflow, axi_w_underflow, axi_w_prog_full, axi_w_prog_empty, axi_b_injectsbiterr, axi_b_injectdbiterr, axi_b_prog_full_thresh, axi_b_prog_empty_thresh, axi_b_data_count, axi_b_wr_data_count, axi_b_rd_data_count, axi_b_sbiterr, axi_b_dbiterr, axi_b_overflow, axi_b_underflow, axi_b_prog_full, axi_b_prog_empty, axi_ar_injectsbiterr, axi_ar_injectdbiterr, axi_ar_prog_full_thresh, axi_ar_prog_empty_thresh, axi_ar_data_count, axi_ar_wr_data_count, axi_ar_rd_data_count, axi_ar_sbiterr, axi_ar_dbiterr, axi_ar_overflow, axi_ar_underflow, axi_ar_prog_full, axi_ar_prog_empty, axi_r_injectsbiterr, axi_r_injectdbiterr, axi_r_prog_full_thresh, axi_r_prog_empty_thresh, axi_r_data_count, axi_r_wr_data_count, axi_r_rd_data_count, axi_r_sbiterr, axi_r_dbiterr, axi_r_overflow, axi_r_underflow, axi_r_prog_full, axi_r_prog_empty, axis_injectsbiterr, axis_injectdbiterr, axis_prog_full_thresh, axis_prog_empty_thresh, axis_data_count, axis_wr_data_count, axis_rd_data_count, axis_sbiterr, axis_dbiterr, axis_overflow, axis_underflow, axis_prog_full, axis_prog_empty); input backup; input backup_marker; input clk; input rst; input srst; input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [9:0]din; input wr_en; input rd_en; input [3:0]prog_empty_thresh; input [3:0]prog_empty_thresh_assert; input [3:0]prog_empty_thresh_negate; input [3:0]prog_full_thresh; input [3:0]prog_full_thresh_assert; input [3:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; input sleep; output [9:0]dout; output full; output almost_full; output wr_ack; output overflow; output empty; output almost_empty; output valid; output underflow; output [3:0]data_count; output [3:0]rd_data_count; output [3:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; output dbiterr; output wr_rst_busy; output rd_rst_busy; input m_aclk; input s_aclk; input s_aresetn; input m_aclk_en; input s_aclk_en; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input [3:0]s_axi_awregion; input [0:0]s_axi_awuser; input s_axi_awvalid; output s_axi_awready; input [0:0]s_axi_wid; input [63:0]s_axi_wdata; input [7:0]s_axi_wstrb; input s_axi_wlast; input [0:0]s_axi_wuser; input s_axi_wvalid; output s_axi_wready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output [0:0]s_axi_buser; output s_axi_bvalid; input s_axi_bready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awqos; output [3:0]m_axi_awregion; output [0:0]m_axi_awuser; output m_axi_awvalid; input m_axi_awready; output [0:0]m_axi_wid; output [63:0]m_axi_wdata; output [7:0]m_axi_wstrb; output m_axi_wlast; output [0:0]m_axi_wuser; output m_axi_wvalid; input m_axi_wready; input [0:0]m_axi_bid; input [1:0]m_axi_bresp; input [0:0]m_axi_buser; input m_axi_bvalid; output m_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input [3:0]s_axi_arregion; input [0:0]s_axi_aruser; input s_axi_arvalid; output s_axi_arready; output [0:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output [0:0]s_axi_ruser; output s_axi_rvalid; input s_axi_rready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; output [3:0]m_axi_arregion; output [0:0]m_axi_aruser; output m_axi_arvalid; input m_axi_arready; input [0:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; input [0:0]m_axi_ruser; input m_axi_rvalid; output m_axi_rready; input s_axis_tvalid; output s_axis_tready; input [15:0]s_axis_tdata; input [1:0]s_axis_tstrb; input [1:0]s_axis_tkeep; input s_axis_tlast; input [0:0]s_axis_tid; input [0:0]s_axis_tdest; input [3:0]s_axis_tuser; output m_axis_tvalid; input m_axis_tready; output [15:0]m_axis_tdata; output [1:0]m_axis_tstrb; output [1:0]m_axis_tkeep; output m_axis_tlast; output [0:0]m_axis_tid; output [0:0]m_axis_tdest; output [3:0]m_axis_tuser; input axi_aw_injectsbiterr; input axi_aw_injectdbiterr; input [3:0]axi_aw_prog_full_thresh; input [3:0]axi_aw_prog_empty_thresh; output [4:0]axi_aw_data_count; output [4:0]axi_aw_wr_data_count; output [4:0]axi_aw_rd_data_count; output axi_aw_sbiterr; output axi_aw_dbiterr; output axi_aw_overflow; output axi_aw_underflow; output axi_aw_prog_full; output axi_aw_prog_empty; input axi_w_injectsbiterr; input axi_w_injectdbiterr; input [9:0]axi_w_prog_full_thresh; input [9:0]axi_w_prog_empty_thresh; output [10:0]axi_w_data_count; output [10:0]axi_w_wr_data_count; output [10:0]axi_w_rd_data_count; output axi_w_sbiterr; output axi_w_dbiterr; output axi_w_overflow; output axi_w_underflow; output axi_w_prog_full; output axi_w_prog_empty; input axi_b_injectsbiterr; input axi_b_injectdbiterr; input [3:0]axi_b_prog_full_thresh; input [3:0]axi_b_prog_empty_thresh; output [4:0]axi_b_data_count; output [4:0]axi_b_wr_data_count; output [4:0]axi_b_rd_data_count; output axi_b_sbiterr; output axi_b_dbiterr; output axi_b_overflow; output axi_b_underflow; output axi_b_prog_full; output axi_b_prog_empty; input axi_ar_injectsbiterr; input axi_ar_injectdbiterr; input [3:0]axi_ar_prog_full_thresh; input [3:0]axi_ar_prog_empty_thresh; output [4:0]axi_ar_data_count; output [4:0]axi_ar_wr_data_count; output [4:0]axi_ar_rd_data_count; output axi_ar_sbiterr; output axi_ar_dbiterr; output axi_ar_overflow; output axi_ar_underflow; output axi_ar_prog_full; output axi_ar_prog_empty; input axi_r_injectsbiterr; input axi_r_injectdbiterr; input [9:0]axi_r_prog_full_thresh; input [9:0]axi_r_prog_empty_thresh; output [10:0]axi_r_data_count; output [10:0]axi_r_wr_data_count; output [10:0]axi_r_rd_data_count; output axi_r_sbiterr; output axi_r_dbiterr; output axi_r_overflow; output axi_r_underflow; output axi_r_prog_full; output axi_r_prog_empty; input axis_injectsbiterr; input axis_injectdbiterr; input [9:0]axis_prog_full_thresh; input [9:0]axis_prog_empty_thresh; output [10:0]axis_data_count; output [10:0]axis_wr_data_count; output [10:0]axis_rd_data_count; output axis_sbiterr; output axis_dbiterr; output axis_overflow; output axis_underflow; output axis_prog_full; output axis_prog_empty; wire \<const0> ; wire \<const1> ; wire axi_ar_injectdbiterr; wire axi_ar_injectsbiterr; wire [3:0]axi_ar_prog_empty_thresh; wire [3:0]axi_ar_prog_full_thresh; wire axi_aw_injectdbiterr; wire axi_aw_injectsbiterr; wire [3:0]axi_aw_prog_empty_thresh; wire [3:0]axi_aw_prog_full_thresh; wire axi_b_injectdbiterr; wire axi_b_injectsbiterr; wire [3:0]axi_b_prog_empty_thresh; wire [3:0]axi_b_prog_full_thresh; wire axi_r_injectdbiterr; wire axi_r_injectsbiterr; wire [9:0]axi_r_prog_empty_thresh; wire [9:0]axi_r_prog_full_thresh; wire axi_w_injectdbiterr; wire axi_w_injectsbiterr; wire [9:0]axi_w_prog_empty_thresh; wire [9:0]axi_w_prog_full_thresh; wire axis_injectdbiterr; wire axis_injectsbiterr; wire [9:0]axis_prog_empty_thresh; wire [9:0]axis_prog_full_thresh; wire backup; wire backup_marker; wire clk; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire injectdbiterr; wire injectsbiterr; wire int_clk; wire m_aclk; wire m_aclk_en; wire m_axi_arready; wire m_axi_awready; wire [0:0]m_axi_bid; wire [1:0]m_axi_bresp; wire [0:0]m_axi_buser; wire m_axi_bvalid; wire [63:0]m_axi_rdata; wire [0:0]m_axi_rid; wire m_axi_rlast; wire [1:0]m_axi_rresp; wire [0:0]m_axi_ruser; wire m_axi_rvalid; wire m_axi_wready; wire m_axis_tready; wire [3:0]prog_empty_thresh; wire [3:0]prog_empty_thresh_assert; wire [3:0]prog_empty_thresh_negate; wire [3:0]prog_full_thresh; wire [3:0]prog_full_thresh_assert; wire [3:0]prog_full_thresh_negate; wire rd_clk; wire rd_en; wire rd_rst; wire rst; wire s_aclk; wire s_aclk_en; wire s_aresetn; wire [31:0]s_axi_araddr; wire [1:0]s_axi_arburst; wire [3:0]s_axi_arcache; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire [0:0]s_axi_arlock; wire [2:0]s_axi_arprot; wire [3:0]s_axi_arqos; wire [3:0]s_axi_arregion; wire [2:0]s_axi_arsize; wire [0:0]s_axi_aruser; wire s_axi_arvalid; wire [31:0]s_axi_awaddr; wire [1:0]s_axi_awburst; wire [3:0]s_axi_awcache; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire [0:0]s_axi_awlock; wire [2:0]s_axi_awprot; wire [3:0]s_axi_awqos; wire [3:0]s_axi_awregion; wire [2:0]s_axi_awsize; wire [0:0]s_axi_awuser; wire s_axi_awvalid; wire s_axi_bready; wire s_axi_rready; wire [63:0]s_axi_wdata; wire [0:0]s_axi_wid; wire s_axi_wlast; wire [7:0]s_axi_wstrb; wire [0:0]s_axi_wuser; wire s_axi_wvalid; wire [15:0]s_axis_tdata; wire [0:0]s_axis_tdest; wire [0:0]s_axis_tid; wire [1:0]s_axis_tkeep; wire s_axis_tlast; wire [1:0]s_axis_tstrb; wire [3:0]s_axis_tuser; wire s_axis_tvalid; wire srst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; assign almost_empty = \<const0> ; assign almost_full = \<const0> ; assign axi_ar_data_count[4] = \<const0> ; assign axi_ar_data_count[3] = \<const0> ; assign axi_ar_data_count[2] = \<const0> ; assign axi_ar_data_count[1] = \<const0> ; assign axi_ar_data_count[0] = \<const0> ; assign axi_ar_dbiterr = \<const0> ; assign axi_ar_overflow = \<const0> ; assign axi_ar_prog_empty = \<const1> ; assign axi_ar_prog_full = \<const0> ; assign axi_ar_rd_data_count[4] = \<const0> ; assign axi_ar_rd_data_count[3] = \<const0> ; assign axi_ar_rd_data_count[2] = \<const0> ; assign axi_ar_rd_data_count[1] = \<const0> ; assign axi_ar_rd_data_count[0] = \<const0> ; assign axi_ar_sbiterr = \<const0> ; assign axi_ar_underflow = \<const0> ; assign axi_ar_wr_data_count[4] = \<const0> ; assign axi_ar_wr_data_count[3] = \<const0> ; assign axi_ar_wr_data_count[2] = \<const0> ; assign axi_ar_wr_data_count[1] = \<const0> ; assign axi_ar_wr_data_count[0] = \<const0> ; assign axi_aw_data_count[4] = \<const0> ; assign axi_aw_data_count[3] = \<const0> ; assign axi_aw_data_count[2] = \<const0> ; assign axi_aw_data_count[1] = \<const0> ; assign axi_aw_data_count[0] = \<const0> ; assign axi_aw_dbiterr = \<const0> ; assign axi_aw_overflow = \<const0> ; assign axi_aw_prog_empty = \<const1> ; assign axi_aw_prog_full = \<const0> ; assign axi_aw_rd_data_count[4] = \<const0> ; assign axi_aw_rd_data_count[3] = \<const0> ; assign axi_aw_rd_data_count[2] = \<const0> ; assign axi_aw_rd_data_count[1] = \<const0> ; assign axi_aw_rd_data_count[0] = \<const0> ; assign axi_aw_sbiterr = \<const0> ; assign axi_aw_underflow = \<const0> ; assign axi_aw_wr_data_count[4] = \<const0> ; assign axi_aw_wr_data_count[3] = \<const0> ; assign axi_aw_wr_data_count[2] = \<const0> ; assign axi_aw_wr_data_count[1] = \<const0> ; assign axi_aw_wr_data_count[0] = \<const0> ; assign axi_b_data_count[4] = \<const0> ; assign axi_b_data_count[3] = \<const0> ; assign axi_b_data_count[2] = \<const0> ; assign axi_b_data_count[1] = \<const0> ; assign axi_b_data_count[0] = \<const0> ; assign axi_b_dbiterr = \<const0> ; assign axi_b_overflow = \<const0> ; assign axi_b_prog_empty = \<const1> ; assign axi_b_prog_full = \<const0> ; assign axi_b_rd_data_count[4] = \<const0> ; assign axi_b_rd_data_count[3] = \<const0> ; assign axi_b_rd_data_count[2] = \<const0> ; assign axi_b_rd_data_count[1] = \<const0> ; assign axi_b_rd_data_count[0] = \<const0> ; assign axi_b_sbiterr = \<const0> ; assign axi_b_underflow = \<const0> ; assign axi_b_wr_data_count[4] = \<const0> ; assign axi_b_wr_data_count[3] = \<const0> ; assign axi_b_wr_data_count[2] = \<const0> ; assign axi_b_wr_data_count[1] = \<const0> ; assign axi_b_wr_data_count[0] = \<const0> ; assign axi_r_data_count[10] = \<const0> ; assign axi_r_data_count[9] = \<const0> ; assign axi_r_data_count[8] = \<const0> ; assign axi_r_data_count[7] = \<const0> ; assign axi_r_data_count[6] = \<const0> ; assign axi_r_data_count[5] = \<const0> ; assign axi_r_data_count[4] = \<const0> ; assign axi_r_data_count[3] = \<const0> ; assign axi_r_data_count[2] = \<const0> ; assign axi_r_data_count[1] = \<const0> ; assign axi_r_data_count[0] = \<const0> ; assign axi_r_dbiterr = \<const0> ; assign axi_r_overflow = \<const0> ; assign axi_r_prog_empty = \<const1> ; assign axi_r_prog_full = \<const0> ; assign axi_r_rd_data_count[10] = \<const0> ; assign axi_r_rd_data_count[9] = \<const0> ; assign axi_r_rd_data_count[8] = \<const0> ; assign axi_r_rd_data_count[7] = \<const0> ; assign axi_r_rd_data_count[6] = \<const0> ; assign axi_r_rd_data_count[5] = \<const0> ; assign axi_r_rd_data_count[4] = \<const0> ; assign axi_r_rd_data_count[3] = \<const0> ; assign axi_r_rd_data_count[2] = \<const0> ; assign axi_r_rd_data_count[1] = \<const0> ; assign axi_r_rd_data_count[0] = \<const0> ; assign axi_r_sbiterr = \<const0> ; assign axi_r_underflow = \<const0> ; assign axi_r_wr_data_count[10] = \<const0> ; assign axi_r_wr_data_count[9] = \<const0> ; assign axi_r_wr_data_count[8] = \<const0> ; assign axi_r_wr_data_count[7] = \<const0> ; assign axi_r_wr_data_count[6] = \<const0> ; assign axi_r_wr_data_count[5] = \<const0> ; assign axi_r_wr_data_count[4] = \<const0> ; assign axi_r_wr_data_count[3] = \<const0> ; assign axi_r_wr_data_count[2] = \<const0> ; assign axi_r_wr_data_count[1] = \<const0> ; assign axi_r_wr_data_count[0] = \<const0> ; assign axi_w_data_count[10] = \<const0> ; assign axi_w_data_count[9] = \<const0> ; assign axi_w_data_count[8] = \<const0> ; assign axi_w_data_count[7] = \<const0> ; assign axi_w_data_count[6] = \<const0> ; assign axi_w_data_count[5] = \<const0> ; assign axi_w_data_count[4] = \<const0> ; assign axi_w_data_count[3] = \<const0> ; assign axi_w_data_count[2] = \<const0> ; assign axi_w_data_count[1] = \<const0> ; assign axi_w_data_count[0] = \<const0> ; assign axi_w_dbiterr = \<const0> ; assign axi_w_overflow = \<const0> ; assign axi_w_prog_empty = \<const1> ; assign axi_w_prog_full = \<const0> ; assign axi_w_rd_data_count[10] = \<const0> ; assign axi_w_rd_data_count[9] = \<const0> ; assign axi_w_rd_data_count[8] = \<const0> ; assign axi_w_rd_data_count[7] = \<const0> ; assign axi_w_rd_data_count[6] = \<const0> ; assign axi_w_rd_data_count[5] = \<const0> ; assign axi_w_rd_data_count[4] = \<const0> ; assign axi_w_rd_data_count[3] = \<const0> ; assign axi_w_rd_data_count[2] = \<const0> ; assign axi_w_rd_data_count[1] = \<const0> ; assign axi_w_rd_data_count[0] = \<const0> ; assign axi_w_sbiterr = \<const0> ; assign axi_w_underflow = \<const0> ; assign axi_w_wr_data_count[10] = \<const0> ; assign axi_w_wr_data_count[9] = \<const0> ; assign axi_w_wr_data_count[8] = \<const0> ; assign axi_w_wr_data_count[7] = \<const0> ; assign axi_w_wr_data_count[6] = \<const0> ; assign axi_w_wr_data_count[5] = \<const0> ; assign axi_w_wr_data_count[4] = \<const0> ; assign axi_w_wr_data_count[3] = \<const0> ; assign axi_w_wr_data_count[2] = \<const0> ; assign axi_w_wr_data_count[1] = \<const0> ; assign axi_w_wr_data_count[0] = \<const0> ; assign axis_data_count[10] = \<const0> ; assign axis_data_count[9] = \<const0> ; assign axis_data_count[8] = \<const0> ; assign axis_data_count[7] = \<const0> ; assign axis_data_count[6] = \<const0> ; assign axis_data_count[5] = \<const0> ; assign axis_data_count[4] = \<const0> ; assign axis_data_count[3] = \<const0> ; assign axis_data_count[2] = \<const0> ; assign axis_data_count[1] = \<const0> ; assign axis_data_count[0] = \<const0> ; assign axis_dbiterr = \<const0> ; assign axis_overflow = \<const0> ; assign axis_prog_empty = \<const1> ; assign axis_prog_full = \<const0> ; assign axis_rd_data_count[10] = \<const0> ; assign axis_rd_data_count[9] = \<const0> ; assign axis_rd_data_count[8] = \<const0> ; assign axis_rd_data_count[7] = \<const0> ; assign axis_rd_data_count[6] = \<const0> ; assign axis_rd_data_count[5] = \<const0> ; assign axis_rd_data_count[4] = \<const0> ; assign axis_rd_data_count[3] = \<const0> ; assign axis_rd_data_count[2] = \<const0> ; assign axis_rd_data_count[1] = \<const0> ; assign axis_rd_data_count[0] = \<const0> ; assign axis_sbiterr = \<const0> ; assign axis_underflow = \<const0> ; assign axis_wr_data_count[10] = \<const0> ; assign axis_wr_data_count[9] = \<const0> ; assign axis_wr_data_count[8] = \<const0> ; assign axis_wr_data_count[7] = \<const0> ; assign axis_wr_data_count[6] = \<const0> ; assign axis_wr_data_count[5] = \<const0> ; assign axis_wr_data_count[4] = \<const0> ; assign axis_wr_data_count[3] = \<const0> ; assign axis_wr_data_count[2] = \<const0> ; assign axis_wr_data_count[1] = \<const0> ; assign axis_wr_data_count[0] = \<const0> ; assign data_count[3] = \<const0> ; assign data_count[2] = \<const0> ; assign data_count[1] = \<const0> ; assign data_count[0] = \<const0> ; assign dbiterr = \<const0> ; assign m_axi_araddr[31] = \<const0> ; assign m_axi_araddr[30] = \<const0> ; assign m_axi_araddr[29] = \<const0> ; assign m_axi_araddr[28] = \<const0> ; assign m_axi_araddr[27] = \<const0> ; assign m_axi_araddr[26] = \<const0> ; assign m_axi_araddr[25] = \<const0> ; assign m_axi_araddr[24] = \<const0> ; assign m_axi_araddr[23] = \<const0> ; assign m_axi_araddr[22] = \<const0> ; assign m_axi_araddr[21] = \<const0> ; assign m_axi_araddr[20] = \<const0> ; assign m_axi_araddr[19] = \<const0> ; assign m_axi_araddr[18] = \<const0> ; assign m_axi_araddr[17] = \<const0> ; assign m_axi_araddr[16] = \<const0> ; assign m_axi_araddr[15] = \<const0> ; assign m_axi_araddr[14] = \<const0> ; assign m_axi_araddr[13] = \<const0> ; assign m_axi_araddr[12] = \<const0> ; assign m_axi_araddr[11] = \<const0> ; assign m_axi_araddr[10] = \<const0> ; assign m_axi_araddr[9] = \<const0> ; assign m_axi_araddr[8] = \<const0> ; assign m_axi_araddr[7] = \<const0> ; assign m_axi_araddr[6] = \<const0> ; assign m_axi_araddr[5] = \<const0> ; assign m_axi_araddr[4] = \<const0> ; assign m_axi_araddr[3] = \<const0> ; assign m_axi_araddr[2] = \<const0> ; assign m_axi_araddr[1] = \<const0> ; assign m_axi_araddr[0] = \<const0> ; assign m_axi_arburst[1] = \<const0> ; assign m_axi_arburst[0] = \<const0> ; assign m_axi_arcache[3] = \<const0> ; assign m_axi_arcache[2] = \<const0> ; assign m_axi_arcache[1] = \<const0> ; assign m_axi_arcache[0] = \<const0> ; assign m_axi_arid[0] = \<const0> ; assign m_axi_arlen[7] = \<const0> ; assign m_axi_arlen[6] = \<const0> ; assign m_axi_arlen[5] = \<const0> ; assign m_axi_arlen[4] = \<const0> ; assign m_axi_arlen[3] = \<const0> ; assign m_axi_arlen[2] = \<const0> ; assign m_axi_arlen[1] = \<const0> ; assign m_axi_arlen[0] = \<const0> ; assign m_axi_arlock[0] = \<const0> ; assign m_axi_arprot[2] = \<const0> ; assign m_axi_arprot[1] = \<const0> ; assign m_axi_arprot[0] = \<const0> ; assign m_axi_arqos[3] = \<const0> ; assign m_axi_arqos[2] = \<const0> ; assign m_axi_arqos[1] = \<const0> ; assign m_axi_arqos[0] = \<const0> ; assign m_axi_arregion[3] = \<const0> ; assign m_axi_arregion[2] = \<const0> ; assign m_axi_arregion[1] = \<const0> ; assign m_axi_arregion[0] = \<const0> ; assign m_axi_arsize[2] = \<const0> ; assign m_axi_arsize[1] = \<const0> ; assign m_axi_arsize[0] = \<const0> ; assign m_axi_aruser[0] = \<const0> ; assign m_axi_arvalid = \<const0> ; assign m_axi_awaddr[31] = \<const0> ; assign m_axi_awaddr[30] = \<const0> ; assign m_axi_awaddr[29] = \<const0> ; assign m_axi_awaddr[28] = \<const0> ; assign m_axi_awaddr[27] = \<const0> ; assign m_axi_awaddr[26] = \<const0> ; assign m_axi_awaddr[25] = \<const0> ; assign m_axi_awaddr[24] = \<const0> ; assign m_axi_awaddr[23] = \<const0> ; assign m_axi_awaddr[22] = \<const0> ; assign m_axi_awaddr[21] = \<const0> ; assign m_axi_awaddr[20] = \<const0> ; assign m_axi_awaddr[19] = \<const0> ; assign m_axi_awaddr[18] = \<const0> ; assign m_axi_awaddr[17] = \<const0> ; assign m_axi_awaddr[16] = \<const0> ; assign m_axi_awaddr[15] = \<const0> ; assign m_axi_awaddr[14] = \<const0> ; assign m_axi_awaddr[13] = \<const0> ; assign m_axi_awaddr[12] = \<const0> ; assign m_axi_awaddr[11] = \<const0> ; assign m_axi_awaddr[10] = \<const0> ; assign m_axi_awaddr[9] = \<const0> ; assign m_axi_awaddr[8] = \<const0> ; assign m_axi_awaddr[7] = \<const0> ; assign m_axi_awaddr[6] = \<const0> ; assign m_axi_awaddr[5] = \<const0> ; assign m_axi_awaddr[4] = \<const0> ; assign m_axi_awaddr[3] = \<const0> ; assign m_axi_awaddr[2] = \<const0> ; assign m_axi_awaddr[1] = \<const0> ; assign m_axi_awaddr[0] = \<const0> ; assign m_axi_awburst[1] = \<const0> ; assign m_axi_awburst[0] = \<const0> ; assign m_axi_awcache[3] = \<const0> ; assign m_axi_awcache[2] = \<const0> ; assign m_axi_awcache[1] = \<const0> ; assign m_axi_awcache[0] = \<const0> ; assign m_axi_awid[0] = \<const0> ; assign m_axi_awlen[7] = \<const0> ; assign m_axi_awlen[6] = \<const0> ; assign m_axi_awlen[5] = \<const0> ; assign m_axi_awlen[4] = \<const0> ; assign m_axi_awlen[3] = \<const0> ; assign m_axi_awlen[2] = \<const0> ; assign m_axi_awlen[1] = \<const0> ; assign m_axi_awlen[0] = \<const0> ; assign m_axi_awlock[0] = \<const0> ; assign m_axi_awprot[2] = \<const0> ; assign m_axi_awprot[1] = \<const0> ; assign m_axi_awprot[0] = \<const0> ; assign m_axi_awqos[3] = \<const0> ; assign m_axi_awqos[2] = \<const0> ; assign m_axi_awqos[1] = \<const0> ; assign m_axi_awqos[0] = \<const0> ; assign m_axi_awregion[3] = \<const0> ; assign m_axi_awregion[2] = \<const0> ; assign m_axi_awregion[1] = \<const0> ; assign m_axi_awregion[0] = \<const0> ; assign m_axi_awsize[2] = \<const0> ; assign m_axi_awsize[1] = \<const0> ; assign m_axi_awsize[0] = \<const0> ; assign m_axi_awuser[0] = \<const0> ; assign m_axi_awvalid = \<const0> ; assign m_axi_bready = \<const0> ; assign m_axi_rready = \<const0> ; assign m_axi_wdata[63] = \<const0> ; assign m_axi_wdata[62] = \<const0> ; assign m_axi_wdata[61] = \<const0> ; assign m_axi_wdata[60] = \<const0> ; assign m_axi_wdata[59] = \<const0> ; assign m_axi_wdata[58] = \<const0> ; assign m_axi_wdata[57] = \<const0> ; assign m_axi_wdata[56] = \<const0> ; assign m_axi_wdata[55] = \<const0> ; assign m_axi_wdata[54] = \<const0> ; assign m_axi_wdata[53] = \<const0> ; assign m_axi_wdata[52] = \<const0> ; assign m_axi_wdata[51] = \<const0> ; assign m_axi_wdata[50] = \<const0> ; assign m_axi_wdata[49] = \<const0> ; assign m_axi_wdata[48] = \<const0> ; assign m_axi_wdata[47] = \<const0> ; assign m_axi_wdata[46] = \<const0> ; assign m_axi_wdata[45] = \<const0> ; assign m_axi_wdata[44] = \<const0> ; assign m_axi_wdata[43] = \<const0> ; assign m_axi_wdata[42] = \<const0> ; assign m_axi_wdata[41] = \<const0> ; assign m_axi_wdata[40] = \<const0> ; assign m_axi_wdata[39] = \<const0> ; assign m_axi_wdata[38] = \<const0> ; assign m_axi_wdata[37] = \<const0> ; assign m_axi_wdata[36] = \<const0> ; assign m_axi_wdata[35] = \<const0> ; assign m_axi_wdata[34] = \<const0> ; assign m_axi_wdata[33] = \<const0> ; assign m_axi_wdata[32] = \<const0> ; assign m_axi_wdata[31] = \<const0> ; assign m_axi_wdata[30] = \<const0> ; assign m_axi_wdata[29] = \<const0> ; assign m_axi_wdata[28] = \<const0> ; assign m_axi_wdata[27] = \<const0> ; assign m_axi_wdata[26] = \<const0> ; assign m_axi_wdata[25] = \<const0> ; assign m_axi_wdata[24] = \<const0> ; assign m_axi_wdata[23] = \<const0> ; assign m_axi_wdata[22] = \<const0> ; assign m_axi_wdata[21] = \<const0> ; assign m_axi_wdata[20] = \<const0> ; assign m_axi_wdata[19] = \<const0> ; assign m_axi_wdata[18] = \<const0> ; assign m_axi_wdata[17] = \<const0> ; assign m_axi_wdata[16] = \<const0> ; assign m_axi_wdata[15] = \<const0> ; assign m_axi_wdata[14] = \<const0> ; assign m_axi_wdata[13] = \<const0> ; assign m_axi_wdata[12] = \<const0> ; assign m_axi_wdata[11] = \<const0> ; assign m_axi_wdata[10] = \<const0> ; assign m_axi_wdata[9] = \<const0> ; assign m_axi_wdata[8] = \<const0> ; assign m_axi_wdata[7] = \<const0> ; assign m_axi_wdata[6] = \<const0> ; assign m_axi_wdata[5] = \<const0> ; assign m_axi_wdata[4] = \<const0> ; assign m_axi_wdata[3] = \<const0> ; assign m_axi_wdata[2] = \<const0> ; assign m_axi_wdata[1] = \<const0> ; assign m_axi_wdata[0] = \<const0> ; assign m_axi_wid[0] = \<const0> ; assign m_axi_wlast = \<const0> ; assign m_axi_wstrb[7] = \<const0> ; assign m_axi_wstrb[6] = \<const0> ; assign m_axi_wstrb[5] = \<const0> ; assign m_axi_wstrb[4] = \<const0> ; assign m_axi_wstrb[3] = \<const0> ; assign m_axi_wstrb[2] = \<const0> ; assign m_axi_wstrb[1] = \<const0> ; assign m_axi_wstrb[0] = \<const0> ; assign m_axi_wuser[0] = \<const0> ; assign m_axi_wvalid = \<const0> ; assign m_axis_tdata[15] = \<const0> ; assign m_axis_tdata[14] = \<const0> ; assign m_axis_tdata[13] = \<const0> ; assign m_axis_tdata[12] = \<const0> ; assign m_axis_tdata[11] = \<const0> ; assign m_axis_tdata[10] = \<const0> ; assign m_axis_tdata[9] = \<const0> ; assign m_axis_tdata[8] = \<const0> ; assign m_axis_tdata[7] = \<const0> ; assign m_axis_tdata[6] = \<const0> ; assign m_axis_tdata[5] = \<const0> ; assign m_axis_tdata[4] = \<const0> ; assign m_axis_tdata[3] = \<const0> ; assign m_axis_tdata[2] = \<const0> ; assign m_axis_tdata[1] = \<const0> ; assign m_axis_tdata[0] = \<const0> ; assign m_axis_tdest[0] = \<const0> ; assign m_axis_tid[0] = \<const0> ; assign m_axis_tkeep[1] = \<const0> ; assign m_axis_tkeep[0] = \<const0> ; assign m_axis_tlast = \<const0> ; assign m_axis_tstrb[1] = \<const0> ; assign m_axis_tstrb[0] = \<const0> ; assign m_axis_tuser[3] = \<const0> ; assign m_axis_tuser[2] = \<const0> ; assign m_axis_tuser[1] = \<const0> ; assign m_axis_tuser[0] = \<const0> ; assign m_axis_tvalid = \<const0> ; assign overflow = \<const0> ; assign prog_empty = \<const0> ; assign prog_full = \<const0> ; assign rd_data_count[3] = \<const0> ; assign rd_data_count[2] = \<const0> ; assign rd_data_count[1] = \<const0> ; assign rd_data_count[0] = \<const0> ; assign rd_rst_busy = \<const0> ; assign s_axi_arready = \<const0> ; assign s_axi_awready = \<const0> ; assign s_axi_bid[0] = \<const0> ; assign s_axi_bresp[1] = \<const0> ; assign s_axi_bresp[0] = \<const0> ; assign s_axi_buser[0] = \<const0> ; assign s_axi_bvalid = \<const0> ; assign s_axi_rdata[63] = \<const0> ; assign s_axi_rdata[62] = \<const0> ; assign s_axi_rdata[61] = \<const0> ; assign s_axi_rdata[60] = \<const0> ; assign s_axi_rdata[59] = \<const0> ; assign s_axi_rdata[58] = \<const0> ; assign s_axi_rdata[57] = \<const0> ; assign s_axi_rdata[56] = \<const0> ; assign s_axi_rdata[55] = \<const0> ; assign s_axi_rdata[54] = \<const0> ; assign s_axi_rdata[53] = \<const0> ; assign s_axi_rdata[52] = \<const0> ; assign s_axi_rdata[51] = \<const0> ; assign s_axi_rdata[50] = \<const0> ; assign s_axi_rdata[49] = \<const0> ; assign s_axi_rdata[48] = \<const0> ; assign s_axi_rdata[47] = \<const0> ; assign s_axi_rdata[46] = \<const0> ; assign s_axi_rdata[45] = \<const0> ; assign s_axi_rdata[44] = \<const0> ; assign s_axi_rdata[43] = \<const0> ; assign s_axi_rdata[42] = \<const0> ; assign s_axi_rdata[41] = \<const0> ; assign s_axi_rdata[40] = \<const0> ; assign s_axi_rdata[39] = \<const0> ; assign s_axi_rdata[38] = \<const0> ; assign s_axi_rdata[37] = \<const0> ; assign s_axi_rdata[36] = \<const0> ; assign s_axi_rdata[35] = \<const0> ; assign s_axi_rdata[34] = \<const0> ; assign s_axi_rdata[33] = \<const0> ; assign s_axi_rdata[32] = \<const0> ; assign s_axi_rdata[31] = \<const0> ; assign s_axi_rdata[30] = \<const0> ; assign s_axi_rdata[29] = \<const0> ; assign s_axi_rdata[28] = \<const0> ; assign s_axi_rdata[27] = \<const0> ; assign s_axi_rdata[26] = \<const0> ; assign s_axi_rdata[25] = \<const0> ; assign s_axi_rdata[24] = \<const0> ; assign s_axi_rdata[23] = \<const0> ; assign s_axi_rdata[22] = \<const0> ; assign s_axi_rdata[21] = \<const0> ; assign s_axi_rdata[20] = \<const0> ; assign s_axi_rdata[19] = \<const0> ; assign s_axi_rdata[18] = \<const0> ; assign s_axi_rdata[17] = \<const0> ; assign s_axi_rdata[16] = \<const0> ; assign s_axi_rdata[15] = \<const0> ; assign s_axi_rdata[14] = \<const0> ; assign s_axi_rdata[13] = \<const0> ; assign s_axi_rdata[12] = \<const0> ; assign s_axi_rdata[11] = \<const0> ; assign s_axi_rdata[10] = \<const0> ; assign s_axi_rdata[9] = \<const0> ; assign s_axi_rdata[8] = \<const0> ; assign s_axi_rdata[7] = \<const0> ; assign s_axi_rdata[6] = \<const0> ; assign s_axi_rdata[5] = \<const0> ; assign s_axi_rdata[4] = \<const0> ; assign s_axi_rdata[3] = \<const0> ; assign s_axi_rdata[2] = \<const0> ; assign s_axi_rdata[1] = \<const0> ; assign s_axi_rdata[0] = \<const0> ; assign s_axi_rid[0] = \<const0> ; assign s_axi_rlast = \<const0> ; assign s_axi_rresp[1] = \<const0> ; assign s_axi_rresp[0] = \<const0> ; assign s_axi_ruser[0] = \<const0> ; assign s_axi_rvalid = \<const0> ; assign s_axi_wready = \<const0> ; assign s_axis_tready = \<const0> ; assign sbiterr = \<const0> ; assign underflow = \<const0> ; assign wr_ack = \<const0> ; assign wr_data_count[3] = \<const0> ; assign wr_data_count[2] = \<const0> ; assign wr_data_count[1] = \<const0> ; assign wr_data_count[0] = \<const0> ; assign wr_rst_busy = \<const0> ; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); fifo_generator_0fifo_generator_v12_0_synth inst_fifo_gen (.din(din), .dout(dout), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .valid(valid), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule (* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *) module fifo_generator_0fifo_generator_v12_0_synth (dout, empty, valid, full, wr_en, rd_clk, wr_clk, rd_rst, din, wr_rst, rd_en); output [9:0]dout; output empty; output valid; output full; input wr_en; input rd_clk; input wr_clk; input rd_rst; input [9:0]din; input wr_rst; input rd_en; wire [9:0]din; wire [9:0]dout; wire empty; wire full; wire rd_clk; wire rd_en; wire rd_rst; wire valid; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0fifo_generator_top \gconvfifo.rf (.din(din), .dout(dout), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .valid(valid), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule (* ORIG_REF_NAME = "memory" *) module fifo_generator_0memory (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, rd_rst, O1, I1, din); output [9:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input rd_rst; input [3:0]O1; input [3:0]I1; input [9:0]din; wire [0:0]E; wire [3:0]I1; wire [3:0]O1; wire [9:0]din; wire [9:0]dout; wire rd_clk; wire rd_rst; wire tmp_ram_rd_en; wire wr_clk; fifo_generator_0blk_mem_gen_v8_2__parameterized0 \gbm.gbmg.gbmga.ngecc.bmg (.E(E), .I1(I1), .O1(O1), .din(din), .dout(dout), .rd_clk(rd_clk), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module fifo_generator_0rd_bin_cntr (Q, D, O1, E, rd_clk, rd_rst); output [3:0]Q; output [2:0]D; output [3:0]O1; input [0:0]E; input rd_clk; input rd_rst; wire [2:0]D; wire [0:0]E; wire [3:0]O1; wire [3:0]Q; wire [3:0]plusOp; wire rd_clk; wire rd_rst; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1 (.I0(Q[0]), .O(plusOp[0])); LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(plusOp[1])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h6A)) \gc0.count[2]_i_1 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .O(plusOp[2])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( .INIT(16'h6AAA)) \gc0.count[3]_i_1 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .O(plusOp[3])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[0]), .Q(O1[0])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[1]), .Q(O1[1])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[2]), .Q(O1[2])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(Q[3]), .Q(O1[3])); (* counter = "2" *) FDPE #( .INIT(1'b1)) \gc0.count_reg[0] (.C(rd_clk), .CE(E), .D(plusOp[0]), .PRE(rd_rst), .Q(Q[0])); (* counter = "2" *) FDCE #( .INIT(1'b0)) \gc0.count_reg[1] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(plusOp[1]), .Q(Q[1])); (* counter = "2" *) FDCE #( .INIT(1'b0)) \gc0.count_reg[2] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(plusOp[2]), .Q(Q[2])); (* counter = "2" *) FDCE #( .INIT(1'b0)) \gc0.count_reg[3] (.C(rd_clk), .CE(E), .CLR(rd_rst), .D(plusOp[3]), .Q(Q[3])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \rd_pntr_gc[0]_i_1 (.I0(O1[1]), .I1(O1[0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \rd_pntr_gc[1]_i_1 (.I0(O1[1]), .I1(O1[2]), .O(D[1])); LUT2 #( .INIT(4'h6)) \rd_pntr_gc[2]_i_1 (.I0(O1[2]), .I1(O1[3]), .O(D[2])); endmodule (* ORIG_REF_NAME = "rd_handshaking_flags" *) module fifo_generator_0rd_handshaking_flags (valid, ram_valid_i, rd_clk, rd_rst); output valid; input ram_valid_i; input rd_clk; input rd_rst; wire ram_valid_i; wire rd_clk; wire rd_rst; wire valid; FDCE #( .INIT(1'b0)) \gv.ram_valid_d1_reg (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(ram_valid_i), .Q(valid)); endmodule (* ORIG_REF_NAME = "rd_logic" *) module fifo_generator_0rd_logic (empty, p_18_out, valid, Q, tmp_ram_rd_en, D, O1, I1, rd_clk, rd_rst, rd_en); output empty; output p_18_out; output valid; output [3:0]Q; output tmp_ram_rd_en; output [2:0]D; output [3:0]O1; input I1; input rd_clk; input rd_rst; input rd_en; wire [2:0]D; wire I1; wire [3:0]O1; wire [3:0]Q; wire empty; wire p_14_out; wire p_18_out; wire ram_valid_i; wire rd_clk; wire rd_en; wire rd_rst; wire tmp_ram_rd_en; wire valid; fifo_generator_0rd_status_flags_as \gras.rsts (.E(p_14_out), .I1(I1), .empty(empty), .p_18_out(p_18_out), .ram_valid_i(ram_valid_i), .rd_clk(rd_clk), .rd_en(rd_en), .rd_rst(rd_rst), .tmp_ram_rd_en(tmp_ram_rd_en)); fifo_generator_0rd_handshaking_flags \grhf.rhf (.ram_valid_i(ram_valid_i), .rd_clk(rd_clk), .rd_rst(rd_rst), .valid(valid)); fifo_generator_0rd_bin_cntr rpntr (.D(D), .E(p_14_out), .O1(O1), .Q(Q), .rd_clk(rd_clk), .rd_rst(rd_rst)); endmodule (* ORIG_REF_NAME = "rd_status_flags_as" *) module fifo_generator_0rd_status_flags_as (empty, p_18_out, tmp_ram_rd_en, E, ram_valid_i, I1, rd_clk, rd_rst, rd_en); output empty; output p_18_out; output tmp_ram_rd_en; output [0:0]E; output ram_valid_i; input I1; input rd_clk; input rd_rst; input rd_en; wire [0:0]E; wire I1; wire empty; wire p_18_out; wire ram_valid_i; wire rd_clk; wire rd_en; wire rd_rst; wire tmp_ram_rd_en; LUT3 #( .INIT(8'hBA)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1 (.I0(rd_rst), .I1(p_18_out), .I2(rd_en), .O(tmp_ram_rd_en)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h2)) \gc0.count_d1[3]_i_1 (.I0(rd_en), .I1(p_18_out), .O(E)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h2)) \gv.ram_valid_d1_i_1 (.I0(rd_en), .I1(empty), .O(ram_valid_i)); (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_fb_i_reg (.C(rd_clk), .CE(1'b1), .D(I1), .PRE(rd_rst), .Q(p_18_out)); (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(I1), .PRE(rd_rst), .Q(empty)); endmodule (* ORIG_REF_NAME = "reset_blk_ramfifo" *) module fifo_generator_0reset_blk_ramfifo (rst_full_gen_i, rst_d2, wr_clk, wr_rst); output rst_full_gen_i; output rst_d2; input wr_clk; input wr_rst; wire rst_d1; wire rst_d2; wire rst_d3; wire rst_full_gen_i; wire wr_clk; wire wr_rst; FDCE #( .INIT(1'b0)) \grstd1.grst_full.grst_f.RST_FULL_GEN_reg (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(rst_d3), .Q(rst_full_gen_i)); (* ASYNC_REG *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d1_reg (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(wr_rst), .Q(rst_d1)); (* ASYNC_REG *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d2_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1), .PRE(wr_rst), .Q(rst_d2)); (* ASYNC_REG *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d3_reg (.C(wr_clk), .CE(1'b1), .D(rst_d2), .PRE(wr_rst), .Q(rst_d3)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fifo_generator_0synchronizer_ff (Q, I1, rd_clk, rd_rst); output [3:0]Q; input [3:0]I1; input rd_clk; input rd_rst; wire [3:0]I1; wire [3:0]Q; wire rd_clk; wire rd_rst; (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[0]), .Q(Q[0])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[1]), .Q(Q[1])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[2]), .Q(Q[2])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[3]), .Q(Q[3])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fifo_generator_0synchronizer_ff_0 (Q, I1, wr_clk, wr_rst); output [3:0]Q; input [3:0]I1; input wr_clk; input wr_rst; wire [3:0]I1; wire [3:0]Q; wire wr_clk; wire wr_rst; (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[0]), .Q(Q[0])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[1]), .Q(Q[1])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[2]), .Q(Q[2])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[3]), .Q(Q[3])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fifo_generator_0synchronizer_ff_1 (D, Q, I1, rd_clk, rd_rst); output [1:0]D; output [2:0]Q; input [3:0]I1; input rd_clk; input rd_rst; wire [1:0]D; wire [3:0]I1; wire [2:0]Q; wire rd_clk; wire rd_rst; (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[0]), .Q(Q[0])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[1]), .Q(Q[1])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[2]), .Q(Q[2])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(rd_rst), .D(I1[3]), .Q(D[1])); LUT2 #( .INIT(4'h6)) \wr_pntr_bin[2]_i_1 (.I0(Q[2]), .I1(D[1]), .O(D[0])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fifo_generator_0synchronizer_ff_2 (D, Q, I1, wr_clk, wr_rst); output [1:0]D; output [2:0]Q; input [3:0]I1; input wr_clk; input wr_rst; wire [1:0]D; wire [3:0]I1; wire [2:0]Q; wire wr_clk; wire wr_rst; (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[0]), .Q(Q[0])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[1]), .Q(Q[1])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[2]), .Q(Q[2])); (* ASYNC_REG *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(wr_rst), .D(I1[3]), .Q(D[1])); LUT2 #( .INIT(4'h6)) \rd_pntr_bin[2]_i_1 (.I0(Q[2]), .I1(D[1]), .O(D[0])); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module fifo_generator_0wr_bin_cntr (ram_full_i, Q, O1, O3, rst_full_gen_i, wr_en, p_0_out, I1, E, wr_clk, wr_rst); output ram_full_i; output [2:0]Q; output [3:0]O1; input [3:0]O3; input rst_full_gen_i; input wr_en; input p_0_out; input I1; input [0:0]E; input wr_clk; input wr_rst; wire [0:0]E; wire I1; wire [3:0]O1; wire [3:0]O3; wire [2:0]Q; wire n_0_ram_full_i_i_2; wire n_0_ram_full_i_i_3; wire n_0_ram_full_i_i_4; wire p_0_out; wire [3:3]p_8_out; wire [3:0]plusOp__0; wire ram_full_i; wire rst_full_gen_i; wire wr_clk; wire wr_en; wire [3:0]wr_pntr_plus2; wire wr_rst; (* RETAIN_INVERTER *) (* SOFT_HLUTNM = "soft_lutpair7" *) LUT1 #( .INIT(2'h1)) \gic0.gc0.count[0]_i_1 (.I0(wr_pntr_plus2[0]), .O(plusOp__0[0])); LUT2 #( .INIT(4'h6)) \gic0.gc0.count[1]_i_1 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .O(plusOp__0[1])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[2]_i_1 (.I0(wr_pntr_plus2[1]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[2]), .O(plusOp__0[2])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[3]_i_1 (.I0(wr_pntr_plus2[2]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[1]), .I3(wr_pntr_plus2[3]), .O(plusOp__0[3])); FDPE #( .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), .CE(E), .D(wr_pntr_plus2[0]), .PRE(wr_rst), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(wr_pntr_plus2[1]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(wr_pntr_plus2[2]), .Q(Q[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(wr_pntr_plus2[3]), .Q(p_8_out)); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(Q[0]), .Q(O1[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(Q[1]), .Q(O1[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(Q[2]), .Q(O1[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(p_8_out), .Q(O1[3])); (* counter = "3" *) FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(plusOp__0[0]), .Q(wr_pntr_plus2[0])); (* counter = "3" *) FDPE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), .CE(E), .D(plusOp__0[1]), .PRE(wr_rst), .Q(wr_pntr_plus2[1])); (* counter = "3" *) FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(plusOp__0[2]), .Q(wr_pntr_plus2[2])); (* counter = "3" *) FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), .CE(E), .CLR(wr_rst), .D(plusOp__0[3]), .Q(wr_pntr_plus2[3])); LUT6 #( .INIT(64'hFFFF800880088008)) ram_full_i_i_1 (.I0(n_0_ram_full_i_i_2), .I1(n_0_ram_full_i_i_3), .I2(O3[1]), .I3(wr_pntr_plus2[1]), .I4(n_0_ram_full_i_i_4), .I5(I1), .O(ram_full_i)); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'h9009)) ram_full_i_i_2 (.I0(wr_pntr_plus2[2]), .I1(O3[2]), .I2(wr_pntr_plus2[0]), .I3(O3[0]), .O(n_0_ram_full_i_i_2)); LUT5 #( .INIT(32'h00000900)) ram_full_i_i_3 (.I0(wr_pntr_plus2[3]), .I1(O3[3]), .I2(rst_full_gen_i), .I3(wr_en), .I4(p_0_out), .O(n_0_ram_full_i_i_3)); LUT3 #( .INIT(8'h09)) ram_full_i_i_4 (.I0(p_8_out), .I1(O3[3]), .I2(rst_full_gen_i), .O(n_0_ram_full_i_i_4)); endmodule (* ORIG_REF_NAME = "wr_logic" *) module fifo_generator_0wr_logic (full, E, Q, O1, wr_clk, rst_d2, O3, rst_full_gen_i, wr_en, I1, wr_rst); output full; output [0:0]E; output [2:0]Q; output [3:0]O1; input wr_clk; input rst_d2; input [3:0]O3; input rst_full_gen_i; input wr_en; input I1; input wr_rst; wire [0:0]E; wire I1; wire [3:0]O1; wire [3:0]O3; wire [2:0]Q; wire full; wire p_0_out; wire ram_full_i; wire rst_d2; wire rst_full_gen_i; wire wr_clk; wire wr_en; wire wr_rst; fifo_generator_0wr_status_flags_as \gwas.wsts (.E(E), .full(full), .p_0_out(p_0_out), .ram_full_i(ram_full_i), .rst_d2(rst_d2), .wr_clk(wr_clk), .wr_en(wr_en)); fifo_generator_0wr_bin_cntr wpntr (.E(E), .I1(I1), .O1(O1), .O3(O3), .Q(Q), .p_0_out(p_0_out), .ram_full_i(ram_full_i), .rst_full_gen_i(rst_full_gen_i), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst(wr_rst)); endmodule (* ORIG_REF_NAME = "wr_status_flags_as" *) module fifo_generator_0wr_status_flags_as (full, p_0_out, E, ram_full_i, wr_clk, rst_d2, wr_en); output full; output p_0_out; output [0:0]E; input ram_full_i; input wr_clk; input rst_d2; input wr_en; wire [0:0]E; wire full; wire p_0_out; wire ram_full_i; wire rst_d2; wire wr_clk; wire wr_en; LUT2 #( .INIT(4'h2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2 (.I0(wr_en), .I1(p_0_out), .O(E)); (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_fb_i_reg (.C(wr_clk), .CE(1'b1), .D(ram_full_i), .PRE(rst_d2), .Q(p_0_out)); (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(ram_full_i), .PRE(rst_d2), .Q(full)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif

/** * This is written by Zhiyang Ong * for EE577b Extra Credit Homework , Question 2 * * Behavioral model for the large XOR gate */ module large_xor (a,b,out); // Output vector output reg [14:0] out; // Input vector input [14:0] a; // Another input vector input [15:1] b; // Declare "reg" signals... //reg [3:0] in_bar; // Declare "wire" signals... // Defining constants: parameter [name_of_constant] = value; always @(*) begin out[0]=a[0]^b[1]; out[1]=a[1]^b[2]; out[2]=a[2]^b[3]; out[3]=a[3]^b[4]; out[4]=a[4]^b[5]; out[5]=a[5]^b[6]; out[6]=a[6]^b[7]; out[7]=a[7]^b[8]; out[8]=a[8]^b[9]; out[9]=a[9]^b[10]; out[10]=a[10]^b[11]; out[11]=a[11]^b[12]; out[12]=a[12]^b[13]; out[13]=a[13]^b[14]; out[14]=a[14]^b[15]; end endmodule module parity_stripper (in,out); // Output vector output reg [10:0] out; // Input vector input [14:0] in; // Declare "reg" signals... //reg [3:0] in_bar; // Declare "wire" signals... // Defining constants: parameter [name_of_constant] = value; always @(*) begin out[0]=in[2]; out[1]=in[4]; out[2]=in[5]; out[3]=in[6]; out[4]=in[8]; out[5]=in[9]; out[6]=in[10]; out[7]=in[11]; out[8]=in[12]; out[9]=in[13]; out[10]=in[14]; end endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V `define SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V /** * sdfstp: Scan delay flop, inverted set, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_dff_ps/sky130_fd_sc_ms__udp_dff_ps.v" `include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v" `celldefine module sky130_fd_sc_ms__sdfstp ( Q , CLK , D , SCD , SCE , SET_B ); // Module ports output Q ; input CLK ; input D ; input SCD ; input SCE ; input SET_B; // Local signals wire buf_Q ; wire SET ; wire mux_out; // Delay Name Output Other arguments not not0 (SET , SET_B ); sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); sky130_fd_sc_ms__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET); buf buf0 (Q , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V `define SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V /** * dlxtn: Delay latch, inverted enable, single output. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__dlxtn ( //# {{data|Data Signals}} input D , output Q , //# {{clocks|Clocking}} input GATE_N, //# {{power|Power}} input VPB , input VPWR , input VGND , input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V

// megafunction wizard: %ALTPLL%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: ddr3_int_phy_alt_mem_phy_pll.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 10.0 Build 262 08/18/2010 SP 1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module ddr3_int_phy_alt_mem_phy_pll ( areset, inclk0, phasecounterselect, phasestep, phaseupdown, scanclk, c0, c1, c2, c3, c4, c5, locked, phasedone); input areset; input inclk0; input [3:0] phasecounterselect; input phasestep; input phaseupdown; input scanclk; output c0; output c1; output c2; output c3; output c4; output c5; output locked; output phasedone; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 areset; tri0 [3:0] phasecounterselect; tri0 phasestep; tri0 phaseupdown; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "3" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "300.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg" // Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000" // Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "300.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" // Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK5 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLK4 STRING "1" // Retrieval info: PRIVATE: USE_CLK5 STRING "1" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833" // Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "12" // Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" // Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" // Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" // Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF" // Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE" // Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7" // Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]" // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" // Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]" // Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone" // Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep" // Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown" // Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0 // Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0 // Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0 // Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 // Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_bb.v TRUE

// $Id: rtr_flit_type_check.v 5188 2012-08-30 00:31:31Z dub $ /* Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ //============================================================================== // flit type checker module //============================================================================== module rtr_flit_type_check (clk, reset, active, flit_valid, flit_head, flit_tail, error); `include "c_constants.v" //--------------------------------------------------------------------------- // parameters //--------------------------------------------------------------------------- parameter reset_type = `RESET_TYPE_ASYNC; //--------------------------------------------------------------------------- // interface //--------------------------------------------------------------------------- input clk; input reset; input active; input flit_valid; input flit_head; input flit_tail; output error; wire error; //--------------------------------------------------------------------------- // implementation //--------------------------------------------------------------------------- wire packet_active_s, packet_active_q; assign packet_active_s = flit_valid ? ((packet_active_q | flit_head) & ~flit_tail) : packet_active_q; c_dff #(.width(1), .reset_type(reset_type)) packet_activeq (.clk(clk), .reset(reset), .active(active), .d(packet_active_s), .q(packet_active_q)); assign error = flit_valid & (flit_head ~^ packet_active_q); // synopsys translate_off always @(posedge clk) begin if(error) $display("ERROR: Received flit with unexpected type in module %m."); end // synopsys translate_on endmodule

// $Id: c_encoder.v 1534 2009-09-16 16:10:23Z dub $ /* Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the Stanford University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ // encoder from one-hot to binary module c_encoder (data_in, data_out); `include "c_functions.v" // number of input ports (i.e., decoded width) parameter num_ports = 8; localparam width = clogb(num_ports); // one-hot input data input [0:num_ports-1] data_in; // binary encoded output data output [0:width-1] data_out; wire [0:width-1] data_out; generate genvar level; for(level = 0; level < width; level = level + 1) begin:levels wire [0:num_ports-1] bits; genvar position; for(position = 0; position < num_ports; position = position + 1) begin:positions if(position & (1 << level)) assign bits[position] = data_in[position]; else assign bits[position] = 1'b0; end assign data_out[(width-1)-level] = |bits; end endgenerate endmodule

//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_core_pcie_pipe_pipeline.v // Version : 1.10 // // Description: PIPE module for Virtex7 PCIe Block // // // //-------------------------------------------------------------------------------- `timescale 1ps/1ps module pcie_core_pcie_pipe_pipeline # ( parameter LINK_CAP_MAX_LINK_WIDTH = 8, parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages ) ( // Pipe Per-Link Signals input wire pipe_tx_rcvr_det_i , input wire pipe_tx_reset_i , input wire pipe_tx_rate_i , input wire pipe_tx_deemph_i , input wire [2:0] pipe_tx_margin_i , input wire pipe_tx_swing_i , output wire pipe_tx_rcvr_det_o , output wire pipe_tx_reset_o , output wire pipe_tx_rate_o , output wire pipe_tx_deemph_o , output wire [2:0] pipe_tx_margin_o , output wire pipe_tx_swing_o , // Pipe Per-Lane Signals - Lane 0 output wire [ 1:0] pipe_rx0_char_is_k_o , output wire [15:0] pipe_rx0_data_o , output wire pipe_rx0_valid_o , output wire pipe_rx0_chanisaligned_o , output wire [ 2:0] pipe_rx0_status_o , output wire pipe_rx0_phy_status_o , output wire pipe_rx0_elec_idle_o , input wire pipe_rx0_polarity_i , input wire pipe_tx0_compliance_i , input wire [ 1:0] pipe_tx0_char_is_k_i , input wire [15:0] pipe_tx0_data_i , input wire pipe_tx0_elec_idle_i , input wire [ 1:0] pipe_tx0_powerdown_i , input wire [ 1:0] pipe_rx0_char_is_k_i , input wire [15:0] pipe_rx0_data_i , input wire pipe_rx0_valid_i , input wire pipe_rx0_chanisaligned_i , input wire [ 2:0] pipe_rx0_status_i , input wire pipe_rx0_phy_status_i , input wire pipe_rx0_elec_idle_i , output wire pipe_rx0_polarity_o , output wire pipe_tx0_compliance_o , output wire [ 1:0] pipe_tx0_char_is_k_o , output wire [15:0] pipe_tx0_data_o , output wire pipe_tx0_elec_idle_o , output wire [ 1:0] pipe_tx0_powerdown_o , // Pipe Per-Lane Signals - Lane 1 output wire [ 1:0] pipe_rx1_char_is_k_o , output wire [15:0] pipe_rx1_data_o , output wire pipe_rx1_valid_o , output wire pipe_rx1_chanisaligned_o , output wire [ 2:0] pipe_rx1_status_o , output wire pipe_rx1_phy_status_o , output wire pipe_rx1_elec_idle_o , input wire pipe_rx1_polarity_i , input wire pipe_tx1_compliance_i , input wire [ 1:0] pipe_tx1_char_is_k_i , input wire [15:0] pipe_tx1_data_i , input wire pipe_tx1_elec_idle_i , input wire [ 1:0] pipe_tx1_powerdown_i , input wire [ 1:0] pipe_rx1_char_is_k_i , input wire [15:0] pipe_rx1_data_i , input wire pipe_rx1_valid_i , input wire pipe_rx1_chanisaligned_i , input wire [ 2:0] pipe_rx1_status_i , input wire pipe_rx1_phy_status_i , input wire pipe_rx1_elec_idle_i , output wire pipe_rx1_polarity_o , output wire pipe_tx1_compliance_o , output wire [ 1:0] pipe_tx1_char_is_k_o , output wire [15:0] pipe_tx1_data_o , output wire pipe_tx1_elec_idle_o , output wire [ 1:0] pipe_tx1_powerdown_o , // Pipe Per-Lane Signals - Lane 2 output wire [ 1:0] pipe_rx2_char_is_k_o , output wire [15:0] pipe_rx2_data_o , output wire pipe_rx2_valid_o , output wire pipe_rx2_chanisaligned_o , output wire [ 2:0] pipe_rx2_status_o , output wire pipe_rx2_phy_status_o , output wire pipe_rx2_elec_idle_o , input wire pipe_rx2_polarity_i , input wire pipe_tx2_compliance_i , input wire [ 1:0] pipe_tx2_char_is_k_i , input wire [15:0] pipe_tx2_data_i , input wire pipe_tx2_elec_idle_i , input wire [ 1:0] pipe_tx2_powerdown_i , input wire [ 1:0] pipe_rx2_char_is_k_i , input wire [15:0] pipe_rx2_data_i , input wire pipe_rx2_valid_i , input wire pipe_rx2_chanisaligned_i , input wire [ 2:0] pipe_rx2_status_i , input wire pipe_rx2_phy_status_i , input wire pipe_rx2_elec_idle_i , output wire pipe_rx2_polarity_o , output wire pipe_tx2_compliance_o , output wire [ 1:0] pipe_tx2_char_is_k_o , output wire [15:0] pipe_tx2_data_o , output wire pipe_tx2_elec_idle_o , output wire [ 1:0] pipe_tx2_powerdown_o , // Pipe Per-Lane Signals - Lane 3 output wire [ 1:0] pipe_rx3_char_is_k_o , output wire [15:0] pipe_rx3_data_o , output wire pipe_rx3_valid_o , output wire pipe_rx3_chanisaligned_o , output wire [ 2:0] pipe_rx3_status_o , output wire pipe_rx3_phy_status_o , output wire pipe_rx3_elec_idle_o , input wire pipe_rx3_polarity_i , input wire pipe_tx3_compliance_i , input wire [ 1:0] pipe_tx3_char_is_k_i , input wire [15:0] pipe_tx3_data_i , input wire pipe_tx3_elec_idle_i , input wire [ 1:0] pipe_tx3_powerdown_i , input wire [ 1:0] pipe_rx3_char_is_k_i , input wire [15:0] pipe_rx3_data_i , input wire pipe_rx3_valid_i , input wire pipe_rx3_chanisaligned_i , input wire [ 2:0] pipe_rx3_status_i , input wire pipe_rx3_phy_status_i , input wire pipe_rx3_elec_idle_i , output wire pipe_rx3_polarity_o , output wire pipe_tx3_compliance_o , output wire [ 1:0] pipe_tx3_char_is_k_o , output wire [15:0] pipe_tx3_data_o , output wire pipe_tx3_elec_idle_o , output wire [ 1:0] pipe_tx3_powerdown_o , // Pipe Per-Lane Signals - Lane 4 output wire [ 1:0] pipe_rx4_char_is_k_o , output wire [15:0] pipe_rx4_data_o , output wire pipe_rx4_valid_o , output wire pipe_rx4_chanisaligned_o , output wire [ 2:0] pipe_rx4_status_o , output wire pipe_rx4_phy_status_o , output wire pipe_rx4_elec_idle_o , input wire pipe_rx4_polarity_i , input wire pipe_tx4_compliance_i , input wire [ 1:0] pipe_tx4_char_is_k_i , input wire [15:0] pipe_tx4_data_i , input wire pipe_tx4_elec_idle_i , input wire [ 1:0] pipe_tx4_powerdown_i , input wire [ 1:0] pipe_rx4_char_is_k_i , input wire [15:0] pipe_rx4_data_i , input wire pipe_rx4_valid_i , input wire pipe_rx4_chanisaligned_i , input wire [ 2:0] pipe_rx4_status_i , input wire pipe_rx4_phy_status_i , input wire pipe_rx4_elec_idle_i , output wire pipe_rx4_polarity_o , output wire pipe_tx4_compliance_o , output wire [ 1:0] pipe_tx4_char_is_k_o , output wire [15:0] pipe_tx4_data_o , output wire pipe_tx4_elec_idle_o , output wire [ 1:0] pipe_tx4_powerdown_o , // Pipe Per-Lane Signals - Lane 5 output wire [ 1:0] pipe_rx5_char_is_k_o , output wire [15:0] pipe_rx5_data_o , output wire pipe_rx5_valid_o , output wire pipe_rx5_chanisaligned_o , output wire [ 2:0] pipe_rx5_status_o , output wire pipe_rx5_phy_status_o , output wire pipe_rx5_elec_idle_o , input wire pipe_rx5_polarity_i , input wire pipe_tx5_compliance_i , input wire [ 1:0] pipe_tx5_char_is_k_i , input wire [15:0] pipe_tx5_data_i , input wire pipe_tx5_elec_idle_i , input wire [ 1:0] pipe_tx5_powerdown_i , input wire [ 1:0] pipe_rx5_char_is_k_i , input wire [15:0] pipe_rx5_data_i , input wire pipe_rx5_valid_i , input wire pipe_rx5_chanisaligned_i , input wire [ 2:0] pipe_rx5_status_i , input wire pipe_rx5_phy_status_i , input wire pipe_rx5_elec_idle_i , output wire pipe_rx5_polarity_o , output wire pipe_tx5_compliance_o , output wire [ 1:0] pipe_tx5_char_is_k_o , output wire [15:0] pipe_tx5_data_o , output wire pipe_tx5_elec_idle_o , output wire [ 1:0] pipe_tx5_powerdown_o , // Pipe Per-Lane Signals - Lane 6 output wire [ 1:0] pipe_rx6_char_is_k_o , output wire [15:0] pipe_rx6_data_o , output wire pipe_rx6_valid_o , output wire pipe_rx6_chanisaligned_o , output wire [ 2:0] pipe_rx6_status_o , output wire pipe_rx6_phy_status_o , output wire pipe_rx6_elec_idle_o , input wire pipe_rx6_polarity_i , input wire pipe_tx6_compliance_i , input wire [ 1:0] pipe_tx6_char_is_k_i , input wire [15:0] pipe_tx6_data_i , input wire pipe_tx6_elec_idle_i , input wire [ 1:0] pipe_tx6_powerdown_i , input wire [ 1:0] pipe_rx6_char_is_k_i , input wire [15:0] pipe_rx6_data_i , input wire pipe_rx6_valid_i , input wire pipe_rx6_chanisaligned_i , input wire [ 2:0] pipe_rx6_status_i , input wire pipe_rx6_phy_status_i , input wire pipe_rx6_elec_idle_i , output wire pipe_rx6_polarity_o , output wire pipe_tx6_compliance_o , output wire [ 1:0] pipe_tx6_char_is_k_o , output wire [15:0] pipe_tx6_data_o , output wire pipe_tx6_elec_idle_o , output wire [ 1:0] pipe_tx6_powerdown_o , // Pipe Per-Lane Signals - Lane 7 output wire [ 1:0] pipe_rx7_char_is_k_o , output wire [15:0] pipe_rx7_data_o , output wire pipe_rx7_valid_o , output wire pipe_rx7_chanisaligned_o , output wire [ 2:0] pipe_rx7_status_o , output wire pipe_rx7_phy_status_o , output wire pipe_rx7_elec_idle_o , input wire pipe_rx7_polarity_i , input wire pipe_tx7_compliance_i , input wire [ 1:0] pipe_tx7_char_is_k_i , input wire [15:0] pipe_tx7_data_i , input wire pipe_tx7_elec_idle_i , input wire [ 1:0] pipe_tx7_powerdown_i , input wire [ 1:0] pipe_rx7_char_is_k_i , input wire [15:0] pipe_rx7_data_i , input wire pipe_rx7_valid_i , input wire pipe_rx7_chanisaligned_i , input wire [ 2:0] pipe_rx7_status_i , input wire pipe_rx7_phy_status_i , input wire pipe_rx7_elec_idle_i , output wire pipe_rx7_polarity_o , output wire pipe_tx7_compliance_o , output wire [ 1:0] pipe_tx7_char_is_k_o , output wire [15:0] pipe_tx7_data_o , output wire pipe_tx7_elec_idle_o , output wire [ 1:0] pipe_tx7_powerdown_o , // Non PIPE signals input wire pipe_clk , input wire rst_n ); //******************************************************************// // Reality check. // //******************************************************************// //synthesis translate_off // initial begin // $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d PIPE_PIPELINE_STAGES %0d", // $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES); // end //synthesis translate_on generate pcie_core_pcie_pipe_misc # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_misc_i ( .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i), .pipe_tx_reset_i(pipe_tx_reset_i), .pipe_tx_rate_i(pipe_tx_rate_i), .pipe_tx_deemph_i(pipe_tx_deemph_i), .pipe_tx_margin_i(pipe_tx_margin_i), .pipe_tx_swing_i(pipe_tx_swing_i), .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o), .pipe_tx_reset_o(pipe_tx_reset_o), .pipe_tx_rate_o(pipe_tx_rate_o), .pipe_tx_deemph_o(pipe_tx_deemph_o), .pipe_tx_margin_o(pipe_tx_margin_o), .pipe_tx_swing_o(pipe_tx_swing_o) , .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_0_i ( .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o), .pipe_rx_data_o(pipe_rx0_data_o), .pipe_rx_valid_o(pipe_rx0_valid_o), .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o), .pipe_rx_status_o(pipe_rx0_status_o), .pipe_rx_phy_status_o(pipe_rx0_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o), .pipe_rx_polarity_i(pipe_rx0_polarity_i), .pipe_tx_compliance_i(pipe_tx0_compliance_i), .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i), .pipe_tx_data_i(pipe_tx0_data_i), .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx0_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i), .pipe_rx_data_i(pipe_rx0_data_i), .pipe_rx_valid_i(pipe_rx0_valid_i), .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i), .pipe_rx_status_i(pipe_rx0_status_i), .pipe_rx_phy_status_i(pipe_rx0_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i), .pipe_rx_polarity_o(pipe_rx0_polarity_o), .pipe_tx_compliance_o(pipe_tx0_compliance_o), .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o), .pipe_tx_data_o(pipe_tx0_data_o), .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx0_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_1_i ( .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o), .pipe_rx_data_o(pipe_rx1_data_o), .pipe_rx_valid_o(pipe_rx1_valid_o), .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o), .pipe_rx_status_o(pipe_rx1_status_o), .pipe_rx_phy_status_o(pipe_rx1_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o), .pipe_rx_polarity_i(pipe_rx1_polarity_i), .pipe_tx_compliance_i(pipe_tx1_compliance_i), .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i), .pipe_tx_data_i(pipe_tx1_data_i), .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx1_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i), .pipe_rx_data_i(pipe_rx1_data_i), .pipe_rx_valid_i(pipe_rx1_valid_i), .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i), .pipe_rx_status_i(pipe_rx1_status_i), .pipe_rx_phy_status_i(pipe_rx1_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i), .pipe_rx_polarity_o(pipe_rx1_polarity_o), .pipe_tx_compliance_o(pipe_tx1_compliance_o), .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o), .pipe_tx_data_o(pipe_tx1_data_o), .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx1_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); end // if (LINK_CAP_MAX_LINK_WIDTH >= 2) else begin assign pipe_rx1_char_is_k_o = 2'b00; assign pipe_rx1_data_o = 16'h0000; assign pipe_rx1_valid_o = 1'b0; assign pipe_rx1_chanisaligned_o = 1'b0; assign pipe_rx1_status_o = 3'b000; assign pipe_rx1_phy_status_o = 1'b0; assign pipe_rx1_elec_idle_o = 1'b1; assign pipe_rx1_polarity_o = 1'b0; assign pipe_tx1_compliance_o = 1'b0; assign pipe_tx1_char_is_k_o = 2'b00; assign pipe_tx1_data_o = 16'h0000; assign pipe_tx1_elec_idle_o = 1'b1; assign pipe_tx1_powerdown_o = 2'b00; end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2) if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_2_i ( .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o), .pipe_rx_data_o(pipe_rx2_data_o), .pipe_rx_valid_o(pipe_rx2_valid_o), .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o), .pipe_rx_status_o(pipe_rx2_status_o), .pipe_rx_phy_status_o(pipe_rx2_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o), .pipe_rx_polarity_i(pipe_rx2_polarity_i), .pipe_tx_compliance_i(pipe_tx2_compliance_i), .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i), .pipe_tx_data_i(pipe_tx2_data_i), .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx2_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i), .pipe_rx_data_i(pipe_rx2_data_i), .pipe_rx_valid_i(pipe_rx2_valid_i), .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i), .pipe_rx_status_i(pipe_rx2_status_i), .pipe_rx_phy_status_i(pipe_rx2_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i), .pipe_rx_polarity_o(pipe_rx2_polarity_o), .pipe_tx_compliance_o(pipe_tx2_compliance_o), .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o), .pipe_tx_data_o(pipe_tx2_data_o), .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx2_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_3_i ( .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o), .pipe_rx_data_o(pipe_rx3_data_o), .pipe_rx_valid_o(pipe_rx3_valid_o), .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o), .pipe_rx_status_o(pipe_rx3_status_o), .pipe_rx_phy_status_o(pipe_rx3_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o), .pipe_rx_polarity_i(pipe_rx3_polarity_i), .pipe_tx_compliance_i(pipe_tx3_compliance_i), .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i), .pipe_tx_data_i(pipe_tx3_data_i), .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx3_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i), .pipe_rx_data_i(pipe_rx3_data_i), .pipe_rx_valid_i(pipe_rx3_valid_i), .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i), .pipe_rx_status_i(pipe_rx3_status_i), .pipe_rx_phy_status_i(pipe_rx3_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i), .pipe_rx_polarity_o(pipe_rx3_polarity_o), .pipe_tx_compliance_o(pipe_tx3_compliance_o), .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o), .pipe_tx_data_o(pipe_tx3_data_o), .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx3_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); end // if (LINK_CAP_MAX_LINK_WIDTH >= 4) else begin assign pipe_rx2_char_is_k_o = 2'b00; assign pipe_rx2_data_o = 16'h0000; assign pipe_rx2_valid_o = 1'b0; assign pipe_rx2_chanisaligned_o = 1'b0; assign pipe_rx2_status_o = 3'b000; assign pipe_rx2_phy_status_o = 1'b0; assign pipe_rx2_elec_idle_o = 1'b1; assign pipe_rx2_polarity_o = 1'b0; assign pipe_tx2_compliance_o = 1'b0; assign pipe_tx2_char_is_k_o = 2'b00; assign pipe_tx2_data_o = 16'h0000; assign pipe_tx2_elec_idle_o = 1'b1; assign pipe_tx2_powerdown_o = 2'b00; assign pipe_rx3_char_is_k_o = 2'b00; assign pipe_rx3_data_o = 16'h0000; assign pipe_rx3_valid_o = 1'b0; assign pipe_rx3_chanisaligned_o = 1'b0; assign pipe_rx3_status_o = 3'b000; assign pipe_rx3_phy_status_o = 1'b0; assign pipe_rx3_elec_idle_o = 1'b1; assign pipe_rx3_polarity_o = 1'b0; assign pipe_tx3_compliance_o = 1'b0; assign pipe_tx3_char_is_k_o = 2'b00; assign pipe_tx3_data_o = 16'h0000; assign pipe_tx3_elec_idle_o = 1'b1; assign pipe_tx3_powerdown_o = 2'b00; end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4) if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_4_i ( .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o), .pipe_rx_data_o(pipe_rx4_data_o), .pipe_rx_valid_o(pipe_rx4_valid_o), .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o), .pipe_rx_status_o(pipe_rx4_status_o), .pipe_rx_phy_status_o(pipe_rx4_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o), .pipe_rx_polarity_i(pipe_rx4_polarity_i), .pipe_tx_compliance_i(pipe_tx4_compliance_i), .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i), .pipe_tx_data_i(pipe_tx4_data_i), .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx4_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i), .pipe_rx_data_i(pipe_rx4_data_i), .pipe_rx_valid_i(pipe_rx4_valid_i), .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i), .pipe_rx_status_i(pipe_rx4_status_i), .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i), .pipe_rx_polarity_o(pipe_rx4_polarity_o), .pipe_tx_compliance_o(pipe_tx4_compliance_o), .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o), .pipe_tx_data_o(pipe_tx4_data_o), .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx4_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_5_i ( .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o), .pipe_rx_data_o(pipe_rx5_data_o), .pipe_rx_valid_o(pipe_rx5_valid_o), .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o), .pipe_rx_status_o(pipe_rx5_status_o), .pipe_rx_phy_status_o(pipe_rx5_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o), .pipe_rx_polarity_i(pipe_rx5_polarity_i), .pipe_tx_compliance_i(pipe_tx5_compliance_i), .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i), .pipe_tx_data_i(pipe_tx5_data_i), .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx5_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i), .pipe_rx_data_i(pipe_rx5_data_i), .pipe_rx_valid_i(pipe_rx5_valid_i), .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i), .pipe_rx_status_i(pipe_rx5_status_i), .pipe_rx_phy_status_i(pipe_rx5_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i), .pipe_rx_polarity_o(pipe_rx5_polarity_o), .pipe_tx_compliance_o(pipe_tx5_compliance_o), .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o), .pipe_tx_data_o(pipe_tx5_data_o), .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx5_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_6_i ( .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o), .pipe_rx_data_o(pipe_rx6_data_o), .pipe_rx_valid_o(pipe_rx6_valid_o), .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o), .pipe_rx_status_o(pipe_rx6_status_o), .pipe_rx_phy_status_o(pipe_rx6_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o), .pipe_rx_polarity_i(pipe_rx6_polarity_i), .pipe_tx_compliance_i(pipe_tx6_compliance_i), .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i), .pipe_tx_data_i(pipe_tx6_data_i), .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx6_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i), .pipe_rx_data_i(pipe_rx6_data_i), .pipe_rx_valid_i(pipe_rx6_valid_i), .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i), .pipe_rx_status_i(pipe_rx6_status_i), .pipe_rx_phy_status_i(pipe_rx6_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i), .pipe_rx_polarity_o(pipe_rx6_polarity_o), .pipe_tx_compliance_o(pipe_tx6_compliance_o), .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o), .pipe_tx_data_o(pipe_tx6_data_o), .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx6_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); pcie_core_pcie_pipe_lane # ( .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) ) pipe_lane_7_i ( .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o), .pipe_rx_data_o(pipe_rx7_data_o), .pipe_rx_valid_o(pipe_rx7_valid_o), .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o), .pipe_rx_status_o(pipe_rx7_status_o), .pipe_rx_phy_status_o(pipe_rx7_phy_status_o), .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o), .pipe_rx_polarity_i(pipe_rx7_polarity_i), .pipe_tx_compliance_i(pipe_tx7_compliance_i), .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i), .pipe_tx_data_i(pipe_tx7_data_i), .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i), .pipe_tx_powerdown_i(pipe_tx7_powerdown_i), .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i), .pipe_rx_data_i(pipe_rx7_data_i), .pipe_rx_valid_i(pipe_rx7_valid_i), .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i), .pipe_rx_status_i(pipe_rx7_status_i), .pipe_rx_phy_status_i(pipe_rx7_phy_status_i), .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i), .pipe_rx_polarity_o(pipe_rx7_polarity_o), .pipe_tx_compliance_o(pipe_tx7_compliance_o), .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o), .pipe_tx_data_o(pipe_tx7_data_o), .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o), .pipe_tx_powerdown_o(pipe_tx7_powerdown_o), .pipe_clk(pipe_clk), .rst_n(rst_n) ); end // if (LINK_CAP_MAX_LINK_WIDTH >= 8) else begin assign pipe_rx4_char_is_k_o = 2'b00; assign pipe_rx4_data_o = 16'h0000; assign pipe_rx4_valid_o = 1'b0; assign pipe_rx4_chanisaligned_o = 1'b0; assign pipe_rx4_status_o = 3'b000; assign pipe_rx4_phy_status_o = 1'b0; assign pipe_rx4_elec_idle_o = 1'b1; assign pipe_rx4_polarity_o = 1'b0; assign pipe_tx4_compliance_o = 1'b0; assign pipe_tx4_char_is_k_o = 2'b00; assign pipe_tx4_data_o = 16'h0000; assign pipe_tx4_elec_idle_o = 1'b1; assign pipe_tx4_powerdown_o = 2'b00; assign pipe_rx5_char_is_k_o = 2'b00; assign pipe_rx5_data_o = 16'h0000; assign pipe_rx5_valid_o = 1'b0; assign pipe_rx5_chanisaligned_o = 1'b0; assign pipe_rx5_status_o = 3'b000; assign pipe_rx5_phy_status_o = 1'b0; assign pipe_rx5_elec_idle_o = 1'b1; assign pipe_rx5_polarity_o = 1'b0; assign pipe_tx5_compliance_o = 1'b0; assign pipe_tx5_char_is_k_o = 2'b00; assign pipe_tx5_data_o = 16'h0000; assign pipe_tx5_elec_idle_o = 1'b1; assign pipe_tx5_powerdown_o = 2'b00; assign pipe_rx6_char_is_k_o = 2'b00; assign pipe_rx6_data_o = 16'h0000; assign pipe_rx6_valid_o = 1'b0; assign pipe_rx6_chanisaligned_o = 1'b0; assign pipe_rx6_status_o = 3'b000; assign pipe_rx6_phy_status_o = 1'b0; assign pipe_rx6_elec_idle_o = 1'b1; assign pipe_rx6_polarity_o = 1'b0; assign pipe_tx6_compliance_o = 1'b0; assign pipe_tx6_char_is_k_o = 2'b00; assign pipe_tx6_data_o = 16'h0000; assign pipe_tx6_elec_idle_o = 1'b1; assign pipe_tx6_powerdown_o = 2'b00; assign pipe_rx7_char_is_k_o = 2'b00; assign pipe_rx7_data_o = 16'h0000; assign pipe_rx7_valid_o = 1'b0; assign pipe_rx7_chanisaligned_o = 1'b0; assign pipe_rx7_status_o = 3'b000; assign pipe_rx7_phy_status_o = 1'b0; assign pipe_rx7_elec_idle_o = 1'b1; assign pipe_rx7_polarity_o = 1'b0; assign pipe_tx7_compliance_o = 1'b0; assign pipe_tx7_char_is_k_o = 2'b00; assign pipe_tx7_data_o = 16'h0000; assign pipe_tx7_elec_idle_o = 1'b1; assign pipe_tx7_powerdown_o = 2'b00; end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8) endgenerate endmodule

module control_mult( clk , rst , lsb_B , init , z , done , sh , reset , add ); input clk; input rst; input lsb_B; input init; input z; output reg done; output reg sh; output reg reset; output reg add; parameter START = 3'b000; parameter CHECK = 3'b001; parameter SHIFT = 3'b010; parameter ADD = 3'b011; parameter END = 3'b100; reg [2:0] state; initial begin done = 0; sh = 0; reset = 0; add = 0; state = 0; end reg [3:0] count; always @(posedge clk) begin if (rst) begin state = START; end else begin case(state) START:begin count=0; if(init) state = CHECK; else state = START; end CHECK: if(lsb_B) state = SHIFT; else state = ADD; SHIFT: state = ADD; ADD: if(z) state = END; else state = CHECK; END:begin count = count + 1; state = (count>9) ? START : END ; // hace falta de 10 ciclos de reloj, para que lea el done y luego cargue el resultado end default: state = START; endcase end end always @(state) begin case(state) START:begin done = 0; sh = 0; reset = 1; add = 0; end CHECK:begin done = 0; sh = 0; reset = 0; add = 0; end SHIFT:begin done = 0; sh = 0; reset = 0; add = 1; end ADD:begin done = 0; sh = 1; reset = 0; add = 0; end END:begin done = 1; sh = 0; reset = 0; add = 0; end default:begin done = 0; sh = 0; reset = 0; add = 0; end endcase end endmodule

// Test constant functions. module main; localparam BYTESIZE = 8; localparam STRLEN = 4; function [STRLEN*BYTESIZE - 1 : 0] bits2text; input [STRLEN-1:0] use_map; integer idx; begin bits2text = 0; for (idx = 0 ; idx < STRLEN ; idx = idx+1) begin bits2text[(idx*BYTESIZE) +: BYTESIZE] = (use_map[idx] == 1'b0)? "1" : "0"; end end endfunction localparam [STRLEN*BYTESIZE - 1 : 0] str0010 = bits2text(4'b0010); localparam [STRLEN*BYTESIZE - 1 : 0] str0100 = bits2text(4'b0100); localparam [STRLEN*BYTESIZE - 1 : 0] str0011 = bits2text(4'b0011); localparam [STRLEN*BYTESIZE - 1 : 0] str1100 = bits2text(4'b1100); reg [STRLEN*BYTESIZE - 1 : 0] tmp; initial begin tmp = bits2text(4'b0010); if (tmp !== str0010) begin $display("FAILED -- str0010=%h, expect %h", str0010, tmp); $finish; end tmp = bits2text(4'b0100); if (tmp !== str0100) begin $display("FAILED -- str0100=%h, expect %h", str0100, tmp); $finish; end tmp = bits2text(4'b0011); if (tmp !== str0011) begin $display("FAILED -- str0011=%h, expect %h", str0011, tmp); $finish; end tmp = bits2text(4'b1100); if (tmp !== str1100) begin $display("FAILED -- str1100=%h, expect %h", str1100, tmp); $finish; end $display("PASSED"); $finish; end endmodule // main

module test (input wire clk, output reg foo, bar, input wire foo_valid, foo_in, input wire bar_valid, bar_in /* */); always @(posedge clk) begin if (foo_valid) foo <= foo_in; if (bar_valid) bar <= bar_in; end endmodule // test module main; reg clk; wire foo, bar; reg foo_valid, foo_in; reg bar_valid, bar_in; test dut (.clk(clk), .foo(foo), .bar(bar), .foo_valid(foo_valid), .bar_valid(bar_valid), .foo_in(foo_in), .bar_in(bar_in)); task fail; begin $display("FAILED -- foo/bar=%b/%b, foo/bar_valid=%b/%b, foo/bar_in=%b/%b", foo, bar, foo_valid, bar_valid, foo_in, bar_in); $finish; end endtask // fail initial begin clk = 0; foo_valid = 1; bar_valid = 1; foo_in = 0; bar_in = 0; #1 clk = 1; #1 clk = 0; if (foo !== 0 || bar !== 0) fail; bar_in = 1; #1 clk = 1; #1 clk = 0; if (foo !== 0 || bar !== 1) fail; foo_in = 1; bar_in = 0; foo_valid = 1; bar_valid = 0; #1 clk = 1; #1 clk = 0; if (foo !== 1 || bar !== 1) fail; $display("PASSED"); end endmodule // main

//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. /////////////////////////////////////////////////////////////////////////////// // Title : DDR controller wrapper // // File : alt_ddrx_controller_wrapper.v // // Abstract : This file is a wrapper that configures DDRx controller /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps // module ddr3_int_alt_ddrx_controller_wrapper ( ctl_clk, ctl_reset_n, ctl_half_clk, ctl_half_clk_reset_n, local_ready, local_read_req, local_write_req, local_wdata_req, local_size, local_burstbegin, local_addr, local_rdata_valid, local_rdata_error, local_rdata, local_wdata, local_be, local_autopch_req, local_multicast, local_init_done, local_refresh_req, local_refresh_chip, local_refresh_ack, local_self_rfsh_req, local_self_rfsh_chip, local_self_rfsh_ack, local_power_down_ack, ctl_cal_success, ctl_cal_fail, ctl_cal_req, ctl_mem_clk_disable, ctl_cal_byte_lane_sel_n, afi_cke, afi_cs_n, afi_ras_n, afi_cas_n, afi_we_n, afi_ba, afi_addr, afi_odt, afi_rst_n, afi_dqs_burst, afi_wdata_valid, afi_wdata, afi_dm, afi_wlat, afi_doing_read, afi_rdata, afi_rdata_valid, csr_write_req, csr_read_req, csr_addr, csr_be, csr_wdata, csr_waitrequest, csr_rdata, csr_rdata_valid, ecc_interrupt, bank_information, bank_open ); //Inserted Generics localparam MEM_TYPE = "DDR3"; localparam LOCAL_SIZE_WIDTH = 6; localparam LOCAL_ADDR_WIDTH = 25; localparam LOCAL_DATA_WIDTH = 128; localparam LOCAL_IF_TYPE = "AVALON"; localparam MEM_IF_CS_WIDTH = 1; localparam MEM_IF_CHIP_BITS = 1; localparam MEM_IF_CKE_WIDTH = 1; localparam MEM_IF_ODT_WIDTH = 1; localparam MEM_IF_ADDR_WIDTH = 14; localparam MEM_IF_ROW_WIDTH = 14; localparam MEM_IF_COL_WIDTH = 10; localparam MEM_IF_BA_WIDTH = 3; localparam MEM_IF_DQS_WIDTH = 4; localparam MEM_IF_DQ_WIDTH = 32; localparam MEM_IF_DM_WIDTH = 4; localparam MEM_IF_CLK_PAIR_COUNT = 1; localparam MEM_IF_CS_PER_DIMM = 1; localparam DWIDTH_RATIO = 4; localparam CTL_LOOK_AHEAD_DEPTH = 8; localparam CTL_CMD_QUEUE_DEPTH = 8; localparam CTL_HRB_ENABLED = 0; localparam CTL_ECC_ENABLED = 0; localparam CTL_ECC_RMW_ENABLED = 0; localparam CTL_ECC_CSR_ENABLED = 0; localparam CTL_CSR_ENABLED = 0; localparam CTL_ODT_ENABLED = 1; localparam CSR_ADDR_WIDTH = 16; localparam CSR_DATA_WIDTH = 32; localparam CTL_OUTPUT_REGD = 0; localparam MEM_CAS_WR_LAT = 6; localparam MEM_ADD_LAT = 0; localparam MEM_TCL = 8; localparam MEM_TRRD = 2; localparam MEM_TFAW = 10; localparam MEM_TRFC = 34; localparam MEM_TREFI = 2341; localparam MEM_TRCD = 5; localparam MEM_TRP = 5; localparam MEM_TWR = 5; localparam MEM_TWTR = 4; localparam MEM_TRTP = 3; localparam MEM_TRAS = 11; localparam MEM_TRC = 15; localparam ADDR_ORDER = 0; localparam MEM_AUTO_PD_CYCLES = 0; localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 2; localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0; localparam CTL_ECC_MULTIPLES_40_72 = 0; localparam CTL_USR_REFRESH = 0; localparam CTL_REGDIMM_ENABLED = 0; localparam MULTICAST_WR_EN = 0; localparam LOW_LATENCY = 0; localparam CTL_DYNAMIC_BANK_ALLOCATION = 0; localparam CTL_DYNAMIC_BANK_NUM = 4; localparam ENABLE_BURST_MERGE = 0; input ctl_clk; input ctl_reset_n; input ctl_half_clk; input ctl_half_clk_reset_n; output local_ready; input local_read_req; input local_write_req; output local_wdata_req; input [LOCAL_SIZE_WIDTH-1:0] local_size; input local_burstbegin; input [LOCAL_ADDR_WIDTH-1:0] local_addr; output local_rdata_valid; output local_rdata_error; output [LOCAL_DATA_WIDTH-1:0] local_rdata; input [LOCAL_DATA_WIDTH-1:0] local_wdata; input [LOCAL_DATA_WIDTH/8-1:0] local_be; input local_autopch_req; input local_multicast; output local_init_done; input local_refresh_req; input [MEM_IF_CS_WIDTH-1:0] local_refresh_chip; output local_refresh_ack; input local_self_rfsh_req; input [MEM_IF_CS_WIDTH-1:0] local_self_rfsh_chip; output local_self_rfsh_ack; output local_power_down_ack; input ctl_cal_success; input ctl_cal_fail; output ctl_cal_req; output [MEM_IF_CLK_PAIR_COUNT - 1:0] ctl_mem_clk_disable; output [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1:0] ctl_cal_byte_lane_sel_n; output [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke; output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n; output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n; output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n; output [(DWIDTH_RATIO/2) - 1:0] afi_we_n; output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba; output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr; output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt; output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n; output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_dqs_burst; output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_wdata_valid; output [(MEM_IF_DQ_WIDTH*DWIDTH_RATIO) - 1:0] afi_wdata; output [(MEM_IF_DM_WIDTH*DWIDTH_RATIO) - 1:0] afi_dm; input [4:0] afi_wlat; output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_doing_read; input [(MEM_IF_DQ_WIDTH * DWIDTH_RATIO) - 1:0] afi_rdata; input [(DWIDTH_RATIO/2) - 1:0] afi_rdata_valid; input csr_write_req; input csr_read_req; input [CSR_ADDR_WIDTH - 1 : 0] csr_addr; input [(CSR_DATA_WIDTH / 8) - 1 : 0] csr_be; input [CSR_DATA_WIDTH - 1 : 0] csr_wdata; output csr_waitrequest; output [CSR_DATA_WIDTH - 1 : 0] csr_rdata; output csr_rdata_valid; output ecc_interrupt; output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) - 1:0] bank_information; output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH)) - 1:0] bank_open; alt_ddrx_controller # ( .MEM_TYPE ( MEM_TYPE ), .LOCAL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ), .LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ), .LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ), .LOCAL_IF_TYPE ( LOCAL_IF_TYPE ), .MEM_IF_CS_WIDTH ( MEM_IF_CS_WIDTH ), .MEM_IF_CHIP_BITS ( MEM_IF_CHIP_BITS ), .MEM_IF_CKE_WIDTH ( MEM_IF_CKE_WIDTH ), .MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ), .MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ), .MEM_IF_ROW_WIDTH ( MEM_IF_ROW_WIDTH ), .MEM_IF_COL_WIDTH ( MEM_IF_COL_WIDTH ), .MEM_IF_BA_WIDTH ( MEM_IF_BA_WIDTH ), .MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ), .MEM_IF_DQ_WIDTH ( MEM_IF_DQ_WIDTH ), .MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ), .MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ), .MEM_IF_CS_PER_DIMM ( MEM_IF_CS_PER_DIMM ), .DWIDTH_RATIO ( DWIDTH_RATIO ), .CTL_LOOK_AHEAD_DEPTH ( CTL_LOOK_AHEAD_DEPTH ), .CTL_CMD_QUEUE_DEPTH ( CTL_CMD_QUEUE_DEPTH ), .CTL_HRB_ENABLED ( CTL_HRB_ENABLED ), .CTL_ECC_ENABLED ( CTL_ECC_ENABLED ), .CTL_ECC_RMW_ENABLED ( CTL_ECC_RMW_ENABLED ), .CTL_ECC_CSR_ENABLED ( CTL_ECC_CSR_ENABLED ), .CTL_ECC_MULTIPLES_40_72 ( CTL_ECC_MULTIPLES_40_72 ), .CTL_CSR_ENABLED ( CTL_CSR_ENABLED ), .CTL_ODT_ENABLED ( CTL_ODT_ENABLED ), .CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ), .CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ), .CSR_DATA_WIDTH ( CSR_DATA_WIDTH ), .CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ), .CTL_USR_REFRESH ( CTL_USR_REFRESH ), .MEM_CAS_WR_LAT ( MEM_CAS_WR_LAT ), .MEM_ADD_LAT ( MEM_ADD_LAT ), .MEM_TCL ( MEM_TCL ), .MEM_TRRD ( MEM_TRRD ), .MEM_TFAW ( MEM_TFAW ), .MEM_TRFC ( MEM_TRFC ), .MEM_TREFI ( MEM_TREFI ), .MEM_TRCD ( MEM_TRCD ), .MEM_TRP ( MEM_TRP ), .MEM_TWR ( MEM_TWR ), .MEM_TWTR ( MEM_TWTR ), .MEM_TRTP ( MEM_TRTP ), .MEM_TRAS ( MEM_TRAS ), .MEM_TRC ( MEM_TRC ), .MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ), .MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ), .MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ), .ADDR_ORDER ( ADDR_ORDER ), .MULTICAST_WR_EN ( MULTICAST_WR_EN ), .LOW_LATENCY ( LOW_LATENCY ), .CTL_DYNAMIC_BANK_ALLOCATION ( CTL_DYNAMIC_BANK_ALLOCATION ), .CTL_DYNAMIC_BANK_NUM ( CTL_DYNAMIC_BANK_NUM ), .ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE ) ) alt_ddrx_controller_inst ( .ctl_clk ( ctl_clk ), .ctl_reset_n ( ctl_reset_n ), .ctl_half_clk ( ctl_half_clk ), .ctl_half_clk_reset_n ( ctl_half_clk_reset_n ), .local_ready ( local_ready ), .local_read_req ( local_read_req ), .local_write_req ( local_write_req ), .local_wdata_req ( local_wdata_req ), .local_size ( local_size ), .local_burstbegin ( local_burstbegin ), .local_addr ( local_addr ), .local_rdata_valid ( local_rdata_valid ), .local_rdata_error ( local_rdata_error ), .local_rdata ( local_rdata ), .local_wdata ( local_wdata ), .local_be ( local_be ), .local_autopch_req ( local_autopch_req ), .local_multicast ( local_multicast ), .local_init_done ( local_init_done ), .local_refresh_req ( local_refresh_req ), .local_refresh_chip ( local_refresh_chip ), .local_refresh_ack ( local_refresh_ack ), .local_self_rfsh_req ( local_self_rfsh_req ), .local_self_rfsh_chip ( local_self_rfsh_chip ), .local_self_rfsh_ack ( local_self_rfsh_ack ), .local_power_down_ack ( local_power_down_ack ), .ctl_cal_success ( ctl_cal_success ), .ctl_cal_fail ( ctl_cal_fail ), .ctl_cal_req ( ctl_cal_req ), .ctl_mem_clk_disable ( ctl_mem_clk_disable ), .ctl_cal_byte_lane_sel_n ( ctl_cal_byte_lane_sel_n ), .afi_cke ( afi_cke ), .afi_cs_n ( afi_cs_n ), .afi_ras_n ( afi_ras_n ), .afi_cas_n ( afi_cas_n ), .afi_we_n ( afi_we_n ), .afi_ba ( afi_ba ), .afi_addr ( afi_addr ), .afi_odt ( afi_odt ), .afi_rst_n ( afi_rst_n ), .afi_dqs_burst ( afi_dqs_burst ), .afi_wdata_valid ( afi_wdata_valid ), .afi_wdata ( afi_wdata ), .afi_dm ( afi_dm ), .afi_wlat ( afi_wlat ), .afi_doing_read ( afi_doing_read ), .afi_doing_read_full ( ), .afi_rdata ( afi_rdata ), .afi_rdata_valid ( afi_rdata_valid ), .csr_write_req ( csr_write_req ), .csr_read_req ( csr_read_req ), .csr_addr ( csr_addr ), .csr_be ( csr_be ), .csr_wdata ( csr_wdata ), .csr_waitrequest ( csr_waitrequest ), .csr_rdata ( csr_rdata ), .csr_rdata_valid ( csr_rdata_valid ), .ecc_interrupt ( ecc_interrupt ), .bank_information ( bank_information ), .bank_open ( bank_open ) ); endmodule

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Any other * * use of such megafunction design, net list, support information, device * * programming or simulation file, or any other related documentation or * * information is prohibited for any other purpose, including, but not * * limited to modification, reverse engineering, de-compiling, or use with * * any other silicon devices, unless such use is explicitly licensed under * * a separate agreement with Altera or a megafunction partner. Title to * * the intellectual property, including patents, copyrights, trademarks, * * trade secrets, or maskworks, embodied in any such megafunction design, * * net list, support information, device programming or simulation file, or * * any other related documentation or information provided by Altera or a * * megafunction partner, remains with Altera, the megafunction partner, or * * their respective licensors. No other licenses, including any licenses * * needed under any third party's intellectual property, are provided herein.* * Copying or modifying any file, or portion thereof, to which this notice * * is attached violates this copyright. * * * * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * * IN THIS FILE. * * * * This agreement shall be governed in all respects by the laws of the State * * of California and by the laws of the United States of America. * * * ******************************************************************************/ /****************************************************************************** * * * This module reads and writes data to the RS232 connectpr on Altera's * * DE1 and DE2 Development and Education Boards. * * * ******************************************************************************/ module altera_up_rs232_counters ( // Inputs clk, reset, reset_counters, // Bidirectionals // Outputs baud_clock_rising_edge, baud_clock_falling_edge, all_bits_transmitted ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter CW = 9; // BAUD COUNTER WIDTH parameter BAUD_TICK_COUNT = 433; parameter HALF_BAUD_TICK_COUNT = 216; parameter TDW = 11; // TOTAL DATA WIDTH /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input reset_counters; // Bidirectionals // Outputs output reg baud_clock_rising_edge; output reg baud_clock_falling_edge; output reg all_bits_transmitted; /***************************************************************************** * Constant Declarations * *****************************************************************************/ /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers reg [(CW-1):0] baud_counter; reg [ 3: 0] bit_counter; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential Logic * *****************************************************************************/ always @(posedge clk) begin if (reset) baud_counter <= {CW{1'b0}}; else if (reset_counters) baud_counter <= {CW{1'b0}}; else if (baud_counter == BAUD_TICK_COUNT) baud_counter <= {CW{1'b0}}; else baud_counter <= baud_counter + 1; end always @(posedge clk) begin if (reset) baud_clock_rising_edge <= 1'b0; else if (baud_counter == BAUD_TICK_COUNT) baud_clock_rising_edge <= 1'b1; else baud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin if (reset) baud_clock_falling_edge <= 1'b0; else if (baud_counter == HALF_BAUD_TICK_COUNT) baud_clock_falling_edge <= 1'b1; else baud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin if (reset) bit_counter <= 4'h0; else if (reset_counters) bit_counter <= 4'h0; else if (bit_counter == TDW) bit_counter <= 4'h0; else if (baud_counter == BAUD_TICK_COUNT) bit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin if (reset) all_bits_transmitted <= 1'b0; else if (bit_counter == TDW) all_bits_transmitted <= 1'b1; else all_bits_transmitted <= 1'b0; end /***************************************************************************** * Combinational Logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule

`timescale 1ns / 1ps // Documented Verilog UART // Copyright (C) 2010 Timothy Goddard ([email protected]) // Distributed under the MIT licence. // // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal // in the Software without restriction, including without limitation the rights // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell // copies of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in // all copies or substantial portions of the Software. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // module uart( input clk, // The master clock for this module input rst, // Synchronous reset. input rx, // Incoming serial line output tx, // Outgoing serial line input transmit, // Signal to transmit input [7:0] tx_byte, // Byte to transmit output received, // Indicated that a byte has been received. output [7:0] rx_byte, // Byte received output is_receiving, // Low when receive line is idle. output is_transmitting, // Low when transmit line is idle. output recv_error // Indicates error in receiving packet. ); parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4) // States for the receiving state machine. // These are just constants, not parameters to override. parameter RX_IDLE = 0; parameter RX_CHECK_START = 1; parameter RX_READ_BITS = 2; parameter RX_CHECK_STOP = 3; parameter RX_DELAY_RESTART = 4; parameter RX_ERROR = 5; parameter RX_RECEIVED = 6; // States for the transmitting state machine. // Constants - do not override. parameter TX_IDLE = 0; parameter TX_SENDING = 1; parameter TX_DELAY_RESTART = 2; reg [10:0] rx_clk_divider = CLOCK_DIVIDE; reg [10:0] tx_clk_divider = CLOCK_DIVIDE; reg [2:0] recv_state = RX_IDLE; reg [5:0] rx_countdown; reg [3:0] rx_bits_remaining; reg [7:0] rx_data; reg tx_out = 1'b1; reg [1:0] tx_state = TX_IDLE; reg [5:0] tx_countdown; reg [3:0] tx_bits_remaining; reg [7:0] tx_data; assign received = recv_state == RX_RECEIVED; assign recv_error = recv_state == RX_ERROR; assign is_receiving = recv_state != RX_IDLE; assign rx_byte = rx_data; assign tx = tx_out; assign is_transmitting = tx_state != TX_IDLE; always @(posedge clk) begin if (rst) begin recv_state = RX_IDLE; tx_state = TX_IDLE; end // The clk_divider counter counts down from // the CLOCK_DIVIDE constant. Whenever it // reaches 0, 1/16 of the bit period has elapsed. // Countdown timers for the receiving and transmitting // state machines are decremented. rx_clk_divider = rx_clk_divider - 1; if (!rx_clk_divider) begin rx_clk_divider = CLOCK_DIVIDE; rx_countdown = rx_countdown - 1; end tx_clk_divider = tx_clk_divider - 1; if (!tx_clk_divider) begin tx_clk_divider = CLOCK_DIVIDE; tx_countdown = tx_countdown - 1; end // Receive state machine case (recv_state) RX_IDLE: begin // A low pulse on the receive line indicates the // start of data. if (!rx) begin // Wait half the period - should resume in the // middle of this first pulse. rx_clk_divider = CLOCK_DIVIDE; rx_countdown = 2; recv_state = RX_CHECK_START; end end RX_CHECK_START: begin if (!rx_countdown) begin // Check the pulse is still there if (!rx) begin // Pulse still there - good // Wait the bit period to resume half-way // through the first bit. rx_countdown = 4; rx_bits_remaining = 8; recv_state = RX_READ_BITS; end else begin // Pulse lasted less than half the period - // not a valid transmission. recv_state = RX_ERROR; end end end RX_READ_BITS: begin if (!rx_countdown) begin // Should be half-way through a bit pulse here. // Read this bit in, wait for the next if we // have more to get. rx_data = {rx, rx_data[7:1]}; rx_countdown = 4; rx_bits_remaining = rx_bits_remaining - 1; recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP; end end RX_CHECK_STOP: begin if (!rx_countdown) begin // Should resume half-way through the stop bit // This should be high - if not, reject the // transmission and signal an error. recv_state = rx ? RX_RECEIVED : RX_ERROR; end end RX_DELAY_RESTART: begin // Waits a set number of cycles before accepting // another transmission. recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE; end RX_ERROR: begin // There was an error receiving. // Raises the recv_error flag for one clock // cycle while in this state and then waits // 2 bit periods before accepting another // transmission. rx_countdown = 8; recv_state = RX_DELAY_RESTART; end RX_RECEIVED: begin // Successfully received a byte. // Raises the received flag for one clock // cycle while in this state. recv_state = RX_IDLE; end endcase // Transmit state machine case (tx_state) TX_IDLE: begin if (transmit) begin // If the transmit flag is raised in the idle // state, start transmitting the current content // of the tx_byte input. tx_data = tx_byte; // Send the initial, low pulse of 1 bit period // to signal the start, followed by the data tx_clk_divider = CLOCK_DIVIDE; tx_countdown = 4; tx_out = 0; tx_bits_remaining = 8; tx_state = TX_SENDING; end end TX_SENDING: begin if (!tx_countdown) begin if (tx_bits_remaining) begin tx_bits_remaining = tx_bits_remaining - 1; tx_out = tx_data[0]; tx_data = {1'b0, tx_data[7:1]}; tx_countdown = 4; tx_state = TX_SENDING; end else begin // Set delay to send out 2 stop bits. tx_out = 1; tx_countdown = 8; tx_state = TX_DELAY_RESTART; end end end TX_DELAY_RESTART: begin // Wait until tx_countdown reaches the end before // we send another transmission. This covers the // "stop bit" delay. tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE; end endcase end endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Case Western Reserve University // Engineer: Matt McConnell // // Create Date: 00:35:00 01/25/2017 // Project Name: EECS301 Digital Design // Design Name: Lab #2 Project // Module Name: CLS_PWM_Interval_Timer // Target Devices: Altera Cyclone V // Tool versions: Quartus v15.0 // Description: PWM Interval Timer // // Dependencies: // ////////////////////////////////////////////////////////////////////////////////// module CLS_PWM_Interval_Timer #( parameter CLK_RATE_HZ = 50000000, // Hz parameter DUTY_RATE_HZ = 1000 // Hz ) ( // Output Signals output reg PWM_TICK, // System Signals input CLK ); // Include Standard Functions header file (needed for bit_index()) `include "StdFunctions.vh" // Initial Parameters initial begin PWM_TICK <= 1'b0; end //!! Add Implementation Here !! // Compute the PWM Interval Counter Parameters localparam PWM_INV_TICKS = CLK_RATE_HZ / DUTY_RATE_HZ; localparam PWM_REG_WIDTH = bit_index(PWM_INV_TICKS); localparam [PWM_REG_WIDTH:0] PWM_INV_LOADVAL = {1'b1, {PWM_REG_WIDTH{1'b0}}} - PWM_INV_TICKS[PWM_REG_WIDTH:0] + 1'b1; wire pwm_inv_tick; reg [PWM_REG_WIDTH:0] pwm_inv_count_reg; // Initialize Registers initial begin pwm_inv_count_reg = PWM_INV_LOADVAL; end // PWM Interval Counter assign pwm_inv_tick = pwm_inv_count_reg[PWM_REG_WIDTH]; always @(*) begin PWM_TICK <= pwm_inv_tick; end always @(posedge CLK) begin if (pwm_inv_tick) pwm_inv_count_reg <= PWM_INV_LOADVAL; else pwm_inv_count_reg <= pwm_inv_count_reg + 1'b1; end endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V `define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V /** * dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage * gates on keep-alive power rail. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__dlybuf4s25kapwr ( //# {{data|Data Signals}} input A , output X , //# {{power|Power}} input KAPWR, input VPB , input VPWR , input VGND , input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg [127:0] in; check #(48) check48 (.*); check #(31) check31 (.*); check #(32) check32 (.*); check #(63) check63 (.*); check #(64) check64 (.*); check #(96) check96 (.*); check #(128) check128 (.*); always_comb begin if (crc[2:0] == 0) in = '0; else if (crc[2:0] == 1) in = ~'0; else if (crc[2:0] == 2) in = 128'b1; else if (crc[2:0] == 3) in = ~ 128'b1; else begin in = {crc, crc}; if (crc[3]) in[31:0] = '0; if (crc[4]) in[63:32] = '0; if (crc[5]) in[95:64] = '0; if (crc[6]) in[127:96] = '0; if (crc[7]) in[31:0] = ~'0; if (crc[8]) in[63:32] = ~'0; if (crc[9]) in[95:64] = ~'0; if (crc[10]) in[127:96] = ~'0; end end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x\n", $time, cyc, in); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc == 99) begin `checkr(check48.sum, 14574057015683440.000000); `checkr(check31.sum, 114141374814.000000); `checkr(check32.sum, 236547942750.000000); `checkr(check63.sum, 513694866079917670400.000000); `checkr(check64.sum, 1002533584033221181440.000000); `checkr(check96.sum, 4377373669974269260279175970816.000000); `checkr(check128.sum, 18358899571808044815012294240949812330496.000000); $write("*-* All Finished *-*\n"); $finish; end end endmodule module check(/*AUTOARG*/ // Inputs in, clk, cyc ); parameter WIDTH = 128; input [127:0] in; wire [WIDTH-1:0] ci = in[WIDTH-1:0]; wire signed [WIDTH-1:0] cis = in[WIDTH-1:0]; real r; real rs; always_comb r = ci; always_comb rs = cis; input clk; input integer cyc; real sum; always_ff @ (negedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum); `endif if (cyc < 10) sum <= 0; else sum <= sum + r + rs; end endmodule

/******************************************************************************/ /* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */ /* 2016-08-01 */ /******************************************************************************/ `default_nettype none `include "define.vh" `include "user_logic.v" `include "sorter.v" /******************************************************************************/ module tb_USER_LOGIC(); reg CLK, RST; wire chnl_rx_clk; wire chnl_rx; wire chnl_rx_ack; wire chnl_rx_last; wire [31:0] chnl_rx_len; wire [30:0] chnl_rx_off; wire [128-1:0] chnl_rx_data; wire chnl_rx_data_valid; wire chnl_rx_data_ren; wire chnl_tx_clk; wire chnl_tx; wire chnl_tx_ack; wire chnl_tx_last; wire [31:0] chnl_tx_len; wire [30:0] chnl_tx_off; wire [128-1:0] chnl_tx_data; wire chnl_tx_data_vaild; wire chnl_tx_data_ren = 1; wire d_busy; wire d_w; wire [`DRAMW-1:0] d_din; wire [`DRAMW-1:0] d_dout; wire d_douten; wire [1:0] d_req; // DRAM access request (read/write) wire [31:0] d_initadr; // dram initial address for the access wire [31:0] d_blocks; // the number of blocks per one access(read/write) reg sortdone; initial begin CLK=0; forever #50 CLK=~CLK; end initial begin RST=1; #400 RST=0; end reg [31:0] cnt; always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1; reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9; always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0; always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1; always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2; always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3; always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4; always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5; always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6; always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7; always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8; always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9; reg [31:0] rslt_cnt; always @(posedge CLK) begin if (RST) begin rslt_cnt <= 0; end else begin if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4; end end always @(posedge CLK) begin if (RST) sortdone <= 0; else if (rslt_cnt == `SORT_ELM) sortdone <= 1; end // Debug Info always @(posedge CLK) begin if (!RST) begin $write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a); $write("|"); if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" "); // $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero); // if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" "); // $write("|"); // if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" "); // $write("|"); // if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" "); $write("|"); $write("(%d)", u.core.state); $write("| %d", u.core.decompressor.dmf_cnt); $write("| %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d", u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt, u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt, u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt, u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt); $write("| %d %d", u.core.ob_a.compressor.tmp.cnt, u.core.ob_b.compressor.tmp.cnt); $write("| %d %d|", u.core.ob_a.OB_cnt, u.core.ob_b.OB_cnt); $write("(%d)", u.core.ob_a.buf_t_cnt); // if (u.core.stree_a.F01_emp) $write("------------------------------------ "); else $write("%08x %08x %08x %08x ", u.core.stree_a.F01_dot[127:96], u.core.stree_a.F01_dot[95:64], u.core.stree_a.F01_dot[63:32], u.core.stree_a.F01_dot[31:0]); if (u.core.decompressor.dmf_cnt > (1<<`IB_SIZE)) begin $write("\noverflow at dc"); $finish(); end if (u.core.im00_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_a"); $finish(); end if (u.core.im01_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_a"); $finish(); end if (u.core.im02_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_a"); $finish(); end if (u.core.im03_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_a"); $finish(); end if (u.core.im04_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im04_a"); $finish(); end if (u.core.im05_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im05_a"); $finish(); end if (u.core.im06_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im06_a"); $finish(); end if (u.core.im07_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im07_a"); $finish(); end if (u.core.im00_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_b"); $finish(); end if (u.core.im01_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_b"); $finish(); end if (u.core.im02_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_b"); $finish(); end if (u.core.im03_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_b"); $finish(); end if (u.core.im04_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im04_b"); $finish(); end if (u.core.im05_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im05_b"); $finish(); end if (u.core.im06_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im06_b"); $finish(); end if (u.core.im07_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im07_b"); $finish(); end if (u.core.ob_a.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_a.cmp"); $finish(); end if (u.core.ob_b.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_b.cmp"); $finish(); end if (u.core.ob_a.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_a"); $finish(); end if (u.core.ob_b.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_b"); $finish(); end // if (u.core.phase_b == 1 && u.core.elem_b == 2097136) $finish(); $write(" "); if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" "); if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" "); // $write("| "); // $write("%d", u.core.dcnt); if (d.app_wdf_wren) $write(" |M %08x %08x ", d_din[63:32], d_din[31:0]); $write("\n"); $fflush(); end end // checking the result generate if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin reg [`MERGW-1:0] check_cnt; always @(posedge CLK) begin if (RST) begin check_cnt[31 : 0] <= 1; check_cnt[63 :32] <= 2; check_cnt[95 :64] <= 3; check_cnt[127:96] <= 4; end else begin if (chnl_tx_data_vaild) begin if (check_cnt != chnl_tx_data) begin $write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation $finish(); // for simulation end check_cnt[31 : 0] <= check_cnt[31 : 0] + 4; check_cnt[63 :32] <= check_cnt[63 :32] + 4; check_cnt[95 :64] <= check_cnt[95 :64] + 4; check_cnt[127:96] <= check_cnt[127:96] + 4; end end end end else if (`INITTYPE=="xorshift") begin integer fp; initial begin fp = $fopen("log.txt", "w"); end always @(posedge CLK) begin if (chnl_tx_data_vaild) begin $fwrite(fp, "%08x\n", chnl_tx_data[31:0]); $fwrite(fp, "%08x\n", chnl_tx_data[63:32]); $fwrite(fp, "%08x\n", chnl_tx_data[95:64]); $fwrite(fp, "%08x\n", chnl_tx_data[127:96]); $fflush(); end if (sortdone) $fclose(fp); end end else begin always @(posedge CLK) begin $write("Error! INITTYPE is wrong.\n"); $write("Please make sure src/define.vh\n"); $finish(); end end endgenerate // Show the elapsed cycles always @(posedge CLK) begin if(sortdone) begin : simulation_finish $write("\nIt takes %d cycles\n", cnt); $write("phase0: %d cycles\n", cnt0); $write("phase1: %d cycles\n", cnt1); $write("phase2: %d cycles\n", cnt2); $write("phase3: %d cycles\n", cnt3); $write("phase4: %d cycles\n", cnt4); $write("phase5: %d cycles\n", cnt5); $write("phase6: %d cycles\n", cnt6); $write("phase7: %d cycles\n", cnt7); $write("phase8: %d cycles\n", cnt8); $write("phase9: %d cycles\n", cnt9); $write("Sorting finished!\n"); $finish(); end end // Stub modules /**********************************************************************************************/ Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len); DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy); /***** Core Module Instantiation *****/ /**********************************************************************************************/ USER_LOGIC u(CLK, RST, chnl_rx_clk, chnl_rx, chnl_rx_ack, chnl_rx_last, chnl_rx_len, chnl_rx_off, chnl_rx_data, chnl_rx_data_valid, chnl_rx_data_ren, chnl_tx_clk, chnl_tx, chnl_tx_ack, chnl_tx_last, chnl_tx_len, chnl_tx_off, chnl_tx_data, chnl_tx_data_vaild, chnl_tx_data_ren, d_busy, // DRAM busy d_din, // DRAM data in d_w, // DRAM write flag d_dout, // DRAM data out d_douten, // DRAM data out enable d_req, // DRAM REQ access request (read/write) d_initadr, // DRAM REQ initial address for the access d_blocks // DRAM REQ the number of blocks per one access ); endmodule /**************************************************************************************************/ /***** Xorshift *****/ /**************************************************************************************************/ module XORSHIFT #(parameter WIDTH = 32, parameter SEED = 1) (input wire CLK, input wire RST, input wire EN, output wire [WIDTH-1:0] RAND_VAL); reg [WIDTH-1:0] x; reg [WIDTH-1:0] y; reg [WIDTH-1:0] z; reg [WIDTH-1:0] w; wire [WIDTH-1:0] t = x^(x<<11); // Mask MSB for not generating the maximum value assign RAND_VAL = {1'b0, w[WIDTH-2:0]}; reg ocen; always @(posedge CLK) ocen <= RST; always @(posedge CLK) begin if (RST) begin x <= 123456789; y <= 362436069; z <= 521288629; w <= 88675123 ^ SEED; end else begin if (EN || ocen) begin x <= y; y <= z; z <= w; w <= (w^(w>>19))^(t^(t>>8)); end end end endmodule /**************************************************************************************************/ module Host_to_FPGA(input wire CLK, input wire RST, input wire ren, output reg chnl_rx, output wire [`MERGW-1:0] dot, output wire doten, output wire [31:0] length); reg rst_buf; always @(posedge CLK) rst_buf <= RST; wire enq; wire deq; wire [`MERGW-1:0] din; wire emp; wire ful; wire [4:0] cnt; reg [`SORTW-1:0] i_d,i_c,i_b,i_a; reg onetime; reg [31:0] enqcnt; reg enqstop; wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00; reg [1:0] selector; // wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} : // (selector == 1) ? {r07,r06,r05,r04} : // (selector == 2) ? {r11,r10,r09,r08} : // (selector == 3) ? {r15,r14,r13,r12} : 0; wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,(r01 % 32'd65536),(r00 % 32'd65536)} : (selector == 1) ? {r07,(r06 % 32'd65536),r05,(r04 % 32'd65536)} : (selector == 2) ? {r11,(r10 % 32'd65536),r09,(r08 % 32'd65536)} : (selector == 3) ? {(r15 % 32'd65536),(r14 % 32'd65536),r13,(r12 % 32'd65536)} : 0; SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt); assign enq = (!enqstop && !ful); assign deq = (ren && !emp); assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a}; assign doten = deq; assign length = `SORT_ELM; always @(posedge CLK) begin if (rst_buf) begin chnl_rx <= 0; onetime <= 1; end else begin chnl_rx <= onetime; onetime <= 0; end end always @(posedge CLK) begin if (rst_buf) enqcnt <= 0; else if (enq) enqcnt <= enqcnt + 4; end always @(posedge CLK) begin if (rst_buf) enqstop <= 0; else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1; end always @(posedge CLK) begin if (rst_buf) selector <= 0; else if (enq) selector <= selector + 1; end generate if (`INITTYPE=="sorted") begin always @(posedge CLK) begin if (rst_buf) begin i_a <= 1; i_b <= 2; i_c <= 3; i_d <= 4; end else begin if (enq) begin i_a <= i_a+4; i_b <= i_b+4; i_c <= i_c+4; i_d <= i_d+4; end end end end else if (`INITTYPE=="reverse") begin always @(posedge CLK) begin if (rst_buf) begin i_a <= `SORT_ELM; i_b <= `SORT_ELM-1; i_c <= `SORT_ELM-2; i_d <= `SORT_ELM-3; end else begin if (enq) begin i_a <= i_a-4; i_b <= i_b-4; i_c <= i_c-4; i_d <= i_d-4; end end end end else if (`INITTYPE=="xorshift") begin XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00); XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01); XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02); XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03); XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04); XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05); XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06); XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07); XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08); XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09); XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10); XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11); XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12); XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13); XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14); XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15); end endgenerate endmodule /**************************************************************************************************/ module DRAM(input wire CLK, // input wire RST, // input wire [1:0] D_REQ, // dram request, load or store input wire [31:0] D_INITADR, // dram request, initial address input wire [31:0] D_ELEM, // dram request, the number of elements input wire [`DRAMW-1:0] D_DIN, // output wire D_W, // output reg [`DRAMW-1:0] D_DOUT, // output reg D_DOUTEN, // output wire D_BUSY); // /******* DRAM ******************************************************/ localparam M_REQ = 0; localparam M_WRITE = 1; localparam M_READ = 2; /////////////////////////////////////////////////////////////////////////////////// reg [`DDR3_CMD] app_cmd; reg app_en; wire [`DRAMW-1:0] app_wdf_data; reg app_wdf_wren; wire app_wdf_end = app_wdf_wren; // outputs of u_dram wire [`DRAMW-1:0] app_rd_data; wire app_rd_data_end; wire app_rd_data_valid=1; // in simulation, always ready !! wire app_rdy = 1; // in simulation, always ready !! wire app_wdf_rdy = 1; // in simulation, always ready !! wire ui_clk = CLK; reg [1:0] mode; reg [`DRAMW-1:0] app_wdf_data_buf; reg [31:0] caddr; // check address reg [31:0] remain, remain2; // reg [7:0] req_state; // /////////////////////////////////////////////////////////////////////////////////// reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0]; reg [31:0] app_addr; reg [31:0] dram_addr; always @(posedge CLK) dram_addr <= app_addr; always @(posedge CLK) begin /***** DRAM WRITE *****/ if (RST) begin end else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data; end assign app_rd_data = mem[app_addr[27:3]]; assign app_wdf_data = D_DIN; assign D_BUSY = (mode!=M_REQ); // DRAM busy assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element ///// READ & WRITE PORT CONTROL (begin) //////////////////////////////////////////// always @(posedge ui_clk) begin if (RST) begin mode <= M_REQ; {app_addr, app_cmd, app_en, app_wdf_wren} <= 0; {D_DOUT, D_DOUTEN} <= 0; {caddr, remain, remain2, req_state} <= 0; end else begin case (mode) ///////////////////////////////////////////////////////////////// request M_REQ: begin D_DOUTEN <= 0; if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request app_cmd <= `DRAM_CMD_WRITE; mode <= M_WRITE; app_wdf_wren <= 0; app_en <= 1; app_addr <= D_INITADR; // param, initial address remain <= D_ELEM; // the number of blocks to be written end else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request app_cmd <= `DRAM_CMD_READ; mode <= M_READ; app_wdf_wren <= 0; app_en <= 1; app_addr <= D_INITADR; // param, initial address remain <= D_ELEM; // param, the number of blocks to be read remain2 <= D_ELEM; // param, the number of blocks to be read end else begin app_wdf_wren <= 0; app_en <= 0; end end //////////////////////////////////////////////////////////////////// read M_READ: begin if (app_rdy) begin // read request is accepted. app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8; remain2 <= remain2 - 1; if(remain2==1) app_en <= 0; end D_DOUTEN <= app_rd_data_valid; // dram data_out enable if (app_rd_data_valid) begin D_DOUT <= app_rd_data; caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8; remain <= remain - 1; if(remain==1) begin mode <= M_REQ; end end end /////////////////////////////////////////////////////////////////// write M_WRITE: begin if (app_rdy && app_wdf_rdy) begin app_wdf_wren <= 1; app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8; remain <= remain - 1; if(remain==1) begin mode <= M_REQ; app_en <= 0; end end else app_wdf_wren <= 0; end endcase end end ///// READ & WRITE PORT CONTROL (end) ////////////////////////////////////// endmodule /**************************************************************************************************/ `default_nettype wire

/* salsaengine.v * * Copyright (c) 2013 kramble * Parts copyright (c) 2011 [email protected] * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. * */ // NB HALFRAM no longer applies, configure via parameters ADDRBITS, THREADS // Bracket this config option in SIM so we don't accidentally leave it set in a live build `ifdef SIM //`define ONETHREAD // Start one thread only (for SIMULATION less confusing and faster startup) `endif `timescale 1ns/1ps module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result ); input hash_clk; input reset; // NB pbkdf_clk domain (need a long reset (at least THREADS+4) to initialize correctly, this is done in pbkdfengine input shift; input start; // NB pbkdf_clk domain output busy; output reg result = 1'b0; parameter SBITS = 8; // Shift data path width input [SBITS-1:0] din; output [SBITS-1:0] dout; // Configure ADDRBITS to allocate RAM for core (automatically sets LOOKAHEAD_GAP) // NB do not use ADDRBITS > 13 for THREADS=8 or ADDRBITS > 14 for THREADS=16 as this is more than // a full scratchpad and the calculation for INT_BITS will be invalid. // These settings are now overriden in ltcminer_icarus.v determined by LOCAL_MINERS ... // These values are for THREADS=8, scratchpad sizes are halved for THREADS=16 // parameter ADDRBITS = 14; // 16MBit RAM allocated to core, full scratchpad for THREADS=16(will not fit LX150) // parameter ADDRBITS = 13; // 8MBit RAM allocated to core, full scratchpad (will not fit LX150) parameter ADDRBITS = 12; // 4MBit RAM allocated to core, half scratchpad // parameter ADDRBITS = 11; // 2MBit RAM allocated to core, quarter scratchpad // parameter ADDRBITS = 10; // 1MBit RAM allocated to core, eighth scratchpad // Do not change THREADS - this must match the salsa pipeline (8 or 16 cycle latency for 8 or 16 threads) parameter THREADS = 16; // NB Phase has THREADS+1 cycles function integer clog2; // Courtesy of razorfishsl, replaces $clog2() input integer value; begin value = value-1; for (clog2=0; value>0; clog2=clog2+1) value = value>>1; end endfunction parameter THREADS_BITS = clog2(THREADS); reg [THREADS_BITS:0]phase = 0; reg [THREADS_BITS:0]phase_d = THREADS; reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0; always @ (posedge hash_clk) // Phase control and sync begin phase <= (phase == THREADS) ? 0 : phase + 1; phase_d <= phase; reset_d <= reset; // Synchronise to hash_clk domain fsmreset <= reset_d; start_d <= start; fsmstart <= start_d; end // Salsa Mix FSM (handles both loading of the scratchpad ROM and the subsequent processing) parameter XSmix = 0, XSload = 1, XSram = 2; // One-hot since these map directly to mux contrls reg [1:0] XCtl = XSmix; parameter R_IDLE=0, R_START=1, R_LOAD=2, R_WRITE=3, R_MIX=4, R_INT=5, R_WAIT=6; reg [2:0] mstate = R_IDLE; reg [10:0] cycle = 11'd0; reg doneROM = 1'd0; // Yes ROM, as its referred thus in the salsa docs reg addrwriteMix = 1'b0; reg addrreadInit = 1'b0; reg addrreadSave = 1'b0; reg xoren = 1'b0; // NB This caclulation does NOT work for ADDRBITS>13 with THREADS=8 or ADDRBITS>14 with THREADS=16 parameter INT_BITS = THREADS_BITS - ADDRBITS + 10; // Max intcycle value is 15 for THREADS=16 and ADDRBITS=10, needing 5 bits // Where INT_BITS==0 we have a full scratchpad and intcycles is not used (though a 1 bit reg[0:0] is still allocated) parameter INT_BITX = (INT_BITS > 0) ? INT_BITS : INT_BITS+1; // Workaround for compilation errors in unused code branches reg [INT_BITS:0] intcycles = 0; // Number of interpolation cycles required wire [511:0] Xmix; reg [511:0] X0; reg [511:0] X1; wire [511:0] X0in; wire [511:0] X1in; wire [511:0] X0out; reg [1023:0] salsaShiftReg; reg [31:0] nonce_sr; // In series with salsaShiftReg assign dout = salsaShiftReg[1023:1024-SBITS]; // sstate is implemented in ram (alternatively could use a rotating shift register) reg [INT_BITS+28:0] sstate [THREADS-1:0]; // NB initialized via a long reset (see pbkdfengine) // List components of sstate here for ease of maintenance ... wire [2:0] mstate_in; wire [10:0] cycle_in; wire [9:0] writeaddr_in; wire doneROM_in; wire addrwriteMix_in; wire addrreadInit_in; wire addrreadSave_in; wire [INT_BITS:0] intcycles_in; wire [9:0] writeaddr_next = writeaddr_in + 10'd1; reg [31:0] snonce [THREADS-1:0]; // Nonce store. Note bidirectional loading below, this will either implement // as registers or dual-port ram, so do NOT integrate with sstate. // NB There is no busy_in or result_in as these flags are NOT saved on a per-thread basis // Convert salsaShiftReg to little-endian word format to match scrypt.c as its easier to debug it // this way rather than recoding the SMix salsa to work with original buffer wire [1023:0] X; `define IDX(x) (((x)+1)*(32)-1):((x)*(32)) genvar i; generate for (i = 0; i < 32; i = i + 1) begin : Xrewire wire [31:0] tmp; assign tmp = salsaShiftReg[`IDX(i)]; assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] }; end endgenerate // NB writeaddr is cycle counter in R_WRITE so use full size regardless of RAM size (* S = "TRUE" *) reg [9:0] writeaddr = 10'd0; // ALTRAM Max is 256 bit width, so use four // Ram is registered on inputs vis ram_addr, ram_din and ram_wren // Output is unregistered, OLD data on write (less delay than NEW??) wire [9:0] Xaddr; wire [ADDRBITS-1:0]rd_addr; wire [ADDRBITS-1:0]wr_addr1; wire [ADDRBITS-1:0]wr_addr2; wire [ADDRBITS-1:0]wr_addr3; wire [ADDRBITS-1:0]wr_addr4; wire [255:0]ram1_din; wire [255:0]ram1_dout; wire [255:0]ram2_din; wire [255:0]ram2_dout; wire [255:0]ram3_din; wire [255:0]ram3_dout; wire [255:0]ram4_din; wire [255:0]ram4_dout; wire [1023:0]ramout; (* S = "TRUE" *) reg ram_wren = 1'b0; wire ram_clk; assign ram_clk = hash_clk; // Uses same clock as hasher for now // Top ram address is reserved for X0Save/X1save, so adjust wire [15:0] memtop = 16'hfffe; // One less than the top memory location (per THREAD bank) wire [9-INT_BITS:0] adj_addr; if (INT_BITS > 0) assign adj_addr = (Xaddr[9:INT_BITS] == memtop[9:INT_BITS]) ? memtop[9-INT_BITS:0] : Xaddr[9:INT_BITS]; else assign adj_addr = Xaddr; wire [THREADS_BITS-1:0] phase_addr; // Prefix for read address assign phase_addr = phase[THREADS_BITS-1:0]; reg [THREADS_BITS-1:0] phase_addr_d = 0; // Prefix for write address assign rd_addr = { phase_addr, (addrreadSave_in | addrreadInit_in) ? (addrreadInit_in ? {ADDRBITS-THREADS_BITS{1'b0}} : memtop[ADDRBITS-THREADS_BITS:1]) : adj_addr }; wire [9:0] writeaddr_adj = addrwriteMix ? memtop[10:1] : writeaddr; assign wr_addr1 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; assign wr_addr2 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; assign wr_addr3 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; assign wr_addr4 = { phase_addr_d, writeaddr_adj[9:INT_BITS] }; // Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method) (* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0; (* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0; (* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0; (* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0; (* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1; (* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2; (* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3; (* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4; ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout); ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout); ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout); ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout); assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout }; // Unregistered output // Two ram data sources, the initial X value and the salsa output assign { ram4_din, ram3_din, ram2_din, ram1_din } = XCtl[0] ? X : { Xmix, X0out}; // Registered input // Salsa unit salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr); // Main multiplexer wire [511:0] Zbits; assign Zbits = {512{xoren}}; // xoren enables xor from ram (else we load from ram) // XSMix is now the default and the initial load is now done via RAM to simplify the pipeline assign X0in = XCtl[1] ? (X0out & Zbits) ^ ramout[511:0] : X0out; assign X1in = XCtl[1] ? (Xmix & Zbits) ^ ramout[1023:512] : Xmix; // Salsa FSM - TODO may want to move this into a separate function (for floorplanning), see hashvariant-C // Hold separate state for each thread (a bit of a kludge to avoid rewriting FSM from scratch) // NB must ensure shift and result do NOT overlap by carefully controlling timing of start signal // NB Phase has THREADS+1 cycles, but we do not save the state for (phase==THREADS) as it is never active assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrwriteMix_in, addrreadInit_in, addrreadSave_in, intcycles_in} = (phase == THREADS ) ? 0 : sstate[phase]; // Interface FSM ensures threads start evenly (required for correct salsa FSM operation) reg busy_flag = 1'b0; `ifdef ONETHREAD // TEST CONTROLLER ... just allow a single thread to run (busy is currently a common flag) // NB the thread automatically restarts after it completes, so its a slight misnomer to say it starts once. reg start_once = 1'b0; wire start_flag; assign start_flag = fsmstart & ~start_once; assign busy = busy_flag; // Ack to pbkdfengine `else // NB start_flag only has effect when a thread is at R_IDLE, ie after reset, normally a thread will automatically // restart on completion. We need to spread the R_IDLE starts evenly to ensure proper ooperation. NB the pbkdf // engine requires busy and result, but this looks alter itself in the salsa FSM, even though these are global // flags. Reset periodically (on loadnonce in pbkdfengine) to ensure it stays in sync. reg [15:0] start_count = 0; // For THREADS=8, lookup_gap=2 salsa takes on average 9*(1024+(1024*1.5)) = 23040 clocks, generically 9*1024*(lookup_gap/2+1.5) // For THREADS=16, use 17*1024*(lookup_gap/2+1.5), where lookupgap is double that for THREADS=8 // This is OK, but only does ADDRBITS=10,11,12 ... // parameter START_INTERVAL = (THREADS==16) ? ((ADDRBITS==12) ? 60928 : (ADDRBITS==11) ? 95744 : 165376) / THREADS : // 16 threads // ((ADDRBITS==12) ? 23040 : (ADDRBITS==11) ? 36864 : 50688) / THREADS ; // 8 threads // This seems to work OK generically (TODO check full scratchpad) ... parameter START_INTERVAL = (THREADS+1) * 1024 * ((1 << (15-ADDRBITS)) * THREADS / 32 + 3) / THREADS / 2; reg start_flag = 1'b0; assign busy = busy_flag; // Ack to pbkdfengine - this will toggle on transtion through R_START `endif always @ (posedge hash_clk) begin X0 <= X0in; X1 <= X1in; if (phase_d != THREADS) sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrwriteMix, addrreadInit, addrreadSave, intcycles }; mstate <= mstate_in; // Set defaults (overridden below as necessary) writeaddr <= writeaddr_in; cycle <= cycle_in; intcycles <= intcycles_in; doneROM <= doneROM_in; addrwriteMix <= addrwriteMix_in; addrreadInit <= addrreadInit_in; addrreadSave <= addrreadSave_in; // Overwritten below, but addrreadSave_in is used above // Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method) rd_addr_z_1 <= {ADDRBITS{fsmreset}}; rd_addr_z_2 <= {ADDRBITS{fsmreset}}; rd_addr_z_3 <= {ADDRBITS{fsmreset}}; rd_addr_z_4 <= {ADDRBITS{fsmreset}}; phase_addr_d <= phase[THREADS_BITS-1:0]; XCtl <= XSmix; // Default states addrreadInit <= 1'b0; // NB addrreadInit_in is the active control so this DOES need to be in sstate addrreadSave <= 1'b0; // Ditto ram_wren <= 1'b0; xoren <= 1'b1; // Interface FSM ensures threads start evenly (required for correct salsa FSM operation) `ifdef ONETHREAD if (fsmstart && phase!=THREADS) start_once <= 1'b1; if (fsmreset) start_once <= 1'b0; `else start_count <= start_count + 1; // start_flag <= 1'b0; // Done below when we transition out of R_IDLE if (fsmreset || start_count == START_INTERVAL) begin start_count <= 0; if (~fsmreset && fsmstart) start_flag <= 1'b1; end `endif // Could use explicit mux for this ... if (shift) begin salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] }; nonce_sr <= { nonce_sr[31-SBITS:0], din}; end else if (XCtl[0] && phase_d != THREADS) // Set at end of previous hash - this is executed regardless of phase begin salsaShiftReg <= ramout; // Simultaneously with XSload nonce_sr <= snonce[phase_d]; // NB bidirectional load snonce[phase_d] <= nonce_sr; end if (fsmreset == 1'b1) begin mstate <= R_IDLE; // This will propagate to all sstate slots as we hold reset for 10 cycles busy_flag <= 1'b0; result <= 1'b0; end else begin case (mstate_in) R_IDLE: begin // R_IDLE only applies after reset. Normally each thread will reenter at S_START and // assumes that input data is waiting (this relies on the threads being started evenly, // hence the interface FSM at the top of this file) if (phase!=THREADS && start_flag) // Ensure (phase==THREADS) slot is never active begin `ifndef ONETHREAD start_flag <= 1'b0; `endif busy_flag <= 1'b0; // Toggle the busy flag low to ack pbkdfengine (its usually already set // since other threads are running) mstate <= R_START; // We cycle the initial data through the RAM to simplify the data path (costs 17 clocks) // Setup to write initial data to ram (on next clock) writeaddr <= 0; addrwriteMix <= 1'b0; ram_wren <= 1'b1; // Setup to read initial data back from ram (17 clocks later) XCtl <= XSload; addrreadInit <= 1'b1; end end R_START: begin // Reentry point after thread completion. ASSUMES new data is ready. XCtl <= XSram; // Load from ram next cycle xoren <= 1'b0; cycle <= 0; doneROM <= 1'b0; busy_flag <= 1'b1; result <= 1'b0; mstate <= R_LOAD; end R_LOAD: begin // Now loading initial data via RAM to simplify data path (costs 17 clocks) writeaddr <= writeaddr_next; if (INT_BITS == 0) ram_wren <= 1'b1; // Full scratchpad needs to write to addr=001 next cycle mstate <= R_WRITE; end R_WRITE: begin writeaddr <= writeaddr_next; if (writeaddr_in==1022) doneROM <= 1'b1; // Need to do one more cycle to update X0,X1 if (doneROM_in) begin addrwriteMix <= 1'b1; // Remains set for duration of R_MIX mstate <= R_MIX; XCtl <= XSram; // Load from ram next cycle (xor'd with XMix) // Need this to cover the case of the initial read being interpolated // NB CODE IS REPLICATED IN R_MIX if (INT_BITS > 0) begin intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] }; // Interpolated addresses if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) // Highest address reserved intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] }; if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) || |Xaddr[INT_BITX-1:0] ) begin ram_wren <= 1'b1; xoren <= 1'b0; // Will do direct load from ram, not xor mstate <= R_INT; // Interpolate end // If intcycles will be set to 1, need to preset for readback if ( ( Xaddr[INT_BITX-1:0] == 1 ) && !( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) ) addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) end // END REPLICATED BLOCK end else begin ram_wren <= (INT_BITS > 0) ? ~|writeaddr_next[INT_BITX-1:0] : 1'b1; end end R_MIX: begin // NB There is an extra step here cf R_WRITE above to read ram data hence 9 not 8 stages. cycle <= cycle_in + 11'd1; if (cycle_in==1023) begin // We now ALWAYS write result to ram, thus simplifying the data path at the cost of 17 clock cycles mstate <= R_WAIT; addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) ram_wren <= 1'b1; // Save result end else begin XCtl <= XSram; // Load from ram next cycle (xor'd with XMix) // NB CODE IS REPLICATED IN R_WRITE if (INT_BITS > 0) begin intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] }; // Interpolated addresses if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) // Highest address reserved intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] }; if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) || |Xaddr[INT_BITX-1:0] ) begin ram_wren <= 1'b1; xoren <= 1'b0; // Will do direct load from ram, not xor mstate <= R_INT; // Interpolate end // If intcycles will be set to 1, need to preset for readback if ( ( Xaddr[INT_BITX-1:0] == 1 ) && !( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] ) ) addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) end // END REPLICATED BLOCK end end R_INT: begin // Interpolate scratchpad for odd addresses intcycles <= intcycles_in - 1; if (intcycles_in==2) addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) if (intcycles_in==1) begin XCtl <= XSram; // Setup to XOR from saved X0/X1 in ram at next cycle mstate <= R_MIX; end // Else mstate remains at R_INT so we continue interpolating end R_WAIT: begin if (fsmstart) // Check data input is ready begin // Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32 busy_flag <= 1'b0; // Will hold at 0 for 17 clocks until set at R_START result <= 1'b1; mstate <= R_START; // Restart immediately // We cycle the initial data through the RAM to simplify the data path (costs 17 clocks) // Setup to write initial data to ram (on next clock) writeaddr <= 0; // Preset to write X on next cycle addrwriteMix <= 1'b0; ram_wren <= 1'b1; // Setup to read initial data back from ram (17 clocks later) XCtl <= XSload; addrreadInit <= 1'b1; end else addrreadSave <= 1'b1; // Preset to read saved data (17 clocks later) end endcase end `ifdef SIM // Print the final Xmix for each cycle to compare with scrypt.c (debugging) // if (mstate==R_MIX) // $display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]); `endif end // always @(posedge hash_clk) endmodule

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Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module video_sys_CPU_test_bench ( // inputs: D_iw, D_iw_op, D_iw_opx, D_valid, E_alu_result, E_mem_byte_en, E_st_data, E_valid, F_pcb, F_valid, R_ctrl_exception, R_ctrl_ld, R_ctrl_ld_non_io, R_dst_regnum, R_wr_dst_reg, W_bstatus_reg, W_cmp_result, W_estatus_reg, W_ienable_reg, W_ipending_reg, W_mem_baddr, W_rf_wr_data, W_status_reg, W_valid, W_vinst, W_wr_data, av_ld_data_aligned_unfiltered, clk, d_address, d_byteenable, d_read, d_write_nxt, i_address, i_read, i_readdata, i_waitrequest, reset_n, // outputs: av_ld_data_aligned_filtered, d_write, test_has_ended ) ; output [ 31: 0] av_ld_data_aligned_filtered; output d_write; output test_has_ended; input [ 31: 0] D_iw; input [ 5: 0] D_iw_op; input [ 5: 0] D_iw_opx; input D_valid; input [ 31: 0] E_alu_result; input [ 3: 0] E_mem_byte_en; input [ 31: 0] E_st_data; input E_valid; input [ 24: 0] F_pcb; input F_valid; input R_ctrl_exception; input R_ctrl_ld; input R_ctrl_ld_non_io; input [ 4: 0] R_dst_regnum; input R_wr_dst_reg; input W_bstatus_reg; input W_cmp_result; input W_estatus_reg; input [ 31: 0] W_ienable_reg; input [ 31: 0] W_ipending_reg; input [ 24: 0] W_mem_baddr; input [ 31: 0] W_rf_wr_data; input W_status_reg; input W_valid; input [ 55: 0] W_vinst; input [ 31: 0] W_wr_data; input [ 31: 0] av_ld_data_aligned_unfiltered; input clk; input [ 24: 0] d_address; input [ 3: 0] d_byteenable; input d_read; input d_write_nxt; input [ 24: 0] i_address; input i_read; input [ 31: 0] i_readdata; input i_waitrequest; input reset_n; wire D_op_add; wire D_op_addi; wire D_op_and; wire D_op_andhi; wire D_op_andi; wire D_op_beq; wire D_op_bge; wire D_op_bgeu; wire D_op_blt; wire D_op_bltu; wire D_op_bne; wire D_op_br; wire D_op_break; wire D_op_bret; wire D_op_call; wire D_op_callr; wire D_op_cmpeq; wire D_op_cmpeqi; wire D_op_cmpge; wire D_op_cmpgei; wire D_op_cmpgeu; wire D_op_cmpgeui; wire D_op_cmplt; wire D_op_cmplti; wire D_op_cmpltu; wire D_op_cmpltui; wire D_op_cmpne; wire D_op_cmpnei; wire D_op_crst; wire D_op_custom; wire D_op_div; wire D_op_divu; wire D_op_eret; wire D_op_flushd; wire D_op_flushda; wire D_op_flushi; wire D_op_flushp; wire D_op_hbreak; wire D_op_initd; wire D_op_initda; wire D_op_initi; wire D_op_intr; wire D_op_jmp; wire D_op_jmpi; wire D_op_ldb; wire D_op_ldbio; wire D_op_ldbu; wire D_op_ldbuio; wire D_op_ldh; wire D_op_ldhio; wire D_op_ldhu; wire D_op_ldhuio; wire D_op_ldl; wire D_op_ldw; wire D_op_ldwio; wire D_op_mul; wire D_op_muli; wire D_op_mulxss; wire D_op_mulxsu; wire D_op_mulxuu; wire D_op_nextpc; wire D_op_nor; wire D_op_opx; wire D_op_or; wire D_op_orhi; wire D_op_ori; wire D_op_rdctl; wire D_op_rdprs; wire D_op_ret; wire D_op_rol; wire D_op_roli; wire D_op_ror; wire D_op_rsv02; wire D_op_rsv09; wire D_op_rsv10; wire D_op_rsv17; wire D_op_rsv18; wire D_op_rsv25; wire D_op_rsv26; wire D_op_rsv33; wire D_op_rsv34; wire D_op_rsv41; wire D_op_rsv42; wire D_op_rsv49; wire D_op_rsv57; wire D_op_rsv61; wire D_op_rsv62; wire D_op_rsv63; wire D_op_rsvx00; wire D_op_rsvx10; wire D_op_rsvx15; wire D_op_rsvx17; wire D_op_rsvx21; wire D_op_rsvx25; wire D_op_rsvx33; wire D_op_rsvx34; wire D_op_rsvx35; wire D_op_rsvx42; wire D_op_rsvx43; wire D_op_rsvx44; wire D_op_rsvx47; wire D_op_rsvx50; wire D_op_rsvx51; wire D_op_rsvx55; wire D_op_rsvx56; wire D_op_rsvx60; wire D_op_rsvx63; wire D_op_sll; wire D_op_slli; wire D_op_sra; wire D_op_srai; wire D_op_srl; wire D_op_srli; wire D_op_stb; wire D_op_stbio; wire D_op_stc; wire D_op_sth; wire D_op_sthio; wire D_op_stw; wire D_op_stwio; wire D_op_sub; wire D_op_sync; wire D_op_trap; wire D_op_wrctl; wire D_op_wrprs; wire D_op_xor; wire D_op_xorhi; wire D_op_xori; wire [ 31: 0] av_ld_data_aligned_filtered; wire av_ld_data_aligned_unfiltered_0_is_x; wire av_ld_data_aligned_unfiltered_10_is_x; wire av_ld_data_aligned_unfiltered_11_is_x; wire av_ld_data_aligned_unfiltered_12_is_x; wire av_ld_data_aligned_unfiltered_13_is_x; wire av_ld_data_aligned_unfiltered_14_is_x; wire av_ld_data_aligned_unfiltered_15_is_x; wire av_ld_data_aligned_unfiltered_16_is_x; wire av_ld_data_aligned_unfiltered_17_is_x; wire av_ld_data_aligned_unfiltered_18_is_x; wire av_ld_data_aligned_unfiltered_19_is_x; wire av_ld_data_aligned_unfiltered_1_is_x; wire av_ld_data_aligned_unfiltered_20_is_x; wire av_ld_data_aligned_unfiltered_21_is_x; wire av_ld_data_aligned_unfiltered_22_is_x; wire av_ld_data_aligned_unfiltered_23_is_x; wire av_ld_data_aligned_unfiltered_24_is_x; wire av_ld_data_aligned_unfiltered_25_is_x; wire av_ld_data_aligned_unfiltered_26_is_x; wire av_ld_data_aligned_unfiltered_27_is_x; wire av_ld_data_aligned_unfiltered_28_is_x; wire av_ld_data_aligned_unfiltered_29_is_x; wire av_ld_data_aligned_unfiltered_2_is_x; wire av_ld_data_aligned_unfiltered_30_is_x; wire av_ld_data_aligned_unfiltered_31_is_x; wire av_ld_data_aligned_unfiltered_3_is_x; wire av_ld_data_aligned_unfiltered_4_is_x; wire av_ld_data_aligned_unfiltered_5_is_x; wire av_ld_data_aligned_unfiltered_6_is_x; wire av_ld_data_aligned_unfiltered_7_is_x; wire av_ld_data_aligned_unfiltered_8_is_x; wire av_ld_data_aligned_unfiltered_9_is_x; reg d_write; wire test_has_ended; assign D_op_call = D_iw_op == 0; assign D_op_jmpi = D_iw_op == 1; assign D_op_ldbu = D_iw_op == 3; assign D_op_addi = D_iw_op == 4; assign D_op_stb = D_iw_op == 5; assign D_op_br = D_iw_op == 6; assign D_op_ldb = D_iw_op == 7; assign D_op_cmpgei = D_iw_op == 8; assign D_op_ldhu = D_iw_op == 11; assign D_op_andi = D_iw_op == 12; assign D_op_sth = D_iw_op == 13; assign D_op_bge = D_iw_op == 14; assign D_op_ldh = D_iw_op == 15; assign D_op_cmplti = D_iw_op == 16; assign D_op_initda = D_iw_op == 19; assign D_op_ori = D_iw_op == 20; assign D_op_stw = D_iw_op == 21; assign D_op_blt = D_iw_op == 22; assign D_op_ldw = D_iw_op == 23; assign D_op_cmpnei = D_iw_op == 24; assign D_op_flushda = D_iw_op == 27; assign D_op_xori = D_iw_op == 28; assign D_op_stc = D_iw_op == 29; assign D_op_bne = D_iw_op == 30; assign D_op_ldl = D_iw_op == 31; assign D_op_cmpeqi = D_iw_op == 32; assign D_op_ldbuio = D_iw_op == 35; assign D_op_muli = D_iw_op == 36; assign D_op_stbio = D_iw_op == 37; assign D_op_beq = D_iw_op == 38; assign D_op_ldbio = D_iw_op == 39; assign D_op_cmpgeui = D_iw_op == 40; assign D_op_ldhuio = D_iw_op == 43; assign D_op_andhi = D_iw_op == 44; assign D_op_sthio = D_iw_op == 45; assign D_op_bgeu = D_iw_op == 46; assign D_op_ldhio = D_iw_op == 47; assign D_op_cmpltui = D_iw_op == 48; assign D_op_initd = D_iw_op == 51; assign D_op_orhi = D_iw_op == 52; assign D_op_stwio = D_iw_op == 53; assign D_op_bltu = D_iw_op == 54; assign D_op_ldwio = D_iw_op == 55; assign D_op_rdprs = D_iw_op == 56; assign D_op_flushd = D_iw_op == 59; assign D_op_xorhi = D_iw_op == 60; assign D_op_rsv02 = D_iw_op == 2; assign D_op_rsv09 = D_iw_op == 9; assign D_op_rsv10 = D_iw_op == 10; assign D_op_rsv17 = D_iw_op == 17; assign D_op_rsv18 = D_iw_op == 18; assign D_op_rsv25 = D_iw_op == 25; assign D_op_rsv26 = D_iw_op == 26; assign D_op_rsv33 = D_iw_op == 33; assign D_op_rsv34 = D_iw_op == 34; assign D_op_rsv41 = D_iw_op == 41; assign D_op_rsv42 = D_iw_op == 42; assign D_op_rsv49 = D_iw_op == 49; assign D_op_rsv57 = D_iw_op == 57; assign D_op_rsv61 = D_iw_op == 61; assign D_op_rsv62 = D_iw_op == 62; assign D_op_rsv63 = D_iw_op == 63; assign D_op_eret = D_op_opx & (D_iw_opx == 1); assign D_op_roli = D_op_opx & (D_iw_opx == 2); assign D_op_rol = D_op_opx & (D_iw_opx == 3); assign D_op_flushp = D_op_opx & (D_iw_opx == 4); assign D_op_ret = D_op_opx & (D_iw_opx == 5); assign D_op_nor = D_op_opx & (D_iw_opx == 6); assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); assign D_op_bret = D_op_opx & (D_iw_opx == 9); assign D_op_ror = D_op_opx & (D_iw_opx == 11); assign D_op_flushi = D_op_opx & (D_iw_opx == 12); assign D_op_jmp = D_op_opx & (D_iw_opx == 13); assign D_op_and = D_op_opx & (D_iw_opx == 14); assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); assign D_op_slli = D_op_opx & (D_iw_opx == 18); assign D_op_sll = D_op_opx & (D_iw_opx == 19); assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); assign D_op_or = D_op_opx & (D_iw_opx == 22); assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); assign D_op_srli = D_op_opx & (D_iw_opx == 26); assign D_op_srl = D_op_opx & (D_iw_opx == 27); assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); assign D_op_callr = D_op_opx & (D_iw_opx == 29); assign D_op_xor = D_op_opx & (D_iw_opx == 30); assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); assign D_op_divu = D_op_opx & (D_iw_opx == 36); assign D_op_div = D_op_opx & (D_iw_opx == 37); assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); assign D_op_mul = D_op_opx & (D_iw_opx == 39); assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); assign D_op_initi = D_op_opx & (D_iw_opx == 41); assign D_op_trap = D_op_opx & (D_iw_opx == 45); assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); assign D_op_add = D_op_opx & (D_iw_opx == 49); assign D_op_break = D_op_opx & (D_iw_opx == 52); assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); assign D_op_sync = D_op_opx & (D_iw_opx == 54); assign D_op_sub = D_op_opx & (D_iw_opx == 57); assign D_op_srai = D_op_opx & (D_iw_opx == 58); assign D_op_sra = D_op_opx & (D_iw_opx == 59); assign D_op_intr = D_op_opx & (D_iw_opx == 61); assign D_op_crst = D_op_opx & (D_iw_opx == 62); assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); assign D_op_opx = D_iw_op == 58; assign D_op_custom = D_iw_op == 50; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d_write <= 0; else d_write <= d_write_nxt; end assign test_has_ended = 1'b0; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //Clearing 'X' data bits assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; always @(posedge clk) begin if (reset_n) if (^(F_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/F_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(D_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/D_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(E_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/E_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(W_valid) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/W_valid is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid) if (^(R_wr_dst_reg) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/R_wr_dst_reg is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_wr_dst_reg) if (^(W_wr_data) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/W_wr_data is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_wr_dst_reg) if (^(R_dst_regnum) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/R_dst_regnum is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(d_write) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_write is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (d_write) if (^(d_byteenable) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_byteenable is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (d_write | d_read) if (^(d_address) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_address is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(d_read) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/d_read is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(i_read) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/i_read is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (i_read) if (^(i_address) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/i_address is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (i_read & ~i_waitrequest) if (^(i_readdata) === 1'bx) begin $write("%0d ns: ERROR: video_sys_CPU_test_bench/i_readdata is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_ctrl_ld) if (^(av_ld_data_aligned_unfiltered) === 1'bx) begin $write("%0d ns: WARNING: video_sys_CPU_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid & R_wr_dst_reg) if (^(W_wr_data) === 1'bx) begin $write("%0d ns: WARNING: video_sys_CPU_test_bench/W_wr_data is 'x'\n", $time); end end reg [31:0] trace_handle; // for $fopen initial begin trace_handle = $fopen("video_sys_CPU.tr"); $fwrite(trace_handle, "version 3\nnumThreads 1\n"); end always @(posedge clk) begin if ((~reset_n || (W_valid)) && ~test_has_ended) $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0); end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // // assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; // //synthesis read_comments_as_HDL off endmodule

// megafunction wizard: %ROM: 1-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: pizza.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.1.1 Build 166 11/26/2013 SJ Full Version // ************************************************************ //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module pizza ( address, clock, q); input [11:0] address; input clock; output [11:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "./sprites/pizza.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" // Retrieval info: PRIVATE: WidthData NUMERIC "12" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/pizza.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "12" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]" // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pizza_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf

(** * Extraction: Extracting ML from Coq *) (** * Basic Extraction *) (** In its simplest form, program extraction from Coq is completely straightforward. *) (** First we say what language we want to extract into. Options are OCaml (the most mature), Haskell (which mostly works), and Scheme (a bit out of date). *) Extraction Language Ocaml. (** Now we load up the Coq environment with some definitions, either directly or by importing them from other modules. *) Require Import SfLib. Require Import ImpCEvalFun. (** Finally, we tell Coq the name of a definition to extract and the name of a file to put the extracted code into. *) Extraction "imp1.ml" ceval_step. (** When Coq processes this command, it generates a file [imp1.ml] containing an extracted version of [ceval_step], together with everything that it recursively depends on. Have a look at this file now. *) (* ############################################################## *) (** * Controlling Extraction of Specific Types *) (** We can tell Coq to extract certain [Inductive] definitions to specific OCaml types. For each one, we must say - how the Coq type itself should be represented in OCaml, and - how each constructor should be translated. *) Extract Inductive bool => "bool" [ "true" "false" ]. (** Also, for non-enumeration types (where the constructors take arguments), we give an OCaml expression that can be used as a "recursor" over elements of the type. (Think Church numerals.) *) Extract Inductive nat => "int" [ "0" "(fun x -> x + 1)" ] "(fun zero succ n -> if n=0 then zero () else succ (n-1))". (** We can also extract defined constants to specific OCaml terms or operators. *) Extract Constant plus => "( + )". Extract Constant mult => "( * )". Extract Constant beq_nat => "( = )". (** Important: It is entirely _your responsibility_ to make sure that the translations you're proving make sense. For example, it might be tempting to include this one Extract Constant minus => "( - )". but doing so could lead to serious confusion! (Why?) *) Extraction "imp2.ml" ceval_step. (** Have a look at the file [imp2.ml]. Notice how the fundamental definitions have changed from [imp1.ml]. *) (* ############################################################## *) (** * A Complete Example *) (** To use our extracted evaluator to run Imp programs, all we need to add is a tiny driver program that calls the evaluator and somehow prints out the result. For simplicity, we'll print results by dumping out the first four memory locations in the final state. Also, to make it easier to type in examples, let's extract a parser from the [ImpParser] Coq module. To do this, we need a few more declarations to set up the right correspondence between Coq strings and lists of OCaml characters. *) Require Import Ascii String. Extract Inductive ascii => char [ "(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))" ] "(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))". Extract Constant zero => "'\000'". Extract Constant one => "'\001'". Extract Constant shift => "fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)". Extract Inlined Constant ascii_dec => "(=)". (** We also need one more variant of booleans. *) Extract Inductive sumbool => "bool" ["true" "false"]. (** The extraction is the same as always. *) Require Import Imp. Require Import ImpParser. Extraction "imp.ml" empty_state ceval_step parse. (** Now let's run our generated Imp evaluator. First, have a look at [impdriver.ml]. (This was written by hand, not extracted.) Next, compile the driver together with the extracted code and execute it, as follows. << ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml ./impdriver >> (The [-w] flags to [ocamlc] are just there to suppress a few spurious warnings.) *) (* ############################################################## *) (** * Discussion *) (** Since we've proved that the [ceval_step] function behaves the same as the [ceval] relation in an appropriate sense, the extracted program can be viewed as a _certified_ Imp interpreter. (Of course, the parser is not certified in any interesting sense, since we didn't prove anything about it.) *) (** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)

////////////////////////////////////////////////////////////////////////////////// // NPM_Toggle_POR for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Ilyong Jung <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Ilyong Jung <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: NPM_Toggle_POR // Module Name: NPM_Toggle_POR // File Name: NPM_Toggle_POR.v // // Version: v1.0.0 // // Description: NFC PM output module reset // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module NPM_Toggle_POR ( iSystemClock , iReset , oReady , oLastStep , iStart , oPO_Reset ); input iSystemClock ; input iReset ; output oReady ; output oLastStep ; input iStart ; output oPO_Reset ; // FSM Parameters/Wires/Regs parameter POR_FSM_BIT = 4; parameter POR_RESET = 4'b0001; parameter POR_READY = 4'b0010; parameter POR_RFRST = 4'b0100; // reset first parameter POR_RLOOP = 4'b1000; // reset loop reg [POR_FSM_BIT-1:0] rPOR_cur_state ; reg [POR_FSM_BIT-1:0] rPOR_nxt_state ; // Internal Wires/Regs reg rReady ; reg [3:0] rTimer ; wire wJOBDone ; reg rPO_Reset ; // Control Signals // Flow Control assign wJOBDone = (4'b1001 == rTimer[3:0]); // 1 + '9' = 10 cycles // FSM // update current state to next state always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rPOR_cur_state <= POR_RESET; end else begin rPOR_cur_state <= rPOR_nxt_state; end end // deside next state always @ ( * ) begin case (rPOR_cur_state) POR_RESET: begin rPOR_nxt_state <= POR_READY; end POR_READY: begin rPOR_nxt_state <= (iStart)? POR_RFRST:POR_READY; end POR_RFRST: begin rPOR_nxt_state <= POR_RLOOP; end POR_RLOOP: begin rPOR_nxt_state <= (wJOBDone)? ((iStart)? POR_RFRST:POR_READY):POR_RLOOP; end default: rPOR_nxt_state <= POR_READY; endcase end // state behaviour always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rReady <= 0; rTimer[3:0] <= 0; rPO_Reset <= 0; end else begin case (rPOR_nxt_state) POR_RESET: begin rReady <= 0; rTimer[3:0] <= 0; rPO_Reset <= 0; end POR_READY: begin rReady <= 1; rTimer[3:0] <= 0; rPO_Reset <= 0; end POR_RFRST: begin rReady <= 0; rTimer[3:0] <= 4'b0000; rPO_Reset <= 1; end POR_RLOOP: begin rReady <= 0; rTimer[3:0] <= rTimer[3:0] + 1'b1; rPO_Reset <= 1; end endcase end end // Output assign oReady = rReady | wJOBDone ; assign oLastStep = wJOBDone ; assign oPO_Reset = rPO_Reset ; endmodule

// // Spartan-3E on-chip RAM interface. // // Author(s): // - Serge Vakulenko, [email protected] // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // either version 2.1 of the License, or (at your option) any // later version. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.opencores.org/lgpl.shtml // //---------------------- // CVS Revision History // // $Log: onchip_ram_top.v,v $ // Revision 1.3 2006-12-22 17:16:26 vak // Added comments and copyrights. // // Revision 1.2 2006/12/22 11:07:34 vak // Amount of on-chip RAM increased to 16 kbytes. // The generated bit file is successfully downloaded to the target board. // Debug interface is functioning (jp1) via Xilinx parallel cable III. // Hello-uart is running fine. // // Revision 1.1 2006/12/22 08:34:00 vak // The design is successfully compiled using on-chip RAM. // // synopsys translate_off `include "timescale.v" // synopsys translate_on module onchip_ram_top ( // // I/O Ports // input wb_clk_i, input wb_rst_i, // // WB slave i/f // input [31:0] wb_dat_i, output [31:0] wb_dat_o, input [31:0] wb_adr_i, input [3:0] wb_sel_i, input wb_we_i, input wb_cyc_i, input wb_stb_i, output wb_ack_o, output wb_err_o ); // // Paraneters // parameter AW = 12; // RAM size = 4 kwords (16 kbytes) // // Internal wires and regs // wire we; wire [3:0] be_i; reg ack_we; reg ack_re; // // Aliases and simple assignments // assign wb_ack_o = ack_re | ack_we; assign wb_err_o = wb_cyc_i & wb_stb_i & (| wb_adr_i[23:AW+2]); // If Access to > (8-bit leading prefix ignored) assign we = wb_cyc_i & wb_stb_i & wb_we_i & (| wb_sel_i[3:0]); assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; // // Write acknowledge // always @ (negedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) ack_we <= 1'b0; else if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) ack_we <= #1 1'b1; else ack_we <= #1 1'b0; end // // Read acknowledge // always @ (posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) ack_re <= 1'b0; else if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) ack_re <= #1 1'b1; else ack_re <= #1 1'b0; end // // Generate 8 blocks of standard Xilinx library component: // 16K-Bit Data and 2K-Bit Parity Single Port Block RAM // RAMB16_S4 block_ram_00 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [3 : 0]), .DO (wb_dat_o [3 : 0]), .EN (be_i [0]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_01 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [7 : 4]), .DO (wb_dat_o [7 : 4]), .EN (be_i [0]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_10 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [11 : 8]), .DO (wb_dat_o [11 : 8]), .EN (be_i [1]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_11 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [15 : 12]), .DO (wb_dat_o [15 : 12]), .EN (be_i [1]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_20 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [19 : 16]), .DO (wb_dat_o [19 : 16]), .EN (be_i [2]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_21 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [23 : 20]), .DO (wb_dat_o [23 : 20]), .EN (be_i [2]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_30 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [27 : 24]), .DO (wb_dat_o [27 : 24]), .EN (be_i [3]), .WE (we), .SSR (0)); RAMB16_S4 block_ram_31 ( .ADDR (wb_adr_i [AW+1 : 2]), .CLK (wb_clk_i), .DI (wb_dat_i [31 : 28]), .DO (wb_dat_o [31 : 28]), .EN (be_i [3]), .WE (we), .SSR (0)); endmodule

// A restricted 27x27 bit multiplier. (The restriction is that if the // MSB bit of opa is set the three LSB bits of opa must be zero as we // will otherwise get an overflow in the pre-adder portion of the DSP // blocks.) module mult_27x27 (input wire clk, input wire [26:0] opa, opb, output reg [53:0] res); parameter LATENCY = 0; // Unused so far... // FIXME - sanity check for LATENCY! wire [26:0] multop_a; wire [26:0] multop_b; assign multop_a = opa; assign multop_b = opb; // Implementation of 27x27 using a 24x35 bit multiplier together with some LUTS: // // res_tmp = op_a*(op_b[26:3] + op_a[2])* 8 // // Note: The clever detail when using this module for HRFP_16 is // that we know that if op_b[2] is set, op_b[26] can never be set, // which ensures that we can never get an overflow in the addition // above which would overflow the multiplier in the DSP48E1 block! // (Thus the method below is not going to work in the general case // for a 27x27 bit multiplier.) // // case(op_b[2:0]) // 3'b000: foo = 0; // 3'b001: foo = op_a; // 3'b010: foo = op_a << 1; // 3'b011: foo = op_a + op_a << 1; // 3'b100: foo = op_a << 2; // Eller möjligtvis op_a << 1 + op_a << 1 // 3'b101: foo = op_a + op_a << 1; // 3'b110: foo = op_a << 1; // 3'b111: foo = op_a; // endcase // if(op_b[2]) begin // res = res_tmp - foo; // end else begin // res = res_tmp + foo; // end `define INSTANTIATED `ifdef INSTANTIATED wire [47:0] p_low, p_high; reg [47:0] p_low_delay; wire [47:0] pcout_low; reg [47:0] c_in; reg carryin; reg dosub, dosub1; always @(posedge clk) begin dosub1 <= multop_a[2]; dosub <= dosub1; end DSP48E1 #(.AREG(1), .ADREG(0), // Hopefully isn't needed... .BREG(1), .ALUMODEREG(1), .CARRYINREG(1), .CARRYINSELREG(1), .CREG(1), .DREG(1), .INMODEREG(1), .MREG(1), .OPMODEREG(1), .PREG(1), .A_INPUT("DIRECT"), .B_INPUT("DIRECT"), .USE_DPORT("TRUE"), .USE_MULT("MULTIPLY"), .USE_SIMD("ONE48")) low( // Outputs .ACOUT (), .BCOUT (), .CARRYCASCOUT (), .CARRYOUT (), .MULTSIGNOUT (), .OVERFLOW (), .P (p_low), .PATTERNBDETECT (), .PATTERNDETECT (), .PCOUT (pcout_low), .UNDERFLOW (), // Inputs .A ({6'h0, multop_a[26:3]}), .ACIN (), .ALUMODE ({3'b000, dosub1}), .B ({1'b0, multop_b[16:0]}), .BCIN (), .C (c_in), .CARRYCASCIN (), .CARRYIN (carryin), // For subtract... .CARRYINSEL (3'h0), .CEA1 (1'b1), .CEA2 (1'b1), .CEAD (1'b1), .CEALUMODE (1'b1), .CEB1 (1'b1), .CEB2 (1'b1), .CEC (1'b1), .CECARRYIN (1'b1), .CECTRL (1'b1), .CED (1'b1), .CEINMODE (1'b1), .CEM (1'b1), .CEP (1'b1), .CLK (clk), .D ({24'h0, multop_a[2]}), .INMODE (5'b00101), .MULTSIGNIN (1'b0), .OPMODE (7'b0110101), // P = A*B + C (or minus C depending on ALUMODE above) .PCIN (48'b0), .RSTA (1'b0), .RSTALLCARRYIN (1'b0), .RSTALUMODE (1'b0), .RSTB (1'b0), .RSTC (1'b0), .RSTCTRL (1'b0), .RSTD (1'b0), .RSTINMODE (1'b0), .RSTM (1'b0), .RSTP (1'b0)); reg [28:0] multfix; reg [28:0] add1, add2; always @* begin case(multop_a[2:0]) 3'b000: begin add1 <= 0; add2 <= 0; end 3'b001: begin add1 <= multop_b; add2 <= 0; end 3'b010: begin add1 <= 0; add2 <= multop_b << 1; end 3'b011: begin add1 <= multop_b; add2 <= multop_b << 1; end 3'b100: begin add1 <= multop_b <<1; add2 <= multop_b << 1; end 3'b101: begin add1 <= multop_b; add2 <= multop_b << 1; end 3'b110: begin add1 <= 0; add2 <= multop_b << 1; end 3'b111: begin add1 <= multop_b; add2 <= 0; end endcase multfix = add1 + add2; end // Generate carry the carry input to the DSP48E1 based adder always @(posedge clk) begin c_in <= multfix >> 3; // Final three LSB bits are calculated below using a lookup table... if(multop_a[2] == 0) begin carryin <= 0; end else begin carryin <= 0; if(~multfix[2:0] == 3'b111) begin carryin <= 1; end end end reg [2:0] lsbresult1, lsbresult2, lsbresult3, lsbresult4; always @(posedge clk) begin lsbresult1 <= multop_a[2:0]*multop_b[2:0]; lsbresult2 <= lsbresult1; lsbresult3 <= lsbresult2; lsbresult4 <= lsbresult3; p_low_delay <= p_low; end DSP48E1 #(.AREG(2), .ADREG(0), // Hopefully isn't needed... .BREG(2), .ALUMODEREG(1), .CARRYINREG(1), .CARRYINSELREG(1), .CREG(1), .DREG(1), .INMODEREG(1), .MREG(1), .OPMODEREG(1), .PREG(1), .A_INPUT("DIRECT"), .B_INPUT("DIRECT"), .USE_DPORT("TRUE"), .USE_MULT("MULTIPLY"), .USE_SIMD("ONE48")) high( // Outputs .ACOUT (), .BCOUT (), .CARRYCASCOUT (), .CARRYOUT (), .MULTSIGNOUT (), .OVERFLOW (), .P (p_high), .PATTERNBDETECT (), .PATTERNDETECT (), .PCOUT (), .UNDERFLOW (), // Inputs .A ({6'h0, multop_a[26:3]}), .ACIN (), .ALUMODE ({4'b0000}), .B ({8'b0, multop_b[26:17]}), .BCIN (), .C (48'h0), .CARRYCASCIN (), .CARRYIN (1'b0), .CARRYINSEL (3'h0), .CEA1 (1'b1), .CEA2 (1'b1), .CEAD (1'b1), .CEALUMODE (1'b1), .CEB1 (1'b1), .CEB2 (1'b1), .CEC (1'b1), .CECARRYIN (1'b1), .CECTRL (1'b1), .CED (1'b1), .CEINMODE (1'b1), .CEM (1'b1), .CEP (1'b1), .CLK (clk), .D ({24'h0, dosub1}), .INMODE (5'b00100), .MULTSIGNIN (1'b0), .OPMODE (7'b1010101), // P = A*B + PCIN >> 17 .PCIN (pcout_low), .RSTA (1'b0), .RSTALLCARRYIN (1'b0), .RSTALUMODE (1'b0), .RSTB (1'b0), .RSTC (1'b0), .RSTCTRL (1'b0), .RSTD (1'b0), .RSTINMODE (1'b0), .RSTM (1'b0), .RSTP (1'b0)); always @* begin res = {p_high, p_low_delay[16:0], lsbresult4}; end `endif endmodule

module tx_buffer_inband ( //System input wire usbclk, input wire bus_reset, input wire reset, input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, //output transmit signals output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, output wire [15:0] tx_i_1, output wire [15:0] tx_q_1, output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, input wire txclk, input wire txstrobe, input wire WR, input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, //command reader io output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, input wire rx_WR_enabled, //register io output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr, input wire [31:0] reg_data_out, //input characteristic signals input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, output wire [1:0] tx_underrun, //system stop output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1); /* Debug paramters */ parameter STROBE_RATE_0 = 8'd1 ; parameter STROBE_RATE_1 = 8'd2 ; parameter NUM_CHAN = 2 ; /* To generate channel readers */ genvar i ; /* These will eventually be external register */ reg [31:0] adc_time ; wire datapattern_err; wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; wire [31:0] rssi [3:0]; assign rssi[0] = rssi_0; assign rssi[1] = rssi_1; assign rssi[2] = rssi_2; assign rssi[3] = rssi_3; always @(posedge txclk) if (reset) adc_time <= 0; else if (txstrobe) adc_time <= adc_time + 1; /* Connections between tx_usb_fifo_reader and cnannel/command processing blocks */ wire [31:0] tx_data_bus ; wire [NUM_CHAN:0] chan_WR ; wire [NUM_CHAN:0] chan_done ; /* Connections between data block and the FX2/TX chains */ wire [NUM_CHAN:0] chan_underrun; wire [NUM_CHAN:0] chan_txempty; /* Conections between tx_data_packet_fifo and its reader + strobe generator */ wire [31:0] chan_fifodata [NUM_CHAN:0] ; wire chan_pkt_waiting [NUM_CHAN:0] ; wire chan_rdreq [NUM_CHAN:0] ; wire chan_skip [NUM_CHAN:0] ; wire chan_have_space [NUM_CHAN:0] ; wire chan_txstrobe [NUM_CHAN-1:0] ; wire [14:0] debug [NUM_CHAN:0]; /* Outputs to transmit chains */ wire [15:0] tx_i [NUM_CHAN-1:0] ; wire [15:0] tx_q [NUM_CHAN-1:0] ; /* TODO: Figure out how to write this genericly */ assign have_space = chan_have_space[0];// & chan_have_space[1]; assign tx_empty = chan_txempty[0];// & chan_txempty[1] ; assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty; assign test_bit0 = datapattern_err; /* Debug statement */ assign txstrobe_rate[0] = STROBE_RATE_0 ; assign txstrobe_rate[1] = STROBE_RATE_1 ; assign tx_q_2 = 16'b0 ; assign tx_i_2 = 16'b0 ; assign tx_q_3 = 16'b0 ; assign tx_i_3 = 16'b0 ; assign tx_i_3 = 16'b0 ; wire [31:0] usbdata_final; wire WR_final; assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, chan_pkt_waiting[0], chan_pkt_waiting[1], chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]}; tx_packer tx_usb_packer (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR), .usbdata(usbdata), .reset(reset), .txclk(txclk), .usbdata_final(usbdata_final), .WR_final(WR_final), .test_bit0(), .test_bit1(test_bit1)); channel_demux channel_demuxer (.usbdata_final(usbdata_final), .WR_final(WR_final), .reset(reset), .txclk(txclk), .WR_channel(chan_WR), .WR_done_channel(chan_done), .ram_data(tx_data_bus)); generate for (i = 0 ; i < NUM_CHAN; i = i + 1) begin : generate_channel_readers assign tx_underrun[i] = chan_underrun[i]; channel_ram tx_data_packet_fifo (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[i]), .WR_done(chan_done[i]), .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]), .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]), .RD_done(chan_skip[i])); chan_fifo_reader tx_chan_reader (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe), .adc_time(adc_time), .samples_format(4'b0), .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]), .skip(chan_skip[i]), .rdreq(chan_rdreq[i]), .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]), .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]), .threshhold(threshhold), .rssi_wait(rssi_wait)); end endgenerate channel_ram tx_cmd_packet_fifo (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]), .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]), .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]), .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN])); cmd_reader tx_cmd_reader (.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]), .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]), .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus), .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr), .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time)); endmodule // tx_buffer

// -*- verilog -*- // Copyright (c) 2012 Ben Reynwar // Released under MIT License (see LICENSE.txt) module message_slicer #( parameter N_SLICES = 2, parameter WIDTH = 32, parameter BUFFER_LENGTH = 32 ) ( input clk, input rst_n, input wire [WIDTH*N_SLICES-1:0] in_data, input wire in_nd, output reg [WIDTH-1:0] out_data, output reg out_nd, output wire error ); function integer clog2; input integer value; begin value = value-1; for (clog2=0; value>0; clog2=clog2+1) value = value>>1; end endfunction localparam integer LOG_N_SLICES = clog2(N_SLICES); reg read_delete; wire [N_SLICES*WIDTH-1:0] read_data; wire read_full; buffer_BB #(N_SLICES*WIDTH, BUFFER_LENGTH) buffer_0 (.clk(clk), .rst_n(rst_n), .write_strobe(in_nd), .write_data(in_data), .read_delete(read_delete), .read_full(read_full), .read_data(read_data), .error(error) ); reg [LOG_N_SLICES-1:0] pos; wire [WIDTH-1:0] sliced_data[N_SLICES-1:0]; genvar i; generate for(i=0; i<N_SLICES; i=i+1) begin: loop_0 assign sliced_data[i] = read_data[WIDTH*(i+1)-1 -:WIDTH]; end endgenerate // Send out data from the buffer. always @ (posedge clk) begin out_nd <= 1'b0; read_delete <= 1'b0; if (!rst_n) begin pos <= N_SLICES-1; end else if (read_full) begin out_nd <= 1'b1; out_data <= sliced_data[pos]; if (pos == 0) begin pos <= N_SLICES-1; read_delete <= 1'b1; end else pos <= pos - 1; end end endmodule

//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_app_7x.v // Version : 1.11 //-- //-- Description: PCI Express Endpoint sample application //-- design. //-- //------------------------------------------------------------------------------ `timescale 1ps / 1ps `define PCI_EXP_EP_OUI 24'h000A35 `define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI} `define PCI_EXP_EP_DSN_2 32'h00000001 module pcie_app_7x#( parameter C_DATA_WIDTH = 64, // RX/TX interface data width // Do not override parameters below this line parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width parameter TCQ = 1 )( input user_clk, input user_reset, input user_lnk_up, // Tx //input [5:0] tx_buf_av, //input tx_cfg_req, //input tx_err_drop, output tx_cfg_gnt, input s_axis_tx_tready, output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, output [3:0] s_axis_tx_tuser, output s_axis_tx_tlast, output s_axis_tx_tvalid, // Rx output rx_np_ok, output rx_np_req, input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, input m_axis_rx_tlast, input m_axis_rx_tvalid, output m_axis_rx_tready, input [21:0] m_axis_rx_tuser, // Flow Control //input [11:0] fc_cpld, //input [7:0] fc_cplh, //input [11:0] fc_npd, //input [7:0] fc_nph, //input [11:0] fc_pd, //input [7:0] fc_ph, output [2:0] fc_sel, // CFG output cfg_err_cor, output cfg_err_ur, output cfg_err_ecrc, output cfg_err_cpl_timeout, output cfg_err_cpl_unexpect, output cfg_err_cpl_abort, output cfg_err_atomic_egress_blocked, output cfg_err_internal_cor, output cfg_err_malformed, output cfg_err_mc_blocked, output cfg_err_poisoned, output cfg_err_norecovery, output cfg_err_acs, output cfg_err_internal_uncor, output cfg_pm_halt_aspm_l0s, output cfg_pm_halt_aspm_l1, output cfg_pm_force_state_en, output [1:0] cfg_pm_force_state, output cfg_err_posted, output cfg_err_locked, output [47:0] cfg_err_tlp_cpl_header, // input cfg_err_cpl_rdy, output cfg_interrupt, // input cfg_interrupt_rdy, output cfg_interrupt_assert, output [7:0] cfg_interrupt_di, // input [7:0] cfg_interrupt_do, // input [2:0] cfg_interrupt_mmenable, // input cfg_interrupt_msienable, // input cfg_interrupt_msixenable, // input cfg_interrupt_msixfm, output cfg_turnoff_ok, input cfg_to_turnoff, output cfg_trn_pending, output cfg_pm_wake, input [7:0] cfg_bus_number, input [4:0] cfg_device_number, input [2:0] cfg_function_number, // input [15:0] cfg_status, // input [15:0] cfg_command, // input [15:0] cfg_dstatus, // input [15:0] cfg_dcommand, // input [15:0] cfg_lstatus, // input [15:0] cfg_lcommand, // input [15:0] cfg_dcommand2, // input [2:0] cfg_pcie_link_state, output cfg_interrupt_stat, output [4:0] cfg_pciecap_interrupt_msgnum, output [1:0] pl_directed_link_change, // input [5:0] pl_ltssm_state, output [1:0] pl_directed_link_width, output pl_directed_link_speed, output pl_directed_link_auton, output pl_upstream_prefer_deemph, // input [1:0] pl_sel_lnk_width, // input pl_sel_lnk_rate, // input pl_link_gen2_cap, // input pl_link_partner_gen2_supported, // input [2:0] pl_initial_link_width, // input pl_link_upcfg_cap, // input [1:0] pl_lane_reversal_mode, // input pl_received_hot_rst, output [127:0] cfg_err_aer_headerlog, output [4:0] cfg_aer_interrupt_msgnum, // input cfg_err_aer_headerlog_set, // input cfg_aer_ecrc_check_en, // input cfg_aer_ecrc_gen_en, output [31:0] cfg_mgmt_di, output [3:0] cfg_mgmt_byte_en, output [9:0] cfg_mgmt_dwaddr, output cfg_mgmt_wr_en, output cfg_mgmt_rd_en, output cfg_mgmt_wr_readonly, output [63:0] cfg_dsn ); //----------------------------------------------------------------------------------------------------------------// // PCIe Block EP Tieoffs - Example PIO doesn't support the following inputs // //----------------------------------------------------------------------------------------------------------------// assign fc_sel = 3'b0; assign rx_np_ok = 1'b1; // Allow Reception of Non-posted Traffic assign rx_np_req = 1'b1; // Always request Non-posted Traffic if available assign s_axis_tx_tuser[0] = 1'b0; // Unused for V6 assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet assign s_axis_tx_tuser[2] = 1'b0; // Stream packet assign tx_cfg_gnt = 1'b1; // Always allow transmission of Config traffic within block assign cfg_err_cor = 1'b0; // Never report Correctable Error assign cfg_err_ur = 1'b0; // Never report UR assign cfg_err_ecrc = 1'b0; // Never report ECRC Error assign cfg_err_cpl_timeout = 1'b0; // Never report Completion Timeout assign cfg_err_cpl_abort = 1'b0; // Never report Completion Abort assign cfg_err_cpl_unexpect = 1'b0; // Never report unexpected completion assign cfg_err_posted = 1'b0; // Never qualify cfg_err_* inputs assign cfg_err_locked = 1'b0; // Never qualify cfg_err_ur or cfg_err_cpl_abort assign cfg_pm_wake = 1'b0; // Never direct the core to send a PM_PME Message assign cfg_trn_pending = 1'b0; // Never set the transaction pending bit in the Device Status Register assign cfg_err_atomic_egress_blocked = 1'b0; // Never report Atomic TLP blocked assign cfg_err_internal_cor = 1'b0; // Never report internal error occurred assign cfg_err_malformed = 1'b0; // Never report malformed error assign cfg_err_mc_blocked = 1'b0; // Never report multi-cast TLP blocked assign cfg_err_poisoned = 1'b0; // Never report poisoned TLP received assign cfg_err_norecovery = 1'b0; // Never qualify cfg_err_poisoned or cfg_err_cpl_timeout assign cfg_err_acs = 1'b0; // Never report an ACS violation assign cfg_err_internal_uncor = 1'b0; // Never report internal uncorrectable error assign cfg_pm_halt_aspm_l0s = 1'b0; // Allow entry into L0s assign cfg_pm_halt_aspm_l1 = 1'b0; // Allow entry into L1 assign cfg_pm_force_state_en = 1'b0; // Do not qualify cfg_pm_force_state assign cfg_pm_force_state = 2'b00; // Do not move force core into specific PM state assign cfg_err_aer_headerlog = 128'h0; // Zero out the AER Header Log assign cfg_aer_interrupt_msgnum = 5'b00000; // Zero out the AER Root Error Status Register assign cfg_interrupt_stat = 1'b0; // Never set the Interrupt Status bit assign cfg_pciecap_interrupt_msgnum = 5'b00000; // Zero out Interrupt Message Number assign cfg_interrupt_assert = 1'b0; // Always drive interrupt de-assert assign cfg_interrupt = 1'b0; // Never drive interrupt by qualifying cfg_interrupt_assert assign pl_directed_link_change = 2'b00; // Never initiate link change assign pl_directed_link_width = 2'b00; // Zero out directed link width assign pl_directed_link_speed = 1'b0; // Zero out directed link speed assign pl_directed_link_auton = 1'b0; // Zero out link autonomous input assign pl_upstream_prefer_deemph = 1'b1; // Zero out preferred de-emphasis of upstream port assign cfg_interrupt_di = 8'b0; // Do not set interrupt fields assign cfg_err_tlp_cpl_header = 48'h0; // Zero out the header information assign cfg_mgmt_di = 32'h0; // Zero out CFG MGMT input data bus assign cfg_mgmt_byte_en = 4'h0; // Zero out CFG MGMT byte enables assign cfg_mgmt_dwaddr = 10'h0; // Zero out CFG MGMT 10-bit address port assign cfg_mgmt_wr_en = 1'b0; // Do not write CFG space assign cfg_mgmt_rd_en = 1'b0; // Do not read CFG space assign cfg_mgmt_wr_readonly = 1'b0; // Never treat RO bit as RW assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1}; // Assign the input DSN //----------------------------------------------------------------------------------------------------------------// // Programmable I/O Module // //----------------------------------------------------------------------------------------------------------------// wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number }; // wire cfg_bus_mstr_enable = cfg_command[2]; reg s_axis_tx_tready_i ; always @(posedge user_clk) begin if (user_reset) s_axis_tx_tready_i <= #TCQ 1'b0; else s_axis_tx_tready_i <= #TCQ s_axis_tx_tready; end //----------------------------------------------------------------------------------------------------------------// PIO #( .C_DATA_WIDTH( C_DATA_WIDTH ), .KEEP_WIDTH( KEEP_WIDTH ), .TCQ( TCQ ) ) PIO ( .user_clk ( user_clk ), // I .user_reset ( user_reset ), // I .user_lnk_up ( user_lnk_up ), // I .s_axis_tx_tready ( s_axis_tx_tready_i ), // I .s_axis_tx_tdata ( s_axis_tx_tdata ), // O .s_axis_tx_tkeep ( s_axis_tx_tkeep ), // O .s_axis_tx_tlast ( s_axis_tx_tlast ), // O .s_axis_tx_tvalid ( s_axis_tx_tvalid ), // O .tx_src_dsc ( s_axis_tx_tuser[3] ), // O .m_axis_rx_tdata( m_axis_rx_tdata ), // I .m_axis_rx_tkeep( m_axis_rx_tkeep ), // I .m_axis_rx_tlast( m_axis_rx_tlast ), // I .m_axis_rx_tvalid( m_axis_rx_tvalid ), // I .m_axis_rx_tready( m_axis_rx_tready ), // O .m_axis_rx_tuser ( m_axis_rx_tuser ), // I .cfg_to_turnoff ( cfg_to_turnoff ), // I .cfg_turnoff_ok ( cfg_turnoff_ok ), // O .cfg_completer_id ( cfg_completer_id ) // I [15:0] ); endmodule // pcie_app

//////////////////////////////////////////////////////////////////////////////// // Original Author: Schuyler Eldridge // Contact Point: Schuyler Eldridge ([email protected]) // div_pipelined.v // Created: 4.3.2012 // Modified: 4.5.2012 // // Testbench for div_pipelined.v // // Copyright (C) 2012 Schuyler Eldridge, Boston University // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. //////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module t_div_pipelined(); reg clk, start, reset_n; reg [7:0] dividend, divisor; wire data_valid, div_by_zero; wire [7:0] quotient, quotient_correct; parameter BITS = 8; div_pipelined #( .BITS(BITS) ) div_pipelined ( .clk(clk), .reset_n(reset_n), .dividend(dividend), .divisor(divisor), .quotient(quotient), .div_by_zero(div_by_zero), // .quotient_correct(quotient_correct), .start(start), .data_valid(data_valid) ); initial begin #10 reset_n = 0; #50 reset_n = 1; #1 clk = 0; dividend = -1; divisor = 127; #1000 $finish; end // always // #20 dividend = dividend + 1; always begin #10 divisor = divisor - 1; start = 1; #10 start = 0; end always #5 clk = ~clk; endmodule

// Taken from http://www.europa.com/~celiac/fsm_samp.html // These are the symbolic names for states parameter [1:0] //synopsys enum state_info S0 = 2'h0, S1 = 2'h1, S2 = 2'h2, S3 = 2'h3; // These are the current state and next state variables reg [1:0] /* synopsys enum state_info */ state; reg [1:0] /* synopsys enum state_info */ next_state; // synopsys state_vector state always @ (state or y or x) begin next_state = state; case (state) // synopsys full_case parallel_case S0: begin if (x) begin next_state = S1; end else begin next_state = S2; end end S1: begin if (y) begin next_state = S2; end else begin next_state = S0; end end S2: begin if (x & y) begin next_state = S3; end else begin next_state = S0; end end S3: begin next_state = S0; end endcase end always @ (posedge clk or posedge reset) begin if (reset) begin state <= S0; end else begin state <= next_state; end end

/*------------------------------------------------------------------------------ * This code was generated by Spiral Multiplier Block Generator, www.spiral.net * Copyright (c) 2006, Carnegie Mellon University * All rights reserved. * The code is distributed under a BSD style license * (see http://www.opensource.org/licenses/bsd-license.php) *------------------------------------------------------------------------------ */ /* ./multBlockGen.pl 16657 -fractionalBits 0*/ module multiplier_block ( i_data0, o_data0 ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; //Multipliers: wire [31:0] w1, w16384, w16385, w256, w16641, w16, w16657; assign w1 = i_data0; assign w16 = w1 << 4; assign w16384 = w1 << 14; assign w16385 = w1 + w16384; assign w16641 = w16385 + w256; assign w16657 = w16641 + w16; assign w256 = w1 << 8; assign o_data0 = w16657; //multiplier_block area estimate = 4770.05771526471; endmodule //multiplier_block module surround_with_regs( i_data0, o_data0, clk ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; reg [31:0] o_data0; input clk; reg [31:0] i_data0_reg; wire [30:0] o_data0_from_mult; always @(posedge clk) begin i_data0_reg <= i_data0; o_data0 <= o_data0_from_mult; end multiplier_block mult_blk( .i_data0(i_data0_reg), .o_data0(o_data0_from_mult) ); endmodule

// file: main_pll.v // // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //---------------------------------------------------------------------------- // User entered comments //---------------------------------------------------------------------------- // None // //---------------------------------------------------------------------------- // "Output Output Phase Duty Pk-to-Pk Phase" // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" //---------------------------------------------------------------------------- // CLK_OUT1____75.000______0.000______50.0______466.667_____50.000 // //---------------------------------------------------------------------------- // "Input Clock Freq (MHz) Input Jitter (UI)" //---------------------------------------------------------------------------- // __primary_________100.000____________0.010 `timescale 1ps/1ps (* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) module main_pll (// Clock in ports input CLK_IN1, // Clock out ports output CLK_OUT1 ); // Input buffering //------------------------------------ IBUFG clkin1_buf (.O (clkin1), .I (CLK_IN1)); // Clocking primitive //------------------------------------ // Instantiation of the DCM primitive // * Unused inputs are tied off // * Unused outputs are labeled unused wire psdone_unused; wire locked_int; wire [7:0] status_int; wire clkfb; wire clk0; wire clkfx; DCM_SP #(.CLKDV_DIVIDE (2.000), .CLKFX_DIVIDE (10), .CLKFX_MULTIPLY (15), .CLKIN_DIVIDE_BY_2 ("FALSE"), .CLKIN_PERIOD (10.0), .CLKOUT_PHASE_SHIFT ("NONE"), .CLK_FEEDBACK ("NONE"), .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), .PHASE_SHIFT (0), .STARTUP_WAIT ("FALSE")) dcm_sp_inst // Input clock (.CLKIN (clkin1), .CLKFB (clkfb), // Output clocks .CLK0 (clk0), .CLK90 (), .CLK180 (), .CLK270 (), .CLK2X (), .CLK2X180 (), .CLKFX (clkfx), .CLKFX180 (), .CLKDV (), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (locked_int), .STATUS (status_int), .RST (1'b0), // Unused pin- tie low .DSSEN (1'b0)); // Output buffering //----------------------------------- // no phase alignment active, connect to ground assign clkfb = 1'b0; BUFG clkout1_buf (.O (CLK_OUT1), .I (clkfx)); endmodule

// (C) 2001-2014 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/14.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2014/10/06 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 || (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) | out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_mux.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v1_9_arb_mux # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_VECT_INDX = 11, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_VECT_INDX = 31, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs parameter nCS_PER_RANK = 1, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nSLOTS = 2, parameter nWR = 6, // Write recovery (CKs) parameter RANKS = 1, parameter RANK_VECT_INDX = 15, parameter RANK_WIDTH = 2, parameter ROW_VECT_INDX = 63, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010 ) (/*AUTOARG*/ // Outputs output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v output col_periodic_rd, // From arb_select0 of arb_select.v output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v output col_rmw, // From arb_select0 of arb_select.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v output col_size, // From arb_select0 of arb_select.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_pre, output sent_col, // From arb_row_col0 of arb_row_col.v output sent_col_r, // From arb_row_col0 of arb_row_col.v output sent_row, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_col, output rnk_config_strobe, output insert_maint_r1, output rnk_config_kill_rts_col, // Inputs input clk, input rst, input init_calib_complete, input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v input insert_maint_r, // To arb_row_col0 of arb_row_col.v input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v input maint_zq_r, // To arb_select0 of arb_select.v input maint_sre_r, // To arb_select0 of arb_select.v input maint_srx_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v input [7:0] slot_0_present, // To arb_select0 of arb_select.v input [7:0] slot_1_present // To arb_select0 of arb_select.v ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire cs_en0; // From arb_row_col0 of arb_row_col.v wire cs_en1; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v wire send_cmd1_col; wire send_cmd2_row; wire send_cmd2_col; wire send_cmd2_pre; wire send_cmd3_col; wire [5:0] col_channel_offset; // End of automatics wire sent_col_i; assign sent_col = sent_col_i; mig_7series_v1_9_arb_row_col # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .CWL (CWL), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nRAS (nRAS), .nRCD (nRCD), .nWR (nWR)) arb_row_col0 (/*AUTOINST*/ // Outputs .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), .sent_row (sent_row), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col_i), .sent_col_r (sent_col_r), .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), .send_cmd0_row (send_cmd0_row), .send_cmd0_col (send_cmd0_col), .send_cmd1_row (send_cmd1_row), .send_cmd1_col (send_cmd1_col), .send_cmd2_row (send_cmd2_row), .send_cmd2_col (send_cmd2_col), .send_cmd2_pre (send_cmd2_pre), .send_cmd3_col (send_cmd3_col), .col_channel_offset (col_channel_offset), .cs_en0 (cs_en0), .cs_en1 (cs_en1), .cs_en2 (cs_en2), .cs_en3 (cs_en3), .insert_maint_r1 (insert_maint_r1), // Inputs .clk (clk), .rst (rst), .rts_row (rts_row[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .rts_col (rts_col[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0])); mig_7series_v1_9_arb_select # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .CKE_ODT_AUX (CKE_ODT_AUX), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nSLOTS (nSLOTS), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_select0 (/*AUTOINST*/ // Outputs .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_size (col_size), .col_row (col_row[ROW_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .mc_cas_slot (mc_cas_slot), .col_channel_offset (col_channel_offset), .rnk_config (rnk_config), // Inputs .clk (clk), .rst (rst), .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .insert_maint_r1 (insert_maint_r1), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .col_addr (col_addr[ROW_VECT_INDX:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), .send_cmd0_row (send_cmd0_row), .send_cmd0_col (send_cmd0_col), .send_cmd1_row (send_cmd1_row), .send_cmd1_col (send_cmd1_col), .send_cmd2_row (send_cmd2_row), .send_cmd2_col (send_cmd2_col), .send_cmd2_pre (send_cmd2_pre), .send_cmd3_col (send_cmd3_col), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col), .cs_en0 (cs_en0), .cs_en1 (cs_en1), .cs_en2 (cs_en2), .cs_en3 (cs_en3), .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); endmodule

// ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH // DAMAGE. // ---------------------------------------------------------------------- // // Filename: tx_engine_classic.v // Version: 1.0 // Verilog Standard: Verilog-2001 // Description: The TX Engine takes unformatted request and completions, // formats these packets into "TLP's" or Transaction Layer Packets and abitrates // their sending over the PCIe bus. These packets must meet max-request, // max-payload, and payload termination requirements (see Read Completion // Boundary). The TX Engine does not check these requirements during operation, // but may do so during simulation. // // Valid packets are transmitted over the shared PCIe bus as determined // by the arbiter. // // This Engine is capable of operating at "line rate". // Author: Dustin Richmond (@darichmond) //----------------------------------------------------------------------------- `include "trellis.vh" `include "tlp.vh" module tx_engine_classic #(parameter C_PCI_DATA_WIDTH = 128, parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_OUTPUT = 1, parameter C_MAX_PAYLOAD_DWORDS = 256, parameter C_VENDOR = "ALTERA") (// Interface: Clocks input CLK, // Interface: Resets input RST_BUS, // Replacement for generic RST_IN input RST_LOGIC, // Addition for RIFFA_RST output DONE_TXC_RST, output DONE_TXR_RST, // Interface: Configuration input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID, // Interface: TX Classic input TX_TLP_READY, output [C_PCI_DATA_WIDTH-1:0] TX_TLP, output TX_TLP_VALID, output TX_TLP_START_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET, output TX_TLP_END_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET, // Interface: TXC Engine input TXC_DATA_VALID, input [C_PCI_DATA_WIDTH-1:0] TXC_DATA, input TXC_DATA_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET, input TXC_DATA_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET, output TXC_DATA_READY, input TXC_META_VALID, input [`SIG_FBE_W-1:0] TXC_META_FDWBE, input [`SIG_LBE_W-1:0] TXC_META_LDWBE, input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR, input [`SIG_TYPE_W-1:0] TXC_META_TYPE, input [`SIG_LEN_W-1:0] TXC_META_LENGTH, input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT, input [`SIG_TAG_W-1:0] TXC_META_TAG, input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID, input [`SIG_TC_W-1:0] TXC_META_TC, input [`SIG_ATTR_W-1:0] TXC_META_ATTR, input TXC_META_EP, output TXC_META_READY, output TXC_SENT, // Interface: TXR Engine input TXR_DATA_VALID, input [C_PCI_DATA_WIDTH-1:0] TXR_DATA, input TXR_DATA_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET, input TXR_DATA_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET, output TXR_DATA_READY, input TXR_META_VALID, input [`SIG_FBE_W-1:0] TXR_META_FDWBE, input [`SIG_LBE_W-1:0] TXR_META_LDWBE, input [`SIG_ADDR_W-1:0] TXR_META_ADDR, input [`SIG_LEN_W-1:0] TXR_META_LENGTH, input [`SIG_TAG_W-1:0] TXR_META_TAG, input [`SIG_TC_W-1:0] TXR_META_TC, input [`SIG_ATTR_W-1:0] TXR_META_ATTR, input [`SIG_TYPE_W-1:0] TXR_META_TYPE, input TXR_META_EP, output TXR_META_READY, output TXR_SENT); localparam C_MUX_TYPE = "SHIFT"; localparam C_DEPTH_PACKETS = 10; localparam C_RST_COUNT = 10; /*AUTOWIRE*/ /*AUTOINPUT*/ wire [C_PCI_DATA_WIDTH-1:0] _TXC_DATA; wire [C_PCI_DATA_WIDTH-1:0] _TXR_DATA; wire [C_PCI_DATA_WIDTH-1:0] wTxcTlp; wire wTxcTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpEndOffset; wire wTxcTlpReady; wire wTxcTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpStartOffset; wire wTxcTlpValid; wire [C_PCI_DATA_WIDTH-1:0] wTxrTlp; wire wTxrTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpEndOffset; wire wTxrTlpReady; wire wTxrTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpStartOffset; wire wTxrTlpValid; wire [C_PCI_DATA_WIDTH-1:0] wTxTlp; wire wTxTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpEndOffset; wire wTxTlpReady; wire wTxTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpStartOffset; wire wTxTlpValid; wire wDoneTxcEngRst; wire wDoneTxrEngRst; wire wDoneRst; wire wRstWaiting; wire wRstRc; wire wRstEng; wire [C_RST_COUNT:0] wShiftRst; reg rTxValid; reg [`TLP_TYPE_W-1:0] rTxType; reg rTxEndFlag; reg rTxrSent; reg rTxcSent; assign DONE_TXC_RST = wDoneRst & wDoneTxcEngRst; assign DONE_TXR_RST = wDoneRst & wDoneTxrEngRst; assign TXC_SENT = rTxcSent; assign TXR_SENT = rTxrSent; assign wRstEng = wShiftRst[C_RST_COUNT-3]; assign wDoneEngRst = ~wShiftRst[C_RST_COUNT]; always @(posedge CLK) begin if(TX_TLP_START_FLAG) begin rTxType <= TX_TLP[`TLP_TYPE_R]; end rTxEndFlag <= TX_TLP_END_FLAG; rTxValid <= TX_TLP_VALID & TX_TLP_READY; rTxcSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_CPL); rTxrSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_REQ); end generate if(C_VENDOR == "XILINX") begin : xilinx_data if(C_PCI_DATA_WIDTH == 128) begin : x_be_swap128 assign _TXC_DATA = {TXC_DATA[103:96], TXC_DATA[111:104], TXC_DATA[119:112], TXC_DATA[127:120], TXC_DATA[71:64], TXC_DATA[79:72], TXC_DATA[87:80], TXC_DATA[95:88], TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56], TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]}; assign _TXR_DATA = {TXR_DATA[103:96], TXR_DATA[111:104], TXR_DATA[119:112], TXR_DATA[127:120], TXR_DATA[71:64], TXR_DATA[79:72], TXR_DATA[87:80], TXR_DATA[95:88], TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56], TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]}; end else if(C_PCI_DATA_WIDTH == 64) begin: x_be_swap64 assign _TXC_DATA = {TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56], TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]}; assign _TXR_DATA = {TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56], TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]}; end else if(C_PCI_DATA_WIDTH == 32) begin: x_be_swap32 assign _TXC_DATA = {TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]}; assign _TXR_DATA = {TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]}; end end else begin : altera_data assign _TXC_DATA = TXC_DATA; assign _TXR_DATA = TXR_DATA; end endgenerate txc_engine_classic #(.C_PIPELINE_OUTPUT (0), /*AUTOINSTPARAM*/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_INPUT (C_PIPELINE_INPUT), .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS), .C_DEPTH_PACKETS (C_DEPTH_PACKETS), .C_VENDOR (C_VENDOR)) txc_engine_inst (// Outputs .TXC_TLP (wTxcTlp[C_PCI_DATA_WIDTH-1:0] ), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_START_OFFSET (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXC_TLP_END_OFFSET (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .DONE_TXC_RST (wDoneTxcEngRst), // Inputs .TXC_TLP_READY (wTxcTlpReady), .TXC_DATA (_TXC_DATA[C_PCI_DATA_WIDTH-1:0]), .RST_IN (wRstEng), /*AUTOINST*/ // Outputs .TXC_DATA_READY (TXC_DATA_READY), .TXC_META_READY (TXC_META_READY), // Inputs .CLK (CLK), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA_START_FLAG (TXC_DATA_START_FLAG), .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (TXC_DATA_END_FLAG), .TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (TXC_META_VALID), .TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]), .TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]), .TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]), .TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]), .TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]), .TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]), .TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]), .TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]), .TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]), .TXC_META_EP (TXC_META_EP)); txr_engine_classic #(.C_PIPELINE_OUTPUT (0), /*AUTOINSTPARAM*/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_INPUT (C_PIPELINE_INPUT), .C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS), .C_DEPTH_PACKETS (C_DEPTH_PACKETS), .C_VENDOR (C_VENDOR)) txr_engine_inst (// Outputs .TXR_TLP (wTxrTlp[C_PCI_DATA_WIDTH-1:0]), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_START_OFFSET (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), .TXR_TLP_END_OFFSET (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA (_TXR_DATA[C_PCI_DATA_WIDTH-1:0]), .DONE_TXR_RST (wDoneTxrEngRst), // Inputs .TXR_TLP_READY (wTxrTlpReady), .RST_IN (wRstEng), /*AUTOINST*/ // Outputs .TXR_DATA_READY (TXR_DATA_READY), .TXR_META_READY (TXR_META_READY), // Inputs .CLK (CLK), .CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]), .TXR_DATA_VALID (TXR_DATA_VALID), .TXR_DATA_START_FLAG (TXR_DATA_START_FLAG), .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (TXR_DATA_END_FLAG), .TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (TXR_META_VALID), .TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]), .TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]), .TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]), .TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]), .TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]), .TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]), .TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]), .TXR_META_EP (TXR_META_EP)); tx_mux #(.C_PIPELINE_INPUT (0), /*AUTOINSTPARAM*/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT), .C_MUX_TYPE (C_MUX_TYPE), .C_VENDOR (C_VENDOR)) tx_mux_inst (// Inputs .TXC_TLP (wTxcTlp[C_PCI_DATA_WIDTH-1:0]), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_START_OFFSET (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXC_TLP_END_OFFSET (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_TLP (wTxrTlp[C_PCI_DATA_WIDTH-1:0]), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_START_OFFSET (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), .TXR_TLP_END_OFFSET (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RST_IN (wRstEng), // Outputs .TXC_TLP_READY (wTxcTlpReady), .TXR_TLP_READY (wTxrTlpReady), .TX_TLP (wTxTlp[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (wTxTlpValid), .TX_TLP_START_FLAG (wTxTlpStartFlag), .TX_TLP_START_OFFSET (wTxTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (wTxTlpEndFlag), .TX_TLP_END_OFFSET (wTxTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_READY (wTxTlpReady), /*AUTOINST*/ // Inputs .CLK (CLK)); shiftreg #(// Parameters .C_DEPTH (C_RST_COUNT), .C_WIDTH (1), .C_VALUE (1) /*AUTOINSTPARAM*/) rst_shiftreg (// Outputs .RD_DATA (wShiftRst), // Inputs .RST_IN (RST_BUS), .WR_DATA (wRstRc), /*AUTOINST*/ // Inputs .CLK (CLK)); reset_controller #(// Parameters .C_RST_COUNT (C_RST_COUNT) /*AUTOINSTPARAM*/) rc_inst (// Outputs .DONE_RST (wDoneRst), .WAITING_RESET (wRstWaiting), .RST_OUT (wRstRc), // Inputs .RST_IN (RST_BUS), .SIGNAL_RST (RST_LOGIC), .WAIT_RST (TX_TLP_VALID), .NEXT_CYC_RST (TX_TLP_END_FLAG & TX_TLP_READY), /*AUTOINST*/ // Inputs .CLK (CLK)); pipeline #(// Parameters .C_DEPTH (1), .C_WIDTH (C_PCI_DATA_WIDTH + 2*(1 + clog2s(C_PCI_DATA_WIDTH/32))), .C_USE_MEMORY (0) /*AUTOINSTPARAM*/) output_reg_inst (// Outputs .WR_DATA_READY (wTxTlpReady), .RD_DATA ({TX_TLP, TX_TLP_START_FLAG, TX_TLP_START_OFFSET, TX_TLP_END_FLAG, TX_TLP_END_OFFSET}), .RD_DATA_VALID (TX_TLP_VALID), // Inputs .RST_IN (wRstRc), .WR_DATA ({wTxTlp, wTxTlpStartFlag, wTxTlpStartOffset, wTxTlpEndFlag, wTxTlpEndOffset}), .WR_DATA_VALID (wTxTlpValid & ~wRstWaiting), .RD_DATA_READY (TX_TLP_READY), /*AUTOINST*/ // Inputs .CLK (CLK)); // Put output pipeline stage here, OR, at TX Engine outputs endmodule // Local Variables: // verilog-library-directories:("." "../../common/") // End: /* Filename: tx_mux.v Version: 1.0 Verilog Standard: Verilog-2001 Description: The tx_mux arbitrates access to the PCI TX interface between the the Request and Completion engines. The top level tx_mux module instantiates two sub-modules (also declared in this file): tx_arbiter and tx_phi. The arbiter choses the next packet that will be granted the TX interface, based on the priorities given to it. Each priority is the count of how many successive, back-to-back packets can be sent by either the TXC or TXR interface before granting time to the other engine. The mux is a simple multiplexer that uses the select signals from the arbiter. Notes: Any modifications to this file should meet the conditions set forth in the "Trellis Style Guide" - The pipeline stage at the start of the mux means that ready stays high for both TXC and TXR. This the behavior we want? Author: Dustin Richmond (@darichmond) Co-Authors: */ `timescale 1ns/1ns `include "trellis.vh" module tx_mux #(parameter C_PCI_DATA_WIDTH = 128, parameter C_PIPELINE_INPUT = 1, parameter C_PIPELINE_OUTPUT = 1, parameter C_MUX_TYPE = "SHIFT", parameter C_VENDOR = "ALTERA") (// Interface: Clocks input CLK, // Interface: Resets input RST_IN, // Interface: TXC input [C_PCI_DATA_WIDTH-1:0] TXC_TLP, output TXC_TLP_READY, input TXC_TLP_VALID, input TXC_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET, input TXC_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET, // Interface: TXR input [C_PCI_DATA_WIDTH-1:0] TXR_TLP, input TXR_TLP_VALID, input TXR_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET, input TXR_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET, output TXR_TLP_READY, // Interface: TX Classic input TX_TLP_READY, output [C_PCI_DATA_WIDTH-1:0] TX_TLP, output TX_TLP_VALID, output TX_TLP_START_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET, output TX_TLP_END_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET); localparam C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1)); localparam C_TXC_PRIORITY = 1; localparam C_TXR_PRIORITY = 2; /*AUTOWIRE*/ /*AUTOINPUT*/ /*AUTOOUTPUT*/ // Input Pipeline Stage to Mux wire [C_PCI_DATA_WIDTH-1:0] wTxcTlp; wire wTxcTlpReady; wire wTxcTlpValid; wire wTxcTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpStartOffset; wire wTxcTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpEndOffset; wire [C_PCI_DATA_WIDTH-1:0] wTxrTlp; wire wTxrTlpReady; wire wTxrTlpValid; wire wTxrTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpStartOffset; wire wTxrTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpEndOffset; // Output of Mux to wire [C_PCI_DATA_WIDTH-1:0] wTxTlp; wire wTxTlpReady; wire wTxTlpValid; wire wTxTlpStartFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpStartOffset; wire wTxTlpEndFlag; wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpEndOffset; pipeline #(// Parameters .C_DEPTH (C_PIPELINE_INPUT?1:0), .C_USE_MEMORY (0), /*AUTOINSTPARAM*/ // Parameters .C_WIDTH (C_WIDTH)) txr_capture_inst (// Outputs .WR_DATA_READY (TXR_TLP_READY), .RD_DATA ({wTxrTlp, wTxrTlpStartFlag, wTxrTlpStartOffset, wTxrTlpEndFlag, wTxrTlpEndOffset}), .RD_DATA_VALID (wTxrTlpValid), // Inputs .WR_DATA ({TXR_TLP, TXR_TLP_START_FLAG, TXR_TLP_START_OFFSET, TXR_TLP_END_FLAG, TXR_TLP_END_OFFSET}), .WR_DATA_VALID (TXR_TLP_VALID), .RD_DATA_READY (wTxrTlpReady), /*AUTOINST*/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); pipeline #(// Parameters .C_DEPTH (C_PIPELINE_INPUT?1:0), .C_USE_MEMORY (0), /*AUTOINSTPARAM*/ // Parameters .C_WIDTH (C_WIDTH)) txc_capture_inst (// Outputs .WR_DATA_READY (TXC_TLP_READY), .RD_DATA ({wTxcTlp, wTxcTlpStartFlag, wTxcTlpStartOffset, wTxcTlpEndFlag, wTxcTlpEndOffset}), .RD_DATA_VALID (wTxcTlpValid), // Inputs .WR_DATA ({TXC_TLP, TXC_TLP_START_FLAG, TXC_TLP_START_OFFSET, TXC_TLP_END_FLAG, TXC_TLP_END_OFFSET}), .WR_DATA_VALID (TXC_TLP_VALID), .RD_DATA_READY (wTxcTlpReady), /*AUTOINST*/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); tx_arbiter #(/*AUTOINSTPARAM*/ // Parameters .C_TXC_PRIORITY (C_TXC_PRIORITY), .C_TXR_PRIORITY (C_TXR_PRIORITY)) tx_arbiter_inst (// Outputs .TXR_TLP_READY (wTxrTlpReady), .TXC_TLP_READY (wTxcTlpReady), // Inputs .TX_TLP_READY (wTxTlpReady), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), /*AUTOINST*/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); // MUX Selector tx_phi #(/*AUTOINSTPARAM*/ // Parameters .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_MUX_TYPE (C_MUX_TYPE), .C_WIDTH (C_WIDTH)) tx_phi_inst (// Outputs .TXC_TLP_READY (wTxcTlpReady), .TXR_TLP_READY (wTxrTlpReady), .TX_TLP (wTxTlp), .TX_TLP_VALID (wTxTlpValid), .TX_TLP_START_FLAG (wTxTlpStartFlag), .TX_TLP_START_OFFSET (wTxTlpStartOffset), .TX_TLP_END_FLAG (wTxTlpEndFlag), .TX_TLP_END_OFFSET (wTxTlpEndOffset), // Inputs .TXC_TLP (wTxcTlp), .TXC_TLP_VALID (wTxcTlpValid), .TXC_TLP_START_FLAG (wTxcTlpStartFlag), .TXC_TLP_START_OFFSET (wTxcTlpStartOffset), .TXC_TLP_END_FLAG (wTxcTlpEndFlag), .TXC_TLP_END_OFFSET (wTxcTlpEndOffset), .TXR_TLP (wTxrTlp), .TXR_TLP_VALID (wTxrTlpValid), .TXR_TLP_START_FLAG (wTxrTlpStartFlag), .TXR_TLP_START_OFFSET (wTxrTlpStartOffset), .TXR_TLP_END_FLAG (wTxrTlpEndFlag), .TXR_TLP_END_OFFSET (wTxrTlpEndOffset), /*AUTOINST*/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); pipeline #(// Parameters .C_DEPTH (C_PIPELINE_OUTPUT?1:0), .C_USE_MEMORY (0), /*AUTOINSTPARAM*/ // Parameters .C_WIDTH (C_WIDTH)) tx_output_inst (// Outputs .WR_DATA_READY (wTxTlpReady), .RD_DATA ({TX_TLP, TX_TLP_START_FLAG, TX_TLP_START_OFFSET, TX_TLP_END_FLAG, TX_TLP_END_OFFSET}), .RD_DATA_VALID (TX_TLP_VALID), // Inputs .WR_DATA ({wTxTlp, wTxTlpStartFlag, wTxTlpStartOffset, wTxTlpEndFlag, wTxTlpEndOffset}), .WR_DATA_VALID (wTxTlpValid), .RD_DATA_READY (TX_TLP_READY), /*AUTOINST*/ // Inputs .CLK (CLK), .RST_IN (RST_IN)); endmodule // Local Variables: // verilog-library-directories:("." "../../../common/") // End: /* Description: The tx_arbiter arbitrates between TXC and TXR channels. The C_TX*_PRIORITY values are counters are the maximum number of uninterrupted TXR or TXC packets that can be transmitted without transmitting a packet of the other type. Notes: Any modifications to this file should meet the conditions set forth in the "Trellis Style Guide" Author: Dustin Richmond (@darichmond) Co-Authors: */ module tx_arbiter #(parameter C_TXC_PRIORITY = 1, parameter C_TXR_PRIORITY = 1) ( // Interface: Clocks input CLK, // Interface: Resets input RST_IN, // Interface: TX Classic Flow Control input TX_TLP_READY, // Interface: TXR Flow Control output TXR_TLP_READY, input TXR_TLP_VALID, input TXR_TLP_START_FLAG, input TXR_TLP_END_FLAG, // Interface: TXC Flow Control output TXC_TLP_READY, input TXC_TLP_VALID, input TXC_TLP_START_FLAG, input TXC_TLP_END_FLAG); localparam S_TXARB_IDLE = 0; // STATE: Idle state for the arbiter (not currently used) localparam S_TXARB_TRANSMIT_TXR = 1; // STATE: Transmit TXR packets until the priority counter is reached localparam S_TXARB_TRANSMIT_TXC = 2; // STATE: Transmit TXC packets until the priority counter is reached // S_TXARB_PRIORITY is a special state that encodes the type (TXR/TXC) with // higher priority so that the state machine (below) is general. localparam S_TXARB_PRIORITY = (S_TXARB_TRANSMIT_TXR >= S_TXARB_TRANSMIT_TXC)? S_TXARB_TRANSMIT_TXR: S_TXARB_TRANSMIT_TXC; localparam C_NUM_STATES = S_TXARB_TRANSMIT_TXC; wire wTxrGrant; wire wTxrReq; wire wTxrDone; wire wTxcGrant; wire wTxcReq; wire wTxcDone; reg [clog2s(C_NUM_STATES):0] rArbState,_rArbState; reg rTxrLast,_rTxrLast; // Reset on RST_IN or TXC_TLP_READY reg rTxcLast,_rTxcLast; // Reset on RST_IN or TXR_TLP_READY reg rTxrActive,_rTxrActive; // Reset on RST_IN or TXC_TLP_READY reg rTxcActive,_rTxcActive; // Reset on RST_IN or TXR_TLP_READY reg [clog2s(C_TXC_PRIORITY)-1:0] rTxcCounter,_rTxcCounter; // Reset on RST_IN or TXC_TLP_READY reg [clog2s(C_TXR_PRIORITY)-1:0] rTxrCounter,_rTxrCounter; // Reset on RST_IN or TXR_TLP_READY assign TXR_TLP_READY = wTxrGrant & TX_TLP_READY; // TODO: Not great assign wTxrReq = TXR_TLP_START_FLAG & TXR_TLP_VALID; assign wTxrDone = TXR_TLP_END_FLAG & TXR_TLP_READY; assign wTxrGrant = (rArbState == S_TXARB_TRANSMIT_TXR); assign TXC_TLP_READY = wTxcGrant & TX_TLP_READY; // TODO: Not great assign wTxcReq = TXC_TLP_START_FLAG & TXC_TLP_VALID; assign wTxcDone = TXC_TLP_END_FLAG & TXC_TLP_READY; assign wTxcGrant = (rArbState == S_TXARB_TRANSMIT_TXC); always @(*) begin // Defaults _rTxcCounter = rTxcCounter; _rTxcActive = rTxcActive; _rTxcLast = rTxcLast; if(wTxrGrant) begin _rTxcCounter = 0; end else if(wTxcReq & wTxcGrant & ~rTxcLast) begin _rTxcCounter = _rTxcCounter + 1; end if(wTxcReq & wTxcGrant) begin _rTxcActive = 1; end else if(wTxcDone) begin _rTxcActive = 0; end if(wTxrGrant | RST_IN) begin _rTxcLast = 0; end else if(wTxcReq & wTxcGrant) begin _rTxcLast = (rTxcCounter == (C_TXC_PRIORITY - 1)); end end // always @ (*) always @(posedge CLK) begin if(RST_IN) begin rTxcCounter <= #1 0; rTxcActive <= #1 0; rTxcLast <= #1 0; end else begin rTxcCounter <= #1 _rTxcCounter; rTxcActive <= #1 _rTxcActive; rTxcLast <= #1 _rTxcLast; end end always @(*) begin // Defaults _rTxrCounter = rTxrCounter; _rTxrActive = rTxrActive; _rTxrLast = rTxrLast; if(wTxcGrant) begin _rTxrCounter = 0; end else if(wTxrReq & wTxrGrant & ~rTxrLast) begin _rTxrCounter = _rTxrCounter + 1; end if(wTxrReq & wTxrGrant) begin _rTxrActive = 1; end else if(wTxrDone) begin _rTxrActive = 0; end if(wTxcGrant | RST_IN) begin _rTxrLast = 0; end else if(wTxrReq & wTxrGrant) begin /* verilator lint_off WIDTH */ _rTxrLast = (rTxrCounter == (C_TXR_PRIORITY - 1)); /* verilator lint_on WIDTH */ end end always @(posedge CLK) begin if(RST_IN) begin rTxrCounter <= #1 0; rTxrActive <= #1 0; rTxrLast <= #1 0; end else begin rTxrCounter <= #1 _rTxrCounter; rTxrActive <= #1 _rTxrActive; rTxrLast <= #1 _rTxrLast; end end // User encoded state machine always @(*) begin _rArbState = rArbState; case(rArbState) S_TXARB_TRANSMIT_TXR: begin if((rTxrLast & wTxrDone & wTxcReq) | (~rTxrActive & ~wTxrReq & wTxcReq)) begin _rArbState = S_TXARB_TRANSMIT_TXC; end end S_TXARB_TRANSMIT_TXC: begin if((rTxcLast & wTxcDone & wTxrReq) | (~rTxcActive & ~wTxcReq & wTxrReq)) begin _rArbState = S_TXARB_TRANSMIT_TXR; end end default: begin // Error! This should never happen... end endcase end // always @ begin always @(posedge CLK) begin if(RST_IN) begin rArbState <= #1 S_TXARB_PRIORITY; end else begin rArbState <= #1 _rArbState; end end endmodule /* Description: The tx_phi wraps a mux instantiation for the tx_mux. It is controlled by the tx_arbiter Notes: Any modifications to this file should meet the conditions set forth in the "Trellis Style Guide" Author: Dustin Richmond (@darichmond) Co-Authors: */ module tx_phi #(parameter C_PCI_DATA_WIDTH = 10'd128, parameter C_MUX_TYPE = "SHIFT", parameter C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1))) (// Interface: Clocks input CLK, // Interface: Resets input RST_IN, // Interface: TXC Flow Control input TXC_TLP_READY, // Interface: TXR Flow Control input TXR_TLP_READY, // Interface: TXC input [C_PCI_DATA_WIDTH-1:0] TXC_TLP, input TXC_TLP_VALID, input TXC_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET, input TXC_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET, // Interface: TXR input [C_PCI_DATA_WIDTH-1:0] TXR_TLP, input TXR_TLP_VALID, input TXR_TLP_START_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET, input TXR_TLP_END_FLAG, input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET, // Interface: TX Classic output [C_PCI_DATA_WIDTH-1:0] TX_TLP, output TX_TLP_VALID, output TX_TLP_START_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET, output TX_TLP_END_FLAG, output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET); // Width = 2 * (DATA WIDTH + VALID + START FLAG + START OFFSET + END FLAG + END OFFSET) localparam C_MUX_WIDTH = C_PCI_DATA_WIDTH + 3 + 2*clog2s(C_PCI_DATA_WIDTH/32); wire [2*C_MUX_WIDTH-1:0] wAggregate; assign wAggregate = {{TXR_TLP,TXR_TLP_VALID,TXR_TLP_START_FLAG, TXR_TLP_START_OFFSET,TXR_TLP_END_FLAG,TXR_TLP_END_OFFSET}, {TXC_TLP,TXC_TLP_VALID,TXC_TLP_START_FLAG, TXC_TLP_START_OFFSET,TXC_TLP_END_FLAG,TXC_TLP_END_OFFSET}}; mux #(// Parameters .C_NUM_INPUTS (2), .C_CLOG_NUM_INPUTS (1), .C_WIDTH (C_MUX_WIDTH), .C_MUX_TYPE ("SELECT") /*AUTOINSTPARAM*/) mux_inst (// Outputs .MUX_OUTPUT ({TX_TLP,TX_TLP_VALID,TX_TLP_START_FLAG, TX_TLP_START_OFFSET,TX_TLP_END_FLAG, TX_TLP_END_OFFSET}), // Inputs .MUX_INPUTS (wAggregate), .MUX_SELECT (TXR_TLP_READY) /*AUTOINST*/); endmodule

/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_8_b2s_b_channel.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_8_b2s_b_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk, input wire reset, // AXI signals output wire [C_ID_WIDTH-1:0] s_bid, output wire [1:0] s_bresp, output wire s_bvalid, input wire s_bready, input wire [1:0] m_bresp, input wire m_bvalid, output wire m_bready, // Signals to/from the axi_protocol_converter_v2_1_8_b2s_aw_channel modules input wire b_push, input wire [C_ID_WIDTH-1:0] b_awid, input wire [7:0] b_awlen, input wire b_resp_rdy, output wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // AXI protocol responses: localparam [1:0] LP_RESP_OKAY = 2'b00; localparam [1:0] LP_RESP_EXOKAY = 2'b01; localparam [1:0] LP_RESP_SLVERROR = 2'b10; localparam [1:0] LP_RESP_DECERR = 2'b11; // FIFO settings localparam P_WIDTH = C_ID_WIDTH + 8; localparam P_DEPTH = 4; localparam P_AWIDTH = 2; localparam P_RWIDTH = 2; localparam P_RDEPTH = 4; localparam P_RAWIDTH = 2; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg bvalid_i; wire [C_ID_WIDTH-1:0] bid_i; wire shandshake; reg shandshake_r; wire mhandshake; reg mhandshake_r; wire b_empty; wire bresp_full; wire bresp_empty; wire [7:0] b_awlen_i; reg [7:0] bresp_cnt; reg [1:0] s_bresp_acc; wire [1:0] s_bresp_acc_r; reg [1:0] s_bresp_i; wire need_to_update_bresp; wire bresp_push; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // assign AXI outputs assign s_bid = bid_i; assign s_bresp = s_bresp_acc_r; assign s_bvalid = bvalid_i; assign shandshake = s_bvalid & s_bready; assign mhandshake = m_bvalid & m_bready; always @(posedge clk) begin if (reset | shandshake) begin bvalid_i <= 1'b0; end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin bvalid_i <= 1'b1; end end always @(posedge clk) begin shandshake_r <= shandshake; mhandshake_r <= mhandshake; end axi_protocol_converter_v2_1_8_b2s_simple_fifo #( .C_WIDTH (P_WIDTH), .C_AWIDTH (P_AWIDTH), .C_DEPTH (P_DEPTH) ) bid_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( b_push ) , .rd_en ( shandshake_r ) , .din ( {b_awid, b_awlen} ) , .dout ( {bid_i, b_awlen_i}) , .a_full ( ) , .full ( b_full ) , .a_empty ( ) , .empty ( b_empty ) ); assign m_bready = ~mhandshake_r & bresp_empty; ///////////////////////////////////////////////////////////////////////////// // Update if more critical. assign need_to_update_bresp = ( m_bresp > s_bresp_acc ); // Select accumultated or direct depending on setting. always @( * ) begin if ( need_to_update_bresp ) begin s_bresp_i = m_bresp; end else begin s_bresp_i = s_bresp_acc; end end ///////////////////////////////////////////////////////////////////////////// // Accumulate MI-side BRESP. always @ (posedge clk) begin if (reset | bresp_push ) begin s_bresp_acc <= LP_RESP_OKAY; end else if ( mhandshake ) begin s_bresp_acc <= s_bresp_i; end end assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty; always @ (posedge clk) begin if (reset | bresp_push ) begin bresp_cnt <= 8'h00; end else if ( mhandshake_r ) begin bresp_cnt <= bresp_cnt + 1'b1; end end axi_protocol_converter_v2_1_8_b2s_simple_fifo #( .C_WIDTH (P_RWIDTH), .C_AWIDTH (P_RAWIDTH), .C_DEPTH (P_RDEPTH) ) bresp_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( bresp_push ) , .rd_en ( shandshake_r ) , .din ( s_bresp_acc ) , .dout ( s_bresp_acc_r) , .a_full ( ) , .full ( bresp_full ) , .a_empty ( ) , .empty ( bresp_empty ) ); endmodule `default_nettype wire

/* * Titor - Byte-striped Memory Bank * Copyright (C) 2013 Sean Ryan Moore * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ `ifdef INC_STRIPED_MEMORY `else `define INC_STRIPED_MEMORY module StripedMemory( dout, din, address, size, read_write, enable, clk, reset ); `include "definition/Definition.v" parameter MDIR = BLANKFILE; // interface output reg [WORD-1:0] dout; input [WORD-1:0] din; input [WORD-1:0] address; input [LOGWORDBYTE-1:0] size; // [0 to WORDBYTE-1] maps to [1 to WORDBYTE] input read_write; input enable; input clk; input reset; wire [WORD-1:0] stripe_dout [WORDBYTE-1:0]; reg [WORD-1:0] stripe_din [WORDBYTE-1:0]; reg [WORD-1:0] stripe_address [WORDBYTE-1:0]; //reg [0-1:0] stripe_size [WORDBYTE-1:0]; reg stripe_read_write [WORDBYTE-1:0]; reg stripe_enable [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] end_left; reg [LOGWORDBYTE-1:0] end_right; reg [LOGWORDBYTE-1:0] off_addr [WORDBYTE-1:0]; reg [WORD-1:0] div_addr [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] iselect [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] oselect [WORDBYTE-1:0]; reg [BYTE-1:0] breakout_din [WORDBYTE-1:0]; reg [LOGWORDBYTE-1:0] d_size; reg [LOGWORDBYTE-1:0] d_oselect [WORDBYTE-1:0]; always @(posedge clk) begin if(reset) begin d_size <= 0; end else begin d_size <= size; end end always @(*) begin end_left <= ((address+0 ) % WORDBYTE); end_right <= ((address+size) % WORDBYTE); end genvar i; generate for(i=0; i<WORDBYTE; i=i+1) begin : MEMGEN if(MDIR != BLANKFILE) begin Memory #( .MWIDTH (BYTE ), // 8-bit word .LOGWORDBYTE (LOGWORDBYTE ), // with 32-bit interfaces .LOGMEM (LOGMEM-LOGWORDBYTE ) // divide by 8 for the 8 banks ) mem ( .dout (stripe_dout[i] ), .din (stripe_din[i] ), .address (stripe_address[i] ), .size (0 ), .read_write (stripe_read_write[i] ), .enable (stripe_enable[i] ), .clk (clk ), .reset (reset ) ); end else begin Memory #( .MFILE (BLANKFILE ), // no input file .MWIDTH (BYTE ), // 8-bit word .LOGWORDBYTE (LOGWORDBYTE ), // with 32-bit interfaces .LOGMEM (LOGMEM-LOGWORDBYTE ) // divide by 8 for the 8 banks ) mem ( .dout (stripe_dout[i] ), .din (stripe_din[i] ), .address (stripe_address[i] ), .size (0 ), .read_write (stripe_read_write[i] ), .enable (stripe_enable[i] ), .clk (clk ), .reset (reset ) ); end always @(*) begin stripe_address[i] <= div_addr[i]; stripe_read_write[i] <= read_write; stripe_enable[i] <= enable && ( (end_left <= end_right) ? ((end_left<=i) && (i<=end_right)) : ((end_left<=i) || (i<=end_right)) ); off_addr[i] <= end_left <= i ? i-end_left : (WORDBYTE-end_left)+i; div_addr[i] <= (address+off_addr[i]) / WORDBYTE; stripe_din[i] <= breakout_din[iselect[i]]; iselect[i] <= (i + WORDBYTE - end_left) % WORDBYTE; oselect[i] <= (i + WORDBYTE + end_left) % WORDBYTE; breakout_din[i] <= din[ (BYTE*(i+1))-1 : (BYTE*(i+0)) ]; dout[ (BYTE*(i+1))-1 : (BYTE*(i+0))-0 ] <= (i<=d_size) ? stripe_dout[d_oselect[i]] : 0; end always @(posedge clk) begin if(reset) begin d_oselect[i] <= 0; end else begin d_oselect[i] <= oselect[i]; end end end endgenerate endmodule `endif

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. //////////////////////////////////////////////////////////////////// // // ALTERA_INT_OSC // // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // //////////////////////////////////////////////////////////////////// // synthesis VERILOG_INPUT_VERSION VERILOG_2001 `timescale 1 ps / 1 ps module altera_int_osc ( clkout, oscena); parameter DEVICE_FAMILY = "MAX 10"; parameter DEVICE_ID = "08"; parameter CLOCK_FREQUENCY = "dummy"; output clkout; input oscena; wire wire_clkout; assign clkout = wire_clkout; // ------------------------------------------------------------------- // Instantiate wysiwyg for chipidblock according to device family // ------------------------------------------------------------------- generate if (DEVICE_FAMILY == "MAX 10") begin fiftyfivenm_oscillator # ( //MAX 10 .device_id(DEVICE_ID), .clock_frequency(CLOCK_FREQUENCY) ) oscillator_dut ( .clkout(wire_clkout), .clkout1(), .oscena(oscena)); end endgenerate endmodule //altera_int_osc //VALID FILE

//Copyright (C) 1991-2012 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module acl_fp_custom_mul_op_s5 ( clock, resetn, mantissa_left, exponent_left, sign_left, mantissa_right, exponent_right, sign_right, result_mantissa, result_exponent, result_sign, // Used in HIGH_CAPACITY = 1 mode stall_in, valid_in, stall_out, valid_out, // Used in HIGH_CAPACITY = 0 mode enable); parameter HIGH_CAPACITY = 1; parameter FLUSH_DENORMS = 0; parameter REMOVE_STICKY = 1; parameter FINITE_MATH_ONLY = 1; parameter HIGH_LATENCY = 1; input clock, resetn; input [26:0] mantissa_left; input [8:0] exponent_left; input sign_left; input [26:0] mantissa_right; input [8:0] exponent_right; input sign_right; input enable; input stall_in, valid_in; output stall_out, valid_out; output [27:0] result_mantissa; output [8:0] result_exponent; output result_sign; wire [53:0] sub_wire0; wire enable_mult_stage; // The multiplier. -- CAUTION This only works for HIGH_LATENCY == 0 --> 2 cycles sv_mult27 the_multiplier(clock,enable_mult_stage,mantissa_left,mantissa_right,sub_wire0); reg [9:0] exponent_1; reg [8:0] exponent_2; reg [8:0] exponent_3; reg [5:0] man_a_clear; reg [5:0] man_b_clear; reg exp_zeroed; reg sign_1, sign_2, sign_3, exp_out_of_range, generate_inf, exp_left, exp_right; reg valid_1, valid_2, valid_3, flush_mantissa, make_nan, make_nan_r; wire stall_mult; assign enable_mult_stage = (HIGH_CAPACITY == 1) ? (~valid_2 | ~stall_mult) : enable; assign stall_out = valid_2 & stall_mult; generate if (HIGH_LATENCY == 1) begin reg flush_mantissa_r; always@(posedge clock or negedge resetn) begin if (~resetn) begin exponent_1 <= 10'dx; exponent_2 <= 9'dx; exponent_3 <= 9'dx; exp_out_of_range <= 1'bx; sign_1 <= 1'bx; sign_2 <= 1'bx; sign_3 <= 1'bx; flush_mantissa_r <= 1'bx; flush_mantissa <= 1'bx; man_a_clear <= 6'dx; man_b_clear <= 6'dx; make_nan_r <= 1'bx; make_nan <= 1'bx; valid_1 <= 1'b0; valid_2 <= 1'b0; valid_3 <= 1'b0; exp_left <= 1'bx; exp_right <= 1'bx; exp_zeroed <= 1'bx; end else if (enable_mult_stage) begin valid_1 <= valid_in; valid_2 <= valid_1; sign_1 <= sign_left ^ sign_right; sign_2 <= sign_1; exp_left <= exponent_left[8]; exp_right <= exponent_right[8]; exp_out_of_range <= (exponent_left[8] | exponent_right[8]); if ((exponent_left[8] || exponent_right[8]) && (FINITE_MATH_ONLY == 0)) exponent_1 <= 10'h1ff; else exponent_1 <= exponent_left + exponent_right - 10'd127; man_a_clear <= {mantissa_left[26], |mantissa_left[25:21], |mantissa_left[20:15], |mantissa_left[14:10], |mantissa_left[9:5], |mantissa_left[4:0]}; man_b_clear <= {mantissa_right[26], |mantissa_right[25:21], |mantissa_right[20:15], |mantissa_right[14:10], |mantissa_right[9:5], |mantissa_right[4:0]}; // Second cycle. flush_mantissa_r <= 1'b0; make_nan_r <= 1'b0; if (exp_out_of_range && (FINITE_MATH_ONLY == 0)) begin exponent_2 <= 9'h1ff; if (((exp_left & (~|man_a_clear[4:0])) & (~exp_right & (~|man_b_clear))) || ((exp_right & (~|man_b_clear[4:0])) & (~exp_left & (~|man_a_clear))) || ((exp_left & (|man_a_clear[4:0])) || (exp_right & (|man_b_clear[4:0])))) make_nan_r <= 1'b1; else flush_mantissa_r <= 1'b1; end else if (exponent_1[9]) // resulting exponent is less than zero. begin exponent_2 <= 9'd0; flush_mantissa_r <= 1'b1; end else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0))// resulting exponent is above max begin flush_mantissa_r <= 1'b1; exponent_2 <= 9'h1ff; end else exponent_2 <= exponent_1[8:0]; // Third cycle. exp_zeroed <= ~|exponent_2; flush_mantissa <= flush_mantissa_r; exponent_3 <= exponent_2; sign_3 <= sign_2; valid_3 <= valid_2; make_nan <= make_nan_r; end end end else begin always@(posedge clock or negedge resetn) begin if (~resetn) begin exponent_1 <= 10'dx; exponent_2 <= 9'dx; exp_out_of_range <= 1'bx; sign_1 <= 1'bx; sign_2 <= 1'bx; flush_mantissa <= 1'bx; man_a_clear <= 5'dx; man_b_clear <= 5'dx; make_nan <= 1'bx; valid_1 <= 1'b0; valid_2 <= 1'b0; exp_left <= 1'bx; exp_right <= 1'bx; exp_zeroed <= 1'bx; end else if (enable_mult_stage) begin valid_1 <= valid_in; valid_2 <= valid_1; sign_1 <= sign_left ^ sign_right; sign_2 <= sign_1; exp_out_of_range <= exponent_left[8] | exponent_right[8]; exp_left <= exponent_left[8]; exp_right <= exponent_right[8]; if ((exponent_left[8] || exponent_right[8]) && (FINITE_MATH_ONLY == 0)) exponent_1 <= 10'h1ff; else exponent_1 <= exponent_left + exponent_right - 10'd127; man_a_clear <= {mantissa_left[26], |mantissa_left[25:21], |mantissa_left[20:15], |mantissa_left[14:10], |mantissa_left[9:5], |mantissa_left[4:0]}; man_b_clear <= {mantissa_right[26], |mantissa_right[25:21], |mantissa_right[20:15], |mantissa_right[14:10], |mantissa_right[9:5], |mantissa_right[4:0]}; // Second cycle. flush_mantissa <= 1'b0; make_nan <= 1'b0; if (exp_out_of_range && (FINITE_MATH_ONLY == 0)) begin exponent_2 <= 9'h1ff; if (((exp_left & (~|man_a_clear[4:0])) & (~exp_right & (~|man_b_clear))) || ((exp_right & (~|man_b_clear[4:0])) & (~exp_left & (~|man_a_clear))) || ((exp_left & (|man_a_clear[4:0])) || (exp_right & (|man_b_clear[4:0])))) make_nan <= 1'b1; else flush_mantissa <= 1'b1; end else if (exponent_1[9]) // resulting exponent is less than zero. begin exponent_2 <= 9'd0; flush_mantissa <= 1'b1; end else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0)) // resulting exponent is above max begin flush_mantissa <= 1'b1; exponent_2 <= 9'h1ff; end else exponent_2 <= exponent_1[8:0]; exp_zeroed <= ~|exponent_1; end end end endgenerate // Now collect results in registers. reg [27:0] mult_result_int; reg [8:0] mult_exp_int; reg mult_sign_int; reg mult_valid_int; reg [4:0] mult_tail_bits; reg exp_was_zero; reg clear_mantissa; reg is_nan; wire stall_post_int; wire enable_post_mult_stage_int; assign enable_post_mult_stage_int = (HIGH_CAPACITY == 1) ? (~mult_valid_int | ~stall_post_int) : enable; assign stall_mult = mult_valid_int & stall_post_int; generate if (HIGH_LATENCY == 1) begin always@(posedge clock or negedge resetn) begin if (~resetn) begin mult_valid_int <= 1'b0; mult_result_int <= 28'dx; mult_exp_int <= 9'dx; clear_mantissa <= 1'bx; mult_tail_bits <= 5'dx; exp_was_zero <= 1'bx; is_nan <= 1'bx; mult_sign_int <= 1'bx; end else if (enable_post_mult_stage_int) begin mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2; is_nan <= make_nan; clear_mantissa <= flush_mantissa | ((FLUSH_DENORMS == 1) & exp_zeroed & (~|sub_wire0[53:52])); mult_result_int <= sub_wire0[53:26]; exp_was_zero <= exp_zeroed; mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2; mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2; if (REMOVE_STICKY == 1) mult_tail_bits <= 5'd0; else mult_tail_bits <= {|sub_wire0[25:20],|sub_wire0[19:15],|sub_wire0[14:10],|sub_wire0[9:5],|sub_wire0[4:0]}; end end end else begin always@(*) begin mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2; is_nan <= make_nan; clear_mantissa <= flush_mantissa | ((FLUSH_DENORMS == 1) & exp_zeroed & (~|sub_wire0[53:52])); mult_result_int <= sub_wire0[53:26]; exp_was_zero <= exp_zeroed; mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2; mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2; if (REMOVE_STICKY == 1) mult_tail_bits <= 5'd0; else mult_tail_bits <= {|sub_wire0[25:20],|sub_wire0[19:15],|sub_wire0[14:10],|sub_wire0[9:5],|sub_wire0[4:0]}; end end endgenerate // Now collect results in registers. reg [27:0] mult_result; reg [8:0] mult_exp; reg mult_sign; reg mult_valid; wire stall_post, enable_post_mult_stage; assign enable_post_mult_stage = (HIGH_CAPACITY == 1) ? (~mult_valid | ~stall_post) : enable; assign stall_post_int = mult_valid & stall_post; generate if (HIGH_LATENCY == 1) begin always@(posedge clock or negedge resetn) begin if (~resetn) begin mult_valid <= 1'b0; mult_result <= 28'dx; mult_exp <= 9'dx; mult_sign <= 1'bx; end else if (enable_post_mult_stage) begin mult_valid <= mult_valid_int; if (REMOVE_STICKY == 1) begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:1]}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0]; end else begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:2], |mult_result_int[1:0] | (|mult_tail_bits)}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] | (|mult_tail_bits)}; end if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa) mult_exp <= 9'd1; else mult_exp <= mult_exp_int; mult_sign <= mult_sign_int; end end end else begin always@(*) begin mult_valid <= mult_valid_int; if (REMOVE_STICKY == 1) begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:1]}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0]; end else begin if (exp_was_zero & ~is_nan &~clear_mantissa) mult_result <= {1'b0, mult_result_int[27:2], |mult_result_int[1:0] | (|mult_tail_bits)}; else mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] | (|mult_tail_bits)}; end if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa) mult_exp <= 9'd1; else mult_exp <= mult_exp_int; mult_sign <= mult_sign_int; end end endgenerate // Now put a staging register if we are in high-capacity mode generate if (HIGH_CAPACITY == 1) begin reg [27:0] result_mantissa_sr; reg [8:0] result_exponent_sr; reg result_sign_sr; reg result_sr_valid; always@(posedge clock or negedge resetn) begin if (~resetn) begin result_mantissa_sr <= 28'dx; result_exponent_sr <= 9'dx; result_sign_sr <= 1'bx; result_sr_valid <= 1'b0; end else begin if (~stall_in) result_sr_valid <= 1'b0; else if (~result_sr_valid) result_sr_valid <= mult_valid; if (~result_sr_valid) begin result_mantissa_sr <= mult_result; result_exponent_sr <= mult_exp; result_sign_sr <= mult_sign; end end end assign result_mantissa = result_sr_valid ? result_mantissa_sr : mult_result; assign result_exponent = result_sr_valid ? result_exponent_sr : mult_exp; assign result_sign = result_sr_valid ? result_sign_sr : mult_sign; assign valid_out = result_sr_valid | mult_valid; assign stall_post = result_sr_valid; end else begin assign result_mantissa = mult_result; assign result_exponent = mult_exp; assign result_sign = mult_sign; assign valid_out = mult_valid; assign stall_post = stall_in; end endgenerate endmodule

//////////////////////////////////////////////////////////////////////////////// // Original Author: Schuyler Eldridge // Contact Point: Schuyler Eldridge ([email protected]) // t_sqrt_pipelined.v // Created: 4.2.2012 // Modified: 4.5.2012 // // Testbench for generic sqrt operation // // Copyright (C) 2012 Schuyler Eldridge, Boston University // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. //////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module t_sqrt_pipelined(); parameter INPUT_BITS = 4; localparam OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; reg [INPUT_BITS-1:0] radicand; reg clk, start, reset_n; wire [OUTPUT_BITS-1:0] root; wire data_valid; // wire [7:0] root_good; sqrt_pipelined #( .INPUT_BITS(INPUT_BITS) ) sqrt_pipelined ( .clk(clk), .reset_n(reset_n), .start(start), .radicand(radicand), .data_valid(data_valid), .root(root) ); initial begin radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;; #10 reset_n = 0; clk = 0; #50 reset_n = 1; radicand = 0; // #40 radicand = 81; start = 1; // #10 radicand = 16'bx; start = 0; #10000 $finish; end always #5 clk = ~clk; always begin #10 radicand = radicand + 1; start = 1; #10 start = 0; end // always begin // #80 start = 1; // #10 start = 0; // end endmodule

//`include "../../firmware/include/fpga_regs_common.v" //`include "../../firmware/include/fpga_regs_standard.v" module rx_buffer_inband ( input usbclk, input bus_reset, input reset, // DSP side reset (used here), do not reset registers input reset_regs, //Only reset registers output [15:0] usbdata, input RD, output wire have_pkt_rdy, output reg rx_overrun, input wire [3:0] channels, input wire [15:0] ch_0, input wire [15:0] ch_1, input wire [15:0] ch_2, input wire [15:0] ch_3, input wire [15:0] ch_4, input wire [15:0] ch_5, input wire [15:0] ch_6, input wire [15:0] ch_7, input rxclk, input rxstrobe, input clear_status, input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, output wire [15:0] debugbus, //Connection with tx_inband input rx_WR, input [15:0] rx_databus, input rx_WR_done, output reg rx_WR_enabled, //signal strength input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, input wire [31:0] rssi_3, input wire [1:0] tx_underrun ); parameter NUM_CHAN =1; genvar i ; // FX2 Bug Fix reg [8:0] read_count; always @(negedge usbclk) if(bus_reset) read_count <= #1 9'd0; else if(RD & ~read_count[8]) read_count <= #1 read_count + 9'd1; else read_count <= #1 RD ? read_count : 9'b0; // Time counter reg [31:0] adctime; always @(posedge rxclk) if (reset) adctime <= 0; else if (rxstrobe) adctime <= adctime + 1; // USB side fifo wire [11:0] rdusedw; wire [11:0] wrusedw; wire [15:0] fifodata; wire [15:0] fifodata_il; reg [15:0] fifodata_16; wire WR; wire have_space; assign fifodata_il = fifodata_16; fifo_4kx16_dc rx_usb_fifo ( .aclr ( reset ), .data ( fifodata ), .rdclk ( ~usbclk ), .rdreq ( RD & ~read_count[8] ), .wrclk ( rxclk ), .wrreq ( WR ), .q ( usbdata ), .rdempty ( ), .rdusedw ( rdusedw ), .wrfull ( ), .wrusedw ( wrusedw ) ); assign have_pkt_rdy = (rdusedw >= 12'd256); assign have_space = (wrusedw < 12'd760); // Rx side fifos wire chan_rdreq; wire [15:0] chan_fifodata; wire [9:0] chan_usedw; wire [NUM_CHAN:0] chan_empty; wire [3:0] rd_select; wire [NUM_CHAN:0] rx_full; wire [7:0] debug; packet_builder #(NUM_CHAN) rx_pkt_builer ( .rxclk ( rxclk ), .reset ( reset ), .adctime ( adctime ), .channels ( 4'd1 ), //need to be tested and changed to channels .chan_rdreq ( chan_rdreq ), .chan_fifodata ( chan_fifodata ), .chan_empty ( chan_empty ), .rd_select ( rd_select ), .chan_usedw ( chan_usedw ), .WR ( WR ), .fifodata ( fifodata ), .have_space ( have_space ), .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), .underrun(tx_underrun)); // Detect overrun always @(posedge rxclk) if(reset) rx_overrun <= 1'b0; else if(rx_full[0]) rx_overrun <= 1'b1; else if(clear_status) rx_overrun <= 1'b0; // TODO write this genericly //wire [15:0]ch[NUM_CHAN:0]; //assign ch[0] = ch_0; wire cmd_empty; always @(posedge rxclk) if(reset) rx_WR_enabled <= 1; else if(cmd_empty) rx_WR_enabled <= 1; else if(rx_WR_done) rx_WR_enabled <= 0; // Switching of channels reg [3:0] store_next; always @(posedge rxclk) if(reset) store_next <= #1 4'd0; else if(rxstrobe & (store_next == 0)) store_next <= #1 4'd1; else if(~rx_full & (store_next == 4'd2)) store_next <= #1 4'd0; else if(~rx_full & (store_next != 0)) store_next <= #1 store_next + 4'd1; always @* case(store_next) 4'd1 : fifodata_16 = ch_0; 4'd2 : fifodata_16 = ch_1; default: fifodata_16 = 16'hFFFF; endcase wire [15:0] dataout [0:NUM_CHAN]; wire [9:0] usedw [0:NUM_CHAN]; wire empty[0:NUM_CHAN]; generate for (i = 0 ; i < NUM_CHAN; i = i + 1) begin : generate_channel_fifos wire rdreq; assign rdreq = (rd_select == i) & chan_rdreq; fifo_1kx16 rx_chan_fifo ( .aclr ( reset ), .clock ( rxclk ), .data ( fifodata_il ), .rdreq ( rdreq ), .wrreq ( ~rx_full[i] & (store_next != 0)), .empty (empty[i]), .full (rx_full[i]), .q ( dataout[i]), .usedw ( usedw[i]), .almost_empty(chan_empty[i]) ); end endgenerate fifo_1kx16 rx_cmd_fifo ( .aclr ( reset ), .clock ( rxclk ), .data ( rx_databus ), .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), .wrreq ( rx_WR & rx_WR_enabled), .empty ( cmd_empty), .full ( rx_full[NUM_CHAN] ), .q ( dataout[NUM_CHAN]), .usedw ( usedw[NUM_CHAN] ) ); assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; assign chan_fifodata = dataout[rd_select]; assign chan_usedw = usedw[rd_select]; assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]}; endmodule

module m_tera; // global section // specify clock LOW and reset HIGH initial values reg r_clock = 1'b0; reg r_reset = 1'b1; wire w_clock, w_reset; assign w_clock = r_clock; assign w_reset = r_reset; // end global section // program counter section reg r_pc_demux_channel = 1'b0; wire [7:0] w_bus_instr_mem_addr, w_bus_alu_out; wire w_jump_flag; m_program_counter pc (w_bus_instr_mem_addr, w_bus_alu_out, w_jump_flag, w_clock, w_reset); // end program counter section // memory section wire [7:0] w_bus_instr_mem_word, w_bus_data_mem_word, w_bus_data_mem_addr, w_bus_high_register_value, w_bus_low_register_value; wire w_data_mem_write_enable; m_instruction_memory instr_mem (w_bus_instr_mem_word, w_bus_instr_mem_addr); m_data_memory data_mem (w_bus_data_mem_word, w_bus_high_register_value, w_data_mem_write_enable, w_reset, w_clock); // end memory section // register file section wire [7:0] w_bus_write_back_value; wire [3:0] w_bus_write_back_reg; wire w_write_back_flag; m_register_file regfile (w_bus_high_register_value, w_bus_low_register_value, w_bus_instr_mem_word, w_bus_write_back_value, w_bus_write_back_reg, w_write_back_flag, w_clock, w_reset); // end register file section // instruction logic unit section wire w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_cf; // w_cf is comparison flag m_instruction_logic_unit ilu (w_jump_flag, w_data_mem_write_enable, w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_write_back_flag, w_bus_write_back_reg, w_bus_instr_mem_word, w_cf, w_clock); // end instruction logic unit section // arithmetic logic unit section m_arithmetic_logic_unit alu (w_bus_alu_out, w_cf, w_bus_instr_mem_word, w_bus_high_register_value, w_bus_low_register_value, w_clock); // end arithmetic logic unit section // mux/demux section wire [7:0] w_bus_demux_inter0, w_bus_mux_inter; m_1to2_8bit_demux store_demux (w_bus_demux_inter0, w_bus_data_mem_word, w_bus_alu_out, w_store_word_flag); m_2to1_8bit_mux load_mux (w_bus_mux_inter, w_bus_demux_inter0, w_bus_data_mem_word, w_load_word_flag); m_2to1_8bit_mux_with_add1 pc_mux (w_bus_write_back_value, w_bus_mux_inter, w_bus_instr_mem_addr, w_store_pc_flag); // end mux/demux section initial begin $dumpfile ("dumpfile.vcd"); $dumpvars (0, m_tera); $display ("\nStarting program (Program Counter = 0).\n"); #2 r_reset = 1'b0; end always #1 begin r_clock = ~w_clock; // send clock pulses if (w_bus_instr_mem_addr == 8'b11111111) begin $display ("\nReached EOF (Program Counter = 255). Closing program.\n"); $finish; end end endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V `define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V /** * or2b: 2-input OR, first input inverted. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_hd__or2b ( X , A , B_N , VPWR, VGND, VPB , VNB ); // Module ports output X ; input A ; input B_N ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire not0_out ; wire or0_out_X ; wire pwrgood_pp0_out_X; // Name Output Other arguments not not0 (not0_out , B_N ); or or0 (or0_out_X , not0_out, A ); sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND); buf buf0 (X , pwrgood_pp0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V

//----------------------------------------------------------------- // System Generator version 2013.4 Verilog source file. // // Copyright(C) 2013 by Xilinx, Inc. All rights reserved. This // text/file contains proprietary, confidential information of Xilinx, // Inc., is distributed under license from Xilinx, Inc., and may be used, // copied and/or disclosed only pursuant to the terms of a valid license // agreement with Xilinx, Inc. Xilinx hereby grants you a license to use // this text/file solely for design, simulation, implementation and // creation of design files limited to Xilinx devices or technologies. // Use with non-Xilinx devices or technologies is expressly prohibited // and immediately terminates your license unless covered by a separate // agreement. // // Xilinx is providing this design, code, or information "as is" solely // for use in developing programs and solutions for Xilinx devices. By // providing this design, code, or information as one possible // implementation of this feature, application or standard, Xilinx is // making no representation that this implementation is free from any // claims of infringement. You are responsible for obtaining any rights // you may require for your implementation. Xilinx expressly disclaims // any warranty whatsoever with respect to the adequacy of the // implementation, including but not limited to warranties of // merchantability or fitness for a particular purpose. // // Xilinx products are not intended for use in life support appliances, // devices, or systems. Use in such applications is expressly prohibited. // // Any modifications that are made to the source code are done at the user's // sole risk and will be unsupported. // // This copyright and support notice must be retained as part of this // text at all times. (c) Copyright 1995-2013 Xilinx, Inc. All rights // reserved. //----------------------------------------------------------------- `include "conv_pkg.v" module xlconvert_ip_pid_controller (din, clk, ce, clr, en, dout); //Parameter Definitions parameter din_width= 16; parameter din_bin_pt= 4; parameter din_arith= `xlUnsigned; parameter dout_width= 8; parameter dout_bin_pt= 2; parameter dout_arith= `xlUnsigned; parameter en_width = 1; parameter en_bin_pt = 0; parameter en_arith = `xlUnsigned; parameter bool_conversion = 0; parameter latency = 0; parameter quantization= `xlTruncate; parameter overflow= `xlWrap; //Port Declartions input [din_width-1:0] din; input clk, ce, clr; input [en_width-1:0] en; output [dout_width-1:0] dout; //Wire Declartions wire [dout_width-1:0] result; wire internal_ce; assign internal_ce = ce & en[0]; generate if (bool_conversion == 1) begin:bool_converion_generate assign result = din; end else begin:std_conversion convert_type #(din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow) conv_udp (.inp(din), .res(result)); end endgenerate generate if (latency > 0) begin:latency_test synth_reg # (dout_width, latency) reg1 ( .i(result), .ce(internal_ce), .clr(clr), .clk(clk), .o(dout)); end else begin:latency0 assign dout = result; end endgenerate endmodule module sysgen_mcode_block_698c2b186c ( input [(32 - 1):0] x, output [(32 - 1):0] z, input clk, input ce, input clr); wire signed [(32 - 1):0] x_1_22; localparam [(11 - 1):0] const_value = 11'b10010000000; localparam [(11 - 1):0] const_value_x_000000 = 11'b11111111111; localparam [(11 - 1):0] const_value_x_000001 = 11'b10010000000; localparam signed [(32 - 1):0] const_value_x_000002 = 32'sb00000100100000000000000000000000; wire rel_3_6; localparam [(11 - 1):0] const_value_x_000003 = 11'b11111111111; localparam signed [(32 - 1):0] const_value_x_000004 = 32'sb00000111111111110000000000000000; wire rel_5_10; reg signed [(32 - 1):0] z_join_3_3; localparam signed [(32 - 1):0] const_value_x_000005 = 32'sb00000100100000000000000000000000; localparam signed [(32 - 1):0] const_value_x_000006 = 32'sb00000111111111110000000000000000; assign x_1_22 = x; assign rel_3_6 = x_1_22 < const_value_x_000002; assign rel_5_10 = x_1_22 > const_value_x_000004; always @(rel_3_6 or rel_5_10 or x_1_22) begin:proc_if_3_3 if (rel_3_6) begin z_join_3_3 = const_value_x_000005; end else if (rel_5_10) begin z_join_3_3 = const_value_x_000006; end else begin z_join_3_3 = x_1_22; end end assign z = z_join_3_3; endmodule module sysgen_constant_383443dd88 ( output [(8 - 1):0] op, input clk, input ce, input clr); assign op = 8'b00000000; endmodule module xldelay_ip_pid_controller #(parameter width = -1, latency = -1, reg_retiming = 0, reset = 0) (input [width-1:0] d, input ce, clk, en, rst, output [width-1:0] q); generate if ((latency == 0) || ((reg_retiming == 0) && (reset == 0))) begin:srl_delay synth_reg # (width, latency) reg1 ( .i(d), .ce(ce & en), .clr(1'b0), .clk(clk), .o(q)); end if ((latency>=1) && ((reg_retiming) || (reset))) begin:reg_delay synth_reg_reg # (width, latency) reg2 ( .i(d), .ce(ce & en), .clr(rst), .clk(clk), .o(q)); end endgenerate endmodule module sysgen_inverter_91fd45ca5a ( input [(1 - 1):0] ip, output [(1 - 1):0] op, input clk, input ce, input clr); wire ip_1_26; reg op_mem_22_20[0:(1 - 1)]; initial begin op_mem_22_20[0] = 1'b0; end wire op_mem_22_20_front_din; wire op_mem_22_20_back; wire op_mem_22_20_push_front_pop_back_en; localparam [(1 - 1):0] const_value = 1'b1; wire internal_ip_12_1_bitnot; assign ip_1_26 = ip; assign op_mem_22_20_back = op_mem_22_20[0]; always @(posedge clk) begin:proc_op_mem_22_20 integer i; if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1))) begin op_mem_22_20[0] <= op_mem_22_20_front_din; end end assign internal_ip_12_1_bitnot = ~ip_1_26; assign op_mem_22_20_front_din = internal_ip_12_1_bitnot; assign op_mem_22_20_push_front_pop_back_en = 1'b1; assign op = op_mem_22_20_back; endmodule module sysgen_logical_098c9fa070 ( input [(1 - 1):0] d0, input [(1 - 1):0] d1, output [(1 - 1):0] y, input clk, input ce, input clr); wire d0_1_24; wire d1_1_27; wire fully_2_1_bit; assign d0_1_24 = d0; assign d1_1_27 = d1; assign fully_2_1_bit = d0_1_24 & d1_1_27; assign y = fully_2_1_bit; endmodule module xlregister_ip_pid_controller (d, rst, en, ce, clk, q); parameter d_width = 5; parameter init_value = 'b0; input [d_width-1:0] d; input rst, en, ce, clk; output [d_width-1:0] q; wire internal_clr, internal_ce; assign internal_clr = rst & ce; assign internal_ce = ce & en; synth_reg_w_init #(.width(d_width), .init_index(2), .init_value(init_value), .latency(1)) synth_reg_inst(.i(d), .ce(internal_ce), .clr(internal_clr), .clk(clk), .o(q)); endmodule module sysgen_relational_0c5dbda85b ( input [(8 - 1):0] a, input [(8 - 1):0] b, output [(1 - 1):0] op, input clk, input ce, input clr); wire [(8 - 1):0] a_1_31; wire [(8 - 1):0] b_1_34; localparam [(1 - 1):0] const_value = 1'b1; wire result_12_3_rel; assign a_1_31 = a; assign b_1_34 = b; assign result_12_3_rel = a_1_31 == b_1_34; assign op = result_12_3_rel; endmodule module sysgen_constant_61a644b4c8 ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b01011111010111100001000000000000; endmodule module sysgen_accum_ac23432ab2 ( input [(32 - 1):0] b, input [(1 - 1):0] rst, input [(1 - 1):0] en, output [(32 - 1):0] q, input clk, input ce, input clr); wire signed [(32 - 1):0] b_17_24; wire rst_17_27; wire en_17_32; reg signed [(32 - 1):0] accum_reg_41_23 = 32'b00000000000000000000000000000000; wire accum_reg_41_23_rst; wire accum_reg_41_23_en; localparam [(1 - 1):0] const_value = 1'b0; localparam [(1 - 1):0] const_value_x_000000 = 1'b1; localparam [(1 - 1):0] const_value_x_000001 = 1'b0; localparam [(1 - 1):0] const_value_x_000002 = 1'b1; reg signed [(33 - 1):0] accum_reg_join_47_1; reg accum_reg_join_47_1_en; reg accum_reg_join_47_1_rst; assign b_17_24 = b; assign rst_17_27 = rst; assign en_17_32 = en; always @(posedge clk) begin:proc_accum_reg_41_23 if (((ce == 1'b1) && (accum_reg_41_23_rst == 1'b1))) begin accum_reg_41_23 <= 32'b00000000000000000000000000000000; end else if (((ce == 1'b1) && (accum_reg_41_23_en == 1'b1))) begin accum_reg_41_23 <= accum_reg_41_23 + b_17_24; end end always @(accum_reg_41_23 or b_17_24 or en_17_32 or rst_17_27) begin:proc_if_47_1 if (rst_17_27) begin accum_reg_join_47_1_rst = 1'b1; end else if (en_17_32) begin accum_reg_join_47_1_rst = 1'b0; end else begin accum_reg_join_47_1_rst = 1'b0; end if (en_17_32) begin accum_reg_join_47_1_en = 1'b1; end else begin accum_reg_join_47_1_en = 1'b0; end end assign accum_reg_41_23_rst = accum_reg_join_47_1_rst; assign accum_reg_41_23_en = accum_reg_join_47_1_en; assign q = accum_reg_41_23; endmodule module sysgen_constant_b4741603e8 ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b00000111111111110000000000000000; endmodule module sysgen_constant_a7c2a996dd ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b00000000000000000000000000000000; endmodule module sysgen_constant_bd840882a6 ( output [(32 - 1):0] op, input clk, input ce, input clr); assign op = 32'b00000100100000000000000000000000; endmodule module sysgen_logical_0c47d61908 ( input [(1 - 1):0] d0, input [(1 - 1):0] d1, output [(1 - 1):0] y, input clk, input ce, input clr); wire d0_1_24; wire d1_1_27; wire bit_2_27; wire fully_2_1_bitnot; assign d0_1_24 = d0; assign d1_1_27 = d1; assign bit_2_27 = d0_1_24 & d1_1_27; assign fully_2_1_bitnot = ~bit_2_27; assign y = fully_2_1_bitnot; endmodule module sysgen_logical_7913ccf482 ( input [(1 - 1):0] d0, input [(1 - 1):0] d1, input [(1 - 1):0] d2, output [(1 - 1):0] y, input clk, input ce, input clr); wire d0_1_24; wire d1_1_27; wire d2_1_30; wire fully_2_1_bit; assign d0_1_24 = d0; assign d1_1_27 = d1; assign d2_1_30 = d2; assign fully_2_1_bit = d0_1_24 & d1_1_27 & d2_1_30; assign y = fully_2_1_bit; endmodule module sysgen_relational_56046aa836 ( input [(32 - 1):0] a, input [(32 - 1):0] b, output [(1 - 1):0] op, input clk, input ce, input clr); wire signed [(32 - 1):0] a_1_31; wire signed [(32 - 1):0] b_1_34; localparam [(1 - 1):0] const_value = 1'b1; wire result_18_3_rel; assign a_1_31 = a; assign b_1_34 = b; assign result_18_3_rel = a_1_31 > b_1_34; assign op = result_18_3_rel; endmodule module sysgen_relational_860373682b ( input [(32 - 1):0] a, input [(32 - 1):0] b, output [(1 - 1):0] op, input clk, input ce, input clr); wire signed [(32 - 1):0] a_1_31; wire signed [(32 - 1):0] b_1_34; localparam [(1 - 1):0] const_value = 1'b1; wire result_16_3_rel; assign a_1_31 = a; assign b_1_34 = b; assign result_16_3_rel = a_1_31 < b_1_34; assign op = result_16_3_rel; endmodule module xladdsub_ip_pid_controller (a, b, c_in, ce, clr, clk, rst, en, c_out, s); parameter core_name0= ""; parameter a_width= 16; parameter signed a_bin_pt= 4; parameter a_arith= `xlUnsigned; parameter c_in_width= 16; parameter c_in_bin_pt= 4; parameter c_in_arith= `xlUnsigned; parameter c_out_width= 16; parameter c_out_bin_pt= 4; parameter c_out_arith= `xlUnsigned; parameter b_width= 8; parameter signed b_bin_pt= 2; parameter b_arith= `xlUnsigned; parameter s_width= 17; parameter s_bin_pt= 4; parameter s_arith= `xlUnsigned; parameter rst_width= 1; parameter rst_bin_pt= 0; parameter rst_arith= `xlUnsigned; parameter en_width= 1; parameter en_bin_pt= 0; parameter en_arith= `xlUnsigned; parameter full_s_width= 17; parameter full_s_arith= `xlUnsigned; parameter mode= `xlAddMode; parameter extra_registers= 0; parameter latency= 0; parameter quantization= `xlTruncate; parameter overflow= `xlWrap; parameter c_a_width= 16; parameter c_b_width= 8; parameter c_a_type= 1; parameter c_b_type= 1; parameter c_has_sclr= 0; parameter c_has_ce= 0; parameter c_latency= 0; parameter c_output_width= 17; parameter c_enable_rlocs= 1; parameter c_has_c_in= 0; parameter c_has_c_out= 0; input [a_width-1:0] a; input [b_width-1:0] b; input c_in, ce, clr, clk, rst, en; output c_out; output [s_width-1:0] s; parameter full_a_width = full_s_width; parameter full_b_width = full_s_width; parameter full_s_bin_pt = (a_bin_pt > b_bin_pt) ? a_bin_pt : b_bin_pt; wire [full_a_width-1:0] full_a; wire [full_b_width-1:0] full_b; wire [full_s_width-1:0] full_s; wire [full_s_width-1:0] core_s; wire [s_width-1:0] conv_s; wire temp_cout; wire real_a,real_b,real_s; wire internal_clr; wire internal_ce; wire extra_reg_ce; wire override; wire logic1; wire temp_cin; assign internal_clr = (clr | rst) & ce; assign internal_ce = ce & en; assign logic1 = 1'b1; assign temp_cin = (c_has_c_in) ? c_in : 1'b0; align_input # (a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width) align_inp_a(.inp(a),.res(full_a)); align_input # (b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width) align_inp_b(.inp(b),.res(full_b)); convert_type # (full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow) conv_typ_s(.inp(core_s),.res(conv_s)); generate if (core_name0 == "ip_pid_controller_c_addsub_v12_0_0") begin:comp0 ip_pid_controller_c_addsub_v12_0_0 core_instance0 ( .A(full_a), .S(core_s), .B(full_b) ); end if (core_name0 == "ip_pid_controller_c_addsub_v12_0_1") begin:comp1 ip_pid_controller_c_addsub_v12_0_1 core_instance1 ( .A(full_a), .S(core_s), .B(full_b) ); end endgenerate generate if (extra_registers > 0) begin:latency_test if (c_latency > 1) begin:override_test synth_reg # (1, c_latency) override_pipe ( .i(logic1), .ce(internal_ce), .clr(internal_clr), .clk(clk), .o(override)); assign extra_reg_ce = ce & en & override; end // override_test if ((c_latency == 0) || (c_latency == 1)) begin:no_override assign extra_reg_ce = ce & en; end // no_override synth_reg # (s_width, extra_registers) extra_reg ( .i(conv_s), .ce(extra_reg_ce), .clr(internal_clr), .clk(clk), .o(s)); if (c_has_c_out == 1) begin:cout_test synth_reg # (1, extra_registers) c_out_extra_reg ( .i(temp_cout), .ce(extra_reg_ce), .clr(internal_clr), .clk(clk), .o(c_out)); end // cout_test end // latency_test endgenerate generate if ((latency == 0) || (extra_registers == 0)) begin:latency_s assign s = conv_s; end // latency_s endgenerate generate if (((latency == 0) || (extra_registers == 0)) && (c_has_c_out == 1)) begin:latency0 assign c_out = temp_cout; end // latency0 endgenerate generate if (c_has_c_out == 0) begin:tie_dangling_cout assign c_out = 0; end // tie_dangling_cout endgenerate endmodule module xlcounter_limit_ip_pid_controller (ce, clr, clk, op, up, en, rst); parameter core_name0= ""; parameter op_width= 5; parameter op_arith= `xlSigned; parameter cnt_63_48 = 0; parameter cnt_47_32 = 0; parameter cnt_31_16 = 0; parameter cnt_15_0 = 0; parameter count_limited= 0; input ce, clr, clk; input rst, en; input up; output [op_width-1:0] op; parameter [63:0] cnt_to = { cnt_63_48[15:0], cnt_47_32[15:0], cnt_31_16[15:0], cnt_15_0[15:0]}; parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}}; reg op_thresh0; wire core_sinit, core_ce; wire rst_overrides_en; wire [op_width-1:0] op_net; assign op = op_net; assign core_ce = ce & en; assign rst_overrides_en = rst | en; generate if (count_limited == 1) begin :limit always @(op_net) begin:eq_cnt_to op_thresh0 = (op_net == cnt_to[op_width-1:0])? 1'b1 : 1'b0; end assign core_sinit = (op_thresh0 | clr | rst) & ce & rst_overrides_en; end if (count_limited == 0) begin :no_limit assign core_sinit = (clr | rst) & ce & rst_overrides_en; end if (core_name0 == "ip_pid_controller_c_counter_binary_v12_0_0") begin:comp0 ip_pid_controller_c_counter_binary_v12_0_0 core_instance0 ( .CLK(clk), .CE(core_ce), .SINIT(core_sinit), .Q(op_net) ); end endgenerate endmodule module xldivider_generator_c21cb25008addda87fe275acdfb605e1 (a,a_tvalid,b,b_tvalid,ce,clk,op); input[31:0] a; input a_tvalid; input[31:0] b; input b_tvalid; input ce; input clk; output[37:0] op; wire[39:0] m_axis_dout_tdata_net; wire[37:0] m_axis_dout_tdata_shift_in_net; wire[37:0] m_axis_dout_tdata_shift_out_net; wire result_tvalid; wire[31:0] s_axis_dividend_tdata_net; wire[31:0] s_axis_divisor_tdata_net; assign m_axis_dout_tdata_shift_in_net = m_axis_dout_tdata_net[37 : 0]; assign op = m_axis_dout_tdata_shift_out_net; assign s_axis_dividend_tdata_net[31 : 0] = a; assign s_axis_divisor_tdata_net[31 : 0] = b; shift_op # ( .inp_width(38), .result_width(38), .shift_value(6), .shift_dir(0)) shift_op_m_axis_dout_tdata_shift_in_net(.inp(m_axis_dout_tdata_shift_in_net), .res(m_axis_dout_tdata_shift_out_net)); ip_pid_controller_div_gen_v5_1_0 ip_pid_controller_div_gen_v5_1_0_instance( .aclk(clk), .m_axis_dout_tdata(m_axis_dout_tdata_net), .m_axis_dout_tvalid(result_tvalid), .s_axis_dividend_tdata(s_axis_dividend_tdata_net), .s_axis_dividend_tvalid(a_tvalid), .s_axis_divisor_tdata(s_axis_divisor_tdata_net), .s_axis_divisor_tvalid(b_tvalid) ); endmodule module xlmult_ip_pid_controller (a, b, ce, clr, clk, core_ce, core_clr,core_clk, rst, en,p); parameter core_name0 = ""; parameter a_width = 4; parameter a_bin_pt = 2; parameter a_arith = `xlSigned; parameter b_width = 4; parameter b_bin_pt = 1; parameter b_arith = `xlSigned; parameter p_width = 8; parameter p_bin_pt = 2; parameter p_arith = `xlSigned; parameter rst_width = 1; parameter rst_bin_pt = 0; parameter rst_arith = `xlUnsigned; parameter en_width = 1; parameter en_bin_pt = 0; parameter en_arith = `xlUnsigned; parameter quantization = `xlTruncate; parameter overflow = `xlWrap; parameter extra_registers = 0; parameter c_a_width = 7; parameter c_b_width = 7; parameter c_type = 0; parameter c_a_type = 0; parameter c_b_type = 0; parameter c_baat = 4; parameter oversample = 1; parameter multsign = `xlSigned; parameter c_output_width = 16; input [a_width - 1 : 0] a; input [b_width - 1 : 0] b; input ce, clr, clk; input core_ce, core_clr, core_clk; input en, rst; output [p_width - 1 : 0] p; wire [c_a_width - 1 : 0] tmp_a, conv_a; wire [c_b_width - 1 : 0] tmp_b, conv_b; wire [c_output_width - 1 : 0] tmp_p; wire [p_width - 1 : 0] conv_p; wire internal_ce, internal_clr, internal_core_ce; wire rfd, rdy, nd; assign internal_ce = ce & en; assign internal_core_ce = core_ce & en; assign internal_clr = (clr | rst) & en; assign nd = ce & en; zero_ext # (a_width, c_a_width) zero_ext_a (.inp(a), .res(tmp_a)); zero_ext # (b_width, c_b_width) zero_ext_b (.inp(b), .res(tmp_b)); //Output Process convert_type # (c_output_width, a_bin_pt+b_bin_pt, multsign, p_width, p_bin_pt, p_arith, quantization, overflow) conv_udp (.inp(tmp_p), .res(conv_p)); generate if (core_name0 == "ip_pid_controller_mult_gen_v12_0_0") begin:comp0 ip_pid_controller_mult_gen_v12_0_0 core_instance0 ( .A(tmp_a), .B(tmp_b), .CLK(clk), .CE(internal_ce), .SCLR(internal_clr), .P(tmp_p) ); end if (extra_registers > 0) begin:latency_gt_0 synth_reg # (p_width, extra_registers) reg1 ( .i(conv_p), .ce(internal_ce), .clr(internal_clr), .clk(clk), .o(p)); end if (extra_registers == 0) begin:latency_eq_0 assign p = conv_p; end endgenerate endmodule

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Wilson Snyder. module t; integer p_i; reg [7*8:1] p_str; initial begin if ($test$plusargs("PLUS")!==1) $stop; if ($test$plusargs("PLUSNOT")!==0) $stop; if ($test$plusargs("PL")!==1) $stop; //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer if ($test$plusargs("NOTTHERE")!==0) $stop; p_i = 10; if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop; if (p_i !== 10) $stop; if ($value$plusargs("INT=%d", p_i)!==1) $stop; if (p_i !== 32'd1234) $stop; if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also if (p_i !== 32'h1234) $stop; if ($value$plusargs("INT=%o", p_i)!==1) $stop; if (p_i !== 32'o1234) $stop; if ($value$plusargs("IN%s", p_str)!==1) $stop; $display("str='%s'",p_str); if (p_str !== "T=1234") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule

//----------------------------------------------------------------------------- // File : avalon_st_gen.v // Author : Altera Corporation //----------------------------------------------------------------------------- // Copyright 2008 Altera Corporation. All rights reserved. Altera products are // protected under numerous U.S. and foreign patents, maskwork rights, copyrights and // other intellectual property laws. // This reference design file, and your use thereof, is subject to and governed by // the terms and conditions of the applicable Altera Reference Design License Agreement. // By using this reference design file, you indicate your acceptance of such terms and // conditions between you and Altera Corporation. In the event that you do not agree with // such terms and conditions, you may not use the reference design file. Please promptly // destroy any copies you have made. // // This reference design file being provided on an "as-is" basis and as an accommodation // and therefore all warranties, representations or guarantees of any kind // (whether express, implied or statutory) including, without limitation, warranties of // merchantability, non-infringement, or fitness for a particular purpose, are // specifically disclaimed. By making this reference design file available, Altera // expressly does not recommend, suggest or require that this reference design file be // used in combination with any other product not provided by Altera // turn off bogus verilog processor warnings // altera message_off 10034 10035 10036 10037 10230 module avalon_st_gen ( input clk // TX FIFO Interface clock ,input reset // Reset signal ,input [7:0] address // Register Address ,input write // Register Write Strobe ,input read // Register Read Strobe ,output wire waitrequest ,input [31:0] writedata // Register Write Data ,output reg [31:0] readdata // Register Read Data ,input tx_ready // Avalon-ST Ready Input ,output reg [63:0] tx_data // Avalon-ST TX Data ,output reg tx_valid // Avalon-ST TX Valid ,output reg tx_sop // Avalon-ST TX StartOfPacket ,output reg tx_eop // Avalon-ST TX EndOfPacket ,output reg [2:0] tx_empty // Avalon-ST TX Empty ,output wire tx_error // Avalon-ST TX Error ); // ___________________________________________________________ // address parameters // ___________________________________________________________ parameter ADDR_NUMPKTS = 8'h0; parameter ADDR_RANDOMLENGTH = 8'h1; parameter ADDR_RANDOMPAYLOAD = 8'h2; parameter ADDR_START = 8'h3; parameter ADDR_STOP = 8'h4; parameter ADDR_MACSA0 = 8'h5; parameter ADDR_MACSA1 = 8'h6; parameter ADDR_MACDA0 = 8'h7; parameter ADDR_MACDA1 = 8'h8; parameter ADDR_TXPKTCNT = 8'h9; parameter ADDR_RNDSEED0 = 8'ha; parameter ADDR_RNDSEED1 = 8'hb; parameter ADDR_RNDSEED2 = 8'hc; parameter ADDR_PKTLENGTH = 8'hd; parameter ADDR_CNTDASA = 8'hf0; parameter ADDR_CNTSATLEN = 8'hf1; parameter ADDR_CNTDATA = 8'hf2; parameter ADDR_CNTTRNSTN = 8'hf3; // 10G Ethernet Control Registers reg start_reg; wire start; // Start operation of packet generator reg stop; // Stop operation of packet generator reg [31:0] number_packet; // Register to store number of packets to be transmitted reg [31:0] config_setting; // Register to configure settings: data pattern type, length reg [31:0] source_addr0; // Register to program the MAC source address [31:0] reg [31:0] source_addr1; // Register to program the MAC source address [47:32] reg [31:0] destination_addr0; // Register to program the MAC destination address [31:0] reg [31:0] destination_addr1; // Register to program the MAC destination address [47:32] reg [31:0] packet_tx_count; // Register to count the number of succesfully transmitted packets reg [31:0] rand_seed0; // Register to program seed number for prbs generator [31:0] reg [31:0] rand_seed1; // Register to program seed number for prbs generator [63:32] reg [31:0] rand_seed2; // Register to program seed number for prbs generator [91:64] reg random_payload; // Select what type of data pattern:0=incremental, 1=random reg random_length; // Select what type of packet length:0=fixed, 1=random reg [13:0] pkt_length; // Fixed payload length for every packet wire [7:0] DA5,DA4,DA3,DA2,DA1,DA0; wire [7:0] SA5,SA4,SA3,SA2,SA1,SA0; wire [91:0] random_seed; // Random seed number for PRBS generator wire S_IDLE; wire S_DEST_SRC; wire S_SRC_LEN_SEQ; wire S_DATA; wire S_TRANSITION; reg[31:0] cnt_dasa, cnt_satlen, cnt_data, cnt_trnstn; reg [2:0] ns; reg [2:0] ps; // State machine parameters // -------------------------- localparam state_idle = 3'b000; // Idle State localparam state_dest_src = 3'b001; // Dest(47:0) & Src(47:32) State localparam state_src_len_seq = 3'b010; // Src(31:0) & Length(15:0) & SeqNr(15:0) State localparam state_data = 3'b011; // Data Pattern State localparam state_transition = 3'b100; // Transition State wire [91:0] tx_prbs; reg [15:0] byte_count; reg [63:0] data_pattern; reg [15:0] length; reg [15:0] seq_num; // Avalon-ST signals to CRC generator // ----------------------------------- wire [3:0] empty; reg [63:0] tx_data_reg; reg tx_valid_reg; reg tx_sop_reg; reg tx_eop_reg; reg [2:0] tx_empty_reg; wire crc_valid; wire [31:0] crc; reg [31:0] crc_l1; reg [31:0] crc_l2; reg [31:0] crc_l3; reg [31:0] crc_l4; reg [2:0] crc_valid_count; wire [31:0] checksum; wire [63:0] tx_data_out; wire [5:0] tx_ctrl_out; reg add_extra_qword; reg valid_extended; reg eop_extended; reg [2:0] empty_extended; // ____________________________________________________________________________ // number packet register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) number_packet <= 32'h0; else if (write & address == ADDR_NUMPKTS) number_packet <= writedata; end // ____________________________________________________________________________ // packet length setting register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) pkt_length <= 14'd0; else if (write & address == ADDR_PKTLENGTH) pkt_length[13:0] <= writedata[13:0]; end // ____________________________________________________________________________ // payload pattern setting register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) random_payload <= 1'h0; else if (write & address == ADDR_RANDOMPAYLOAD) random_payload <= writedata[0]; end // ____________________________________________________________________________ // packet length type (fixed or random) setting register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) random_length <= 1'h0; else if (write & address == ADDR_RANDOMLENGTH) random_length <= writedata[0]; end // ____________________________________________________________________________ // start register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) start_reg <= 1'h0; else if (write & address == ADDR_START) start_reg <= writedata[0]; else if (start_reg) start_reg <= 1'b0; // clear itself end // used for edge detection because start_reg[0] assertion maybe > 1 clk long reg start_d; always @ (posedge reset or posedge clk) begin if (reset) start_d<= 1'd0; else start_d<= start_reg; end assign start = start_reg & ~start_d; // ____________________________________________________________________________ // stop register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) stop <= 1'h0; else if (write & address == ADDR_STOP) stop <= writedata[0]; end // ____________________________________________________________________________ // MAC source_addr0 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) source_addr0 <= 32'h0; else if (write & address == ADDR_MACSA0) source_addr0 <= writedata; end // ____________________________________________________________________________ // MAC dest_addr1 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) source_addr1 <= 32'h0; else if (write & address == ADDR_MACSA1) source_addr1[15:0] <= writedata[15:0]; end // ____________________________________________________________________________ // MAC dest_addr0 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) destination_addr0 <= 32'h0; else if (write & address == ADDR_MACDA0) destination_addr0 <= writedata; end // ____________________________________________________________________________ // MAC dest_addr1 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) destination_addr1 <= 32'h0; else if (write & address == ADDR_MACDA1) destination_addr1[15:0] <= writedata[15:0]; end assign {DA5,DA4,DA3,DA2,DA1,DA0} = {destination_addr1[15:0], destination_addr0[31:0]}; assign {SA5,SA4,SA3,SA2,SA1,SA0} = {source_addr1[15:0], source_addr0[31:0]}; // ____________________________________________________________________________ // packet_tx_count register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin packet_tx_count <= 32'h0; end else begin if (start) begin packet_tx_count <= 32'h0; end else if (tx_ready & S_SRC_LEN_SEQ) begin packet_tx_count <= packet_tx_count + 32'h1; end end end // ____________________________________________________________________________ // rand_seed0 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin // rand_seed0 <= 32'h0; // initialize with non zero seed so that // prbs works even when no random seed is // provided by the user - ajay dubey rand_seed0 <= 32'h5EED_0000; end else begin if (write & address == ADDR_RNDSEED0) begin rand_seed0 <= writedata; end end end // ____________________________________________________________________________ // rand_seed1 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin // rand_seed1 <= 32'h0; // initialize with non zero seed so that // prbs works even when no random seed is // provided by the user - ajay dubey rand_seed1 <= 32'h5EED_0001; end else begin if (write & address == ADDR_RNDSEED1) begin rand_seed1 <= writedata; end end end // ____________________________________________________________________________ // rand_seed2 register // ____________________________________________________________________________ always @ (posedge reset or posedge clk) begin if (reset) begin //rand_seed2 <= 32'h0; // initialize with non zero seed so that // prbs works even when no random seed is // provided by the user - ajay dubey rand_seed2 <= 32'h0002_5EED; end else begin if (write & address == ADDR_RNDSEED2) begin rand_seed2[27:0] <= {5'd0,writedata[27:0]}; end end end assign random_seed = {rand_seed2[27:0], rand_seed1[31:0], rand_seed0[31:0]}; // Output MUX of registers into readdata bus always@(posedge clk or posedge reset) begin if(reset) readdata <= 32'h0; else if (read) begin case (address) ADDR_NUMPKTS: readdata <= number_packet; ADDR_RANDOMLENGTH: readdata <= random_length; ADDR_RANDOMPAYLOAD: readdata <= random_payload; ADDR_START: readdata <= start; ADDR_STOP: readdata <= stop; ADDR_MACSA0: readdata <= source_addr0; ADDR_MACSA1: readdata <= source_addr1; ADDR_MACDA0: readdata <= destination_addr0; ADDR_MACDA1: readdata <= destination_addr1; ADDR_TXPKTCNT: readdata <= packet_tx_count; ADDR_RNDSEED0: readdata <= rand_seed0; ADDR_RNDSEED1: readdata <= rand_seed1; ADDR_RNDSEED2: readdata <= rand_seed2; ADDR_CNTDASA: readdata <= cnt_dasa; ADDR_CNTSATLEN: readdata <= cnt_satlen; ADDR_CNTDATA: readdata <= cnt_data; ADDR_CNTTRNSTN: readdata <= cnt_trnstn; default: readdata <=32'h0; endcase end end // ____________________________________________________________ // reg rddly, wrdly; always@(posedge clk or posedge reset) begin if(reset) begin wrdly <= 1'b0; rddly <= 1'b0; end else begin wrdly <= write; rddly <= read; end end wire wredge = write& ~wrdly; wire rdedge = read & ~rddly; assign waitrequest = (wredge|rdedge); // your design is done with transaction when this goes down // __________________________________________________________________________________ // PRBS Pattern Generator // -------------------------------- prbs23 prbs_tx0 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)), .seed (random_seed[22:0]), .d (tx_prbs[22:0]), .m (tx_prbs[22:0]) ); prbs23 prbs_tx1 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)), .seed (random_seed[45:23]), .d (tx_prbs[45:23]), .m (tx_prbs[45:23]) ); prbs23 prbs_tx2 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)), .seed (random_seed[68:46]), .d (tx_prbs[68:46]), .m (tx_prbs[68:46]) ); prbs23 prbs_tx3 ( .clk (clk), .rst_n (~reset), .load (S_IDLE), .enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)), .seed (random_seed[91:69]), .d (tx_prbs[91:69]), .m (tx_prbs[91:69]) ); // FSM State Machine for Generator // -------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin ps <= state_idle; end else begin if (start) begin ps <= state_dest_src; end else begin ps <= ns; end end end always @ (*) begin ns = ps; case (ps) state_idle:begin if (start) begin ns = state_dest_src; end end state_dest_src:begin if (tx_ready) begin ns = state_src_len_seq; end end state_src_len_seq:begin if (tx_ready & (length == 16'h0)) begin ns = state_transition; end else if (tx_ready) begin ns = state_data; end end state_data:begin if (tx_ready & (byte_count[15] | byte_count == 16'h0)) begin ns = state_transition; end end state_transition:begin if (stop | packet_tx_count == number_packet) begin ns = state_idle; end else if (tx_ready) begin ns = state_dest_src; end end default: ns = state_idle; endcase end assign S_IDLE = (ns == state_idle) ? 1'b1 : 1'b0; assign S_DEST_SRC = (ns == state_dest_src) ? 1'b1 : 1'b0; assign S_SRC_LEN_SEQ = (ns == state_src_len_seq) ? 1'b1 : 1'b0; assign S_DATA = (ns == state_data) ? 1'b1 : 1'b0; assign S_TRANSITION = (ns == state_transition) ? 1'b1 : 1'b0; // Length is used to store the payload length size. Payload length smaller than 46 will have zeros data padded // Allowable fixed payload length: 6 -> 9582 // Allowable random payload length: 6 -> 1500 // -------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin length <= 16'h0; end else begin if (S_IDLE | S_TRANSITION) begin if (~random_length & (pkt_length < 14'h0018)) begin length <= 16'h0; end else if (~random_length & (pkt_length > 14'h2580)) begin length <= 16'h2568; end else if (~random_length) begin length <= {2'b00, pkt_length - 14'h18}; end else if (random_length) begin length <= (tx_prbs[74:64] % 16'h05D7); end end end end // Byte_count is used to keep track of how many bytes of data payload being generated out // -------------------------------------------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin byte_count <= 16'h0; end else begin if (S_DEST_SRC) begin byte_count <= length; end else if (S_DATA & tx_ready) begin byte_count <= byte_count - 16'h8; end end end // Seq_num is inserted into the first 2 bytes of data payload of every packet // --------------------------------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin seq_num <= 16'h0; end else begin if (start) begin seq_num <= 16'h0; end else if (S_TRANSITION & tx_ready) begin seq_num <= seq_num + 16'h1; end end end // Generation of incremental data or pseudo random data // ----------------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin data_pattern <= 64'h0; end else begin if (S_IDLE & ~random_payload) begin data_pattern <= 64'h0001020304050607; end else if (S_DATA & ~random_payload & tx_ready & data_pattern == 64'hF8F9FAFBFCFDFEFF) begin data_pattern <= 64'h0001020304050607; end else if (S_DATA & ~random_payload & tx_ready) begin data_pattern <= data_pattern + 64'h0808080808080808; end else if ((S_SRC_LEN_SEQ | S_DATA) & random_payload & tx_ready) begin data_pattern <= tx_prbs[63:0]; end end end // Avalon-ST tx_data interface to CRC generator // --------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_data_reg <= 64'h0; end else begin if (S_DEST_SRC) begin tx_data_reg[63:32] <= {DA5,DA4,DA3,DA2}; tx_data_reg[31: 0] <= {DA1,DA0,SA5,SA4}; end else if (S_SRC_LEN_SEQ) begin tx_data_reg[63:32] <= {SA3,SA2,SA1,SA0}; tx_data_reg[31: 0] <= {length + 16'h6, seq_num}; end else if (S_DATA & tx_ready) begin tx_data_reg <= data_pattern; end end end // Avalon-ST tx_valid interface to CRC generator // ---------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_valid_reg <= 1'b0; end else begin if (S_IDLE | S_TRANSITION) begin tx_valid_reg <= 1'b0; end else begin tx_valid_reg <= 1'b1; end end end // Avalon-ST tx_sop interface to CRC generator // -------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_sop_reg <= 1'b0; end else begin if (S_DEST_SRC) begin tx_sop_reg <= 1'b1; end else begin tx_sop_reg <= 1'b0; end end end // Avalon-ST tx_eop interface to CRC generator // -------------------------------------------- always @ (posedge reset or posedge clk) begin if (reset) begin tx_eop_reg <= 1'b0; end else begin if (S_SRC_LEN_SEQ & (length == 0)) begin tx_eop_reg <= 1'b1; end else if (S_DATA & tx_ready & (byte_count <= 8)) begin tx_eop_reg <= 1'b1; end else if (S_TRANSITION) begin tx_eop_reg <= 1'b0; end end end // Avalon-ST tx_empty interface to CRC generator // ---------------------------------------------- assign empty = 4'h8 - length[2:0]; always @ (posedge reset or posedge clk) begin if (reset) begin tx_empty_reg <= 3'b000; end else begin if (S_DATA & tx_ready & (byte_count <= 8)) begin tx_empty_reg <= empty[2:0]; end else if (S_TRANSITION) begin tx_empty_reg <= 3'b000; end end end // Using CRC Compiler to generate checksum and append it to EOP // ------------------------------------------------------------- /* crcgen crcgen_inst ( .clk (clk), .data (tx_data_reg), .datavalid (tx_valid_reg & tx_ready), .empty (tx_empty_reg), .endofpacket (tx_eop_reg), .reset_n (~reset), .startofpacket (tx_sop_reg), .checksum (crc), .crcvalid (crc_valid) ); */ // Using RAM based shift register to delay packet payload sending to TSE TX FIFO // interface for CRC checksum merging at EOP // ------------------------------------------------------------------------------- shiftreg_data shiftreg_data_inst ( .aclr (reset), .clken (tx_ready), .clock (clk), .shiftin (tx_data_reg), .shiftout (tx_data_out), .taps () ); // Using RAM based shift register to store and delay control signals // ------------------------------------------------------------------ shiftreg_ctrl shiftreg_ctrl_inst ( .aclr (reset), .clken (tx_ready), .clock (clk), .shiftin ({tx_valid_reg, tx_sop_reg, tx_eop_reg, tx_empty_reg}), .shiftout (tx_ctrl_out), .taps () ); always @ (posedge reset or posedge clk) begin if (reset) begin crc_valid_count <= 2'b00; end else begin crc_valid_count <= crc_valid_count + (crc_valid) - (tx_ready & tx_eop); end end always @ (posedge reset or posedge clk) begin if (reset) begin crc_l1 <= 32'h0; crc_l2 <= 32'h0; end else begin if (crc_valid) begin crc_l1 <= crc; crc_l2 <= crc_l1; crc_l3 <= crc_l2; crc_l4 <= crc_l3; end end end assign checksum = (crc_valid_count == 3'b001) ? crc_l1 : (crc_valid_count == 3'b010) ? crc_l2 : (crc_valid_count == 3'b011) ? crc_l3 : (crc_valid_count == 3'b100) ? crc_l4 : 32'h0; // Extend packet by one cycle when not enough // space in last word to add in checksum // ------------------------------------------- always @ (*) begin add_extra_qword <= 1'b0; if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop if (tx_ctrl_out[2] == 1'b0) begin // Less than 4 empty bytes add_extra_qword <= 1'b1; end end end always @ (posedge reset or posedge clk) begin if (reset) begin valid_extended <= 1'b0; eop_extended <= 1'b0; empty_extended <= 3'b000; end else begin if (tx_ready) begin if (add_extra_qword) begin valid_extended <= 1'b1; eop_extended <= 1'b1; empty_extended[2] <= 1'b1; empty_extended[1:0] <= tx_ctrl_out[1:0]; end else begin valid_extended <= 1'b0; eop_extended <= 1'b0; empty_extended[2] <= 1'b0; empty_extended[1:0] <= 3'b000; end end end end always @ (posedge reset or posedge clk) begin if (reset) begin tx_valid <= 1'b0; tx_sop <= 1'b0; tx_eop <= 1'b0; tx_empty <= 1'b0; end else begin if (tx_ready) begin tx_valid <= tx_ctrl_out[5] | valid_extended; end else begin //tx_valid <= 1'b0 ; tx_valid <= tx_valid ; // ajay: remain unchanged end if (tx_ready) begin //tx_valid <= tx_ctrl_out[5] | valid_extended; // ajay: unnecessary: already defined above tx_sop <= tx_ctrl_out[4]; if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop tx_eop <= !add_extra_qword; // keep original end else begin tx_eop <= eop_extended; end if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop if (add_extra_qword) begin tx_empty <= 3'b000; end else begin tx_empty <= tx_ctrl_out[2:0] - 3'h4; end end else begin tx_empty <= empty_extended[2:0]; end end end end always @ (posedge reset or posedge clk) begin if (reset) begin tx_data <= 64'h0; end else begin if (tx_ready) begin tx_data <= tx_data_out; // By default if (tx_ctrl_out[3]) begin // Normal EOP field case (tx_ctrl_out[2:0]) 3'b000: tx_data <= tx_data_out[63:0]; 3'b001: tx_data <= {tx_data_out[63:8], checksum[31:24]}; 3'b010: tx_data <= {tx_data_out[63:16], checksum[31:16]}; 3'b011: tx_data <= {tx_data_out[63:24], checksum[31: 8]}; 3'b100: tx_data <= {tx_data_out[63:32], checksum[31: 0]}; 3'b101: tx_data <= {tx_data_out[63:40], checksum[31: 0], 8'h0}; 3'b110: tx_data <= {tx_data_out[63:48], checksum[31: 0], 16'h0}; 3'b111: tx_data <= {tx_data_out[63:56], checksum[31: 0], 24'h0}; default: tx_data <= tx_data_out; endcase end else if (eop_extended) begin case (empty_extended) 3'b100: tx_data <= {checksum[31:0], 32'h0}; 3'b101: tx_data <= {checksum[23:0], 40'h0}; 3'b110: tx_data <= {checksum[15:0], 48'h0}; 3'b111: tx_data <= {checksum[ 7:0], 56'h0}; default: tx_data <= 64'h0; endcase end end end end assign tx_error = 1'b0; // ___________________________________________________________________________________________ // Debug Logic // ___________________________________________________________________________________________ reg ppln_dasa, ppln_satlen, ppln_data, ppln_trnstn; always @ (posedge reset or posedge clk) begin if (reset) begin ppln_dasa <= 1'b0; ppln_satlen <= 1'b0; ppln_data <= 1'b0; ppln_trnstn <= 1'b0; end else begin ppln_dasa <= S_DEST_SRC; ppln_satlen <= S_SRC_LEN_SEQ; ppln_data <= S_DATA; ppln_trnstn <= S_TRANSITION; end end wire ena_dasa = S_DEST_SRC & ~ppln_dasa; wire ena_satlen = S_SRC_LEN_SEQ & ~ppln_satlen; wire ena_data = S_DATA & ~ppln_data; wire ena_trnstn = S_TRANSITION & ~ppln_trnstn; always @ (posedge reset or posedge clk) begin if (reset) begin cnt_dasa <= 32'd0; cnt_satlen <= 32'd0; cnt_data <= 32'd0; cnt_trnstn <= 32'd0; end else begin if (ena_dasa) cnt_dasa <= cnt_dasa + 32'd1; if (ena_satlen) cnt_satlen <= cnt_satlen + 32'd1; if (ena_data) cnt_data <= cnt_data + 32'd1; if (ena_trnstn) cnt_trnstn <= cnt_trnstn + 32'd1; end end endmodule // ___________________________________________________________________________________________________ // PRBS23 GENERATOR // ___________________________________________________________________________________________________ //----------------------------------------------------------------------------- // Functional Description: // This module is the Pseudo-Random Bit Sequence 23 Block // where g(x) = x^23 + x^18 + x^0 // // use lsb of m 1st first // k can be > N, but part of the sequence will be skipped // //------------------------------------------------------------------------------- // // Copyright 2007 Altera Corporation. All rights reserved. Altera products are // protected under numerous U.S. and foreign patents, maskwork rights, copyrights and // other intellectual property laws. // This reference design file, and your use thereof, is subject to and governed by // the terms and conditions of the applicable Altera Reference Design License Agreement. // By using this reference design file, you indicate your acceptance of such terms and // conditions between you and Altera Corporation. In the event that you do not agree with // such terms and conditions, you may not use the reference design file. Please promptly // destroy any copies you have made. // // This reference design file being provided on an "as-is" basis and as an accommodation // and therefore all warranties, representations or guarantees of any kind // (whether express, implied or statutory) including, without limitation, warranties of // merchantability, non-infringement, or fitness for a particular purpose, are // specifically disclaimed. By making this reference design file available, Altera // expressly does not recommend, suggest or require that this reference design file be // used in combination with any other product not provided by Altera // turn off bogus verilog processor warnings // altera message_off 10034 10035 10036 10037 10230 module prbs23 ( clk, rst_n, load, enable, seed, d, m); parameter k = 23; //step value = a^k parameter N = 23; input clk; input rst_n; input load; input enable; input [N-1:0] seed; input [N-1:0] d; output [N-1:0] m; reg [N-1:0] m; reg [N-1:0] tmpa; reg [N-1:0] tmpb; integer i,j; always @ (d) begin tmpa = d; for (i=0; i<k; i=i+1) begin for (j=0; j<(N-1); j=j+1) begin tmpb[j] = tmpa[j+1]; end tmpb[N-1] = tmpa[18] ^ tmpa[0]; //x^23 + x[18] + x[0] tmpa = tmpb; end end always @(posedge clk or negedge rst_n) begin begin if (!rst_n) m <= 0; else if (load) m <= seed; else if (enable) m <= tmpb; end end endmodule

// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: bw_io_ddr_sig_bot.v // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ module bw_io_ddr_sig_bot(dram_io_drive_enable_o_l ,se_o_l ,cbd_o_l , cbu_o_l ,cbu_o_r ,cbd_o_r ,cbd_i_l ,cbu_i_r ,cbd_i_r ,vrefcode_i_l ,vrefcode_i_r ,serial_in ,afo ,serial_out ,ps_select_i_r ,afi , spare_ddr_data ,spare_ddr_pin ,test_mode_i_l ,testmode_l_i_r , test_mode_i_r ,bypass_enable_i_l ,bypass_enable_i_r ,ps_select_i_l ,update_dr_o_l ,shift_dr_o_l ,clock_dr_o_l ,hiz_n_o_l , bypass_enable_o_l ,ps_select_o_r ,mode_ctrl_o_r ,update_dr_o_r , se_i_r ,mode_ctrl_i_r ,clock_dr_i_r ,mode_ctrl_o_l ,hiz_n_i_r , update_dr_i_r ,cbu_i_l ,shift_dr_o_r ,dram_io_drive_enable_i_r , clock_dr_o_r ,hiz_n_o_r ,ps_select_o_l ,rclk ,testmode_l_i_l , dram_io_ptr_clk_inv_i_l ,burst_length_four_i_l , dram_io_pad_enable_i_l ,dram_io_drive_enable_i_l ,rst_l_i_l , arst_l_i_l, arst_l_out, lpf_code_i_l ,strobe_i_l ,pad_pos_cnt_i_l , dram_io_channel_disabled_i_l ,pad_neg_cnt_i_l , dram_io_drive_data_i_l ,dram_io_channel_disabled_i_r , dram_io_write_en_l ,\dram_io_data_out[63] ,\dram_io_data_out[62] , \dram_io_data_out[61] ,\dram_io_data_out[60] ,\dram_io_data_out[59] ,\dram_io_data_out[58] ,\dram_io_data_out[57] , \dram_io_data_out[56] ,\dram_io_data_out[55] ,\dram_io_data_out[54] ,\dram_io_data_out[53] ,\dram_io_data_out[52] , \dram_io_data_out[51] ,\dram_io_data_out[50] ,\dram_io_data_out[49] ,\dram_io_data_out[48] ,\dram_io_data_out[47] , \dram_io_data_out[46] ,\dram_io_data_out[45] ,\dram_io_data_out[44] ,\dram_io_data_out[43] ,\dram_io_data_out[42] , \dram_io_data_out[41] ,\dram_io_data_out[40] ,\dram_io_data_out[39] ,\dram_io_data_out[38] ,\dram_io_data_out[37] , \dram_io_data_out[36] ,\dram_io_data_out[35] ,\dram_io_data_out[34] ,\dram_io_data_out[33] ,\dram_io_data_out[32] , \io_dram_data_in[255] ,\io_dram_data_in[254] ,\io_dram_data_in[253] ,\io_dram_data_in[252] ,\io_dram_data_in[251] , \io_dram_data_in[250] ,\io_dram_data_in[249] ,\io_dram_data_in[248] ,\io_dram_data_in[247] ,\io_dram_data_in[246] , \io_dram_data_in[245] ,\io_dram_data_in[244] ,\io_dram_data_in[243] ,\io_dram_data_in[242] ,\io_dram_data_in[241] , \io_dram_data_in[240] ,\io_dram_data_in[239] ,\io_dram_data_in[238] ,\io_dram_data_in[237] ,\io_dram_data_in[236] , \io_dram_data_in[235] ,\io_dram_data_in[234] ,\io_dram_data_in[233] ,\io_dram_data_in[232] ,\io_dram_data_in[231] , \io_dram_data_in[230] ,\io_dram_data_in[229] ,\io_dram_data_in[228] ,\io_dram_data_in[227] ,\io_dram_data_in[226] , \io_dram_data_in[225] ,\io_dram_data_in[224] ,dram_io_cas_l , dram_cs_l ,dram_we_l ,dram_cas_l ,\dram_dq[127] ,\dram_dq[126] , \dram_dq[125] ,\dram_dq[124] ,\dram_dq[123] ,\dram_dq[122] , \dram_dq[121] ,\dram_dq[120] ,\dram_dq[119] ,\dram_dq[118] , \dram_dq[117] ,\dram_dq[116] ,\dram_dq[115] ,\dram_dq[114] , \dram_dq[113] ,\dram_dq[112] ,\dram_dq[111] ,\dram_dq[110] , \dram_dq[109] ,\dram_dq[108] ,\dram_dq[107] ,\dram_dq[106] , \dram_dq[105] ,\dram_dq[104] ,\dram_dq[103] ,\dram_dq[102] , \dram_dq[101] ,\dram_dq[100] ,\dram_dq[99] ,\dram_dq[98] , \dram_dq[97] ,\dram_dq[96] ,\dram_io_data_out[287] , \dram_io_data_out[286] ,\dram_io_data_out[285] , \dram_io_data_out[284] ,\dram_io_data_out[283] , \dram_io_data_out[282] ,\dram_io_data_out[281] , \dram_io_data_out[280] ,\dram_io_data_out[143] , \dram_io_data_out[142] ,\dram_io_data_out[141] , \dram_io_data_out[140] ,\dram_io_data_out[139] , \dram_io_data_out[138] ,\dram_io_data_out[137] , \dram_io_data_out[136] ,\io_dram_ecc_in[31] ,\io_dram_ecc_in[30] , \io_dram_ecc_in[29] ,\io_dram_ecc_in[28] ,\io_dram_ecc_in[27] , \io_dram_ecc_in[26] ,\io_dram_ecc_in[25] ,\io_dram_ecc_in[24] , \io_dram_ecc_in[15] ,\io_dram_ecc_in[14] ,\io_dram_ecc_in[13] , \io_dram_ecc_in[12] ,\io_dram_ecc_in[11] ,\io_dram_ecc_in[10] , \io_dram_ecc_in[9] ,\io_dram_ecc_in[8] ,dram_cb , \dram_io_data_out[127] ,\dram_io_data_out[126] , \dram_io_data_out[125] ,\dram_io_data_out[124] , \dram_io_data_out[123] ,\dram_io_data_out[122] , \dram_io_data_out[121] ,\dram_io_data_out[120] , \dram_io_data_out[119] ,\dram_io_data_out[118] , \dram_io_data_out[117] ,\dram_io_data_out[116] , \dram_io_data_out[115] ,\dram_io_data_out[114] , \dram_io_data_out[113] ,\dram_io_data_out[112] , \dram_io_data_out[111] ,\dram_io_data_out[110] , \dram_io_data_out[109] ,\dram_io_data_out[108] , \dram_io_data_out[107] ,\dram_io_data_out[106] , \dram_io_data_out[105] ,\dram_io_data_out[104] , \dram_io_data_out[103] ,\dram_io_data_out[102] , \dram_io_data_out[101] ,\dram_io_data_out[100] , \dram_io_data_out[99] ,\dram_io_data_out[98] ,\dram_io_data_out[97] ,\dram_io_data_out[96] ,pad_neg_cnt_i_r ,\io_dram_data_in[191] , \io_dram_data_in[190] ,\io_dram_data_in[189] ,\io_dram_data_in[188] ,\io_dram_data_in[187] ,\io_dram_data_in[186] , \io_dram_data_in[185] ,\io_dram_data_in[184] ,\io_dram_data_in[183] ,\io_dram_data_in[182] ,\io_dram_data_in[181] , \io_dram_data_in[180] ,\io_dram_data_in[179] ,\io_dram_data_in[178] ,\io_dram_data_in[177] ,\io_dram_data_in[176] , \io_dram_data_in[175] ,\io_dram_data_in[174] ,\io_dram_data_in[173] ,\io_dram_data_in[172] ,\io_dram_data_in[171] , \io_dram_data_in[170] ,\io_dram_data_in[169] ,\io_dram_data_in[168] ,\io_dram_data_in[167] ,\io_dram_data_in[166] , \io_dram_data_in[165] ,\io_dram_data_in[164] ,\io_dram_data_in[163] ,\io_dram_data_in[162] ,\io_dram_data_in[161] , \io_dram_data_in[160] ,rst_l_i_r , arst_l_i_r, \io_dram_data_in[127] , \io_dram_data_in[126] ,\io_dram_data_in[125] ,\io_dram_data_in[124] ,\io_dram_data_in[123] ,\io_dram_data_in[122] , \io_dram_data_in[121] ,\io_dram_data_in[120] ,\io_dram_data_in[119] ,\io_dram_data_in[118] ,\io_dram_data_in[117] , \io_dram_data_in[116] ,\io_dram_data_in[115] ,\io_dram_data_in[114] ,\io_dram_data_in[113] ,\io_dram_data_in[112] , \io_dram_data_in[111] ,\io_dram_data_in[110] ,\io_dram_data_in[109] ,\io_dram_data_in[108] ,\io_dram_data_in[107] , \io_dram_data_in[106] ,\io_dram_data_in[105] ,\io_dram_data_in[104] ,\io_dram_data_in[103] ,\io_dram_data_in[102] , \io_dram_data_in[101] ,\io_dram_data_in[100] ,\io_dram_data_in[99] ,\io_dram_data_in[98] ,\io_dram_data_in[97] ,\io_dram_data_in[96] ,pad_clk_si ,dram_ras_l ,dram_io_pad_enable_i_r , \dram_io_data_out[271] ,\dram_io_data_out[270] , \dram_io_data_out[269] ,\dram_io_data_out[268] , \dram_io_data_out[267] ,\dram_io_data_out[266] , \dram_io_data_out[265] ,\dram_io_data_out[264] , \dram_io_data_out[263] ,\dram_io_data_out[262] , \dram_io_data_out[261] ,\dram_io_data_out[260] , \dram_io_data_out[259] ,\dram_io_data_out[258] , \dram_io_data_out[257] ,\dram_io_data_out[256] , \dram_io_data_out[255] ,\dram_io_data_out[254] , \dram_io_data_out[253] ,\dram_io_data_out[252] , \dram_io_data_out[251] ,\dram_io_data_out[250] , \dram_io_data_out[249] ,\dram_io_data_out[248] , \dram_io_data_out[247] ,\dram_io_data_out[246] , \dram_io_data_out[245] ,\dram_io_data_out[244] , \dram_io_data_out[243] ,\dram_io_data_out[242] , \dram_io_data_out[241] ,\dram_io_data_out[240] ,mode_ctrl_i_l , \dram_dqs[7] ,\dram_dqs[6] ,\dram_dqs[5] ,\dram_dqs[4] ,bsi ,bso , dram_io_bank ,dram_addr ,burst_length_four_i_r ,lpf_code_i_r , strobe_i_r ,update_dr_i_l ,hiz_n_i_l ,clock_dr_i_l ,shift_dr_i_l , se_i_l ,pad_clk_so ,dram_io_ptr_clk_inv_i_r ,dram_io_ras_l , dram_io_cs_l ,dram_ba ,\dram_dq[63] ,\dram_dq[62] ,\dram_dq[61] , \dram_dq[60] ,\dram_dq[59] ,\dram_dq[58] ,\dram_dq[57] , \dram_dq[56] ,\dram_dq[55] ,\dram_dq[54] ,\dram_dq[53] , \dram_dq[52] ,\dram_dq[51] ,\dram_dq[50] ,\dram_dq[49] , \dram_dq[48] ,\dram_dq[47] ,\dram_dq[46] ,\dram_dq[45] , \dram_dq[44] ,\dram_dq[43] ,\dram_dq[42] ,\dram_dq[41] , \dram_dq[40] ,\dram_dq[39] ,\dram_dq[38] ,\dram_dq[37] , \dram_dq[36] ,\dram_dq[35] ,\dram_dq[34] ,\dram_dq[33] , \dram_dq[32] ,\dram_dqs[35] ,\dram_dqs[34] ,\dram_dqs[33] , \dram_dqs[32] ,\dram_dqs[31] ,dram_io_addr ,\dram_dqs[16] , \dram_dqs[15] ,\dram_dqs[14] ,\dram_dqs[13] ,\dram_dqs[26] , \dram_dqs[25] ,\dram_dqs[24] ,\dram_dqs[23] ,\dram_dqs[22] , pad_pos_cnt_i_r ,dram_io_drive_data_i_r ,shift_dr_i_r , bypass_enable_o_r ,vdd_h ,\io_dram_data_in[63] , \io_dram_data_in[62] ,\io_dram_data_in[61] ,\io_dram_data_in[60] , \io_dram_data_in[59] ,\io_dram_data_in[58] ,\io_dram_data_in[57] , \io_dram_data_in[56] ,\io_dram_data_in[55] ,\io_dram_data_in[54] , \io_dram_data_in[53] ,\io_dram_data_in[52] ,\io_dram_data_in[51] , \io_dram_data_in[50] ,\io_dram_data_in[49] ,\io_dram_data_in[48] , \io_dram_data_in[47] ,\io_dram_data_in[46] ,\io_dram_data_in[45] , \io_dram_data_in[44] ,\io_dram_data_in[43] ,\io_dram_data_in[42] , \io_dram_data_in[41] ,\io_dram_data_in[40] ,\io_dram_data_in[39] , \io_dram_data_in[38] ,\io_dram_data_in[37] ,\io_dram_data_in[36] , \io_dram_data_in[35] ,\io_dram_data_in[34] ,\io_dram_data_in[33] , \io_dram_data_in[32] ,\dram_io_data_out[207] , \dram_io_data_out[206] ,\dram_io_data_out[205] , \dram_io_data_out[204] ,\dram_io_data_out[203] , \dram_io_data_out[202] ,\dram_io_data_out[201] , \dram_io_data_out[200] ,\dram_io_data_out[199] , \dram_io_data_out[198] ,\dram_io_data_out[197] , \dram_io_data_out[196] ,\dram_io_data_out[195] , \dram_io_data_out[194] ,\dram_io_data_out[193] , \dram_io_data_out[192] ,\dram_io_data_out[191] , \dram_io_data_out[190] ,\dram_io_data_out[189] , \dram_io_data_out[188] ,\dram_io_data_out[187] , \dram_io_data_out[186] ,\dram_io_data_out[185] , \dram_io_data_out[184] ,\dram_io_data_out[183] , \dram_io_data_out[182] ,\dram_io_data_out[181] , \dram_io_data_out[180] ,\dram_io_data_out[179] , \dram_io_data_out[178] ,\dram_io_data_out[177] , \dram_io_data_out[176] ); output arst_l_out ; output [8:1] cbd_o_l ; output [8:1] cbu_o_l ; output [8:1] cbu_o_r ; output [8:1] cbd_o_r ; output [143:72] serial_out ; output [143:72] afi ; input [8:1] cbd_i_l ; input [8:1] cbu_i_r ; input [8:1] cbd_i_r ; input [7:0] vrefcode_i_l ; input [7:0] vrefcode_i_r ; input [143:72] serial_in ; input [143:72] afo ; input [7:0] spare_ddr_data ; input [8:1] cbu_i_l ; input [1:0] dram_io_ptr_clk_inv_i_l ; input [4:0] lpf_code_i_l ; input [1:0] pad_pos_cnt_i_l ; input [1:0] pad_neg_cnt_i_l ; input [1:0] pad_neg_cnt_i_r ; input [1:0] dram_io_bank ; input [4:0] lpf_code_i_r ; input [1:0] dram_io_ptr_clk_inv_i_r ; input [3:0] dram_io_cs_l ; input [10:10] dram_io_addr ; input [1:0] pad_pos_cnt_i_r ; inout [7:0] spare_ddr_pin ; inout [3:0] dram_cs_l ; inout [15:8] dram_cb ; inout [10:10] dram_addr ; inout [1:0] dram_ba ; output dram_io_drive_enable_o_l ; output se_o_l ; output update_dr_o_l ; output shift_dr_o_l ; output clock_dr_o_l ; output hiz_n_o_l ; output bypass_enable_o_l ; output ps_select_o_r ; output mode_ctrl_o_r ; output update_dr_o_r ; output mode_ctrl_o_l ; output shift_dr_o_r ; output clock_dr_o_r ; output hiz_n_o_r ; output ps_select_o_l ; output \io_dram_data_in[255] ; output \io_dram_data_in[254] ; output \io_dram_data_in[253] ; output \io_dram_data_in[252] ; output \io_dram_data_in[251] ; output \io_dram_data_in[250] ; output \io_dram_data_in[249] ; output \io_dram_data_in[248] ; output \io_dram_data_in[247] ; output \io_dram_data_in[246] ; output \io_dram_data_in[245] ; output \io_dram_data_in[244] ; output \io_dram_data_in[243] ; output \io_dram_data_in[242] ; output \io_dram_data_in[241] ; output \io_dram_data_in[240] ; output \io_dram_data_in[239] ; output \io_dram_data_in[238] ; output \io_dram_data_in[237] ; output \io_dram_data_in[236] ; output \io_dram_data_in[235] ; output \io_dram_data_in[234] ; output \io_dram_data_in[233] ; output \io_dram_data_in[232] ; output \io_dram_data_in[231] ; output \io_dram_data_in[230] ; output \io_dram_data_in[229] ; output \io_dram_data_in[228] ; output \io_dram_data_in[227] ; output \io_dram_data_in[226] ; output \io_dram_data_in[225] ; output \io_dram_data_in[224] ; output \io_dram_ecc_in[31] ; output \io_dram_ecc_in[30] ; output \io_dram_ecc_in[29] ; output \io_dram_ecc_in[28] ; output \io_dram_ecc_in[27] ; output \io_dram_ecc_in[26] ; output \io_dram_ecc_in[25] ; output \io_dram_ecc_in[24] ; output \io_dram_ecc_in[15] ; output \io_dram_ecc_in[14] ; output \io_dram_ecc_in[13] ; output \io_dram_ecc_in[12] ; output \io_dram_ecc_in[11] ; output \io_dram_ecc_in[10] ; output \io_dram_ecc_in[9] ; output \io_dram_ecc_in[8] ; output \io_dram_data_in[191] ; output \io_dram_data_in[190] ; output \io_dram_data_in[189] ; output \io_dram_data_in[188] ; output \io_dram_data_in[187] ; output \io_dram_data_in[186] ; output \io_dram_data_in[185] ; output \io_dram_data_in[184] ; output \io_dram_data_in[183] ; output \io_dram_data_in[182] ; output \io_dram_data_in[181] ; output \io_dram_data_in[180] ; output \io_dram_data_in[179] ; output \io_dram_data_in[178] ; output \io_dram_data_in[177] ; output \io_dram_data_in[176] ; output \io_dram_data_in[175] ; output \io_dram_data_in[174] ; output \io_dram_data_in[173] ; output \io_dram_data_in[172] ; output \io_dram_data_in[171] ; output \io_dram_data_in[170] ; output \io_dram_data_in[169] ; output \io_dram_data_in[168] ; output \io_dram_data_in[167] ; output \io_dram_data_in[166] ; output \io_dram_data_in[165] ; output \io_dram_data_in[164] ; output \io_dram_data_in[163] ; output \io_dram_data_in[162] ; output \io_dram_data_in[161] ; output \io_dram_data_in[160] ; output \io_dram_data_in[127] ; output \io_dram_data_in[126] ; output \io_dram_data_in[125] ; output \io_dram_data_in[124] ; output \io_dram_data_in[123] ; output \io_dram_data_in[122] ; output \io_dram_data_in[121] ; output \io_dram_data_in[120] ; output \io_dram_data_in[119] ; output \io_dram_data_in[118] ; output \io_dram_data_in[117] ; output \io_dram_data_in[116] ; output \io_dram_data_in[115] ; output \io_dram_data_in[114] ; output \io_dram_data_in[113] ; output \io_dram_data_in[112] ; output \io_dram_data_in[111] ; output \io_dram_data_in[110] ; output \io_dram_data_in[109] ; output \io_dram_data_in[108] ; output \io_dram_data_in[107] ; output \io_dram_data_in[106] ; output \io_dram_data_in[105] ; output \io_dram_data_in[104] ; output \io_dram_data_in[103] ; output \io_dram_data_in[102] ; output \io_dram_data_in[101] ; output \io_dram_data_in[100] ; output \io_dram_data_in[99] ; output \io_dram_data_in[98] ; output \io_dram_data_in[97] ; output \io_dram_data_in[96] ; output bso ; output pad_clk_so ; output bypass_enable_o_r ; output \io_dram_data_in[63] ; output \io_dram_data_in[62] ; output \io_dram_data_in[61] ; output \io_dram_data_in[60] ; output \io_dram_data_in[59] ; output \io_dram_data_in[58] ; output \io_dram_data_in[57] ; output \io_dram_data_in[56] ; output \io_dram_data_in[55] ; output \io_dram_data_in[54] ; output \io_dram_data_in[53] ; output \io_dram_data_in[52] ; output \io_dram_data_in[51] ; output \io_dram_data_in[50] ; output \io_dram_data_in[49] ; output \io_dram_data_in[48] ; output \io_dram_data_in[47] ; output \io_dram_data_in[46] ; output \io_dram_data_in[45] ; output \io_dram_data_in[44] ; output \io_dram_data_in[43] ; output \io_dram_data_in[42] ; output \io_dram_data_in[41] ; output \io_dram_data_in[40] ; output \io_dram_data_in[39] ; output \io_dram_data_in[38] ; output \io_dram_data_in[37] ; output \io_dram_data_in[36] ; output \io_dram_data_in[35] ; output \io_dram_data_in[34] ; output \io_dram_data_in[33] ; output \io_dram_data_in[32] ; input ps_select_i_r ; input test_mode_i_l ; input testmode_l_i_r ; input test_mode_i_r ; input bypass_enable_i_l ; input bypass_enable_i_r ; input ps_select_i_l ; input se_i_r ; input mode_ctrl_i_r ; input clock_dr_i_r ; input hiz_n_i_r ; input update_dr_i_r ; input dram_io_drive_enable_i_r ; input rclk ; input testmode_l_i_l ; input burst_length_four_i_l ; input dram_io_pad_enable_i_l ; input dram_io_drive_enable_i_l ; input rst_l_i_l ; input arst_l_i_l ; input strobe_i_l ; input dram_io_channel_disabled_i_l ; input dram_io_drive_data_i_l ; input dram_io_channel_disabled_i_r ; input dram_io_write_en_l ; input \dram_io_data_out[63] ; input \dram_io_data_out[62] ; input \dram_io_data_out[61] ; input \dram_io_data_out[60] ; input \dram_io_data_out[59] ; input \dram_io_data_out[58] ; input \dram_io_data_out[57] ; input \dram_io_data_out[56] ; input \dram_io_data_out[55] ; input \dram_io_data_out[54] ; input \dram_io_data_out[53] ; input \dram_io_data_out[52] ; input \dram_io_data_out[51] ; input \dram_io_data_out[50] ; input \dram_io_data_out[49] ; input \dram_io_data_out[48] ; input \dram_io_data_out[47] ; input \dram_io_data_out[46] ; input \dram_io_data_out[45] ; input \dram_io_data_out[44] ; input \dram_io_data_out[43] ; input \dram_io_data_out[42] ; input \dram_io_data_out[41] ; input \dram_io_data_out[40] ; input \dram_io_data_out[39] ; input \dram_io_data_out[38] ; input \dram_io_data_out[37] ; input \dram_io_data_out[36] ; input \dram_io_data_out[35] ; input \dram_io_data_out[34] ; input \dram_io_data_out[33] ; input \dram_io_data_out[32] ; input dram_io_cas_l ; input \dram_io_data_out[287] ; input \dram_io_data_out[286] ; input \dram_io_data_out[285] ; input \dram_io_data_out[284] ; input \dram_io_data_out[283] ; input \dram_io_data_out[282] ; input \dram_io_data_out[281] ; input \dram_io_data_out[280] ; input \dram_io_data_out[143] ; input \dram_io_data_out[142] ; input \dram_io_data_out[141] ; input \dram_io_data_out[140] ; input \dram_io_data_out[139] ; input \dram_io_data_out[138] ; input \dram_io_data_out[137] ; input \dram_io_data_out[136] ; input \dram_io_data_out[127] ; input \dram_io_data_out[126] ; input \dram_io_data_out[125] ; input \dram_io_data_out[124] ; input \dram_io_data_out[123] ; input \dram_io_data_out[122] ; input \dram_io_data_out[121] ; input \dram_io_data_out[120] ; input \dram_io_data_out[119] ; input \dram_io_data_out[118] ; input \dram_io_data_out[117] ; input \dram_io_data_out[116] ; input \dram_io_data_out[115] ; input \dram_io_data_out[114] ; input \dram_io_data_out[113] ; input \dram_io_data_out[112] ; input \dram_io_data_out[111] ; input \dram_io_data_out[110] ; input \dram_io_data_out[109] ; input \dram_io_data_out[108] ; input \dram_io_data_out[107] ; input \dram_io_data_out[106] ; input \dram_io_data_out[105] ; input \dram_io_data_out[104] ; input \dram_io_data_out[103] ; input \dram_io_data_out[102] ; input \dram_io_data_out[101] ; input \dram_io_data_out[100] ; input \dram_io_data_out[99] ; input \dram_io_data_out[98] ; input \dram_io_data_out[97] ; input \dram_io_data_out[96] ; input rst_l_i_r ; input arst_l_i_r ; input pad_clk_si ; input dram_io_pad_enable_i_r ; input \dram_io_data_out[271] ; input \dram_io_data_out[270] ; input \dram_io_data_out[269] ; input \dram_io_data_out[268] ; input \dram_io_data_out[267] ; input \dram_io_data_out[266] ; input \dram_io_data_out[265] ; input \dram_io_data_out[264] ; input \dram_io_data_out[263] ; input \dram_io_data_out[262] ; input \dram_io_data_out[261] ; input \dram_io_data_out[260] ; input \dram_io_data_out[259] ; input \dram_io_data_out[258] ; input \dram_io_data_out[257] ; input \dram_io_data_out[256] ; input \dram_io_data_out[255] ; input \dram_io_data_out[254] ; input \dram_io_data_out[253] ; input \dram_io_data_out[252] ; input \dram_io_data_out[251] ; input \dram_io_data_out[250] ; input \dram_io_data_out[249] ; input \dram_io_data_out[248] ; input \dram_io_data_out[247] ; input \dram_io_data_out[246] ; input \dram_io_data_out[245] ; input \dram_io_data_out[244] ; input \dram_io_data_out[243] ; input \dram_io_data_out[242] ; input \dram_io_data_out[241] ; input \dram_io_data_out[240] ; input mode_ctrl_i_l ; input bsi ; input burst_length_four_i_r ; input strobe_i_r ; input update_dr_i_l ; input hiz_n_i_l ; input clock_dr_i_l ; input shift_dr_i_l ; input se_i_l ; input dram_io_ras_l ; input dram_io_drive_data_i_r ; input shift_dr_i_r ; input vdd_h ; input \dram_io_data_out[207] ; input \dram_io_data_out[206] ; input \dram_io_data_out[205] ; input \dram_io_data_out[204] ; input \dram_io_data_out[203] ; input \dram_io_data_out[202] ; input \dram_io_data_out[201] ; input \dram_io_data_out[200] ; input \dram_io_data_out[199] ; input \dram_io_data_out[198] ; input \dram_io_data_out[197] ; input \dram_io_data_out[196] ; input \dram_io_data_out[195] ; input \dram_io_data_out[194] ; input \dram_io_data_out[193] ; input \dram_io_data_out[192] ; input \dram_io_data_out[191] ; input \dram_io_data_out[190] ; input \dram_io_data_out[189] ; input \dram_io_data_out[188] ; input \dram_io_data_out[187] ; input \dram_io_data_out[186] ; input \dram_io_data_out[185] ; input \dram_io_data_out[184] ; input \dram_io_data_out[183] ; input \dram_io_data_out[182] ; input \dram_io_data_out[181] ; input \dram_io_data_out[180] ; input \dram_io_data_out[179] ; input \dram_io_data_out[178] ; input \dram_io_data_out[177] ; input \dram_io_data_out[176] ; inout dram_we_l ; inout dram_cas_l ; inout \dram_dq[127] ; inout \dram_dq[126] ; inout \dram_dq[125] ; inout \dram_dq[124] ; inout \dram_dq[123] ; inout \dram_dq[122] ; inout \dram_dq[121] ; inout \dram_dq[120] ; inout \dram_dq[119] ; inout \dram_dq[118] ; inout \dram_dq[117] ; inout \dram_dq[116] ; inout \dram_dq[115] ; inout \dram_dq[114] ; inout \dram_dq[113] ; inout \dram_dq[112] ; inout \dram_dq[111] ; inout \dram_dq[110] ; inout \dram_dq[109] ; inout \dram_dq[108] ; inout \dram_dq[107] ; inout \dram_dq[106] ; inout \dram_dq[105] ; inout \dram_dq[104] ; inout \dram_dq[103] ; inout \dram_dq[102] ; inout \dram_dq[101] ; inout \dram_dq[100] ; inout \dram_dq[99] ; inout \dram_dq[98] ; inout \dram_dq[97] ; inout \dram_dq[96] ; inout dram_ras_l ; inout \dram_dqs[7] ; inout \dram_dqs[6] ; inout \dram_dqs[5] ; inout \dram_dqs[4] ; inout \dram_dq[63] ; inout \dram_dq[62] ; inout \dram_dq[61] ; inout \dram_dq[60] ; inout \dram_dq[59] ; inout \dram_dq[58] ; inout \dram_dq[57] ; inout \dram_dq[56] ; inout \dram_dq[55] ; inout \dram_dq[54] ; inout \dram_dq[53] ; inout \dram_dq[52] ; inout \dram_dq[51] ; inout \dram_dq[50] ; inout \dram_dq[49] ; inout \dram_dq[48] ; inout \dram_dq[47] ; inout \dram_dq[46] ; inout \dram_dq[45] ; inout \dram_dq[44] ; inout \dram_dq[43] ; inout \dram_dq[42] ; inout \dram_dq[41] ; inout \dram_dq[40] ; inout \dram_dq[39] ; inout \dram_dq[38] ; inout \dram_dq[37] ; inout \dram_dq[36] ; inout \dram_dq[35] ; inout \dram_dq[34] ; inout \dram_dq[33] ; inout \dram_dq[32] ; inout \dram_dqs[35] ; inout \dram_dqs[34] ; inout \dram_dqs[33] ; inout \dram_dqs[32] ; inout \dram_dqs[31] ; inout \dram_dqs[16] ; inout \dram_dqs[15] ; inout \dram_dqs[14] ; inout \dram_dqs[13] ; inout \dram_dqs[26] ; inout \dram_dqs[25] ; inout \dram_dqs[24] ; inout \dram_dqs[23] ; inout \dram_dqs[22] ; wire [7:0] net0601 ; wire [7:0] net0324 ; wire [7:0] net0742 ; wire [7:0] net1106 ; wire [7:0] net0643 ; wire [1:0] net1118 ; wire [7:0] net0648 ; wire [7:0] net1290 ; wire [7:0] net997 ; wire [7:0] net857 ; wire [7:0] net856 ; wire [7:0] net0644 ; wire [7:0] net0945 ; wire [1:0] net1016 ; wire [7:0] net0845 ; wire [7:0] net0691 ; wire [1:0] net0373 ; wire [1:0] net0557 ; wire [7:0] net0844 ; wire [1:0] net0402 ; wire [7:0] net0699 ; wire [7:0] net1167 ; wire [7:0] net1122 ; wire [1:0] net1163 ; wire [7:0] net872 ; wire [1:0] net863 ; wire [7:0] net0895 ; wire [4:0] net0390 ; wire [4:0] net0565 ; wire [4:0] net1277 ; wire [7:0] net981 ; wire [4:0] net1007 ; wire [7:0] net1042 ; wire [4:0] net0399 ; wire [7:0] net1107 ; wire [7:0] net1145 ; wire [7:0] net0974 ; wire [7:0] net0602 ; wire [1:0] net0509 ; wire [1:0] net0558 ; wire [4:0] net1155 ; wire [4:0] net0517 ; wire [1:0] net868 ; wire [1:0] net0407 ; wire [1:0] net966 ; wire [1:0] net1286 ; wire [1:0] net1158 ; wire [1:0] net1164 ; wire [4:0] net1029 ; wire [1:0] net1038 ; wire [1:0] net1136 ; wire [4:0] net1103 ; wire [1:0] net1097 ; wire [1:0] net0371 ; wire [1:0] net0381 ; wire [1:0] net0408 ; wire [4:0] net977 ; wire [1:0] net1090 ; wire [1:0] net848 ; wire [1:0] net1015 ; wire [1:0] net0562 ; wire [1:0] net964 ; wire [1:0] net1280 ; wire [1:0] net0510 ; wire [1:0] net0514 ; wire [1:0] net1264 ; wire net875 ; wire net973 ; wire net1291 ; wire net1096 ; wire net0370 ; wire net1115 ; wire net974 ; wire net1017 ; wire net1293 ; wire net0372 ; wire net1294 ; wire net879 ; wire net0374 ; wire net1296 ; wire net0552 ; wire net0377 ; wire net0555 ; wire net0556 ; wire net1121 ; wire net1023 ; wire net0559 ; wire net982 ; wire net1025 ; wire net983 ; wire net1125 ; wire net1027 ; wire net1028 ; wire net0400 ; wire net0401 ; wire net1128 ; wire net0560 ; wire net0403 ; wire net0404 ; wire net0561 ; wire net0386 ; wire net0387 ; wire net0406 ; wire net0563 ; wire net0388 ; wire net0564 ; wire net0389 ; wire net0409 ; wire net0566 ; wire net1171 ; wire net991 ; wire net1270 ; wire net1271 ; wire net994 ; wire net1272 ; wire net1273 ; wire net1274 ; wire net1275 ; wire net999 ; wire net1278 ; wire net1279 ; wire net0831 ; wire net1001 ; wire net0832 ; wire net1100 ; wire net1002 ; wire net0735 ; wire bso0_bsi1 ; wire net1101 ; wire net1003 ; wire net0736 ; wire net0639 ; wire net1004 ; wire bso2_bsi3 ; wire net1104 ; wire net1281 ; wire net1006 ; wire net1008 ; wire net1284 ; wire net1089 ; wire net0640 ; wire net1287 ; wire net0543 ; wire net0544 ; wire net0368 ; wire net0369 ; wire net1150 ; wire net1151 ; wire net1154 ; wire net1254 ; wire net837 ; wire net1156 ; wire net0511 ; wire net1157 ; wire net0512 ; wire net0591 ; wire net839 ; wire net1159 ; wire net0513 ; wire net1257 ; wire net0592 ; wire net0515 ; wire pad_clk_so1_si2 ; wire net1259 ; wire net0516 ; wire net0518 ; wire pad_clk_so2_si3 ; wire net1160 ; wire net843 ; wire net1260 ; wire net844 ; wire net846 ; wire net847 ; wire net1166 ; wire pad_clk_so0_si1 ; wire net1266 ; wire net1169 ; wire net1030 ; wire net850 ; wire net1130 ; wire net1033 ; wire net852 ; wire net1036 ; wire net1134 ; wire net0410 ; wire pad_clk_so3_si4 ; wire net1137 ; wire net858 ; wire net0393 ; wire net0413 ; wire net0394 ; wire net0414 ; wire net0415 ; wire net0416 ; wire net0397 ; wire net0495 ; wire net0417 ; wire net0496 ; wire net0398 ; wire net0418 ; wire net0419 ; wire net862 ; wire net1043 ; wire bso1_bsi2 ; wire net1143 ; wire net1045 ; wire net1144 ; wire net963 ; wire net1046 ; wire net865 ; wire net1047 ; wire bso3_bsi4 ; wire net1049 ; wire net967 ; wire net0879 ; wire net968 ; wire net1149 ; wire net0504 ; wire net870 ; wire net0507 ; wire net0783 ; wire net871 ; wire net0508 ; wire net0784 ; wire net0687 ; wire net971 ; wire net0884 ; wire net0688 ; bw_io_ddr_6sig_x4 I0 ( .serial_in ({serial_in[87:72] } ), .afo ({afo[87:72] } ), .serial_out ({serial_out[87:72] } ), .afi ({afi[87:72] } ), .vrefcode_i_l ({net0324[0] ,net0324[1] ,net0324[2] ,net0324[3] , net0324[4] ,net0324[5] ,net0324[6] ,net0324[7] } ), .vrefcode_i_r ({net0691[0] ,net0691[1] ,net0691[2] ,net0691[3] , net0691[4] ,net0691[5] ,net0691[6] ,net0691[7] } ), .data_neg ({\dram_io_data_out[247] ,\dram_io_data_out[246] , \dram_io_data_out[245] ,\dram_io_data_out[244] , \dram_io_data_out[243] ,\dram_io_data_out[242] , \dram_io_data_out[241] ,\dram_io_data_out[240] , \dram_io_data_out[183] ,\dram_io_data_out[182] , \dram_io_data_out[181] ,\dram_io_data_out[180] , \dram_io_data_out[179] ,\dram_io_data_out[178] , \dram_io_data_out[177] ,\dram_io_data_out[176] } ), .data_pos ({\dram_io_data_out[103] ,\dram_io_data_out[102] , \dram_io_data_out[101] ,\dram_io_data_out[100] , \dram_io_data_out[99] ,\dram_io_data_out[98] , \dram_io_data_out[97] ,\dram_io_data_out[96] , \dram_io_data_out[39] ,\dram_io_data_out[38] , \dram_io_data_out[37] ,\dram_io_data_out[36] , \dram_io_data_out[35] ,\dram_io_data_out[34] , \dram_io_data_out[33] ,\dram_io_data_out[32] } ), .io_dram_data_in ({\io_dram_data_in[103] ,\io_dram_data_in[102] , \io_dram_data_in[101] ,\io_dram_data_in[100] , \io_dram_data_in[99] ,\io_dram_data_in[98] , \io_dram_data_in[97] ,\io_dram_data_in[96] , \io_dram_data_in[39] ,\io_dram_data_in[38] , \io_dram_data_in[37] ,\io_dram_data_in[36] , \io_dram_data_in[35] ,\io_dram_data_in[34] , \io_dram_data_in[33] ,\io_dram_data_in[32] } ), .io_dram_data_in_hi ({\io_dram_data_in[231] ,\io_dram_data_in[230] ,\io_dram_data_in[229] ,\io_dram_data_in[228] , \io_dram_data_in[227] ,\io_dram_data_in[226] , \io_dram_data_in[225] ,\io_dram_data_in[224] , \io_dram_data_in[167] ,\io_dram_data_in[166] , \io_dram_data_in[165] ,\io_dram_data_in[164] , \io_dram_data_in[163] ,\io_dram_data_in[162] , \io_dram_data_in[161] ,\io_dram_data_in[160] } ), .dq_pad ({\dram_dq[103] ,\dram_dq[102] ,\dram_dq[101] , \dram_dq[100] ,\dram_dq[99] ,\dram_dq[98] ,\dram_dq[97] , \dram_dq[96] ,\dram_dq[39] ,\dram_dq[38] ,\dram_dq[37] , \dram_dq[36] ,\dram_dq[35] ,\dram_dq[34] ,\dram_dq[33] , \dram_dq[32] } ), .lpf_code_i_r ({net0565[0] ,net0565[1] ,net0565[2] ,net0565[3] , net0565[4] } ), .dram_io_ptr_clk_inv_i_r ({net0562[0] ,net0562[1] } ), .pad_pos_cnt_i_r ({net0558[0] ,net0558[1] } ), .pad_neg_cnt_i_r ({net0557[0] ,net0557[1] } ), .cbu_i_r ({net0602[0] ,net0602[1] ,net0602[2] ,net0602[3] , net0602[4] ,net0602[5] ,net0602[6] ,net0602[7] } ), .cbd_i_r ({net0601[0] ,net0601[1] ,net0601[2] ,net0601[3] , net0601[4] ,net0601[5] ,net0601[6] ,net0601[7] } ), .dqs_pad ({\dram_dqs[31] ,\dram_dqs[22] ,\dram_dqs[13] , \dram_dqs[4] } ), .lpf_code_i_l ({net0517[0] ,net0517[1] ,net0517[2] ,net0517[3] , net0517[4] } ), .dram_io_ptr_clk_inv_i_l ({net0514[0] ,net0514[1] } ), .pad_pos_cnt_i_l ({net0510[0] ,net0510[1] } ), .pad_neg_cnt_i_l ({net0509[0] ,net0509[1] } ), .cbu_i_l ({net0644[0] ,net0644[1] ,net0644[2] ,net0644[3] , net0644[4] ,net0644[5] ,net0644[6] ,net0644[7] } ), .cbd_i_l ({net0643[0] ,net0643[1] ,net0643[2] ,net0643[3] , net0643[4] ,net0643[5] ,net0643[6] ,net0643[7] } ), .bypass_enable_i_r (net1130 ), .ps_select_i_r (net0544 ), .test_mode_i_l (net0495 ), .testmode_l_i_l (net0511 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0543 ), .strobe_i_r (net0566 ), .burst_length_four_i_r (net0563 ), .dram_io_pad_enable_i_r (net0561 ), .dram_io_drive_enable_i_r (net0560 ), .rst_l_i_r (net0564 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net0556 ), .dram_io_drive_data_i_r (net0555 ), .se_i_r (net0552 ), .mode_ctrl_i_r (net1125 ), .update_dr_i_r (net1293 ), .shift_dr_i_r (net1294 ), .clock_dr_i_r (net1128 ), .hiz_n_i_r (net1296 ), .pad_clk_si (pad_clk_si ), .pad_clk_so (pad_clk_so0_si1 ), .ctl_pad_0 (dram_addr[10] ), .ctl_pad_1 (dram_ba[1] ), .ctl_pad_3 (dram_ras_l ), .ctl_pad_2 (dram_ba[0] ), .ctl_data_0 (dram_io_addr[10] ), .ctl_data_1 (dram_io_bank[1] ), .ctl_data_2 (dram_io_bank[0] ), .ctl_data_3 (dram_io_ras_l ), .bsi (bsi ), .bso (bso0_bsi1 ), .strobe_i_l (net0518 ), .burst_length_four_i_l (net0515 ), .dram_io_pad_enable_i_l (net0513 ), .dram_io_drive_enable_i_l (net0512 ), .rst_l_i_l (net0516 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net0508 ), .dram_io_drive_data_i_l (net0507 ), .se_i_l (net0504 ), .mode_ctrl_i_l (net1270 ), .ps_select_i_l (net0496 ), .shift_dr_i_l (net1272 ), .clock_dr_i_l (net1273 ), .testmode_l_i_r (net0559 ), .hiz_n_i_l (net1274 ), .bypass_enable_i_l (net1275 ), .update_dr_i_l (net1271 ) ); bw_io_ddr_6sig_x4 I1 ( .serial_in ({serial_in[103:88] } ), .afo ({afo[103:88] } ), .serial_out ({serial_out[103:88] } ), .afi ({afi[103:88] } ), .vrefcode_i_l ({net0648[0] ,net0648[1] ,net0648[2] ,net0648[3] , net0648[4] ,net0648[5] ,net0648[6] ,net0648[7] } ), .vrefcode_i_r ({net0699[0] ,net0699[1] ,net0699[2] ,net0699[3] , net0699[4] ,net0699[5] ,net0699[6] ,net0699[7] } ), .data_neg ({\dram_io_data_out[255] ,\dram_io_data_out[254] , \dram_io_data_out[253] ,\dram_io_data_out[252] , \dram_io_data_out[251] ,\dram_io_data_out[250] , \dram_io_data_out[249] ,\dram_io_data_out[248] , \dram_io_data_out[191] ,\dram_io_data_out[190] , \dram_io_data_out[189] ,\dram_io_data_out[188] , \dram_io_data_out[187] ,\dram_io_data_out[186] , \dram_io_data_out[185] ,\dram_io_data_out[184] } ), .data_pos ({\dram_io_data_out[111] ,\dram_io_data_out[110] , \dram_io_data_out[109] ,\dram_io_data_out[108] , \dram_io_data_out[107] ,\dram_io_data_out[106] , \dram_io_data_out[105] ,\dram_io_data_out[104] , \dram_io_data_out[47] ,\dram_io_data_out[46] , \dram_io_data_out[45] ,\dram_io_data_out[44] , \dram_io_data_out[43] ,\dram_io_data_out[42] , \dram_io_data_out[41] ,\dram_io_data_out[40] } ), .io_dram_data_in ({\io_dram_data_in[111] ,\io_dram_data_in[110] , \io_dram_data_in[109] ,\io_dram_data_in[108] , \io_dram_data_in[107] ,\io_dram_data_in[106] , \io_dram_data_in[105] ,\io_dram_data_in[104] , \io_dram_data_in[47] ,\io_dram_data_in[46] , \io_dram_data_in[45] ,\io_dram_data_in[44] , \io_dram_data_in[43] ,\io_dram_data_in[42] , \io_dram_data_in[41] ,\io_dram_data_in[40] } ), .io_dram_data_in_hi ({\io_dram_data_in[239] ,\io_dram_data_in[238] ,\io_dram_data_in[237] ,\io_dram_data_in[236] , \io_dram_data_in[235] ,\io_dram_data_in[234] , \io_dram_data_in[233] ,\io_dram_data_in[232] , \io_dram_data_in[175] ,\io_dram_data_in[174] , \io_dram_data_in[173] ,\io_dram_data_in[172] , \io_dram_data_in[171] ,\io_dram_data_in[170] , \io_dram_data_in[169] ,\io_dram_data_in[168] } ), .dq_pad ({\dram_dq[111] ,\dram_dq[110] ,\dram_dq[109] , \dram_dq[108] ,\dram_dq[107] ,\dram_dq[106] ,\dram_dq[105] , \dram_dq[104] ,\dram_dq[47] ,\dram_dq[46] ,\dram_dq[45] , \dram_dq[44] ,\dram_dq[43] ,\dram_dq[42] ,\dram_dq[41] , \dram_dq[40] } ), .lpf_code_i_r ({net1277[0] ,net1277[1] ,net1277[2] ,net1277[3] , net1277[4] } ), .dram_io_ptr_clk_inv_i_r ({net1280[0] ,net1280[1] } ), .pad_pos_cnt_i_r ({net1118[0] ,net1118[1] } ), .pad_neg_cnt_i_r ({net1286[0] ,net1286[1] } ), .cbu_i_r ({net1290[0] ,net1290[1] ,net1290[2] ,net1290[3] , net1290[4] ,net1290[5] ,net1290[6] ,net1290[7] } ), .cbd_i_r ({net1122[0] ,net1122[1] ,net1122[2] ,net1122[3] , net1122[4] ,net1122[5] ,net1122[6] ,net1122[7] } ), .dqs_pad ({\dram_dqs[32] ,\dram_dqs[23] ,\dram_dqs[14] , \dram_dqs[5] } ), .lpf_code_i_l ({net1103[0] ,net1103[1] ,net1103[2] ,net1103[3] , net1103[4] } ), .dram_io_ptr_clk_inv_i_l ({net1097[0] ,net1097[1] } ), .pad_pos_cnt_i_l ({net1090[0] ,net1090[1] } ), .pad_neg_cnt_i_l ({net1264[0] ,net1264[1] } ), .cbu_i_l ({net1107[0] ,net1107[1] ,net1107[2] ,net1107[3] , net1107[4] ,net1107[5] ,net1107[6] ,net1107[7] } ), .cbd_i_l ({net1106[0] ,net1106[1] ,net1106[2] ,net1106[3] , net1106[4] ,net1106[5] ,net1106[6] ,net1106[7] } ), .bypass_enable_i_r (net1004 ), .ps_select_i_r (net0640 ), .test_mode_i_l (net0591 ), .testmode_l_i_l (net1100 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0639 ), .strobe_i_r (net1104 ), .burst_length_four_i_r (net1279 ), .dram_io_pad_enable_i_r (net1281 ), .dram_io_drive_enable_i_r (net1115 ), .rst_l_i_r (net1278 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net1287 ), .dram_io_drive_data_i_r (net1121 ), .se_i_r (net1291 ), .mode_ctrl_i_r (net999 ), .update_dr_i_r (net1171 ), .shift_dr_i_r (net1001 ), .clock_dr_i_r (net1002 ), .hiz_n_i_r (net1003 ), .pad_clk_si (pad_clk_so0_si1 ), .pad_clk_so (pad_clk_so1_si2 ), .ctl_pad_0 (spare_ddr_pin[7] ), .ctl_pad_1 (dram_we_l ), .ctl_pad_3 (dram_cs_l[0] ), .ctl_pad_2 (dram_cas_l ), .ctl_data_0 (spare_ddr_data[7] ), .ctl_data_1 (dram_io_write_en_l ), .ctl_data_2 (dram_io_cas_l ), .ctl_data_3 (dram_io_cs_l[0] ), .bsi (bso0_bsi1 ), .bso (bso1_bsi2 ), .strobe_i_l (net1254 ), .burst_length_four_i_l (net1257 ), .dram_io_pad_enable_i_l (net1259 ), .dram_io_drive_enable_i_l (net1260 ), .rst_l_i_l (net1101 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net1089 ), .dram_io_drive_data_i_l (net1266 ), .se_i_l (net1096 ), .mode_ctrl_i_l (net963 ), .ps_select_i_l (net0592 ), .shift_dr_i_l (net1150 ), .clock_dr_i_l (net1151 ), .testmode_l_i_r (net1284 ), .hiz_n_i_l (net982 ), .bypass_enable_i_l (net983 ), .update_dr_i_l (net1149 ) ); bw_io_ddr_6sig_x4 I2 ( .serial_in ({serial_in[119:104] } ), .afo ({afo[119:104] } ), .serial_out ({serial_out[119:104] } ), .afi ({afi[119:104] } ), .vrefcode_i_l ({net0895[0] ,net0895[1] ,net0895[2] ,net0895[3] , net0895[4] ,net0895[5] ,net0895[6] ,net0895[7] } ), .vrefcode_i_r ({net0844[0] ,net0844[1] ,net0844[2] ,net0844[3] , net0844[4] ,net0844[5] ,net0844[6] ,net0844[7] } ), .data_neg ({\dram_io_data_out[263] ,\dram_io_data_out[262] , \dram_io_data_out[261] ,\dram_io_data_out[260] , \dram_io_data_out[259] ,\dram_io_data_out[258] , \dram_io_data_out[257] ,\dram_io_data_out[256] , \dram_io_data_out[199] ,\dram_io_data_out[198] , \dram_io_data_out[197] ,\dram_io_data_out[196] , \dram_io_data_out[195] ,\dram_io_data_out[194] , \dram_io_data_out[193] ,\dram_io_data_out[192] } ), .data_pos ({\dram_io_data_out[119] ,\dram_io_data_out[118] , \dram_io_data_out[117] ,\dram_io_data_out[116] , \dram_io_data_out[115] ,\dram_io_data_out[114] , \dram_io_data_out[113] ,\dram_io_data_out[112] , \dram_io_data_out[55] ,\dram_io_data_out[54] , \dram_io_data_out[53] ,\dram_io_data_out[52] , \dram_io_data_out[51] ,\dram_io_data_out[50] , \dram_io_data_out[49] ,\dram_io_data_out[48] } ), .io_dram_data_in ({\io_dram_data_in[119] ,\io_dram_data_in[118] , \io_dram_data_in[117] ,\io_dram_data_in[116] , \io_dram_data_in[115] ,\io_dram_data_in[114] , \io_dram_data_in[113] ,\io_dram_data_in[112] , \io_dram_data_in[55] ,\io_dram_data_in[54] , \io_dram_data_in[53] ,\io_dram_data_in[52] , \io_dram_data_in[51] ,\io_dram_data_in[50] , \io_dram_data_in[49] ,\io_dram_data_in[48] } ), .io_dram_data_in_hi ({\io_dram_data_in[247] ,\io_dram_data_in[246] ,\io_dram_data_in[245] ,\io_dram_data_in[244] , \io_dram_data_in[243] ,\io_dram_data_in[242] , \io_dram_data_in[241] ,\io_dram_data_in[240] , \io_dram_data_in[183] ,\io_dram_data_in[182] , \io_dram_data_in[181] ,\io_dram_data_in[180] , \io_dram_data_in[179] ,\io_dram_data_in[178] , \io_dram_data_in[177] ,\io_dram_data_in[176] } ), .dq_pad ({\dram_dq[119] ,\dram_dq[118] ,\dram_dq[117] , \dram_dq[116] ,\dram_dq[115] ,\dram_dq[114] ,\dram_dq[113] , \dram_dq[112] ,\dram_dq[55] ,\dram_dq[54] ,\dram_dq[53] , \dram_dq[52] ,\dram_dq[51] ,\dram_dq[50] ,\dram_dq[49] , \dram_dq[48] } ), .lpf_code_i_r ({net1155[0] ,net1155[1] ,net1155[2] ,net1155[3] , net1155[4] } ), .dram_io_ptr_clk_inv_i_r ({net1158[0] ,net1158[1] } ), .pad_pos_cnt_i_r ({net1163[0] ,net1163[1] } ), .pad_neg_cnt_i_r ({net1164[0] ,net1164[1] } ), .cbu_i_r ({net997[0] ,net997[1] ,net997[2] ,net997[3] , net997[4] ,net997[5] ,net997[6] ,net997[7] } ), .cbd_i_r ({net1167[0] ,net1167[1] ,net1167[2] ,net1167[3] , net1167[4] ,net1167[5] ,net1167[6] ,net1167[7] } ), .dqs_pad ({\dram_dqs[33] ,\dram_dqs[24] ,\dram_dqs[15] , \dram_dqs[6] } ), .lpf_code_i_l ({net977[0] ,net977[1] ,net977[2] ,net977[3] , net977[4] } ), .dram_io_ptr_clk_inv_i_l ({net1136[0] ,net1136[1] } ), .pad_pos_cnt_i_l ({net966[0] ,net966[1] } ), .pad_neg_cnt_i_l ({net964[0] ,net964[1] } ), .cbu_i_l ({net981[0] ,net981[1] ,net981[2] ,net981[3] , net981[4] ,net981[5] ,net981[6] ,net981[7] } ), .cbd_i_l ({net1145[0] ,net1145[1] ,net1145[2] ,net1145[3] , net1145[4] ,net1145[5] ,net1145[6] ,net1145[7] } ), .bypass_enable_i_r (net1049 ), .ps_select_i_r (net0736 ), .test_mode_i_l (net0831 ), .testmode_l_i_l (net974 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0735 ), .strobe_i_r (net1154 ), .burst_length_four_i_r (net1157 ), .dram_io_pad_enable_i_r (net1159 ), .dram_io_drive_enable_i_r (net1160 ), .rst_l_i_r (net1156 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net994 ), .dram_io_drive_data_i_r (net1166 ), .se_i_r (net1169 ), .mode_ctrl_i_r (net875 ), .update_dr_i_r (net1045 ), .shift_dr_i_r (net1046 ), .clock_dr_i_r (net1047 ), .hiz_n_i_r (net879 ), .pad_clk_si (pad_clk_so1_si2 ), .pad_clk_so (pad_clk_so2_si3 ), .ctl_pad_0 (dram_cs_l[1] ), .ctl_pad_1 (dram_cs_l[2] ), .ctl_pad_3 (spare_ddr_pin[2] ), .ctl_pad_2 (dram_cs_l[3] ), .ctl_data_0 (dram_io_cs_l[1] ), .ctl_data_1 (dram_io_cs_l[2] ), .ctl_data_2 (dram_io_cs_l[3] ), .ctl_data_3 (spare_ddr_data[2] ), .bsi (bso1_bsi2 ), .bso (bso2_bsi3 ), .strobe_i_l (net973 ), .burst_length_four_i_l (net967 ), .dram_io_pad_enable_i_l (net1137 ), .dram_io_drive_enable_i_l (net968 ), .rst_l_i_l (net1134 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net1143 ), .dram_io_drive_data_i_l (net1144 ), .se_i_l (net971 ), .mode_ctrl_i_l (net839 ), .ps_select_i_l (net0832 ), .shift_dr_i_l (net837 ), .clock_dr_i_l (net1025 ), .testmode_l_i_r (net991 ), .hiz_n_i_l (net858 ), .bypass_enable_i_l (net1027 ), .update_dr_i_l (net1023 ) ); bw_io_ddr_6sig_x4 I3 ( .serial_in ({serial_in[135:120] } ), .afo ({afo[135:120] } ), .serial_out ({serial_out[135:120] } ), .afi ({afi[135:120] } ), .vrefcode_i_l ({net0742[0] ,net0742[1] ,net0742[2] ,net0742[3] , net0742[4] ,net0742[5] ,net0742[6] ,net0742[7] } ), .vrefcode_i_r ({net0845[0] ,net0845[1] ,net0845[2] ,net0845[3] , net0845[4] ,net0845[5] ,net0845[6] ,net0845[7] } ), .data_neg ({\dram_io_data_out[271] ,\dram_io_data_out[270] , \dram_io_data_out[269] ,\dram_io_data_out[268] , \dram_io_data_out[267] ,\dram_io_data_out[266] , \dram_io_data_out[265] ,\dram_io_data_out[264] , \dram_io_data_out[207] ,\dram_io_data_out[206] , \dram_io_data_out[205] ,\dram_io_data_out[204] , \dram_io_data_out[203] ,\dram_io_data_out[202] , \dram_io_data_out[201] ,\dram_io_data_out[200] } ), .data_pos ({\dram_io_data_out[127] ,\dram_io_data_out[126] , \dram_io_data_out[125] ,\dram_io_data_out[124] , \dram_io_data_out[123] ,\dram_io_data_out[122] , \dram_io_data_out[121] ,\dram_io_data_out[120] , \dram_io_data_out[63] ,\dram_io_data_out[62] , \dram_io_data_out[61] ,\dram_io_data_out[60] , \dram_io_data_out[59] ,\dram_io_data_out[58] , \dram_io_data_out[57] ,\dram_io_data_out[56] } ), .io_dram_data_in ({\io_dram_data_in[127] ,\io_dram_data_in[126] , \io_dram_data_in[125] ,\io_dram_data_in[124] , \io_dram_data_in[123] ,\io_dram_data_in[122] , \io_dram_data_in[121] ,\io_dram_data_in[120] , \io_dram_data_in[63] ,\io_dram_data_in[62] , \io_dram_data_in[61] ,\io_dram_data_in[60] , \io_dram_data_in[59] ,\io_dram_data_in[58] , \io_dram_data_in[57] ,\io_dram_data_in[56] } ), .io_dram_data_in_hi ({\io_dram_data_in[255] ,\io_dram_data_in[254] ,\io_dram_data_in[253] ,\io_dram_data_in[252] , \io_dram_data_in[251] ,\io_dram_data_in[250] , \io_dram_data_in[249] ,\io_dram_data_in[248] , \io_dram_data_in[191] ,\io_dram_data_in[190] , \io_dram_data_in[189] ,\io_dram_data_in[188] , \io_dram_data_in[187] ,\io_dram_data_in[186] , \io_dram_data_in[185] ,\io_dram_data_in[184] } ), .dq_pad ({\dram_dq[127] ,\dram_dq[126] ,\dram_dq[125] , \dram_dq[124] ,\dram_dq[123] ,\dram_dq[122] ,\dram_dq[121] , \dram_dq[120] ,\dram_dq[63] ,\dram_dq[62] ,\dram_dq[61] , \dram_dq[60] ,\dram_dq[59] ,\dram_dq[58] ,\dram_dq[57] , \dram_dq[56] } ), .lpf_code_i_r ({net1029[0] ,net1029[1] ,net1029[2] ,net1029[3] , net1029[4] } ), .dram_io_ptr_clk_inv_i_r ({net863[0] ,net863[1] } ), .pad_pos_cnt_i_r ({net868[0] ,net868[1] } ), .pad_neg_cnt_i_r ({net1038[0] ,net1038[1] } ), .cbu_i_r ({net1042[0] ,net1042[1] ,net1042[2] ,net1042[3] , net1042[4] ,net1042[5] ,net1042[6] ,net1042[7] } ), .cbd_i_r ({net872[0] ,net872[1] ,net872[2] ,net872[3] , net872[4] ,net872[5] ,net872[6] ,net872[7] } ), .dqs_pad ({\dram_dqs[34] ,\dram_dqs[25] ,\dram_dqs[16] , \dram_dqs[7] } ), .lpf_code_i_l ({net1007[0] ,net1007[1] ,net1007[2] ,net1007[3] , net1007[4] } ), .dram_io_ptr_clk_inv_i_l ({net848[0] ,net848[1] } ), .pad_pos_cnt_i_l ({net1015[0] ,net1015[1] } ), .pad_neg_cnt_i_l ({net1016[0] ,net1016[1] } ), .cbu_i_l ({net857[0] ,net857[1] ,net857[2] ,net857[3] , net857[4] ,net857[5] ,net857[6] ,net857[7] } ), .cbd_i_l ({net856[0] ,net856[1] ,net856[2] ,net856[3] , net856[4] ,net856[5] ,net856[6] ,net856[7] } ), .bypass_enable_i_r (net0419 ), .ps_select_i_r (net0784 ), .test_mode_i_l (net0687 ), .testmode_l_i_l (net850 ), .rclk (rclk ), .vdd_h (vdd_h ), .test_mode_i_r (net0783 ), .strobe_i_r (net1028 ), .burst_length_four_i_r (net862 ), .dram_io_pad_enable_i_r (net1033 ), .dram_io_drive_enable_i_r (net865 ), .rst_l_i_r (net1030 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net870 ), .dram_io_drive_data_i_r (net871 ), .se_i_r (net1043 ), .mode_ctrl_i_r (net0414 ), .update_dr_i_r (net0415 ), .shift_dr_i_r (net0416 ), .clock_dr_i_r (net0417 ), .hiz_n_i_r (net0418 ), .pad_clk_si (pad_clk_so2_si3 ), .pad_clk_so (pad_clk_so3_si4 ), .ctl_pad_0 (spare_ddr_pin[3] ), .ctl_pad_1 (spare_ddr_pin[4] ), .ctl_pad_3 (spare_ddr_pin[6] ), .ctl_pad_2 (spare_ddr_pin[5] ), .ctl_data_0 (spare_ddr_data[3] ), .ctl_data_1 (spare_ddr_data[4] ), .ctl_data_2 (spare_ddr_data[5] ), .ctl_data_3 (spare_ddr_data[6] ), .bsi (bso2_bsi3 ), .bso (bso3_bsi4 ), .strobe_i_l (net1006 ), .burst_length_four_i_l (net843 ), .dram_io_pad_enable_i_l (net852 ), .dram_io_drive_enable_i_l (net844 ), .rst_l_i_l (net1008 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net1017 ), .dram_io_drive_data_i_l (net846 ), .se_i_l (net847 ), .mode_ctrl_i_l (net0370 ), .ps_select_i_l (net0688 ), .shift_dr_i_l (net0368 ), .clock_dr_i_l (net0369 ), .testmode_l_i_r (net1036 ), .hiz_n_i_l (net0397 ), .bypass_enable_i_l (net0398 ), .update_dr_i_l (net0394 ) ); bw_io_ddr_rptr_b I358 ( .out14 ({cbd_o_l } ), .out13 ({cbu_o_l } ), .out10 ({net0509[0] ,net0509[1] } ), .out9 ({net0510[0] ,net0510[1] } ), .out4 ({net0514[0] ,net0514[1] } ), .in14 ({net0643[0] ,net0643[1] ,net0643[2] ,net0643[3] , net0643[4] ,net0643[5] ,net0643[6] ,net0643[7] } ), .in13 ({net0644[0] ,net0644[1] ,net0644[2] ,net0644[3] , net0644[4] ,net0644[5] ,net0644[6] ,net0644[7] } ), .out1 ({net0517[0] ,net0517[1] ,net0517[2] ,net0517[3] , net0517[4] } ), .in10 ({pad_neg_cnt_i_l } ), .out25 ({net0324[0] ,net0324[1] ,net0324[2] ,net0324[3] , net0324[4] ,net0324[5] ,net0324[6] ,net0324[7] } ), .in25 ({vrefcode_i_l } ), .in1 ({lpf_code_i_l } ), .in4 ({dram_io_ptr_clk_inv_i_l } ), .in9 ({pad_pos_cnt_i_l } ), .out21 (bypass_enable_o_l ), .out20 (hiz_n_o_l ), .out19 (clock_dr_o_l ), .out18 (shift_dr_o_l ), .out17 (update_dr_o_l ), .out16 (mode_ctrl_o_l ), .out15 (net0504 ), .out12 (net0507 ), .out8 (net0511 ), .out6 (net0512 ), .out5 (net0513 ), .out3 (net0515 ), .out2 (net0516 ), .in21 (net1275 ), .in20 (net1274 ), .in19 (net1273 ), .in18 (net1272 ), .in17 (net1271 ), .in16 (net1270 ), .in15 (se_i_l ), .in12 (dram_io_drive_data_i_l ), .out0 (net0518 ), .in22 (net0496 ), .out22 (ps_select_o_l ), .in24 (test_mode_i_l ), .out24 (net0495 ), .vdd18 (vdd_h ), .in2 (rst_l_i_l ), .in5 (dram_io_pad_enable_i_l ), .out11 (net0508 ), .in3 (burst_length_four_i_l ), .in11 (dram_io_channel_disabled_i_l ), .in0 (strobe_i_l ), .in6 (dram_io_drive_enable_i_l ), .in8 (testmode_l_i_l ) ); bw_io_ddr_rptr_b I359 ( .out14 ({cbd_o_r } ), .out13 ({cbu_o_r } ), .out10 ({net0557[0] ,net0557[1] } ), .out9 ({net0558[0] ,net0558[1] } ), .out4 ({net0562[0] ,net0562[1] } ), .in14 ({net0601[0] ,net0601[1] ,net0601[2] ,net0601[3] , net0601[4] ,net0601[5] ,net0601[6] ,net0601[7] } ), .in13 ({net0602[0] ,net0602[1] ,net0602[2] ,net0602[3] , net0602[4] ,net0602[5] ,net0602[6] ,net0602[7] } ), .out1 ({net0565[0] ,net0565[1] ,net0565[2] ,net0565[3] , net0565[4] } ), .in10 ({pad_neg_cnt_i_r } ), .out25 ({net0691[0] ,net0691[1] ,net0691[2] ,net0691[3] , net0691[4] ,net0691[5] ,net0691[6] ,net0691[7] } ), .in25 ({vrefcode_i_r } ), .in1 ({lpf_code_i_r } ), .in4 ({dram_io_ptr_clk_inv_i_r } ), .in9 ({pad_pos_cnt_i_r } ), .out21 (bypass_enable_o_r ), .out20 (hiz_n_o_r ), .out19 (clock_dr_o_r ), .out18 (shift_dr_o_r ), .out17 (update_dr_o_r ), .out16 (mode_ctrl_o_r ), .out15 (net0552 ), .out12 (net0555 ), .out8 (net0559 ), .out6 (net0560 ), .out5 (net0561 ), .out3 (net0563 ), .out2 (net0564 ), .in21 (net1130 ), .in20 (net1296 ), .in19 (net1128 ), .in18 (net1294 ), .in17 (net1293 ), .in16 (net1125 ), .in15 (se_i_r ), .in12 (dram_io_drive_data_i_r ), .out0 (net0566 ), .in22 (net0544 ), .out22 (ps_select_o_r ), .in24 (test_mode_i_r ), .out24 (net0543 ), .vdd18 (vdd_h ), .in2 (rst_l_i_r ), .in5 (dram_io_pad_enable_i_r ), .out11 (net0556 ), .in3 (burst_length_four_i_r ), .in11 (dram_io_channel_disabled_i_r ), .in0 (strobe_i_r ), .in6 (dram_io_drive_enable_i_r ), .in8 (testmode_l_i_r ) ); bw_io_ddr_rptr_b I277 ( .out14 ({net0643[0] ,net0643[1] ,net0643[2] ,net0643[3] , net0643[4] ,net0643[5] ,net0643[6] ,net0643[7] } ), .out13 ({net0644[0] ,net0644[1] ,net0644[2] ,net0644[3] , net0644[4] ,net0644[5] ,net0644[6] ,net0644[7] } ), .out10 ({net1264[0] ,net1264[1] } ), .out9 ({net1090[0] ,net1090[1] } ), .out4 ({net1097[0] ,net1097[1] } ), .in14 ({net1106[0] ,net1106[1] ,net1106[2] ,net1106[3] , net1106[4] ,net1106[5] ,net1106[6] ,net1106[7] } ), .in13 ({net1107[0] ,net1107[1] ,net1107[2] ,net1107[3] , net1107[4] ,net1107[5] ,net1107[6] ,net1107[7] } ), .out1 ({net1103[0] ,net1103[1] ,net1103[2] ,net1103[3] , net1103[4] } ), .in10 ({net0509[0] ,net0509[1] } ), .out25 ({net0648[0] ,net0648[1] ,net0648[2] ,net0648[3] , net0648[4] ,net0648[5] ,net0648[6] ,net0648[7] } ), .in25 ({net0324[0] ,net0324[1] ,net0324[2] ,net0324[3] , net0324[4] ,net0324[5] ,net0324[6] ,net0324[7] } ), .in1 ({net0517[0] ,net0517[1] ,net0517[2] ,net0517[3] , net0517[4] } ), .in4 ({net0514[0] ,net0514[1] } ), .in9 ({net0510[0] ,net0510[1] } ), .out21 (net1275 ), .out20 (net1274 ), .out19 (net1273 ), .out18 (net1272 ), .out17 (net1271 ), .out16 (net1270 ), .out15 (net1096 ), .out12 (net1266 ), .out8 (net1100 ), .out6 (net1260 ), .out5 (net1259 ), .out3 (net1257 ), .out2 (net1101 ), .in21 (net983 ), .in20 (net982 ), .in19 (net1151 ), .in18 (net1150 ), .in17 (net1149 ), .in16 (net963 ), .in15 (net0504 ), .in12 (net0507 ), .out0 (net1254 ), .in22 (net0592 ), .out22 (net0496 ), .in24 (net0495 ), .out24 (net0591 ), .vdd18 (vdd_h ), .in2 (net0516 ), .in5 (net0513 ), .out11 (net1089 ), .in3 (net0515 ), .in11 (net0508 ), .in0 (net0518 ), .in6 (net0512 ), .in8 (net0511 ) ); bw_io_ddr_rptr_b I278 ( .out14 ({net0601[0] ,net0601[1] ,net0601[2] ,net0601[3] , net0601[4] ,net0601[5] ,net0601[6] ,net0601[7] } ), .out13 ({net0602[0] ,net0602[1] ,net0602[2] ,net0602[3] , net0602[4] ,net0602[5] ,net0602[6] ,net0602[7] } ), .out10 ({net1286[0] ,net1286[1] } ), .out9 ({net1118[0] ,net1118[1] } ), .out4 ({net1280[0] ,net1280[1] } ), .in14 ({net1122[0] ,net1122[1] ,net1122[2] ,net1122[3] , net1122[4] ,net1122[5] ,net1122[6] ,net1122[7] } ), .in13 ({net1290[0] ,net1290[1] ,net1290[2] ,net1290[3] , net1290[4] ,net1290[5] ,net1290[6] ,net1290[7] } ), .out1 ({net1277[0] ,net1277[1] ,net1277[2] ,net1277[3] , net1277[4] } ), .in10 ({net0557[0] ,net0557[1] } ), .out25 ({net0699[0] ,net0699[1] ,net0699[2] ,net0699[3] , net0699[4] ,net0699[5] ,net0699[6] ,net0699[7] } ), .in25 ({net0691[0] ,net0691[1] ,net0691[2] ,net0691[3] , net0691[4] ,net0691[5] ,net0691[6] ,net0691[7] } ), .in1 ({net0565[0] ,net0565[1] ,net0565[2] ,net0565[3] , net0565[4] } ), .in4 ({net0562[0] ,net0562[1] } ), .in9 ({net0558[0] ,net0558[1] } ), .out21 (net1130 ), .out20 (net1296 ), .out19 (net1128 ), .out18 (net1294 ), .out17 (net1293 ), .out16 (net1125 ), .out15 (net1291 ), .out12 (net1121 ), .out8 (net1284 ), .out6 (net1115 ), .out5 (net1281 ), .out3 (net1279 ), .out2 (net1278 ), .in21 (net1004 ), .in20 (net1003 ), .in19 (net1002 ), .in18 (net1001 ), .in17 (net1171 ), .in16 (net999 ), .in15 (net0552 ), .in12 (net0555 ), .out0 (net1104 ), .in22 (net0640 ), .out22 (net0544 ), .in24 (net0543 ), .out24 (net0639 ), .vdd18 (vdd_h ), .in2 (net0564 ), .in5 (net0561 ), .out11 (net1287 ), .in3 (net0563 ), .in11 (net0556 ), .in0 (net0566 ), .in6 (net0560 ), .in8 (net0559 ) ); bw_io_ddr_rptr_b I279 ( .out14 ({net1106[0] ,net1106[1] ,net1106[2] ,net1106[3] , net1106[4] ,net1106[5] ,net1106[6] ,net1106[7] } ), .out13 ({net1107[0] ,net1107[1] ,net1107[2] ,net1107[3] , net1107[4] ,net1107[5] ,net1107[6] ,net1107[7] } ), .out10 ({net964[0] ,net964[1] } ), .out9 ({net966[0] ,net966[1] } ), .out4 ({net1136[0] ,net1136[1] } ), .in14 ({net1145[0] ,net1145[1] ,net1145[2] ,net1145[3] , net1145[4] ,net1145[5] ,net1145[6] ,net1145[7] } ), .in13 ({net981[0] ,net981[1] ,net981[2] ,net981[3] , net981[4] ,net981[5] ,net981[6] ,net981[7] } ), .out1 ({net977[0] ,net977[1] ,net977[2] ,net977[3] , net977[4] } ), .in10 ({net1264[0] ,net1264[1] } ), .out25 ({net0895[0] ,net0895[1] ,net0895[2] ,net0895[3] , net0895[4] ,net0895[5] ,net0895[6] ,net0895[7] } ), .in25 ({net0648[0] ,net0648[1] ,net0648[2] ,net0648[3] , net0648[4] ,net0648[5] ,net0648[6] ,net0648[7] } ), .in1 ({net1103[0] ,net1103[1] ,net1103[2] ,net1103[3] , net1103[4] } ), .in4 ({net1097[0] ,net1097[1] } ), .in9 ({net1090[0] ,net1090[1] } ), .out21 (net983 ), .out20 (net982 ), .out19 (net1151 ), .out18 (net1150 ), .out17 (net1149 ), .out16 (net963 ), .out15 (net971 ), .out12 (net1144 ), .out8 (net974 ), .out6 (net968 ), .out5 (net1137 ), .out3 (net967 ), .out2 (net1134 ), .in21 (net1027 ), .in20 (net858 ), .in19 (net1025 ), .in18 (net837 ), .in17 (net1023 ), .in16 (net839 ), .in15 (net1096 ), .in12 (net1266 ), .out0 (net973 ), .in22 (net0832 ), .out22 (net0592 ), .in24 (net0591 ), .out24 (net0831 ), .vdd18 (vdd_h ), .in2 (net1101 ), .in5 (net1259 ), .out11 (net1143 ), .in3 (net1257 ), .in11 (net1089 ), .in0 (net1254 ), .in6 (net1260 ), .in8 (net1100 ) ); bw_io_ddr_6sig_x2_async I181 ( .serial_out ({serial_out[143:136] } ), .serial_in ({serial_in[143:136] } ), .afo ({afo[143:136] } ), .afi ({afi[143:136] } ), .vrefcode_i_l ({net0974[0] ,net0974[1] ,net0974[2] ,net0974[3] , net0974[4] ,net0974[5] ,net0974[6] ,net0974[7] } ), .vrefcode_i_r ({net0945[0] ,net0945[1] ,net0945[2] ,net0945[3] , net0945[4] ,net0945[5] ,net0945[6] ,net0945[7] } ), .dq_pad ({dram_cb } ), .io_dram_data_in ({\io_dram_ecc_in[15] ,\io_dram_ecc_in[14] , \io_dram_ecc_in[13] ,\io_dram_ecc_in[12] , \io_dram_ecc_in[11] ,\io_dram_ecc_in[10] ,\io_dram_ecc_in[9] ,\io_dram_ecc_in[8] } ), .io_dram_data_in_hi ({\io_dram_ecc_in[31] ,\io_dram_ecc_in[30] , \io_dram_ecc_in[29] ,\io_dram_ecc_in[28] , \io_dram_ecc_in[27] ,\io_dram_ecc_in[26] , \io_dram_ecc_in[25] ,\io_dram_ecc_in[24] } ), .data_neg ({\dram_io_data_out[287] ,\dram_io_data_out[286] , \dram_io_data_out[285] ,\dram_io_data_out[284] , \dram_io_data_out[283] ,\dram_io_data_out[282] , \dram_io_data_out[281] ,\dram_io_data_out[280] } ), .data_pos ({\dram_io_data_out[143] ,\dram_io_data_out[142] , \dram_io_data_out[141] ,\dram_io_data_out[140] , \dram_io_data_out[139] ,\dram_io_data_out[138] , \dram_io_data_out[137] ,\dram_io_data_out[136] } ), .dqs_pad ({\dram_dqs[35] ,\dram_dqs[26] } ), .lpf_code_i_r ({net0399[0] ,net0399[1] ,net0399[2] ,net0399[3] , net0399[4] } ), .dram_io_ptr_clk_inv_i_r ({net0402[0] ,net0402[1] } ), .pad_pos_cnt_i_r ({net0407[0] ,net0407[1] } ), .pad_neg_cnt_i_r ({net0408[0] ,net0408[1] } ), .cbu_i_r ({cbu_i_r } ), .cbd_i_r ({cbd_i_r } ), .lpf_code_i_l ({net0390[0] ,net0390[1] ,net0390[2] ,net0390[3] , net0390[4] } ), .dram_io_ptr_clk_inv_i_l ({net0381[0] ,net0381[1] } ), .pad_pos_cnt_i_l ({net0373[0] ,net0373[1] } ), .pad_neg_cnt_i_l ({net0371[0] ,net0371[1] } ), .cbu_i_l ({cbu_i_l } ), .cbd_i_l ({cbd_i_l } ), .ps_select_i_l (ps_select_i_l ), .testmode_l_i_l (net0387 ), .test_mode_i_l (net0879 ), .testmode_l_i_r (net0406 ), .test_mode_i_r (net0884 ), .pad_clk_so (pad_clk_so ), .async_pad_0 (spare_ddr_pin[1] ), .async_pad_1 (spare_ddr_pin[0] ), .ps_select_i_r (ps_select_i_r ), .bso (bso ), .ctl_data_0 (spare_ddr_data[1] ), .pad_clk_si (pad_clk_so3_si4 ), .bypass_enable_i_l (bypass_enable_i_l ), .vdd_h (vdd_h ), .strobe_i_r (net0393 ), .burst_length_four_i_r (net0401 ), .dram_io_pad_enable_i_r (net0403 ), .dram_io_drive_enable_i_r (net0404 ), .rst_l_i_r (net0400 ), .arst_l_i_r (arst_l_i_r ), .dram_io_channel_disabled_i_r (net0409 ), .dram_io_drive_data_i_r (net0410 ), .se_i_r (net0413 ), .mode_ctrl_i_r (mode_ctrl_i_r ), .shift_dr_i_r (shift_dr_i_r ), .clock_dr_i_r (clock_dr_i_r ), .hiz_n_i_r (hiz_n_i_r ), .update_dr_i_r (update_dr_i_r ), .strobe_i_l (net0386 ), .burst_length_four_i_l (net0374 ), .dram_io_pad_enable_i_l (net0389 ), .dram_io_drive_enable_i_l (dram_io_drive_enable_o_l ), .ctl_data_1 (spare_ddr_data[0] ), .rst_l_i_l (net0388 ), .arst_l_i_l (arst_l_i_l ), .dram_io_channel_disabled_i_l (net0372 ), .dram_io_drive_data_i_l (net0377 ), .se_i_l (se_o_l ), .mode_ctrl_i_l (mode_ctrl_i_l ), .shift_dr_i_l (shift_dr_i_l ), .clock_dr_i_l (clock_dr_i_l ), .hiz_n_i_l (hiz_n_i_l ), .update_dr_i_l (update_dr_i_l ), .rclk (rclk ), .bypass_enable_i_r (bypass_enable_i_r ), .bsi (bso3_bsi4 ) ); bw_io_ddr_rptr_b I280 ( .out14 ({net1122[0] ,net1122[1] ,net1122[2] ,net1122[3] , net1122[4] ,net1122[5] ,net1122[6] ,net1122[7] } ), .out13 ({net1290[0] ,net1290[1] ,net1290[2] ,net1290[3] , net1290[4] ,net1290[5] ,net1290[6] ,net1290[7] } ), .out10 ({net1164[0] ,net1164[1] } ), .out9 ({net1163[0] ,net1163[1] } ), .out4 ({net1158[0] ,net1158[1] } ), .in14 ({net1167[0] ,net1167[1] ,net1167[2] ,net1167[3] , net1167[4] ,net1167[5] ,net1167[6] ,net1167[7] } ), .in13 ({net997[0] ,net997[1] ,net997[2] ,net997[3] , net997[4] ,net997[5] ,net997[6] ,net997[7] } ), .out1 ({net1155[0] ,net1155[1] ,net1155[2] ,net1155[3] , net1155[4] } ), .in10 ({net1286[0] ,net1286[1] } ), .out25 ({net0844[0] ,net0844[1] ,net0844[2] ,net0844[3] , net0844[4] ,net0844[5] ,net0844[6] ,net0844[7] } ), .in25 ({net0699[0] ,net0699[1] ,net0699[2] ,net0699[3] , net0699[4] ,net0699[5] ,net0699[6] ,net0699[7] } ), .in1 ({net1277[0] ,net1277[1] ,net1277[2] ,net1277[3] , net1277[4] } ), .in4 ({net1280[0] ,net1280[1] } ), .in9 ({net1118[0] ,net1118[1] } ), .out21 (net1004 ), .out20 (net1003 ), .out19 (net1002 ), .out18 (net1001 ), .out17 (net1171 ), .out16 (net999 ), .out15 (net1169 ), .out12 (net1166 ), .out8 (net991 ), .out6 (net1160 ), .out5 (net1159 ), .out3 (net1157 ), .out2 (net1156 ), .in21 (net1049 ), .in20 (net879 ), .in19 (net1047 ), .in18 (net1046 ), .in17 (net1045 ), .in16 (net875 ), .in15 (net1291 ), .in12 (net1121 ), .out0 (net1154 ), .in22 (net0736 ), .out22 (net0640 ), .in24 (net0639 ), .out24 (net0735 ), .vdd18 (vdd_h ), .in2 (net1278 ), .in5 (net1281 ), .out11 (net994 ), .in3 (net1279 ), .in11 (net1287 ), .in0 (net1104 ), .in6 (net1115 ), .in8 (net1284 ) ); bw_io_ddr_rptr_b I281 ( .out14 ({net1145[0] ,net1145[1] ,net1145[2] ,net1145[3] , net1145[4] ,net1145[5] ,net1145[6] ,net1145[7] } ), .out13 ({net981[0] ,net981[1] ,net981[2] ,net981[3] , net981[4] ,net981[5] ,net981[6] ,net981[7] } ), .out10 ({net1016[0] ,net1016[1] } ), .out9 ({net1015[0] ,net1015[1] } ), .out4 ({net848[0] ,net848[1] } ), .in14 ({net856[0] ,net856[1] ,net856[2] ,net856[3] , net856[4] ,net856[5] ,net856[6] ,net856[7] } ), .in13 ({net857[0] ,net857[1] ,net857[2] ,net857[3] , net857[4] ,net857[5] ,net857[6] ,net857[7] } ), .out1 ({net1007[0] ,net1007[1] ,net1007[2] ,net1007[3] , net1007[4] } ), .in10 ({net964[0] ,net964[1] } ), .out25 ({net0742[0] ,net0742[1] ,net0742[2] ,net0742[3] , net0742[4] ,net0742[5] ,net0742[6] ,net0742[7] } ), .in25 ({net0895[0] ,net0895[1] ,net0895[2] ,net0895[3] , net0895[4] ,net0895[5] ,net0895[6] ,net0895[7] } ), .in1 ({net977[0] ,net977[1] ,net977[2] ,net977[3] , net977[4] } ), .in4 ({net1136[0] ,net1136[1] } ), .in9 ({net966[0] ,net966[1] } ), .out21 (net1027 ), .out20 (net858 ), .out19 (net1025 ), .out18 (net837 ), .out17 (net1023 ), .out16 (net839 ), .out15 (net847 ), .out12 (net846 ), .out8 (net850 ), .out6 (net844 ), .out5 (net852 ), .out3 (net843 ), .out2 (net1008 ), .in21 (net0398 ), .in20 (net0397 ), .in19 (net0369 ), .in18 (net0368 ), .in17 (net0394 ), .in16 (net0370 ), .in15 (net971 ), .in12 (net1144 ), .out0 (net1006 ), .in22 (net0688 ), .out22 (net0832 ), .in24 (net0831 ), .out24 (net0687 ), .vdd18 (vdd_h ), .in2 (net1134 ), .in5 (net1137 ), .out11 (net1017 ), .in3 (net967 ), .in11 (net1143 ), .in0 (net973 ), .in6 (net968 ), .in8 (net974 ) ); bw_io_ddr_rptr_b I282 ( .out14 ({net1167[0] ,net1167[1] ,net1167[2] ,net1167[3] , net1167[4] ,net1167[5] ,net1167[6] ,net1167[7] } ), .out13 ({net997[0] ,net997[1] ,net997[2] ,net997[3] , net997[4] ,net997[5] ,net997[6] ,net997[7] } ), .out10 ({net1038[0] ,net1038[1] } ), .out9 ({net868[0] ,net868[1] } ), .out4 ({net863[0] ,net863[1] } ), .in14 ({net872[0] ,net872[1] ,net872[2] ,net872[3] , net872[4] ,net872[5] ,net872[6] ,net872[7] } ), .in13 ({net1042[0] ,net1042[1] ,net1042[2] ,net1042[3] , net1042[4] ,net1042[5] ,net1042[6] ,net1042[7] } ), .out1 ({net1029[0] ,net1029[1] ,net1029[2] ,net1029[3] , net1029[4] } ), .in10 ({net1164[0] ,net1164[1] } ), .out25 ({net0845[0] ,net0845[1] ,net0845[2] ,net0845[3] , net0845[4] ,net0845[5] ,net0845[6] ,net0845[7] } ), .in25 ({net0844[0] ,net0844[1] ,net0844[2] ,net0844[3] , net0844[4] ,net0844[5] ,net0844[6] ,net0844[7] } ), .in1 ({net1155[0] ,net1155[1] ,net1155[2] ,net1155[3] , net1155[4] } ), .in4 ({net1158[0] ,net1158[1] } ), .in9 ({net1163[0] ,net1163[1] } ), .out21 (net1049 ), .out20 (net879 ), .out19 (net1047 ), .out18 (net1046 ), .out17 (net1045 ), .out16 (net875 ), .out15 (net1043 ), .out12 (net871 ), .out8 (net1036 ), .out6 (net865 ), .out5 (net1033 ), .out3 (net862 ), .out2 (net1030 ), .in21 (net0419 ), .in20 (net0418 ), .in19 (net0417 ), .in18 (net0416 ), .in17 (net0415 ), .in16 (net0414 ), .in15 (net1169 ), .in12 (net1166 ), .out0 (net1028 ), .in22 (net0784 ), .out22 (net0736 ), .in24 (net0735 ), .out24 (net0783 ), .vdd18 (vdd_h ), .in2 (net1156 ), .in5 (net1159 ), .out11 (net870 ), .in3 (net1157 ), .in11 (net994 ), .in0 (net1154 ), .in6 (net1160 ), .in8 (net991 ) ); bw_io_ddr_rptr_b I283 ( .out14 ({net856[0] ,net856[1] ,net856[2] ,net856[3] , net856[4] ,net856[5] ,net856[6] ,net856[7] } ), .out13 ({net857[0] ,net857[1] ,net857[2] ,net857[3] , net857[4] ,net857[5] ,net857[6] ,net857[7] } ), .out10 ({net0371[0] ,net0371[1] } ), .out9 ({net0373[0] ,net0373[1] } ), .out4 ({net0381[0] ,net0381[1] } ), .in14 ({cbd_i_l } ), .in13 ({cbu_i_l } ), .out1 ({net0390[0] ,net0390[1] ,net0390[2] ,net0390[3] , net0390[4] } ), .in10 ({net1016[0] ,net1016[1] } ), .out25 ({net0974[0] ,net0974[1] ,net0974[2] ,net0974[3] , net0974[4] ,net0974[5] ,net0974[6] ,net0974[7] } ), .in25 ({net0742[0] ,net0742[1] ,net0742[2] ,net0742[3] , net0742[4] ,net0742[5] ,net0742[6] ,net0742[7] } ), .in1 ({net1007[0] ,net1007[1] ,net1007[2] ,net1007[3] , net1007[4] } ), .in4 ({net848[0] ,net848[1] } ), .in9 ({net1015[0] ,net1015[1] } ), .out21 (net0398 ), .out20 (net0397 ), .out19 (net0369 ), .out18 (net0368 ), .out17 (net0394 ), .out16 (net0370 ), .out15 (se_o_l ), .out12 (net0377 ), .out8 (net0387 ), .out6 (dram_io_drive_enable_o_l ), .out5 (net0389 ), .out3 (net0374 ), .out2 (net0388 ), .in21 (bypass_enable_i_l ), .in20 (hiz_n_i_l ), .in19 (clock_dr_i_l ), .in18 (shift_dr_i_l ), .in17 (update_dr_i_l ), .in16 (mode_ctrl_i_l ), .in15 (net847 ), .in12 (net846 ), .out0 (net0386 ), .in22 (ps_select_i_l ), .out22 (net0688 ), .in24 (net0687 ), .out24 (net0879 ), .vdd18 (vdd_h ), .in2 (net1008 ), .in5 (net852 ), .out11 (net0372 ), .in3 (net843 ), .in11 (net1017 ), .in0 (net1006 ), .in6 (net844 ), .in8 (net850 ) ); bw_io_ddr_rptr_b I284 ( .out14 ({net872[0] ,net872[1] ,net872[2] ,net872[3] , net872[4] ,net872[5] ,net872[6] ,net872[7] } ), .out13 ({net1042[0] ,net1042[1] ,net1042[2] ,net1042[3] , net1042[4] ,net1042[5] ,net1042[6] ,net1042[7] } ), .out10 ({net0408[0] ,net0408[1] } ), .out9 ({net0407[0] ,net0407[1] } ), .out4 ({net0402[0] ,net0402[1] } ), .in14 ({cbd_i_r } ), .in13 ({cbu_i_r } ), .out1 ({net0399[0] ,net0399[1] ,net0399[2] ,net0399[3] , net0399[4] } ), .in10 ({net1038[0] ,net1038[1] } ), .out25 ({net0945[0] ,net0945[1] ,net0945[2] ,net0945[3] , net0945[4] ,net0945[5] ,net0945[6] ,net0945[7] } ), .in25 ({net0845[0] ,net0845[1] ,net0845[2] ,net0845[3] , net0845[4] ,net0845[5] ,net0845[6] ,net0845[7] } ), .in1 ({net1029[0] ,net1029[1] ,net1029[2] ,net1029[3] , net1029[4] } ), .in4 ({net863[0] ,net863[1] } ), .in9 ({net868[0] ,net868[1] } ), .out21 (net0419 ), .out20 (net0418 ), .out19 (net0417 ), .out18 (net0416 ), .out17 (net0415 ), .out16 (net0414 ), .out15 (net0413 ), .out12 (net0410 ), .out8 (net0406 ), .out6 (net0404 ), .out5 (net0403 ), .out3 (net0401 ), .out2 (net0400 ), .in21 (bypass_enable_i_r ), .in20 (hiz_n_i_r ), .in19 (clock_dr_i_r ), .in18 (shift_dr_i_r ), .in17 (update_dr_i_r ), .in16 (mode_ctrl_i_r ), .in15 (net1043 ), .in12 (net871 ), .out0 (net0393 ), .in22 (ps_select_i_r ), .out22 (net0784 ), .in24 (net0783 ), .out24 (net0884 ), .vdd18 (vdd_h ), .in2 (net1030 ), .in5 (net1033 ), .out11 (net0409 ), .in3 (net862 ), .in11 (net870 ), .in0 (net1028 ), .in6 (net865 ), .in8 (net1036 ) ); assign arst_l_out = arst_l_i_l; endmodule

/*********************************************************************************************************************** * Copyright (C) 2016 Andrew Zonenberg and contributors * * * * This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General * * Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) * * any later version. * * * * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied * * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for * * more details. * * * * You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may * * find one here: * * https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt * * or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software * * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA * **********************************************************************************************************************/ `default_nettype none /** @brief HiL test case for GP_LFOSC OUTPUTS: Oscillator output, divided by 2 (should be ~865 Hz) */ module LFOsc(clkout); //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // I/O declarations (* LOC = "P13" *) output wire clkout; //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // The oscillator GP_LFOSC #( .PWRDN_EN(0), .AUTO_PWRDN(0), .OUT_DIV(2) ) lfosc ( .PWRDN(1'b0), .CLKOUT(clkout) ); endmodule

// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Read Data Response AXI3 Slave Converter // Forwards and re-assembles split transactions. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // r_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_r_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire cmd_split, output wire cmd_ready, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Throttling help signals. wire cmd_ready_i; wire pop_si_data; wire si_stalling; // Internal MI-side control signals. wire M_AXI_RREADY_I; // Internal signals for SI-side. wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I; wire [2-1:0] S_AXI_RRESP_I; wire S_AXI_RLAST_I; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I; wire S_AXI_RVALID_I; wire S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from MI-Side to SI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign M_AXI_RREADY_I = ~si_stalling & cmd_valid; assign M_AXI_RREADY = M_AXI_RREADY_I; // Indicate when there is data available @ SI-side. assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid; // Get SI-side data. assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Simple AXI signal forwarding: // // USER, ID, DATA and RRESP passes through untouched. // // LAST has to be filtered to remove any intermediate LAST (due to split // trasactions). LAST is only removed for the first parts of a split // transaction. When splitting is unsupported is the LAST filtering completely // completely removed. // ///////////////////////////////////////////////////////////////////////////// // Calculate last, i.e. mask from split transactions. assign S_AXI_RLAST_I = M_AXI_RLAST & ( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) ); // Data is passed through. assign S_AXI_RID_I = M_AXI_RID; assign S_AXI_RUSER_I = M_AXI_RUSER; assign S_AXI_RDATA_I = M_AXI_RDATA; assign S_AXI_RRESP_I = M_AXI_RRESP; ///////////////////////////////////////////////////////////////////////////// // SI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign S_AXI_RREADY_I = S_AXI_RREADY; assign S_AXI_RVALID = S_AXI_RVALID_I; assign S_AXI_RID = S_AXI_RID_I; assign S_AXI_RDATA = S_AXI_RDATA_I; assign S_AXI_RRESP = S_AXI_RRESP_I; assign S_AXI_RLAST = S_AXI_RLAST_I; assign S_AXI_RUSER = S_AXI_RUSER_I; endmodule

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Ë¢ÐÂÁ÷Ë®Ïß ³ýÊÜfreezeÐÅºÅ¿ØÖÆÍâ£¬Á÷Ë®ÏßÔÚÏÂÃæÇé¿öÏÂÐèÒªË¢ÐÂÁ÷Ë®Ïß£ÅÅ¿ÕÏÖÓÐÖ¸Áî£¬ÖØÐÂÈ¡Ö¸ £¨1£©ÖÐ¶Ï´¦ÀíÄ£¿é²úÉúµÄflush_exceptÒÔË¢ÐÂÁ÷Ë®Ïß £¨2£©·ÖÖ§´¦ÀíÄ£¿éÓÉÓÚ·ÖÖ§Ô¤²â´íÎó²úÉúµÄflush_branchÒÔË¢ÐÂÁ÷Ë®Ïß 3. PCÎ¬»¤ºÍ¸üÐÂ PCÎ¬»¤ºÍ¸üÐÂÓÐÁ½ÖÖÇé¿öÐèÒª·Ö¿ª´¦Àí £¨1£©Á÷Ë®Ïß¶³½áÊ±£¬±£³ÖÏÖÓÐÈ¡Ö¸µØÖ·PC£¬´ý¶³½á½â³ýºó¼ÌÐøÈ¡Ö¸ £¨2£©Á÷Ë®ÏßË¢ÐÂÊ±£¬ÐèÒª·ÅÆúÏÖÓÐPC£¬´ýË¢ÐÂÍê³Éºó·Ö±ðÊ¹ÓÃnpc_xxxÖØÐÂÈ¡Ö¸ pc_freezeÔÚ´ÓÓÐÐ§×´Ì¬»Ö¸´Ê±£¬ * List2do: * [TBV] timing relationship between flushpipe and freeze. * */ // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "def_pippo.v" module pippo_pipectrl( flush_except, flush_branch, flushpipe, if_stall, lsu_stall, multicycle_cnt, asyn_stall, pc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze ); // // I/O // // stall request from pipeline stages input if_stall; input lsu_stall; input asyn_stall; input [1:0] multicycle_cnt; // freeze command to pipeline stages output pc_freeze; output if_freeze; output id_freeze; output ex_freeze; output wb_freeze; // flush control input flush_except; input flush_branch; output flushpipe; // // Internal wires and regs // wire multicycle_stall; // // flush pipelining // at the last cycle of flushpipe assertion, new fetch address will send to pc register // 1. when flush is raised by except processing, assert for two cycles. // 2. when flush is raised by branch processing, assert for one cycle. // assign flushpipe = flush_except | flush_branch; // // PC freeze signal // // pc_freeze is just for dis-asserting fetch request assign pc_freeze = flushpipe; // // Pipeline freeze generation: // assign multicycle_stall = |multicycle_cnt; // notes for asyn_stall: see except module assign if_freeze = if_stall | id_freeze; assign id_freeze = ex_freeze; assign ex_freeze = wb_freeze | asyn_stall; assign wb_freeze = lsu_stall | multicycle_stall; /* Implementation: Memory access instructions with update, under 3r1w rf design a. Load with update instructions pipectrl.v ×¢Òâ£ºmulticycle_stallÌõ¼þÒ²Ðë±ä»¯£¬µ±wb_twiceÓÐÐ§Ê±£¬ÏÂÒ»ÌõÖ¸ÁîÒýÆðmulticycle_stall²»ÄÜÖÃÆð rf.v we & (~wb_freeze | wb_at_fze) //write enable logic wb_twice come from rfwbop, and more to do: 1. logic for write address and source 2. write order of EA and loaded data? 3. wb_atfzeÓÐÐ§Ê±¼äÖ»ÄÜÒ»ÅÄ b. Store with update instructions ×¢ÒâÐèÒªÍ¬²½storeµÄÍê³ÉºÍupdate£¨Ð´EA»ØRA£©µÄÍê³É Logic.a: ¿ÉÒÔÐ´»ØÊ±£¬¶³½áwb£¬Ð´»ØÒ»´Î£¬ÔÙ½â¶³Íê³ÉµÚ¶þ´ÎÐ´»Ø£» pipectrl.v //wb_atfze means: wb_freeze is asserted by wb_twice only, at this case, write-back can go. assign wb_freeze_a = lsu_stall | multicycle_stall; assign wb_freeze = wb_freeze_a | wb_atfze; always @(posedge clk or posedge rst) begin if (rst) wb_atfze <= #1 1'b0; else if(wb_freeze_a) wb_atfze <= #1 rfwb_uops[0] & rfwb_uops[1]; else wb_atfze <= #1 1'b0; end reg_gprs.v assign rf_we = (~flushpipe) & ((wea & ~wb_freeze) |(wea & wb_atfze) | (web & ~wb_freeze)) ; assign rf_addrw = wea & (!web | wb_atfze) ? addrwa : web ? addrwb : 5'd0; assign rf_dataw = wea & (!web | wb_atfze) ? datawa : web ? datawb : 32'd0; operandmux.v/wbmux.v Èç¹ûÊ¹ÓÃ×ª·¢Âß¼£¬ÔòwraºÍwrbµÄ×ª·¢ÐèÒªÔö¼ÓÓÐÐ§Âß¼£»¼Æ»®ÊµÏÖÓÚwbmuxÄ£¿é (gpr_addr_rda == ex_gpr_addr_wra) && (ex_rfwb_uops[0] & !ex_rfwb_uops[1]) (gpr_addr_rda == ex_gpr_addr_wrb) && (ex_rfwb_uops[1] & !wb_atfze) Logic.b: ÏÈÐ´»ØÒ»´Î£¬ÔÙ¶³½áwb¶ÎÍê³ÉµÚ¶þ´ÎÐ´»Ø£»µ¼ÖÂÎÊÌâ£º 1£¬ÏÂÒ»ÌõÖ¸ÁîÒÑ¾½øÈëexe¶Î£¬Èç¹ûÊÇ¶àÖÜÆÚÖ¸ÁîÔò»áµ¼ÖÂwb_atfze±£³ÖÓÐÐ§ 2£¬ÐèÒª¼Ä´æaddr_wrºÍeaµÈ assign wb_freeze_a = lsu_stall | multicycle_stall; assign wb_freeze = wb_freeze_a | wb_atfze; always @(posedge clk or posedge rst) begin if (rst) wb_atfze <= #1 1'b0; else if(!wb_freeze_a) wb_atfze <= #1 rfwb_uops[0] & rfwb_uops[1]; end */ endmodule

module iir (clk, reset, start, din, params, dout, ready,iir_start,iir_done); input clk, reset, start; input [7:0] din; input [15:0] params; output [7:0] dout; reg [7:0] dout; output ready; reg ready; reg temp_ready; reg [6:0] finite_counter; wire count0; input iir_start; output iir_done; wire iir_done; reg del_count0; reg [15:0] a1, a2, b0, b1, b2, yk1, yk2; reg [7:0] uk, uk1, uk2 ; reg [28:0] ysum ; reg [26:0] yk ; reg [22:0] utmp; reg [3:0] wait_counter ; // temporary variable wire [31:0] yo1, yo2; //wire [23:0] b0t, b1t, b2t; wire [22:0] b0t, b1t, b2t; wire [22:0] b0tpaj, b1tpaj, b2tpaj; reg [3:0] obf_state, obf_next_state ; reg [7:0] temp_uk, temp_uk1, temp_uk2 ; reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2; reg [28:0] temp_ysum ; reg [26:0] temp_yk ; reg [22:0] temp_utmp; reg [7:0] temp_dout; reg [3:0] temp_wait_counter ; parameter idle = 4'b0001 , load_a2 = 4'b0010 , load_b0 = 4'b0011 , load_b1 = 4'b0100 , load_b2 = 4'b0101 , wait4_start = 4'b0110 , latch_din = 4'b0111 , compute_a = 4'b1000 , compute_b = 4'b1001 , compute_yk = 4'b1010 , wait4_count = 4'b1011 , latch_dout = 4'b1100 ; always @(obf_state or start or din or wait_counter or iir_start or count0) begin case (obf_state ) idle : begin if (iir_start) obf_next_state = load_a2 ; else obf_next_state = idle; temp_a1 = params ; end load_a2 : begin obf_next_state = load_b0 ; temp_a2 = params ; end load_b0 : begin obf_next_state = load_b1 ; temp_b0 = params ; end load_b1 : begin obf_next_state = load_b2 ; temp_b1 = params ; end load_b2 : begin obf_next_state = wait4_start ; temp_b2 = params ; end wait4_start : begin if (start) begin obf_next_state = latch_din ; temp_uk = din ; end else begin obf_next_state = wait4_start ; temp_uk = uk; end temp_ready = wait4_start; end latch_din : begin obf_next_state = compute_a ; end compute_a : begin obf_next_state = compute_b ; temp_ysum = yo1[31:3] + yo2[31:3]; end compute_b : begin obf_next_state = compute_yk ; // temp_utmp = b0t[23:0] + b1t[23:0] + b2t[23:0]; temp_utmp = b0t + b1t + b2t; end compute_yk : begin obf_next_state = wait4_count ; temp_uk1 = uk ; temp_uk2 = uk1 ; temp_yk = ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp}; temp_wait_counter = 4 ; end wait4_count : begin if (wait_counter==0 ) begin obf_next_state = latch_dout ; temp_dout = yk[26:19]; temp_yk1 = yk[26:11] ; temp_yk2 = yk1 ; end else begin obf_next_state = wait4_count ; temp_dout = dout; temp_yk1 = yk1; //temp_yk2 = yk2; end temp_wait_counter = wait_counter - 1; end latch_dout : if (count0) obf_next_state = idle; else obf_next_state = wait4_start ; endcase end //assign yo1 = mul_tc_16_16(yk1, a1, clk); assign yo1 = yk1 * a1; //assign yo2 = mul_tc_16_16(yk2, a2, clk); assign yo2 = yk2*a2; //assign b0t = mul_tc_8_16(uk, b0, clk); //assign b1t = mul_tc_8_16(uk1, b1, clk); //assign b2t = mul_tc_8_16(uk2, b2, clk); assign b0t = uk*b0; assign b1t = uk1*b1; assign b2t = uk2*b2; // paj added to solve unused high order bit assign b0tpaj = b0t; assign b1tpaj = b1t; assign b2tpaj = b2t; // A COEFFICENTS always @(posedge clk or posedge reset) begin if (reset ) begin uk <= 0 ; uk1 <= 0 ; uk2 <= 0 ; yk1 <= 0 ; yk2 <= 0 ; yk <= 0 ; ysum <= 0 ; utmp <= 0 ; a1 <= 0 ; a2 <= 0 ; b0 <= 0 ; b1 <= 0 ; b2 <= 0 ; dout <= 0 ; obf_state <= idle ; ready <= 0; end else begin obf_state <= obf_next_state ; uk1 <= temp_uk1; uk2 <= temp_uk2; yk <= temp_yk; uk <= temp_uk ; a1 <= temp_a1 ; a2 <= temp_a2 ; b0 <= temp_b0 ; b1 <= temp_b1 ; b2 <= temp_b2 ; ysum <= temp_ysum; utmp <= temp_utmp; dout <= temp_dout; yk1 <= temp_yk1; yk2 <= temp_yk2; ready <= temp_ready; end end // wait counter, count 4 clock after sum is calculated, to // time outputs are ready, and filter is ready to accept next // input always @(posedge clk or posedge reset ) begin if (reset ) wait_counter <= 0 ; else begin wait_counter <= temp_wait_counter ; end end always @(posedge clk) begin if (reset) finite_counter<=100; else if (iir_start) finite_counter<=finite_counter -1; else finite_counter<=finite_counter; end assign count0=finite_counter==7'b0; always @(posedge clk) begin del_count0 <= count0; end assign iir_done = (count0 && ~del_count0); endmodule

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:38:39 08/19/2014 // Design Name: satadd // Module Name: C:/ece4743/projects/lab2_solution_part1/tb_satadd.v // Project Name: lab2_solution_part1 // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: satadd // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module tb_satadd; // Inputs reg [11:0] a; reg [11:0] b; reg [1:0] mode; // Outputs wire [11:0] y; reg[8*100:1] aline; integer fd; integer count,status; integer i_a, i_b, i_mode, i_result; integer errors; // Instantiate the Unit Under Test (UUT) satadd uut ( .a(a), .b(b), .mode(mode), .y(y) ); initial begin // Initialize Inputs a = 0; b = 0; mode = 0; fd = $fopen("test_out.txt","w"); $fclose(fd); fd = $fopen("satadd_vectors.txt","r"); count = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here errors = 0; while ($fgets(aline,fd)) begin status = $sscanf(aline,"%x %x %x %x",i_mode, i_a, i_b, i_result); a = i_a; b = i_b; mode = i_mode; #10 //delay if (i_result == y) begin $display("PASS, mode: %x, a: %x, b: %x, y: %x\n",mode,a,b,y); end else begin $display("FAIL, mode: %x, a: %x, b: %x, y (actual): %x, y (expected): %x\n",mode,a,b,y,i_result); errors = errors + 1; end end //end while if (errors == 0) $display("PASS: All vectors pased.\n"); else $display ("FAIL: %d vectors failed\n",errors); end endmodule

// hps_sdram.v // This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes // will probably be lost. // // Generated using ACDS version 16.1 196 `timescale 1 ps / 1 ps module hps_sdram ( input wire pll_ref_clk, // pll_ref_clk.clk input wire global_reset_n, // global_reset.reset_n input wire soft_reset_n, // soft_reset.reset_n output wire [14:0] mem_a, // memory.mem_a output wire [2:0] mem_ba, // .mem_ba output wire [0:0] mem_ck, // .mem_ck output wire [0:0] mem_ck_n, // .mem_ck_n output wire [0:0] mem_cke, // .mem_cke output wire [0:0] mem_cs_n, // .mem_cs_n output wire [3:0] mem_dm, // .mem_dm output wire [0:0] mem_ras_n, // .mem_ras_n output wire [0:0] mem_cas_n, // .mem_cas_n output wire [0:0] mem_we_n, // .mem_we_n output wire mem_reset_n, // .mem_reset_n inout wire [31:0] mem_dq, // .mem_dq inout wire [3:0] mem_dqs, // .mem_dqs inout wire [3:0] mem_dqs_n, // .mem_dqs_n output wire [0:0] mem_odt, // .mem_odt input wire oct_rzqin // oct.rzqin ); wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk] wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk] wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl hps_sdram_pll pll ( .global_reset_n (global_reset_n), // global_reset.reset_n .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk .pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk .pll_locked (pll_pll_sharing_pll_locked), // .pll_locked .pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk .pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk .pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk .pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk .afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk .pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk ); hps_sdram_p0 p0 ( .global_reset_n (global_reset_n), // global_reset.reset_n .soft_reset_n (soft_reset_n), // soft_reset.reset_n .afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n .afi_reset_export_n (), // afi_reset_export.reset_n .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk .avl_clk (), // avl_clk.clk .avl_reset_n (), // avl_reset.reset_n .scc_clk (), // scc_clk.clk .scc_reset_n (), // scc_reset.reset_n .avl_address (), // avl.address .avl_write (), // .write .avl_writedata (), // .writedata .avl_read (), // .read .avl_readdata (), // .readdata .avl_waitrequest (), // .waitrequest .dll_clk (p0_dll_clk_clk), // dll_clk.clk .afi_addr (c0_afi_afi_addr), // afi.afi_addr .afi_ba (c0_afi_afi_ba), // .afi_ba .afi_cke (c0_afi_afi_cke), // .afi_cke .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n .afi_we_n (c0_afi_afi_we_n), // .afi_we_n .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n .afi_odt (c0_afi_afi_odt), // .afi_odt .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid .afi_wdata (c0_afi_afi_wdata), // .afi_wdata .afi_dm (c0_afi_afi_dm), // .afi_dm .afi_rdata (p0_afi_afi_rdata), // .afi_rdata .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid .afi_wlat (p0_afi_afi_wlat), // .afi_wlat .afi_rlat (p0_afi_afi_rlat), // .afi_rlat .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail .scc_data (), // scc.scc_data .scc_dqs_ena (), // .scc_dqs_ena .scc_dqs_io_ena (), // .scc_dqs_io_ena .scc_dq_ena (), // .scc_dq_ena .scc_dm_ena (), // .scc_dm_ena .capture_strobe_tracking (), // .capture_strobe_tracking .scc_upd (), // .scc_upd .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable .pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk .pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk .pll_locked (pll_pll_sharing_pll_locked), // .pll_locked .pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk .pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk .pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk .pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk .afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk .pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked .dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl .seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol .parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol .mem_a (mem_a), // memory.mem_a .mem_ba (mem_ba), // .mem_ba .mem_ck (mem_ck), // .mem_ck .mem_ck_n (mem_ck_n), // .mem_ck_n .mem_cke (mem_cke), // .mem_cke .mem_cs_n (mem_cs_n), // .mem_cs_n .mem_dm (mem_dm), // .mem_dm .mem_ras_n (mem_ras_n), // .mem_ras_n .mem_cas_n (mem_cas_n), // .mem_cas_n .mem_we_n (mem_we_n), // .mem_we_n .mem_reset_n (mem_reset_n), // .mem_reset_n .mem_dq (mem_dq), // .mem_dq .mem_dqs (mem_dqs), // .mem_dqs .mem_dqs_n (mem_dqs_n), // .mem_dqs_n .mem_odt (mem_odt), // .mem_odt .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess .csr_soft_reset_req (1'b0), // (terminated) .io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intbadout (12'b000000000000), // (terminated) .io_intcasndout (4'b0000), // (terminated) .io_intckdout (4'b0000), // (terminated) .io_intckedout (8'b00000000), // (terminated) .io_intckndout (4'b0000), // (terminated) .io_intcsndout (8'b00000000), // (terminated) .io_intdmdout (20'b00000000000000000000), // (terminated) .io_intdqdin (), // (terminated) .io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intdqsbdout (20'b00000000000000000000), // (terminated) .io_intdqsboe (10'b0000000000), // (terminated) .io_intdqsdout (20'b00000000000000000000), // (terminated) .io_intdqslogicdqsena (10'b0000000000), // (terminated) .io_intdqslogicfiforeset (5'b00000), // (terminated) .io_intdqslogicincrdataen (10'b0000000000), // (terminated) .io_intdqslogicincwrptr (10'b0000000000), // (terminated) .io_intdqslogicoct (10'b0000000000), // (terminated) .io_intdqslogicrdatavalid (), // (terminated) .io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated) .io_intdqsoe (10'b0000000000), // (terminated) .io_intodtdout (8'b00000000), // (terminated) .io_intrasndout (4'b0000), // (terminated) .io_intresetndout (4'b0000), // (terminated) .io_intwendout (4'b0000), // (terminated) .io_intafirlat (), // (terminated) .io_intafiwlat () // (terminated) ); altera_mem_if_hhp_qseq_synth_top #( .MEM_IF_DM_WIDTH (4), .MEM_IF_DQS_WIDTH (4), .MEM_IF_CS_WIDTH (1), .MEM_IF_DQ_WIDTH (32) ) seq ( ); altera_mem_if_hard_memory_controller_top_cyclonev #( .MEM_IF_DQS_WIDTH (4), .MEM_IF_CS_WIDTH (1), .MEM_IF_CHIP_BITS (1), .MEM_IF_CLK_PAIR_COUNT (1), .CSR_ADDR_WIDTH (10), .CSR_DATA_WIDTH (8), .CSR_BE_WIDTH (1), .AVL_ADDR_WIDTH (27), .AVL_DATA_WIDTH (64), .AVL_SIZE_WIDTH (3), .AVL_DATA_WIDTH_PORT_0 (1), .AVL_ADDR_WIDTH_PORT_0 (1), .AVL_NUM_SYMBOLS_PORT_0 (1), .LSB_WFIFO_PORT_0 (5), .MSB_WFIFO_PORT_0 (5), .LSB_RFIFO_PORT_0 (5), .MSB_RFIFO_PORT_0 (5), .AVL_DATA_WIDTH_PORT_1 (1), .AVL_ADDR_WIDTH_PORT_1 (1), .AVL_NUM_SYMBOLS_PORT_1 (1), .LSB_WFIFO_PORT_1 (5), .MSB_WFIFO_PORT_1 (5), .LSB_RFIFO_PORT_1 (5), .MSB_RFIFO_PORT_1 (5), .AVL_DATA_WIDTH_PORT_2 (1), .AVL_ADDR_WIDTH_PORT_2 (1), .AVL_NUM_SYMBOLS_PORT_2 (1), .LSB_WFIFO_PORT_2 (5), .MSB_WFIFO_PORT_2 (5), .LSB_RFIFO_PORT_2 (5), .MSB_RFIFO_PORT_2 (5), .AVL_DATA_WIDTH_PORT_3 (1), .AVL_ADDR_WIDTH_PORT_3 (1), .AVL_NUM_SYMBOLS_PORT_3 (1), .LSB_WFIFO_PORT_3 (5), .MSB_WFIFO_PORT_3 (5), .LSB_RFIFO_PORT_3 (5), .MSB_RFIFO_PORT_3 (5), .AVL_DATA_WIDTH_PORT_4 (1), .AVL_ADDR_WIDTH_PORT_4 (1), .AVL_NUM_SYMBOLS_PORT_4 (1), .LSB_WFIFO_PORT_4 (5), .MSB_WFIFO_PORT_4 (5), .LSB_RFIFO_PORT_4 (5), .MSB_RFIFO_PORT_4 (5), .AVL_DATA_WIDTH_PORT_5 (1), .AVL_ADDR_WIDTH_PORT_5 (1), .AVL_NUM_SYMBOLS_PORT_5 (1), .LSB_WFIFO_PORT_5 (5), .MSB_WFIFO_PORT_5 (5), .LSB_RFIFO_PORT_5 (5), .MSB_RFIFO_PORT_5 (5), .ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"), .ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"), .ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"), .ENUM_CAL_REQ ("DISABLED"), .ENUM_CFG_BURST_LENGTH ("BL_8"), .ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"), .ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"), .ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"), .ENUM_CFG_TYPE ("DDR3"), .ENUM_CLOCK_OFF_0 ("DISABLED"), .ENUM_CLOCK_OFF_1 ("DISABLED"), .ENUM_CLOCK_OFF_2 ("DISABLED"), .ENUM_CLOCK_OFF_3 ("DISABLED"), .ENUM_CLOCK_OFF_4 ("DISABLED"), .ENUM_CLOCK_OFF_5 ("DISABLED"), .ENUM_CLR_INTR ("NO_CLR_INTR"), .ENUM_CMD_PORT_IN_USE_0 ("FALSE"), .ENUM_CMD_PORT_IN_USE_1 ("FALSE"), .ENUM_CMD_PORT_IN_USE_2 ("FALSE"), .ENUM_CMD_PORT_IN_USE_3 ("FALSE"), .ENUM_CMD_PORT_IN_USE_4 ("FALSE"), .ENUM_CMD_PORT_IN_USE_5 ("FALSE"), .ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT0_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT0_TYPE ("DISABLE"), .ENUM_CPORT0_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT1_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT1_TYPE ("DISABLE"), .ENUM_CPORT1_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT2_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT2_TYPE ("DISABLE"), .ENUM_CPORT2_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT3_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT3_TYPE ("DISABLE"), .ENUM_CPORT3_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT4_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT4_TYPE ("DISABLE"), .ENUM_CPORT4_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT5_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT5_TYPE ("DISABLE"), .ENUM_CPORT5_WFIFO_MAP ("FIFO_0"), .ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"), .ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"), .ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"), .ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"), .ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"), .ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"), .ENUM_DELAY_BONDING ("BONDING_LATENCY_0"), .ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"), .ENUM_DISABLE_MERGING ("MERGING_ENABLED"), .ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"), .ENUM_ENABLE_ATPG ("DISABLED"), .ENUM_ENABLE_BONDING_0 ("DISABLED"), .ENUM_ENABLE_BONDING_1 ("DISABLED"), .ENUM_ENABLE_BONDING_2 ("DISABLED"), .ENUM_ENABLE_BONDING_3 ("DISABLED"), .ENUM_ENABLE_BONDING_4 ("DISABLED"), .ENUM_ENABLE_BONDING_5 ("DISABLED"), .ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"), .ENUM_ENABLE_DQS_TRACKING ("ENABLED"), .ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"), .ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"), .ENUM_ENABLE_INTR ("DISABLED"), .ENUM_ENABLE_NO_DM ("DISABLED"), .ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"), .ENUM_GANGED_ARF ("DISABLED"), .ENUM_GEN_DBE ("GEN_DBE_DISABLED"), .ENUM_GEN_SBE ("GEN_SBE_DISABLED"), .ENUM_INC_SYNC ("FIFO_SET_2"), .ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"), .ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"), .ENUM_MASK_DBE_INTR ("DISABLED"), .ENUM_MASK_SBE_INTR ("DISABLED"), .ENUM_MEM_IF_AL ("AL_0"), .ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"), .ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"), .ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"), .ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"), .ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"), .ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"), .ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"), .ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"), .ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"), .ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"), .ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"), .ENUM_MEM_IF_TCCD ("TCCD_4"), .ENUM_MEM_IF_TCL ("TCL_7"), .ENUM_MEM_IF_TCWL ("TCWL_7"), .ENUM_MEM_IF_TFAW ("TFAW_15"), .ENUM_MEM_IF_TMRD ("TMRD_4"), .ENUM_MEM_IF_TRAS ("TRAS_14"), .ENUM_MEM_IF_TRC ("TRC_20"), .ENUM_MEM_IF_TRCD ("TRCD_6"), .ENUM_MEM_IF_TRP ("TRP_6"), .ENUM_MEM_IF_TRRD ("TRRD_3"), .ENUM_MEM_IF_TRTP ("TRTP_3"), .ENUM_MEM_IF_TWR ("TWR_6"), .ENUM_MEM_IF_TWTR ("TWTR_4"), .ENUM_MMR_CFG_MEM_BL ("MP_BL_8"), .ENUM_OUTPUT_REGD ("DISABLED"), .ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"), .ENUM_PORT0_WIDTH ("PORT_32_BIT"), .ENUM_PORT1_WIDTH ("PORT_32_BIT"), .ENUM_PORT2_WIDTH ("PORT_32_BIT"), .ENUM_PORT3_WIDTH ("PORT_32_BIT"), .ENUM_PORT4_WIDTH ("PORT_32_BIT"), .ENUM_PORT5_WIDTH ("PORT_32_BIT"), .ENUM_PRIORITY_0_0 ("WEIGHT_0"), .ENUM_PRIORITY_0_1 ("WEIGHT_0"), .ENUM_PRIORITY_0_2 ("WEIGHT_0"), .ENUM_PRIORITY_0_3 ("WEIGHT_0"), .ENUM_PRIORITY_0_4 ("WEIGHT_0"), .ENUM_PRIORITY_0_5 ("WEIGHT_0"), .ENUM_PRIORITY_1_0 ("WEIGHT_0"), .ENUM_PRIORITY_1_1 ("WEIGHT_0"), .ENUM_PRIORITY_1_2 ("WEIGHT_0"), .ENUM_PRIORITY_1_3 ("WEIGHT_0"), .ENUM_PRIORITY_1_4 ("WEIGHT_0"), .ENUM_PRIORITY_1_5 ("WEIGHT_0"), .ENUM_PRIORITY_2_0 ("WEIGHT_0"), .ENUM_PRIORITY_2_1 ("WEIGHT_0"), .ENUM_PRIORITY_2_2 ("WEIGHT_0"), .ENUM_PRIORITY_2_3 ("WEIGHT_0"), .ENUM_PRIORITY_2_4 ("WEIGHT_0"), .ENUM_PRIORITY_2_5 ("WEIGHT_0"), .ENUM_PRIORITY_3_0 ("WEIGHT_0"), .ENUM_PRIORITY_3_1 ("WEIGHT_0"), .ENUM_PRIORITY_3_2 ("WEIGHT_0"), .ENUM_PRIORITY_3_3 ("WEIGHT_0"), .ENUM_PRIORITY_3_4 ("WEIGHT_0"), .ENUM_PRIORITY_3_5 ("WEIGHT_0"), .ENUM_PRIORITY_4_0 ("WEIGHT_0"), .ENUM_PRIORITY_4_1 ("WEIGHT_0"), .ENUM_PRIORITY_4_2 ("WEIGHT_0"), .ENUM_PRIORITY_4_3 ("WEIGHT_0"), .ENUM_PRIORITY_4_4 ("WEIGHT_0"), .ENUM_PRIORITY_4_5 ("WEIGHT_0"), .ENUM_PRIORITY_5_0 ("WEIGHT_0"), .ENUM_PRIORITY_5_1 ("WEIGHT_0"), .ENUM_PRIORITY_5_2 ("WEIGHT_0"), .ENUM_PRIORITY_5_3 ("WEIGHT_0"), .ENUM_PRIORITY_5_4 ("WEIGHT_0"), .ENUM_PRIORITY_5_5 ("WEIGHT_0"), .ENUM_PRIORITY_6_0 ("WEIGHT_0"), .ENUM_PRIORITY_6_1 ("WEIGHT_0"), .ENUM_PRIORITY_6_2 ("WEIGHT_0"), .ENUM_PRIORITY_6_3 ("WEIGHT_0"), .ENUM_PRIORITY_6_4 ("WEIGHT_0"), .ENUM_PRIORITY_6_5 ("WEIGHT_0"), .ENUM_PRIORITY_7_0 ("WEIGHT_0"), .ENUM_PRIORITY_7_1 ("WEIGHT_0"), .ENUM_PRIORITY_7_2 ("WEIGHT_0"), .ENUM_PRIORITY_7_3 ("WEIGHT_0"), .ENUM_PRIORITY_7_4 ("WEIGHT_0"), .ENUM_PRIORITY_7_5 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"), .ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"), .ENUM_RD_DWIDTH_0 ("DWIDTH_0"), .ENUM_RD_DWIDTH_1 ("DWIDTH_0"), .ENUM_RD_DWIDTH_2 ("DWIDTH_0"), .ENUM_RD_DWIDTH_3 ("DWIDTH_0"), .ENUM_RD_DWIDTH_4 ("DWIDTH_0"), .ENUM_RD_DWIDTH_5 ("DWIDTH_0"), .ENUM_RD_FIFO_IN_USE_0 ("FALSE"), .ENUM_RD_FIFO_IN_USE_1 ("FALSE"), .ENUM_RD_FIFO_IN_USE_2 ("FALSE"), .ENUM_RD_FIFO_IN_USE_3 ("FALSE"), .ENUM_RD_PORT_INFO_0 ("USE_NO"), .ENUM_RD_PORT_INFO_1 ("USE_NO"), .ENUM_RD_PORT_INFO_2 ("USE_NO"), .ENUM_RD_PORT_INFO_3 ("USE_NO"), .ENUM_RD_PORT_INFO_4 ("USE_NO"), .ENUM_RD_PORT_INFO_5 ("USE_NO"), .ENUM_READ_ODT_CHIP ("ODT_DISABLED"), .ENUM_REORDER_DATA ("DATA_REORDERING"), .ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"), .ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"), .ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"), .ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"), .ENUM_TEST_MODE ("NORMAL_MODE"), .ENUM_THLD_JAR1_0 ("THRESHOLD_32"), .ENUM_THLD_JAR1_1 ("THRESHOLD_32"), .ENUM_THLD_JAR1_2 ("THRESHOLD_32"), .ENUM_THLD_JAR1_3 ("THRESHOLD_32"), .ENUM_THLD_JAR1_4 ("THRESHOLD_32"), .ENUM_THLD_JAR1_5 ("THRESHOLD_32"), .ENUM_THLD_JAR2_0 ("THRESHOLD_16"), .ENUM_THLD_JAR2_1 ("THRESHOLD_16"), .ENUM_THLD_JAR2_2 ("THRESHOLD_16"), .ENUM_THLD_JAR2_3 ("THRESHOLD_16"), .ENUM_THLD_JAR2_4 ("THRESHOLD_16"), .ENUM_THLD_JAR2_5 ("THRESHOLD_16"), .ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"), .ENUM_USER_ECC_EN ("DISABLE"), .ENUM_USER_PRIORITY_0 ("PRIORITY_1"), .ENUM_USER_PRIORITY_1 ("PRIORITY_1"), .ENUM_USER_PRIORITY_2 ("PRIORITY_1"), .ENUM_USER_PRIORITY_3 ("PRIORITY_1"), .ENUM_USER_PRIORITY_4 ("PRIORITY_1"), .ENUM_USER_PRIORITY_5 ("PRIORITY_1"), .ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WR_DWIDTH_0 ("DWIDTH_0"), .ENUM_WR_DWIDTH_1 ("DWIDTH_0"), .ENUM_WR_DWIDTH_2 ("DWIDTH_0"), .ENUM_WR_DWIDTH_3 ("DWIDTH_0"), .ENUM_WR_DWIDTH_4 ("DWIDTH_0"), .ENUM_WR_DWIDTH_5 ("DWIDTH_0"), .ENUM_WR_FIFO_IN_USE_0 ("FALSE"), .ENUM_WR_FIFO_IN_USE_1 ("FALSE"), .ENUM_WR_FIFO_IN_USE_2 ("FALSE"), .ENUM_WR_FIFO_IN_USE_3 ("FALSE"), .ENUM_WR_PORT_INFO_0 ("USE_NO"), .ENUM_WR_PORT_INFO_1 ("USE_NO"), .ENUM_WR_PORT_INFO_2 ("USE_NO"), .ENUM_WR_PORT_INFO_3 ("USE_NO"), .ENUM_WR_PORT_INFO_4 ("USE_NO"), .ENUM_WR_PORT_INFO_5 ("USE_NO"), .ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"), .INTG_MEM_AUTO_PD_CYCLES (0), .INTG_CYC_TO_RLD_JARS_0 (1), .INTG_CYC_TO_RLD_JARS_1 (1), .INTG_CYC_TO_RLD_JARS_2 (1), .INTG_CYC_TO_RLD_JARS_3 (1), .INTG_CYC_TO_RLD_JARS_4 (1), .INTG_CYC_TO_RLD_JARS_5 (1), .INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0), .INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0), .INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0), .INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0), .INTG_EXTRA_CTL_CLK_ARF_PERIOD (0), .INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0), .INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0), .INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0), .INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0), .INTG_EXTRA_CTL_CLK_PDN_PERIOD (0), .INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0), .INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0), .INTG_EXTRA_CTL_CLK_RD_TO_PCH (0), .INTG_EXTRA_CTL_CLK_RD_TO_RD (0), .INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0), .INTG_EXTRA_CTL_CLK_RD_TO_WR (2), .INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2), .INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2), .INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0), .INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0), .INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0), .INTG_EXTRA_CTL_CLK_WR_TO_PCH (0), .INTG_EXTRA_CTL_CLK_WR_TO_RD (3), .INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3), .INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3), .INTG_EXTRA_CTL_CLK_WR_TO_WR (0), .INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0), .INTG_MEM_IF_TREFI (3120), .INTG_MEM_IF_TRFC (120), .INTG_RCFG_SUM_WT_PRIORITY_0 (0), .INTG_RCFG_SUM_WT_PRIORITY_1 (0), .INTG_RCFG_SUM_WT_PRIORITY_2 (0), .INTG_RCFG_SUM_WT_PRIORITY_3 (0), .INTG_RCFG_SUM_WT_PRIORITY_4 (0), .INTG_RCFG_SUM_WT_PRIORITY_5 (0), .INTG_RCFG_SUM_WT_PRIORITY_6 (0), .INTG_RCFG_SUM_WT_PRIORITY_7 (0), .INTG_SUM_WT_PRIORITY_0 (0), .INTG_SUM_WT_PRIORITY_1 (0), .INTG_SUM_WT_PRIORITY_2 (0), .INTG_SUM_WT_PRIORITY_3 (0), .INTG_SUM_WT_PRIORITY_4 (0), .INTG_SUM_WT_PRIORITY_5 (0), .INTG_SUM_WT_PRIORITY_6 (0), .INTG_SUM_WT_PRIORITY_7 (0), .INTG_POWER_SAVING_EXIT_CYCLES (5), .INTG_MEM_CLK_ENTRY_CYCLES (10), .ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"), .ENUM_ENABLE_BURST_TERMINATE ("DISABLED"), .AFI_RATE_RATIO (1), .AFI_ADDR_WIDTH (15), .AFI_BANKADDR_WIDTH (3), .AFI_CONTROL_WIDTH (1), .AFI_CS_WIDTH (1), .AFI_DM_WIDTH (8), .AFI_DQ_WIDTH (64), .AFI_ODT_WIDTH (1), .AFI_WRITE_DQS_WIDTH (4), .AFI_RLAT_WIDTH (6), .AFI_WLAT_WIDTH (6), .HARD_PHY (1) ) c0 ( .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk .local_init_done (), // status.local_init_done .local_cal_success (), // .local_cal_success .local_cal_fail (), // .local_cal_fail .afi_addr (c0_afi_afi_addr), // afi.afi_addr .afi_ba (c0_afi_afi_ba), // .afi_ba .afi_cke (c0_afi_afi_cke), // .afi_cke .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n .afi_we_n (c0_afi_afi_we_n), // .afi_we_n .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n .afi_odt (c0_afi_afi_odt), // .afi_odt .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable .afi_init_req (), // .afi_init_req .afi_cal_req (), // .afi_cal_req .afi_seq_busy (), // .afi_seq_busy .afi_ctl_refresh_done (), // .afi_ctl_refresh_done .afi_ctl_long_idle (), // .afi_ctl_long_idle .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid .afi_wdata (c0_afi_afi_wdata), // .afi_wdata .afi_dm (c0_afi_afi_dm), // .afi_dm .afi_rdata (p0_afi_afi_rdata), // .afi_rdata .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid .afi_wlat (p0_afi_afi_wlat), // .afi_wlat .afi_rlat (p0_afi_afi_rlat), // .afi_rlat .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess .mp_cmd_clk_0 (1'b0), // (terminated) .mp_cmd_reset_n_0 (1'b1), // (terminated) .mp_cmd_clk_1 (1'b0), // (terminated) .mp_cmd_reset_n_1 (1'b1), // (terminated) .mp_cmd_clk_2 (1'b0), // (terminated) .mp_cmd_reset_n_2 (1'b1), // (terminated) .mp_cmd_clk_3 (1'b0), // (terminated) .mp_cmd_reset_n_3 (1'b1), // (terminated) .mp_cmd_clk_4 (1'b0), // (terminated) .mp_cmd_reset_n_4 (1'b1), // (terminated) .mp_cmd_clk_5 (1'b0), // (terminated) .mp_cmd_reset_n_5 (1'b1), // (terminated) .mp_rfifo_clk_0 (1'b0), // (terminated) .mp_rfifo_reset_n_0 (1'b1), // (terminated) .mp_wfifo_clk_0 (1'b0), // (terminated) .mp_wfifo_reset_n_0 (1'b1), // (terminated) .mp_rfifo_clk_1 (1'b0), // (terminated) .mp_rfifo_reset_n_1 (1'b1), // (terminated) .mp_wfifo_clk_1 (1'b0), // (terminated) .mp_wfifo_reset_n_1 (1'b1), // (terminated) .mp_rfifo_clk_2 (1'b0), // (terminated) .mp_rfifo_reset_n_2 (1'b1), // (terminated) .mp_wfifo_clk_2 (1'b0), // (terminated) .mp_wfifo_reset_n_2 (1'b1), // (terminated) .mp_rfifo_clk_3 (1'b0), // (terminated) .mp_rfifo_reset_n_3 (1'b1), // (terminated) .mp_wfifo_clk_3 (1'b0), // (terminated) .mp_wfifo_reset_n_3 (1'b1), // (terminated) .csr_clk (1'b0), // (terminated) .csr_reset_n (1'b1), // (terminated) .avl_ready_0 (), // (terminated) .avl_burstbegin_0 (1'b0), // (terminated) .avl_addr_0 (1'b0), // (terminated) .avl_rdata_valid_0 (), // (terminated) .avl_rdata_0 (), // (terminated) .avl_wdata_0 (1'b0), // (terminated) .avl_be_0 (1'b0), // (terminated) .avl_read_req_0 (1'b0), // (terminated) .avl_write_req_0 (1'b0), // (terminated) .avl_size_0 (3'b000), // (terminated) .avl_ready_1 (), // (terminated) .avl_burstbegin_1 (1'b0), // (terminated) .avl_addr_1 (1'b0), // (terminated) .avl_rdata_valid_1 (), // (terminated) .avl_rdata_1 (), // (terminated) .avl_wdata_1 (1'b0), // (terminated) .avl_be_1 (1'b0), // (terminated) .avl_read_req_1 (1'b0), // (terminated) .avl_write_req_1 (1'b0), // (terminated) .avl_size_1 (3'b000), // (terminated) .avl_ready_2 (), // (terminated) .avl_burstbegin_2 (1'b0), // (terminated) .avl_addr_2 (1'b0), // (terminated) .avl_rdata_valid_2 (), // (terminated) .avl_rdata_2 (), // (terminated) .avl_wdata_2 (1'b0), // (terminated) .avl_be_2 (1'b0), // (terminated) .avl_read_req_2 (1'b0), // (terminated) .avl_write_req_2 (1'b0), // (terminated) .avl_size_2 (3'b000), // (terminated) .avl_ready_3 (), // (terminated) .avl_burstbegin_3 (1'b0), // (terminated) .avl_addr_3 (1'b0), // (terminated) .avl_rdata_valid_3 (), // (terminated) .avl_rdata_3 (), // (terminated) .avl_wdata_3 (1'b0), // (terminated) .avl_be_3 (1'b0), // (terminated) .avl_read_req_3 (1'b0), // (terminated) .avl_write_req_3 (1'b0), // (terminated) .avl_size_3 (3'b000), // (terminated) .avl_ready_4 (), // (terminated) .avl_burstbegin_4 (1'b0), // (terminated) .avl_addr_4 (1'b0), // (terminated) .avl_rdata_valid_4 (), // (terminated) .avl_rdata_4 (), // (terminated) .avl_wdata_4 (1'b0), // (terminated) .avl_be_4 (1'b0), // (terminated) .avl_read_req_4 (1'b0), // (terminated) .avl_write_req_4 (1'b0), // (terminated) .avl_size_4 (3'b000), // (terminated) .avl_ready_5 (), // (terminated) .avl_burstbegin_5 (1'b0), // (terminated) .avl_addr_5 (1'b0), // (terminated) .avl_rdata_valid_5 (), // (terminated) .avl_rdata_5 (), // (terminated) .avl_wdata_5 (1'b0), // (terminated) .avl_be_5 (1'b0), // (terminated) .avl_read_req_5 (1'b0), // (terminated) .avl_write_req_5 (1'b0), // (terminated) .avl_size_5 (3'b000), // (terminated) .csr_write_req (1'b0), // (terminated) .csr_read_req (1'b0), // (terminated) .csr_waitrequest (), // (terminated) .csr_addr (10'b0000000000), // (terminated) .csr_be (1'b0), // (terminated) .csr_wdata (8'b00000000), // (terminated) .csr_rdata (), // (terminated) .csr_rdata_valid (), // (terminated) .local_multicast (1'b0), // (terminated) .local_refresh_req (1'b0), // (terminated) .local_refresh_chip (1'b0), // (terminated) .local_refresh_ack (), // (terminated) .local_self_rfsh_req (1'b0), // (terminated) .local_self_rfsh_chip (1'b0), // (terminated) .local_self_rfsh_ack (), // (terminated) .local_deep_powerdn_req (1'b0), // (terminated) .local_deep_powerdn_chip (1'b0), // (terminated) .local_deep_powerdn_ack (), // (terminated) .local_powerdn_ack (), // (terminated) .local_priority (1'b0), // (terminated) .bonding_in_1 (4'b0000), // (terminated) .bonding_in_2 (6'b000000), // (terminated) .bonding_in_3 (6'b000000), // (terminated) .bonding_out_1 (), // (terminated) .bonding_out_2 (), // (terminated) .bonding_out_3 () // (terminated) ); altera_mem_if_oct_cyclonev #( .OCT_TERM_CONTROL_WIDTH (16) ) oct ( .oct_rzqin (oct_rzqin), // oct.rzqin .seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol .parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol ); altera_mem_if_dll_cyclonev #( .DLL_DELAY_CTRL_WIDTH (7), .DLL_OFFSET_CTRL_WIDTH (6), .DELAY_BUFFER_MODE ("HIGH"), .DELAY_CHAIN_LENGTH (8), .DLL_INPUT_FREQUENCY_PS_STR ("2500 ps") ) dll ( .clk (p0_dll_clk_clk), // clk.clk .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked .dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl ); endmodule

// (C) 2001-2017 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License Subscription // Agreement, Intel FPGA IP License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Intel and sold by // Intel or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/17.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2017/08/13 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 || (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) | out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__O311A_TB_V `define SKY130_FD_SC_LP__O311A_TB_V /** * o311a: 3-input OR into 3-input AND. * * X = ((A1 | A2 | A3) & B1 & C1) * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_lp__o311a.v" module top(); // Inputs are registered reg A1; reg A2; reg A3; reg B1; reg C1; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire X; initial begin // Initial state is x for all inputs. A1 = 1'bX; A2 = 1'bX; A3 = 1'bX; B1 = 1'bX; C1 = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 A1 = 1'b0; #40 A2 = 1'b0; #60 A3 = 1'b0; #80 B1 = 1'b0; #100 C1 = 1'b0; #120 VGND = 1'b0; #140 VNB = 1'b0; #160 VPB = 1'b0; #180 VPWR = 1'b0; #200 A1 = 1'b1; #220 A2 = 1'b1; #240 A3 = 1'b1; #260 B1 = 1'b1; #280 C1 = 1'b1; #300 VGND = 1'b1; #320 VNB = 1'b1; #340 VPB = 1'b1; #360 VPWR = 1'b1; #380 A1 = 1'b0; #400 A2 = 1'b0; #420 A3 = 1'b0; #440 B1 = 1'b0; #460 C1 = 1'b0; #480 VGND = 1'b0; #500 VNB = 1'b0; #520 VPB = 1'b0; #540 VPWR = 1'b0; #560 VPWR = 1'b1; #580 VPB = 1'b1; #600 VNB = 1'b1; #620 VGND = 1'b1; #640 C1 = 1'b1; #660 B1 = 1'b1; #680 A3 = 1'b1; #700 A2 = 1'b1; #720 A1 = 1'b1; #740 VPWR = 1'bx; #760 VPB = 1'bx; #780 VNB = 1'bx; #800 VGND = 1'bx; #820 C1 = 1'bx; #840 B1 = 1'bx; #860 A3 = 1'bx; #880 A2 = 1'bx; #900 A1 = 1'bx; end sky130_fd_sc_lp__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X)); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__O311A_TB_V

//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_7x_v1_3_pipe_rate.v // Version : 1.3 //------------------------------------------------------------------------------ // Filename : pipe_rate.v // Description : PIPE Rate Module for 7 Series Transceiver // Version : 11.4 //------------------------------------------------------------------------------ `timescale 1ns / 1ps //---------- PIPE Rate Module -------------------------------------------------- module pcie_7x_v1_3_pipe_rate # ( parameter PCIE_USE_MODE = "1.1", // PCIe use mode parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max ) ( //---------- Input ------------------------------------- input RATE_CLK, input RATE_RST_N, input RATE_RST_IDLE, input [ 1:0] RATE_RATE_IN, input RATE_CPLLLOCK, input RATE_QPLLLOCK, input RATE_MMCM_LOCK, input RATE_DRP_DONE, input RATE_TXRESETDONE, input RATE_RXRESETDONE, input RATE_TXRATEDONE, input RATE_RXRATEDONE, input RATE_PHYSTATUS, input RATE_RESETOVRD_DONE, input RATE_TXSYNC_DONE, input RATE_RXSYNC_DONE, //---------- Output ------------------------------------ output RATE_CPLLPD, output RATE_QPLLPD, output RATE_CPLLRESET, output RATE_QPLLRESET, output RATE_TXPMARESET, output RATE_RXPMARESET, output RATE_DRP_START, output [ 1:0] RATE_SYSCLKSEL, output RATE_PCLK_SEL, output RATE_GEN3, output [ 2:0] RATE_RATE_OUT, output RATE_RESETOVRD_START, output RATE_TXSYNC_START, output RATE_DONE, output RATE_RXSYNC_START, output RATE_RXSYNC, output RATE_IDLE, output [23:0] RATE_FSM ); //---------- Input FF or Buffer ------------------------ reg rst_idle_reg1; reg [ 1:0] rate_in_reg1; reg cplllock_reg1; reg qplllock_reg1; reg mmcm_lock_reg1; reg drp_done_reg1; reg txresetdone_reg1; reg rxresetdone_reg1; reg txratedone_reg1; reg rxratedone_reg1; reg phystatus_reg1; reg resetovrd_done_reg1; reg txsync_done_reg1; reg rxsync_done_reg1; reg rst_idle_reg2; reg [ 1:0] rate_in_reg2; reg cplllock_reg2; reg qplllock_reg2; reg mmcm_lock_reg2; reg drp_done_reg2; reg txresetdone_reg2; reg rxresetdone_reg2; reg txratedone_reg2; reg rxratedone_reg2; reg phystatus_reg2; reg resetovrd_done_reg2; reg txsync_done_reg2; reg rxsync_done_reg2; //---------- Internal Signals -------------------------- wire pll_lock; wire [ 2:0] rate; reg [ 3:0] txdata_wait_cnt = 4'd0; reg txratedone = 1'd0; reg rxratedone = 1'd0; reg phystatus = 1'd0; reg ratedone = 1'd0; reg gen3_exit = 1'd0; //---------- Output FF or Buffer ----------------------- reg cpllpd = 1'd0; reg qpllpd = 1'd0; reg cpllreset = 1'd0; reg qpllreset = 1'd0; reg txpmareset = 1'd0; reg rxpmareset = 1'd0; reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; reg gen3 = 1'd0; reg pclk_sel = 1'd0; reg [ 2:0] rate_out = 3'd0; reg [23:0] fsm = 24'd0; //---------- FSM --------------------------------------- localparam FSM_IDLE = 24'b000000000000000000000001; localparam FSM_PLL_PU = 24'b000000000000000000000010; // Gen 3 only localparam FSM_PLL_PURESET = 24'b000000000000000000000100; // Gen 3 only localparam FSM_PLL_LOCK = 24'b000000000000000000001000; // Gen 3 or reset only localparam FSM_PMARESET_HOLD = 24'b000000000000000000010000; // Gen 3 or reset only localparam FSM_PLL_SEL = 24'b000000000000000000100000; // Gen 3 or reset only localparam FSM_MMCM_LOCK = 24'b000000000000000001000000; // Gen 3 or reset only localparam FSM_DRP_START = 24'b000000000000000010000000; // Gen 3 or reset only localparam FSM_DRP_DONE = 24'b000000000000000100000000; // Gen 3 or reset only localparam FSM_PMARESET_RELEASE = 24'b000000000000001000000000; // Gen 3 only localparam FSM_PMARESET_DONE = 24'b000000000000010000000000; // Gen 3 only localparam FSM_TXDATA_WAIT = 24'b000000000000100000000000; localparam FSM_PCLK_SEL = 24'b000000000001000000000000; localparam FSM_RATE_SEL = 24'b000000000010000000000000; localparam FSM_RATE_DONE = 24'b000000000100000000000000; localparam FSM_RESETOVRD_START = 24'b000000001000000000000000; // PCIe use mode 1.0 only localparam FSM_RESETOVRD_DONE = 24'b000000010000000000000000; // PCIe use mode 1.0 only localparam FSM_PLL_PDRESET = 24'b000000100000000000000000; localparam FSM_PLL_PD = 24'b000001000000000000000000; localparam FSM_TXSYNC_START = 24'b000010000000000000000000; localparam FSM_TXSYNC_DONE = 24'b000100000000000000000000; localparam FSM_DONE = 24'b001000000000000000000000; // Must sync value to pipe_user.v localparam FSM_RXSYNC_START = 24'b010000000000000000000000; // Gen 3 only localparam FSM_RXSYNC_DONE = 24'b100000000000000000000000; // Gen 3 only //---------- Input FF ---------------------------------------------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) begin //---------- 1st Stage FF -------------------------- rst_idle_reg1 <= 1'd0; rate_in_reg1 <= 2'd0; cplllock_reg1 <= 1'd0; qplllock_reg1 <= 1'd0; mmcm_lock_reg1 <= 1'd0; drp_done_reg1 <= 1'd0; txresetdone_reg1 <= 1'd0; rxresetdone_reg1 <= 1'd0; txratedone_reg1 <= 1'd0; rxratedone_reg1 <= 1'd0; phystatus_reg1 <= 1'd0; resetovrd_done_reg1 <= 1'd0; txsync_done_reg1 <= 1'd0; rxsync_done_reg1 <= 1'd0; //---------- 2nd Stage FF -------------------------- rst_idle_reg2 <= 1'd0; rate_in_reg2 <= 2'd0; cplllock_reg2 <= 1'd0; qplllock_reg2 <= 1'd0; mmcm_lock_reg2 <= 1'd0; drp_done_reg2 <= 1'd0; txresetdone_reg2 <= 1'd0; rxresetdone_reg2 <= 1'd0; txratedone_reg2 <= 1'd0; rxratedone_reg2 <= 1'd0; phystatus_reg2 <= 1'd0; resetovrd_done_reg2 <= 1'd0; txsync_done_reg2 <= 1'd0; rxsync_done_reg2 <= 1'd0; end else begin //---------- 1st Stage FF -------------------------- rst_idle_reg1 <= RATE_RST_IDLE; rate_in_reg1 <= RATE_RATE_IN; cplllock_reg1 <= RATE_CPLLLOCK; qplllock_reg1 <= RATE_QPLLLOCK; mmcm_lock_reg1 <= RATE_MMCM_LOCK; drp_done_reg1 <= RATE_DRP_DONE; txresetdone_reg1 <= RATE_TXRESETDONE; rxresetdone_reg1 <= RATE_RXRESETDONE; txratedone_reg1 <= RATE_TXRATEDONE; rxratedone_reg1 <= RATE_RXRATEDONE; phystatus_reg1 <= RATE_PHYSTATUS; resetovrd_done_reg1 <= RATE_RESETOVRD_DONE; txsync_done_reg1 <= RATE_TXSYNC_DONE; rxsync_done_reg1 <= RATE_RXSYNC_DONE; //---------- 2nd Stage FF -------------------------- rst_idle_reg2 <= rst_idle_reg1; rate_in_reg2 <= rate_in_reg1; cplllock_reg2 <= cplllock_reg1; qplllock_reg2 <= qplllock_reg1; mmcm_lock_reg2 <= mmcm_lock_reg1; drp_done_reg2 <= drp_done_reg1; txresetdone_reg2 <= txresetdone_reg1; rxresetdone_reg2 <= rxresetdone_reg1; txratedone_reg2 <= txratedone_reg1; rxratedone_reg2 <= rxratedone_reg1; phystatus_reg2 <= phystatus_reg1; resetovrd_done_reg2 <= resetovrd_done_reg1; txsync_done_reg2 <= txsync_done_reg1; rxsync_done_reg2 <= rxsync_done_reg1; end end //---------- Select CPLL or QPLL Lock ------------------------------------------ // Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock // Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock // Gen3 : Wait for QPLL lock //------------------------------------------------------------------------------ assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2; //---------- Select Rate ------------------------------------------------------- // Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2 // Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1 // Gen3 : Div 1 using [TX/RX]OUT_DIV = 1 //------------------------------------------------------------------------------ assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 : (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0; //---------- TXDATA Wait Counter ----------------------------------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) txdata_wait_cnt <= 4'd0; else //---------- Increment Wait Counter ---------------- if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX)) txdata_wait_cnt <= txdata_wait_cnt + 4'd1; //---------- Hold Wait Counter --------------------- else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX)) txdata_wait_cnt <= txdata_wait_cnt; //---------- Reset Wait Counter -------------------- else txdata_wait_cnt <= 4'd0; end //---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS ----------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) begin txratedone <= 1'd0; rxratedone <= 1'd0; phystatus <= 1'd0; ratedone <= 1'd0; end else begin if (fsm == FSM_RATE_DONE) begin //---------- Latch TXRATEDONE ------------------ if (txratedone_reg2) txratedone <= 1'd1; else txratedone <= txratedone; //---------- Latch RXRATEDONE ------------------ if (rxratedone_reg2) rxratedone <= 1'd1; else rxratedone <= rxratedone; //---------- Latch PHYSTATUS ------------------- if (phystatus_reg2) phystatus <= 1'd1; else phystatus <= phystatus; //---------- Latch Rate Done ------------------- if (rxratedone && txratedone && phystatus) ratedone <= 1'd1; else ratedone <= ratedone; end else begin txratedone <= 1'd0; rxratedone <= 1'd0; phystatus <= 1'd0; ratedone <= 1'd0; end end end //---------- PIPE Rate FSM ----------------------------------------------------- always @ (posedge RATE_CLK) begin if (!RATE_RST_N) begin fsm <= FSM_PLL_LOCK; gen3_exit <= 1'd0; cpllpd <= 1'd0; qpllpd <= 1'd0; cpllreset <= 1'd0; qpllreset <= 1'd0; txpmareset <= 1'd0; rxpmareset <= 1'd0; sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; pclk_sel <= 1'd0; gen3 <= 1'd0; rate_out <= 3'd0; end else begin case (fsm) //---------- Idle State ---------------------------- FSM_IDLE : begin //---------- Detect Rate Change ---------------- if (rate_in_reg2 != rate_in_reg1) begin fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT; gen3_exit <= (rate_in_reg2 == 2'd2); cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end else begin fsm <= FSM_IDLE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end end //---------- Power-up PLL -------------------------- FSM_PLL_PU : begin fsm <= FSM_PLL_PURESET; gen3_exit <= gen3_exit; cpllpd <= (PCIE_PLL_SEL == "QPLL"); qpllpd <= 1'd0; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Release PLL Resets -------------------- FSM_PLL_PURESET : begin fsm <= FSM_PLL_LOCK; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= (PCIE_PLL_SEL == "QPLL"); qpllreset <= 1'd0; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for PLL Lock --------------------- FSM_PLL_LOCK : begin fsm <= (pll_lock ? FSM_PMARESET_HOLD : FSM_PLL_LOCK); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Hold both PMA in Reset ---------------- // Gen1 : Release PMA Reset // Gen2 : Release PMA Reset // Gen3 : Hold PMA Reset //-------------------------------------------------- FSM_PMARESET_HOLD : begin fsm <= FSM_PLL_SEL; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit); rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit); sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Select PLL ---------------------------- // Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL // Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL // Gen3 : QPLL //-------------------------------------------------- FSM_PLL_SEL : begin fsm <= FSM_MMCM_LOCK; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Check for MMCM Lock ------------------- FSM_MMCM_LOCK : begin fsm <= (mmcm_lock_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Start DRP ----------------------------- FSM_DRP_START: begin fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2)); gen3 <= (rate_in_reg2 == 2'd2); rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out); end //---------- Wait for DRP Done --------------------- FSM_DRP_DONE : begin fsm <= (drp_done_reg2 ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Release PMA Resets -------------------- FSM_PMARESET_RELEASE : begin fsm <= FSM_PMARESET_DONE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= 1'd0; rxpmareset <= 1'd0; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion FSM_PMARESET_DONE : begin fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2)) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for TXDATA to TX[P/N] Latency ---- FSM_TXDATA_WAIT : begin fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Select PCLK Frequency ----------------- // Gen1 : PCLK = 125 MHz // Gen2 : PCLK = 250 MHz // Gen3 : PCLK = 250 MHz //-------------------------------------------------- FSM_PCLK_SEL : begin fsm <= FSM_RATE_SEL; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2)); gen3 <= gen3; rate_out <= rate_out; end //---------- Select Rate --------------------------- FSM_RATE_SEL : begin fsm <= FSM_RATE_DONE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate; // Update [TX/RX]RATE end //---------- Wait for Rate Change Done ------------- FSM_RATE_DONE : begin if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit)) if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit)) fsm <= FSM_RESETOVRD_START; else fsm <= FSM_PLL_PDRESET; else fsm <= FSM_RATE_DONE; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Reset Override Start ------------------ FSM_RESETOVRD_START: begin fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Reset Override Done ------------------- FSM_RESETOVRD_DONE : begin fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Hold PLL Not Used in Reset ------------ FSM_PLL_PDRESET : begin fsm <= FSM_PLL_PD; gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2); qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2); txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Power-Down PLL Not Used --------------- FSM_PLL_PD : begin fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE); gen3_exit <= gen3_exit; cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2); qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2); cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Start TX Sync ------------------------- FSM_TXSYNC_START: begin fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for TX Sync Done ----------------- FSM_TXSYNC_DONE: begin fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Rate Change Done ---------------------- FSM_DONE : begin fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Start RX Sync ------------------------- FSM_RXSYNC_START: begin fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Wait for RX Sync Done ----------------- FSM_RXSYNC_DONE: begin fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE); gen3_exit <= gen3_exit; cpllpd <= cpllpd; qpllpd <= qpllpd; cpllreset <= cpllreset; qpllreset <= qpllreset; txpmareset <= txpmareset; rxpmareset <= rxpmareset; sysclksel <= sysclksel; pclk_sel <= pclk_sel; gen3 <= gen3; rate_out <= rate_out; end //---------- Default State ------------------------- default : begin fsm <= FSM_IDLE; gen3_exit <= 1'd0; cpllpd <= 1'd0; qpllpd <= 1'd0; cpllreset <= 1'd0; qpllreset <= 1'd0; txpmareset <= 1'd0; rxpmareset <= 1'd0; sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; pclk_sel <= 1'd0; gen3 <= 1'd0; rate_out <= 3'd0; end endcase end end //---------- PIPE Rate Output -------------------------------------------------- assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd); assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd); assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset); assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset); assign RATE_TXPMARESET = txpmareset; assign RATE_RXPMARESET = rxpmareset; assign RATE_SYSCLKSEL = sysclksel; assign RATE_DRP_START = (fsm == FSM_DRP_START); assign RATE_PCLK_SEL = pclk_sel; assign RATE_GEN3 = gen3; assign RATE_RATE_OUT = rate_out; assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START); assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START); assign RATE_DONE = (fsm == FSM_DONE); assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START); assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE)); assign RATE_IDLE = (fsm == FSM_IDLE); assign RATE_FSM = fsm; endmodule

(** * Hoare2: Hoare Logic, Part II *) Require Export Hoare. (* ####################################################### *) (** * Decorated Programs *) (** The beauty of Hoare Logic is that it is _compositional_ -- the structure of proofs exactly follows the structure of programs. This suggests that we can record the essential ideas of a proof informally (leaving out some low-level calculational details) by decorating programs with appropriate assertions around each statement. Such a _decorated program_ carries with it an (informal) proof of its own correctness. *) (** For example, here is a complete decorated program: *) (** {{ True }} ->> {{ m = m }} X ::= m;; {{ X = m }} ->> {{ X = m /\ p = p }} Z ::= p; {{ X = m /\ Z = p }} ->> {{ Z - X = p - m }} WHILE X <> 0 DO {{ Z - X = p - m /\ X <> 0 }} ->> {{ (Z - 1) - (X - 1) = p - m }} Z ::= Z - 1;; {{ Z - (X - 1) = p - m }} X ::= X - 1 {{ Z - X = p - m }} END; {{ Z - X = p - m /\ ~ (X <> 0) }} ->> {{ Z = p - m }} *) (** Concretely, a decorated program consists of the program text interleaved with assertions. To check that a decorated program represents a valid proof, we check that each individual command is _locally consistent_ with its accompanying assertions in the following sense: *) (** - [SKIP] is locally consistent if its precondition and postcondition are the same: {{ P }} SKIP {{ P }} *) (** - The sequential composition of [c1] and [c2] is locally consistent (with respect to assertions [P] and [R]) if [c1] is locally consistent (with respect to [P] and [Q]) and [c2] is locally consistent (with respect to [Q] and [R]): {{ P }} c1;; {{ Q }} c2 {{ R }} *) (** - An assignment is locally consistent if its precondition is the appropriate substitution of its postcondition: {{ P [X |-> a] }} X ::= a {{ P }} *) (** - A conditional is locally consistent (with respect to assertions [P] and [Q]) if the assertions at the top of its "then" and "else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then" branch is locally consistent (with respect to [P /\ b] and [Q]) and its "else" branch is locally consistent (with respect to [P /\ ~b] and [Q]): {{ P }} IFB b THEN {{ P /\ b }} c1 {{ Q }} ELSE {{ P /\ ~b }} c2 {{ Q }} FI {{ Q }} *) (** - A while loop with precondition [P] is locally consistent if its postcondition is [P /\ ~b] and if the pre- and postconditions of its body are exactly [P /\ b] and [P]: {{ P }} WHILE b DO {{ P /\ b }} c1 {{ P }} END {{ P /\ ~b }} *) (** - A pair of assertions separated by [->>] is locally consistent if the first implies the second (in all states): {{ P }} ->> {{ P' }} This corresponds to the application of [hoare_consequence] and is the only place in a decorated program where checking if decorations are correct is not fully mechanical and syntactic, but involves logical and/or arithmetic reasoning. *) (** We have seen above how _verifying_ the correctness of a given proof involves checking that every single command is locally consistent with the accompanying assertions. If we are instead interested in _finding_ a proof for a given specification we need to discover the right assertions. This can be done in an almost automatic way, with the exception of finding loop invariants, which is the subject of in the next section. In the reminder of this section we explain in detail how to construct decorations for several simple programs that don't involve non-trivial loop invariants. *) (* ####################################################### *) (** ** Example: Swapping Using Addition and Subtraction *) (** Here is a program that swaps the values of two variables using addition and subtraction (instead of by assigning to a temporary variable). X ::= X + Y;; Y ::= X - Y;; X ::= X - Y We can prove using decorations that this program is correct -- i.e., it always swaps the values of variables [X] and [Y]. *) (** (1) {{ X = m /\ Y = n }} ->> (2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }} X ::= X + Y;; (3) {{ X - (X - Y) = n /\ X - Y = m }} Y ::= X - Y;; (4) {{ X - Y = n /\ Y = m }} X ::= X - Y (5) {{ X = n /\ Y = m }} The decorations were constructed as follows: - We begin with the undecorated program (the unnumbered lines). - We then add the specification -- i.e., the outer precondition (1) and postcondition (5). In the precondition we use auxiliary variables (parameters) [m] and [n] to remember the initial values of variables [X] and respectively [Y], so that we can refer to them in the postcondition (5). - We work backwards mechanically starting from (5) all the way to (2). At each step, we obtain the precondition of the assignment from its postcondition by substituting the assigned variable with the right-hand-side of the assignment. For instance, we obtain (4) by substituting [X] with [X - Y] in (5), and (3) by substituting [Y] with [X - Y] in (4). - Finally, we verify that (1) logically implies (2) -- i.e., that the step from (1) to (2) is a valid use of the law of consequence. For this we substitute [X] by [m] and [Y] by [n] and calculate as follows: (m + n) - ((m + n) - n) = n /\ (m + n) - n = m (m + n) - m = n /\ m = m n = n /\ m = m (Note that, since we are working with natural numbers, not fixed-size machine integers, we don't need to worry about the possibility of arithmetic overflow anywhere in this argument.) *) (* ####################################################### *) (** ** Example: Simple Conditionals *) (** Here is a simple decorated program using conditionals: (1) {{True}} IFB X <= Y THEN (2) {{True /\ X <= Y}} ->> (3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}} Z ::= Y - X (4) {{Z + X = Y \/ Z + Y = X}} ELSE (5) {{True /\ ~(X <= Y) }} ->> (6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}} Z ::= X - Y (7) {{Z + X = Y \/ Z + Y = X}} FI (8) {{Z + X = Y \/ Z + Y = X}} These decorations were constructed as follows: - We start with the outer precondition (1) and postcondition (8). - We follow the format dictated by the [hoare_if] rule and copy the postcondition (8) to (4) and (7). We conjoin the precondition (1) with the guard of the conditional to obtain (2). We conjoin (1) with the negated guard of the conditional to obtain (5). - In order to use the assignment rule and obtain (3), we substitute [Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y] in (7). - Finally, we verify that (2) implies (3) and (5) implies (6). Both of these implications crucially depend on the ordering of [X] and [Y] obtained from the guard. For instance, knowing that [X <= Y] ensures that subtracting [X] from [Y] and then adding back [X] produces [Y], as required by the first disjunct of (3). Similarly, knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and then adding back [Y] produces [X], as needed by the second disjunct of (6). Note that [n - m + m = n] does _not_ hold for arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 = 5]). *) (** **** Exercise: 2 stars (if_minus_plus_reloaded) *) (** Fill in valid decorations for the following program: {{ True }} IFB X <= Y THEN {{ }} ->> {{ }} Z ::= Y - X {{ }} ELSE {{ }} ->> {{ }} Y ::= X + Z {{ }} FI {{ Y = X + Z }} *) (** [] *) (* ####################################################### *) (** ** Example: Reduce to Zero (Trivial Loop) *) (** Here is a [WHILE] loop that is so simple it needs no invariant (i.e., the invariant [True] will do the job). (1) {{ True }} WHILE X <> 0 DO (2) {{ True /\ X <> 0 }} ->> (3) {{ True }} X ::= X - 1 (4) {{ True }} END (5) {{ True /\ X = 0 }} ->> (6) {{ X = 0 }} The decorations can be constructed as follows: - Start with the outer precondition (1) and postcondition (6). - Following the format dictated by the [hoare_while] rule, we copy (1) to (4). We conjoin (1) with the guard to obtain (2) and with the negation of the guard to obtain (5). Note that, because the outer postcondition (6) does not syntactically match (5), we need a trivial use of the consequence rule from (5) to (6). - Assertion (3) is the same as (4), because [X] does not appear in [4], so the substitution in the assignment rule is trivial. - Finally, the implication between (2) and (3) is also trivial. *) (** From this informal proof, it is easy to read off a formal proof using the Coq versions of the Hoare rules. Note that we do _not_ unfold the definition of [hoare_triple] anywhere in this proof -- the idea is to use the Hoare rules as a "self-contained" logic for reasoning about programs. *) Definition reduce_to_zero' : com := WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= AMinus (AId X) (ANum 1) END. Theorem reduce_to_zero_correct' : {{fun st => True}} reduce_to_zero' {{fun st => st X = 0}}. Proof. unfold reduce_to_zero'. (* First we need to transform the postcondition so that hoare_while will apply. *) eapply hoare_consequence_post. apply hoare_while. Case "Loop body preserves invariant". (* Need to massage precondition before [hoare_asgn] applies *) eapply hoare_consequence_pre. apply hoare_asgn. (* Proving trivial implication (2) ->> (3) *) intros st [HT Hbp]. unfold assn_sub. apply I. Case "Invariant and negated guard imply postcondition". intros st [Inv GuardFalse]. unfold bassn in GuardFalse. simpl in GuardFalse. (* SearchAbout helps to find the right lemmas *) SearchAbout [not true]. rewrite not_true_iff_false in GuardFalse. SearchAbout [negb false]. rewrite negb_false_iff in GuardFalse. SearchAbout [beq_nat true]. apply beq_nat_true in GuardFalse. apply GuardFalse. Qed. (* ####################################################### *) (** ** Example: Division *) (** The following Imp program calculates the integer division and remainder of two numbers [m] and [n] that are arbitrary constants in the program. X ::= m;; Y ::= 0;; WHILE n <= X DO X ::= X - n;; Y ::= Y + 1 END; In other words, if we replace [m] and [n] by concrete numbers and execute the program, it will terminate with the variable [X] set to the remainder when [m] is divided by [n] and [Y] set to the quotient. *) (** In order to give a specification to this program we need to remember that dividing [m] by [n] produces a reminder [X] and a quotient [Y] so that [n * Y + X = m /\ X < n]. It turns out that we get lucky with this program and don't have to think very hard about the loop invariant: the invariant is the just first conjunct [n * Y + X = m], so we use that to decorate the program. (1) {{ True }} ->> (2) {{ n * 0 + m = m }} X ::= m;; (3) {{ n * 0 + X = m }} Y ::= 0;; (4) {{ n * Y + X = m }} WHILE n <= X DO (5) {{ n * Y + X = m /\ n <= X }} ->> (6) {{ n * (Y + 1) + (X - n) = m }} X ::= X - n;; (7) {{ n * (Y + 1) + X = m }} Y ::= Y + 1 (8) {{ n * Y + X = m }} END (9) {{ n * Y + X = m /\ X < n }} Assertions (4), (5), (8), and (9) are derived mechanically from the invariant and the loop's guard. Assertions (8), (7), and (6) are derived using the assignment rule going backwards from (8) to (6). Assertions (4), (3), and (2) are again backwards applications of the assignment rule. Now that we've decorated the program it only remains to check that the two uses of the consequence rule are correct -- i.e., that (1) implies (2) and that (5) implies (6). This is indeed the case, so we have a valid decorated program. *) (* ####################################################### *) (** * Finding Loop Invariants *) (** Once the outermost precondition and postcondition are chosen, the only creative part in verifying programs with Hoare Logic is finding the right loop invariants. The reason this is difficult is the same as the reason that doing inductive mathematical proofs requires creativity: strengthening the loop invariant (or the induction hypothesis) means that you have a stronger assumption to work with when trying to establish the postcondition of the loop body (complete the induction step of the proof), but it also means that the loop body postcondition itself is harder to prove! This section is dedicated to teaching you how to approach the challenge of finding loop invariants using a series of examples and exercises. *) (** ** Example: Slow Subtraction *) (** The following program subtracts the value of [X] from the value of [Y] by repeatedly decrementing both [X] and [Y]. We want to verify its correctness with respect to the following specification: {{ X = m /\ Y = n }} WHILE X <> 0 DO Y ::= Y - 1;; X ::= X - 1 END {{ Y = n - m }} To verify this program we need to find an invariant [I] for the loop. As a first step we can leave [I] as an unknown and build a _skeleton_ for the proof by applying backward the rules for local consistency. This process leads to the following skeleton: (1) {{ X = m /\ Y = n }} ->> (a) (2) {{ I }} WHILE X <> 0 DO (3) {{ I /\ X <> 0 }} ->> (c) (4) {{ I[X |-> X-1][Y |-> Y-1] }} Y ::= Y - 1;; (5) {{ I[X |-> X-1] }} X ::= X - 1 (6) {{ I }} END (7) {{ I /\ ~(X <> 0) }} ->> (b) (8) {{ Y = n - m }} By examining this skeleton, we can see that any valid [I] will have to respect three conditions: - (a) it must be weak enough to be implied by the loop's precondition, i.e. (1) must imply (2); - (b) it must be strong enough to imply the loop's postcondition, i.e. (7) must imply (8); - (c) it must be preserved by one iteration of the loop, i.e. (3) must imply (4). *) (** These conditions are actually independent of the particular program and specification we are considering. Indeed, every loop invariant has to satisfy them. One way to find an invariant that simultaneously satisfies these three conditions is by using an iterative process: start with a "candidate" invariant (e.g. a guess or a heuristic choice) and check the three conditions above; if any of the checks fails, try to use the information that we get from the failure to produce another (hopefully better) candidate invariant, and repeat the process. For instance, in the reduce-to-zero example above, we saw that, for a very simple loop, choosing [True] as an invariant did the job. So let's try it again here! I.e., let's instantiate [I] with [True] in the skeleton above see what we get... (1) {{ X = m /\ Y = n }} ->> (a - OK) (2) {{ True }} WHILE X <> 0 DO (3) {{ True /\ X <> 0 }} ->> (c - OK) (4) {{ True }} Y ::= Y - 1;; (5) {{ True }} X ::= X - 1 (6) {{ True }} END (7) {{ True /\ X = 0 }} ->> (b - WRONG!) (8) {{ Y = n - m }} While conditions (a) and (c) are trivially satisfied, condition (b) is wrong, i.e. it is not the case that (7) [True /\ X = 0] implies (8) [Y = n - m]. In fact, the two assertions are completely unrelated and it is easy to find a counterexample (say, [Y = X = m = 0] and [n = 1]). If we want (b) to hold, we need to strengthen the invariant so that it implies the postcondition (8). One very simple way to do this is to let the invariant _be_ the postcondition. So let's return to our skeleton, instantiate [I] with [Y = n - m], and check conditions (a) to (c) again. (1) {{ X = m /\ Y = n }} ->> (a - WRONG!) (2) {{ Y = n - m }} WHILE X <> 0 DO (3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!) (4) {{ Y - 1 = n - m }} Y ::= Y - 1;; (5) {{ Y = n - m }} X ::= X - 1 (6) {{ Y = n - m }} END (7) {{ Y = n - m /\ X = 0 }} ->> (b - OK) (8) {{ Y = n - m }} This time, condition (b) holds trivially, but (a) and (c) are broken. Condition (a) requires that (1) [X = m /\ Y = n] implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to show that [n = n - m] for arbitrary [m] and [n], which does not hold (for instance, when [m = n = 1]). Condition (c) requires that [n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m = 0]. So, although [Y = n - m] holds at the end of the loop, it does not hold from the start, and it doesn't hold on each iteration; it is not a correct invariant. This failure is not very surprising: the variable [Y] changes during the loop, while [m] and [n] are constant, so the assertion we chose didn't have much chance of being an invariant! To do better, we need to generalize (8) to some statement that is equivalent to (8) when [X] is [0], since this will be the case when the loop terminates, and that "fills the gap" in some appropriate way when [X] is nonzero. Looking at how the loop works, we can observe that [X] and [Y] are decremented together until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially, after one iteration of the loop we obtain [X = 1] and [Y = 4]; after two iterations [X = 0] and [Y = 3]; and then the loop stops. Notice that the difference between [Y] and [X] stays constant between iterations; initially, [Y = n] and [X = m], so this difference is always [n - m]. So let's try instantiating [I] in the skeleton above with [Y - X = n - m]. (1) {{ X = m /\ Y = n }} ->> (a - OK) (2) {{ Y - X = n - m }} WHILE X <> 0 DO (3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK) (4) {{ (Y - 1) - (X - 1) = n - m }} Y ::= Y - 1;; (5) {{ Y - (X - 1) = n - m }} X ::= X - 1 (6) {{ Y - X = n - m }} END (7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK) (8) {{ Y = n - m }} Success! Conditions (a), (b) and (c) all hold now. (To verify (c), we need to check that, under the assumption that [X <> 0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all natural numbers [X] and [Y].) *) (* ####################################################### *) (** ** Exercise: Slow Assignment *) (** **** Exercise: 2 stars (slow_assignment) *) (** A roundabout way of assigning a number currently stored in [X] to the variable [Y] is to start [Y] at [0], then decrement [X] until it hits [0], incrementing [Y] at each step. Here is a program that implements this idea: {{ X = m }} Y ::= 0;; WHILE X <> 0 DO X ::= X - 1;; Y ::= Y + 1 END {{ Y = m }} Write an informal decorated program showing that this is correct. *) (* FILL IN HERE *) (** [] *) (* ####################################################### *) (** ** Exercise: Slow Addition *) (** **** Exercise: 3 stars, optional (add_slowly_decoration) *) (** The following program adds the variable X into the variable Z by repeatedly decrementing X and incrementing Z. WHILE X <> 0 DO Z ::= Z + 1;; X ::= X - 1 END Following the pattern of the [subtract_slowly] example above, pick a precondition and postcondition that give an appropriate specification of [add_slowly]; then (informally) decorate the program accordingly. *) (* FILL IN HERE *) (** [] *) (* ####################################################### *) (** ** Example: Parity *) (** Here is a cute little program for computing the parity of the value initially stored in [X] (due to Daniel Cristofani). {{ X = m }} WHILE 2 <= X DO X ::= X - 2 END {{ X = parity m }} The mathematical [parity] function used in the specification is defined in Coq as follows: *) Fixpoint parity x := match x with | 0 => 0 | 1 => 1 | S (S x') => parity x' end. (** The postcondition does not hold at the beginning of the loop, since [m = parity m] does not hold for an arbitrary [m], so we cannot use that as an invariant. To find an invariant that works, let's think a bit about what this loop does. On each iteration it decrements [X] by [2], which preserves the parity of [X]. So the parity of [X] does not change, i.e. it is invariant. The initial value of [X] is [m], so the parity of [X] is always equal to the parity of [m]. Using [parity X = parity m] as an invariant we obtain the following decorated program: {{ X = m }} ->> (a - OK) {{ parity X = parity m }} WHILE 2 <= X DO {{ parity X = parity m /\ 2 <= X }} ->> (c - OK) {{ parity (X-2) = parity m }} X ::= X - 2 {{ parity X = parity m }} END {{ parity X = parity m /\ X < 2 }} ->> (b - OK) {{ X = parity m }} With this invariant, conditions (a), (b), and (c) are all satisfied. For verifying (b), we observe that, when [X < 2], we have [parity X = X] (we can easily see this in the definition of [parity]). For verifying (c), we observe that, when [2 <= X], we have [parity X = parity (X-2)]. *) (** **** Exercise: 3 stars, optional (parity_formal) *) (** Translate this proof to Coq. Refer to the reduce-to-zero example for ideas. You may find the following two lemmas useful: *) Lemma parity_ge_2 : forall x, 2 <= x -> parity (x - 2) = parity x. Proof. induction x; intro. reflexivity. destruct x. inversion H. inversion H1. simpl. rewrite <- minus_n_O. reflexivity. Qed. Lemma parity_lt_2 : forall x, ~ 2 <= x -> parity (x) = x. Proof. intros. induction x. reflexivity. destruct x. reflexivity. apply ex_falso_quodlibet. apply H. omega. Qed. Theorem parity_correct : forall m, {{ fun st => st X = m }} WHILE BLe (ANum 2) (AId X) DO X ::= AMinus (AId X) (ANum 2) END {{ fun st => st X = parity m }}. Proof. (* FILL IN HERE *) Admitted. (** [] *) (* ####################################################### *) (** ** Example: Finding Square Roots *) (** The following program computes the square root of [X] by naive iteration: {{ X=m }} Z ::= 0;; WHILE (Z+1)*(Z+1) <= X DO Z ::= Z+1 END {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }} *) (** As above, we can try to use the postcondition as a candidate invariant, obtaining the following decorated program: (1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!) (2) {{ 0*0 <= m /\ m<1*1 }} Z ::= 0;; (3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }} WHILE (Z+1)*(Z+1) <= X DO (4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!) (5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }} Z ::= Z+1 (6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }} END (7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK) (8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }} This didn't work very well: both conditions (a) and (c) failed. Looking at condition (c), we see that the second conjunct of (4) is almost the same as the first conjunct of (5), except that (4) mentions [X] while (5) mentions [m]. But note that [X] is never assigned in this program, so we should have [X=m], but we didn't propagate this information from (1) into the loop invariant. Also, looking at the second conjunct of (8), it seems quite hopeless as an invariant -- and we don't even need it, since we can obtain it from the negation of the guard (third conjunct in (7)), again under the assumption that [X=m]. So we now try [X=m /\ Z*Z <= m] as the loop invariant: {{ X=m }} ->> (a - OK) {{ X=m /\ 0*0 <= m }} Z ::= 0; {{ X=m /\ Z*Z <= m }} WHILE (Z+1)*(Z+1) <= X DO {{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK) {{ X=m /\ (Z+1)*(Z+1)<=m }} Z ::= Z+1 {{ X=m /\ Z*Z<=m }} END {{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }} This works, since conditions (a), (b), and (c) are now all trivially satisfied. Very often, if a variable is used in a loop in a read-only fashion (i.e., it is referred to by the program or by the specification and it is not changed by the loop) it is necessary to add the fact that it doesn't change to the loop invariant. *) (* ####################################################### *) (** ** Example: Squaring *) (** Here is a program that squares [X] by repeated addition: {{ X = m }} Y ::= 0;; Z ::= 0;; WHILE Y <> X DO Z ::= Z + X;; Y ::= Y + 1 END {{ Z = m*m }} *) (** The first thing to note is that the loop reads [X] but doesn't change its value. As we saw in the previous example, in such cases it is a good idea to add [X = m] to the invariant. The other thing we often use in the invariant is the postcondition, so let's add that too, leading to the invariant candidate [Z = m * m /\ X = m]. {{ X = m }} ->> (a - WRONG) {{ 0 = m*m /\ X = m }} Y ::= 0;; {{ 0 = m*m /\ X = m }} Z ::= 0;; {{ Z = m*m /\ X = m }} WHILE Y <> X DO {{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG) {{ Z+X = m*m /\ X = m }} Z ::= Z + X;; {{ Z = m*m /\ X = m }} Y ::= Y + 1 {{ Z = m*m /\ X = m }} END {{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK) {{ Z = m*m }} Conditions (a) and (c) fail because of the [Z = m*m] part. While [Z] starts at [0] and works itself up to [m*m], we can't expect [Z] to be [m*m] from the start. If we look at how [Z] progesses in the loop, after the 1st iteration [Z = m], after the 2nd iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable [Y] tracks how many times we go through the loop, we derive the new invariant candidate [Z = Y*m /\ X = m]. {{ X = m }} ->> (a - OK) {{ 0 = 0*m /\ X = m }} Y ::= 0;; {{ 0 = Y*m /\ X = m }} Z ::= 0;; {{ Z = Y*m /\ X = m }} WHILE Y <> X DO {{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK) {{ Z+X = (Y+1)*m /\ X = m }} Z ::= Z + X; {{ Z = (Y+1)*m /\ X = m }} Y ::= Y + 1 {{ Z = Y*m /\ X = m }} END {{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK) {{ Z = m*m }} This new invariant makes the proof go through: all three conditions are easy to check. It is worth comparing the postcondition [Z = m*m] and the [Z = Y*m] conjunct of the invariant. It is often the case that one has to replace auxiliary variabes (parameters) with variables -- or with expressions involving both variables and parameters (like [m - Y]) -- when going from postconditions to invariants. *) (* ####################################################### *) (** ** Exercise: Factorial *) (** **** Exercise: 3 stars (factorial) *) (** Recall that [n!] denotes the factorial of [n] (i.e. [n! = 1*2*...*n]). Here is an Imp program that calculates the factorial of the number initially stored in the variable [X] and puts it in the variable [Y]: {{ X = m }} Y ::= 1 ;; WHILE X <> 0 DO Y ::= Y * X ;; X ::= X - 1 END {{ Y = m! }} Fill in the blanks in following decorated program: {{ X = m }} ->> {{ }} Y ::= 1;; {{ }} WHILE X <> 0 DO {{ }} ->> {{ }} Y ::= Y * X;; {{ }} X ::= X - 1 {{ }} END {{ }} ->> {{ Y = m! }} *) (** [] *) (* ####################################################### *) (** ** Exercise: Min *) (** **** Exercise: 3 stars (Min_Hoare) *) (** Fill in valid decorations for the following program. For the => steps in your annotations, you may rely (silently) on the following facts about min Lemma lemma1 : forall x y, (x=0 \/ y=0) -> min x y = 0. Lemma lemma2 : forall x y, min (x-1) (y-1) = (min x y) - 1. plus, as usual, standard high-school algebra. {{ True }} ->> {{ }} X ::= a;; {{ }} Y ::= b;; {{ }} Z ::= 0;; {{ }} WHILE (X <> 0 /\ Y <> 0) DO {{ }} ->> {{ }} X := X - 1;; {{ }} Y := Y - 1;; {{ }} Z := Z + 1 {{ }} END {{ }} ->> {{ Z = min a b }} *) (** [] *) (** **** Exercise: 3 stars (two_loops) *) (** Here is a very inefficient way of adding 3 numbers: X ::= 0;; Y ::= 0;; Z ::= c;; WHILE X <> a DO X ::= X + 1;; Z ::= Z + 1 END;; WHILE Y <> b DO Y ::= Y + 1;; Z ::= Z + 1 END Show that it does what it should by filling in the blanks in the following decorated program. {{ True }} ->> {{ }} X ::= 0;; {{ }} Y ::= 0;; {{ }} Z ::= c;; {{ }} WHILE X <> a DO {{ }} ->> {{ }} X ::= X + 1;; {{ }} Z ::= Z + 1 {{ }} END;; {{ }} ->> {{ }} WHILE Y <> b DO {{ }} ->> {{ }} Y ::= Y + 1;; {{ }} Z ::= Z + 1 {{ }} END {{ }} ->> {{ Z = a + b + c }} *) (** [] *) (* ####################################################### *) (** ** Exercise: Power Series *) (** **** Exercise: 4 stars, optional (dpow2_down) *) (** Here is a program that computes the series: [1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1] X ::= 0;; Y ::= 1;; Z ::= 1;; WHILE X <> m DO Z ::= 2 * Z;; Y ::= Y + Z;; X ::= X + 1 END Write a decorated program for this. *) (* FILL IN HERE *) (* ####################################################### *) (** * Weakest Preconditions (Advanced) *) (** Some Hoare triples are more interesting than others. For example, {{ False }} X ::= Y + 1 {{ X <= 5 }} is _not_ very interesting: although it is perfectly valid, it tells us nothing useful. Since the precondition isn't satisfied by any state, it doesn't describe any situations where we can use the command [X ::= Y + 1] to achieve the postcondition [X <= 5]. By contrast, {{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }} is useful: it tells us that, if we can somehow create a situation in which we know that [Y <= 4 /\ Z = 0], then running this command will produce a state satisfying the postcondition. However, this triple is still not as useful as it could be, because the [Z = 0] clause in the precondition actually has nothing to do with the postcondition [X <= 5]. The _most_ useful triple (for a given command and postcondition) is this one: {{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }} In other words, [Y <= 4] is the _weakest_ valid precondition of the command [X ::= Y + 1] for the postcondition [X <= 5]. *) (** In general, we say that "[P] is the weakest precondition of command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if, whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have [P' st] implies [P st] for all states [st]. *) Definition is_wp P c Q := {{P}} c {{Q}} /\ forall P', {{P'}} c {{Q}} -> (P' ->> P). (** That is, [P] is the weakest precondition of [c] for [Q] if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the _weakest_ (easiest to satisfy) assertion that guarantees [Q] after executing [c]. *) (** **** Exercise: 1 star, optional (wp) *) (** What are the weakest preconditions of the following commands for the following postconditions? 1) {{ ? }} SKIP {{ X = 5 }} 2) {{ ? }} X ::= Y + Z {{ X = 5 }} 3) {{ ? }} X ::= Y {{ X = Y }} 4) {{ ? }} IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI {{ Y = 5 }} 5) {{ ? }} X ::= 5 {{ X = 0 }} 6) {{ ? }} WHILE True DO X ::= 0 END {{ X = 0 }} *) (* FILL IN HERE *) (** [] *) (** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *) (** Prove formally using the definition of [hoare_triple] that [Y <= 4] is indeed the weakest precondition of [X ::= Y + 1] with respect to postcondition [X <= 5]. *) Theorem is_wp_example : is_wp (fun st => st Y <= 4) (X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5). Proof. (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *) (** Show that the precondition in the rule [hoare_asgn] is in fact the weakest precondition. *) Theorem hoare_asgn_weakest : forall Q X a, is_wp (Q [X |-> a]) (X ::= a) Q. Proof. (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *) (** Show that your [havoc_pre] rule from the [himp_hoare] exercise in the [Hoare] chapter returns the weakest precondition. *) Module Himp2. Import Himp. Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id), {{ P }} HAVOC X {{ Q }} -> P ->> havoc_pre X Q. Proof. (* FILL IN HERE *) Admitted. End Himp2. (** [] *) (* ####################################################### *) (** * Formal Decorated Programs (Advanced) *) (** The informal conventions for decorated programs amount to a way of displaying Hoare triples in which commands are annotated with enough embedded assertions that checking the validity of the triple is reduced to simple logical and algebraic calculations showing that some assertions imply others. In this section, we show that this informal presentation style can actually be made completely formal and indeed that checking the validity of decorated programs can mostly be automated. *) (** ** Syntax *) (** The first thing we need to do is to formalize a variant of the syntax of commands with embedded assertions. We call the new commands _decorated commands_, or [dcom]s. *) Inductive dcom : Type := | DCSkip : Assertion -> dcom | DCSeq : dcom -> dcom -> dcom | DCAsgn : id -> aexp -> Assertion -> dcom | DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom -> Assertion-> dcom | DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom | DCPre : Assertion -> dcom -> dcom | DCPost : dcom -> Assertion -> dcom. Tactic Notation "dcom_cases" tactic(first) ident(c) := first; [ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn" | Case_aux c "If" | Case_aux c "While" | Case_aux c "Pre" | Case_aux c "Post" ]. Notation "'SKIP' {{ P }}" := (DCSkip P) (at level 10) : dcom_scope. Notation "l '::=' a {{ P }}" := (DCAsgn l a P) (at level 60, a at next level) : dcom_scope. Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}" := (DCWhile b Pbody d Ppost) (at level 80, right associativity) : dcom_scope. Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}" := (DCIf b P d P' d' Q) (at level 80, right associativity) : dcom_scope. Notation "'->>' {{ P }} d" := (DCPre P d) (at level 90, right associativity) : dcom_scope. Notation "{{ P }} d" := (DCPre P d) (at level 90) : dcom_scope. Notation "d '->>' {{ P }}" := (DCPost d P) (at level 80, right associativity) : dcom_scope. Notation " d ;; d' " := (DCSeq d d') (at level 80, right associativity) : dcom_scope. Delimit Scope dcom_scope with dcom. (** To avoid clashing with the existing [Notation] definitions for ordinary [com]mands, we introduce these notations in a special scope called [dcom_scope], and we wrap examples with the declaration [% dcom] to signal that we want the notations to be interpreted in this scope. Careful readers will note that we've defined two notations for the [DCPre] constructor, one with and one without a [->>]. The "without" version is intended to be used to supply the initial precondition at the very top of the program. *) Example dec_while : dcom := ( {{ fun st => True }} WHILE (BNot (BEq (AId X) (ANum 0))) DO {{ fun st => True /\ st X <> 0}} X ::= (AMinus (AId X) (ANum 1)) {{ fun _ => True }} END {{ fun st => True /\ st X = 0}} ->> {{ fun st => st X = 0 }} ) % dcom. (** It is easy to go from a [dcom] to a [com] by erasing all annotations. *) Fixpoint extract (d:dcom) : com := match d with | DCSkip _ => SKIP | DCSeq d1 d2 => (extract d1 ;; extract d2) | DCAsgn X a _ => X ::= a | DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI | DCWhile b _ d _ => WHILE b DO extract d END | DCPre _ d => extract d | DCPost d _ => extract d end. (** The choice of exactly where to put assertions in the definition of [dcom] is a bit subtle. The simplest thing to do would be to annotate every [dcom] with a precondition and postcondition. But this would result in very verbose programs with a lot of repeated annotations: for example, a program like [SKIP;SKIP] would have to be annotated as {{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}}, with pre- and post-conditions on each [SKIP], plus identical pre- and post-conditions on the semicolon! Instead, the rule we've followed is this: - The _post_-condition expected by each [dcom] [d] is embedded in [d] - The _pre_-condition is supplied by the context. *) (** In other words, the invariant of the representation is that a [dcom] [d] together with a precondition [P] determines a Hoare triple [{{P}} (extract d) {{post d}}], where [post] is defined as follows: *) Fixpoint post (d:dcom) : Assertion := match d with | DCSkip P => P | DCSeq d1 d2 => post d2 | DCAsgn X a Q => Q | DCIf _ _ d1 _ d2 Q => Q | DCWhile b Pbody c Ppost => Ppost | DCPre _ d => post d | DCPost c Q => Q end. (** Similarly, we can extract the "initial precondition" from a decorated program. *) Fixpoint pre (d:dcom) : Assertion := match d with | DCSkip P => fun st => True | DCSeq c1 c2 => pre c1 | DCAsgn X a Q => fun st => True | DCIf _ _ t _ e _ => fun st => True | DCWhile b Pbody c Ppost => fun st => True | DCPre P c => P | DCPost c Q => pre c end. (** This function is not doing anything sophisticated like calculating a weakest precondition; it just recursively searches for an explicit annotation at the very beginning of the program, returning default answers for programs that lack an explicit precondition (like a bare assignment or [SKIP]). *) (** Using [pre] and [post], and assuming that we adopt the convention of always supplying an explicit precondition annotation at the very beginning of our decorated programs, we can express what it means for a decorated program to be correct as follows: *) Definition dec_correct (d:dcom) := {{pre d}} (extract d) {{post d}}. (** To check whether this Hoare triple is _valid_, we need a way to extract the "proof obligations" from a decorated program. These obligations are often called _verification conditions_, because they are the facts that must be verified to see that the decorations are logically consistent and thus add up to a complete proof of correctness. *) (** ** Extracting Verification Conditions *) (** The function [verification_conditions] takes a [dcom] [d] together with a precondition [P] and returns a _proposition_ that, if it can be proved, implies that the triple [{{P}} (extract d) {{post d}}] is valid. *) (** It does this by walking over [d] and generating a big conjunction including all the "local checks" that we listed when we described the informal rules for decorated programs. (Strictly speaking, we need to massage the informal rules a little bit to add some uses of the rule of consequence, but the correspondence should be clear.) *) Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop := match d with | DCSkip Q => (P ->> Q) | DCSeq d1 d2 => verification_conditions P d1 /\ verification_conditions (post d1) d2 | DCAsgn X a Q => (P ->> Q [X |-> a]) | DCIf b P1 d1 P2 d2 Q => ((fun st => P st /\ bassn b st) ->> P1) /\ ((fun st => P st /\ ~ (bassn b st)) ->> P2) /\ (Q <<->> post d1) /\ (Q <<->> post d2) /\ verification_conditions P1 d1 /\ verification_conditions P2 d2 | DCWhile b Pbody d Ppost => (* post d is the loop invariant and the initial precondition *) (P ->> post d) /\ (Pbody <<->> (fun st => post d st /\ bassn b st)) /\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st))) /\ verification_conditions Pbody d | DCPre P' d => (P ->> P') /\ verification_conditions P' d | DCPost d Q => verification_conditions P d /\ (post d ->> Q) end. (** And now, the key theorem, which states that [verification_conditions] does its job correctly. Not surprisingly, we need to use each of the Hoare Logic rules at some point in the proof. *) (** We have used _in_ variants of several tactics before to apply them to values in the context rather than the goal. An extension of this idea is the syntax [tactic in *], which applies [tactic] in the goal and every hypothesis in the context. We most commonly use this facility in conjunction with the [simpl] tactic, as below. *) Theorem verification_correct : forall d P, verification_conditions P d -> {{P}} (extract d) {{post d}}. Proof. dcom_cases (induction d) Case; intros P H; simpl in *. Case "Skip". eapply hoare_consequence_pre. apply hoare_skip. assumption. Case "Seq". inversion H as [H1 H2]. clear H. eapply hoare_seq. apply IHd2. apply H2. apply IHd1. apply H1. Case "Asgn". eapply hoare_consequence_pre. apply hoare_asgn. assumption. Case "If". inversion H as [HPre1 [HPre2 [[Hd11 Hd12] [[Hd21 Hd22] [HThen HElse]]]]]. clear H. apply IHd1 in HThen. clear IHd1. apply IHd2 in HElse. clear IHd2. apply hoare_if. eapply hoare_consequence_pre; eauto. eapply hoare_consequence_post; eauto. eapply hoare_consequence_pre; eauto. eapply hoare_consequence_post; eauto. Case "While". inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]]; subst; clear H. eapply hoare_consequence_pre; eauto. eapply hoare_consequence_post; eauto. apply hoare_while. eapply hoare_consequence_pre; eauto. Case "Pre". inversion H as [HP Hd]; clear H. eapply hoare_consequence_pre. apply IHd. apply Hd. assumption. Case "Post". inversion H as [Hd HQ]; clear H. eapply hoare_consequence_post. apply IHd. apply Hd. assumption. Qed. (** ** Examples *) (** The propositions generated by [verification_conditions] are fairly big, and they contain many conjuncts that are essentially trivial. *) Eval simpl in (verification_conditions (fun st => True) dec_while). (** ==> (((fun _ : state => True) ->> (fun _ : state => True)) /\ ((fun _ : state => True) ->> (fun _ : state => True)) /\ (fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) = (fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\ (fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) = (fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\ (fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->> (fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\ (fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->> (fun st : state => st X = 0) *) (** In principle, we could certainly work with them using just the tactics we have so far, but we can make things much smoother with a bit of automation. We first define a custom [verify] tactic that applies splitting repeatedly to turn all the conjunctions into separate subgoals and then uses [omega] and [eauto] (a handy general-purpose automation tactic that we'll discuss in detail later) to deal with as many of them as possible. *) Lemma ble_nat_true_iff : forall n m : nat, ble_nat n m = true <-> n <= m. Proof. intros n m. split. apply ble_nat_true. generalize dependent m. induction n; intros m H. reflexivity. simpl. destruct m. inversion H. apply le_S_n in H. apply IHn. assumption. Qed. Lemma ble_nat_false_iff : forall n m : nat, ble_nat n m = false <-> ~(n <= m). Proof. intros n m. split. apply ble_nat_false. generalize dependent m. induction n; intros m H. apply ex_falso_quodlibet. apply H. apply le_0_n. simpl. destruct m. reflexivity. apply IHn. intro Hc. apply H. apply le_n_S. assumption. Qed. Tactic Notation "verify" := apply verification_correct; repeat split; simpl; unfold assert_implies; unfold bassn in *; unfold beval in *; unfold aeval in *; unfold assn_sub; intros; repeat rewrite update_eq; repeat (rewrite update_neq; [| (intro X; inversion X)]); simpl in *; repeat match goal with [H : _ /\ _ |- _] => destruct H end; repeat rewrite not_true_iff_false in *; repeat rewrite not_false_iff_true in *; repeat rewrite negb_true_iff in *; repeat rewrite negb_false_iff in *; repeat rewrite beq_nat_true_iff in *; repeat rewrite beq_nat_false_iff in *; repeat rewrite ble_nat_true_iff in *; repeat rewrite ble_nat_false_iff in *; try subst; repeat match goal with [st : state |- _] => match goal with [H : st _ = _ |- _] => rewrite -> H in *; clear H | [H : _ = st _ |- _] => rewrite <- H in *; clear H end end; try eauto; try omega. (** What's left after [verify] does its thing is "just the interesting parts" of checking that the decorations are correct. For very simple examples [verify] immediately solves the goal (provided that the annotations are correct). *) Theorem dec_while_correct : dec_correct dec_while. Proof. verify. Qed. (** Another example (formalizing a decorated program we've seen before): *) Example subtract_slowly_dec (m:nat) (p:nat) : dcom := ( {{ fun st => st X = m /\ st Z = p }} ->> {{ fun st => st Z - st X = p - m }} WHILE BNot (BEq (AId X) (ANum 0)) DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->> {{ fun st => (st Z - 1) - (st X - 1) = p - m }} Z ::= AMinus (AId Z) (ANum 1) {{ fun st => st Z - (st X - 1) = p - m }} ;; X ::= AMinus (AId X) (ANum 1) {{ fun st => st Z - st X = p - m }} END {{ fun st => st Z - st X = p - m /\ st X = 0 }} ->> {{ fun st => st Z = p - m }} ) % dcom. Theorem subtract_slowly_dec_correct : forall m p, dec_correct (subtract_slowly_dec m p). Proof. intros m p. verify. (* this grinds for a bit! *) Qed. (** **** Exercise: 3 stars, advanced (slow_assignment_dec) *) (** In the [slow_assignment] exercise above, we saw a roundabout way of assigning a number currently stored in [X] to the variable [Y]: start [Y] at [0], then decrement [X] until it hits [0], incrementing [Y] at each step. Write a _formal_ version of this decorated program and prove it correct. *) Example slow_assignment_dec (m:nat) : dcom := (* FILL IN HERE *) admit. Theorem slow_assignment_dec_correct : forall m, dec_correct (slow_assignment_dec m). Proof. (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 4 stars, advanced (factorial_dec) *) (** Remember the factorial function we worked with before: *) Fixpoint real_fact (n:nat) : nat := match n with | O => 1 | S n' => n * (real_fact n') end. (** Following the pattern of [subtract_slowly_dec], write a decorated program [factorial_dec] that implements the factorial function and prove it correct as [factorial_dec_correct]. *) (* FILL IN HERE *) (** [] *) (** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2004 by Wilson Snyder. module t (/*AUTOARG*/ // Outputs ign, // Inputs clk ); input clk; output [31:0] ign; reg [31:0] right; reg [31:0] left; reg [63:0] qright; reg [63:0] qleft; reg [31:0] amt; assign ign = {31'h0, clk} >>> 4'bx; // bug760 always @* begin right = 32'h819b018a >> amt; left = 32'h819b018a << amt; qright = 64'hf784bf8f_12734089 >> amt; qleft = 64'hf784bf8f_12734089 >> amt; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright); `endif if (cyc==1) begin amt <= 32'd0; if (5'b10110>>2 != 5'b00101) $stop; if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness if (5'b10110<<2 != 5'b11000) $stop; if (5'b10110<<<2 != 5'b11000) $stop; if (5'sb10110>>2 != 5'sb00101) $stop; if (5'sb10110>>>2 != 5'sb11101) $stop; if (5'sb10110<<2 != 5'sb11000) $stop; if (5'sb10110<<<2 != 5'sb11000) $stop; // Allow >64 bit shifts if the shift amount is a constant if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; end if (cyc==2) begin amt <= 32'd28; if (left != 32'h819b018a) $stop; if (right != 32'h819b018a) $stop; if (qleft != 64'hf784bf8f_12734089) $stop; if (qright != 64'hf784bf8f_12734089) $stop; end if (cyc==3) begin amt <= 32'd31; if (left != 32'ha0000000) $stop; if (right != 32'h8) $stop; if (qleft != 64'h0000000f784bf8f1) $stop; if (qright != 64'h0000000f784bf8f1) $stop; end if (cyc==4) begin amt <= 32'd32; if (left != 32'h0) $stop; if (right != 32'h1) $stop; if (qleft != 64'h00000001ef097f1e) $stop; if (qright != 64'h00000001ef097f1e) $stop; end if (cyc==5) begin amt <= 32'd33; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h00000000f784bf8f) $stop; if (qright != 64'h00000000f784bf8f) $stop; end if (cyc==6) begin amt <= 32'd64; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h000000007bc25fc7) $stop; if (qright != 64'h000000007bc25fc7) $stop; end if (cyc==7) begin amt <= 32'd128; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==8) begin if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Wilson Snyder. module t; function int int123(); int123 = 32'h123; endfunction function bit f_bit ; input bit i; f_bit = ~i; endfunction function int f_int ; input int i; f_int = ~i; endfunction function byte f_byte ; input byte i; f_byte = ~i; endfunction function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction function longint f_longint ; input longint i; f_longint = ~i; endfunction function chandle f_chandle ; input chandle i; f_chandle = i; endfunction // Note there's no "input" here vvvv, it's the default function bit g_bit (bit i); g_bit = ~i; endfunction function int g_int (int i); g_int = ~i; endfunction function byte g_byte (byte i); g_byte = ~i; endfunction function shortint g_shortint(shortint i); g_shortint = ~i; endfunction function longint g_longint (longint i); g_longint = ~i; endfunction function chandle g_chandle (chandle i); g_chandle = i; endfunction chandle c; initial begin if (int123() !== 32'h123) $stop; if (f_bit(1'h1) !== 1'h0) $stop; if (f_bit(1'h0) !== 1'h1) $stop; if (f_int(32'h1) !== 32'hfffffffe) $stop; if (f_byte(8'h1) !== 8'hfe) $stop; if (f_shortint(16'h1) !== 16'hfffe) $stop; if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (f_chandle(c) !== c) $stop; if (g_bit(1'h1) !== 1'h0) $stop; if (g_bit(1'h0) !== 1'h1) $stop; if (g_int(32'h1) !== 32'hfffffffe) $stop; if (g_byte(8'h1) !== 8'hfe) $stop; if (g_shortint(16'h1) !== 16'hfffe) $stop; if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (g_chandle(c) !== c) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:09:39 08/25/2015 // Design Name: // Module Name: FSM_Add_Subtract // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module FSM_Add_Subtract ( //INPUTS input wire clk, //system clock input wire rst, //system reset input wire rst_FSM, input wire beg_FSM, //Begin Finite State Machine //**REVISAD ////////////////////////////////////////////////////////////////////////////// //Oper_Start_In evaluation signals input wire zero_flag_i, //Exp_operation evaluation signals input wire norm_iteration_i, //Barrel_Shifter evaluation signals //None //Add_Subt_Sgf evaluation signals input wire add_overflow_i, //LZA evaluation signals //None //Deco_round evaluation Signals input wire round_i, //Final_result evaluation signals //None //OUTPUT SIGNALS //////////////////////////////////////////////////////////////////////////////////// //Oper_Start_In control signals output wire load_1_o,//Enable input registers output wire load_2_o,//Enable output registers //Exp_operation control signals output reg load_3_o, //Enable Output registers output reg load_8_o, output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift) //Barrel shifter control signals output reg load_4_o, //Enable Output registers output reg left_right_o, //Select direction shift (right=0, left=1) output reg bit_shift_o, //bit input for shifts fills //Add_Subt_sgf control signals output reg load_5_o, //Enables Output registers //LZA control signals output reg load_6_o, //Enables Output registers //Deco_Round control signals //None //Final_Result control signals output reg load_7_o, ///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ //Multiplexer selector for Exp_operation's OPER_A output reg ctrl_a_o, //Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value output reg [1:0] ctrl_b_o, output reg ctrl_b_load_o, //Multiplexer selector for Data shift output reg ctrl_c_o, //Multiplexer selector for Add_Subt_Sgf's inputs output reg ctrl_d_o, //Internal reset signal output reg rst_int, //Ready Signal output reg ready ); localparam [3:0] //First I'm going to declarate the registers of the first phase of execution start = 4'd0, //This state evaluates the beg_FSM to begin operations load_oper = 4'd1, //This state enables the registers that contains //both operands and the operator zero_info_state = 4'd2, //Evaluate zero condition load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first //result normalization extra1_64= 4'd4, norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the //second time (result normalization) add_subt = 4'd6, //Enable the add_subt_sgf's registers add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition overflow_add = 4'd8, round_sgf = 4'd9, //Evaluate the significand round condition overflow_add_r = 4'd10, extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition load_final_result = 4'd13, //Load the final_result's register with the result ready_flag = 4'd14; //Enable the ready flag with the final result //**********************REVISADO reg [3:0] state_reg, state_next ; //state registers declaration ////////////////////////Logic outputs///////////////77 assign load_1_o= (state_reg==load_oper); assign load_2_o= (state_reg==zero_info_state); //// always @(posedge clk, posedge rst) if (rst) begin state_reg <= start; end else begin state_reg <= state_next; end /// always @* begin state_next = state_reg; rst_int = 0; //Oper_Start_In control signals //load_1_o=0; //load_2_o=0; //Exp_operation control signals load_3_o=0; load_8_o=0; A_S_op_o=1; //Barrel shifter control signals load_4_o=0; left_right_o=0; bit_shift_o=0; //bit input for shifts fills //Add_Subt_sgf control signals load_5_o=0; //LZA control signals load_6_o=0; //Deco_Round control signals //None //Final_Result control signals load_7_o=0; ///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ //Multiplexer selector for Exp_operation's OPER_A ctrl_a_o=0; //Multiplexer selector for Exp_operation's OPER_B ctrl_b_o=2'b00; ctrl_b_load_o=0; //Multiplexer selector for Barrel_Shifter's Data shift ctrl_c_o=0; //Multiplexer selector for Barrel_Shifter's Shift value //Multiplexer selector for Add_Subt_Sgf's inputs ctrl_d_o=0; //Ready Phase ready = 0; //**REVISADO rst_int = 0; case(state_reg) //FPU reset start: begin rst_int=1; if(beg_FSM) begin state_next = load_oper; end end load_oper: //Load input registers for Oper_star in evaluation begin // load_1_o = 1; state_next = zero_info_state; end zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation begin if (zero_flag_i)begin state_next = ready_flag;end else begin //load_2_o = 1; state_next = load_diff_exp;end end load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in begin load_3_o = 1; /* if ()*/ state_next = extra1_64; end extra1_64: begin load_3_o = 1; if (norm_iteration_i)begin load_8_o=1; if(add_overflow_i)begin A_S_op_o=0; left_right_o=0; bit_shift_o=1; end else begin A_S_op_o=1; left_right_o=1; bit_shift_o=0; end end state_next = norm_sgf_first; end norm_sgf_first: // begin load_4_o = 1; if (norm_iteration_i)begin if(add_overflow_i)begin left_right_o=0; bit_shift_o=1; state_next = round_sgf; end else begin left_right_o=1; bit_shift_o=0; state_next = round_sgf;end end else state_next = add_subt; end add_subt: begin //Reg enables load_5_o = 1; ctrl_c_o = 1; state_next = overflow_add; end overflow_add: begin //Reg enables/Disables load_6_o=1; ctrl_b_load_o=1; if ( add_overflow_i)begin ctrl_b_o=2'b10; end else begin A_S_op_o=1; ctrl_b_o=2'b01; end //state_next = load_exp_oper_over; state_next = extra1_64; end round_sgf: begin load_4_o = 0; if(round_i) begin ctrl_d_o =1; ctrl_a_o = 1; state_next = add_subt_r; end else begin state_next = load_final_result; end end add_subt_r: begin load_5_o = 1; state_next = overflow_add_r; end overflow_add_r: begin ctrl_b_load_o=1; if ( add_overflow_i)begin ctrl_b_o=2'b10; end else begin ctrl_b_o=2'b11; end state_next = extra2_64; end extra2_64: begin load_3_o = 1; load_8_o = 1; if ( add_overflow_i)begin A_S_op_o=0; bit_shift_o=1; end state_next = norm_sgf_r; end norm_sgf_r: begin load_4_o = 1; if ( add_overflow_i)begin left_right_o=0; bit_shift_o=1; end state_next = load_final_result; end load_final_result: begin load_7_o = 1; state_next = ready_flag; end ready_flag: begin ready = 1; if(rst_FSM) begin state_next = start;end end default: begin state_next =start;end endcase end endmodule

`timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_9_b2s_aw_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Write Address Ports input wire [C_ID_WIDTH-1:0] s_awid , input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr , input wire [7:0] s_awlen , input wire [2:0] s_awsize , input wire [1:0] s_awburst , input wire s_awvalid , output wire s_awready , output wire m_awvalid , output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr , input wire m_awready , // Connections to/from axi_protocol_converter_v2_1_9_b2s_b_channel module output wire b_push , output wire [C_ID_WIDTH-1:0] b_awid , output wire [7:0] b_awlen , input wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire next ; wire next_pending ; wire a_push; wire incr_burst; reg [C_ID_WIDTH-1:0] s_awid_r; reg [7:0] s_awlen_r; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // Translate the AXI transaction to the MC transaction(s) axi_protocol_converter_v2_1_9_b2s_cmd_translator # ( .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ) cmd_translator_0 ( .clk ( clk ) , .reset ( reset ) , .s_axaddr ( s_awaddr ) , .s_axlen ( s_awlen ) , .s_axsize ( s_awsize ) , .s_axburst ( s_awburst ) , .s_axhandshake ( s_awvalid & a_push ) , .m_axaddr ( m_awaddr ) , .incr_burst ( incr_burst ) , .next ( next ) , .next_pending ( next_pending ) ); axi_protocol_converter_v2_1_9_b2s_wr_cmd_fsm aw_cmd_fsm_0 ( .clk ( clk ) , .reset ( reset ) , .s_awready ( s_awready ) , .s_awvalid ( s_awvalid ) , .m_awvalid ( m_awvalid ) , .m_awready ( m_awready ) , .next ( next ) , .next_pending ( next_pending ) , .b_push ( b_push ) , .b_full ( b_full ) , .a_push ( a_push ) ); assign b_awid = s_awid_r; assign b_awlen = s_awlen_r; always @(posedge clk) begin s_awid_r <= s_awid ; s_awlen_r <= s_awlen ; end endmodule `default_nettype wire

// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal // in the Software without restriction, including without limitation the rights // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell // copies of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: // The above copyright notice and this permission notice shall be included in // all copies or substantial portions of the Software. // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // // $Revision: 29455 $ // $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif // A synchronization module for resets. Output resets are held for // RSTDELAY+1 cycles, RSTDELAY >= 0. Both assertion and deassertions is // synchronized to the clock. module PositiveReset ( IN_RST, CLK, OUT_RST ); parameter RSTDELAY = 1 ; // Width of reset shift reg input CLK ; input IN_RST ; output OUT_RST ; (* ASYNC_REG = "true" *) reg reset_meta ; reg [RSTDELAY:1] reset_hold ; wire [RSTDELAY+1:0] next_reset = {reset_hold, reset_meta, 1'b0} ; assign OUT_RST = reset_hold[RSTDELAY] ; always @( posedge CLK ) // reset is read synchronous with clock begin if (IN_RST == `BSV_RESET_VALUE) begin reset_meta <= 1; end else begin reset_meta <= 0; end if (reset_meta == 1) begin reset_hold <= `BSV_ASSIGNMENT_DELAY -1 ; end else begin reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:1]; end end // always @ ( posedge CLK ) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off initial begin #0 ; // initialize out of reset forcing the designer to do one reset_hold = 0 ; end // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS endmodule // PositiveReset

// (C) 2001-2016 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License Subscription // Agreement, Intel MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Intel and sold by // Intel or its authorized distributors. Please refer to the applicable // agreement for further details. `timescale 1 ps / 1 ps (* altera_attribute = "-name GLOBAL_SIGNAL OFF" *) module hps_sdram_p0_reset( seq_reset_mem_stable, pll_afi_clk, pll_addr_cmd_clk, pll_dqs_ena_clk, seq_clk, scc_clk, pll_avl_clk, reset_n_scc_clk, reset_n_avl_clk, read_capture_clk, pll_locked, global_reset_n, soft_reset_n, ctl_reset_n, ctl_reset_export_n, reset_n_afi_clk, reset_n_addr_cmd_clk, reset_n_resync_clk, reset_n_seq_clk, reset_n_read_capture_clk ); parameter MEM_READ_DQS_WIDTH = ""; parameter NUM_AFI_RESET = 1; input seq_reset_mem_stable; input pll_afi_clk; input pll_addr_cmd_clk; input pll_dqs_ena_clk; input seq_clk; input scc_clk; input pll_avl_clk; output reset_n_scc_clk; output reset_n_avl_clk; input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk; input pll_locked; input global_reset_n; input soft_reset_n; output ctl_reset_n; output ctl_reset_export_n; output [NUM_AFI_RESET-1:0] reset_n_afi_clk; output reset_n_addr_cmd_clk; output reset_n_resync_clk; output reset_n_seq_clk; output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk; // Apply the synthesis keep attribute on the synchronized reset wires // so that these names can be constrained using QSF settings to keep // the resets on local routing. wire phy_reset_n /* synthesis keep = 1 */; wire phy_reset_mem_stable_n /* synthesis keep = 1*/; wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture; assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable; assign reset_n_read_capture_clk = reset_n_read_capture; assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n; hps_sdram_p0_reset_sync ureset_afi_clk( .reset_n (phy_reset_n), .clk (pll_afi_clk), .reset_n_sync (reset_n_afi_clk) ); defparam ureset_afi_clk.RESET_SYNC_STAGES = 15; defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET; hps_sdram_p0_reset_sync ureset_ctl_reset_clk( .reset_n (phy_reset_n), .clk (pll_afi_clk), .reset_n_sync ({ctl_reset_n, ctl_reset_export_n}) ); defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15; defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2; hps_sdram_p0_reset_sync ureset_addr_cmd_clk( .reset_n (phy_reset_n), .clk (pll_addr_cmd_clk), .reset_n_sync (reset_n_addr_cmd_clk) ); defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15; defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_resync_clk( .reset_n (phy_reset_n), .clk (pll_dqs_ena_clk), .reset_n_sync (reset_n_resync_clk) ); defparam ureset_resync_clk.RESET_SYNC_STAGES = 15; defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_seq_clk( .reset_n (phy_reset_n), .clk (seq_clk), .reset_n_sync (reset_n_seq_clk) ); defparam ureset_seq_clk.RESET_SYNC_STAGES = 15; defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_scc_clk( .reset_n (phy_reset_n), .clk (scc_clk), .reset_n_sync (reset_n_scc_clk) ); defparam ureset_scc_clk.RESET_SYNC_STAGES = 15; defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1; hps_sdram_p0_reset_sync ureset_avl_clk( .reset_n (phy_reset_n), .clk (pll_avl_clk), .reset_n_sync (reset_n_avl_clk) ); defparam ureset_avl_clk.RESET_SYNC_STAGES = 2; defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1; generate genvar i; for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1) begin: read_capture_reset hps_sdram_p0_reset_sync #( .RESET_SYNC_STAGES(15), .NUM_RESET_OUTPUT(1) ) ureset_read_capture_clk( .reset_n (phy_reset_mem_stable_n), .clk (read_capture_clk[i]), .reset_n_sync (reset_n_read_capture[i]) ); end endgenerate endmodule

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off MULTIDRIVEN /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v wire [15:0] out2; // From test of Test.v // End of automatics // verilator lint_on MULTIDRIVEN Test test ( .en (crc[21:20]), .a1 (crc[19:18]), .a0 (crc[17:16]), .d1 (crc[15:8]), .d0 (crc[7:0]), /*AUTOINST*/ // Outputs .out (out[31:0]), .out2 (out2[15:0]), // Inputs .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {out2, 16'h0, out}; // Test loop `ifdef TEST_VERBOSE always @ (negedge clk) begin $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); end `endif always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; test.clear(); end else if (cyc<10) begin sum <= 64'h0; test.clear(); end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc68a94a34ec970aa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, out2, // Inputs clk, en, a0, a1, d0, d1 ); input clk; input [1:0] en; input [1:0] a0; input [1:0] a1; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; // verilator lint_off MULTIDRIVEN reg [7:0] mem [4]; // verilator lint_on MULTIDRIVEN task clear(); for (int i=0; i<4; ++i) mem[i] = 0; endtask always @(posedge clk) begin if (en[0]) begin mem[a0] <= d0; out2[7:0] <= d0; end end always @(negedge clk) begin if (en[1]) begin mem[a1] <= d1; out2[15:8] <= d0; end end assign out = {mem[3],mem[2],mem[1],mem[0]}; endmodule

(** * Maps: Total and Partial Maps *) (** Maps (or dictionaries) are ubiquitous data structures, both in software construction generally and in the theory of programming languages in particular; we're going to need them in many places in the coming chapters. They also make a nice case study using ideas we've seen in previous chapters, including building data structures out of higher-order functions (from [Basics] and [Poly]) and the use of reflection to streamline proofs (from [IndProp]). We'll define two flavors of maps: _total_ maps, which include a "default" element to be returned when a key being looked up doesn't exist, and _partial_ maps, which return an [option] to indicate success or failure. The latter is defined in terms of the former, using [None] as the default element. *) (* ###################################################################### *) (** * The Coq Standard Library *) (** One small digression before we start. Unlike the chapters we have seen so far, this one does not [Require Import] the chapter before it (and, transitively, all the earlier chapters). Instead, in this chapter and from now, on we're going to import the definitions and theorems we need directly from Coq's standard library stuff. You should not notice much difference, though, because we've been careful to name our own definitions and theorems the same as their counterparts in the standard library, wherever they overlap. *) Require Import Coq.Arith.Arith. Require Import Coq.Bool.Bool. Require Import Coq.Logic.FunctionalExtensionality. (** Documentation for the standard library can be found at http://coq.inria.fr/library/. The [SearchAbout] command is a good way to look for theorems involving objects of specific types. *) (* ###################################################################### *) (** * Identifiers *) (** First, we need a type for the keys that we use to index into our maps. For this purpose, we again use the type [id] from the [Lists] chapter. To make this chapter self contained, we repeat its definition here, together with the equality comparison function for [id]s and its fundamental property. *) Inductive id : Type := | Id : nat -> id. Definition beq_id id1 id2 := match id1,id2 with | Id n1, Id n2 => beq_nat n1 n2 end. Theorem beq_id_refl : forall id, true = beq_id id id. Proof. intros [n]. simpl. rewrite <- beq_nat_refl. reflexivity. Qed. (** The following useful property of [beq_id] follows from an analogous lemma about numbers: *) Theorem beq_id_true_iff : forall id1 id2 : id, beq_id id1 id2 = true <-> id1 = id2. Proof. intros [n1] [n2]. unfold beq_id. rewrite beq_nat_true_iff. split. - (* -> *) intros H. rewrite H. reflexivity. - (* <- *) intros H. inversion H. reflexivity. Qed. (** Similarly: *) Theorem beq_id_false_iff : forall x y : id, beq_id x y = false <-> x <> y. Proof. intros x y. rewrite <- beq_id_true_iff. rewrite not_true_iff_false. reflexivity. Qed. (** This useful variant follows just by rewriting: *) Theorem false_beq_id : forall x y : id, x <> y -> beq_id x y = false. Proof. intros x y. rewrite beq_id_false_iff. intros H. apply H. Qed. (* ###################################################################### *) (** * Total Maps *) (** Our main job in this chapter will be to build a definition of partial maps that is similar in behavior to the one we saw in the [Lists] chapter, plus accompanying lemmas about their behavior. This time around, though, we're going to use _functions_, rather than lists of key-value pairs, to build maps. The advantage of this representation is that it offers a more _extensional_ view of maps, where two maps that respond to queries in the same way will be represented as literally the same thing (the same function), rather than just "equivalent" data structures. This, in turn, simplifies proofs that use maps. We build partial maps in two steps. First, we define a type of _total maps_ that return a default value when we look up a key that is not present in the map. *) Definition total_map (A:Type) := id -> A. (** Intuitively, a total map over an element type [A] _is_ just a function that can be used to look up [id]s, yielding [A]s. The function [t_empty] yields an empty total map, given a default element; this map always returns the default element when applied to any id. *) Definition t_empty {A:Type} (v : A) : total_map A := (fun _ => v). (** More interesting is the [update] function, which (as before) takes a map [m], a key [x], and a value [v] and returns a new map that takes [x] to [v] and takes every other key to whatever [m] does. *) Definition t_update {A:Type} (m : total_map A) (x : id) (v : A) := fun x' => if beq_id x x' then v else m x'. (** This definition is a nice example of higher-order programming. The [t_update] function takes a _function_ [m] and yields a new function [fun x' => ...] that behaves like the desired map. For example, we can build a map taking [id]s to [bool]s, where [Id 3] is mapped to [true] and every other key is mapped to [false], like this: *) Definition examplemap := t_update (t_update (t_empty false) (Id 1) false) (Id 3) true. (** This completes the definition of total maps. Note that we don't need to define a [find] operation because it is just function application! *) Example update_example1 : examplemap (Id 0) = false. Proof. reflexivity. Qed. Example update_example2 : examplemap (Id 1) = false. Proof. reflexivity. Qed. Example update_example3 : examplemap (Id 2) = false. Proof. reflexivity. Qed. Example update_example4 : examplemap (Id 3) = true. Proof. reflexivity. Qed. (** To use maps in later chapters, we'll need several fundamental facts about how they behave. Even if you don't work the following exercises, make sure you thoroughly understand the statements of the lemmas! (Some of the proofs require the functional extensionality axiom discussed in the [Logic] chapter, which is also included in the standard library.) *) (** **** Exercise: 2 stars, optional (t_update_eq) *) (** First, if we update a map [m] at a key [x] with a new value [v] and then look up [x] in the map resulting from the [update], we get back [v]: *) Lemma t_update_eq : forall A (m: total_map A) x v, (t_update m x v) x = v. Proof. intros. unfold t_update. rewrite <- beq_id_refl. reflexivity. Qed. (** [] *) (** **** Exercise: 2 stars, optional (t_update_neq) *) (** On the other hand, if we update a map [m] at a key [x1] and then look up a _different_ key [x2] in the resulting map, we get the same result that [m] would have given: *) Theorem t_update_neq : forall (X:Type) v x1 x2 (m : total_map X), x1 <> x2 -> (t_update m x1 v) x2 = m x2. Proof. intros. unfold t_update. apply false_beq_id in H. rewrite H. reflexivity. Qed. (** [] *) (** **** Exercise: 2 stars, optional (t_update_shadow) *) (** If we update a map [m] at a key [x] with a value [v1] and then update again with the same key [x] and another value [v2], the resulting map behaves the same (gives the same result when applied to any key) as the simpler map obtained by performing just the second [update] on [m]: *) Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x, t_update (t_update m x v1) x v2 = t_update m x v2. Proof. intros. unfold t_update. apply functional_extensionality. intros. destruct (beq_id x x0). - reflexivity. - reflexivity. Qed. (** [] *) (** For the final two lemmas about total maps, it's convenient to use the reflection idioms introduced in chapter [IndProp]. We begin by proving a fundamental _reflection lemma_ relating the equality proposition on [id]s with the boolean function [beq_id]. *) (** **** Exercise: 2 stars (beq_idP) *) (** Use the proof of [beq_natP] in chapter [IndProp] as a template to prove the following: *) Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y). Proof. intros x y. apply iff_reflect. rewrite beq_id_true_iff. reflexivity. Qed. (** [] *) (** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP x1 x2)] to simultaneously perform case analysis on the result of [beq_id x1 x2] and generate hypotheses about the equality (in the sense of [=]) of [x1] and [x2]. *) (** **** Exercise: 2 stars (t_update_same) *) (** Using the example in chapter [IndProp] as a template, use [beq_idP] to prove the following theorem, which states that if we update a map to assign key [x] the same value as it already has in [m], then the result is equal to [m]: *) Theorem t_update_same : forall X x (m : total_map X), t_update m x (m x) = m. Proof. intros. unfold t_update. apply functional_extensionality. intros. destruct (beq_idP x x0) as [H | H']. - rewrite H. reflexivity. - reflexivity. Qed. (** [] *) (** **** Exercise: 3 stars, recommended (t_update_permute) *) (** Use [beq_idP] to prove one final property of the [update] function: If we update a map [m] at two distinct keys, it doesn't matter in which order we do the updates. *) Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2 (m : total_map X), x2 <> x1 -> (t_update (t_update m x2 v2) x1 v1) = (t_update (t_update m x1 v1) x2 v2). Proof. intros. unfold t_update. apply functional_extensionality. intros. destruct (beq_idP x1 x). - destruct (beq_idP x2 x). * destruct H. rewrite e. rewrite e0. reflexivity. * reflexivity. - destruct (beq_idP x2 x). * reflexivity. * reflexivity. Qed. (** [] *) (* ###################################################################### *) (** * Partial maps *) (** Finally, we define _partial maps_ on top of total maps. A partial map with elements of type [A] is simply a total map with elements of type [option A] and default element [None]. *) Definition partial_map (A:Type) := total_map (option A). Definition empty {A:Type} : partial_map A := t_empty None. Definition update {A:Type} (m : partial_map A) (x : id) (v : A) := t_update m x (Some v). (** We can now lift all of the basic lemmas about total maps to partial maps. *) Lemma update_eq : forall A (m: partial_map A) x v, (update m x v) x = Some v. Proof. intros. unfold update. rewrite t_update_eq. reflexivity. Qed. Theorem update_neq : forall (X:Type) v x1 x2 (m : partial_map X), x2 <> x1 -> (update m x2 v) x1 = m x1. Proof. intros X v x1 x2 m H. unfold update. rewrite t_update_neq. reflexivity. apply H. Qed. Lemma update_shadow : forall A (m: partial_map A) v1 v2 x, update (update m x v1) x v2 = update m x v2. Proof. intros A m v1 v2 x1. unfold update. rewrite t_update_shadow. reflexivity. Qed. Theorem update_same : forall X v x (m : partial_map X), m x = Some v -> update m x v = m. Proof. intros X v x m H. unfold update. rewrite <- H. apply t_update_same. Qed. Theorem update_permute : forall (X:Type) v1 v2 x1 x2 (m : partial_map X), x2 <> x1 -> (update (update m x2 v2) x1 v1) = (update (update m x1 v1) x2 v2). Proof. intros X v1 v2 x1 x2 m. unfold update. apply t_update_permute. Qed. (** $Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $ *)

//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_0_oci_test_bench ( // inputs: dct_buffer, dct_count, test_ending, test_has_ended ) ; input [ 29: 0] dct_buffer; input [ 3: 0] dct_count; input test_ending; input test_has_ended; endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V `define SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V /** * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hdll__dlygate4sd3 ( //# {{data|Data Signals}} input A , output X , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V

// megafunction wizard: %ALTGX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: alt_c3gxb // ============================================================ // File Name: altera_tse_altgx_civgx_gige.v // Megafunction Name(s): // alt_c3gxb // // Simulation Library Files(s): // altera_mf;cycloneiv_hssi // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.1 Build 345 02/24/2010 SP 2 SJ Full Version // ************************************************************ //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk gxb_powerdown pll_inclk reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX" //VERSION_BEGIN 9.1SP2 cbx_alt_c3gxb 2010:02:24:21:06:43:SJ cbx_altpll 2010:02:24:21:06:43:SJ cbx_cycloneii 2010:02:24:21:06:43:SJ cbx_mgl 2010:02:24:21:13:40:SJ cbx_stingray 2010:02:24:21:06:43:SJ cbx_stratixii 2010:02:24:21:06:43:SJ cbx_util_mgl 2010:02:24:21:06:43:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 //synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module altera_tse_altgx_civgx_gige_alt_c3gxb_vs07 ( cal_blk_clk, gxb_powerdown, pll_inclk, reconfig_clk, reconfig_fromgxb, reconfig_togxb, rx_analogreset, rx_ctrldetect, rx_datain, rx_dataout, rx_digitalreset, rx_disperr, rx_errdetect, rx_patterndetect, rx_rlv, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_runningdisp, rx_syncstatus, tx_clkout, tx_ctrlenable, tx_datain, tx_dataout, tx_digitalreset) ; input cal_blk_clk; input [0:0] gxb_powerdown; input pll_inclk; input reconfig_clk; output [4:0] reconfig_fromgxb; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; output [0:0] rx_ctrldetect; input [0:0] rx_datain; output [7:0] rx_dataout; input [0:0] rx_digitalreset; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_patterndetect; output [0:0] rx_rlv; output [0:0] rx_rmfifodatadeleted; output [0:0] rx_rmfifodatainserted; output [0:0] rx_runningdisp; output [0:0] rx_syncstatus; output [0:0] tx_clkout; input [0:0] tx_ctrlenable; input [7:0] tx_datain; output [0:0] tx_dataout; input [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 cal_blk_clk; tri0 [0:0] gxb_powerdown; tri0 reconfig_clk; tri0 [0:0] rx_analogreset; tri0 [0:0] rx_digitalreset; tri0 [0:0] tx_ctrlenable; tri0 [7:0] tx_datain; tri0 [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif parameter starting_channel_number = 0; wire [5:0] wire_pll0_clk; wire wire_pll0_fref; wire wire_pll0_icdrclk; wire wire_cal_blk0_nonusertocmu; wire wire_cent_unit0_dprioout; wire wire_cent_unit0_quadresetout; wire [3:0] wire_cent_unit0_rxanalogresetout; wire [3:0] wire_cent_unit0_rxcrupowerdown; wire [3:0] wire_cent_unit0_rxdigitalresetout; wire [3:0] wire_cent_unit0_rxibpowerdown; wire [3:0] wire_cent_unit0_txanalogresetout; wire [3:0] wire_cent_unit0_txdetectrxpowerdown; wire [3:0] wire_cent_unit0_txdigitalresetout; wire [3:0] wire_cent_unit0_txdividerpowerdown; wire [3:0] wire_cent_unit0_txobpowerdown; wire wire_receive_pcs0_cdrctrllocktorefclkout; wire [1:0] wire_receive_pcs0_ctrldetect; wire [19:0] wire_receive_pcs0_dataout; wire [1:0] wire_receive_pcs0_disperr; wire [1:0] wire_receive_pcs0_errdetect; wire [1:0] wire_receive_pcs0_patterndetect; wire wire_receive_pcs0_rlv; wire [1:0] wire_receive_pcs0_rmfifodatadeleted; wire [1:0] wire_receive_pcs0_rmfifodatainserted; wire [1:0] wire_receive_pcs0_runningdisp; wire wire_receive_pcs0_signaldetect; wire [1:0] wire_receive_pcs0_syncstatus; wire [7:0] wire_receive_pma0_analogtestbus; wire wire_receive_pma0_clockout; wire wire_receive_pma0_locktorefout; wire [9:0] wire_receive_pma0_recoverdataout; wire wire_receive_pma0_signaldetect; wire wire_transmit_pcs0_clkout; wire [9:0] wire_transmit_pcs0_dataout; wire wire_transmit_pcs0_forceelecidleout; wire wire_transmit_pcs0_txdetectrx; wire wire_transmit_pma0_clockout; wire wire_transmit_pma0_dataout; wire wire_transmit_pma0_seriallpbkout; wire cal_blk_powerdown; wire [0:0] cent_unit_quadresetout; wire [3:0] cent_unit_rxcrupowerdn; wire [3:0] cent_unit_rxibpowerdn; wire [3:0] cent_unit_txdetectrxpowerdn; wire [3:0] cent_unit_txdividerpowerdown; wire [3:0] cent_unit_txobpowerdn; wire [3:0] fixedclk_to_cmu; wire [0:0] nonusertocmu_out; wire [0:0] pll_powerdown; wire [0:0] reconfig_togxb_busy; wire [0:0] reconfig_togxb_disable; wire [0:0] reconfig_togxb_in; wire [0:0] reconfig_togxb_load; wire [3:0] rx_analogreset_in; wire [3:0] rx_analogreset_out; wire [0:0] rx_coreclk_in; wire [0:0] rx_deserclock_in; wire [3:0] rx_digitalreset_in; wire [3:0] rx_digitalreset_out; wire [0:0] rx_enapatternalign; wire [0:0] rx_locktodata; wire [0:0] rx_locktorefclk; wire [0:0] rx_locktorefclk_wire; wire [7:0] rx_out_wire; wire [0:0] rx_phfifordenable; wire [0:0] rx_phfiforeset; wire [0:0] rx_phfifowrdisable; wire [0:0] rx_pll_pfdrefclkout_wire; wire [4:0] rx_pma_analogtestbus; wire [0:0] rx_pma_clockout; wire [9:0] rx_pma_recoverdataout_wire; wire [0:0] rx_powerdown; wire [3:0] rx_powerdown_in; wire [0:0] rx_prbscidenable; wire [0:0] rx_rmfiforeset; wire [0:0] rx_signaldetect_wire; wire [3:0] tx_analogreset_out; wire [0:0] tx_clkout_int_wire; wire [0:0] tx_core_clkout_wire; wire [0:0] tx_coreclk_in; wire [7:0] tx_datain_wire; wire [9:0] tx_dataout_pcs_to_pma; wire [3:0] tx_digitalreset_in; wire [3:0] tx_digitalreset_out; wire [0:0] tx_forcedisp_wire; wire [0:0] tx_invpolarity; wire [0:0] tx_localrefclk; wire [0:0] tx_phfiforeset; wire [0:0] tx_pma_fastrefclk0in; wire [0:0] tx_pma_refclk0in; wire [0:0] tx_pma_refclk0inpulse; wire [0:0] tx_serialloopbackout; wire [0:0] txdataout; wire [0:0] txdetectrxout; altpll pll0 ( .activeclock(), .areset(pll_powerdown[0]), .clk(wire_pll0_clk), .clkbad(), .clkloss(), .enable0(), .enable1(), .extclk(), .fbout(), .fref(wire_pll0_fref), .icdrclk(wire_pll0_icdrclk), .inclk({{1{1'b0}}, pll_inclk}), .locked(), .phasedone(), .scandataout(), .scandone(), .sclkout0(), .sclkout1(), .vcooverrange(), .vcounderrange() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clkena({6{1'b1}}), .clkswitch(1'b0), .configupdate(1'b0), .extclkena({4{1'b1}}), .fbin(1'b1), .pfdena(1'b1), .phasecounterselect({4{1'b1}}), .phasestep(1'b1), .phaseupdown(1'b1), .pllena(1'b1), .scanaclr(1'b0), .scanclk(1'b0), .scanclkena(1'b1), .scandata(1'b0), .scanread(1'b0), .scanwrite(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam pll0.bandwidth_type = "HIGH", pll0.clk0_divide_by = 1, pll0.clk0_multiply_by = 5, pll0.clk1_divide_by = 5, pll0.clk1_multiply_by = 5, pll0.clk2_divide_by = 5, pll0.clk2_duty_cycle = 20, pll0.clk2_multiply_by = 5, pll0.dpa_divide_by = 1, pll0.dpa_multiply_by = 5, pll0.inclk0_input_frequency = 8000, pll0.operation_mode = "no_compensation", pll0.intended_device_family = "Cyclone IV GX", pll0.lpm_type = "altpll"; cycloneiv_hssi_calibration_block cal_blk0 ( .calibrationstatus(), .clk(cal_blk_clk), .nonusertocmu(wire_cal_blk0_nonusertocmu), .powerdn(cal_blk_powerdown) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .testctrl(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); cycloneiv_hssi_cmu cent_unit0 ( .alignstatus(), .coreclkout(), .digitaltestout(), .dpclk(reconfig_clk), .dpriodisable(reconfig_togxb_disable), .dpriodisableout(), .dprioin(reconfig_togxb_in), .dprioload(reconfig_togxb_load), .dpriooe(), .dprioout(wire_cent_unit0_dprioout), .enabledeskew(), .fiforesetrd(), .fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}), .nonuserfromcal(nonusertocmu_out[0]), .quadreset(gxb_powerdown[0]), .quadresetout(wire_cent_unit0_quadresetout), .refclkout(), .rxanalogreset({rx_analogreset_in[3:0]}), .rxanalogresetout(wire_cent_unit0_rxanalogresetout), .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown), .rxctrlout(), .rxdataout(), .rxdigitalreset({rx_digitalreset_in[3:0]}), .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout), .rxibpowerdown(wire_cent_unit0_rxibpowerdown), .rxphfifox4byteselout(), .rxphfifox4rdenableout(), .rxphfifox4wrclkout(), .rxphfifox4wrenableout(), .rxpowerdown({rx_powerdown_in[3:0]}), .testout(), .txanalogresetout(wire_cent_unit0_txanalogresetout), .txctrlout(), .txdataout(), .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown), .txdigitalreset({tx_digitalreset_in[3:0]}), .txdigitalresetout(wire_cent_unit0_txdigitalresetout), .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown), .txobpowerdown(wire_cent_unit0_txobpowerdown), .txphfifox4byteselout(), .txphfifox4rdclkout(), .txphfifox4rdenableout(), .txphfifox4wrenableout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .adet({4{1'b0}}), .pmacramtest(1'b0), .rdalign({4{1'b0}}), .rdenablesync(1'b1), .recovclk(1'b0), .refclkdig(1'b0), .rxcoreclk(1'b0), .rxctrl({4{1'b0}}), .rxdatain({32{1'b0}}), .rxdatavalid({4{1'b0}}), .rxphfifordenable(1'b1), .rxphfiforeset(1'b0), .rxphfifowrdisable(1'b0), .rxrunningdisp({4{1'b0}}), .scanclk(1'b0), .scanmode(1'b0), .scanshift(1'b0), .syncstatus({4{1'b0}}), .testin({2000{1'b0}}), .txclk(1'b0), .txcoreclk(1'b0), .txctrl({4{1'b0}}), .txdatain({32{1'b0}}), .txphfiforddisable(1'b0), .txphfiforeset(1'b0), .txphfifowrenable(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8, cent_unit0.auto_spd_phystatus_notify_count = 0, cent_unit0.in_xaui_mode = "false", cent_unit0.rx0_channel_bonding = "none", cent_unit0.rx0_clk1_mux_select = "recovered clock", cent_unit0.rx0_clk2_mux_select = "local reference clock", cent_unit0.rx0_ph_fifo_reg_mode = "false", cent_unit0.rx0_rd_clk_mux_select = "core clock", cent_unit0.rx0_recovered_clk_mux_select = "recovered clock", cent_unit0.rx0_reset_clock_output_during_digital_reset = "false", cent_unit0.rx0_use_double_data_mode = "false", cent_unit0.tx0_channel_bonding = "none", cent_unit0.tx0_rd_clk_mux_select = "central", cent_unit0.tx0_reset_clock_output_during_digital_reset = "false", cent_unit0.tx0_use_double_data_mode = "false", cent_unit0.tx0_wr_clk_mux_select = "core_clk", cent_unit0.use_coreclk_out_post_divider = "false", cent_unit0.use_deskew_fifo = "false", cent_unit0.lpm_type = "cycloneiv_hssi_cmu"; cycloneiv_hssi_rx_pcs receive_pcs0 ( .a1a2size(1'b0), .a1a2sizeout(), .a1detect(), .a2detect(), .adetectdeskew(), .alignstatussyncout(), .bistdone(), .bisterr(), .bitslipboundaryselectout(), .byteorderalignstatus(), .cdrctrlearlyeios(), .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])), .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout), .clkout(), .coreclk(rx_coreclk_in[0]), .coreclkout(), .ctrldetect(wire_receive_pcs0_ctrldetect), .datain(rx_pma_recoverdataout_wire[9:0]), .dataout(wire_receive_pcs0_dataout), .dataoutfull(), .digitalreset(rx_digitalreset_out[0]), .disperr(wire_receive_pcs0_disperr), .enabyteord(1'b0), .enapatternalign(rx_enapatternalign[0]), .errdetect(wire_receive_pcs0_errdetect), .fifordout(), .hipdataout(), .hipdatavalid(), .hipelecidle(), .hipphydonestatus(), .hipstatus(), .invpol(1'b0), .k1detect(), .k2detect(), .localrefclk(tx_localrefclk[0]), .parallelfdbk({20{1'b0}}), .patterndetect(wire_receive_pcs0_patterndetect), .phfifooverflow(), .phfifordenable(rx_phfifordenable[0]), .phfifordenableout(), .phfiforeset(rx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrdisable(rx_phfifowrdisable[0]), .phfifowrdisableout(), .pipebufferstat(), .pipedatavalid(), .pipeelecidle(), .pipephydonestatus(), .pipepowerdown({2{1'b0}}), .pipepowerstate({4{1'b0}}), .pipestatus(), .prbscidenable(rx_prbscidenable[0]), .quadreset(cent_unit_quadresetout[0]), .rdalign(), .recoveredclk(rx_pma_clockout[0]), .revbitorderwa(1'b0), .revparallelfdbkdata(), .rlv(wire_receive_pcs0_rlv), .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted), .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted), .rmfifoempty(), .rmfifofull(), .rmfifordena(1'b0), .rmfiforeset(rx_rmfiforeset[0]), .rmfifowrena(1'b0), .runningdisp(wire_receive_pcs0_runningdisp), .rxdetectvalid(1'b0), .rxfound({2{1'b0}}), .signaldetect(wire_receive_pcs0_signaldetect), .signaldetected(rx_signaldetect_wire[0]), .syncstatus(wire_receive_pcs0_syncstatus), .syncstatusdeskew(), .xauidelcondmetout(), .xauififoovrout(), .xauiinsertincompleteout(), .xauilatencycompout(), .xgmctrldet(), .xgmdataout(), .xgmdatavalid(), .xgmrunningdisp() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .alignstatus(1'b0), .alignstatussync(1'b0), .bitslip(1'b0), .elecidleinfersel({3{1'b0}}), .enabledeskew(1'b0), .fifordin(1'b0), .fiforesetrd(1'b0), .grayelecidleinferselfromtx({3{1'b0}}), .hip8b10binvpolarity(1'b0), .hipelecidleinfersel({3{1'b0}}), .hippowerdown({2{1'b0}}), .masterclk(1'b0), .phfifox4bytesel(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrclk(1'b0), .phfifox4wrenable(1'b0), .pipe8b10binvpolarity(1'b0), .pipeenrevparallellpbkfromtx(1'b0), .pmatestbusin({8{1'b0}}), .powerdn({2{1'b0}}), .refclk(1'b0), .wareset(1'b0), .xauidelcondmet(1'b0), .xauififoovr(1'b0), .xauiinsertincomplete(1'b0), .xauilatencycomp(1'b0), .xgmctrlin(1'b0), .xgmdatain({8{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pcs0.align_pattern = "0101111100", receive_pcs0.align_pattern_length = 10, receive_pcs0.allow_align_polarity_inversion = "false", receive_pcs0.allow_pipe_polarity_inversion = "false", receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8, receive_pcs0.auto_spd_phystatus_notify_count = 0, receive_pcs0.bit_slip_enable = "false", receive_pcs0.byte_order_mode = "none", receive_pcs0.byte_order_pad_pattern = "0", receive_pcs0.byte_order_pattern = "0", receive_pcs0.byte_order_pld_ctrl_enable = "false", receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000, receive_pcs0.cdrctrl_enable = "false", receive_pcs0.cdrctrl_mask_cycle = 800, receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63, receive_pcs0.cdrctrl_rxvalid_mask = "false", receive_pcs0.channel_bonding = "none", receive_pcs0.channel_number = ((starting_channel_number + 0) % 4), receive_pcs0.channel_width = 8, receive_pcs0.clk1_mux_select = "recovered clock", receive_pcs0.clk2_mux_select = "local reference clock", receive_pcs0.datapath_low_latency_mode = "false", receive_pcs0.datapath_protocol = "basic", receive_pcs0.dec_8b_10b_compatibility_mode = "true", receive_pcs0.dec_8b_10b_mode = "normal", receive_pcs0.deskew_pattern = "0", receive_pcs0.disable_auto_idle_insertion = "true", receive_pcs0.disable_running_disp_in_word_align = "false", receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false", receive_pcs0.elec_idle_infer_enable = "false", receive_pcs0.elec_idle_num_com_detect = 3, receive_pcs0.enable_bit_reversal = "false", receive_pcs0.enable_self_test_mode = "false", receive_pcs0.force_signal_detect_dig = "true", receive_pcs0.hip_enable = "false", receive_pcs0.infiniband_invalid_code = 0, receive_pcs0.insert_pad_on_underflow = "false", receive_pcs0.num_align_code_groups_in_ordered_set = 1, receive_pcs0.num_align_cons_good_data = 4, receive_pcs0.num_align_cons_pat = 3, receive_pcs0.num_align_loss_sync_error = 4, receive_pcs0.ph_fifo_low_latency_enable = "true", receive_pcs0.ph_fifo_reg_mode = "false", receive_pcs0.protocol_hint = "gige", receive_pcs0.rate_match_back_to_back = "true", receive_pcs0.rate_match_delete_threshold = 13, receive_pcs0.rate_match_empty_threshold = 5, receive_pcs0.rate_match_fifo_mode = "true", receive_pcs0.rate_match_full_threshold = 20, receive_pcs0.rate_match_insert_threshold = 11, receive_pcs0.rate_match_ordered_set_based = "true", receive_pcs0.rate_match_pattern1 = "10100010010101111100", receive_pcs0.rate_match_pattern2 = "10101011011010000011", receive_pcs0.rate_match_pattern_size = 20, receive_pcs0.rate_match_reset_enable = "false", receive_pcs0.rate_match_skip_set_based = "false", receive_pcs0.rate_match_start_threshold = 7, receive_pcs0.rd_clk_mux_select = "core clock", receive_pcs0.recovered_clk_mux_select = "recovered clock", receive_pcs0.run_length = 5, receive_pcs0.run_length_enable = "true", receive_pcs0.rx_detect_bypass = "false", receive_pcs0.rx_phfifo_wait_cnt = 15, receive_pcs0.rxstatus_error_report_mode = 0, receive_pcs0.self_test_mode = "incremental", receive_pcs0.use_alignment_state_machine = "true", receive_pcs0.use_deskew_fifo = "false", receive_pcs0.use_double_data_mode = "false", receive_pcs0.use_parallel_loopback = "false", receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs"; cycloneiv_hssi_rx_pma receive_pma0 ( .analogtestbus(wire_receive_pma0_analogtestbus), .clockout(wire_receive_pma0_clockout), .crupowerdn(cent_unit_rxcrupowerdn[0]), .datain(rx_datain[0]), .datastrobeout(), .deserclock(rx_deserclock_in[0]), .diagnosticlpbkout(), .freqlocked(), .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])), .locktoref(rx_locktorefclk_wire[0]), .locktorefout(wire_receive_pma0_locktorefout), .powerdn(cent_unit_rxibpowerdn[0]), .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]), .recoverdataout(wire_receive_pma0_recoverdataout), .reverselpbkout(), .rxpmareset(rx_analogreset_out[0]), .seriallpbkin(tx_serialloopbackout[0]), .signaldetect(wire_receive_pma0_signaldetect), .testbussel(4'b0110) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .dpashift(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pma0.allow_serial_loopback = "true", receive_pma0.channel_number = ((starting_channel_number + 0) % 4), receive_pma0.common_mode = "0.82V", receive_pma0.deserialization_factor = 10, receive_pma0.effective_data_rate = "1250 Mbps", receive_pma0.enable_ltd = "false", receive_pma0.enable_ltr = "false", receive_pma0.eq_dc_gain = 0, receive_pma0.eq_setting = 1, receive_pma0.force_signal_detect = "true", receive_pma0.offset_cancellation = 1, receive_pma0.ppm_gen1_2_xcnt_en = 1, receive_pma0.ppm_post_eidle = 0, receive_pma0.ppmselect = 32, receive_pma0.protocol_hint = "gige", receive_pma0.signal_detect_hysteresis = 2, receive_pma0.signal_detect_hysteresis_valid_threshold = 1, receive_pma0.signal_detect_loss_threshold = 1, receive_pma0.termination = "OCT 100 Ohms", receive_pma0.use_external_termination = "false", receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma"; cycloneiv_hssi_tx_pcs transmit_pcs0 ( .clkout(wire_transmit_pcs0_clkout), .coreclk(tx_coreclk_in[0]), .coreclkout(), .ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}), .datain({{12{1'b0}}, tx_datain_wire[7:0]}), .datainfull({22{1'b0}}), .dataout(wire_transmit_pcs0_dataout), .detectrxloop(1'b0), .digitalreset(tx_digitalreset_out[0]), .enrevparallellpbk(1'b0), .forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}), .forceelecidleout(wire_transmit_pcs0_forceelecidleout), .grayelecidleinferselout(), .hiptxclkout(), .invpol(tx_invpolarity[0]), .localrefclk(tx_localrefclk[0]), .parallelfdbkout(), .phfifooverflow(), .phfiforddisable(1'b0), .phfiforddisableout(), .phfiforeset(tx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrenable(1'b1), .phfifowrenableout(), .pipeenrevparallellpbkout(), .pipepowerdownout(), .pipepowerstateout(), .powerdn({2{1'b0}}), .quadreset(cent_unit_quadresetout[0]), .rdenablesync(), .revparallelfdbk({20{1'b0}}), .txdetectrx(wire_transmit_pcs0_txdetectrx), .xgmctrlenable(), .xgmdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .bitslipboundaryselect({5{1'b0}}), .dispval({2{1'b0}}), .elecidleinfersel({3{1'b0}}), .forceelecidle(1'b0), .hipdatain({10{1'b0}}), .hipdetectrxloop(1'b0), .hipelecidleinfersel({3{1'b0}}), .hipforceelecidle(1'b0), .hippowerdn({2{1'b0}}), .phfifox4bytesel(1'b0), .phfifox4rdclk(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrenable(1'b0), .pipetxswing(1'b0), .prbscidenable(1'b0), .refclk(1'b0), .xgmctrl(1'b0), .xgmdatain({8{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pcs0.allow_polarity_inversion = "false", transmit_pcs0.bitslip_enable = "false", transmit_pcs0.channel_bonding = "none", transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4), transmit_pcs0.channel_width = 8, transmit_pcs0.datapath_low_latency_mode = "false", transmit_pcs0.datapath_protocol = "basic", transmit_pcs0.disable_ph_low_latency_mode = "false", transmit_pcs0.disparity_mode = "none", transmit_pcs0.elec_idle_delay = 6, transmit_pcs0.enable_bit_reversal = "false", transmit_pcs0.enable_idle_selection = "true", transmit_pcs0.enable_reverse_parallel_loopback = "false", transmit_pcs0.enable_self_test_mode = "false", transmit_pcs0.enc_8b_10b_compatibility_mode = "true", transmit_pcs0.enc_8b_10b_mode = "normal", transmit_pcs0.hip_enable = "false", transmit_pcs0.ph_fifo_reg_mode = "false", transmit_pcs0.prbs_cid_pattern = "false", transmit_pcs0.protocol_hint = "gige", transmit_pcs0.refclk_select = "local", transmit_pcs0.self_test_mode = "incremental", transmit_pcs0.use_double_data_mode = "false", transmit_pcs0.wr_clk_mux_select = "core_clk", transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs"; cycloneiv_hssi_tx_pma transmit_pma0 ( .cgbpowerdn(cent_unit_txdividerpowerdown[0]), .clockout(wire_transmit_pma0_clockout), .datain({tx_dataout_pcs_to_pma[9:0]}), .dataout(wire_transmit_pma0_dataout), .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]), .fastrefclk0in(tx_pma_fastrefclk0in[0]), .forceelecidle(1'b0), .powerdn(cent_unit_txobpowerdn[0]), .refclk0in(tx_pma_refclk0in[0]), .refclk0inpulse(tx_pma_refclk0inpulse[0]), .reverselpbkin(1'b0), .rxdetecten(txdetectrxout[0]), .rxdetectvalidout(), .rxfoundout(), .seriallpbkout(wire_transmit_pma0_seriallpbkout), .txpmareset(tx_analogreset_out[0]) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .diagnosticlpbkin(1'b0), .rxdetectclk(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pma0.channel_number = ((starting_channel_number + 0) % 4), transmit_pma0.common_mode = "0.65V", transmit_pma0.effective_data_rate = "1250 Mbps", transmit_pma0.enable_reverse_serial_loopback = "false", transmit_pma0.preemp_tap_1 = 1, transmit_pma0.protocol_hint = "gige", transmit_pma0.rx_detect = 0, transmit_pma0.serialization_factor = 10, transmit_pma0.slew_rate = "medium", transmit_pma0.termination = "OCT 100 Ohms", transmit_pma0.use_external_termination = "false", transmit_pma0.use_rx_detect = "false", transmit_pma0.vod_selection = 1, transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma"; assign cal_blk_powerdown = 1'b0, cent_unit_quadresetout = {wire_cent_unit0_quadresetout}, cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]}, cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]}, cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]}, cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]}, cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]}, fixedclk_to_cmu = {4{reconfig_clk}}, nonusertocmu_out = {wire_cal_blk0_nonusertocmu}, pll_powerdown = 1'b0, reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout}, reconfig_togxb_busy = reconfig_togxb[3], reconfig_togxb_disable = reconfig_togxb[1], reconfig_togxb_in = reconfig_togxb[0], reconfig_togxb_load = reconfig_togxb[2], rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])}, rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]}, rx_coreclk_in = {tx_core_clkout_wire[0]}, rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]}, rx_dataout = {rx_out_wire[7:0]}, rx_deserclock_in = {wire_pll0_icdrclk}, rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]}, rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]}, rx_disperr = {wire_receive_pcs0_disperr[0]}, rx_enapatternalign = 1'b0, rx_errdetect = {wire_receive_pcs0_errdetect[0]}, rx_locktodata = 1'b0, rx_locktorefclk = 1'b0, rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout}, rx_out_wire = {wire_receive_pcs0_dataout[7:0]}, rx_patterndetect = {wire_receive_pcs0_patterndetect[0]}, rx_phfifordenable = 1'b1, rx_phfiforeset = 1'b0, rx_phfifowrdisable = 1'b0, rx_pll_pfdrefclkout_wire = {wire_pll0_fref}, rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]}, rx_pma_clockout = {wire_receive_pma0_clockout}, rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]}, rx_powerdown = 1'b0, rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]}, rx_prbscidenable = 1'b0, rx_rlv = {wire_receive_pcs0_rlv}, rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]}, rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]}, rx_rmfiforeset = 1'b0, rx_runningdisp = {wire_receive_pcs0_runningdisp[0]}, rx_signaldetect_wire = {wire_receive_pma0_signaldetect}, rx_syncstatus = {wire_receive_pcs0_syncstatus[0]}, tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]}, tx_clkout = {tx_core_clkout_wire[0]}, tx_clkout_int_wire = {wire_transmit_pcs0_clkout}, tx_core_clkout_wire = {tx_clkout_int_wire[0]}, tx_coreclk_in = {tx_clkout_int_wire[0]}, tx_datain_wire = {tx_datain[7:0]}, tx_dataout = {txdataout[0]}, tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]}, tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]}, tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]}, tx_forcedisp_wire = {1'b0}, tx_invpolarity = 1'b0, tx_localrefclk = {wire_transmit_pma0_clockout}, tx_phfiforeset = 1'b0, tx_pma_fastrefclk0in = {wire_pll0_clk[0]}, tx_pma_refclk0in = {wire_pll0_clk[1]}, tx_pma_refclk0inpulse = {wire_pll0_clk[2]}, tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout}, txdataout = {wire_transmit_pma0_dataout}, txdetectrxout = {wire_transmit_pcs0_txdetectrx}; endmodule //altera_tse_altgx_civgx_gige_alt_c3gxb_vs07 //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module altera_tse_altgx_civgx_gige ( cal_blk_clk, gxb_powerdown, pll_inclk, reconfig_clk, reconfig_togxb, rx_analogreset, rx_datain, rx_digitalreset, tx_ctrlenable, tx_datain, tx_digitalreset, reconfig_fromgxb, rx_ctrldetect, rx_dataout, rx_disperr, rx_errdetect, rx_patterndetect, rx_rlv, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_runningdisp, rx_syncstatus, tx_clkout, tx_dataout); input cal_blk_clk; input [0:0] gxb_powerdown; input pll_inclk; input reconfig_clk; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; input [0:0] rx_datain; input [0:0] rx_digitalreset; input [0:0] tx_ctrlenable; input [7:0] tx_datain; input [0:0] tx_digitalreset; output [4:0] reconfig_fromgxb; output [0:0] rx_ctrldetect; output [7:0] rx_dataout; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_patterndetect; output [0:0] rx_rlv; output [0:0] rx_rmfifodatadeleted; output [0:0] rx_rmfifodatainserted; output [0:0] rx_runningdisp; output [0:0] rx_syncstatus; output [0:0] tx_clkout; output [0:0] tx_dataout; parameter starting_channel_number = 0; wire [0:0] sub_wire0; wire [0:0] sub_wire1; wire [0:0] sub_wire2; wire [0:0] sub_wire3; wire [0:0] sub_wire4; wire [0:0] sub_wire5; wire [0:0] sub_wire6; wire [0:0] sub_wire7; wire [0:0] sub_wire8; wire [0:0] sub_wire9; wire [0:0] sub_wire10; wire [4:0] sub_wire11; wire [7:0] sub_wire12; wire [0:0] rx_disperr = sub_wire0[0:0]; wire [0:0] rx_rlv = sub_wire1[0:0]; wire [0:0] rx_patterndetect = sub_wire2[0:0]; wire [0:0] rx_ctrldetect = sub_wire3[0:0]; wire [0:0] rx_errdetect = sub_wire4[0:0]; wire [0:0] rx_rmfifodatadeleted = sub_wire5[0:0]; wire [0:0] rx_runningdisp = sub_wire6[0:0]; wire [0:0] tx_dataout = sub_wire7[0:0]; wire [0:0] rx_rmfifodatainserted = sub_wire8[0:0]; wire [0:0] rx_syncstatus = sub_wire9[0:0]; wire [0:0] tx_clkout = sub_wire10[0:0]; wire [4:0] reconfig_fromgxb = sub_wire11[4:0]; wire [7:0] rx_dataout = sub_wire12[7:0]; altera_tse_altgx_civgx_gige_alt_c3gxb_vs07 altera_tse_altgx_civgx_gige_alt_c3gxb_vs07_component ( .pll_inclk (pll_inclk), .gxb_powerdown (gxb_powerdown), .tx_datain (tx_datain), .cal_blk_clk (cal_blk_clk), .reconfig_clk (reconfig_clk), .rx_datain (rx_datain), .reconfig_togxb (reconfig_togxb), .tx_ctrlenable (tx_ctrlenable), .rx_analogreset (rx_analogreset), .rx_digitalreset (rx_digitalreset), .tx_digitalreset (tx_digitalreset), .rx_disperr (sub_wire0), .rx_rlv (sub_wire1), .rx_patterndetect (sub_wire2), .rx_ctrldetect (sub_wire3), .rx_errdetect (sub_wire4), .rx_rmfifodatadeleted (sub_wire5), .rx_runningdisp (sub_wire6), .tx_dataout (sub_wire7), .rx_rmfifodatainserted (sub_wire8), .rx_syncstatus (sub_wire9), .tx_clkout (sub_wire10), .reconfig_fromgxb (sub_wire11), .rx_dataout (sub_wire12)); defparam altera_tse_altgx_civgx_gige_alt_c3gxb_vs07_component.starting_channel_number = starting_channel_number; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" // Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0" // Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC" // Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none" // Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0" // Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250" // Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0" // Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0" // Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0" // Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250" // Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0" // Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None" // Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0" // Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0" // Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250 Mbps" // Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false" // Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true" // Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true" // Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0" // Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false" // Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "" // Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" // Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6" // Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY" // Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb" // Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb" // Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1" // Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex" // Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "High" // Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1" // Retrieval info: CONSTANT: PROTOCOL STRING "gige" // Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0" // Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10" // Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false" // Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE" // Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v" // Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true" // Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32" // Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20" // Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5" // Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true" // Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2" // Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true" // Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false" // Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false" // Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false" // Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v" // Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High" // Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU" // Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium" // Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true" // Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1" // Retrieval info: CONSTANT: equalization_setting NUMERIC "1" // Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1" // Retrieval info: CONSTANT: number_of_quads NUMERIC "1" // Retrieval info: CONSTANT: pll_divide_by STRING "1" // Retrieval info: CONSTANT: pll_multiply_by STRING "5" // Retrieval info: CONSTANT: reconfig_calibration STRING "true" // Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5" // Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4" // Retrieval info: CONSTANT: rx_deskew_pattern STRING "0" // Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1" // Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1" // Retrieval info: CONSTANT: rx_use_external_termination STRING "false" // Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1" // Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: tx_use_external_termination STRING "false" // Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk" // Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]" // Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk" // Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk" // Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]" // Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]" // Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]" // Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]" // Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]" // Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]" // Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]" // Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]" // Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]" // Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]" // Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]" // Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]" // Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]" // Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]" // Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]" // Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]" // Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]" // Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]" // Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]" // Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]" // Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0 // Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0 // Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0 // Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0 // Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0 // Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0 // Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0 // Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0 // Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0 // Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0 // Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0 // Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 // Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0 // Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0 // Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0 // Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 // Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0 // Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0 // Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0 // Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0 // Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0 // Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0 // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: LIB_FILE: cycloneiv_hssi

// megafunction wizard: %ROM: 1-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: frac_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module frac_rom ( address, clock, q); input [3:0] address; input clock; output [7:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "qrom.hex" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "4" // Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "qrom.hex" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL "address[3..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" // Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.bsf TRUE FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_syn.v TRUE // Retrieval info: LIB_FILE: altera_mf

// UC Berkeley CS251 // Spring 2018 // Arya Reais-Parsi ([email protected]) `include "const.vh" module no_cache_mem #( parameter CPU_WIDTH = `CPU_INST_BITS, parameter WORD_ADDR_BITS = `CPU_ADDR_BITS-`ceilLog2(`CPU_INST_BITS/8) ) ( input clk, input reset, input cpu_req_val, output cpu_req_rdy, input [WORD_ADDR_BITS-1:0] cpu_req_addr, input [CPU_WIDTH-1:0] cpu_req_data, input [3:0] cpu_req_write, output reg cpu_resp_val, output reg [CPU_WIDTH-1:0] cpu_resp_data ); localparam DEPTH = 2*512*512; localparam WORDS = `MEM_DATA_BITS/CPU_WIDTH; reg [`MEM_DATA_BITS-1:0] ram [DEPTH-1:0]; wire [WORD_ADDR_BITS-`ceilLog2(WORDS)-1:0] upper_addr; assign upper_addr = cpu_req_addr[WORD_ADDR_BITS-1:`ceilLog2(WORDS)]; wire [`ceilLog2(WORDS)-1:0] lower_addr; assign lower_addr = cpu_req_addr[`ceilLog2(WORDS)-1:0]; wire [`MEM_DATA_BITS-1:0] read_data; assign read_data = (ram[upper_addr] >> CPU_WIDTH*lower_addr); assign cpu_req_rdy = 1'b1; wire [CPU_WIDTH-1:0] wmask; assign wmask = {{8{cpu_req_write[3]}},{8{cpu_req_write[2]}},{8{cpu_req_write[1]}},{8{cpu_req_write[0]}}}; wire [`MEM_DATA_BITS-1:0] write_data; assign write_data = (ram[upper_addr] & ~({{`MEM_DATA_BITS-CPU_WIDTH{1'b0}},wmask} << CPU_WIDTH*lower_addr)) | ((cpu_req_data & wmask) << CPU_WIDTH*lower_addr); always @(posedge clk) begin if (reset) cpu_resp_val <= 1'b0; else if (cpu_req_val && cpu_req_rdy) begin if (cpu_req_write) begin cpu_resp_val <= 1'b0; ram[upper_addr] <= write_data; end else begin cpu_resp_val <= 1'b1; cpu_resp_data <= read_data[CPU_WIDTH-1:0]; end end else cpu_resp_val <= 1'b0; end initial begin : zero integer i; for (i = 0; i < DEPTH; i = i + 1) ram[i] = 0; end endmodule

/***************************************************************************** * File : processing_system7_bfm_v2_0_5_unused_ports.v * * Date : 2012-11 * * Description : Semantic checks for unused ports. * *****************************************************************************/ /* CAN */ assign CAN0_PHY_TX = 0; assign CAN1_PHY_TX = 0; always @(CAN0_PHY_RX or CAN1_PHY_RX) begin if(CAN0_PHY_RX | CAN1_PHY_RX) $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* ETHERNET */ /* ------------------------------------------- */ assign ENET0_GMII_TX_EN = 0; assign ENET0_GMII_TX_ER = 0; assign ENET0_MDIO_MDC = 0; assign ENET0_MDIO_O = 0; /// confirm assign ENET0_MDIO_T = 0; assign ENET0_PTP_DELAY_REQ_RX = 0; assign ENET0_PTP_DELAY_REQ_TX = 0; assign ENET0_PTP_PDELAY_REQ_RX = 0; assign ENET0_PTP_PDELAY_REQ_TX = 0; assign ENET0_PTP_PDELAY_RESP_RX = 0; assign ENET0_PTP_PDELAY_RESP_TX = 0; assign ENET0_PTP_SYNC_FRAME_RX = 0; assign ENET0_PTP_SYNC_FRAME_TX = 0; assign ENET0_SOF_RX = 0; assign ENET0_SOF_TX = 0; assign ENET0_GMII_TXD = 0; always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD) begin if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER | ENET0_GMII_TX_CLK | ENET0_MDIO_I ) $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); end assign ENET1_GMII_TX_EN = 0; assign ENET1_GMII_TX_ER = 0; assign ENET1_MDIO_MDC = 0; assign ENET1_MDIO_O = 0;/// confirm assign ENET1_MDIO_T = 0; assign ENET1_PTP_DELAY_REQ_RX = 0; assign ENET1_PTP_DELAY_REQ_TX = 0; assign ENET1_PTP_PDELAY_REQ_RX = 0; assign ENET1_PTP_PDELAY_REQ_TX = 0; assign ENET1_PTP_PDELAY_RESP_RX = 0; assign ENET1_PTP_PDELAY_RESP_TX = 0; assign ENET1_PTP_SYNC_FRAME_RX = 0; assign ENET1_PTP_SYNC_FRAME_TX = 0; assign ENET1_SOF_RX = 0; assign ENET1_SOF_TX = 0; assign ENET1_GMII_TXD = 0; always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD) begin if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER | ENET1_GMII_TX_CLK | ENET1_MDIO_I ) $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* GPIO */ /* ------------------------------------------- */ assign GPIO_O = 0; assign GPIO_T = 0; always@(GPIO_I) begin if(GPIO_I !== 0) $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* I2C */ /* ------------------------------------------- */ assign I2C0_SDA_O = 0; assign I2C0_SDA_T = 0; assign I2C0_SCL_O = 0; assign I2C0_SCL_T = 0; assign I2C1_SDA_O = 0; assign I2C1_SDA_T = 0; assign I2C1_SCL_O = 0; assign I2C1_SCL_T = 0; always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I ) begin if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I) $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* JTAG */ /* ------------------------------------------- */ assign PJTAG_TD_T = 0; assign PJTAG_TD_O = 0; always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I) begin if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I) $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* SDIO */ /* ------------------------------------------- */ assign SDIO0_CLK = 0; assign SDIO0_CMD_O = 0; assign SDIO0_CMD_T = 0; assign SDIO0_DATA_O = 0; assign SDIO0_DATA_T = 0; assign SDIO0_LED = 0; assign SDIO0_BUSPOW = 0; assign SDIO0_BUSVOLT = 0; always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP ) begin if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP ) $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); end assign SDIO1_CLK = 0; assign SDIO1_CMD_O = 0; assign SDIO1_CMD_T = 0; assign SDIO1_DATA_O = 0; assign SDIO1_DATA_T = 0; assign SDIO1_LED = 0; assign SDIO1_BUSPOW = 0; assign SDIO1_BUSVOLT = 0; always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP ) begin if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP ) $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* SPI */ /* ------------------------------------------- */ assign SPI0_SCLK_O = 0; assign SPI0_SCLK_T = 0; assign SPI0_MOSI_O = 0; assign SPI0_MOSI_T = 0; assign SPI0_MISO_O = 0; assign SPI0_MISO_T = 0; assign SPI0_SS_O = 0; /// confirm assign SPI0_SS1_O = 0;/// confirm assign SPI0_SS2_O = 0;/// confirm assign SPI0_SS_T = 0; always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I) begin if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I) $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); end assign SPI1_SCLK_O = 0; assign SPI1_SCLK_T = 0; assign SPI1_MOSI_O = 0; assign SPI1_MOSI_T = 0; assign SPI1_MISO_O = 0; assign SPI1_MISO_T = 0; assign SPI1_SS_O = 0; assign SPI1_SS1_O = 0; assign SPI1_SS2_O = 0; assign SPI1_SS_T = 0; always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I) begin if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I) $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* UART */ /* ------------------------------------------- */ /// confirm assign UART0_DTRN = 0; assign UART0_RTSN = 0; assign UART0_TX = 0; always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX) begin if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX) $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); end assign UART1_DTRN = 0; assign UART1_RTSN = 0; assign UART1_TX = 0; always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX) begin if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX) $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* TTC */ /* ------------------------------------------- */ assign TTC0_WAVE0_OUT = 0; assign TTC0_WAVE1_OUT = 0; assign TTC0_WAVE2_OUT = 0; always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN) begin if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN) $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); end assign TTC1_WAVE0_OUT = 0; assign TTC1_WAVE1_OUT = 0; assign TTC1_WAVE2_OUT = 0; always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN) begin if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN) $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* WDT */ /* ------------------------------------------- */ assign WDT_RST_OUT = 0; always@(WDT_CLK_IN) begin if(WDT_CLK_IN) $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* TRACE */ /* ------------------------------------------- */ assign TRACE_CTL = 0; assign TRACE_DATA = 0; always@(TRACE_CLK) begin if(TRACE_CLK) $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* USB */ /* ------------------------------------------- */ assign USB0_PORT_INDCTL = 0; assign USB0_VBUS_PWRSELECT = 0; always@(USB0_VBUS_PWRFAULT) begin if(USB0_VBUS_PWRFAULT) $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); end assign USB1_PORT_INDCTL = 0; assign USB1_VBUS_PWRSELECT = 0; always@(USB1_VBUS_PWRFAULT) begin if(USB1_VBUS_PWRFAULT) $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); end always@(SRAM_INTIN) begin if(SRAM_INTIN) $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* DMA */ /* ------------------------------------------- */ assign DMA0_DATYPE = 0; assign DMA0_DAVALID = 0; assign DMA0_DRREADY = 0; assign DMA0_RSTN = 0; always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE) begin if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end assign DMA1_DATYPE = 0; assign DMA1_DAVALID = 0; assign DMA1_DRREADY = 0; assign DMA1_RSTN = 0; always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE) begin if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end assign DMA2_DATYPE = 0; assign DMA2_DAVALID = 0; assign DMA2_DRREADY = 0; assign DMA2_RSTN = 0; always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE) begin if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end assign DMA3_DATYPE = 0; assign DMA3_DAVALID = 0; assign DMA3_DRREADY = 0; assign DMA3_RSTN = 0; always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE) begin if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE) $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* FTM */ /* ------------------------------------------- */ assign FTMT_F2P_TRIGACK = 0; assign FTMT_P2F_TRIG = 0; assign FTMT_P2F_DEBUG = 0; always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK) begin if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK) $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* EVENT */ /* ------------------------------------------- */ assign EVENT_EVENTO = 0; assign EVENT_STANDBYWFE = 0; assign EVENT_STANDBYWFI = 0; always@(EVENT_EVENTI) begin if(EVENT_EVENTI) $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* MIO */ /* ------------------------------------------- */ always@(MIO) begin if(MIO !== 0) $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* FCLK_TRIG */ /* ------------------------------------------- */ always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N ) begin if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N ) $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* MISC */ /* ------------------------------------------- */ always@(FPGA_IDLE_N) begin if(FPGA_IDLE_N) $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR); end always@(DDR_ARB) begin if(DDR_ARB !== 0) $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR); end always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ ) begin if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* DDR */ /* ------------------------------------------- */ assign DDR_WEB = 0; always@(DDR_Clk or DDR_CS_n) begin if(!DDR_CS_n) $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR); end /* ------------------------------------------- */ /* IRQ_P2F */ /* ------------------------------------------- */ assign IRQ_P2F_DMAC_ABORT = 0; assign IRQ_P2F_DMAC0 = 0; assign IRQ_P2F_DMAC1 = 0; assign IRQ_P2F_DMAC2 = 0; assign IRQ_P2F_DMAC3 = 0; assign IRQ_P2F_DMAC4 = 0; assign IRQ_P2F_DMAC5 = 0; assign IRQ_P2F_DMAC6 = 0; assign IRQ_P2F_DMAC7 = 0; assign IRQ_P2F_SMC = 0; assign IRQ_P2F_QSPI = 0; assign IRQ_P2F_CTI = 0; assign IRQ_P2F_GPIO = 0; assign IRQ_P2F_USB0 = 0; assign IRQ_P2F_ENET0 = 0; assign IRQ_P2F_ENET_WAKE0 = 0; assign IRQ_P2F_SDIO0 = 0; assign IRQ_P2F_I2C0 = 0; assign IRQ_P2F_SPI0 = 0; assign IRQ_P2F_UART0 = 0; assign IRQ_P2F_CAN0 = 0; assign IRQ_P2F_USB1 = 0; assign IRQ_P2F_ENET1 = 0; assign IRQ_P2F_ENET_WAKE1 = 0; assign IRQ_P2F_SDIO1 = 0; assign IRQ_P2F_I2C1 = 0; assign IRQ_P2F_SPI1 = 0; assign IRQ_P2F_UART1 = 0; assign IRQ_P2F_CAN1 = 0;

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__SDFSTP_TB_V `define SKY130_FD_SC_HD__SDFSTP_TB_V /** * sdfstp: Scan delay flop, inverted set, non-inverted clock, * single output. * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__sdfstp.v" module top(); // Inputs are registered reg D; reg SCD; reg SCE; reg SET_B; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire Q; initial begin // Initial state is x for all inputs. D = 1'bX; SCD = 1'bX; SCE = 1'bX; SET_B = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 D = 1'b0; #40 SCD = 1'b0; #60 SCE = 1'b0; #80 SET_B = 1'b0; #100 VGND = 1'b0; #120 VNB = 1'b0; #140 VPB = 1'b0; #160 VPWR = 1'b0; #180 D = 1'b1; #200 SCD = 1'b1; #220 SCE = 1'b1; #240 SET_B = 1'b1; #260 VGND = 1'b1; #280 VNB = 1'b1; #300 VPB = 1'b1; #320 VPWR = 1'b1; #340 D = 1'b0; #360 SCD = 1'b0; #380 SCE = 1'b0; #400 SET_B = 1'b0; #420 VGND = 1'b0; #440 VNB = 1'b0; #460 VPB = 1'b0; #480 VPWR = 1'b0; #500 VPWR = 1'b1; #520 VPB = 1'b1; #540 VNB = 1'b1; #560 VGND = 1'b1; #580 SET_B = 1'b1; #600 SCE = 1'b1; #620 SCD = 1'b1; #640 D = 1'b1; #660 VPWR = 1'bx; #680 VPB = 1'bx; #700 VNB = 1'bx; #720 VGND = 1'bx; #740 SET_B = 1'bx; #760 SCE = 1'bx; #780 SCD = 1'bx; #800 D = 1'bx; end // Create a clock reg CLK; initial begin CLK = 1'b0; end always begin #5 CLK = ~CLK; end sky130_fd_sc_hd__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK)); endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__SDFSTP_TB_V

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; sub #(.IDX(0), .CHK(10)) i0; sub #(.IDX(2), .CHK(12)) i2; sub #(.IDX(7), .CHK(17)) i7; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (); function integer get_element; input integer index; input integer array_arg[7:0]; get_element = array_arg[index]; endfunction parameter integer IDX = 5; parameter integer CHK = 5; localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; localparam element1 = array[IDX]; localparam elementf = get_element(IDX, array); initial begin `checkh (element1, CHK); `checkh (elementf, CHK); end endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V `define SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V /** * clkbuf: Clock tree buffer. * * Verilog stub definition (black box without power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__clkbuf ( X, A ); output X; input A; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter [31:0] TWENTY4 = 24; parameter [31:0] PA = TWENTY4/8; parameter [1:0] VALUE = 2'b10; parameter [5:0] REPL = {PA{VALUE}}; parameter [7:0] CONC = {REPL,VALUE}; parameter DBITS = 32; parameter INIT_BYTE = 8'h1F; parameter DWORDS_LOG2 = 7; parameter DWORDS = (1<<DWORDS_LOG2); parameter DBYTES=DBITS/8; // verilator lint_off LITENDIAN reg [DBITS-1:0] mem [0:DWORDS-1]; // verilator lint_on LITENDIAN integer i; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if (REPL != {2'b10,2'b10,2'b10}) $stop; if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop; end if (cyc==2) begin for (i = 0; i < DWORDS; i = i + 1) mem[i] = {DBYTES{INIT_BYTE}}; end if (cyc==3) begin for (i = 0; i < DWORDS; i = i + 1) if (mem[i] != {DBYTES{INIT_BYTE}}) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule

//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: P.20131013 // \ \ Application: netgen // / / Filename: ApBrC.v // /___/ /\ Timestamp: Thu Mar 26 21:09:09 2015 // \ \ / \ // \___\/\___\ // // Command : -w -sim -ofmt verilog /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.ngc /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.v // Device : 3s500efg320-4 // Input file : /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.ngc // Output file : /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/ApBrC.v // # of Modules : 1 // Design Name : ApBrC // Xilinx : /mnt/data/Xilinx/14.7/ISE_DS/ISE/ // // Purpose: // This verilog netlist is a verification model and uses simulation // primitives which may not represent the true implementation of the // device, however the netlist is functionally correct and should not // be modified. This file cannot be synthesized and should only be used // with supported simulation tools. // // Reference: // Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ps module ApBrC ( clk, ce, p, a, b )/* synthesis syn_black_box syn_noprune=1 */; input clk; input ce; output [37 : 0] p; input [18 : 0] a; input [18 : 0] b; // synthesis translate_off wire \blk00000001/sig00000171 ; wire \blk00000001/sig00000170 ; wire \blk00000001/sig0000016f ; wire \blk00000001/sig0000016e ; wire \blk00000001/sig0000016d ; wire \blk00000001/sig0000016c ; wire \blk00000001/sig0000016b ; wire \blk00000001/sig0000016a ; wire \blk00000001/sig00000169 ; wire \blk00000001/sig00000168 ; wire \blk00000001/sig00000167 ; wire \blk00000001/sig00000166 ; wire \blk00000001/sig00000165 ; wire \blk00000001/sig00000164 ; wire \blk00000001/sig00000163 ; wire \blk00000001/sig00000162 ; wire \blk00000001/sig00000161 ; wire \blk00000001/sig00000160 ; wire \blk00000001/sig0000015f ; wire \blk00000001/sig0000015e ; wire \blk00000001/sig0000015d ; wire \blk00000001/sig0000015c ; wire \blk00000001/sig0000015b ; wire \blk00000001/sig0000015a ; wire \blk00000001/sig00000159 ; wire \blk00000001/sig00000158 ; wire \blk00000001/sig00000157 ; wire \blk00000001/sig00000156 ; wire \blk00000001/sig00000155 ; wire \blk00000001/sig00000154 ; wire \blk00000001/sig00000153 ; wire \blk00000001/sig00000152 ; wire \blk00000001/sig00000151 ; wire \blk00000001/sig00000150 ; wire \blk00000001/sig0000014f ; wire \blk00000001/sig0000014e ; wire \blk00000001/sig0000014d ; wire \blk00000001/sig0000014c ; wire \blk00000001/sig0000014b ; wire \blk00000001/sig0000014a ; wire \blk00000001/sig00000149 ; wire \blk00000001/sig00000148 ; wire \blk00000001/sig00000147 ; wire \blk00000001/sig00000146 ; wire \blk00000001/sig00000145 ; wire \blk00000001/sig00000144 ; wire \blk00000001/sig00000143 ; wire \blk00000001/sig00000142 ; wire \blk00000001/sig00000141 ; wire \blk00000001/sig00000140 ; wire \blk00000001/sig0000013f ; wire \blk00000001/sig0000013e ; wire \blk00000001/sig0000013d ; wire \blk00000001/sig0000013c ; wire \blk00000001/sig0000013b ; wire \blk00000001/sig0000013a ; wire \blk00000001/sig00000139 ; wire \blk00000001/sig00000138 ; wire \blk00000001/sig00000137 ; wire \blk00000001/sig00000136 ; wire \blk00000001/sig00000135 ; wire \blk00000001/sig00000134 ; wire \blk00000001/sig00000133 ; wire \blk00000001/sig00000132 ; wire \blk00000001/sig00000131 ; wire \blk00000001/sig00000130 ; wire \blk00000001/sig0000012f ; wire \blk00000001/sig0000012e ; wire \blk00000001/sig0000012d ; wire \blk00000001/sig0000012c ; wire \blk00000001/sig0000012b ; wire \blk00000001/sig0000012a ; wire \blk00000001/sig00000129 ; wire \blk00000001/sig00000128 ; wire \blk00000001/sig00000127 ; wire \blk00000001/sig00000126 ; wire \blk00000001/sig00000125 ; wire \blk00000001/sig00000124 ; wire \blk00000001/sig00000123 ; wire \blk00000001/sig00000122 ; wire \blk00000001/sig00000121 ; wire \blk00000001/sig00000120 ; wire \blk00000001/sig0000011f ; wire \blk00000001/sig0000011e ; wire \blk00000001/sig0000011d ; wire \blk00000001/sig0000011c ; wire \blk00000001/sig0000011b ; wire \blk00000001/sig0000011a ; wire \blk00000001/sig00000119 ; wire \blk00000001/sig00000118 ; wire \blk00000001/sig00000117 ; wire \blk00000001/sig00000116 ; wire \blk00000001/sig00000115 ; wire \blk00000001/sig00000114 ; wire \blk00000001/sig00000113 ; wire \blk00000001/sig00000112 ; wire \blk00000001/sig00000111 ; wire \blk00000001/sig00000110 ; wire \blk00000001/sig0000010f ; wire \blk00000001/sig0000010e ; wire \blk00000001/sig0000010d ; wire \blk00000001/sig0000010c ; wire \blk00000001/sig0000010b ; wire \blk00000001/sig0000010a ; wire \blk00000001/sig00000109 ; wire \blk00000001/sig00000108 ; wire \blk00000001/sig00000107 ; wire \blk00000001/sig00000106 ; wire \blk00000001/sig00000105 ; wire \blk00000001/sig00000104 ; wire \blk00000001/sig00000103 ; wire \blk00000001/sig00000102 ; wire \blk00000001/sig00000101 ; wire \blk00000001/sig00000100 ; wire \blk00000001/sig000000ff ; wire \blk00000001/sig000000fe ; wire \blk00000001/sig000000fd ; wire \blk00000001/sig000000fc ; wire \blk00000001/sig000000fb ; wire \blk00000001/sig000000fa ; wire \blk00000001/sig000000f9 ; wire \blk00000001/sig000000f8 ; wire \blk00000001/sig000000f7 ; wire \blk00000001/sig000000f6 ; wire \blk00000001/sig000000f5 ; wire \blk00000001/sig000000f4 ; wire \blk00000001/sig000000f3 ; wire \blk00000001/sig000000f2 ; wire \blk00000001/sig000000f1 ; wire \blk00000001/sig000000f0 ; wire \blk00000001/sig000000ef ; wire \blk00000001/sig000000ee ; wire \blk00000001/sig000000ed ; wire \blk00000001/sig000000ec ; wire \blk00000001/sig000000eb ; wire \blk00000001/sig000000ea ; wire \blk00000001/sig000000e9 ; wire \blk00000001/sig000000e8 ; wire \blk00000001/sig000000e7 ; wire \blk00000001/sig000000e6 ; wire \blk00000001/sig000000e5 ; wire \blk00000001/sig000000e4 ; wire \blk00000001/sig000000e3 ; wire \blk00000001/sig000000e2 ; wire \blk00000001/sig000000e1 ; wire \blk00000001/sig000000e0 ; wire \blk00000001/sig000000df ; wire \blk00000001/sig000000de ; wire \blk00000001/sig000000dd ; wire \blk00000001/sig000000dc ; wire \blk00000001/sig000000db ; wire \blk00000001/sig000000da ; wire \blk00000001/sig000000d9 ; wire \blk00000001/sig000000d8 ; wire \blk00000001/sig000000d7 ; wire \blk00000001/sig000000d6 ; wire \blk00000001/sig000000d5 ; wire \blk00000001/sig000000d4 ; wire \blk00000001/sig000000d3 ; wire \blk00000001/sig000000d2 ; wire \blk00000001/sig000000d1 ; wire \blk00000001/sig000000d0 ; wire \blk00000001/sig000000cf ; wire \blk00000001/sig000000ce ; wire \blk00000001/sig000000cd ; wire \blk00000001/sig000000cc ; wire \blk00000001/sig000000cb ; wire \blk00000001/sig000000ca ; wire \blk00000001/sig000000c9 ; wire \blk00000001/sig000000c8 ; wire \blk00000001/sig000000c7 ; wire \blk00000001/sig000000c6 ; wire \blk00000001/sig000000c5 ; wire \blk00000001/sig000000c4 ; wire \blk00000001/sig000000c3 ; wire \blk00000001/sig000000c2 ; wire \blk00000001/sig000000c1 ; wire \blk00000001/sig000000c0 ; wire \blk00000001/sig000000bf ; wire \blk00000001/sig000000be ; wire \blk00000001/sig000000bd ; wire \blk00000001/sig000000bc ; wire \blk00000001/sig000000bb ; wire \blk00000001/sig000000ba ; wire \blk00000001/sig000000b9 ; wire \blk00000001/sig000000b8 ; wire \blk00000001/sig000000b7 ; wire \blk00000001/sig000000b6 ; wire \blk00000001/sig000000b5 ; wire \blk00000001/sig000000b4 ; wire \blk00000001/sig000000b3 ; wire \blk00000001/sig000000b2 ; wire \blk00000001/sig000000b1 ; wire \blk00000001/sig000000b0 ; wire \blk00000001/sig000000af ; wire \blk00000001/sig000000ae ; wire \blk00000001/sig000000ad ; wire \blk00000001/sig000000ac ; wire \blk00000001/sig000000ab ; wire \blk00000001/sig000000aa ; wire \blk00000001/sig000000a9 ; wire \blk00000001/sig000000a8 ; wire \blk00000001/sig000000a7 ; wire \blk00000001/sig000000a6 ; wire \blk00000001/sig000000a5 ; wire \blk00000001/sig000000a4 ; wire \blk00000001/sig000000a3 ; wire \blk00000001/sig000000a2 ; wire \blk00000001/sig000000a1 ; wire \blk00000001/sig000000a0 ; wire \blk00000001/sig0000009f ; wire \blk00000001/sig0000009e ; wire \blk00000001/sig0000009d ; wire \blk00000001/sig0000009c ; wire \blk00000001/sig0000009b ; wire \blk00000001/sig0000009a ; wire \blk00000001/sig00000099 ; wire \blk00000001/sig00000098 ; wire \blk00000001/sig00000097 ; wire \blk00000001/sig00000096 ; wire \blk00000001/sig00000095 ; wire \blk00000001/sig00000094 ; wire \blk00000001/sig00000093 ; wire \blk00000001/sig00000092 ; wire \blk00000001/sig00000091 ; wire \blk00000001/sig00000090 ; wire \blk00000001/sig0000008f ; wire \blk00000001/sig0000008e ; wire \blk00000001/sig0000008d ; wire \blk00000001/sig0000008c ; wire \blk00000001/sig0000008b ; wire \blk00000001/sig0000008a ; wire \blk00000001/sig00000089 ; wire \blk00000001/sig00000088 ; wire \blk00000001/sig00000087 ; wire \blk00000001/sig00000086 ; wire \blk00000001/sig00000085 ; wire \blk00000001/sig00000084 ; wire \blk00000001/sig00000083 ; wire \blk00000001/sig00000082 ; wire \blk00000001/sig00000081 ; wire \blk00000001/sig00000080 ; wire \blk00000001/sig0000007f ; wire \blk00000001/sig0000007e ; wire \blk00000001/sig0000007d ; wire \blk00000001/sig0000007c ; wire \blk00000001/sig0000007b ; wire \blk00000001/sig0000007a ; wire \blk00000001/sig00000079 ; wire \blk00000001/sig00000078 ; wire \blk00000001/sig00000077 ; wire \blk00000001/sig00000076 ; wire \blk00000001/sig00000075 ; wire \blk00000001/sig00000074 ; wire \blk00000001/sig00000073 ; wire \blk00000001/sig00000072 ; wire \blk00000001/sig00000071 ; wire \blk00000001/sig00000070 ; wire \blk00000001/sig0000006f ; wire \blk00000001/sig0000006e ; wire \blk00000001/sig0000006d ; wire \blk00000001/sig0000006c ; wire \blk00000001/sig0000006b ; wire \blk00000001/sig0000006a ; wire \blk00000001/sig00000069 ; wire \blk00000001/sig00000068 ; wire \blk00000001/sig00000067 ; wire \blk00000001/sig00000066 ; wire \blk00000001/sig00000065 ; wire \blk00000001/sig00000064 ; wire \blk00000001/sig00000063 ; wire \blk00000001/sig00000062 ; wire \blk00000001/sig00000061 ; wire \blk00000001/sig00000060 ; wire \blk00000001/sig0000005f ; wire \blk00000001/sig0000005e ; wire \blk00000001/sig0000005d ; wire \blk00000001/sig0000005c ; wire \blk00000001/sig0000005b ; wire \blk00000001/sig0000005a ; wire \blk00000001/sig00000059 ; wire \blk00000001/sig00000058 ; wire \blk00000001/sig00000057 ; wire \blk00000001/sig00000056 ; wire \blk00000001/sig00000055 ; wire \blk00000001/sig00000054 ; wire \blk00000001/sig00000053 ; wire \blk00000001/sig00000052 ; wire \blk00000001/sig00000051 ; wire \blk00000001/sig00000050 ; wire \blk00000001/sig0000004f ; wire \blk00000001/sig0000004e ; wire \blk00000001/sig0000004d ; wire \blk00000001/sig0000004c ; wire \blk00000001/sig0000004b ; wire \blk00000001/sig0000004a ; wire \blk00000001/sig00000049 ; wire \blk00000001/sig00000048 ; wire \blk00000001/sig00000047 ; wire \blk00000001/sig00000046 ; wire \blk00000001/sig00000045 ; wire \blk00000001/sig00000044 ; wire \blk00000001/sig00000043 ; wire \blk00000001/sig00000042 ; wire \blk00000001/sig00000041 ; wire \blk00000001/sig00000040 ; wire \blk00000001/sig0000003f ; wire \blk00000001/sig0000003e ; wire \blk00000001/sig0000003d ; wire \blk00000001/sig0000003c ; wire \blk00000001/sig0000003b ; wire \blk00000001/sig0000003a ; wire \blk00000001/sig00000039 ; wire \blk00000001/sig00000038 ; wire \blk00000001/sig00000037 ; wire \blk00000001/sig00000036 ; wire \blk00000001/sig00000035 ; wire \blk00000001/sig00000034 ; wire \blk00000001/sig00000033 ; wire \blk00000001/sig00000032 ; wire \blk00000001/sig00000031 ; wire \blk00000001/sig00000030 ; wire \blk00000001/sig0000002f ; wire \blk00000001/sig0000002e ; wire \blk00000001/sig0000002d ; wire \blk00000001/sig0000002c ; wire \blk00000001/sig0000002b ; wire \blk00000001/sig0000002a ; wire \blk00000001/sig00000029 ; wire \NLW_blk00000001/blk00000006_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000006_BCOUT<0>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<21>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_P<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<17>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<16>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<15>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<14>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<13>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<12>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<11>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<10>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<9>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<8>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<7>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<6>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<5>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<4>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<3>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<2>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<1>_UNCONNECTED ; wire \NLW_blk00000001/blk00000003_BCOUT<0>_UNCONNECTED ; FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000127 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000095 ), .Q(\blk00000001/sig000000a6 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000126 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ed ), .Q(\blk00000001/sig00000095 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000125 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000096 ), .Q(\blk00000001/sig000000a7 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000124 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f7 ), .Q(\blk00000001/sig00000096 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000123 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009e ), .Q(\blk00000001/sig000000af ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000122 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f8 ), .Q(\blk00000001/sig0000009e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000121 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009f ), .Q(\blk00000001/sig000000b0 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000120 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f9 ), .Q(\blk00000001/sig0000009f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000011f ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a0 ), .Q(\blk00000001/sig000000b1 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000011e ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fa ), .Q(\blk00000001/sig000000a0 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000011d ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a1 ), .Q(\blk00000001/sig000000b2 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000011c ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fb ), .Q(\blk00000001/sig000000a1 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000011b ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a2 ), .Q(\blk00000001/sig000000b3 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000011a ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fc ), .Q(\blk00000001/sig000000a2 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000119 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a3 ), .Q(\blk00000001/sig000000b4 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000118 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fd ), .Q(\blk00000001/sig000000a3 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000117 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a4 ), .Q(\blk00000001/sig000000b5 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000116 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000fe ), .Q(\blk00000001/sig000000a4 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000115 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000a5 ), .Q(\blk00000001/sig000000b6 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000114 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ff ), .Q(\blk00000001/sig000000a5 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000113 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000097 ), .Q(\blk00000001/sig000000a8 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000112 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ee ), .Q(\blk00000001/sig00000097 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000111 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000098 ), .Q(\blk00000001/sig000000a9 ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000110 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ef ), .Q(\blk00000001/sig00000098 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000010f ( .C(clk), .CE(ce), .D(\blk00000001/sig00000099 ), .Q(\blk00000001/sig000000aa ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000010e ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f0 ), .Q(\blk00000001/sig00000099 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000010d ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009a ), .Q(\blk00000001/sig000000ab ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000010c ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f1 ), .Q(\blk00000001/sig0000009a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000010b ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009c ), .Q(\blk00000001/sig000000ad ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk0000010a ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f3 ), .Q(\blk00000001/sig0000009c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000109 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009d ), .Q(\blk00000001/sig000000ae ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000108 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f4 ), .Q(\blk00000001/sig0000009d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000107 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000009b ), .Q(\blk00000001/sig000000ac ) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000106 ( .A0(\blk00000001/sig0000003b ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000f2 ), .Q(\blk00000001/sig0000009b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000105 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000029 ), .Q(p[0]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000104 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000b7 ), .Q(\blk00000001/sig00000029 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000103 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002a ), .Q(p[1]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000102 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000c2 ), .Q(\blk00000001/sig0000002a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000101 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000032 ), .Q(p[2]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk00000100 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000cd ), .Q(\blk00000001/sig00000032 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ff ( .C(clk), .CE(ce), .D(\blk00000001/sig00000033 ), .Q(p[3]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000fe ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d3 ), .Q(\blk00000001/sig00000033 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000fd ( .C(clk), .CE(ce), .D(\blk00000001/sig00000034 ), .Q(p[4]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000fc ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d4 ), .Q(\blk00000001/sig00000034 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000fb ( .C(clk), .CE(ce), .D(\blk00000001/sig00000035 ), .Q(p[5]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000fa ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d5 ), .Q(\blk00000001/sig00000035 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000036 ), .Q(p[6]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f8 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d6 ), .Q(\blk00000001/sig00000036 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000037 ), .Q(p[7]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f6 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d7 ), .Q(\blk00000001/sig00000037 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f5 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000038 ), .Q(p[8]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f4 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d8 ), .Q(\blk00000001/sig00000038 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f3 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000039 ), .Q(p[9]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f2 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000d9 ), .Q(\blk00000001/sig00000039 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000f1 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002b ), .Q(p[10]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000f0 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000b8 ), .Q(\blk00000001/sig0000002b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ef ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002c ), .Q(p[11]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000ee ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000b9 ), .Q(\blk00000001/sig0000002c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ed ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002d ), .Q(p[12]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000ec ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000ba ), .Q(\blk00000001/sig0000002d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000eb ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002e ), .Q(p[13]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000ea ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000bb ), .Q(\blk00000001/sig0000002e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000030 ), .Q(p[15]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000e8 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000bd ), .Q(\blk00000001/sig00000030 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000031 ), .Q(p[16]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000e6 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000be ), .Q(\blk00000001/sig00000031 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e5 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000002f ), .Q(p[14]) ); SRL16E #( .INIT ( 16'h0000 )) \blk00000001/blk000000e4 ( .A0(\blk00000001/sig0000003a ), .A1(\blk00000001/sig0000003b ), .A2(\blk00000001/sig0000003b ), .A3(\blk00000001/sig0000003b ), .CE(ce), .CLK(clk), .D(\blk00000001/sig000000bc ), .Q(\blk00000001/sig0000002f ) ); VCC \blk00000001/blk000000e3 ( .P(\blk00000001/sig0000003a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e2 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000bf ), .Q(\blk00000001/sig00000104 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e1 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c0 ), .Q(\blk00000001/sig00000105 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000e0 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c1 ), .Q(\blk00000001/sig00000106 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000df ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c3 ), .Q(\blk00000001/sig00000107 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000de ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c4 ), .Q(\blk00000001/sig00000108 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000dd ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c5 ), .Q(\blk00000001/sig00000109 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000dc ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c6 ), .Q(\blk00000001/sig0000010a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000db ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c7 ), .Q(\blk00000001/sig0000010b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000da ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c8 ), .Q(\blk00000001/sig0000010c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d9 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000c9 ), .Q(\blk00000001/sig0000010d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d8 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ca ), .Q(\blk00000001/sig0000010e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d7 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000cb ), .Q(\blk00000001/sig0000010f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d6 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000cc ), .Q(\blk00000001/sig00000110 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d5 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ce ), .Q(\blk00000001/sig00000111 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d4 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000cf ), .Q(\blk00000001/sig00000112 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d3 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000d0 ), .Q(\blk00000001/sig00000113 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d2 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000d1 ), .Q(\blk00000001/sig00000114 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d1 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000d2 ), .Q(\blk00000001/sig00000115 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000d0 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000da ), .Q(\blk00000001/sig00000116 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cf ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e4 ), .Q(\blk00000001/sig00000117 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ce ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e5 ), .Q(\blk00000001/sig00000121 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cd ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e6 ), .Q(\blk00000001/sig00000122 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cc ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e7 ), .Q(\blk00000001/sig00000123 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000cb ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e8 ), .Q(\blk00000001/sig00000124 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ca ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e9 ), .Q(\blk00000001/sig00000125 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c9 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ea ), .Q(\blk00000001/sig00000126 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c8 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000eb ), .Q(\blk00000001/sig00000127 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c7 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000ec ), .Q(\blk00000001/sig00000128 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c6 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000db ), .Q(\blk00000001/sig00000118 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c5 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000dc ), .Q(\blk00000001/sig00000119 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c4 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000dd ), .Q(\blk00000001/sig0000011a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c3 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000de ), .Q(\blk00000001/sig0000011b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c2 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000df ), .Q(\blk00000001/sig0000011c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c1 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e0 ), .Q(\blk00000001/sig0000011d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000c0 ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e1 ), .Q(\blk00000001/sig0000011e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bf ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e2 ), .Q(\blk00000001/sig0000011f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000be ( .C(clk), .CE(ce), .D(\blk00000001/sig000000e3 ), .Q(\blk00000001/sig00000120 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bd ( .C(clk), .CE(ce), .D(\blk00000001/sig000000f5 ), .Q(\blk00000001/sig00000129 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bc ( .C(clk), .CE(ce), .D(\blk00000001/sig000000f6 ), .Q(\blk00000001/sig0000012a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000bb ( .C(clk), .CE(ce), .D(\blk00000001/sig00000100 ), .Q(\blk00000001/sig0000012b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ba ( .C(clk), .CE(ce), .D(\blk00000001/sig00000101 ), .Q(\blk00000001/sig0000012c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000102 ), .Q(\blk00000001/sig0000012d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b8 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000103 ), .Q(\blk00000001/sig0000012e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000155 ), .Q(\blk00000001/sig00000159 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b6 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000156 ), .Q(\blk00000001/sig0000015a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b5 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000157 ), .Q(\blk00000001/sig0000015b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b4 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000158 ), .Q(\blk00000001/sig0000015c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b3 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000012f ), .Q(\blk00000001/sig00000142 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b2 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000139 ), .Q(\blk00000001/sig00000143 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b1 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013a ), .Q(\blk00000001/sig0000014d ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000b0 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013b ), .Q(\blk00000001/sig0000014e ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000af ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013c ), .Q(\blk00000001/sig0000014f ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ae ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013d ), .Q(\blk00000001/sig00000150 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ad ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013e ), .Q(\blk00000001/sig00000151 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ac ( .C(clk), .CE(ce), .D(\blk00000001/sig0000013f ), .Q(\blk00000001/sig00000152 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000ab ( .C(clk), .CE(ce), .D(\blk00000001/sig00000140 ), .Q(\blk00000001/sig00000153 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000aa ( .C(clk), .CE(ce), .D(\blk00000001/sig00000141 ), .Q(\blk00000001/sig00000154 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a9 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000130 ), .Q(\blk00000001/sig00000144 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a8 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000131 ), .Q(\blk00000001/sig00000145 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a7 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000132 ), .Q(\blk00000001/sig00000146 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a6 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000133 ), .Q(\blk00000001/sig00000147 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a5 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000134 ), .Q(\blk00000001/sig00000148 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a4 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000135 ), .Q(\blk00000001/sig00000149 ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a3 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000136 ), .Q(\blk00000001/sig0000014a ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a2 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000137 ), .Q(\blk00000001/sig0000014b ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a1 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000138 ), .Q(\blk00000001/sig0000014c ) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk000000a0 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000015d ), .Q(p[17]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009f ( .C(clk), .CE(ce), .D(\blk00000001/sig00000168 ), .Q(p[18]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009e ( .C(clk), .CE(ce), .D(\blk00000001/sig00000169 ), .Q(p[19]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009d ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016a ), .Q(p[20]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009c ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016b ), .Q(p[21]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009b ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016d ), .Q(p[22]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000009a ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016e ), .Q(p[23]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000099 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016f ), .Q(p[24]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000098 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000170 ), .Q(p[25]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000097 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000171 ), .Q(p[26]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000096 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000015e ), .Q(p[27]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000095 ( .C(clk), .CE(ce), .D(\blk00000001/sig0000015f ), .Q(p[28]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000094 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000160 ), .Q(p[29]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000093 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000161 ), .Q(p[30]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000092 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000162 ), .Q(p[31]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000091 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000163 ), .Q(p[32]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk00000090 ( .C(clk), .CE(ce), .D(\blk00000001/sig00000164 ), .Q(p[33]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008f ( .C(clk), .CE(ce), .D(\blk00000001/sig00000165 ), .Q(p[34]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008e ( .C(clk), .CE(ce), .D(\blk00000001/sig00000166 ), .Q(p[35]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008d ( .C(clk), .CE(ce), .D(\blk00000001/sig00000167 ), .Q(p[36]) ); FDE #( .INIT ( 1'b0 )) \blk00000001/blk0000008c ( .C(clk), .CE(ce), .D(\blk00000001/sig0000016c ), .Q(p[37]) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000008b ( .I0(\blk00000001/sig00000129 ), .I1(\blk00000001/sig0000012b ), .O(\blk00000001/sig00000064 ) ); MUXCY \blk00000001/blk0000008a ( .CI(\blk00000001/sig0000003b ), .DI(\blk00000001/sig00000129 ), .S(\blk00000001/sig00000064 ), .O(\blk00000001/sig00000061 ) ); XORCY \blk00000001/blk00000089 ( .CI(\blk00000001/sig0000003b ), .LI(\blk00000001/sig00000064 ), .O(\blk00000001/sig00000155 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000088 ( .I0(\blk00000001/sig0000012a ), .I1(\blk00000001/sig0000012c ), .O(\blk00000001/sig00000065 ) ); MUXCY \blk00000001/blk00000087 ( .CI(\blk00000001/sig00000061 ), .DI(\blk00000001/sig0000012a ), .S(\blk00000001/sig00000065 ), .O(\blk00000001/sig00000062 ) ); XORCY \blk00000001/blk00000086 ( .CI(\blk00000001/sig00000061 ), .LI(\blk00000001/sig00000065 ), .O(\blk00000001/sig00000156 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000085 ( .I0(\blk00000001/sig0000012a ), .I1(\blk00000001/sig0000012d ), .O(\blk00000001/sig00000066 ) ); MUXCY \blk00000001/blk00000084 ( .CI(\blk00000001/sig00000062 ), .DI(\blk00000001/sig0000012a ), .S(\blk00000001/sig00000066 ), .O(\blk00000001/sig00000063 ) ); XORCY \blk00000001/blk00000083 ( .CI(\blk00000001/sig00000062 ), .LI(\blk00000001/sig00000066 ), .O(\blk00000001/sig00000157 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000082 ( .I0(\blk00000001/sig0000012a ), .I1(\blk00000001/sig0000012e ), .O(\blk00000001/sig00000067 ) ); XORCY \blk00000001/blk00000081 ( .CI(\blk00000001/sig00000063 ), .LI(\blk00000001/sig00000067 ), .O(\blk00000001/sig00000158 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000080 ( .I0(\blk00000001/sig00000104 ), .I1(\blk00000001/sig00000116 ), .O(\blk00000001/sig0000004e ) ); MUXCY \blk00000001/blk0000007f ( .CI(\blk00000001/sig0000003b ), .DI(\blk00000001/sig00000104 ), .S(\blk00000001/sig0000004e ), .O(\blk00000001/sig0000003c ) ); XORCY \blk00000001/blk0000007e ( .CI(\blk00000001/sig0000003b ), .LI(\blk00000001/sig0000004e ), .O(\blk00000001/sig0000012f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000007d ( .I0(\blk00000001/sig00000105 ), .I1(\blk00000001/sig00000117 ), .O(\blk00000001/sig00000058 ) ); MUXCY \blk00000001/blk0000007c ( .CI(\blk00000001/sig0000003c ), .DI(\blk00000001/sig00000105 ), .S(\blk00000001/sig00000058 ), .O(\blk00000001/sig00000045 ) ); XORCY \blk00000001/blk0000007b ( .CI(\blk00000001/sig0000003c ), .LI(\blk00000001/sig00000058 ), .O(\blk00000001/sig00000139 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000007a ( .I0(\blk00000001/sig00000106 ), .I1(\blk00000001/sig00000121 ), .O(\blk00000001/sig00000059 ) ); MUXCY \blk00000001/blk00000079 ( .CI(\blk00000001/sig00000045 ), .DI(\blk00000001/sig00000106 ), .S(\blk00000001/sig00000059 ), .O(\blk00000001/sig00000046 ) ); XORCY \blk00000001/blk00000078 ( .CI(\blk00000001/sig00000045 ), .LI(\blk00000001/sig00000059 ), .O(\blk00000001/sig0000013a ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000077 ( .I0(\blk00000001/sig00000107 ), .I1(\blk00000001/sig00000122 ), .O(\blk00000001/sig0000005a ) ); MUXCY \blk00000001/blk00000076 ( .CI(\blk00000001/sig00000046 ), .DI(\blk00000001/sig00000107 ), .S(\blk00000001/sig0000005a ), .O(\blk00000001/sig00000047 ) ); XORCY \blk00000001/blk00000075 ( .CI(\blk00000001/sig00000046 ), .LI(\blk00000001/sig0000005a ), .O(\blk00000001/sig0000013b ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000074 ( .I0(\blk00000001/sig00000108 ), .I1(\blk00000001/sig00000123 ), .O(\blk00000001/sig0000005b ) ); MUXCY \blk00000001/blk00000073 ( .CI(\blk00000001/sig00000047 ), .DI(\blk00000001/sig00000108 ), .S(\blk00000001/sig0000005b ), .O(\blk00000001/sig00000048 ) ); XORCY \blk00000001/blk00000072 ( .CI(\blk00000001/sig00000047 ), .LI(\blk00000001/sig0000005b ), .O(\blk00000001/sig0000013c ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000071 ( .I0(\blk00000001/sig00000109 ), .I1(\blk00000001/sig00000124 ), .O(\blk00000001/sig0000005c ) ); MUXCY \blk00000001/blk00000070 ( .CI(\blk00000001/sig00000048 ), .DI(\blk00000001/sig00000109 ), .S(\blk00000001/sig0000005c ), .O(\blk00000001/sig00000049 ) ); XORCY \blk00000001/blk0000006f ( .CI(\blk00000001/sig00000048 ), .LI(\blk00000001/sig0000005c ), .O(\blk00000001/sig0000013d ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000006e ( .I0(\blk00000001/sig0000010a ), .I1(\blk00000001/sig00000125 ), .O(\blk00000001/sig0000005d ) ); MUXCY \blk00000001/blk0000006d ( .CI(\blk00000001/sig00000049 ), .DI(\blk00000001/sig0000010a ), .S(\blk00000001/sig0000005d ), .O(\blk00000001/sig0000004a ) ); XORCY \blk00000001/blk0000006c ( .CI(\blk00000001/sig00000049 ), .LI(\blk00000001/sig0000005d ), .O(\blk00000001/sig0000013e ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000006b ( .I0(\blk00000001/sig0000010b ), .I1(\blk00000001/sig00000126 ), .O(\blk00000001/sig0000005e ) ); MUXCY \blk00000001/blk0000006a ( .CI(\blk00000001/sig0000004a ), .DI(\blk00000001/sig0000010b ), .S(\blk00000001/sig0000005e ), .O(\blk00000001/sig0000004b ) ); XORCY \blk00000001/blk00000069 ( .CI(\blk00000001/sig0000004a ), .LI(\blk00000001/sig0000005e ), .O(\blk00000001/sig0000013f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000068 ( .I0(\blk00000001/sig0000010c ), .I1(\blk00000001/sig00000127 ), .O(\blk00000001/sig0000005f ) ); MUXCY \blk00000001/blk00000067 ( .CI(\blk00000001/sig0000004b ), .DI(\blk00000001/sig0000010c ), .S(\blk00000001/sig0000005f ), .O(\blk00000001/sig0000004c ) ); XORCY \blk00000001/blk00000066 ( .CI(\blk00000001/sig0000004b ), .LI(\blk00000001/sig0000005f ), .O(\blk00000001/sig00000140 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000065 ( .I0(\blk00000001/sig0000010d ), .I1(\blk00000001/sig00000128 ), .O(\blk00000001/sig00000060 ) ); MUXCY \blk00000001/blk00000064 ( .CI(\blk00000001/sig0000004c ), .DI(\blk00000001/sig0000010d ), .S(\blk00000001/sig00000060 ), .O(\blk00000001/sig0000004d ) ); XORCY \blk00000001/blk00000063 ( .CI(\blk00000001/sig0000004c ), .LI(\blk00000001/sig00000060 ), .O(\blk00000001/sig00000141 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000062 ( .I0(\blk00000001/sig0000010e ), .I1(\blk00000001/sig00000118 ), .O(\blk00000001/sig0000004f ) ); MUXCY \blk00000001/blk00000061 ( .CI(\blk00000001/sig0000004d ), .DI(\blk00000001/sig0000010e ), .S(\blk00000001/sig0000004f ), .O(\blk00000001/sig0000003d ) ); XORCY \blk00000001/blk00000060 ( .CI(\blk00000001/sig0000004d ), .LI(\blk00000001/sig0000004f ), .O(\blk00000001/sig00000130 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000005f ( .I0(\blk00000001/sig0000010f ), .I1(\blk00000001/sig00000119 ), .O(\blk00000001/sig00000050 ) ); MUXCY \blk00000001/blk0000005e ( .CI(\blk00000001/sig0000003d ), .DI(\blk00000001/sig0000010f ), .S(\blk00000001/sig00000050 ), .O(\blk00000001/sig0000003e ) ); XORCY \blk00000001/blk0000005d ( .CI(\blk00000001/sig0000003d ), .LI(\blk00000001/sig00000050 ), .O(\blk00000001/sig00000131 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000005c ( .I0(\blk00000001/sig00000110 ), .I1(\blk00000001/sig0000011a ), .O(\blk00000001/sig00000051 ) ); MUXCY \blk00000001/blk0000005b ( .CI(\blk00000001/sig0000003e ), .DI(\blk00000001/sig00000110 ), .S(\blk00000001/sig00000051 ), .O(\blk00000001/sig0000003f ) ); XORCY \blk00000001/blk0000005a ( .CI(\blk00000001/sig0000003e ), .LI(\blk00000001/sig00000051 ), .O(\blk00000001/sig00000132 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000059 ( .I0(\blk00000001/sig00000111 ), .I1(\blk00000001/sig0000011b ), .O(\blk00000001/sig00000052 ) ); MUXCY \blk00000001/blk00000058 ( .CI(\blk00000001/sig0000003f ), .DI(\blk00000001/sig00000111 ), .S(\blk00000001/sig00000052 ), .O(\blk00000001/sig00000040 ) ); XORCY \blk00000001/blk00000057 ( .CI(\blk00000001/sig0000003f ), .LI(\blk00000001/sig00000052 ), .O(\blk00000001/sig00000133 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000056 ( .I0(\blk00000001/sig00000112 ), .I1(\blk00000001/sig0000011c ), .O(\blk00000001/sig00000053 ) ); MUXCY \blk00000001/blk00000055 ( .CI(\blk00000001/sig00000040 ), .DI(\blk00000001/sig00000112 ), .S(\blk00000001/sig00000053 ), .O(\blk00000001/sig00000041 ) ); XORCY \blk00000001/blk00000054 ( .CI(\blk00000001/sig00000040 ), .LI(\blk00000001/sig00000053 ), .O(\blk00000001/sig00000134 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000053 ( .I0(\blk00000001/sig00000113 ), .I1(\blk00000001/sig0000011d ), .O(\blk00000001/sig00000054 ) ); MUXCY \blk00000001/blk00000052 ( .CI(\blk00000001/sig00000041 ), .DI(\blk00000001/sig00000113 ), .S(\blk00000001/sig00000054 ), .O(\blk00000001/sig00000042 ) ); XORCY \blk00000001/blk00000051 ( .CI(\blk00000001/sig00000041 ), .LI(\blk00000001/sig00000054 ), .O(\blk00000001/sig00000135 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000050 ( .I0(\blk00000001/sig00000114 ), .I1(\blk00000001/sig0000011e ), .O(\blk00000001/sig00000055 ) ); MUXCY \blk00000001/blk0000004f ( .CI(\blk00000001/sig00000042 ), .DI(\blk00000001/sig00000114 ), .S(\blk00000001/sig00000055 ), .O(\blk00000001/sig00000043 ) ); XORCY \blk00000001/blk0000004e ( .CI(\blk00000001/sig00000042 ), .LI(\blk00000001/sig00000055 ), .O(\blk00000001/sig00000136 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000004d ( .I0(\blk00000001/sig00000115 ), .I1(\blk00000001/sig0000011f ), .O(\blk00000001/sig00000056 ) ); MUXCY \blk00000001/blk0000004c ( .CI(\blk00000001/sig00000043 ), .DI(\blk00000001/sig00000115 ), .S(\blk00000001/sig00000056 ), .O(\blk00000001/sig00000044 ) ); XORCY \blk00000001/blk0000004b ( .CI(\blk00000001/sig00000043 ), .LI(\blk00000001/sig00000056 ), .O(\blk00000001/sig00000137 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000004a ( .I0(\blk00000001/sig00000115 ), .I1(\blk00000001/sig00000120 ), .O(\blk00000001/sig00000057 ) ); XORCY \blk00000001/blk00000049 ( .CI(\blk00000001/sig00000044 ), .LI(\blk00000001/sig00000057 ), .O(\blk00000001/sig00000138 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000048 ( .I0(\blk00000001/sig00000142 ), .I1(\blk00000001/sig000000a6 ), .O(\blk00000001/sig0000007e ) ); MUXCY \blk00000001/blk00000047 ( .CI(\blk00000001/sig0000003b ), .DI(\blk00000001/sig00000142 ), .S(\blk00000001/sig0000007e ), .O(\blk00000001/sig00000068 ) ); XORCY \blk00000001/blk00000046 ( .CI(\blk00000001/sig0000003b ), .LI(\blk00000001/sig0000007e ), .O(\blk00000001/sig0000015d ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000045 ( .I0(\blk00000001/sig00000143 ), .I1(\blk00000001/sig000000a7 ), .O(\blk00000001/sig00000089 ) ); MUXCY \blk00000001/blk00000044 ( .CI(\blk00000001/sig00000068 ), .DI(\blk00000001/sig00000143 ), .S(\blk00000001/sig00000089 ), .O(\blk00000001/sig00000073 ) ); XORCY \blk00000001/blk00000043 ( .CI(\blk00000001/sig00000068 ), .LI(\blk00000001/sig00000089 ), .O(\blk00000001/sig00000168 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000042 ( .I0(\blk00000001/sig0000014d ), .I1(\blk00000001/sig000000af ), .O(\blk00000001/sig0000008d ) ); MUXCY \blk00000001/blk00000041 ( .CI(\blk00000001/sig00000073 ), .DI(\blk00000001/sig0000014d ), .S(\blk00000001/sig0000008d ), .O(\blk00000001/sig00000076 ) ); XORCY \blk00000001/blk00000040 ( .CI(\blk00000001/sig00000073 ), .LI(\blk00000001/sig0000008d ), .O(\blk00000001/sig00000169 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000003f ( .I0(\blk00000001/sig0000014e ), .I1(\blk00000001/sig000000b0 ), .O(\blk00000001/sig0000008e ) ); MUXCY \blk00000001/blk0000003e ( .CI(\blk00000001/sig00000076 ), .DI(\blk00000001/sig0000014e ), .S(\blk00000001/sig0000008e ), .O(\blk00000001/sig00000077 ) ); XORCY \blk00000001/blk0000003d ( .CI(\blk00000001/sig00000076 ), .LI(\blk00000001/sig0000008e ), .O(\blk00000001/sig0000016a ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000003c ( .I0(\blk00000001/sig0000014f ), .I1(\blk00000001/sig000000b1 ), .O(\blk00000001/sig0000008f ) ); MUXCY \blk00000001/blk0000003b ( .CI(\blk00000001/sig00000077 ), .DI(\blk00000001/sig0000014f ), .S(\blk00000001/sig0000008f ), .O(\blk00000001/sig00000078 ) ); XORCY \blk00000001/blk0000003a ( .CI(\blk00000001/sig00000077 ), .LI(\blk00000001/sig0000008f ), .O(\blk00000001/sig0000016b ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000039 ( .I0(\blk00000001/sig00000150 ), .I1(\blk00000001/sig000000b2 ), .O(\blk00000001/sig00000090 ) ); MUXCY \blk00000001/blk00000038 ( .CI(\blk00000001/sig00000078 ), .DI(\blk00000001/sig00000150 ), .S(\blk00000001/sig00000090 ), .O(\blk00000001/sig00000079 ) ); XORCY \blk00000001/blk00000037 ( .CI(\blk00000001/sig00000078 ), .LI(\blk00000001/sig00000090 ), .O(\blk00000001/sig0000016d ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000036 ( .I0(\blk00000001/sig00000151 ), .I1(\blk00000001/sig000000b3 ), .O(\blk00000001/sig00000091 ) ); MUXCY \blk00000001/blk00000035 ( .CI(\blk00000001/sig00000079 ), .DI(\blk00000001/sig00000151 ), .S(\blk00000001/sig00000091 ), .O(\blk00000001/sig0000007a ) ); XORCY \blk00000001/blk00000034 ( .CI(\blk00000001/sig00000079 ), .LI(\blk00000001/sig00000091 ), .O(\blk00000001/sig0000016e ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000033 ( .I0(\blk00000001/sig00000152 ), .I1(\blk00000001/sig000000b4 ), .O(\blk00000001/sig00000092 ) ); MUXCY \blk00000001/blk00000032 ( .CI(\blk00000001/sig0000007a ), .DI(\blk00000001/sig00000152 ), .S(\blk00000001/sig00000092 ), .O(\blk00000001/sig0000007b ) ); XORCY \blk00000001/blk00000031 ( .CI(\blk00000001/sig0000007a ), .LI(\blk00000001/sig00000092 ), .O(\blk00000001/sig0000016f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000030 ( .I0(\blk00000001/sig00000153 ), .I1(\blk00000001/sig000000b5 ), .O(\blk00000001/sig00000093 ) ); MUXCY \blk00000001/blk0000002f ( .CI(\blk00000001/sig0000007b ), .DI(\blk00000001/sig00000153 ), .S(\blk00000001/sig00000093 ), .O(\blk00000001/sig0000007c ) ); XORCY \blk00000001/blk0000002e ( .CI(\blk00000001/sig0000007b ), .LI(\blk00000001/sig00000093 ), .O(\blk00000001/sig00000170 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000002d ( .I0(\blk00000001/sig00000154 ), .I1(\blk00000001/sig000000b6 ), .O(\blk00000001/sig00000094 ) ); MUXCY \blk00000001/blk0000002c ( .CI(\blk00000001/sig0000007c ), .DI(\blk00000001/sig00000154 ), .S(\blk00000001/sig00000094 ), .O(\blk00000001/sig0000007d ) ); XORCY \blk00000001/blk0000002b ( .CI(\blk00000001/sig0000007c ), .LI(\blk00000001/sig00000094 ), .O(\blk00000001/sig00000171 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000002a ( .I0(\blk00000001/sig00000144 ), .I1(\blk00000001/sig000000a8 ), .O(\blk00000001/sig0000007f ) ); MUXCY \blk00000001/blk00000029 ( .CI(\blk00000001/sig0000007d ), .DI(\blk00000001/sig00000144 ), .S(\blk00000001/sig0000007f ), .O(\blk00000001/sig00000069 ) ); XORCY \blk00000001/blk00000028 ( .CI(\blk00000001/sig0000007d ), .LI(\blk00000001/sig0000007f ), .O(\blk00000001/sig0000015e ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000027 ( .I0(\blk00000001/sig00000145 ), .I1(\blk00000001/sig000000a9 ), .O(\blk00000001/sig00000080 ) ); MUXCY \blk00000001/blk00000026 ( .CI(\blk00000001/sig00000069 ), .DI(\blk00000001/sig00000145 ), .S(\blk00000001/sig00000080 ), .O(\blk00000001/sig0000006a ) ); XORCY \blk00000001/blk00000025 ( .CI(\blk00000001/sig00000069 ), .LI(\blk00000001/sig00000080 ), .O(\blk00000001/sig0000015f ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000024 ( .I0(\blk00000001/sig00000146 ), .I1(\blk00000001/sig000000aa ), .O(\blk00000001/sig00000081 ) ); MUXCY \blk00000001/blk00000023 ( .CI(\blk00000001/sig0000006a ), .DI(\blk00000001/sig00000146 ), .S(\blk00000001/sig00000081 ), .O(\blk00000001/sig0000006b ) ); XORCY \blk00000001/blk00000022 ( .CI(\blk00000001/sig0000006a ), .LI(\blk00000001/sig00000081 ), .O(\blk00000001/sig00000160 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000021 ( .I0(\blk00000001/sig00000147 ), .I1(\blk00000001/sig000000ab ), .O(\blk00000001/sig00000082 ) ); MUXCY \blk00000001/blk00000020 ( .CI(\blk00000001/sig0000006b ), .DI(\blk00000001/sig00000147 ), .S(\blk00000001/sig00000082 ), .O(\blk00000001/sig0000006c ) ); XORCY \blk00000001/blk0000001f ( .CI(\blk00000001/sig0000006b ), .LI(\blk00000001/sig00000082 ), .O(\blk00000001/sig00000161 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000001e ( .I0(\blk00000001/sig00000148 ), .I1(\blk00000001/sig000000ac ), .O(\blk00000001/sig00000083 ) ); MUXCY \blk00000001/blk0000001d ( .CI(\blk00000001/sig0000006c ), .DI(\blk00000001/sig00000148 ), .S(\blk00000001/sig00000083 ), .O(\blk00000001/sig0000006d ) ); XORCY \blk00000001/blk0000001c ( .CI(\blk00000001/sig0000006c ), .LI(\blk00000001/sig00000083 ), .O(\blk00000001/sig00000162 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000001b ( .I0(\blk00000001/sig00000149 ), .I1(\blk00000001/sig000000ad ), .O(\blk00000001/sig00000084 ) ); MUXCY \blk00000001/blk0000001a ( .CI(\blk00000001/sig0000006d ), .DI(\blk00000001/sig00000149 ), .S(\blk00000001/sig00000084 ), .O(\blk00000001/sig0000006e ) ); XORCY \blk00000001/blk00000019 ( .CI(\blk00000001/sig0000006d ), .LI(\blk00000001/sig00000084 ), .O(\blk00000001/sig00000163 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000018 ( .I0(\blk00000001/sig0000014a ), .I1(\blk00000001/sig000000ae ), .O(\blk00000001/sig00000085 ) ); MUXCY \blk00000001/blk00000017 ( .CI(\blk00000001/sig0000006e ), .DI(\blk00000001/sig0000014a ), .S(\blk00000001/sig00000085 ), .O(\blk00000001/sig0000006f ) ); XORCY \blk00000001/blk00000016 ( .CI(\blk00000001/sig0000006e ), .LI(\blk00000001/sig00000085 ), .O(\blk00000001/sig00000164 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000015 ( .I0(\blk00000001/sig0000014b ), .I1(\blk00000001/sig00000159 ), .O(\blk00000001/sig00000086 ) ); MUXCY \blk00000001/blk00000014 ( .CI(\blk00000001/sig0000006f ), .DI(\blk00000001/sig0000014b ), .S(\blk00000001/sig00000086 ), .O(\blk00000001/sig00000070 ) ); XORCY \blk00000001/blk00000013 ( .CI(\blk00000001/sig0000006f ), .LI(\blk00000001/sig00000086 ), .O(\blk00000001/sig00000165 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000012 ( .I0(\blk00000001/sig0000015a ), .I1(\blk00000001/sig0000014c ), .O(\blk00000001/sig00000087 ) ); MUXCY \blk00000001/blk00000011 ( .CI(\blk00000001/sig00000070 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig00000087 ), .O(\blk00000001/sig00000071 ) ); XORCY \blk00000001/blk00000010 ( .CI(\blk00000001/sig00000070 ), .LI(\blk00000001/sig00000087 ), .O(\blk00000001/sig00000166 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000000f ( .I0(\blk00000001/sig0000015b ), .I1(\blk00000001/sig0000014c ), .O(\blk00000001/sig00000088 ) ); MUXCY \blk00000001/blk0000000e ( .CI(\blk00000001/sig00000071 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig00000088 ), .O(\blk00000001/sig00000072 ) ); XORCY \blk00000001/blk0000000d ( .CI(\blk00000001/sig00000071 ), .LI(\blk00000001/sig00000088 ), .O(\blk00000001/sig00000167 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000000c ( .I0(\blk00000001/sig0000014c ), .I1(\blk00000001/sig0000015c ), .O(\blk00000001/sig0000008a ) ); MUXCY \blk00000001/blk0000000b ( .CI(\blk00000001/sig00000072 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig0000008a ), .O(\blk00000001/sig00000074 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk0000000a ( .I0(\blk00000001/sig0000014c ), .I1(\blk00000001/sig0000015c ), .O(\blk00000001/sig0000008b ) ); MUXCY \blk00000001/blk00000009 ( .CI(\blk00000001/sig00000074 ), .DI(\blk00000001/sig0000014c ), .S(\blk00000001/sig0000008b ), .O(\blk00000001/sig00000075 ) ); LUT2 #( .INIT ( 4'h6 )) \blk00000001/blk00000008 ( .I0(\blk00000001/sig0000014c ), .I1(\blk00000001/sig0000015c ), .O(\blk00000001/sig0000008c ) ); XORCY \blk00000001/blk00000007 ( .CI(\blk00000001/sig00000075 ), .LI(\blk00000001/sig0000008c ), .O(\blk00000001/sig0000016c ) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000006 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({\blk00000001/sig0000003b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({\blk00000001/sig0000003b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000006_P<35>_UNCONNECTED , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , \blk00000001/sig000000cf , \blk00000001/sig000000ce , \blk00000001/sig000000cc , \blk00000001/sig000000cb , \blk00000001/sig000000ca , \blk00000001/sig000000c9 , \blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , \blk00000001/sig000000c5 , \blk00000001/sig000000c4 , \blk00000001/sig000000c3 , \blk00000001/sig000000c1 , \blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc , \blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , \blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000cd , \blk00000001/sig000000c2 , \blk00000001/sig000000b7 }), .BCOUT({\NLW_blk00000001/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000006_BCOUT<0>_UNCONNECTED }) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000005 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({\blk00000001/sig0000003b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[17]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000005_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000ec , \blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 , \blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000da }), .BCOUT({\NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED }) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000004 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[17]}), .B({\blk00000001/sig0000003b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED , \blk00000001/sig000000f6 , \blk00000001/sig000000f5 , \blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig000000f2 , \blk00000001/sig000000f1 , \blk00000001/sig000000f0 , \blk00000001/sig000000ef , \blk00000001/sig000000ee , \blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd , \blk00000001/sig000000fc , \blk00000001/sig000000fb , \blk00000001/sig000000fa , \blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000ed }), .BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }) ); MULT18X18SIO #( .AREG ( 1 ), .BREG ( 1 ), .B_INPUT ( "DIRECT" ), .PREG ( 1 )) \blk00000001/blk00000003 ( .CEA(ce), .CEB(ce), .CEP(ce), .CLK(clk), .RSTA(\blk00000001/sig0000003b ), .RSTB(\blk00000001/sig0000003b ), .RSTP(\blk00000001/sig0000003b ), .A({a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[18], a[17]}), .B({b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[18], b[17]}), .BCIN({\blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b , \blk00000001/sig0000003b }), .P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<14>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<13>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<12>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<11>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<10>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<9>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<8>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<7>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<6>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<5>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<4>_UNCONNECTED , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 }), .BCOUT({\NLW_blk00000001/blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<12>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<6>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000003_BCOUT<0>_UNCONNECTED }) ); GND \blk00000001/blk00000002 ( .G(\blk00000001/sig0000003b ) ); // synthesis translate_on endmodule // synthesis translate_off `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif // synthesis translate_on

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_1_V `define SKY130_FD_SC_HD__DLYMETAL6S2S_1_V /** * dlymetal6s2s: 6-inverter delay with output from 2nd stage on * horizontal route. * * Verilog wrapper for dlymetal6s2s with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__dlymetal6s2s.v" `ifdef USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_hd__dlymetal6s2s_1 ( X , A , VPWR, VGND, VPB , VNB ); output X ; input A ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hd__dlymetal6s2s base ( .X(X), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*********************************************************/ `else // If not USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_hd__dlymetal6s2s_1 ( X, A ); output X; input A; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hd__dlymetal6s2s base ( .X(X), .A(A) ); endmodule `endcelldefine /*********************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_HD__DLYMETAL6S2S_1_V

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V `define SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V /** * sedfxtp: Scan delay flop, data enable, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v" `include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v" `celldefine module sky130_fd_sc_ms__sedfxtp ( Q , CLK , D , DE , SCD , SCE , VPWR, VGND, VPB , VNB ); // Module ports output Q ; input CLK ; input D ; input DE ; input SCD ; input SCE ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire buf_Q ; wire mux_out; wire de_d ; // Delay Name Output Other arguments sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE ); sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE ); sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND); buf buf0 (Q , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V

// // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // // // // // Ports: // Name I/O size props // m_near_mem_io_addr_base O 64 const // m_near_mem_io_addr_size O 64 const // m_near_mem_io_addr_lim O 64 const // m_plic_addr_base O 64 const // m_plic_addr_size O 64 const // m_plic_addr_lim O 64 const // m_uart0_addr_base O 64 const // m_uart0_addr_size O 64 const // m_uart0_addr_lim O 64 const // m_boot_rom_addr_base O 64 const // m_boot_rom_addr_size O 64 const // m_boot_rom_addr_lim O 64 const // m_mem0_controller_addr_base O 64 const // m_mem0_controller_addr_size O 64 const // m_mem0_controller_addr_lim O 64 const // m_tcm_addr_base O 64 const // m_tcm_addr_size O 64 const // m_tcm_addr_lim O 64 const // m_is_mem_addr O 1 // m_is_IO_addr O 1 // m_is_near_mem_IO_addr O 1 // m_pc_reset_value O 64 const // m_mtvec_reset_value O 64 const // m_nmivec_reset_value O 64 const // CLK I 1 unused // RST_N I 1 unused // m_is_mem_addr_addr I 64 // m_is_IO_addr_addr I 64 // m_is_near_mem_IO_addr_addr I 64 // // Combinational paths from inputs to outputs: // m_is_mem_addr_addr -> m_is_mem_addr // m_is_IO_addr_addr -> m_is_IO_addr // m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkSoC_Map(CLK, RST_N, m_near_mem_io_addr_base, m_near_mem_io_addr_size, m_near_mem_io_addr_lim, m_plic_addr_base, m_plic_addr_size, m_plic_addr_lim, m_uart0_addr_base, m_uart0_addr_size, m_uart0_addr_lim, m_boot_rom_addr_base, m_boot_rom_addr_size, m_boot_rom_addr_lim, m_mem0_controller_addr_base, m_mem0_controller_addr_size, m_mem0_controller_addr_lim, m_tcm_addr_base, m_tcm_addr_size, m_tcm_addr_lim, m_is_mem_addr_addr, m_is_mem_addr, m_is_IO_addr_addr, m_is_IO_addr, m_is_near_mem_IO_addr_addr, m_is_near_mem_IO_addr, m_pc_reset_value, m_mtvec_reset_value, m_nmivec_reset_value); input CLK; input RST_N; // value method m_near_mem_io_addr_base output [63 : 0] m_near_mem_io_addr_base; // value method m_near_mem_io_addr_size output [63 : 0] m_near_mem_io_addr_size; // value method m_near_mem_io_addr_lim output [63 : 0] m_near_mem_io_addr_lim; // value method m_plic_addr_base output [63 : 0] m_plic_addr_base; // value method m_plic_addr_size output [63 : 0] m_plic_addr_size; // value method m_plic_addr_lim output [63 : 0] m_plic_addr_lim; // value method m_uart0_addr_base output [63 : 0] m_uart0_addr_base; // value method m_uart0_addr_size output [63 : 0] m_uart0_addr_size; // value method m_uart0_addr_lim output [63 : 0] m_uart0_addr_lim; // value method m_boot_rom_addr_base output [63 : 0] m_boot_rom_addr_base; // value method m_boot_rom_addr_size output [63 : 0] m_boot_rom_addr_size; // value method m_boot_rom_addr_lim output [63 : 0] m_boot_rom_addr_lim; // value method m_mem0_controller_addr_base output [63 : 0] m_mem0_controller_addr_base; // value method m_mem0_controller_addr_size output [63 : 0] m_mem0_controller_addr_size; // value method m_mem0_controller_addr_lim output [63 : 0] m_mem0_controller_addr_lim; // value method m_tcm_addr_base output [63 : 0] m_tcm_addr_base; // value method m_tcm_addr_size output [63 : 0] m_tcm_addr_size; // value method m_tcm_addr_lim output [63 : 0] m_tcm_addr_lim; // value method m_is_mem_addr input [63 : 0] m_is_mem_addr_addr; output m_is_mem_addr; // value method m_is_IO_addr input [63 : 0] m_is_IO_addr_addr; output m_is_IO_addr; // value method m_is_near_mem_IO_addr input [63 : 0] m_is_near_mem_IO_addr_addr; output m_is_near_mem_IO_addr; // value method m_pc_reset_value output [63 : 0] m_pc_reset_value; // value method m_mtvec_reset_value output [63 : 0] m_mtvec_reset_value; // value method m_nmivec_reset_value output [63 : 0] m_nmivec_reset_value; // signals for module outputs wire [63 : 0] m_boot_rom_addr_base, m_boot_rom_addr_lim, m_boot_rom_addr_size, m_mem0_controller_addr_base, m_mem0_controller_addr_lim, m_mem0_controller_addr_size, m_mtvec_reset_value, m_near_mem_io_addr_base, m_near_mem_io_addr_lim, m_near_mem_io_addr_size, m_nmivec_reset_value, m_pc_reset_value, m_plic_addr_base, m_plic_addr_lim, m_plic_addr_size, m_tcm_addr_base, m_tcm_addr_lim, m_tcm_addr_size, m_uart0_addr_base, m_uart0_addr_lim, m_uart0_addr_size; wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; // value method m_near_mem_io_addr_base assign m_near_mem_io_addr_base = 64'h0000000002000000 ; // value method m_near_mem_io_addr_size assign m_near_mem_io_addr_size = 64'h000000000000C000 ; // value method m_near_mem_io_addr_lim assign m_near_mem_io_addr_lim = 64'd33603584 ; // value method m_plic_addr_base assign m_plic_addr_base = 64'h000000000C000000 ; // value method m_plic_addr_size assign m_plic_addr_size = 64'h0000000000400000 ; // value method m_plic_addr_lim assign m_plic_addr_lim = 64'd205520896 ; // value method m_uart0_addr_base assign m_uart0_addr_base = 64'h00000000C0000000 ; // value method m_uart0_addr_size assign m_uart0_addr_size = 64'h0000000000000080 ; // value method m_uart0_addr_lim assign m_uart0_addr_lim = 64'h00000000C0000080 ; // value method m_boot_rom_addr_base assign m_boot_rom_addr_base = 64'h0000000000001000 ; // value method m_boot_rom_addr_size assign m_boot_rom_addr_size = 64'h0000000000001000 ; // value method m_boot_rom_addr_lim assign m_boot_rom_addr_lim = 64'd8192 ; // value method m_mem0_controller_addr_base assign m_mem0_controller_addr_base = 64'h0000000080000000 ; // value method m_mem0_controller_addr_size assign m_mem0_controller_addr_size = 64'h0000000010000000 ; // value method m_mem0_controller_addr_lim assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; // value method m_tcm_addr_base assign m_tcm_addr_base = 64'h0 ; // value method m_tcm_addr_size assign m_tcm_addr_size = 64'd0 ; // value method m_tcm_addr_lim assign m_tcm_addr_lim = 64'd0 ; // value method m_is_mem_addr assign m_is_mem_addr = m_is_mem_addr_addr >= 64'h0000000000001000 && m_is_mem_addr_addr < 64'd8192 || m_is_mem_addr_addr >= 64'h0000000080000000 && m_is_mem_addr_addr < 64'h0000000090000000 ; // value method m_is_IO_addr assign m_is_IO_addr = m_is_IO_addr_addr >= 64'h0000000002000000 && m_is_IO_addr_addr < 64'd33603584 || m_is_IO_addr_addr >= 64'h000000000C000000 && m_is_IO_addr_addr < 64'd205520896 || m_is_IO_addr_addr >= 64'h00000000C0000000 && m_is_IO_addr_addr < 64'h00000000C0000080 ; // value method m_is_near_mem_IO_addr assign m_is_near_mem_IO_addr = m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && m_is_near_mem_IO_addr_addr < 64'd33603584 ; // value method m_pc_reset_value assign m_pc_reset_value = 64'h0000000000001000 ; // value method m_mtvec_reset_value assign m_mtvec_reset_value = 64'h0000000000001000 ; // value method m_nmivec_reset_value assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; endmodule // mkSoC_Map

//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module acl_fp_tan_s5 ( enable, clock, dataa, result); input enable; input clock; input [31:0] dataa; output [31:0] result; wire [31:0] sub_wire0; wire [31:0] result = sub_wire0[31:0]; fp_tan_s5 inst( .en (enable), .clk (clock), .a (dataa), .q (sub_wire0), .areset(1'b0)); endmodule

/*------------------------------------------------------------------------------ * This code was generated by Spiral Multiplier Block Generator, www.spiral.net * Copyright (c) 2006, Carnegie Mellon University * All rights reserved. * The code is distributed under a BSD style license * (see http://www.opensource.org/licenses/bsd-license.php) *------------------------------------------------------------------------------ */ /* ./multBlockGen.pl 8789 -fractionalBits 0*/ module multiplier_block ( i_data0, o_data0 ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; //Multipliers: wire [31:0] w1, w512, w513, w4, w517, w8272, w8789; assign w1 = i_data0; assign w4 = w1 << 2; assign w512 = w1 << 9; assign w513 = w1 + w512; assign w517 = w513 + w4; assign w8272 = w517 << 4; assign w8789 = w517 + w8272; assign o_data0 = w8789; //multiplier_block area estimate = 4979.62092201029; endmodule //multiplier_block module surround_with_regs( i_data0, o_data0, clk ); // Port mode declarations: input [31:0] i_data0; output [31:0] o_data0; reg [31:0] o_data0; input clk; reg [31:0] i_data0_reg; wire [30:0] o_data0_from_mult; always @(posedge clk) begin i_data0_reg <= i_data0; o_data0 <= o_data0_from_mult; end multiplier_block mult_blk( .i_data0(i_data0_reg), .o_data0(o_data0_from_mult) ); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v1_9_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // ** Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1 ) ( input rst, input clk, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; end end endfunction function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2*nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], DATA16_MAP[12*DQ_PER_DQS-1:0], DATA15_MAP[12*DQ_PER_DQS-1:0], DATA14_MAP[12*DQ_PER_DQS-1:0], DATA13_MAP[12*DQ_PER_DQS-1:0], DATA12_MAP[12*DQ_PER_DQS-1:0], DATA11_MAP[12*DQ_PER_DQS-1:0], DATA10_MAP[12*DQ_PER_DQS-1:0], DATA9_MAP[12*DQ_PER_DQS-1:0], DATA8_MAP[12*DQ_PER_DQS-1:0], DATA7_MAP[12*DQ_PER_DQS-1:0], DATA6_MAP[12*DQ_PER_DQS-1:0], DATA5_MAP[12*DQ_PER_DQS-1:0], DATA4_MAP[12*DQ_PER_DQS-1:0], DATA3_MAP[12*DQ_PER_DQS-1:0], DATA2_MAP[12*DQ_PER_DQS-1:0], DATA1_MAP[12*DQ_PER_DQS-1:0], DATA0_MAP[12*DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + 12*data_mask_in[(12*z+4)+:2] + data_mask_in[12*z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //*************************************************************************** // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //*************************************************************************** //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE"; //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK > 2500 ? "DIV2": "NONE"; localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? ((tCK > 2500) ? 8 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE*10-1:0] mem_dq_in; wire [HIGHEST_LANE*12-1:0] mem_dq_out; wire [HIGHEST_LANE*12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; (* keep = "true", max_fanout = 3 *) wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; //*************************************************************************** // Auxiliary output steering //*************************************************************************** // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //*************************************************************************** // Read data bit steering //*************************************************************************** // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTH*j + i] = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ 80*FULL_DATA_MAP[(12*i+4)+:2] + 8*FULL_DATA_MAP[12*i+:4]) + j]; end end endgenerate //*************************************************************************** // Control/address //*************************************************************************** assign out_cas_n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //***************************************************************** generate genvar m, n,x; //***************************************************************** // Control/address (multi-bit) buses //***************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + 12*ADDR_MAP[(12*m+4)+:2] + ADDR_MAP[12*m+:4]]; if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*ADDR_MAP[12*m+:4] + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + 12*BANK_MAP[(12*m+4)+:2] + BANK_MAP[12*m+:4]]; if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*BANK_MAP[12*m+:4] + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + 12*CS_MAP[(12*m+4)+:2] + CS_MAP[12*m+:4]]; if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*CS_MAP[12*m+:4] + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*(CS_MAP[12*m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + 12*ODT_MAP[(12*m+4)+:2] + ODT_MAP[12*m+:4]]; if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*ODT_MAP[12*m+:4] + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + 12*CKE_MAP[(12*m+4)+:2] + CKE_MAP[12*m+:4]]; if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*CKE_MAP[12*m+:4] + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end end end //***************************************************************** // Data mask //***************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; assign ts_dm[m] = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + 80*FULL_MASK_MAP[(12*m+4)+:2] + 8*FULL_MASK_MAP[12*m+:4] + n] = mux_wrdata_mask[DM_WIDTH*n + m]; end end end //***************************************************************** // Input and output DQ //***************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + 10*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; assign ts_dq[m] = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + 80*FULL_DATA_MAP[(12*m+4)+:2] + 8*FULL_DATA_MAP[12*m+:4] + n] = mux_wrdata[DQ_WIDTH*n + m]; end end //***************************************************************** // Input and output DQS //***************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; end endgenerate //*************************************************************************** // Memory I/F output and I/O buffer instantiation //*************************************************************************** // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); end end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v1_9_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v1_9_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v1_9_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //*************************************************************************** // Hard PHY instantiation //*************************************************************************** assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v1_9_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP) ,.PHY_1_IODELAY_GRP (IODELAY_GRP) ,.PHY_2_IODELAY_GRP (IODELAY_GRP) ,.BANK_TYPE (BANK_TYPE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__A41OI_1_V `define SKY130_FD_SC_MS__A41OI_1_V /** * a41oi: 4-input AND into first input of 2-input NOR. * * Y = !((A1 & A2 & A3 & A4) | B1) * * Verilog wrapper for a41oi with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_ms__a41oi.v" `ifdef USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_ms__a41oi_1 ( Y , A1 , A2 , A3 , A4 , B1 , VPWR, VGND, VPB , VNB ); output Y ; input A1 ; input A2 ; input A3 ; input A4 ; input B1 ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_ms__a41oi base ( .Y(Y), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*********************************************************/ `else // If not USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_ms__a41oi_1 ( Y , A1, A2, A3, A4, B1 ); output Y ; input A1; input A2; input A3; input A4; input B1; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_ms__a41oi base ( .Y(Y), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1) ); endmodule `endcelldefine /*********************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_MS__A41OI_1_V

`default_nettype none //Parallel Adder - non pipeline module mul4( input [3 : 0] iSOURCE0, input [3 : 0] iSOURCE1, output [7 : 0] oOUTPUT); assign oOUTPUT = ((iSOURCE0[0])? iSOURCE1 : 7'h00) + ((iSOURCE0[1])? iSOURCE1 << 1 : 7'h00) + ((iSOURCE0[2])? iSOURCE1 << 2 : 7'h00) + ((iSOURCE0[3])? iSOURCE1 << 3 : 7'h00); endmodule //Parallel Adder - non pipeline module mul32( input [31 : 0] iSOURCE0, input [31 : 0] iSOURCE1, output [63 : 0] oDATA, output oHSF, output oHOF, output oHCF, output oHPF, output oHZF, output oLSF, output oLOF, output oLCF, output oLPF, output oLZF); wire [63:0] w_tmp_out; assign w_tmp_out = ((iSOURCE0[0])? iSOURCE1 : 64'h00) + ((iSOURCE0[1])? iSOURCE1 << 1 : 64'h00) + ((iSOURCE0[2])? iSOURCE1 << 2 : 64'h00) + ((iSOURCE0[3])? iSOURCE1 << 3 : 64'h00) +((iSOURCE0[4])? iSOURCE1 << 4 : 64'h00) + ((iSOURCE0[5])? iSOURCE1 << 5 : 64'h00) + ((iSOURCE0[6])? iSOURCE1 << 6 : 64'h00) + ((iSOURCE0[7])? iSOURCE1 << 7 : 64'h00) +((iSOURCE0[8])? iSOURCE1 << 8 : 64'h00) + ((iSOURCE0[9])? iSOURCE1 << 9 : 64'h00) + ((iSOURCE0[10])? iSOURCE1 << 10 : 64'h00) + ((iSOURCE0[11])? iSOURCE1 << 11 : 64'h00) +((iSOURCE0[12])? iSOURCE1 << 12 : 64'h00) + ((iSOURCE0[13])? iSOURCE1 << 13 : 64'h00) + ((iSOURCE0[14])? iSOURCE1 << 14 : 64'h00) + ((iSOURCE0[15])? iSOURCE1 << 15 : 64'h00) +((iSOURCE0[16])? iSOURCE1 << 16 : 64'h00) + ((iSOURCE0[17])? iSOURCE1 << 17 : 64'h00) + ((iSOURCE0[18])? iSOURCE1 << 18 : 64'h00) + ((iSOURCE0[19])? iSOURCE1 << 19 : 64'h00) +((iSOURCE0[20])? iSOURCE1 << 20 : 64'h00) + ((iSOURCE0[21])? iSOURCE1 << 21 : 64'h00) + ((iSOURCE0[22])? iSOURCE1 << 22 : 64'h00) + ((iSOURCE0[23])? iSOURCE1 << 23 : 64'h00) +((iSOURCE0[24])? iSOURCE1 << 24 : 64'h00) + ((iSOURCE0[25])? iSOURCE1 << 25 : 64'h00) + ((iSOURCE0[26])? iSOURCE1 << 26 : 64'h00) + ((iSOURCE0[27])? iSOURCE1 << 27 : 64'h00) +((iSOURCE0[28])? iSOURCE1 << 28 : 64'h00) + ((iSOURCE0[29])? iSOURCE1 << 29 : 64'h00) + ((iSOURCE0[30])? iSOURCE1 << 30 : 64'h00) + ((iSOURCE0[31])? iSOURCE1 << 31 : 64'h00); /**************************************** Assign ****************************************/ assign oDATA = w_tmp_out; assign oHSF = w_tmp_out[31]; assign oHOF = w_tmp_out[32] ^ w_tmp_out[31]; assign oHCF = w_tmp_out[32]; assign oHPF = w_tmp_out[0]; assign oHZF = (w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0; assign oLSF = w_tmp_out[32]; assign oLOF = w_tmp_out[63]; assign oLCF = 1'b0; assign oLPF = w_tmp_out[32]; assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; endmodule `default_nettype wire

// CONFIG: // NUM_COEFF = 51 // PIPLINED = 0 module fir ( clk, reset, clk_ena, i_valid, i_in, o_valid, o_out ); // Data Width parameter dw = 18; //Data input/output bits // Number of filter coefficients parameter N = 51; parameter N_UNIQ = 26; // ciel(N/2) assuming symmetric filter coefficients //Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers localparam N_VALID_REGS = 52; input clk; input reset; input clk_ena; input i_valid; input [dw-1:0] i_in; // signed output o_valid; output [dw-1:0] o_out; // signed // Data Width dervied parameters localparam dw_add_int = 18; //Internal adder precision bits localparam dw_mult_int = 36; //Internal multiplier precision bits localparam scale_factor = 17; //Multiplier normalization shift amount // Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders localparam N_INPUT_REGS = 51; // Debug // initial begin // $display ("Data Width: %d", dw); // $display ("Data Width Add Internal: %d", dw_add_int); // $display ("Data Width Mult Internal: %d", dw_mult_int); // $display ("Scale Factor: %d", scale_factor); // end reg [dw-1:0] COEFFICIENT_0; reg [dw-1:0] COEFFICIENT_1; reg [dw-1:0] COEFFICIENT_2; reg [dw-1:0] COEFFICIENT_3; reg [dw-1:0] COEFFICIENT_4; reg [dw-1:0] COEFFICIENT_5; reg [dw-1:0] COEFFICIENT_6; reg [dw-1:0] COEFFICIENT_7; reg [dw-1:0] COEFFICIENT_8; reg [dw-1:0] COEFFICIENT_9; reg [dw-1:0] COEFFICIENT_10; reg [dw-1:0] COEFFICIENT_11; reg [dw-1:0] COEFFICIENT_12; reg [dw-1:0] COEFFICIENT_13; reg [dw-1:0] COEFFICIENT_14; reg [dw-1:0] COEFFICIENT_15; reg [dw-1:0] COEFFICIENT_16; reg [dw-1:0] COEFFICIENT_17; reg [dw-1:0] COEFFICIENT_18; reg [dw-1:0] COEFFICIENT_19; reg [dw-1:0] COEFFICIENT_20; reg [dw-1:0] COEFFICIENT_21; reg [dw-1:0] COEFFICIENT_22; reg [dw-1:0] COEFFICIENT_23; reg [dw-1:0] COEFFICIENT_24; reg [dw-1:0] COEFFICIENT_25; always@(posedge clk) begin COEFFICIENT_0 <= 18'd88; COEFFICIENT_1 <= 18'd0; COEFFICIENT_2 <= -18'd97; COEFFICIENT_3 <= -18'd197; COEFFICIENT_4 <= -18'd294; COEFFICIENT_5 <= -18'd380; COEFFICIENT_6 <= -18'd447; COEFFICIENT_7 <= -18'd490; COEFFICIENT_8 <= -18'd504; COEFFICIENT_9 <= -18'd481; COEFFICIENT_10 <= -18'd420; COEFFICIENT_11 <= -18'd319; COEFFICIENT_12 <= -18'd178; COEFFICIENT_13 <= 18'd0; COEFFICIENT_14 <= 18'd212; COEFFICIENT_15 <= 18'd451; COEFFICIENT_16 <= 18'd710; COEFFICIENT_17 <= 18'd980; COEFFICIENT_18 <= 18'd1252; COEFFICIENT_19 <= 18'd1514; COEFFICIENT_20 <= 18'd1756; COEFFICIENT_21 <= 18'd1971; COEFFICIENT_22 <= 18'd2147; COEFFICIENT_23 <= 18'd2278; COEFFICIENT_24 <= 18'd2360; COEFFICIENT_25 <= 18'd2387; end ////****************************************************** // * // * Valid Delay Pipeline // * // ***************************************************** //Input valid signal is pipelined to become output valid signal //Valid registers reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS; always@(posedge clk or posedge reset) begin if(reset) begin VALID_PIPELINE_REGS <= 0; end else begin if(clk_ena) begin VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid}; end else begin VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS; end end end ////****************************************************** // * // * Input Register Pipeline // * // ***************************************************** //Pipelined input values //Input value registers wire [dw-1:0] INPUT_PIPELINE_REG_0; wire [dw-1:0] INPUT_PIPELINE_REG_1; wire [dw-1:0] INPUT_PIPELINE_REG_2; wire [dw-1:0] INPUT_PIPELINE_REG_3; wire [dw-1:0] INPUT_PIPELINE_REG_4; wire [dw-1:0] INPUT_PIPELINE_REG_5; wire [dw-1:0] INPUT_PIPELINE_REG_6; wire [dw-1:0] INPUT_PIPELINE_REG_7; wire [dw-1:0] INPUT_PIPELINE_REG_8; wire [dw-1:0] INPUT_PIPELINE_REG_9; wire [dw-1:0] INPUT_PIPELINE_REG_10; wire [dw-1:0] INPUT_PIPELINE_REG_11; wire [dw-1:0] INPUT_PIPELINE_REG_12; wire [dw-1:0] INPUT_PIPELINE_REG_13; wire [dw-1:0] INPUT_PIPELINE_REG_14; wire [dw-1:0] INPUT_PIPELINE_REG_15; wire [dw-1:0] INPUT_PIPELINE_REG_16; wire [dw-1:0] INPUT_PIPELINE_REG_17; wire [dw-1:0] INPUT_PIPELINE_REG_18; wire [dw-1:0] INPUT_PIPELINE_REG_19; wire [dw-1:0] INPUT_PIPELINE_REG_20; wire [dw-1:0] INPUT_PIPELINE_REG_21; wire [dw-1:0] INPUT_PIPELINE_REG_22; wire [dw-1:0] INPUT_PIPELINE_REG_23; wire [dw-1:0] INPUT_PIPELINE_REG_24; wire [dw-1:0] INPUT_PIPELINE_REG_25; wire [dw-1:0] INPUT_PIPELINE_REG_26; wire [dw-1:0] INPUT_PIPELINE_REG_27; wire [dw-1:0] INPUT_PIPELINE_REG_28; wire [dw-1:0] INPUT_PIPELINE_REG_29; wire [dw-1:0] INPUT_PIPELINE_REG_30; wire [dw-1:0] INPUT_PIPELINE_REG_31; wire [dw-1:0] INPUT_PIPELINE_REG_32; wire [dw-1:0] INPUT_PIPELINE_REG_33; wire [dw-1:0] INPUT_PIPELINE_REG_34; wire [dw-1:0] INPUT_PIPELINE_REG_35; wire [dw-1:0] INPUT_PIPELINE_REG_36; wire [dw-1:0] INPUT_PIPELINE_REG_37; wire [dw-1:0] INPUT_PIPELINE_REG_38; wire [dw-1:0] INPUT_PIPELINE_REG_39; wire [dw-1:0] INPUT_PIPELINE_REG_40; wire [dw-1:0] INPUT_PIPELINE_REG_41; wire [dw-1:0] INPUT_PIPELINE_REG_42; wire [dw-1:0] INPUT_PIPELINE_REG_43; wire [dw-1:0] INPUT_PIPELINE_REG_44; wire [dw-1:0] INPUT_PIPELINE_REG_45; wire [dw-1:0] INPUT_PIPELINE_REG_46; wire [dw-1:0] INPUT_PIPELINE_REG_47; wire [dw-1:0] INPUT_PIPELINE_REG_48; wire [dw-1:0] INPUT_PIPELINE_REG_49; wire [dw-1:0] INPUT_PIPELINE_REG_50; input_pipeline in_pipe( .clk(clk), .clk_ena(clk_ena), .in_stream(i_in), .pipeline_reg_0(INPUT_PIPELINE_REG_0), .pipeline_reg_1(INPUT_PIPELINE_REG_1), .pipeline_reg_2(INPUT_PIPELINE_REG_2), .pipeline_reg_3(INPUT_PIPELINE_REG_3), .pipeline_reg_4(INPUT_PIPELINE_REG_4), .pipeline_reg_5(INPUT_PIPELINE_REG_5), .pipeline_reg_6(INPUT_PIPELINE_REG_6), .pipeline_reg_7(INPUT_PIPELINE_REG_7), .pipeline_reg_8(INPUT_PIPELINE_REG_8), .pipeline_reg_9(INPUT_PIPELINE_REG_9), .pipeline_reg_10(INPUT_PIPELINE_REG_10), .pipeline_reg_11(INPUT_PIPELINE_REG_11), .pipeline_reg_12(INPUT_PIPELINE_REG_12), .pipeline_reg_13(INPUT_PIPELINE_REG_13), .pipeline_reg_14(INPUT_PIPELINE_REG_14), .pipeline_reg_15(INPUT_PIPELINE_REG_15), .pipeline_reg_16(INPUT_PIPELINE_REG_16), .pipeline_reg_17(INPUT_PIPELINE_REG_17), .pipeline_reg_18(INPUT_PIPELINE_REG_18), .pipeline_reg_19(INPUT_PIPELINE_REG_19), .pipeline_reg_20(INPUT_PIPELINE_REG_20), .pipeline_reg_21(INPUT_PIPELINE_REG_21), .pipeline_reg_22(INPUT_PIPELINE_REG_22), .pipeline_reg_23(INPUT_PIPELINE_REG_23), .pipeline_reg_24(INPUT_PIPELINE_REG_24), .pipeline_reg_25(INPUT_PIPELINE_REG_25), .pipeline_reg_26(INPUT_PIPELINE_REG_26), .pipeline_reg_27(INPUT_PIPELINE_REG_27), .pipeline_reg_28(INPUT_PIPELINE_REG_28), .pipeline_reg_29(INPUT_PIPELINE_REG_29), .pipeline_reg_30(INPUT_PIPELINE_REG_30), .pipeline_reg_31(INPUT_PIPELINE_REG_31), .pipeline_reg_32(INPUT_PIPELINE_REG_32), .pipeline_reg_33(INPUT_PIPELINE_REG_33), .pipeline_reg_34(INPUT_PIPELINE_REG_34), .pipeline_reg_35(INPUT_PIPELINE_REG_35), .pipeline_reg_36(INPUT_PIPELINE_REG_36), .pipeline_reg_37(INPUT_PIPELINE_REG_37), .pipeline_reg_38(INPUT_PIPELINE_REG_38), .pipeline_reg_39(INPUT_PIPELINE_REG_39), .pipeline_reg_40(INPUT_PIPELINE_REG_40), .pipeline_reg_41(INPUT_PIPELINE_REG_41), .pipeline_reg_42(INPUT_PIPELINE_REG_42), .pipeline_reg_43(INPUT_PIPELINE_REG_43), .pipeline_reg_44(INPUT_PIPELINE_REG_44), .pipeline_reg_45(INPUT_PIPELINE_REG_45), .pipeline_reg_46(INPUT_PIPELINE_REG_46), .pipeline_reg_47(INPUT_PIPELINE_REG_47), .pipeline_reg_48(INPUT_PIPELINE_REG_48), .pipeline_reg_49(INPUT_PIPELINE_REG_49), .pipeline_reg_50(INPUT_PIPELINE_REG_50), .reset(reset) ); defparam in_pipe.WIDTH = 18; // = dw ////****************************************************** // * // * Computation Pipeline // * // ***************************************************** // ************************* LEVEL 0 ************************* \\ wire [dw-1:0] L0_output_wires_0; wire [dw-1:0] L0_output_wires_1; wire [dw-1:0] L0_output_wires_2; wire [dw-1:0] L0_output_wires_3; wire [dw-1:0] L0_output_wires_4; wire [dw-1:0] L0_output_wires_5; wire [dw-1:0] L0_output_wires_6; wire [dw-1:0] L0_output_wires_7; wire [dw-1:0] L0_output_wires_8; wire [dw-1:0] L0_output_wires_9; wire [dw-1:0] L0_output_wires_10; wire [dw-1:0] L0_output_wires_11; wire [dw-1:0] L0_output_wires_12; wire [dw-1:0] L0_output_wires_13; wire [dw-1:0] L0_output_wires_14; wire [dw-1:0] L0_output_wires_15; wire [dw-1:0] L0_output_wires_16; wire [dw-1:0] L0_output_wires_17; wire [dw-1:0] L0_output_wires_18; wire [dw-1:0] L0_output_wires_19; wire [dw-1:0] L0_output_wires_20; wire [dw-1:0] L0_output_wires_21; wire [dw-1:0] L0_output_wires_22; wire [dw-1:0] L0_output_wires_23; wire [dw-1:0] L0_output_wires_24; wire [dw-1:0] L0_output_wires_25; adder_with_1_reg L0_adder_0and50( .dataa (INPUT_PIPELINE_REG_0), .datab (INPUT_PIPELINE_REG_50), .result(L0_output_wires_0) ); adder_with_1_reg L0_adder_1and49( .dataa (INPUT_PIPELINE_REG_1), .datab (INPUT_PIPELINE_REG_49), .result(L0_output_wires_1) ); adder_with_1_reg L0_adder_2and48( .dataa (INPUT_PIPELINE_REG_2), .datab (INPUT_PIPELINE_REG_48), .result(L0_output_wires_2) ); adder_with_1_reg L0_adder_3and47( .dataa (INPUT_PIPELINE_REG_3), .datab (INPUT_PIPELINE_REG_47), .result(L0_output_wires_3) ); adder_with_1_reg L0_adder_4and46( .dataa (INPUT_PIPELINE_REG_4), .datab (INPUT_PIPELINE_REG_46), .result(L0_output_wires_4) ); adder_with_1_reg L0_adder_5and45( .dataa (INPUT_PIPELINE_REG_5), .datab (INPUT_PIPELINE_REG_45), .result(L0_output_wires_5) ); adder_with_1_reg L0_adder_6and44( .dataa (INPUT_PIPELINE_REG_6), .datab (INPUT_PIPELINE_REG_44), .result(L0_output_wires_6) ); adder_with_1_reg L0_adder_7and43( .dataa (INPUT_PIPELINE_REG_7), .datab (INPUT_PIPELINE_REG_43), .result(L0_output_wires_7) ); adder_with_1_reg L0_adder_8and42( .dataa (INPUT_PIPELINE_REG_8), .datab (INPUT_PIPELINE_REG_42), .result(L0_output_wires_8) ); adder_with_1_reg L0_adder_9and41( .dataa (INPUT_PIPELINE_REG_9), .datab (INPUT_PIPELINE_REG_41), .result(L0_output_wires_9) ); adder_with_1_reg L0_adder_10and40( .dataa (INPUT_PIPELINE_REG_10), .datab (INPUT_PIPELINE_REG_40), .result(L0_output_wires_10) ); adder_with_1_reg L0_adder_11and39( .dataa (INPUT_PIPELINE_REG_11), .datab (INPUT_PIPELINE_REG_39), .result(L0_output_wires_11) ); adder_with_1_reg L0_adder_12and38( .dataa (INPUT_PIPELINE_REG_12), .datab (INPUT_PIPELINE_REG_38), .result(L0_output_wires_12) ); adder_with_1_reg L0_adder_13and37( .dataa (INPUT_PIPELINE_REG_13), .datab (INPUT_PIPELINE_REG_37), .result(L0_output_wires_13) ); adder_with_1_reg L0_adder_14and36( .dataa (INPUT_PIPELINE_REG_14), .datab (INPUT_PIPELINE_REG_36), .result(L0_output_wires_14) ); adder_with_1_reg L0_adder_15and35( .dataa (INPUT_PIPELINE_REG_15), .datab (INPUT_PIPELINE_REG_35), .result(L0_output_wires_15) ); adder_with_1_reg L0_adder_16and34( .dataa (INPUT_PIPELINE_REG_16), .datab (INPUT_PIPELINE_REG_34), .result(L0_output_wires_16) ); adder_with_1_reg L0_adder_17and33( .dataa (INPUT_PIPELINE_REG_17), .datab (INPUT_PIPELINE_REG_33), .result(L0_output_wires_17) ); adder_with_1_reg L0_adder_18and32( .dataa (INPUT_PIPELINE_REG_18), .datab (INPUT_PIPELINE_REG_32), .result(L0_output_wires_18) ); adder_with_1_reg L0_adder_19and31( .dataa (INPUT_PIPELINE_REG_19), .datab (INPUT_PIPELINE_REG_31), .result(L0_output_wires_19) ); adder_with_1_reg L0_adder_20and30( .dataa (INPUT_PIPELINE_REG_20), .datab (INPUT_PIPELINE_REG_30), .result(L0_output_wires_20) ); adder_with_1_reg L0_adder_21and29( .dataa (INPUT_PIPELINE_REG_21), .datab (INPUT_PIPELINE_REG_29), .result(L0_output_wires_21) ); adder_with_1_reg L0_adder_22and28( .dataa (INPUT_PIPELINE_REG_22), .datab (INPUT_PIPELINE_REG_28), .result(L0_output_wires_22) ); adder_with_1_reg L0_adder_23and27( .dataa (INPUT_PIPELINE_REG_23), .datab (INPUT_PIPELINE_REG_27), .result(L0_output_wires_23) ); adder_with_1_reg L0_adder_24and26( .dataa (INPUT_PIPELINE_REG_24), .datab (INPUT_PIPELINE_REG_26), .result(L0_output_wires_24) ); // (25 main tree Adders) // ********* Byes ******** \\ one_register L0_byereg_for_25( .dataa (INPUT_PIPELINE_REG_25), .result(L0_output_wires_25) ); // (1 byes) // ************************* LEVEL 1 ************************* \\ // **************** Multipliers **************** \\ wire [dw-1:0] L1_mult_wires_0; wire [dw-1:0] L1_mult_wires_1; wire [dw-1:0] L1_mult_wires_2; wire [dw-1:0] L1_mult_wires_3; wire [dw-1:0] L1_mult_wires_4; wire [dw-1:0] L1_mult_wires_5; wire [dw-1:0] L1_mult_wires_6; wire [dw-1:0] L1_mult_wires_7; wire [dw-1:0] L1_mult_wires_8; wire [dw-1:0] L1_mult_wires_9; wire [dw-1:0] L1_mult_wires_10; wire [dw-1:0] L1_mult_wires_11; wire [dw-1:0] L1_mult_wires_12; wire [dw-1:0] L1_mult_wires_13; wire [dw-1:0] L1_mult_wires_14; wire [dw-1:0] L1_mult_wires_15; wire [dw-1:0] L1_mult_wires_16; wire [dw-1:0] L1_mult_wires_17; wire [dw-1:0] L1_mult_wires_18; wire [dw-1:0] L1_mult_wires_19; wire [dw-1:0] L1_mult_wires_20; wire [dw-1:0] L1_mult_wires_21; wire [dw-1:0] L1_mult_wires_22; wire [dw-1:0] L1_mult_wires_23; wire [dw-1:0] L1_mult_wires_24; wire [dw-1:0] L1_mult_wires_25; multiplier_with_reg L1_mul_0( .dataa (L0_output_wires_0), .datab (COEFFICIENT_0), .result(L1_mult_wires_0) ); multiplier_with_reg L1_mul_1( .dataa (L0_output_wires_1), .datab (COEFFICIENT_1), .result(L1_mult_wires_1) ); multiplier_with_reg L1_mul_2( .dataa (L0_output_wires_2), .datab (COEFFICIENT_2), .result(L1_mult_wires_2) ); multiplier_with_reg L1_mul_3( .dataa (L0_output_wires_3), .datab (COEFFICIENT_3), .result(L1_mult_wires_3) ); multiplier_with_reg L1_mul_4( .dataa (L0_output_wires_4), .datab (COEFFICIENT_4), .result(L1_mult_wires_4) ); multiplier_with_reg L1_mul_5( .dataa (L0_output_wires_5), .datab (COEFFICIENT_5), .result(L1_mult_wires_5) ); multiplier_with_reg L1_mul_6( .dataa (L0_output_wires_6), .datab (COEFFICIENT_6), .result(L1_mult_wires_6) ); multiplier_with_reg L1_mul_7( .dataa (L0_output_wires_7), .datab (COEFFICIENT_7), .result(L1_mult_wires_7) ); multiplier_with_reg L1_mul_8( .dataa (L0_output_wires_8), .datab (COEFFICIENT_8), .result(L1_mult_wires_8) ); multiplier_with_reg L1_mul_9( .dataa (L0_output_wires_9), .datab (COEFFICIENT_9), .result(L1_mult_wires_9) ); multiplier_with_reg L1_mul_10( .dataa (L0_output_wires_10), .datab (COEFFICIENT_10), .result(L1_mult_wires_10) ); multiplier_with_reg L1_mul_11( .dataa (L0_output_wires_11), .datab (COEFFICIENT_11), .result(L1_mult_wires_11) ); multiplier_with_reg L1_mul_12( .dataa (L0_output_wires_12), .datab (COEFFICIENT_12), .result(L1_mult_wires_12) ); multiplier_with_reg L1_mul_13( .dataa (L0_output_wires_13), .datab (COEFFICIENT_13), .result(L1_mult_wires_13) ); multiplier_with_reg L1_mul_14( .dataa (L0_output_wires_14), .datab (COEFFICIENT_14), .result(L1_mult_wires_14) ); multiplier_with_reg L1_mul_15( .dataa (L0_output_wires_15), .datab (COEFFICIENT_15), .result(L1_mult_wires_15) ); multiplier_with_reg L1_mul_16( .dataa (L0_output_wires_16), .datab (COEFFICIENT_16), .result(L1_mult_wires_16) ); multiplier_with_reg L1_mul_17( .dataa (L0_output_wires_17), .datab (COEFFICIENT_17), .result(L1_mult_wires_17) ); multiplier_with_reg L1_mul_18( .dataa (L0_output_wires_18), .datab (COEFFICIENT_18), .result(L1_mult_wires_18) ); multiplier_with_reg L1_mul_19( .dataa (L0_output_wires_19), .datab (COEFFICIENT_19), .result(L1_mult_wires_19) ); multiplier_with_reg L1_mul_20( .dataa (L0_output_wires_20), .datab (COEFFICIENT_20), .result(L1_mult_wires_20) ); multiplier_with_reg L1_mul_21( .dataa (L0_output_wires_21), .datab (COEFFICIENT_21), .result(L1_mult_wires_21) ); multiplier_with_reg L1_mul_22( .dataa (L0_output_wires_22), .datab (COEFFICIENT_22), .result(L1_mult_wires_22) ); multiplier_with_reg L1_mul_23( .dataa (L0_output_wires_23), .datab (COEFFICIENT_23), .result(L1_mult_wires_23) ); multiplier_with_reg L1_mul_24( .dataa (L0_output_wires_24), .datab (COEFFICIENT_24), .result(L1_mult_wires_24) ); multiplier_with_reg L1_mul_25( .dataa (L0_output_wires_25), .datab (COEFFICIENT_25), .result(L1_mult_wires_25) ); // (26 Multipliers) // **************** Adders **************** \\ wire [dw-1:0] L1_output_wires_0; wire [dw-1:0] L1_output_wires_1; wire [dw-1:0] L1_output_wires_2; wire [dw-1:0] L1_output_wires_3; wire [dw-1:0] L1_output_wires_4; wire [dw-1:0] L1_output_wires_5; wire [dw-1:0] L1_output_wires_6; wire [dw-1:0] L1_output_wires_7; wire [dw-1:0] L1_output_wires_8; wire [dw-1:0] L1_output_wires_9; wire [dw-1:0] L1_output_wires_10; wire [dw-1:0] L1_output_wires_11; wire [dw-1:0] L1_output_wires_12; adder_with_1_reg L1_adder_0and1( .dataa (L1_mult_wires_0), .datab (L1_mult_wires_1), .result(L1_output_wires_0) ); adder_with_1_reg L1_adder_2and3( .dataa (L1_mult_wires_2), .datab (L1_mult_wires_3), .result(L1_output_wires_1) ); adder_with_1_reg L1_adder_4and5( .dataa (L1_mult_wires_4), .datab (L1_mult_wires_5), .result(L1_output_wires_2) ); adder_with_1_reg L1_adder_6and7( .dataa (L1_mult_wires_6), .datab (L1_mult_wires_7), .result(L1_output_wires_3) ); adder_with_1_reg L1_adder_8and9( .dataa (L1_mult_wires_8), .datab (L1_mult_wires_9), .result(L1_output_wires_4) ); adder_with_1_reg L1_adder_10and11( .dataa (L1_mult_wires_10), .datab (L1_mult_wires_11), .result(L1_output_wires_5) ); adder_with_1_reg L1_adder_12and13( .dataa (L1_mult_wires_12), .datab (L1_mult_wires_13), .result(L1_output_wires_6) ); adder_with_1_reg L1_adder_14and15( .dataa (L1_mult_wires_14), .datab (L1_mult_wires_15), .result(L1_output_wires_7) ); adder_with_1_reg L1_adder_16and17( .dataa (L1_mult_wires_16), .datab (L1_mult_wires_17), .result(L1_output_wires_8) ); adder_with_1_reg L1_adder_18and19( .dataa (L1_mult_wires_18), .datab (L1_mult_wires_19), .result(L1_output_wires_9) ); adder_with_1_reg L1_adder_20and21( .dataa (L1_mult_wires_20), .datab (L1_mult_wires_21), .result(L1_output_wires_10) ); adder_with_1_reg L1_adder_22and23( .dataa (L1_mult_wires_22), .datab (L1_mult_wires_23), .result(L1_output_wires_11) ); adder_with_1_reg L1_adder_24and25( .dataa (L1_mult_wires_24), .datab (L1_mult_wires_25), .result(L1_output_wires_12) ); // (13 main tree Adders) // ************************* LEVEL 2 ************************* \\ wire [dw-1:0] L2_output_wires_0; wire [dw-1:0] L2_output_wires_1; wire [dw-1:0] L2_output_wires_2; wire [dw-1:0] L2_output_wires_3; wire [dw-1:0] L2_output_wires_4; wire [dw-1:0] L2_output_wires_5; wire [dw-1:0] L2_output_wires_6; adder_with_1_reg L2_adder_0and1( .dataa (L1_output_wires_0), .datab (L1_output_wires_1), .result(L2_output_wires_0) ); adder_with_1_reg L2_adder_2and3( .dataa (L1_output_wires_2), .datab (L1_output_wires_3), .result(L2_output_wires_1) ); adder_with_1_reg L2_adder_4and5( .dataa (L1_output_wires_4), .datab (L1_output_wires_5), .result(L2_output_wires_2) ); adder_with_1_reg L2_adder_6and7( .dataa (L1_output_wires_6), .datab (L1_output_wires_7), .result(L2_output_wires_3) ); adder_with_1_reg L2_adder_8and9( .dataa (L1_output_wires_8), .datab (L1_output_wires_9), .result(L2_output_wires_4) ); adder_with_1_reg L2_adder_10and11( .dataa (L1_output_wires_10), .datab (L1_output_wires_11), .result(L2_output_wires_5) ); // (6 main tree Adders) // ********* Byes ******** \\ one_register L2_byereg_for_12( .dataa (L1_output_wires_12), .result(L2_output_wires_6) ); // (1 byes) // ************************* LEVEL 3 ************************* \\ wire [dw-1:0] L3_output_wires_0; wire [dw-1:0] L3_output_wires_1; wire [dw-1:0] L3_output_wires_2; wire [dw-1:0] L3_output_wires_3; adder_with_1_reg L3_adder_0and1( .dataa (L2_output_wires_0), .datab (L2_output_wires_1), .result(L3_output_wires_0) ); adder_with_1_reg L3_adder_2and3( .dataa (L2_output_wires_2), .datab (L2_output_wires_3), .result(L3_output_wires_1) ); adder_with_1_reg L3_adder_4and5( .dataa (L2_output_wires_4), .datab (L2_output_wires_5), .result(L3_output_wires_2) ); // (3 main tree Adders) // ********* Byes ******** \\ one_register L3_byereg_for_6( .dataa (L2_output_wires_6), .result(L3_output_wires_3) ); // (1 byes) // ************************* LEVEL 4 ************************* \\ wire [dw-1:0] L4_output_wires_0; wire [dw-1:0] L4_output_wires_1; adder_with_1_reg L4_adder_0and1( .dataa (L3_output_wires_0), .datab (L3_output_wires_1), .result(L4_output_wires_0) ); adder_with_1_reg L4_adder_2and3( .dataa (L3_output_wires_2), .datab (L3_output_wires_3), .result(L4_output_wires_1) ); // (2 main tree Adders) // ************************* LEVEL 5 ************************* \\ wire [dw-1:0] L5_output_wires_0; adder_with_1_reg L5_adder_0and1( .dataa (L4_output_wires_0), .datab (L4_output_wires_1), .result(L5_output_wires_0) ); // (1 main tree Adders) ////****************************************************** // * // * Output Logic // * // ***************************************************** //Actual outputs reg [17:0] o_out; always @(posedge clk) begin if(clk_ena) begin o_out <= L5_output_wires_0; end end assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1]; endmodule module input_pipeline ( clk, clk_ena, in_stream, pipeline_reg_0, pipeline_reg_1, pipeline_reg_2, pipeline_reg_3, pipeline_reg_4, pipeline_reg_5, pipeline_reg_6, pipeline_reg_7, pipeline_reg_8, pipeline_reg_9, pipeline_reg_10, pipeline_reg_11, pipeline_reg_12, pipeline_reg_13, pipeline_reg_14, pipeline_reg_15, pipeline_reg_16, pipeline_reg_17, pipeline_reg_18, pipeline_reg_19, pipeline_reg_20, pipeline_reg_21, pipeline_reg_22, pipeline_reg_23, pipeline_reg_24, pipeline_reg_25, pipeline_reg_26, pipeline_reg_27, pipeline_reg_28, pipeline_reg_29, pipeline_reg_30, pipeline_reg_31, pipeline_reg_32, pipeline_reg_33, pipeline_reg_34, pipeline_reg_35, pipeline_reg_36, pipeline_reg_37, pipeline_reg_38, pipeline_reg_39, pipeline_reg_40, pipeline_reg_41, pipeline_reg_42, pipeline_reg_43, pipeline_reg_44, pipeline_reg_45, pipeline_reg_46, pipeline_reg_47, pipeline_reg_48, pipeline_reg_49, pipeline_reg_50, reset); parameter WIDTH = 1; //Input value registers input clk; input clk_ena; input [WIDTH-1:0] in_stream; output [WIDTH-1:0] pipeline_reg_0; output [WIDTH-1:0] pipeline_reg_1; output [WIDTH-1:0] pipeline_reg_2; output [WIDTH-1:0] pipeline_reg_3; output [WIDTH-1:0] pipeline_reg_4; output [WIDTH-1:0] pipeline_reg_5; output [WIDTH-1:0] pipeline_reg_6; output [WIDTH-1:0] pipeline_reg_7; output [WIDTH-1:0] pipeline_reg_8; output [WIDTH-1:0] pipeline_reg_9; output [WIDTH-1:0] pipeline_reg_10; output [WIDTH-1:0] pipeline_reg_11; output [WIDTH-1:0] pipeline_reg_12; output [WIDTH-1:0] pipeline_reg_13; output [WIDTH-1:0] pipeline_reg_14; output [WIDTH-1:0] pipeline_reg_15; output [WIDTH-1:0] pipeline_reg_16; output [WIDTH-1:0] pipeline_reg_17; output [WIDTH-1:0] pipeline_reg_18; output [WIDTH-1:0] pipeline_reg_19; output [WIDTH-1:0] pipeline_reg_20; output [WIDTH-1:0] pipeline_reg_21; output [WIDTH-1:0] pipeline_reg_22; output [WIDTH-1:0] pipeline_reg_23; output [WIDTH-1:0] pipeline_reg_24; output [WIDTH-1:0] pipeline_reg_25; output [WIDTH-1:0] pipeline_reg_26; output [WIDTH-1:0] pipeline_reg_27; output [WIDTH-1:0] pipeline_reg_28; output [WIDTH-1:0] pipeline_reg_29; output [WIDTH-1:0] pipeline_reg_30; output [WIDTH-1:0] pipeline_reg_31; output [WIDTH-1:0] pipeline_reg_32; output [WIDTH-1:0] pipeline_reg_33; output [WIDTH-1:0] pipeline_reg_34; output [WIDTH-1:0] pipeline_reg_35; output [WIDTH-1:0] pipeline_reg_36; output [WIDTH-1:0] pipeline_reg_37; output [WIDTH-1:0] pipeline_reg_38; output [WIDTH-1:0] pipeline_reg_39; output [WIDTH-1:0] pipeline_reg_40; output [WIDTH-1:0] pipeline_reg_41; output [WIDTH-1:0] pipeline_reg_42; output [WIDTH-1:0] pipeline_reg_43; output [WIDTH-1:0] pipeline_reg_44; output [WIDTH-1:0] pipeline_reg_45; output [WIDTH-1:0] pipeline_reg_46; output [WIDTH-1:0] pipeline_reg_47; output [WIDTH-1:0] pipeline_reg_48; output [WIDTH-1:0] pipeline_reg_49; output [WIDTH-1:0] pipeline_reg_50; reg [WIDTH-1:0] pipeline_reg_0; reg [WIDTH-1:0] pipeline_reg_1; reg [WIDTH-1:0] pipeline_reg_2; reg [WIDTH-1:0] pipeline_reg_3; reg [WIDTH-1:0] pipeline_reg_4; reg [WIDTH-1:0] pipeline_reg_5; reg [WIDTH-1:0] pipeline_reg_6; reg [WIDTH-1:0] pipeline_reg_7; reg [WIDTH-1:0] pipeline_reg_8; reg [WIDTH-1:0] pipeline_reg_9; reg [WIDTH-1:0] pipeline_reg_10; reg [WIDTH-1:0] pipeline_reg_11; reg [WIDTH-1:0] pipeline_reg_12; reg [WIDTH-1:0] pipeline_reg_13; reg [WIDTH-1:0] pipeline_reg_14; reg [WIDTH-1:0] pipeline_reg_15; reg [WIDTH-1:0] pipeline_reg_16; reg [WIDTH-1:0] pipeline_reg_17; reg [WIDTH-1:0] pipeline_reg_18; reg [WIDTH-1:0] pipeline_reg_19; reg [WIDTH-1:0] pipeline_reg_20; reg [WIDTH-1:0] pipeline_reg_21; reg [WIDTH-1:0] pipeline_reg_22; reg [WIDTH-1:0] pipeline_reg_23; reg [WIDTH-1:0] pipeline_reg_24; reg [WIDTH-1:0] pipeline_reg_25; reg [WIDTH-1:0] pipeline_reg_26; reg [WIDTH-1:0] pipeline_reg_27; reg [WIDTH-1:0] pipeline_reg_28; reg [WIDTH-1:0] pipeline_reg_29; reg [WIDTH-1:0] pipeline_reg_30; reg [WIDTH-1:0] pipeline_reg_31; reg [WIDTH-1:0] pipeline_reg_32; reg [WIDTH-1:0] pipeline_reg_33; reg [WIDTH-1:0] pipeline_reg_34; reg [WIDTH-1:0] pipeline_reg_35; reg [WIDTH-1:0] pipeline_reg_36; reg [WIDTH-1:0] pipeline_reg_37; reg [WIDTH-1:0] pipeline_reg_38; reg [WIDTH-1:0] pipeline_reg_39; reg [WIDTH-1:0] pipeline_reg_40; reg [WIDTH-1:0] pipeline_reg_41; reg [WIDTH-1:0] pipeline_reg_42; reg [WIDTH-1:0] pipeline_reg_43; reg [WIDTH-1:0] pipeline_reg_44; reg [WIDTH-1:0] pipeline_reg_45; reg [WIDTH-1:0] pipeline_reg_46; reg [WIDTH-1:0] pipeline_reg_47; reg [WIDTH-1:0] pipeline_reg_48; reg [WIDTH-1:0] pipeline_reg_49; reg [WIDTH-1:0] pipeline_reg_50; input reset; always@(posedge clk or posedge reset) begin if(reset) begin pipeline_reg_0 <= 0; pipeline_reg_1 <= 0; pipeline_reg_2 <= 0; pipeline_reg_3 <= 0; pipeline_reg_4 <= 0; pipeline_reg_5 <= 0; pipeline_reg_6 <= 0; pipeline_reg_7 <= 0; pipeline_reg_8 <= 0; pipeline_reg_9 <= 0; pipeline_reg_10 <= 0; pipeline_reg_11 <= 0; pipeline_reg_12 <= 0; pipeline_reg_13 <= 0; pipeline_reg_14 <= 0; pipeline_reg_15 <= 0; pipeline_reg_16 <= 0; pipeline_reg_17 <= 0; pipeline_reg_18 <= 0; pipeline_reg_19 <= 0; pipeline_reg_20 <= 0; pipeline_reg_21 <= 0; pipeline_reg_22 <= 0; pipeline_reg_23 <= 0; pipeline_reg_24 <= 0; pipeline_reg_25 <= 0; pipeline_reg_26 <= 0; pipeline_reg_27 <= 0; pipeline_reg_28 <= 0; pipeline_reg_29 <= 0; pipeline_reg_30 <= 0; pipeline_reg_31 <= 0; pipeline_reg_32 <= 0; pipeline_reg_33 <= 0; pipeline_reg_34 <= 0; pipeline_reg_35 <= 0; pipeline_reg_36 <= 0; pipeline_reg_37 <= 0; pipeline_reg_38 <= 0; pipeline_reg_39 <= 0; pipeline_reg_40 <= 0; pipeline_reg_41 <= 0; pipeline_reg_42 <= 0; pipeline_reg_43 <= 0; pipeline_reg_44 <= 0; pipeline_reg_45 <= 0; pipeline_reg_46 <= 0; pipeline_reg_47 <= 0; pipeline_reg_48 <= 0; pipeline_reg_49 <= 0; pipeline_reg_50 <= 0; end else begin if(clk_ena) begin pipeline_reg_0 <= in_stream; pipeline_reg_1 <= pipeline_reg_0; pipeline_reg_2 <= pipeline_reg_1; pipeline_reg_3 <= pipeline_reg_2; pipeline_reg_4 <= pipeline_reg_3; pipeline_reg_5 <= pipeline_reg_4; pipeline_reg_6 <= pipeline_reg_5; pipeline_reg_7 <= pipeline_reg_6; pipeline_reg_8 <= pipeline_reg_7; pipeline_reg_9 <= pipeline_reg_8; pipeline_reg_10 <= pipeline_reg_9; pipeline_reg_11 <= pipeline_reg_10; pipeline_reg_12 <= pipeline_reg_11; pipeline_reg_13 <= pipeline_reg_12; pipeline_reg_14 <= pipeline_reg_13; pipeline_reg_15 <= pipeline_reg_14; pipeline_reg_16 <= pipeline_reg_15; pipeline_reg_17 <= pipeline_reg_16; pipeline_reg_18 <= pipeline_reg_17; pipeline_reg_19 <= pipeline_reg_18; pipeline_reg_20 <= pipeline_reg_19; pipeline_reg_21 <= pipeline_reg_20; pipeline_reg_22 <= pipeline_reg_21; pipeline_reg_23 <= pipeline_reg_22; pipeline_reg_24 <= pipeline_reg_23; pipeline_reg_25 <= pipeline_reg_24; pipeline_reg_26 <= pipeline_reg_25; pipeline_reg_27 <= pipeline_reg_26; pipeline_reg_28 <= pipeline_reg_27; pipeline_reg_29 <= pipeline_reg_28; pipeline_reg_30 <= pipeline_reg_29; pipeline_reg_31 <= pipeline_reg_30; pipeline_reg_32 <= pipeline_reg_31; pipeline_reg_33 <= pipeline_reg_32; pipeline_reg_34 <= pipeline_reg_33; pipeline_reg_35 <= pipeline_reg_34; pipeline_reg_36 <= pipeline_reg_35; pipeline_reg_37 <= pipeline_reg_36; pipeline_reg_38 <= pipeline_reg_37; pipeline_reg_39 <= pipeline_reg_38; pipeline_reg_40 <= pipeline_reg_39; pipeline_reg_41 <= pipeline_reg_40; pipeline_reg_42 <= pipeline_reg_41; pipeline_reg_43 <= pipeline_reg_42; pipeline_reg_44 <= pipeline_reg_43; pipeline_reg_45 <= pipeline_reg_44; pipeline_reg_46 <= pipeline_reg_45; pipeline_reg_47 <= pipeline_reg_46; pipeline_reg_48 <= pipeline_reg_47; pipeline_reg_49 <= pipeline_reg_48; pipeline_reg_50 <= pipeline_reg_49; end //else begin //pipeline_reg_0 <= pipeline_reg_0; //pipeline_reg_1 <= pipeline_reg_1; //pipeline_reg_2 <= pipeline_reg_2; //pipeline_reg_3 <= pipeline_reg_3; //pipeline_reg_4 <= pipeline_reg_4; //pipeline_reg_5 <= pipeline_reg_5; //pipeline_reg_6 <= pipeline_reg_6; //pipeline_reg_7 <= pipeline_reg_7; //pipeline_reg_8 <= pipeline_reg_8; //pipeline_reg_9 <= pipeline_reg_9; //pipeline_reg_10 <= pipeline_reg_10; //pipeline_reg_11 <= pipeline_reg_11; //pipeline_reg_12 <= pipeline_reg_12; //pipeline_reg_13 <= pipeline_reg_13; //pipeline_reg_14 <= pipeline_reg_14; //pipeline_reg_15 <= pipeline_reg_15; //pipeline_reg_16 <= pipeline_reg_16; //pipeline_reg_17 <= pipeline_reg_17; //pipeline_reg_18 <= pipeline_reg_18; //pipeline_reg_19 <= pipeline_reg_19; //pipeline_reg_20 <= pipeline_reg_20; //pipeline_reg_21 <= pipeline_reg_21; //pipeline_reg_22 <= pipeline_reg_22; //pipeline_reg_23 <= pipeline_reg_23; //pipeline_reg_24 <= pipeline_reg_24; //pipeline_reg_25 <= pipeline_reg_25; //pipeline_reg_26 <= pipeline_reg_26; //pipeline_reg_27 <= pipeline_reg_27; //pipeline_reg_28 <= pipeline_reg_28; //pipeline_reg_29 <= pipeline_reg_29; //pipeline_reg_30 <= pipeline_reg_30; //pipeline_reg_31 <= pipeline_reg_31; //pipeline_reg_32 <= pipeline_reg_32; //pipeline_reg_33 <= pipeline_reg_33; //pipeline_reg_34 <= pipeline_reg_34; //pipeline_reg_35 <= pipeline_reg_35; //pipeline_reg_36 <= pipeline_reg_36; //pipeline_reg_37 <= pipeline_reg_37; //pipeline_reg_38 <= pipeline_reg_38; //pipeline_reg_39 <= pipeline_reg_39; //pipeline_reg_40 <= pipeline_reg_40; //pipeline_reg_41 <= pipeline_reg_41; //pipeline_reg_42 <= pipeline_reg_42; //pipeline_reg_43 <= pipeline_reg_43; //pipeline_reg_44 <= pipeline_reg_44; //pipeline_reg_45 <= pipeline_reg_45; //pipeline_reg_46 <= pipeline_reg_46; //pipeline_reg_47 <= pipeline_reg_47; //pipeline_reg_48 <= pipeline_reg_48; //pipeline_reg_49 <= pipeline_reg_49; //pipeline_reg_50 <= pipeline_reg_50; //end end end endmodule module adder_with_1_reg ( dataa, datab, result); input clk; input clk_ena; input [17:0] dataa; input [17:0] datab; output [17:0] result; assign result = dataa + datab; endmodule module multiplier_with_reg ( dataa, datab, result); input clk; input clk_ena; input [17:0] dataa; input [17:0] datab; output [17:0] result; assign result = dataa * datab; endmodule module one_register ( dataa, result); input clk; input clk_ena; input [17:0] dataa; output [17:0] result; assign result = dataa; endmodule

/***************************************************************************** * * * Module: Altera_UP_RS232_Counters * * Description: * * This module reads and writes data to the RS232 connector on Altera's * * DE1 and DE2 Development and Education Boards. * * * *****************************************************************************/ module Altera_UP_RS232_Counters ( // Inputs clk, reset, reset_counters, // Bidirectionals // Outputs baud_clock_rising_edge, baud_clock_falling_edge, all_bits_transmitted ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input reset_counters; // Bidirectionals // Outputs output reg baud_clock_rising_edge; output reg baud_clock_falling_edge; output reg all_bits_transmitted; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter; reg [3:0] bit_counter; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (reset_counters) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (baud_counter == BAUD_TICK_COUNT) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else baud_counter <= baud_counter + BAUD_TICK_INCREMENT; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_rising_edge <= 1'b0; else if (baud_counter == BAUD_TICK_COUNT) baud_clock_rising_edge <= 1'b1; else baud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_falling_edge <= 1'b0; else if (baud_counter == HALF_BAUD_TICK_COUNT) baud_clock_falling_edge <= 1'b1; else baud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) bit_counter <= 4'h0; else if (reset_counters) bit_counter <= 4'h0; else if (bit_counter == TOTAL_DATA_WIDTH) bit_counter <= 4'h0; else if (baud_counter == BAUD_TICK_COUNT) bit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin if (reset == 1'b1) all_bits_transmitted <= 1'b0; else if (bit_counter == TOTAL_DATA_WIDTH) all_bits_transmitted <= 1'b1; else all_bits_transmitted <= 1'b0; end /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule

module main(CLK,HSYNC,VSYNC,R,G,B,XCLK,PCLK,D,HIN,VIN); input CLK; output reg HSYNC; output reg VSYNC; output reg R; output reg G; output reg B; output reg XCLK; input PCLK; input [7:0] D; input HIN; input VIN; //hsync = 1589 //pulse = 191 //vsync = 834150 //pulse = 3200 reg [15:0] HCNT; reg [15:0] VCNT; reg drawH; reg drawV; reg [7:0] CAMDAT [1:0]; reg BCNT; reg [15:0] PXCNT; reg [15:0] PVCNT; reg [255:0] RDAT [127:0]; reg [255:0] GDAT [127:0]; reg [255:0] BDAT [127:0]; reg CR; reg CG; reg CB; always @(posedge PCLK)begin if(VIN) PVCNT <= 7'd0; else if(!HIN)begin if(PXCNT != 8'h0) PVCNT <= PVCNT + 7'd1; BCNT <= 1'b0; PXCNT <= 8'h0; end else begin BCNT <= !BCNT; if(BCNT) PXCNT <= PXCNT + 8'd1; end CAMDAT[BCNT] <= D; end always @(negedge CLK) begin XCLK <= ~XCLK; HCNT <= HCNT + 16'h1; if(HCNT == 16'd1588)begin HCNT <= 16'h0; drawH <= 1'b1; end else if(HCNT == 16'd1302)begin HSYNC <= 1'b0; VCNT <= VCNT + 16'h1; end else if(HCNT == 16'd1493)begin HSYNC <= 1'b1; end else if(HCNT == 16'd1270)begin drawH <= 1'b0; end if(VCNT == 16'd513)begin VSYNC <= 1'b0; end else if(VCNT == 16'd515)begin VSYNC <= 1'b1; end else if(VCNT == 16'd524)begin drawV <= 1'b1; VCNT <= 16'h0; end else if(VCNT == 16'd480)begin drawV <= 1'b0; end if(!BCNT && HIN && !VIN && PVCNT[15:8]==0 && PXCNT[15:9]==0) begin RDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][6]; GDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][7]; BDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][5]; end CR <= RDAT[VCNT[7:1]][HCNT[9:2]]; CG <= GDAT[VCNT[7:1]][HCNT[9:2]]; CB <= BDAT[VCNT[7:1]][HCNT[9:2]]; R <= drawH && drawV && CR; G <= drawH && drawV && CG; B <= drawH && drawV && CB; end endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V `define SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V /** * a22o: 2-input AND into both inputs of 2-input OR. * * X = ((A1 & A2) | (B1 & B2)) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_hdll__a22o ( X , A1, A2, B1, B2 ); // Module ports output X ; input A1; input A2; input B1; input B2; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire and0_out ; wire and1_out ; wire or0_out_X; // Name Output Other arguments and and0 (and0_out , B1, B2 ); and and1 (and1_out , A1, A2 ); or or0 (or0_out_X, and1_out, and0_out); buf buf0 (X , or0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V

// bin2v output // module bin2v( input wire [ 9:0] in_addr, output reg [ 7:0] out_word ); always @* case( in_addr ) 10'h0: out_word = 8'h01; 10'h1: out_word = 8'hf7; 10'h2: out_word = 8'h3f; 10'h3: out_word = 8'h3e; 10'h4: out_word = 8'h80; 10'h5: out_word = 8'hED; 10'h6: out_word = 8'h79; // 3ff7<=BF 10'h7: out_word = 8'h00; 10'h8: out_word = 8'h06; 10'h9: out_word = 8'h7F; 10'hA: out_word = 8'h3e; 10'hB: out_word = 8'b01111010; 10'hC: out_word = 8'hED; 10'hD: out_word = 8'h79; 10'hE: out_word = 8'h06; 10'hF: out_word = 8'hBF; 10'h10: out_word = 8'h3E; 10'h11: out_word = 8'b01111101; 10'h12: out_word = 8'hED; 10'h13: out_word = 8'h79; 10'h14: out_word = 8'h06; 10'h15: out_word = 8'hFF; 10'h16: out_word = 8'h3E; 10'h17: out_word = 8'b01111111; 10'h18: out_word = 8'hED; 10'h19: out_word = 8'h79; 10'h1A: out_word = 8'h01; 10'h1B: out_word = 8'h77; 10'h1C: out_word = 8'hFD; 10'h1D: out_word = 8'h3E; 10'h1E: out_word = 8'hAB; 10'h1F: out_word = 8'hED; 10'h20: out_word = 8'h79; 10'h21: out_word = 8'h21; 10'h22: out_word = 8'h00; 10'h23: out_word = 8'h01; 10'h24: out_word = 8'h11; 10'h25: out_word = 8'h00; 10'h26: out_word = 8'h60; 10'h27: out_word = 8'h01; 10'h28: out_word = 8'h00; 10'h29: out_word = 8'h01; 10'h2A: out_word = 8'hED; 10'h2B: out_word = 8'hB0; 10'h2C: out_word = 8'hC3; 10'h2D: out_word = 8'h00; 10'h2E: out_word = 8'h60; 10'h100: out_word = 8'h01; 10'h101: out_word = 8'h77; 10'h102: out_word = 8'hff; 10'h103: out_word = 8'h3e; 10'h104: out_word = 8'hab; 10'h105: out_word = 8'hed; 10'h106: out_word = 8'h79; 10'h107: out_word = 8'h3e; 10'h108: out_word = 8'h01; 10'h109: out_word = 8'hd3; 10'h10a: out_word = 8'hbf; 10'h10b: out_word = 8'h01; 10'h10c: out_word = 8'hf7; 10'h10d: out_word = 8'hee; 10'h10e: out_word = 8'h3e; 10'h10f: out_word = 8'h80; 10'h110: out_word = 8'hed; 10'h111: out_word = 8'h79; 10'h112: out_word = 8'h06; 10'h113: out_word = 8'hde; 10'h114: out_word = 8'h3e; 10'h115: out_word = 8'h01; 10'h116: out_word = 8'hed; 10'h117: out_word = 8'h79; 10'h118: out_word = 8'h06; 10'h119: out_word = 8'hbe; 10'h11a: out_word = 8'h3e; 10'h11b: out_word = 8'h22; 10'h11c: out_word = 8'hed; 10'h11d: out_word = 8'h78; default: out_word = 8'hFF; endcase endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V `define SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V /** * nand2b: 2-input NAND, first input inverted. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_ms__nand2b ( Y , A_N, B ); // Module ports output Y ; input A_N; input B ; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire not0_out ; wire or0_out_Y; // Name Output Other arguments not not0 (not0_out , B ); or or0 (or0_out_Y, not0_out, A_N ); buf buf0 (Y , or0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V

module dyn_pll_ctrl # (parameter SPEED_MHZ = 25, parameter SPEED_LIMIT = 100, parameter SPEED_MIN = 25, parameter OSC_MHZ = 100) (clk, clk_valid, speed_in, start, progclk, progdata, progen, reset, locked, status); input clk; // NB Assumed to be 12.5MHz uart_clk input clk_valid; // Drive from LOCKED output of first dcm (ie uart_clk valid) input [7:0] speed_in; input start; output reg progclk = 0; output reg progdata = 0; output reg progen = 0; output reg reset = 0; input locked; input [2:1] status; // NB spec says to use (dval-1) and (mval-1), but I don't think we need to be that accurate // and this saves an adder. Feel free to amend it. reg [23:0] watchdog = 0; reg [7:0] state = 0; reg [7:0] dval = OSC_MHZ; // Osc clock speed (hence mval scales in MHz) reg [7:0] mval = SPEED_MHZ; reg start_d1 = 0; always @ (posedge clk) begin progclk <= ~progclk; start_d1 <= start; reset <= 1'b0; // Watchdog is just using locked, perhaps also need | ~status[2] if (locked) watchdog <= 0; else watchdog <= watchdog + 1'b1; if (watchdog[23]) // Approx 670mS at 12.5MHz - NB spec is 5ms to lock at >50MHz CLKIN (50ms at <50MHz CLKIN) begin // but allow longer just in case watchdog <= 0; reset <= 1'b1; // One cycle at 12.5MHz should suffice (requirment is 3 CLKIN at 100MHz) end if (~clk_valid) // Try not to run while clk is unstable begin progen <= 0; progdata <= 0; state <= 0; end else begin // The documentation is unclear as to whether the DCM loads data on positive or negative edge. The timing // diagram unhelpfully shows data changing on the positive edge, which could mean either its sampled on // negative, or it was clocked on positive! However the following (WRONGLY) says NEGATIVE ... // http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-DCM-CLKGEN-does-PROGCLK-have-a-maximum-period-minimum/td-p/175642 // BUT this can lock up the DCM, positive clock seems more reliable (but it can still lock up for low values of M, eg 2). // Added SPEED_MIN to prevent this (and positive clock is correct, after looking at other implementations eg ztex/theseven) if ((start || start_d1) && state==0 && speed_in >= SPEED_MIN && speed_in <= SPEED_LIMIT && progclk==1) // positive clock // if ((start || start_d1) && state==0 && speed_in >= SPEED_MIN && speed_in <= SPEED_LIMIT && progclk==0) // negative clock begin progen <= 0; progdata <= 0; mval <= speed_in; dval <= OSC_MHZ; state <= 1; end if (state != 0) state <= state + 1'd1; case (state) // Even values to sync with progclk // Send D 2: begin progen <= 1; progdata <= 1; end 4: begin progdata <= 0; end 6,8,10,12,14,16,18,20: begin progdata <= dval[0]; dval[6:0] <= dval[7:1]; end 22: begin progen <= 0; progdata <= 0; end // Send M 32: begin progen <= 1; progdata <= 1; end 36,38,40,42,44,46,48,50: begin progdata <= mval[0]; mval[6:0] <= mval[7:1]; end 52: begin progen <= 0; progdata <= 0; end // Send GO - NB 1 clock cycle 62: begin progen <= 1; end 64: begin progen <= 0; end // We should wait on progdone/locked, but just go straight back to idle 254: begin state <= 0; end endcase end end endmodule

// Model of FIFO in Altera module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); parameter width = 32; parameter depth = 4096; //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req input [31:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [31:0] q; output rdfull; output rdempty; output [7:0] rdusedw; output wrfull; output wrempty; output [7:0] wrusedw; reg [width-1:0] mem [0:depth-1]; reg [7:0] rdptr; reg [7:0] wrptr; `ifdef rd_req reg [width-1:0] q; `else wire [width-1:0] q; `endif reg [7:0] rdusedw; reg [7:0] wrusedw; integer i; always @( aclr) begin wrptr <= #1 0; rdptr <= #1 0; for(i=0;i<depth;i=i+1) mem[i] <= #1 0; end always @(posedge wrclk) if(wrreq) begin wrptr <= #1 wrptr+1; mem[wrptr] <= #1 data; end always @(posedge rdclk) if(rdreq) begin rdptr <= #1 rdptr+1; `ifdef rd_req q <= #1 mem[rdptr]; `endif end `ifdef rd_req `else assign q = mem[rdptr]; `endif // Fix these always @(posedge wrclk) wrusedw <= #1 wrptr - rdptr; always @(posedge rdclk) rdusedw <= #1 wrptr - rdptr; endmodule // fifo_1c_4k

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_V `define SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_V /** * srsdfxtp: Scan flop with sleep mode, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v" `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v" `include "../../models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v" `celldefine module sky130_fd_sc_lp__srsdfxtp ( Q , CLK , D , SCD , SCE , SLEEP_B ); // Module ports output Q ; input CLK ; input D ; input SCD ; input SCE ; input SLEEP_B; // Module supplies supply1 KAPWR; supply1 VPWR ; supply0 VGND ; supply1 VPB ; supply0 VNB ; // Local signals wire buf_Q ; wire mux_out ; wire pwrgood_pp0_out_Q; // Delay Name Output Other arguments sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE ); sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SLEEP_B, , KAPWR, VGND, VPWR); sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND ); buf buf0 (Q , pwrgood_pp0_out_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_V

// ---------------------------------------------------------------------- // Copyright (c) 2015, The Regents of the University of California All // rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH // DAMAGE. // ---------------------------------------------------------------------- //---------------------------------------------------------------------------- // Filename: tx_port_monitor_64.v // Version: 1.00.a // Verilog Standard: Verilog-2001 // Description: Detects transaction open/close events from the stream // of data from the tx_port_channel_gate. Filters out events and passes data // onto the tx_port_buffer. // Author: Matt Jacobsen // History: @mattj: Version 2.0 //----------------------------------------------------------------------------- `define S_TXPORTMON64_NEXT 5'b0_0001 `define S_TXPORTMON64_TXN 5'b0_0010 `define S_TXPORTMON64_READ 5'b0_0100 `define S_TXPORTMON64_END_0 5'b0_1000 `define S_TXPORTMON64_END_1 5'b1_0000 `timescale 1ns/1ns module tx_port_monitor_64 #( parameter C_DATA_WIDTH = 9'd64, parameter C_FIFO_DEPTH = 512, // Local parameters parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4), parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1), parameter C_VALID_HIST = 1 ) ( input RST, input CLK, input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate input EVT_DATA_EMPTY, // Event data FIFO is empty output EVT_DATA_RD_EN, // Event data FIFO read enable output [C_DATA_WIDTH-1:0] WR_DATA, // Output data output WR_EN, // Write enable for output data input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count output TXN, // Transaction parameters are valid input ACK, // Transaction parameter read, continue output LAST, // Channel last write output [31:0] LEN, // Channel write length (in 32 bit words) output [30:0] OFF, // Channel write offset output [31:0] WORDS_RECVD, // Count of data words received in transaction output DONE, // Transaction is closed input TX_ERR // Transaction encountered an error ); `include "functions.vh" (* syn_encoding = "user" *) (* fsm_encoding = "user" *) reg [4:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT; reg rRead=0, _rRead=0; reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}}; reg rEvent=0, _rEvent=0; reg [63:0] rReadData=64'd0, _rReadData=64'd0; reg [31:0] rWordsRecvd=0, _rWordsRecvd=0; reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0; reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0; reg rAlmostFull=0, _rAlmostFull=0; reg rLenEQ0Hi=0, _rLenEQ0Hi=0; reg rLenEQ0Lo=0, _rLenEQ0Lo=0; reg rLenLE2Lo=0, _rLenLE2Lo=0; reg rTxErr=0, _rTxErr=0; wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]); wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON64_READ wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData); assign EVT_DATA_RD_EN = rRead; assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0]; assign WR_EN = wPayloadData; // S_TXPORTMON64_READ assign TXN = rState[1]; // S_TXPORTMON64_TXN assign LAST = rReadData[0]; assign OFF = rReadData[31:1]; assign LEN = rReadData[63:32]; assign WORDS_RECVD = rWordsRecvd; assign DONE = !rState[2]; // !S_TXPORTMON64_READ // Buffer the input signals that come from outside the tx_port. always @ (posedge CLK) begin rTxErr <= #1 (RST ? 1'd0 : _rTxErr); end always @ (*) begin _rTxErr = TX_ERR; end // Transaction monitoring FSM. always @ (posedge CLK) begin rState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState); end always @ (*) begin _rState = rState; case (rState) `S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event if (rEvent) _rState = `S_TXPORTMON64_TXN; end `S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged if (ACK) _rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ); end `S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data if (rEvent) _rState = `S_TXPORTMON64_END_1; else if (wAllWordsRecvd | rTxErr) _rState = `S_TXPORTMON64_END_0; end `S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event if (rEvent) _rState = `S_TXPORTMON64_END_1; end `S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event if (rEvent) _rState = `S_TXPORTMON64_NEXT; end default: begin _rState = `S_TXPORTMON64_NEXT; end endcase end // Manage reading from the FIFO and tracking amounts read. always @ (posedge CLK) begin rRead <= #1 (RST ? 1'd0 : _rRead); rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid); rEvent <= #1 (RST ? 1'd0 : _rEvent); rReadData <= #1 _rReadData; rWordsRecvd <= #1 _rWordsRecvd; rWordsRecvdAdv <= #1 _rWordsRecvdAdv; rAlmostAllRecvd <= #1 _rAlmostAllRecvd; rAlmostFull <= #1 _rAlmostFull; rLenEQ0Hi <= #1 _rLenEQ0Hi; rLenEQ0Lo <= #1 _rLenEQ0Lo; rLenLE2Lo <= #1 _rLenLE2Lo; end always @ (*) begin // Don't get to the full point in the output FIFO _rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH); // Track read history so we know when data is valid _rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY)); // Read until we get a (valid) event _rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN // Track detected events _rEvent = wEventData; // Save event data when valid if (wEventData) _rReadData = EVT_DATA[C_DATA_WIDTH-1:0]; else _rReadData = rReadData; // If LEN == 0, we don't want to send any data to the output _rLenEQ0Hi = (LEN[31:16] == 16'd0); _rLenEQ0Lo = (LEN[15:0] == 16'd0); // If LEN <= 2, we want to trigger the almost all received flag _rLenLE2Lo = (LEN[15:0] <= 16'd2); // Count received non-event data _rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1)); _rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1)); _rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData); end /* wire [35:0] wControl0; chipscope_icon_1 cs_icon( .CONTROL0(wControl0) ); chipscope_ila_t8_512 a0( .CLK(CLK), .CONTROL(wControl0), .TRIG0({TXN, wPayloadData, wEventData, rState}), .DATA({297'd0, WR_COUNT, // 10 wPayloadData, // 1 EVT_DATA_RD_EN, // 1 RST, // 1 rTxErr, // 1 wEventData, // 1 rReadData, // 64 OFF, // 31 LEN, // 32 LAST, // 1 TXN, // 1 EVT_DATA_EMPTY, // 1 EVT_DATA, // 65 rState}) // 5 ); */ endmodule

/* * Copyright (c) 2003 Stephen Williams ([email protected]) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU * General Public License as published by the Free Software * Foundation; either version 2 of the License, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * * $Id: timer_tb.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $ */ `timescale 1us / 1us module main; wire rdy; reg reset, clk; timer dut(.rdy(rdy), .clk(clk), .reset(reset)); always begin #5 clk = 1; #5 clk = 0; end initial begin $dumpvars(0, main); #7 reset = 1; #1 if (rdy !== 0) begin $display("FAILED: reset did not clear rdy. rdy=%b", rdy); $finish; end #6 reset = 0; end always @(posedge clk) if (rdy === 1) begin $display("rdy=%b at time=%0d", rdy, $time); if ($time != 175) begin $display("FAILED: timer ran out incorrectly."); $finish; end $display("PASSED"); $finish; end endmodule // main

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V `define SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V /** * xnor3: 3-input exclusive NOR. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hs__xnor3 ( X , A , B , C , VPWR, VGND ); output X ; input A ; input B ; input C ; input VPWR; input VGND; endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V

////////////////////////////////////////////////////////////////////////////////// // BCHEncoderDataChannel for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Jinwoo Jeong <[email protected]> // Kibin Park <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Jinwoo Jeong <[email protected]> // Kibin Park <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: BCH encoder controller data channel // Module Name: BCHEncoderDataChannel // File Name: BCHEncoderDataChannel.v // // Version: v1.0.0 // // Description: BCH encoder controller data channel // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module BCHEncoderDataChannel # ( parameter DataWidth = 32 , parameter InnerIFLengthWidth = 16 ) ( iClock , iReset , iLength , iCmdType , iCmdValid , oCmdReady , oSrcReadData , oSrcReadValid , oSrcReadLast , iSrcReadReady , iDstReadData , iDstReadValid , iDstReadLast , oDstReadReady ); input iClock ; input iReset ; input [InnerIFLengthWidth - 1:0] iLength ; input [1:0] iCmdType ; input iCmdValid ; output oCmdReady ; output [DataWidth - 1:0] oSrcReadData ; output oSrcReadValid ; output oSrcReadLast ; input iSrcReadReady ; input [DataWidth - 1:0] iDstReadData ; input iDstReadValid ; input iDstReadLast ; output oDstReadReady ; reg [DataWidth - 1:0] rReadData ; reg rReadLast ; reg rReadValid ; wire wReadReady ; wire wReadFull ; wire wReadEmpty ; reg rDstReadReady ; parameter ECCCtrlCmdType_Bypass = 2'b00 ; parameter ECCCtrlCmdType_PageEncode = 2'b01 ; parameter ECCCtrlCmdType_SpareEncode = 2'b10 ; reg [1:0] rCmdType ; reg [InnerIFLengthWidth - 1:0] rLength ; reg [5:0] rCurLoopCount ; reg [5:0] rGoalLoopCount ; //reg [7:0] rCounter ; reg rCRCSpareSwitch ; wire wPageEncEnable ; wire wCRCEncEnable ; wire wCRCDataValid ; wire [DataWidth - 1:0] wCRCData ; reg rDstPageDataValid ; reg rDstPageDataLast ; reg [DataWidth - 1:0] rDstPageData ; reg rPageDataValid ; wire wCRCSpareSwitch ; wire wCRCParityLast ; wire wCRCParityValid ; wire [DataWidth - 1:0] wCRCParityOut ; wire wDownConverterReady ; wire wDownConvertedDataValid ; wire wDownConvertedDataLast ; wire [DataWidth/2 - 1:0] wDownConvertedData ; wire wEncoderReady ; wire wEncodeDataInReady ; wire wPageDataLast ; wire [DataWidth/2 - 1:0] wPageParityData ; wire wPageParityValid ; wire wPageParityLast ; wire wUpConverterReady ; wire wEncodeDataValid; wire [DataWidth/2 - 1:0] wEncodeData; wire wUpConvertDataValid; wire [DataWidth/2 - 1:0] wUpConvertData; wire wUpConvertedDataValid; wire wUpConvertedDataLast; reg rUpConvertedDataLast; wire wUpConvertedParityLast; wire [DataWidth - 1:0] wUpConvertedData; reg rReadReady; wire wDataBufferPopSignal ; wire wCRCAvailable ; wire wReset ; localparam State_Idle = 3'b000; localparam State_Forward = 3'b001; localparam State_Encode = 3'b011; localparam State_ParityOut = 3'b010; localparam State_LoopEnd = 3'b110; reg [2:0] rCurState ; reg [2:0] rNextState ; assign oCmdReady = (rCurState == State_Idle); assign wReadReady = !wReadFull; assign wEncodeDataValid = (rCurState == State_ParityOut) ? wPageParityValid : (rCurState == State_Encode) ? wDownConvertedDataValid : 1'b0; assign wEncodeData = (rCurState == State_ParityOut) ? wPageParityData : (rCurState == State_Encode) ? wDownConvertedData : {(DataWidth/2){1'b0}}; assign wUpConvertDataValid = (rUpConvertedDataLast | wUpConvertedDataLast) ? 1'b0 : wEncodeDataValid; assign wEncodeDataInReady = (rCurState == State_Encode) && (wUpConverterReady & wEncoderReady); assign oDstReadReady = rDstReadReady; assign wCRCDataValid = rDstPageDataValid & wDownConverterReady; assign wCRCData = rDstPageData; assign wCRCEncEnable = (rCmdType == ECCCtrlCmdType_SpareEncode) ? 1'b0 : 1'b1; assign wPageEncEnable = 1'b1; assign wReset = (iReset) || ((rCmdType == ECCCtrlCmdType_SpareEncode) && (rCurState == State_ParityOut)); always @ (posedge iClock) if (iReset) rCurState <= State_Idle; else rCurState <= rNextState; always @ (posedge iClock) if (iReset) rCRCSpareSwitch <= 0; else begin if (wCRCSpareSwitch) rCRCSpareSwitch <= 1'b1; else begin if (wPageDataLast && (rCmdType == ECCCtrlCmdType_SpareEncode)) rCRCSpareSwitch <= 1'b0; end end always @ (*) case (rCurState) State_Idle: if (iCmdValid) begin if (iCmdType == ECCCtrlCmdType_Bypass) rNextState <= State_Forward; else rNextState <= State_Encode; end else rNextState <= State_Idle; State_Forward: rNextState <= (iDstReadValid && iDstReadLast && oDstReadReady)?State_Idle:State_Forward; State_Encode: rNextState <= (wPageDataLast)?State_ParityOut:State_Encode; State_ParityOut: rNextState <= (wUpConvertedDataValid && wReadReady && wUpConvertedParityLast)?State_LoopEnd:State_ParityOut; State_LoopEnd: rNextState <= (rCurLoopCount == rGoalLoopCount)?State_Idle:State_Encode; default: rNextState <= State_Idle; endcase always @ (posedge iClock) if (iReset) rCmdType <= 2'b0; else case (rCurState) State_Idle: if (iCmdValid) rCmdType <= iCmdType; endcase always @ (posedge iClock) if (iReset) rLength <= {(InnerIFLengthWidth){1'b0}}; else case (rCurState) State_Idle: if (iCmdValid) rLength <= iLength; endcase /*always @ (posedge iClock) if (iReset) rCounter <= {(8){1'b0}}; else case (rCurState) State_Encode: rCounter <= (iDstReadValid & oDstReadReady) ? rCounter + 1'b1 : rCounter; default: rCounter <= {(8){1'b0}}; endcase*/ always @ (posedge iClock) if (iReset) rCurLoopCount <= {(6){1'b0}}; else case (rCurState) State_Idle: rCurLoopCount <= {(6){1'b0}}; State_LoopEnd: rCurLoopCount <= rCurLoopCount + 1'b1; endcase always @ (posedge iClock) if (iReset) rGoalLoopCount <= {(6){1'b0}}; else case (rCurState) State_Idle: if (iCmdValid) begin if (iCmdType == ECCCtrlCmdType_PageEncode) rGoalLoopCount <= 31; else rGoalLoopCount <= 0; end endcase /*always @ (*) case (rCurState) State_Idle: rSpareCounter <= {(8){1'b0}}; State_Encode: if (rCRCSpareSwitch && iDstReadValid && wCRCParityLast && wDstReadReady) rSpareCounter <= rSpareCounter + 1'b1; endcase */ always @ (*) case (rCurState) State_Encode: if (rCmdType == ECCCtrlCmdType_PageEncode) begin rDstPageData <= iDstReadData; rDstPageDataValid <= iDstReadValid; end else if (rCRCSpareSwitch) begin if (wCRCAvailable) begin rDstPageData <= {(DataWidth){1'b0}}; rDstPageDataValid <= 1'b1; end else begin rDstPageData <= wCRCParityOut; rDstPageDataValid <= wCRCParityValid; end end else begin rDstPageData <= iDstReadData; rDstPageDataValid <= iDstReadValid; end default: begin rDstPageData <= {(DataWidth){1'b0}}; rDstPageDataValid <= 1'b0; end endcase always @ (posedge iClock) if (iReset) rDstPageDataLast <= 0; else if (wCRCParityLast & rDstPageDataValid) rDstPageDataLast <= 1'b1; else rDstPageDataLast <= 1'b0; always @ (posedge iClock) if (iReset) rUpConvertedDataLast <= 0; else if (wUpConvertedDataLast) rUpConvertedDataLast <= wUpConvertedDataLast; else if (rCurState == State_ParityOut) rUpConvertedDataLast <= 0; always @ (*) case (rCurState) State_Forward: begin rReadData <= iDstReadData ; rReadValid <= iDstReadValid ; rReadLast <= iDstReadLast ; rDstReadReady <= wReadReady ; end State_Encode: begin rReadData <= wUpConvertedData ; rReadValid <= (rUpConvertedDataLast) ? 1'b0 : wUpConvertedDataValid ; rReadLast <= 1'b0 ; if (rCRCSpareSwitch & wCRCAvailable) rDstReadReady <= 1'b0; else rDstReadReady <= wDownConverterReady; end State_ParityOut: begin rReadData <= wUpConvertedData ; rReadValid <= wUpConvertedDataValid; rReadLast <= wUpConvertedParityLast && (rCurLoopCount == rGoalLoopCount) ; rDstReadReady <= 1'b0 ; end default: begin rReadData <= {(DataWidth){1'b0}} ; rReadValid <= 1'b0 ; rReadLast <= 1'b0 ; rDstReadReady <= 1'b0 ; end endcase CRC_Generator # ( .DATA_WIDTH (32), .HASH_LENGTH (64), .INPUT_COUNT_BITS (13), .INPUT_COUNT (4158), .OUTPUT_COUNT (2) ) CRCGenerator ( .i_clk (iClock), .i_nRESET (!iReset), .i_execute_crc_gen (wCRCEncEnable), .i_message_valid (wCRCDataValid), .i_message (wCRCData), .i_out_pause (!rDstReadReady), .o_crc_gen_start (), .o_last_message (), .o_crc_gen_complete (), .o_crc_spare_switch (wCRCSpareSwitch), .o_parity_out_strobe (wCRCParityValid), .o_parity_out_start (), .o_parity_out_complete (wCRCParityLast), .o_parity_out (wCRCParityOut), .o_crc_available (wCRCAvailable) ); EncWidthConverter32to16 #( .InputDataWidth(32), .OutputDataWidth(16) ) Inst_WidthDownConverter ( .iClock (iClock), .iReset (wReset), .iSrcDataValid (rDstPageDataValid), .iSrcDataLast (rDstPageDataLast), .iSrcData (rDstPageData), .oConverterReady (wDownConverterReady), .oConvertedDataValid (wDownConvertedDataValid), .oConvertedDataLast (wDownConvertedDataLast), .oConvertedData (wDownConvertedData), .iDstReady (wEncodeDataInReady) ); BCHEncoderX # ( .Multi(2) ) BCHPageEncoder ( .iClock (iClock), .iReset (iReset), .iEnable (wPageEncEnable), .iData (wEncodeData), .iDataValid (wEncodeDataValid), .oDataReady (wEncoderReady), .oDataLast (wPageDataLast), .oParityData (wPageParityData), .oParityValid (wPageParityValid), .oParityLast (wPageParityLast), .iParityReady (wUpConverterReady) ); EncWidthConverter16to32 #( .InputDataWidth(16), .OutputDataWidth(32) ) Inst_WidthUpConverter ( .iClock (iClock), .iReset (iReset), .iCurLoopCount (rCurLoopCount[0]), .iCmdType (rCmdType), .iSrcDataValid (wUpConvertDataValid), .iSrcDataLast (wDownConvertedDataLast), .iSrcParityLast (wPageParityLast), .iSrcData (wEncodeData), .oConverterReady (wUpConverterReady), .oConvertedDataValid (wUpConvertedDataValid), .oConvertedDataLast (wUpConvertedDataLast), .oConvertedParityLast (wUpConvertedParityLast), .oConvertedData (wUpConvertedData), .iDstReady (wReadReady) ); SCFIFO_64x64_withCount DataBuffer ( .iClock (iClock ), .iReset (iReset ), .iPushData ({rReadData, rReadLast} ), .iPushEnable (rReadValid && wReadReady ), .oIsFull (wReadFull ), .oPopData ({oSrcReadData, oSrcReadLast} ), .iPopEnable (wDataBufferPopSignal ), .oIsEmpty (wReadEmpty ), .oDataCount ( ) ); AutoFIFOPopControl DataBufferControl ( .iClock (iClock ), .iReset (iReset ), .oPopSignal (wDataBufferPopSignal ), .iEmpty (wReadEmpty ), .oValid (oSrcReadValid ), .iReady (iSrcReadReady ) ); endmodule

//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_7x_0_core_top_pipe_reset.v // Version : 3.0 //------------------------------------------------------------------------------ // Filename : pipe_reset.v // Description : PIPE Reset Module for 7 Series Transceiver // Version : 20.2 //------------------------------------------------------------------------------ `timescale 1ns / 1ps //---------- PIPE Reset Module ------------------------------------------------- (* DowngradeIPIdentifiedWarnings = "yes" *) module pcie_7x_0_core_top_pipe_reset # ( //---------- Global ------------------------------------ parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup parameter PCIE_GT_DEVICE = "GTX", parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable parameter PCIE_LANE = 1, // PCIe number of lanes //---------- Local ------------------------------------- parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK ) ( //---------- Input ------------------------------------- input RST_CLK, input RST_RXUSRCLK, input RST_DCLK, input RST_RST_N, input [PCIE_LANE-1:0] RST_DRP_DONE, input [PCIE_LANE-1:0] RST_RXPMARESETDONE, input [PCIE_LANE-1:0] RST_CPLLLOCK, input RST_QPLL_IDLE, input [PCIE_LANE-1:0] RST_RATE_IDLE, input [PCIE_LANE-1:0] RST_RXCDRLOCK, input RST_MMCM_LOCK, input [PCIE_LANE-1:0] RST_RESETDONE, input [PCIE_LANE-1:0] RST_PHYSTATUS, input [PCIE_LANE-1:0] RST_TXSYNC_DONE, //---------- Output ------------------------------------ output RST_CPLLRESET, output RST_CPLLPD, output reg RST_DRP_START, output reg RST_DRP_X16X20_MODE, output reg RST_DRP_X16, output RST_RXUSRCLK_RESET, output RST_DCLK_RESET, output RST_GTRESET, output RST_USERRDY, output RST_TXSYNC_START, output RST_IDLE, output [4:0] RST_FSM ); //---------- Input Register ---------------------------- (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2; //---------- Internal Signal --------------------------- reg [ 5:0] cfg_wait_cnt = 6'd0; //---------- Output Register --------------------------- reg cpllreset = 1'd0; reg cpllpd = 1'd0; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0; reg gtreset = 1'd0; reg userrdy = 1'd0; reg [4:0] fsm = 5'h2; //---------- FSM --------------------------------------- localparam FSM_IDLE = 5'h0; localparam FSM_CFG_WAIT = 5'h1; localparam FSM_CPLLRESET = 5'h2; localparam FSM_DRP_X16_START = 5'h3; localparam FSM_DRP_X16_DONE = 5'h4; localparam FSM_CPLLLOCK = 5'h5; localparam FSM_DRP = 5'h6; localparam FSM_GTRESET = 5'h7; localparam FSM_RXPMARESETDONE_1 = 5'h8; localparam FSM_RXPMARESETDONE_2 = 5'h9; localparam FSM_DRP_X20_START = 5'hA; localparam FSM_DRP_X20_DONE = 5'hB; localparam FSM_MMCM_LOCK = 5'hC; localparam FSM_RESETDONE = 5'hD; localparam FSM_CPLL_PD = 5'hE; localparam FSM_TXSYNC_START = 5'hF; localparam FSM_TXSYNC_DONE = 5'h10; //---------- Input FF ---------------------------------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) begin //---------- 1st Stage FF -------------------------- drp_done_reg1 <= {PCIE_LANE{1'd0}}; rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}}; cplllock_reg1 <= {PCIE_LANE{1'd0}}; qpll_idle_reg1 <= 1'd0; rate_idle_reg1 <= {PCIE_LANE{1'd0}}; rxcdrlock_reg1 <= {PCIE_LANE{1'd0}}; mmcm_lock_reg1 <= 1'd0; resetdone_reg1 <= {PCIE_LANE{1'd0}}; phystatus_reg1 <= {PCIE_LANE{1'd0}}; txsync_done_reg1 <= {PCIE_LANE{1'd0}}; //---------- 2nd Stage FF -------------------------- drp_done_reg2 <= {PCIE_LANE{1'd0}}; rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}}; cplllock_reg2 <= {PCIE_LANE{1'd0}}; qpll_idle_reg2 <= 1'd0; rate_idle_reg2 <= {PCIE_LANE{1'd0}}; rxcdrlock_reg2 <= {PCIE_LANE{1'd0}}; mmcm_lock_reg2 <= 1'd0; resetdone_reg2 <= {PCIE_LANE{1'd0}}; phystatus_reg2 <= {PCIE_LANE{1'd0}}; txsync_done_reg2 <= {PCIE_LANE{1'd0}}; end else begin //---------- 1st Stage FF -------------------------- drp_done_reg1 <= RST_DRP_DONE; rxpmaresetdone_reg1 <= RST_RXPMARESETDONE; cplllock_reg1 <= RST_CPLLLOCK; qpll_idle_reg1 <= RST_QPLL_IDLE; rate_idle_reg1 <= RST_RATE_IDLE; rxcdrlock_reg1 <= RST_RXCDRLOCK; mmcm_lock_reg1 <= RST_MMCM_LOCK; resetdone_reg1 <= RST_RESETDONE; phystatus_reg1 <= RST_PHYSTATUS; txsync_done_reg1 <= RST_TXSYNC_DONE; //---------- 2nd Stage FF -------------------------- drp_done_reg2 <= drp_done_reg1; rxpmaresetdone_reg2 <= rxpmaresetdone_reg1; cplllock_reg2 <= cplllock_reg1; qpll_idle_reg2 <= qpll_idle_reg1; rate_idle_reg2 <= rate_idle_reg1; rxcdrlock_reg2 <= rxcdrlock_reg1; mmcm_lock_reg2 <= mmcm_lock_reg1; resetdone_reg2 <= resetdone_reg1; phystatus_reg2 <= phystatus_reg1; txsync_done_reg2 <= txsync_done_reg1; end end //---------- Configuration Reset Wait Counter ---------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) cfg_wait_cnt <= 6'd0; else //---------- Increment Configuration Reset Wait Counter if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX)) cfg_wait_cnt <= cfg_wait_cnt + 6'd1; //---------- Hold Configuration Reset Wait Counter - else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX)) cfg_wait_cnt <= cfg_wait_cnt; //---------- Reset Configuration Reset Wait Counter else cfg_wait_cnt <= 6'd0; end //---------- PIPE Reset FSM ---------------------------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) begin fsm <= FSM_CFG_WAIT; cpllreset <= 1'd0; cpllpd <= 1'd0; gtreset <= 1'd0; userrdy <= 1'd0; end else begin case (fsm) //---------- Idle State ---------------------------- FSM_IDLE : begin if (!RST_RST_N) begin fsm <= FSM_CFG_WAIT; cpllreset <= 1'd0; cpllpd <= 1'd0; gtreset <= 1'd0; userrdy <= 1'd0; end else begin fsm <= FSM_IDLE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end end //---------- Wait for Configuration Reset Delay --- FSM_CFG_WAIT : begin fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Hold CPLL and GTX Channel in Reset ---- FSM_CPLLRESET : begin fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET); cpllreset <= 1'd1; cpllpd <= cpllpd; gtreset <= 1'd1; userrdy <= userrdy; end //---------- Wait for CPLL Lock -------------------- FSM_CPLLLOCK : begin fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK); cpllreset <= 1'd0; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for DRP Done to Setup Gen1 ------- FSM_DRP : begin fsm <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Start DRP x16 ------------------------- FSM_DRP_X16_START : begin fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for DRP x16 Done ----------------- FSM_DRP_X16_DONE : begin fsm <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Release GTX Channel Reset ------------- FSM_GTRESET : begin fsm <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= 1'b0; userrdy <= userrdy; end //---------- Wait for RXPMARESETDONE Assertion ----- FSM_RXPMARESETDONE_1 : begin fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for RXPMARESETDONE De-assertion -- FSM_RXPMARESETDONE_2 : begin fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Start DRP x20 ------------------------- FSM_DRP_X20_START : begin fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for DRP x20 Done ----------------- FSM_DRP_X20_DONE : begin fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for MMCM and RX CDR Lock --------- FSM_MMCM_LOCK : begin if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL"))) begin fsm <= FSM_RESETDONE; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= 1'd1; end else begin fsm <= FSM_MMCM_LOCK; cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= 1'd0; end end //---------- Wait for [TX/RX]RESETDONE and PHYSTATUS FSM_RESETDONE : begin fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2 FSM_CPLL_PD : begin fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START); cpllreset <= cpllreset; cpllpd <= (PCIE_PLL_SEL == "QPLL"); gtreset <= gtreset; userrdy <= userrdy; end //---------- Start TX Sync ------------------------- FSM_TXSYNC_START : begin fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Wait for TX Sync Done ----------------- FSM_TXSYNC_DONE : begin fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE); cpllreset <= cpllreset; cpllpd <= cpllpd; gtreset <= gtreset; userrdy <= userrdy; end //---------- Default State ------------------------- default : begin fsm <= FSM_CFG_WAIT; cpllreset <= 1'd0; cpllpd <= 1'd0; gtreset <= 1'd0; userrdy <= 1'd0; end endcase end end //---------- RXUSRCLK Reset Synchronizer --------------------------------------- always @ (posedge RST_RXUSRCLK) begin if (cpllreset) begin rxusrclk_rst_reg1 <= 1'd1; rxusrclk_rst_reg2 <= 1'd1; end else begin rxusrclk_rst_reg1 <= 1'd0; rxusrclk_rst_reg2 <= rxusrclk_rst_reg1; end end //---------- DCLK Reset Synchronizer ------------------------------------------- always @ (posedge RST_DCLK) begin if (fsm == FSM_CFG_WAIT) begin dclk_rst_reg1 <= 1'd1; dclk_rst_reg2 <= dclk_rst_reg1; end else begin dclk_rst_reg1 <= 1'd0; dclk_rst_reg2 <= dclk_rst_reg1; end end //---------- PIPE Reset Output ------------------------------------------------- assign RST_CPLLRESET = cpllreset; assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd); assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; assign RST_DCLK_RESET = dclk_rst_reg2; assign RST_GTRESET = gtreset; assign RST_USERRDY = userrdy; assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START); assign RST_IDLE = (fsm == FSM_IDLE); assign RST_FSM = fsm; //-------------------------------------------------------------------------------------------------- // Register Output //-------------------------------------------------------------------------------------------------- always @ (posedge RST_CLK) begin if (!RST_RST_N) begin RST_DRP_START <= 1'd0; RST_DRP_X16X20_MODE <= 1'd0; RST_DRP_X16 <= 1'd0; end else begin RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE); RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); end end endmodule

////////////////////////////////////////////////////////////////////////////////// // NPM_Toggle_DO_tADL_DDR100 for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Ilyong Jung <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Ilyong Jung <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: NPM_Toggle_DO_tADL_DDR100 // Module Name: NPM_Toggle_DO_tADL_DDR100 // File Name: NPM_Toggle_DO_tADL_DDR100.v // // Version: v1.0.0 // // Description: NFC PM data out FSM // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module NPM_Toggle_DO_tADL_DDR100 # ( // support "serial execution" // Data Packet Width (DQ): 8 bit // iOption: set SDR/DDR mode // 0-SDR(WE#), 1-DDR(DQS) // NumOfData: 0 means 1 // -> unit: word (32 bit = 4 B) // _tADL.v // (original design: tCDQSS = 110 ns, tWPRE = 30 ns) // // tCDQSS = 250 ns => 25 cycles // tWPRE = 50 ns => 5 cycles // future -> add data buffer? parameter NumberOfWays = 4 ) ( iSystemClock , iReset , oReady , oLastStep , iStart , iOption , iTargetWay , iWriteData , iWriteLast , iWriteValid , oWriteReady , oPO_DQStrobe , oPO_DQ , oPO_ChipEnable , oPO_WriteEnable , oPO_AddressLatchEnable , oPO_CommandLatchEnable , oDQSOutEnable , oDQOutEnable ); input iSystemClock ; input iReset ; output oReady ; output oLastStep ; input iStart ; input iOption ; input [NumberOfWays - 1:0] iTargetWay ; input [31:0] iWriteData ; input iWriteLast ; input iWriteValid ; output oWriteReady ; output [7:0] oPO_DQStrobe ; output [31:0] oPO_DQ ; output [2*NumberOfWays - 1:0] oPO_ChipEnable ; output [3:0] oPO_WriteEnable ; output [3:0] oPO_AddressLatchEnable ; output [3:0] oPO_CommandLatchEnable ; output oDQSOutEnable ; output oDQOutEnable ; // FSM Parameters/Wires/Regs localparam DTO_FSM_BIT = 9; // DaTa Out localparam DTO_RESET = 9'b000_000_001; localparam DTO_READY = 9'b000_000_010; localparam DTO_DQS01 = 9'b000_000_100; // info. capture, wait state for tCDQSS localparam DTO_DQS02 = 9'b000_001_000; // wait state for tCDQSS localparam DTO_WPRAM = 9'b000_010_000; // wait state for tWRPE localparam DTO_DQOUT = 9'b000_100_000; // DQ out: loop localparam DTO_PAUSE = 9'b001_000_000; // pause DQ out localparam DTO_DQLST = 9'b010_000_000; // DQ out: last localparam DTO_WPSAM = 9'b100_000_000; // wait state for tWPST localparam DTO_WPSA2 = 9'b110_000_000; // temp. state: will be removed reg [DTO_FSM_BIT-1:0] rDTO_cur_state ; reg [DTO_FSM_BIT-1:0] rDTO_nxt_state ; // Internal Wires/Regs reg rReady ; reg rLastStep ; reg rOption ; reg [4:0] rDTOSubCounter ; wire [2*NumberOfWays - 1:0] wPO_ChipEnable ; wire wtCDQSSDone ; wire wtWPREDone ; wire wLoopDone ; wire wtWPSTDone ; reg [7:0] rPO_DQStrobe ; reg [31:0] rPO_DQ ; reg [2*NumberOfWays - 1:0] rPO_ChipEnable ; reg [3:0] rPO_WriteEnable ; reg [3:0] rPO_AddressLatchEnable ; reg [3:0] rPO_CommandLatchEnable ; reg rDQSOutEnable ; reg rDQOutEnable ; reg rStageFlag ; // Control Signals // Target Way Decoder assign wPO_ChipEnable = { iTargetWay[NumberOfWays - 1:0], iTargetWay[NumberOfWays - 1:0] }; // Flow Control assign wtCDQSSDone = (rDTOSubCounter[4:0] == 5'd25); // 25 => 250 ns assign wtWPREDone = (rDTOSubCounter[4:0] == 5'd30); // 30 - 25 = 5 => 50 ns assign wLoopDone = iWriteLast & iWriteValid; assign wtWPSTDone = (rDTOSubCounter[4:0] == 5'd3); // 3 - 0 = 3 => 30 ns, tWPST = 6.5 ns // FSM: DaTa Out (DTO) // update current state to next state always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rDTO_cur_state <= DTO_RESET; end else begin rDTO_cur_state <= rDTO_nxt_state; end end // deside next state always @ ( * ) begin case (rDTO_cur_state) DTO_RESET: begin rDTO_nxt_state <= DTO_READY; end DTO_READY: begin rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY; end DTO_DQS01: begin rDTO_nxt_state <= DTO_DQS02; end DTO_DQS02: begin rDTO_nxt_state <= (wtCDQSSDone)? DTO_WPRAM:DTO_DQS02; end DTO_WPRAM: begin rDTO_nxt_state <= (wtWPREDone)? ((iWriteValid)? DTO_DQOUT:DTO_PAUSE):DTO_WPRAM; end DTO_DQOUT: begin rDTO_nxt_state <= (rStageFlag)? (DTO_DQOUT):((wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE)); end DTO_PAUSE: begin rDTO_nxt_state <= (wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE); end DTO_DQLST: begin rDTO_nxt_state <= (rStageFlag)? DTO_DQLST:DTO_WPSAM; end DTO_WPSAM: begin rDTO_nxt_state <= (wtWPSTDone)? DTO_WPSA2:DTO_WPSAM; end DTO_WPSA2: begin rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY; end default: rDTO_nxt_state <= DTO_READY; endcase end // state behaviour always @ (posedge iSystemClock, posedge iReset) begin if (iReset) begin rReady <= 0; rLastStep <= 0; rOption <= 0; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= 0; rPO_WriteEnable[3:0] <= 0; rPO_AddressLatchEnable[3:0] <= 0; rPO_CommandLatchEnable[3:0] <= 0; rDQSOutEnable <= 0; rDQOutEnable <= 0; rStageFlag <= 0; end else begin case (rDTO_nxt_state) DTO_RESET: begin rReady <= 0; rLastStep <= 0; rOption <= 0; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= 0; rPO_WriteEnable[3:0] <= 0; rPO_AddressLatchEnable[3:0] <= 0; rPO_CommandLatchEnable[3:0] <= 0; rDQSOutEnable <= 0; rDQOutEnable <= 0; rStageFlag <= 0; end DTO_READY: begin rReady <= 1; rLastStep <= 0; rOption <= 0; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= 0; rPO_WriteEnable[3:0] <= 0; rPO_AddressLatchEnable[3:0] <= 0; rPO_CommandLatchEnable[3:0] <= 0; rDQSOutEnable <= 0; rDQOutEnable <= 0; rStageFlag <= 0; end DTO_DQS01: begin rReady <= 0; rLastStep <= 0; rOption <= iOption; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= wPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b1111; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (iOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 0; end DTO_DQS02: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1; rPO_DQStrobe[7:0] <= 8'b1111_1111; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b1111; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 0; end DTO_WPRAM: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 1'b0; end DTO_DQOUT: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0]; rPO_DQStrobe[7:0] <= 8'b0110_0110; rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0]; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1001; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0; end DTO_PAUSE: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0]; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= { 4{rPO_DQ[31:24]} }; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= 1'b0; end DTO_DQLST: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= 0; rPO_DQStrobe[7:0] <= 8'b0110_0110; rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0]; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b0001; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b1; rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0; end DTO_WPSAM: begin rReady <= 0; rLastStep <= 0; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b0; rStageFlag <= 1'b0; end DTO_WPSA2: begin rReady <= 1; rLastStep <= 1; rOption <= rOption; rDTOSubCounter[4:0] <= rDTOSubCounter[4:0]; rPO_DQStrobe[7:0] <= 8'b0000_0000; rPO_DQ[31:0] <= 0; rPO_ChipEnable <= rPO_ChipEnable; rPO_WriteEnable[3:0] <= 4'b0000; rPO_AddressLatchEnable[3:0] <= 4'b0000; rPO_CommandLatchEnable[3:0] <= 4'b0000; rDQSOutEnable <= (rOption)? 1'b1:1'b0; rDQOutEnable <= 1'b0; rStageFlag <= 1'b0; end endcase end end // Output assign oReady = rReady ; assign oLastStep = rLastStep ; assign oWriteReady = wtWPREDone & (~rStageFlag); assign oPO_DQStrobe = rPO_DQStrobe ; assign oPO_DQ = rPO_DQ ; assign oPO_ChipEnable = rPO_ChipEnable ; assign oPO_WriteEnable = rPO_WriteEnable ; assign oPO_AddressLatchEnable = rPO_AddressLatchEnable; assign oPO_CommandLatchEnable = rPO_CommandLatchEnable; assign oDQSOutEnable = rDQSOutEnable ; assign oDQOutEnable = rDQOutEnable ; endmodule