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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3 (
VPWR,
VGND,
Y ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_FUNCTIONAL_PP_V |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cache_d.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cache_d (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [10:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [15:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]"
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
`include "functions.vh"
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_mem_data_fsm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Receive Memory Data State Machine module. This module takes the
// data from the width conversion fifo (data_trn_mem_fifo) and send it into the
// dma_ddr2_if block
// that passes the data off to the MIG memory controller to write to the DDR2
// memory.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang
// add TX descriptor handling here ---------------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_mem_data_fsm(
input wire clk,
input wire rst,
//interface to dma_ddr2_if block
output reg [127:0] ingress_data,
// output reg [1:0] ingress_fifo_ctrl, //bit 1 = unused bit 0 = write_en
output reg ingress_fifo_wren,
// input wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
output reg [2:0] ingress_xfer_size,
output reg [27:6] ingress_start_addr,
output reg ingress_data_req,
input wire ingress_data_ack,
//interface to xfer_trn_mem_fifo
input wire isDes_fifo, /// Jiansong: added for TX des
input wire [27:6] mem_dest_addr_fifo,
input wire [10:0] mem_dma_size_fifo,
input wire mem_dma_start,//start signal not used-monitor empty instead
input wire mem_trn_fifo_empty,
output reg mem_trn_fifo_rden,
//interface to data_trn_mem_fifo
input wire [127:0] data_fifo_data,
output reg data_fifo_cntrl,
input wire data_fifo_status,
///Jiansong: interface to dma control wrapper
output reg new_des_one, /// Jiansong: is one cycle ok?
output wire [31:0] SourceAddr_L,
output wire [31:0] SourceAddr_H,
output wire [31:0] DestAddr,
output wire [23:0] FrameSize,
output wire [7:0] FrameControl
// output reg [4:0] state /// liuchang: for debug
);
reg [4:0] state;
reg [9:0] cnt;
//reg [1:0] ingress_fifo_ctrl_pipe = 2'b00;
reg ingress_fifo_wren_pipe;
/// liuchang
reg [10:0] mem_dma_size_fifo_r;
reg [27:6] mem_dest_addr_fifo_r;
/// Jiansong
reg [127:0] TX_des_1;
reg [127:0] TX_des_2;
/// Jiansong: parse TX descriptor
assign SourceAddr_L[31:0] = TX_des_1[95:64];
assign SourceAddr_H[31:0] = TX_des_1[127:96];
assign DestAddr[31:0] = TX_des_2[31:0];
assign FrameSize[23:0] = TX_des_2[87:64];
assign FrameControl[7:0] = TX_des_2[95:88];
/// Jiansong: check own bit?
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// Jiansong: data fifo empty pipeline
reg data_fifo_status_r;
always@(posedge clk) data_fifo_status_r <= data_fifo_status;
localparam IDLE = 5'b00000;
localparam WREQ = 5'b00001;
localparam WDATA2 = 5'b00010;
localparam WDONE = 5'b00011;
localparam MREQ = 5'b00100;
localparam MREQ2 = 5'b00101;
localparam MREQ_WAIT = 5'b00110; /// liuchang
/// Jiansong:
localparam PARSE_TX_DES = 5'b01000;
localparam READ_TX_DES_1 = 5'b10000;
localparam READ_TX_DES_2 = 5'b11000;
//This state machine block waits for the xfer_trn_mem_fifo to go non-empty.
//It then performs the following steps:
// 1. read the transfer size and destination
// information out of the xfer_trn_mem_fifo
// 2. encode the transfer size info from DWORDS to the encoding used by
// dma_ddr2_if block
// 3. transfer the correct amount of data from the data_trn_mem_fifo to
// the dma_ddr2_if (ingress data fifo)
always @ (posedge clk)
begin
if(rst_reg)
begin
state <= IDLE;
ingress_xfer_size <= 3'b000;
ingress_start_addr <= 22'h000000;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b0;
mem_trn_fifo_rden <= 1'b0;
cnt <= 10'h000;
new_des_one <= 1'b0;
TX_des_1 <= 128'h00000000_00000000_00000000_00000000;
TX_des_2 <= 128'h00000000_00000000_00000000_00000000;
mem_dma_size_fifo_r <= 11'h000; /// liuchang
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
end
else
begin
case(state)
IDLE: begin
new_des_one <= 1'b0;
//wait for non-empty case and assert the read enable if so
if(~mem_trn_fifo_empty)begin
mem_trn_fifo_rden <= 1'b1;
ingress_data_req <= 1'b0;
state <= MREQ;
end else begin
state <= IDLE;
end
end
MREQ: begin //deassert the read enable
mem_trn_fifo_rden <= 1'b0;
// state <= MREQ2; /// liuchang
state <= MREQ_WAIT; /// liuchang
end
MREQ_WAIT: begin /// liuchang
mem_dma_size_fifo_r <= mem_dma_size_fifo;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo[27:6];
state <= MREQ2;
end
MREQ2:begin
if(isDes_fifo) begin /// Jiansong: parse TX des
// check whether TX descriptor data arrived in
// if (~data_fifo_status)begin
if (~data_fifo_status_r)begin
state <= PARSE_TX_DES;
data_fifo_cntrl <= 1'b1; /// read enable the 1st cycle
end else begin
state <= MREQ2;
data_fifo_cntrl <= 1'b0;
end
end else begin
state <= WREQ;
//encode the transfer size information for the dma_ddr2_if
//also load a counter with the number of 128-bit (16 byte)
//transfers it will require to fullfill the total data
/// liuchang
if(mem_dma_size_fifo_r[10]) begin
ingress_xfer_size <= 3'b110; // 4k byte
cnt <= 10'h100;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b10000000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b1000000;
end else if(mem_dma_size_fifo_r[9]) begin // 2k
ingress_xfer_size <= 3'b101;
cnt <= 10'h080;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b01000000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0100000;
end else if(mem_dma_size_fifo_r[8]) begin // 1k
ingress_xfer_size <= 3'b100;
cnt <= 10'h040;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00100000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0010000;
end else if(mem_dma_size_fifo_r[7]) begin // 512
ingress_xfer_size <= 3'b011;
cnt <= 10'h020;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00010000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0001000;
end else if(mem_dma_size_fifo_r[6]) begin // 256
ingress_xfer_size <= 3'b010;
cnt <= 10'h010;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00001000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000100;
end else if(mem_dma_size_fifo_r[5]) begin // 128
ingress_xfer_size <= 3'b001;
cnt <= 10'h008;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000100000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000010;
end else if(mem_dma_size_fifo_r[4]) begin // 64 byte
ingress_xfer_size <= 3'b000;
cnt <= 10'h004;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000010000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000001;
end
/// liuchang
/*
case(mem_dma_size_fifo)
11'b00000010000: begin //64 byte
ingress_xfer_size <= 3'b000;
//64 bytes / 16 byte/xfer = 4 xfers
cnt <= 10'h004;
end
11'b00000100000: begin //128
ingress_xfer_size <= 3'b001;
cnt <= 10'h008;
end
11'b00001000000: begin //256
ingress_xfer_size <= 3'b010;
cnt <= 10'h010;
end
11'b00010000000: begin //512
ingress_xfer_size <= 3'b011;
cnt <= 10'h020;
end
11'b00100000000: begin //1k
ingress_xfer_size <= 3'b100;
cnt <= 10'h040;
end
11'b01000000000: begin //2k
ingress_xfer_size <= 3'b101;
cnt <= 10'h080;
end
11'b10000000000: begin //4k
ingress_xfer_size <= 3'b110;
cnt <= 10'h100;
end
endcase
*/
ingress_start_addr[27:6] <= mem_dest_addr_fifo_r[27:6];
ingress_data_req <= 1'b1;//request access to ingress fifo
end
end
/// Jiansong: parse TX des
PARSE_TX_DES: begin
state <= READ_TX_DES_1;
data_fifo_cntrl <= 1'b1; /// read enable the 2nd cycle
end
READ_TX_DES_1: begin
state <= READ_TX_DES_2;
data_fifo_cntrl <= 1'b0;
/// read data, 1st cycle
TX_des_2[127:0] <= data_fifo_data[127:0];
new_des_one <= 1'b0;
end
READ_TX_DES_2: begin
state <= IDLE; /// Jiansong: possible timing problem here
/// read data, 2nd cycle
TX_des_2[127:0] <= data_fifo_data[127:0];
TX_des_1[127:0] <= TX_des_2[127:0];
new_des_one <= 1'b1;
end
WREQ: begin /// Jiansong: data should be already in data_trn_mem_fifo
if(ingress_data_ack) begin//wait for a grant from the dma_ddr2_if
state <= WDATA2;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b1;
end else begin
state <= WREQ;
end
end
WDATA2: begin
//keep data_fifo_cntrl asserted until cnt is 1 - then deassert
//and finish
if(cnt == 10'h001)begin
state <= WDONE;
data_fifo_cntrl <= 1'b0;
end else begin
cnt <= cnt - 1'b1;
data_fifo_cntrl <= 1'b1;
state <= WDATA2;
end
end
WDONE: begin
// state <= IDLE; /// liuchang
if(mem_dma_size_fifo_r[10:4] == 7'h00) /// liuchang
state <= IDLE;
else
state <= MREQ2;
end
default:begin
state <= IDLE;
ingress_xfer_size <= 3'b000;
ingress_start_addr <= 22'h000000;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b0;
mem_trn_fifo_rden <= 1'b0;
cnt <= 10'h000;
mem_dma_size_fifo_r <= 11'h000; /// liuchang
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
end
endcase
end
end
/// Jiansong: timing ok? all driven by the same clk
//data_fifo_cntrl is used as both a read enable to the data_trn_mem_fifo and
//a write enable to the ingress fifo (in dma_ddr2_if). The write enable
//needs to be pipelined by two clocks so that it is synched with the
//ingress_data (normally it would only need one pipeline register but since
//ingress_data is pipelined, it requires two.
always@(posedge clk) begin // Jiansong: add logic to prevent TX des write into DDR
// ingress_fifo_ctrl_pipe[1:0] <= {1'b0,(data_fifo_cntrl&(~isDes_fifo))};//1st pipeline
// ingress_fifo_ctrl[1:0] <= ingress_fifo_ctrl_pipe[1:0]; //2nd pipeline
ingress_fifo_wren_pipe <= data_fifo_cntrl&(~isDes_fifo); //1st pipeline
ingress_fifo_wren <= ingress_fifo_wren_pipe; //2nd pipeline
ingress_data[127:0] <= data_fifo_data[127:0]; //pipelined data
end
endmodule
|
/*
* schoolMIPS - small MIPS CPU for "Young Russian Chip Architects"
* summer school ( [email protected] )
*
* originally based on Sarah L. Harris MIPS CPU
*
* Copyright(c) 2017 Stanislav Zhelnio
* Alexander Romanov
*/
`include "sm_cpu.vh"
module sm_cpu
(
input clk, // clock
input rst_n, // reset
input [ 4:0] regAddr, // debug access reg address
output [31:0] regData, // debug access reg data
output [31:0] imAddr, // instruction memory address
input [31:0] imData, // instruction memory data
input [7:0] exData // External data from GPIOs
);
//control wires
wire pcSrc;
wire regDst;
wire regWrite;
wire aluSrc;
wire aluZero;
wire [ 3:0] aluControl;
wire exControl;
//program counter
wire [31:0] pc;
wire [31:0] pcBranch;
wire [31:0] pcNext = pc + 1;
wire [31:0] pc_new = ~pcSrc ? pcNext : pcBranch;
sm_register r_pc(clk, rst_n, pc_new, pc);
//program memory access
assign imAddr = pc;
wire [31:0] instr = imData;
//debug register access
wire [31:0] rd0;
assign regData = (regAddr != 0) ? rd0 : pc;
//register file
wire [ 4:0] a3 = regDst ? instr[15:11] : instr[20:16];
wire [31:0] rd1;
wire [31:0] rd2;
wire [31:0] wd3;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instr[25:21] ),
.a2 ( instr[20:16] ),
.a3 ( a3 ),
.rd0 ( rd0 ),
.rd1 ( rd1 ),
.rd2 ( rd2 ),
.wd3 ( wd3 ),
.we3 ( regWrite )
);
//sign extension
wire signExtend;
wire [31:0] signImm = (exControl) ? {{24 { exData[7] }}, exData[7:0] }
: (~signExtend) ? { {16 { instr[15] }}, instr[15:0] } : { {16 {1'b0}}, instr[15:0] };
assign pcBranch = pcNext + signImm;
//alu
wire [31:0] srcB = aluSrc ? signImm : rd2;
sm_alu alu
(
.srcA ( (exControl) ? 32'b0: rd1 ),
.srcB ( srcB ),
.oper ( aluControl ),
.shift ( instr[10:6 ] ),
.sign ( aluZero ),
.result ( wd3 )
);
//control
sm_control sm_control
(
.cmdOper ( instr[31:26] ),
.cmdFunk ( instr[ 5:0 ] ),
.aluZero ( aluZero ),
.pcSrc ( pcSrc ),
.regDst ( regDst ),
.regWrite ( regWrite ),
.aluSrc ( aluSrc ),
.aluControl ( aluControl ),
.exControl ( exControl )
);
endmodule
module sm_control
(
input [5:0] cmdOper,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output reg regDst,
output reg regWrite,
output reg aluSrc,
output reg [3:0] aluControl,
output reg exControl
);
reg branch;
reg condZero;
assign pcSrc = branch & (aluZero == condZero);
always @ (*) begin
branch = 1'b0;
condZero = 1'b0;
regDst = 1'b0;
regWrite = 1'b0;
aluSrc = 1'b0;
aluControl = `ALU_ADD;
exControl = 1'b0;
casez( {cmdOper,cmdFunk} )
default : ;
{ `C_SPEC, `F_ADDU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD; end
{ `C_SPEC, `F_OR } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR; end
{ `C_SPEC, `F_AND } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_AND; end
{ `C_SPEC, `F_SRL } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL; end
{ `C_SPEC, `F_SLTU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
{ `C_SPEC, `F_SUBU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
{ `C_SPEC, `F_SRLV } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRLV; end
{ `C_ADDIU, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; end
{ `C_LUI, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI; end
{ `C_BEQ, `F_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BNE, `F_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BGEZ, `F_ANY } : begin branch = 1'b1; aluControl = `ALU_NOTNEG; end
{ `C_EXT, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; exControl = 1'b1; aluControl = `ALU_ADD; end
endcase
end
endmodule
module sm_alu
(
input [31:0] srcA,
input [31:0] srcB,
input [ 3:0] oper,
input [ 4:0] shift,
output sign,
output reg [31:0] result
);
always @ (*) begin
case (oper)
default : result = srcA + srcB;
`ALU_ADD : result = srcA + srcB;
`ALU_OR : result = srcA | srcB;
`ALU_AND : result = srcA & srcB;
`ALU_LUI : result = (srcB << 16);
`ALU_SRL : result = srcB >> shift;
`ALU_SRLV : result = srcB >> srcA;
`ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
`ALU_SUBU : result = srcA - srcB;
`ALU_NOR : result = ~(srcA | srcB);
`ALU_NOTNEG : result = srcB >=0;
endcase
end
assign sign = (result == 0);
endmodule
module sm_register_file
(
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf [31:0];
assign rd0 = (a0 != 0) ? rf [a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf [a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf [a2] : 32'b0;
always @ (posedge clk)
if(we3) rf [a3] <= wd3;
endmodule |
timeunit 10us;
timeprecision 10us;
module fast_g (out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast_g
`timescale 100us / 1us
// These will be ignored since a `timescale was already given.
timeunit 10us;
timeprecision 10us;
module slow (out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // slow
module fast (out);
timeunit 10us;
timeprecision 1us;
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast
module saf(out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // saf
`timescale 1us / 1us
module main;
reg pass;
wire slow, fast, fast_g, saf;
slow m1 (slow);
fast_g m2 (fast_g);
fast m3 (fast);
saf m4 (saf);
initial begin
pass = 1'b1;
#9;
if (slow !== 1'b0) begin
$display("FAILED: slow at 9us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 9us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b0) begin
$display("FAILED: fast at 9us, expected 1'b0, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b0) begin
$display("FAILED: fast_g at 9us, expected 1'b0, got %b.", fast_g);
pass = 1'b0;
end
#2 // 11us
if (slow !== 1'b0) begin
$display("FAILED: slow at 11us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 11us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 11us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 11us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
#88 // 99 us
if (slow !== 1'b0) begin
$display("FAILED: slow at 99us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 99us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 99us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 99us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
#2 // 101 us
if (slow !== 1'b1) begin
$display("FAILED: slow at 101us, expected 1'b1, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b1) begin
$display("FAILED: saf at 101us, expected 1'b1, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 101us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 101us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
if (pass) $display("PASSED");
end // initial begin
endmodule // main
|
`timescale 1us/100ns
module testbench ();
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
reg [0:0] clk = 0;
reg [0:0] resetn = 0;
initial begin
// pull reset if available
resetn = 0;
repeat(10) #1 clk = !clk;
// release reset if available
resetn = 1;
forever #1 clk = !clk;
end
reg [0:0] SPI_CS = 1;
reg [0:0] SPI_CLK = 0;
reg [0:0] SPI_MOSI = 0;
wire [0:0] first_byte;
reg [0:0] first_byte_expected;
wire [7:0] read_value;
reg [7:0] read_value_expected;
wire [0:0] done;
localparam FCLK = 100;
localparam BAUDRATE = 15;
localparam HALFBITTIME = FCLK / BAUDRATE / 2;
task send_byte;
input [7:0] byte;
input [3:0] bitcount;
integer i;
// for(i=0; i<8; i=i+1)
begin
for(i=0; i<bitcount; i=i+1) begin
SPI_MOSI <= byte[7-i];
#HALFBITTIME SPI_CLK <= 1;
#HALFBITTIME SPI_CLK <= 0;
end
SPI_MOSI <= 0;
#HALFBITTIME;
end
endtask
// CPOL == 0: clock state while idle is low ("inactive")
// CPOL == 1: clock state while idle is high ("inactive")
parameter CPOL = 0;
// CPHA == 0: write on clock deactivation, sample on clock activation
// CPHA == 1: write on clock activation, sample on clock deactivation
parameter CPHA = 0;
parameter LSBFIRST = 1;
spi_slave #(.CPOL (CPOL),
.CPHA (CPHA),
.LSBFIRST (LSBFIRST),
.TIMEOUT__NOT_CS(0),
.TIMEOUT_CYCLES (1))
DUT (.clk (clk),
.resetn (resetn),
.spi_clk (SPI_CLK),
.spi_mosi (SPI_MOSI),
.spi_cs (SPI_CS),
.read_value (read_value),
.done (done),
.timeout_expired (),
.first_byte (first_byte),
.debug_info ()
);
initial begin
SPI_CS = 1;
#20 SPI_CS <= 0;
read_value_expected <= 8'h81; first_byte_expected <= 1; #1 send_byte(read_value_expected, 8);
read_value_expected <= "@"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
read_value_expected <= "A"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
read_value_expected <= "B"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
read_value_expected <= "C"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
#1 SPI_CS <= 1;
// this is an incomplete transmission
// "done" should not get 1, if it gets 1, the test should fail, since MOSI was inverted
#20 SPI_CS <= 0;
read_value_expected <= "0"; first_byte_expected <= 1; #1 send_byte(~read_value_expected, 7);
#1 SPI_CS <= 1;
// the incomplete transmission shall not have any consequences for following receptions
#20 SPI_CS <= 0;
read_value_expected <= "0"; first_byte_expected <= 1; #1 send_byte(read_value_expected, 8);
read_value_expected <= "-"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
#1 SPI_CS <= 1;
#100 $finish;
end
always @(posedge done) begin
if (read_value == read_value_expected)
$display("pass: value: %c, is_first_byte: %b", read_value, first_byte);
else
$display("fail: value(expected): %c / 0x%X (%c / 0x%X), first_byte: %b(%b)", read_value, read_value, read_value_expected, read_value_expected, first_byte, first_byte_expected);
end
endmodule
|
// cog_ram
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ram
(
input clk,
input ena,
input w,
input [8:0] a,
input [31:0] d,
output reg [31:0] q
);
// 512 x 32 ram
reg [511:0] [31:0] r;
always @(posedge clk)
begin
if (ena && w)
r[a] <= d;
if (ena)
q <= r[a];
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
`ifndef verilator // Hacky array subscripting
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
wire bitout = (^ onebit) ^ (^ allbits);
endmodule
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_TB_V
`define SKY130_FD_SC_LS__NAND2_TB_V
/**
* nand2: 2-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_TB_V
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: pcie_4243_hip_s4gx_gen2_x8_128_serdes.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 hip_enable="true" input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=8 number_of_quads=2 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=34 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x8" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=0 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x8" tx_channel_width=8 tx_clkout_width=8 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=0 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked pll_powerdown powerdn rateswitch rateswitchbaseclock reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_pll_locked rx_signaldetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
//VERSION_BEGIN 10.1SP1 cbx_alt4gxb 2011:01:19:21:23:40:SJ cbx_mgl 2011:01:19:21:24:50:SJ cbx_tgx 2011:01:19:21:23:40:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 20 stratixiv_hssi_calibration_block 2 stratixiv_hssi_clock_divider 2 stratixiv_hssi_cmu 2 stratixiv_hssi_pll 9 stratixiv_hssi_rx_pcs 8 stratixiv_hssi_rx_pma 8 stratixiv_hssi_tx_pcs 8 stratixiv_hssi_tx_pma 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa
(
cal_blk_clk,
coreclkout,
fixedclk,
gxb_powerdown,
hip_tx_clkout,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_inclk,
pll_locked,
pll_powerdown,
powerdn,
rateswitch,
rateswitchbaseclock,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_elecidleinfersel,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_signaldetect,
rx_syncstatus,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
output [0:0] coreclkout;
input fixedclk;
input [0:0] gxb_powerdown;
output [7:0] hip_tx_clkout;
input [7:0] pipe8b10binvpolarity;
output [7:0] pipedatavalid;
output [7:0] pipeelecidle;
output [7:0] pipephydonestatus;
output [23:0] pipestatus;
input pll_inclk;
output [0:0] pll_locked;
input [0:0] pll_powerdown;
input [15:0] powerdn;
input [0:0] rateswitch;
output [1:0] rateswitchbaseclock;
input reconfig_clk;
output [33:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [7:0] rx_cruclk;
output [7:0] rx_ctrldetect;
input [7:0] rx_datain;
output [63:0] rx_dataout;
input [0:0] rx_digitalreset;
input [23:0] rx_elecidleinfersel;
output [7:0] rx_freqlocked;
output [7:0] rx_patterndetect;
output [7:0] rx_pll_locked;
output [7:0] rx_signaldetect;
output [7:0] rx_syncstatus;
input [7:0] tx_ctrlenable;
input [63:0] tx_datain;
output [7:0] tx_dataout;
input [7:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [7:0] tx_forcedispcompliance;
input [7:0] tx_forceelecidle;
input [7:0] tx_pipedeemph;
input [23:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri0 [0:0] gxb_powerdown;
tri0 [7:0] pipe8b10binvpolarity;
tri0 pll_inclk;
tri0 [0:0] pll_powerdown;
tri0 [15:0] powerdn;
tri0 [0:0] rateswitch;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [7:0] rx_cruclk;
tri0 [0:0] rx_digitalreset;
tri0 [23:0] rx_elecidleinfersel;
tri0 [7:0] tx_ctrlenable;
tri0 [63:0] tx_datain;
tri0 [7:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [7:0] tx_forcedispcompliance;
tri0 [7:0] tx_forceelecidle;
tri0 [7:0] tx_pipedeemph;
tri0 [23:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
reg fixedclk_div0quad0c;
wire wire_fixedclk_div0quad0c_clk;
reg fixedclk_div0quad1c;
wire wire_fixedclk_div0quad1c_clk;
reg fixedclk_div1quad0c;
wire wire_fixedclk_div1quad0c_clk;
reg fixedclk_div1quad1c;
wire wire_fixedclk_div1quad1c_clk;
reg fixedclk_div2quad0c;
wire wire_fixedclk_div2quad0c_clk;
reg fixedclk_div2quad1c;
wire wire_fixedclk_div2quad1c_clk;
reg fixedclk_div3quad0c;
wire wire_fixedclk_div3quad0c_clk;
reg fixedclk_div3quad1c;
wire wire_fixedclk_div3quad1c_clk;
reg fixedclk_div4quad0c;
wire wire_fixedclk_div4quad0c_clk;
reg fixedclk_div4quad1c;
wire wire_fixedclk_div4quad1c_clk;
reg fixedclk_div5quad0c;
wire wire_fixedclk_div5quad0c_clk;
reg fixedclk_div5quad1c;
wire wire_fixedclk_div5quad1c_clk;
reg [1:0] reconfig_togxb_busy_reg;
wire [2:0] wire_rx_digitalreset_reg0c_d;
reg [2:0] rx_digitalreset_reg0c;
wire [2:0] wire_rx_digitalreset_reg0c_clk;
wire [2:0] wire_tx_digitalreset_reg0c_d;
reg [2:0] tx_digitalreset_reg0c;
wire [2:0] wire_tx_digitalreset_reg0c_clk;
wire wire_cal_blk0_nonusertocmu;
wire wire_cal_blk1_nonusertocmu;
wire [1:0] wire_central_clk_div0_analogfastrefclkout;
wire [1:0] wire_central_clk_div0_analogrefclkout;
wire wire_central_clk_div0_analogrefclkpulse;
wire wire_central_clk_div0_coreclkout;
wire [99:0] wire_central_clk_div0_dprioout;
wire wire_central_clk_div0_rateswitchbaseclock;
wire wire_central_clk_div0_rateswitchdone;
wire wire_central_clk_div0_refclkout;
wire [1:0] wire_central_clk_div1_analogfastrefclkout;
wire [1:0] wire_central_clk_div1_analogrefclkout;
wire wire_central_clk_div1_analogrefclkpulse;
wire wire_central_clk_div1_coreclkout;
wire [99:0] wire_central_clk_div1_dprioout;
wire wire_central_clk_div1_rateswitchbaseclock;
wire wire_central_clk_div1_rateswitchdone;
wire wire_central_clk_div1_refclkout;
wire wire_cent_unit0_autospdx4configsel;
wire wire_cent_unit0_autospdx4rateswitchout;
wire wire_cent_unit0_autospdx4spdchg;
wire [1:0] wire_cent_unit0_clkdivpowerdn;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_phfifiox4ptrsreset;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire wire_cent_unit0_rxphfifox4byteselout;
wire wire_cent_unit0_rxphfifox4rdenableout;
wire wire_cent_unit0_rxphfifox4wrclkout;
wire wire_cent_unit0_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire wire_cent_unit0_txphfifox4byteselout;
wire wire_cent_unit0_txphfifox4rdclkout;
wire wire_cent_unit0_txphfifox4rdenableout;
wire wire_cent_unit0_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire wire_cent_unit1_autospdx4configsel;
wire wire_cent_unit1_autospdx4rateswitchout;
wire wire_cent_unit1_autospdx4spdchg;
wire [1:0] wire_cent_unit1_clkdivpowerdn;
wire [599:0] wire_cent_unit1_cmudividerdprioout;
wire [1799:0] wire_cent_unit1_cmuplldprioout;
wire wire_cent_unit1_dpriodisableout;
wire wire_cent_unit1_dprioout;
wire wire_cent_unit1_phfifiox4ptrsreset;
wire [1:0] wire_cent_unit1_pllpowerdn;
wire [1:0] wire_cent_unit1_pllresetout;
wire wire_cent_unit1_quadresetout;
wire [5:0] wire_cent_unit1_rxanalogresetout;
wire [5:0] wire_cent_unit1_rxcrupowerdown;
wire [5:0] wire_cent_unit1_rxcruresetout;
wire [3:0] wire_cent_unit1_rxdigitalresetout;
wire [5:0] wire_cent_unit1_rxibpowerdown;
wire [1599:0] wire_cent_unit1_rxpcsdprioout;
wire wire_cent_unit1_rxphfifox4byteselout;
wire wire_cent_unit1_rxphfifox4rdenableout;
wire wire_cent_unit1_rxphfifox4wrclkout;
wire wire_cent_unit1_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit1_rxpmadprioout;
wire [5:0] wire_cent_unit1_txanalogresetout;
wire [3:0] wire_cent_unit1_txctrlout;
wire [31:0] wire_cent_unit1_txdataout;
wire [5:0] wire_cent_unit1_txdetectrxpowerdown;
wire [3:0] wire_cent_unit1_txdigitalresetout;
wire [5:0] wire_cent_unit1_txobpowerdown;
wire [599:0] wire_cent_unit1_txpcsdprioout;
wire wire_cent_unit1_txphfifox4byteselout;
wire wire_cent_unit1_txphfifox4rdclkout;
wire wire_cent_unit1_txphfifox4rdenableout;
wire wire_cent_unit1_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit1_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll1_clk;
wire [1:0] wire_rx_cdr_pll1_dataout;
wire [299:0] wire_rx_cdr_pll1_dprioout;
wire wire_rx_cdr_pll1_freqlocked;
wire wire_rx_cdr_pll1_locked;
wire wire_rx_cdr_pll1_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll2_clk;
wire [1:0] wire_rx_cdr_pll2_dataout;
wire [299:0] wire_rx_cdr_pll2_dprioout;
wire wire_rx_cdr_pll2_freqlocked;
wire wire_rx_cdr_pll2_locked;
wire wire_rx_cdr_pll2_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll3_clk;
wire [1:0] wire_rx_cdr_pll3_dataout;
wire [299:0] wire_rx_cdr_pll3_dprioout;
wire wire_rx_cdr_pll3_freqlocked;
wire wire_rx_cdr_pll3_locked;
wire wire_rx_cdr_pll3_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll4_clk;
wire [1:0] wire_rx_cdr_pll4_dataout;
wire [299:0] wire_rx_cdr_pll4_dprioout;
wire wire_rx_cdr_pll4_freqlocked;
wire wire_rx_cdr_pll4_locked;
wire wire_rx_cdr_pll4_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll5_clk;
wire [1:0] wire_rx_cdr_pll5_dataout;
wire [299:0] wire_rx_cdr_pll5_dprioout;
wire wire_rx_cdr_pll5_freqlocked;
wire wire_rx_cdr_pll5_locked;
wire wire_rx_cdr_pll5_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll6_clk;
wire [1:0] wire_rx_cdr_pll6_dataout;
wire [299:0] wire_rx_cdr_pll6_dprioout;
wire wire_rx_cdr_pll6_freqlocked;
wire wire_rx_cdr_pll6_locked;
wire wire_rx_cdr_pll6_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll7_clk;
wire [1:0] wire_rx_cdr_pll7_dataout;
wire [299:0] wire_rx_cdr_pll7_dprioout;
wire wire_rx_cdr_pll7_freqlocked;
wire wire_rx_cdr_pll7_locked;
wire wire_rx_cdr_pll7_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_autospdrateswitchout;
wire wire_receive_pcs0_autospdspdchgout;
wire wire_receive_pcs0_cdrctrlearlyeios;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_coreclkout;
wire [399:0] wire_receive_pcs0_dprioout;
wire [8:0] wire_receive_pcs0_hipdataout;
wire wire_receive_pcs0_hipdatavalid;
wire wire_receive_pcs0_hipelecidle;
wire wire_receive_pcs0_hipphydonestatus;
wire [2:0] wire_receive_pcs0_hipstatus;
wire wire_receive_pcs0_iqpphfifobyteselout;
wire wire_receive_pcs0_iqpphfifoptrsresetout;
wire wire_receive_pcs0_iqpphfifordenableout;
wire wire_receive_pcs0_iqpphfifowrclkout;
wire wire_receive_pcs0_iqpphfifowrenableout;
wire wire_receive_pcs0_phfifobyteserdisableout;
wire wire_receive_pcs0_phfifoptrsresetout;
wire wire_receive_pcs0_phfifordenableout;
wire wire_receive_pcs0_phfiforesetout;
wire wire_receive_pcs0_phfifowrdisableout;
wire wire_receive_pcs0_pipestatetransdoneout;
wire wire_receive_pcs0_rateswitchout;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire wire_receive_pcs0_signaldetect;
wire wire_receive_pcs1_autospdrateswitchout;
wire wire_receive_pcs1_autospdspdchgout;
wire wire_receive_pcs1_cdrctrlearlyeios;
wire wire_receive_pcs1_cdrctrllocktorefclkout;
wire wire_receive_pcs1_coreclkout;
wire [399:0] wire_receive_pcs1_dprioout;
wire [8:0] wire_receive_pcs1_hipdataout;
wire wire_receive_pcs1_hipdatavalid;
wire wire_receive_pcs1_hipelecidle;
wire wire_receive_pcs1_hipphydonestatus;
wire [2:0] wire_receive_pcs1_hipstatus;
wire wire_receive_pcs1_iqpphfifobyteselout;
wire wire_receive_pcs1_iqpphfifoptrsresetout;
wire wire_receive_pcs1_iqpphfifordenableout;
wire wire_receive_pcs1_iqpphfifowrclkout;
wire wire_receive_pcs1_iqpphfifowrenableout;
wire wire_receive_pcs1_phfifobyteserdisableout;
wire wire_receive_pcs1_phfifoptrsresetout;
wire wire_receive_pcs1_phfifordenableout;
wire wire_receive_pcs1_phfiforesetout;
wire wire_receive_pcs1_phfifowrdisableout;
wire wire_receive_pcs1_pipestatetransdoneout;
wire wire_receive_pcs1_rateswitchout;
wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
wire wire_receive_pcs1_signaldetect;
wire wire_receive_pcs2_autospdrateswitchout;
wire wire_receive_pcs2_autospdspdchgout;
wire wire_receive_pcs2_cdrctrlearlyeios;
wire wire_receive_pcs2_cdrctrllocktorefclkout;
wire wire_receive_pcs2_coreclkout;
wire [399:0] wire_receive_pcs2_dprioout;
wire [8:0] wire_receive_pcs2_hipdataout;
wire wire_receive_pcs2_hipdatavalid;
wire wire_receive_pcs2_hipelecidle;
wire wire_receive_pcs2_hipphydonestatus;
wire [2:0] wire_receive_pcs2_hipstatus;
wire wire_receive_pcs2_iqpphfifobyteselout;
wire wire_receive_pcs2_iqpphfifoptrsresetout;
wire wire_receive_pcs2_iqpphfifordenableout;
wire wire_receive_pcs2_iqpphfifowrclkout;
wire wire_receive_pcs2_iqpphfifowrenableout;
wire wire_receive_pcs2_phfifobyteserdisableout;
wire wire_receive_pcs2_phfifoptrsresetout;
wire wire_receive_pcs2_phfifordenableout;
wire wire_receive_pcs2_phfiforesetout;
wire wire_receive_pcs2_phfifowrdisableout;
wire wire_receive_pcs2_pipestatetransdoneout;
wire wire_receive_pcs2_rateswitchout;
wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
wire wire_receive_pcs2_signaldetect;
wire wire_receive_pcs3_autospdrateswitchout;
wire wire_receive_pcs3_autospdspdchgout;
wire wire_receive_pcs3_cdrctrlearlyeios;
wire wire_receive_pcs3_cdrctrllocktorefclkout;
wire wire_receive_pcs3_coreclkout;
wire [399:0] wire_receive_pcs3_dprioout;
wire [8:0] wire_receive_pcs3_hipdataout;
wire wire_receive_pcs3_hipdatavalid;
wire wire_receive_pcs3_hipelecidle;
wire wire_receive_pcs3_hipphydonestatus;
wire [2:0] wire_receive_pcs3_hipstatus;
wire wire_receive_pcs3_iqpphfifobyteselout;
wire wire_receive_pcs3_iqpphfifoptrsresetout;
wire wire_receive_pcs3_iqpphfifordenableout;
wire wire_receive_pcs3_iqpphfifowrclkout;
wire wire_receive_pcs3_iqpphfifowrenableout;
wire wire_receive_pcs3_phfifobyteserdisableout;
wire wire_receive_pcs3_phfifoptrsresetout;
wire wire_receive_pcs3_phfifordenableout;
wire wire_receive_pcs3_phfiforesetout;
wire wire_receive_pcs3_phfifowrdisableout;
wire wire_receive_pcs3_pipestatetransdoneout;
wire wire_receive_pcs3_rateswitchout;
wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
wire wire_receive_pcs3_signaldetect;
wire wire_receive_pcs4_autospdrateswitchout;
wire wire_receive_pcs4_autospdspdchgout;
wire wire_receive_pcs4_cdrctrlearlyeios;
wire wire_receive_pcs4_cdrctrllocktorefclkout;
wire wire_receive_pcs4_coreclkout;
wire [399:0] wire_receive_pcs4_dprioout;
wire [8:0] wire_receive_pcs4_hipdataout;
wire wire_receive_pcs4_hipdatavalid;
wire wire_receive_pcs4_hipelecidle;
wire wire_receive_pcs4_hipphydonestatus;
wire [2:0] wire_receive_pcs4_hipstatus;
wire wire_receive_pcs4_iqpphfifobyteselout;
wire wire_receive_pcs4_iqpphfifoptrsresetout;
wire wire_receive_pcs4_iqpphfifordenableout;
wire wire_receive_pcs4_iqpphfifowrclkout;
wire wire_receive_pcs4_iqpphfifowrenableout;
wire wire_receive_pcs4_phfifobyteserdisableout;
wire wire_receive_pcs4_phfifoptrsresetout;
wire wire_receive_pcs4_phfifordenableout;
wire wire_receive_pcs4_phfiforesetout;
wire wire_receive_pcs4_phfifowrdisableout;
wire wire_receive_pcs4_pipestatetransdoneout;
wire wire_receive_pcs4_rateswitchout;
wire [19:0] wire_receive_pcs4_revparallelfdbkdata;
wire wire_receive_pcs4_signaldetect;
wire wire_receive_pcs5_autospdrateswitchout;
wire wire_receive_pcs5_autospdspdchgout;
wire wire_receive_pcs5_cdrctrlearlyeios;
wire wire_receive_pcs5_cdrctrllocktorefclkout;
wire wire_receive_pcs5_coreclkout;
wire [399:0] wire_receive_pcs5_dprioout;
wire [8:0] wire_receive_pcs5_hipdataout;
wire wire_receive_pcs5_hipdatavalid;
wire wire_receive_pcs5_hipelecidle;
wire wire_receive_pcs5_hipphydonestatus;
wire [2:0] wire_receive_pcs5_hipstatus;
wire wire_receive_pcs5_iqpphfifobyteselout;
wire wire_receive_pcs5_iqpphfifoptrsresetout;
wire wire_receive_pcs5_iqpphfifordenableout;
wire wire_receive_pcs5_iqpphfifowrclkout;
wire wire_receive_pcs5_iqpphfifowrenableout;
wire wire_receive_pcs5_phfifobyteserdisableout;
wire wire_receive_pcs5_phfifoptrsresetout;
wire wire_receive_pcs5_phfifordenableout;
wire wire_receive_pcs5_phfiforesetout;
wire wire_receive_pcs5_phfifowrdisableout;
wire wire_receive_pcs5_pipestatetransdoneout;
wire wire_receive_pcs5_rateswitchout;
wire [19:0] wire_receive_pcs5_revparallelfdbkdata;
wire wire_receive_pcs5_signaldetect;
wire wire_receive_pcs6_autospdrateswitchout;
wire wire_receive_pcs6_autospdspdchgout;
wire wire_receive_pcs6_cdrctrlearlyeios;
wire wire_receive_pcs6_cdrctrllocktorefclkout;
wire wire_receive_pcs6_coreclkout;
wire [399:0] wire_receive_pcs6_dprioout;
wire [8:0] wire_receive_pcs6_hipdataout;
wire wire_receive_pcs6_hipdatavalid;
wire wire_receive_pcs6_hipelecidle;
wire wire_receive_pcs6_hipphydonestatus;
wire [2:0] wire_receive_pcs6_hipstatus;
wire wire_receive_pcs6_iqpphfifobyteselout;
wire wire_receive_pcs6_iqpphfifoptrsresetout;
wire wire_receive_pcs6_iqpphfifordenableout;
wire wire_receive_pcs6_iqpphfifowrclkout;
wire wire_receive_pcs6_iqpphfifowrenableout;
wire wire_receive_pcs6_phfifobyteserdisableout;
wire wire_receive_pcs6_phfifoptrsresetout;
wire wire_receive_pcs6_phfifordenableout;
wire wire_receive_pcs6_phfiforesetout;
wire wire_receive_pcs6_phfifowrdisableout;
wire wire_receive_pcs6_pipestatetransdoneout;
wire wire_receive_pcs6_rateswitchout;
wire [19:0] wire_receive_pcs6_revparallelfdbkdata;
wire wire_receive_pcs6_signaldetect;
wire wire_receive_pcs7_autospdrateswitchout;
wire wire_receive_pcs7_autospdspdchgout;
wire wire_receive_pcs7_cdrctrlearlyeios;
wire wire_receive_pcs7_cdrctrllocktorefclkout;
wire wire_receive_pcs7_coreclkout;
wire [399:0] wire_receive_pcs7_dprioout;
wire [8:0] wire_receive_pcs7_hipdataout;
wire wire_receive_pcs7_hipdatavalid;
wire wire_receive_pcs7_hipelecidle;
wire wire_receive_pcs7_hipphydonestatus;
wire [2:0] wire_receive_pcs7_hipstatus;
wire wire_receive_pcs7_iqpphfifobyteselout;
wire wire_receive_pcs7_iqpphfifoptrsresetout;
wire wire_receive_pcs7_iqpphfifordenableout;
wire wire_receive_pcs7_iqpphfifowrclkout;
wire wire_receive_pcs7_iqpphfifowrenableout;
wire wire_receive_pcs7_phfifobyteserdisableout;
wire wire_receive_pcs7_phfifoptrsresetout;
wire wire_receive_pcs7_phfifordenableout;
wire wire_receive_pcs7_phfiforesetout;
wire wire_receive_pcs7_phfifowrdisableout;
wire wire_receive_pcs7_pipestatetransdoneout;
wire wire_receive_pcs7_rateswitchout;
wire [19:0] wire_receive_pcs7_revparallelfdbkdata;
wire wire_receive_pcs7_signaldetect;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire [7:0] wire_receive_pma1_analogtestbus;
wire wire_receive_pma1_clockout;
wire wire_receive_pma1_dataout;
wire [299:0] wire_receive_pma1_dprioout;
wire wire_receive_pma1_locktorefout;
wire [63:0] wire_receive_pma1_recoverdataout;
wire wire_receive_pma1_signaldetect;
wire [7:0] wire_receive_pma2_analogtestbus;
wire wire_receive_pma2_clockout;
wire wire_receive_pma2_dataout;
wire [299:0] wire_receive_pma2_dprioout;
wire wire_receive_pma2_locktorefout;
wire [63:0] wire_receive_pma2_recoverdataout;
wire wire_receive_pma2_signaldetect;
wire [7:0] wire_receive_pma3_analogtestbus;
wire wire_receive_pma3_clockout;
wire wire_receive_pma3_dataout;
wire [299:0] wire_receive_pma3_dprioout;
wire wire_receive_pma3_locktorefout;
wire [63:0] wire_receive_pma3_recoverdataout;
wire wire_receive_pma3_signaldetect;
wire [7:0] wire_receive_pma4_analogtestbus;
wire wire_receive_pma4_clockout;
wire wire_receive_pma4_dataout;
wire [299:0] wire_receive_pma4_dprioout;
wire wire_receive_pma4_locktorefout;
wire [63:0] wire_receive_pma4_recoverdataout;
wire wire_receive_pma4_signaldetect;
wire [7:0] wire_receive_pma5_analogtestbus;
wire wire_receive_pma5_clockout;
wire wire_receive_pma5_dataout;
wire [299:0] wire_receive_pma5_dprioout;
wire wire_receive_pma5_locktorefout;
wire [63:0] wire_receive_pma5_recoverdataout;
wire wire_receive_pma5_signaldetect;
wire [7:0] wire_receive_pma6_analogtestbus;
wire wire_receive_pma6_clockout;
wire wire_receive_pma6_dataout;
wire [299:0] wire_receive_pma6_dprioout;
wire wire_receive_pma6_locktorefout;
wire [63:0] wire_receive_pma6_recoverdataout;
wire wire_receive_pma6_signaldetect;
wire [7:0] wire_receive_pma7_analogtestbus;
wire wire_receive_pma7_clockout;
wire wire_receive_pma7_dataout;
wire [299:0] wire_receive_pma7_dprioout;
wire wire_receive_pma7_locktorefout;
wire [63:0] wire_receive_pma7_recoverdataout;
wire wire_receive_pma7_signaldetect;
wire wire_transmit_pcs0_coreclkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire wire_transmit_pcs0_iqpphfifobyteselout;
wire wire_transmit_pcs0_iqpphfifordclkout;
wire wire_transmit_pcs0_iqpphfifordenableout;
wire wire_transmit_pcs0_iqpphfifowrenableout;
wire wire_transmit_pcs0_phfiforddisableout;
wire wire_transmit_pcs0_phfiforesetout;
wire wire_transmit_pcs0_phfifowrenableout;
wire wire_transmit_pcs0_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pcs1_coreclkout;
wire [19:0] wire_transmit_pcs1_dataout;
wire [149:0] wire_transmit_pcs1_dprioout;
wire wire_transmit_pcs1_forceelecidleout;
wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
wire wire_transmit_pcs1_iqpphfifobyteselout;
wire wire_transmit_pcs1_iqpphfifordclkout;
wire wire_transmit_pcs1_iqpphfifordenableout;
wire wire_transmit_pcs1_iqpphfifowrenableout;
wire wire_transmit_pcs1_phfiforddisableout;
wire wire_transmit_pcs1_phfiforesetout;
wire wire_transmit_pcs1_phfifowrenableout;
wire wire_transmit_pcs1_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs1_pipepowerdownout;
wire [3:0] wire_transmit_pcs1_pipepowerstateout;
wire wire_transmit_pcs1_txdetectrx;
wire wire_transmit_pcs2_coreclkout;
wire [19:0] wire_transmit_pcs2_dataout;
wire [149:0] wire_transmit_pcs2_dprioout;
wire wire_transmit_pcs2_forceelecidleout;
wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
wire wire_transmit_pcs2_iqpphfifobyteselout;
wire wire_transmit_pcs2_iqpphfifordclkout;
wire wire_transmit_pcs2_iqpphfifordenableout;
wire wire_transmit_pcs2_iqpphfifowrenableout;
wire wire_transmit_pcs2_phfiforddisableout;
wire wire_transmit_pcs2_phfiforesetout;
wire wire_transmit_pcs2_phfifowrenableout;
wire wire_transmit_pcs2_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs2_pipepowerdownout;
wire [3:0] wire_transmit_pcs2_pipepowerstateout;
wire wire_transmit_pcs2_txdetectrx;
wire wire_transmit_pcs3_coreclkout;
wire [19:0] wire_transmit_pcs3_dataout;
wire [149:0] wire_transmit_pcs3_dprioout;
wire wire_transmit_pcs3_forceelecidleout;
wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
wire wire_transmit_pcs3_iqpphfifobyteselout;
wire wire_transmit_pcs3_iqpphfifordclkout;
wire wire_transmit_pcs3_iqpphfifordenableout;
wire wire_transmit_pcs3_iqpphfifowrenableout;
wire wire_transmit_pcs3_phfiforddisableout;
wire wire_transmit_pcs3_phfiforesetout;
wire wire_transmit_pcs3_phfifowrenableout;
wire wire_transmit_pcs3_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs3_pipepowerdownout;
wire [3:0] wire_transmit_pcs3_pipepowerstateout;
wire wire_transmit_pcs3_txdetectrx;
wire wire_transmit_pcs4_coreclkout;
wire [19:0] wire_transmit_pcs4_dataout;
wire [149:0] wire_transmit_pcs4_dprioout;
wire wire_transmit_pcs4_forceelecidleout;
wire [2:0] wire_transmit_pcs4_grayelecidleinferselout;
wire wire_transmit_pcs4_iqpphfifobyteselout;
wire wire_transmit_pcs4_iqpphfifordclkout;
wire wire_transmit_pcs4_iqpphfifordenableout;
wire wire_transmit_pcs4_iqpphfifowrenableout;
wire wire_transmit_pcs4_phfiforddisableout;
wire wire_transmit_pcs4_phfiforesetout;
wire wire_transmit_pcs4_phfifowrenableout;
wire wire_transmit_pcs4_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs4_pipepowerdownout;
wire [3:0] wire_transmit_pcs4_pipepowerstateout;
wire wire_transmit_pcs4_txdetectrx;
wire wire_transmit_pcs5_coreclkout;
wire [19:0] wire_transmit_pcs5_dataout;
wire [149:0] wire_transmit_pcs5_dprioout;
wire wire_transmit_pcs5_forceelecidleout;
wire [2:0] wire_transmit_pcs5_grayelecidleinferselout;
wire wire_transmit_pcs5_iqpphfifobyteselout;
wire wire_transmit_pcs5_iqpphfifordclkout;
wire wire_transmit_pcs5_iqpphfifordenableout;
wire wire_transmit_pcs5_iqpphfifowrenableout;
wire wire_transmit_pcs5_phfiforddisableout;
wire wire_transmit_pcs5_phfiforesetout;
wire wire_transmit_pcs5_phfifowrenableout;
wire wire_transmit_pcs5_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs5_pipepowerdownout;
wire [3:0] wire_transmit_pcs5_pipepowerstateout;
wire wire_transmit_pcs5_txdetectrx;
wire wire_transmit_pcs6_coreclkout;
wire [19:0] wire_transmit_pcs6_dataout;
wire [149:0] wire_transmit_pcs6_dprioout;
wire wire_transmit_pcs6_forceelecidleout;
wire [2:0] wire_transmit_pcs6_grayelecidleinferselout;
wire wire_transmit_pcs6_iqpphfifobyteselout;
wire wire_transmit_pcs6_iqpphfifordclkout;
wire wire_transmit_pcs6_iqpphfifordenableout;
wire wire_transmit_pcs6_iqpphfifowrenableout;
wire wire_transmit_pcs6_phfiforddisableout;
wire wire_transmit_pcs6_phfiforesetout;
wire wire_transmit_pcs6_phfifowrenableout;
wire wire_transmit_pcs6_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs6_pipepowerdownout;
wire [3:0] wire_transmit_pcs6_pipepowerstateout;
wire wire_transmit_pcs6_txdetectrx;
wire wire_transmit_pcs7_coreclkout;
wire [19:0] wire_transmit_pcs7_dataout;
wire [149:0] wire_transmit_pcs7_dprioout;
wire wire_transmit_pcs7_forceelecidleout;
wire [2:0] wire_transmit_pcs7_grayelecidleinferselout;
wire wire_transmit_pcs7_iqpphfifobyteselout;
wire wire_transmit_pcs7_iqpphfifordclkout;
wire wire_transmit_pcs7_iqpphfifordenableout;
wire wire_transmit_pcs7_iqpphfifowrenableout;
wire wire_transmit_pcs7_phfiforddisableout;
wire wire_transmit_pcs7_phfiforesetout;
wire wire_transmit_pcs7_phfifowrenableout;
wire wire_transmit_pcs7_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs7_pipepowerdownout;
wire [3:0] wire_transmit_pcs7_pipepowerstateout;
wire wire_transmit_pcs7_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma1_clockout;
wire wire_transmit_pma1_dataout;
wire [299:0] wire_transmit_pma1_dprioout;
wire wire_transmit_pma1_rxdetectvalidout;
wire wire_transmit_pma1_rxfoundout;
wire wire_transmit_pma2_clockout;
wire wire_transmit_pma2_dataout;
wire [299:0] wire_transmit_pma2_dprioout;
wire wire_transmit_pma2_rxdetectvalidout;
wire wire_transmit_pma2_rxfoundout;
wire wire_transmit_pma3_clockout;
wire wire_transmit_pma3_dataout;
wire [299:0] wire_transmit_pma3_dprioout;
wire wire_transmit_pma3_rxdetectvalidout;
wire wire_transmit_pma3_rxfoundout;
wire wire_transmit_pma4_clockout;
wire wire_transmit_pma4_dataout;
wire [299:0] wire_transmit_pma4_dprioout;
wire wire_transmit_pma4_rxdetectvalidout;
wire wire_transmit_pma4_rxfoundout;
wire wire_transmit_pma5_clockout;
wire wire_transmit_pma5_dataout;
wire [299:0] wire_transmit_pma5_dprioout;
wire wire_transmit_pma5_rxdetectvalidout;
wire wire_transmit_pma5_rxfoundout;
wire wire_transmit_pma6_clockout;
wire wire_transmit_pma6_dataout;
wire [299:0] wire_transmit_pma6_dprioout;
wire wire_transmit_pma6_rxdetectvalidout;
wire wire_transmit_pma6_rxfoundout;
wire wire_transmit_pma7_clockout;
wire wire_transmit_pma7_dataout;
wire [299:0] wire_transmit_pma7_dprioout;
wire wire_transmit_pma7_rxdetectvalidout;
wire wire_transmit_pma7_rxfoundout;
wire cal_blk_powerdown;
wire [1:0] cent_unit_clkdivpowerdn;
wire [1199:0] cent_unit_cmudividerdprioout;
wire [3599:0] cent_unit_cmuplldprioout;
wire [3:0] cent_unit_pllpowerdn;
wire [3:0] cent_unit_pllresetout;
wire [1:0] cent_unit_quadresetout;
wire [11:0] cent_unit_rxcrupowerdn;
wire [11:0] cent_unit_rxibpowerdn;
wire [3199:0] cent_unit_rxpcsdprioin;
wire [3199:0] cent_unit_rxpcsdprioout;
wire [3599:0] cent_unit_rxpmadprioin;
wire [3599:0] cent_unit_rxpmadprioout;
wire [2399:0] cent_unit_tx_dprioin;
wire [63:0] cent_unit_tx_xgmdataout;
wire [7:0] cent_unit_txctrlout;
wire [11:0] cent_unit_txdetectrxpowerdn;
wire [1199:0] cent_unit_txdprioout;
wire [11:0] cent_unit_txobpowerdn;
wire [3599:0] cent_unit_txpmadprioin;
wire [3599:0] cent_unit_txpmadprioout;
wire [7:0] clk_div_clk0in;
wire [1199:0] clk_div_cmudividerdprioin;
wire [1:0] clk_div_pclkin;
wire [3:0] cmu_analogfastrefclkout;
wire [3:0] cmu_analogrefclkout;
wire [1:0] cmu_analogrefclkpulse;
wire [1:0] coreclkout_wire;
wire [11:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [11:0] fixedclk_fast;
wire [11:0] fixedclk_in;
wire [0:0] fixedclk_sel;
wire [11:0] fixedclk_to_cmu;
wire [1:0] int_autospdx4configsel;
wire [1:0] int_autospdx4rateswitchout;
wire [1:0] int_autospdx4spdchg;
wire [7:0] int_hipautospdrateswitchout;
wire [1:0] int_hiprateswtichdone;
wire [1:0] int_phfifiox4ptrsreset;
wire [7:0] int_pipeenrevparallellpbkfromtx;
wire [1:0] int_rateswitch;
wire [7:0] int_rx_autospdspdchgout;
wire [23:0] int_rx_autospdxnconfigsel;
wire [23:0] int_rx_autospdxnspdchg;
wire [7:0] int_rx_coreclkout;
wire [0:0] int_rx_digitalreset_reg;
wire [15:0] int_rx_iqpautospdxnspgchg;
wire [7:0] int_rx_iqpphfifobyteselout;
wire [7:0] int_rx_iqpphfifoptrsresetout;
wire [7:0] int_rx_iqpphfifordenableout;
wire [7:0] int_rx_iqpphfifowrclkout;
wire [7:0] int_rx_iqpphfifowrenableout;
wire [15:0] int_rx_iqpphfifoxnbytesel;
wire [15:0] int_rx_iqpphfifoxnptrsreset;
wire [15:0] int_rx_iqpphfifoxnrdenable;
wire [15:0] int_rx_iqpphfifoxnwrclk;
wire [15:0] int_rx_iqpphfifoxnwrenable;
wire [23:0] int_rx_phfifioxnptrsreset;
wire [7:0] int_rx_phfifobyteserdisable;
wire [7:0] int_rx_phfifoptrsresetout;
wire [7:0] int_rx_phfifordenableout;
wire [7:0] int_rx_phfiforesetout;
wire [7:0] int_rx_phfifowrdisableout;
wire [23:0] int_rx_phfifoxnbytesel;
wire [23:0] int_rx_phfifoxnrdenable;
wire [23:0] int_rx_phfifoxnwrclk;
wire [23:0] int_rx_phfifoxnwrenable;
wire [7:0] int_rx_rateswitchout;
wire [1:0] int_rxcoreclk;
wire [7:0] int_rxpcs_cdrctrlearlyeios;
wire [1:0] int_rxphfifordenable;
wire [1:0] int_rxphfiforeset;
wire [1:0] int_rxphfifox4byteselout;
wire [1:0] int_rxphfifox4rdenableout;
wire [1:0] int_rxphfifox4wrclkout;
wire [1:0] int_rxphfifox4wrenableout;
wire [7:0] int_tx_coreclkout;
wire [0:0] int_tx_digitalreset_reg;
wire [7:0] int_tx_iqpphfifobyteselout;
wire [7:0] int_tx_iqpphfifordclkout;
wire [7:0] int_tx_iqpphfifordenableout;
wire [7:0] int_tx_iqpphfifowrenableout;
wire [15:0] int_tx_iqpphfifoxnbytesel;
wire [15:0] int_tx_iqpphfifoxnrdclk;
wire [15:0] int_tx_iqpphfifoxnrdenable;
wire [15:0] int_tx_iqpphfifoxnwrenable;
wire [23:0] int_tx_phfifioxnptrsreset;
wire [7:0] int_tx_phfiforddisableout;
wire [7:0] int_tx_phfiforesetout;
wire [7:0] int_tx_phfifowrenableout;
wire [23:0] int_tx_phfifoxnbytesel;
wire [23:0] int_tx_phfifoxnrdclk;
wire [23:0] int_tx_phfifoxnrdenable;
wire [23:0] int_tx_phfifoxnwrenable;
wire [1:0] int_txcoreclk;
wire [1:0] int_txphfiforddisable;
wire [1:0] int_txphfiforeset;
wire [1:0] int_txphfifowrenable;
wire [1:0] int_txphfifox4byteselout;
wire [1:0] int_txphfifox4rdclkout;
wire [1:0] int_txphfifox4rdenableout;
wire [1:0] int_txphfifox4wrenableout;
wire [1:0] nonusertocmu_out;
wire [7:0] pipedatavalid_out;
wire [7:0] pipeelecidle_out;
wire [19:0] pll0_clkin;
wire [599:0] pll0_dprioin;
wire [599:0] pll0_dprioout;
wire [7:0] pll0_out;
wire [15:0] pll_ch_dataout_wire;
wire [2399:0] pll_ch_dprioout;
wire [3599:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [1:0] pll_locked_out;
wire [3:0] pllpowerdn_in;
wire [3:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [1:0] refclk_pma;
wire [11:0] rx_analogreset_in;
wire [11:0] rx_analogreset_out;
wire [79:0] rx_cruclk_in;
wire [31:0] rx_deserclock_in;
wire [7:0] rx_digitalreset_in;
wire [7:0] rx_digitalreset_out;
wire [7:0] rx_enapatternalign;
wire [7:0] rx_freqlocked_wire;
wire [7:0] rx_locktodata;
wire [7:0] rx_locktodata_wire;
wire [7:0] rx_locktorefclk_wire;
wire [63:0] rx_out_wire;
wire [15:0] rx_pcs_rxfound_wire;
wire [3199:0] rx_pcsdprioin_wire;
wire [3199:0] rx_pcsdprioout;
wire [7:0] rx_phfifordenable;
wire [7:0] rx_phfiforeset;
wire [7:0] rx_phfifowrdisable;
wire [7:0] rx_pipestatetransdoneout;
wire [7:0] rx_pldcruclk_in;
wire [31:0] rx_pll_clkout;
wire [7:0] rx_pll_pfdrefclkout_wire;
wire [7:0] rx_plllocked_wire;
wire [135:0] rx_pma_analogtestbus;
wire [7:0] rx_pma_clockout;
wire [7:0] rx_pma_dataout;
wire [7:0] rx_pma_locktorefout;
wire [159:0] rx_pma_recoverdataout_wire;
wire [3599:0] rx_pmadprioin_wire;
wire [3599:0] rx_pmadprioout;
wire [7:0] rx_powerdown;
wire [11:0] rx_powerdown_in;
wire [7:0] rx_prbscidenable;
wire [159:0] rx_revparallelfdbkdata;
wire [7:0] rx_rmfiforeset;
wire [11:0] rx_rxcruresetout;
wire [7:0] rx_signaldetect_wire;
wire [7:0] rx_signaldetectout_wire;
wire [1:0] rxphfifowrdisable;
wire [3599:0] rxpll_dprioin;
wire [11:0] tx_analogreset_out;
wire [7:0] tx_clkout_int_wire;
wire [63:0] tx_datain_wire;
wire [159:0] tx_dataout_pcs_to_pma;
wire [7:0] tx_digitalreset_in;
wire [7:0] tx_digitalreset_out;
wire [2399:0] tx_dprioin_wire;
wire [7:0] tx_invpolarity;
wire [7:0] tx_localrefclk;
wire [7:0] tx_pcs_forceelecidleout;
wire [7:0] tx_phfiforeset;
wire [15:0] tx_pipepowerdownout;
wire [31:0] tx_pipepowerstateout;
wire [7:0] tx_pipeswing;
wire [3599:0] tx_pmadprioin_wire;
wire [3599:0] tx_pmadprioout;
wire [7:0] tx_revparallellpbken;
wire [7:0] tx_rxdetectvalidout;
wire [7:0] tx_rxfoundout;
wire [1199:0] tx_txdprioout;
wire [7:0] txdetectrxout;
wire [1:0] w_cent_unit_dpriodisableout1w;
// synopsys translate_off
initial
fixedclk_div0quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div0quad0c_clk)
fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
assign
wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
// synopsys translate_off
initial
fixedclk_div0quad1c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div0quad1c_clk)
fixedclk_div0quad1c <= (~ fixedclk_div_in[6]);
assign
wire_fixedclk_div0quad1c_clk = fixedclk_in[6];
// synopsys translate_off
initial
fixedclk_div1quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div1quad0c_clk)
fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
assign
wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
// synopsys translate_off
initial
fixedclk_div1quad1c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div1quad1c_clk)
fixedclk_div1quad1c <= (~ fixedclk_div_in[7]);
assign
wire_fixedclk_div1quad1c_clk = fixedclk_in[7];
// synopsys translate_off
initial
fixedclk_div2quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div2quad0c_clk)
fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
assign
wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
// synopsys translate_off
initial
fixedclk_div2quad1c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div2quad1c_clk)
fixedclk_div2quad1c <= (~ fixedclk_div_in[8]);
assign
wire_fixedclk_div2quad1c_clk = fixedclk_in[8];
// synopsys translate_off
initial
fixedclk_div3quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div3quad0c_clk)
fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
assign
wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
// synopsys translate_off
initial
fixedclk_div3quad1c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div3quad1c_clk)
fixedclk_div3quad1c <= (~ fixedclk_div_in[9]);
assign
wire_fixedclk_div3quad1c_clk = fixedclk_in[9];
// synopsys translate_off
initial
fixedclk_div4quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div4quad0c_clk)
fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
assign
wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
// synopsys translate_off
initial
fixedclk_div4quad1c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div4quad1c_clk)
fixedclk_div4quad1c <= (~ fixedclk_div_in[10]);
assign
wire_fixedclk_div4quad1c_clk = fixedclk_in[10];
// synopsys translate_off
initial
fixedclk_div5quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div5quad0c_clk)
fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
assign
wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
// synopsys translate_off
initial
fixedclk_div5quad1c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div5quad1c_clk)
fixedclk_div5quad1c <= (~ fixedclk_div_in[11]);
assign
wire_fixedclk_div5quad1c_clk = fixedclk_in[11];
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
// synopsys translate_off
initial
rx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
rx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
rx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
assign
wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
assign
wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
// synopsys translate_off
initial
tx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
tx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
tx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
assign
wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
assign
wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_calibration_block cal_blk1
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk1_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider central_clk_div0
(
.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[3:0]),
.coreclkout(wire_central_clk_div0_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[499:400]),
.dprioout(wire_central_clk_div0_dprioout),
.powerdn(cent_unit_clkdivpowerdn[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(int_autospdx4rateswitchout[0]),
.rateswitchbaseclock(wire_central_clk_div0_rateswitchbaseclock),
.rateswitchdone(wire_central_clk_div0_rateswitchdone),
.rateswitchout(),
.refclkout(wire_central_clk_div0_refclkout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
central_clk_div0.divide_by = 5,
central_clk_div0.divider_type = "CENTRAL_ENHANCED",
central_clk_div0.effective_data_rate = "5000 Mbps",
central_clk_div0.enable_dynamic_divider = "true",
central_clk_div0.enable_refclk_out = "true",
central_clk_div0.inclk_select = 0,
central_clk_div0.logical_channel_address = 0,
central_clk_div0.pre_divide_by = 1,
central_clk_div0.refclkin_select = 0,
central_clk_div0.select_local_rate_switch_base_clock = "true",
central_clk_div0.select_local_rate_switch_done = "true",
central_clk_div0.select_local_refclk = "true",
central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div0.sim_analogrefclkout_phase_shift = 0,
central_clk_div0.sim_coreclkout_phase_shift = 0,
central_clk_div0.sim_refclkout_phase_shift = 0,
central_clk_div0.use_coreclk_out_post_divider = "false",
central_clk_div0.use_refclk_post_divider = "false",
central_clk_div0.use_vco_bypass = "false",
central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_clock_divider central_clk_div1
(
.analogfastrefclkout(wire_central_clk_div1_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div1_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div1_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[7:4]),
.coreclkout(wire_central_clk_div1_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(cent_unit_cmudividerdprioout[1099:1000]),
.dprioout(wire_central_clk_div1_dprioout),
.powerdn(cent_unit_clkdivpowerdn[1]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchbaseclock(wire_central_clk_div1_rateswitchbaseclock),
.rateswitchdone(wire_central_clk_div1_rateswitchdone),
.rateswitchdonein({{1{1'b0}}, int_hiprateswtichdone[0]}),
.rateswitchout(),
.refclkin({{1{1'b0}}, clk_div_pclkin[1]}),
.refclkout(wire_central_clk_div1_refclkout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitch(1'b0),
.rateswitchbaseclkin({2{1'b0}}),
.refclkdig(1'b0),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
central_clk_div1.divide_by = 5,
central_clk_div1.divider_type = "CENTRAL_ENHANCED",
central_clk_div1.effective_data_rate = "5000 Mbps",
central_clk_div1.enable_dynamic_divider = "true",
central_clk_div1.enable_refclk_out = "true",
central_clk_div1.inclk_select = 0,
central_clk_div1.logical_channel_address = 0,
central_clk_div1.pre_divide_by = 1,
central_clk_div1.refclkin_select = 0,
central_clk_div1.select_local_rate_switch_done = "false",
central_clk_div1.select_local_refclk = "false",
central_clk_div1.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div1.sim_analogrefclkout_phase_shift = 0,
central_clk_div1.sim_coreclkout_phase_shift = 0,
central_clk_div1.sim_refclkout_phase_shift = 0,
central_clk_div1.use_coreclk_out_post_divider = "false",
central_clk_div1.use_refclk_post_divider = "false",
central_clk_div1.use_vco_bypass = "false",
central_clk_div1.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(wire_cent_unit0_autospdx4configsel),
.autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
.autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rateswitch(int_rateswitch[0]),
.rateswitchdonein(int_hiprateswtichdone[0]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxclk(refclk_pma[0]),
.rxcoreclk(int_rxcoreclk[0]),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[0]),
.rxphfiforeset(int_rxphfiforeset[0]),
.rxphfifowrdisable(rxphfifowrdisable[0]),
.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txclk(refclk_pma[0]),
.txcoreclk(int_txcoreclk[0]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[0]),
.txphfiforeset(int_txphfiforeset[0]),
.txphfifowrenable(int_txphfifowrenable[0]),
.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.bonded_quad_mode = "driver",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "true",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 249950,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "true",
cent_unit0.rx0_channel_bonding = "x8",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "digital reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "true",
cent_unit0.rx0_rd_clk_mux_select = "int clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_auto_spd_self_switch_enable = "true",
cent_unit0.tx0_channel_bonding = "x8",
cent_unit0.tx0_ph_fifo_reg_mode = "true",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "int_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "Auto",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_cmu cent_unit1
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(wire_cent_unit1_autospdx4configsel),
.autospdx4rateswitchout(wire_cent_unit1_autospdx4rateswitchout),
.autospdx4spdchg(wire_cent_unit1_autospdx4spdchg),
.clkdivpowerdn(wire_cent_unit1_clkdivpowerdn),
.cmudividerdprioin({clk_div_cmudividerdprioin[1199:600]}),
.cmudividerdprioout(wire_cent_unit1_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[3599:1800]),
.cmuplldprioout(wire_cent_unit1_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit1_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit1_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[9:6]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[1]),
.phfifiox4ptrsreset(wire_cent_unit1_phfifiox4ptrsreset),
.pllpowerdn(wire_cent_unit1_pllpowerdn),
.pllresetout(wire_cent_unit1_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit1_quadresetout),
.rateswitch(int_rateswitch[1]),
.rateswitchdonein(int_hiprateswtichdone[1]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[7:4]}),
.rxanalogresetout(wire_cent_unit1_rxanalogresetout),
.rxclk(refclk_pma[1]),
.rxcoreclk(int_rxcoreclk[1]),
.rxcrupowerdown(wire_cent_unit1_rxcrupowerdown),
.rxcruresetout(wire_cent_unit1_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[7:4]}),
.rxdigitalresetout(wire_cent_unit1_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit1_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[3199:1600]}),
.rxpcsdprioout(wire_cent_unit1_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[1]),
.rxphfiforeset(int_rxphfiforeset[1]),
.rxphfifowrdisable(rxphfifowrdisable[1]),
.rxphfifox4byteselout(wire_cent_unit1_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit1_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit1_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit1_rxphfifox4wrenableout),
.rxpmadprioin({cent_unit_rxpmadprioin[3599:1800]}),
.rxpmadprioout(wire_cent_unit1_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[7:4]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit1_txanalogresetout),
.txclk(refclk_pma[1]),
.txcoreclk(int_txcoreclk[1]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit1_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit1_txdataout),
.txdetectrxpowerdown(wire_cent_unit1_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[7:4]}),
.txdigitalresetout(wire_cent_unit1_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit1_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[1199:600]}),
.txpcsdprioout(wire_cent_unit1_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[1]),
.txphfiforeset(int_txphfiforeset[1]),
.txphfifowrenable(int_txphfifowrenable[1]),
.txphfifox4byteselout(wire_cent_unit1_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit1_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit1_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit1_txphfifox4wrenableout),
.txpmadprioin({cent_unit_txpmadprioin[3599:1800]}),
.txpmadprioout(wire_cent_unit1_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}}),
.txpllreset({2{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit1.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit1.auto_spd_phystatus_notify_count = 14,
cent_unit1.bonded_quad_mode = "receiver",
cent_unit1.devaddr = ((((starting_channel_number / 4) + 1) % 32) + 1),
cent_unit1.in_xaui_mode = "false",
cent_unit1.offset_all_errors_align = "false",
cent_unit1.pipe_auto_speed_nego_enable = "true",
cent_unit1.pipe_freq_scale_mode = "Frequency",
cent_unit1.pma_done_count = 249950,
cent_unit1.portaddr = (((starting_channel_number + 4) / 128) + 1),
cent_unit1.rx0_auto_spd_self_switch_enable = "true",
cent_unit1.rx0_channel_bonding = "x8",
cent_unit1.rx0_clk1_mux_select = "recovered clock",
cent_unit1.rx0_clk2_mux_select = "digital reference clock",
cent_unit1.rx0_ph_fifo_reg_mode = "true",
cent_unit1.rx0_rd_clk_mux_select = "int clock",
cent_unit1.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit1.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit1.rx0_use_double_data_mode = "false",
cent_unit1.tx0_auto_spd_self_switch_enable = "true",
cent_unit1.tx0_channel_bonding = "x8",
cent_unit1.tx0_ph_fifo_reg_mode = "true",
cent_unit1.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit1.tx0_use_double_data_mode = "false",
cent_unit1.tx0_wr_clk_mux_select = "int_clk",
cent_unit1.use_deskew_fifo = "false",
cent_unit1.vcceh_voltage = "Auto",
cent_unit1.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({rx_cruclk_in[9:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.rateswitch(int_hipautospdrateswitchout[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Auto",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "5000 Mbps",
rx_cdr_pll0.enable_dynamic_divider = "true",
rx_cdr_pll0.fast_lock_control = "false",
rx_cdr_pll0.inclk0_input_period = 10000,
rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
rx_cdr_pll0.m = 25,
rx_cdr_pll0.n = 1,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_post_scale = 1,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll1
(
.areset(rx_rxcruresetout[1]),
.clk(wire_rx_cdr_pll1_clk),
.datain(rx_pma_dataout[1]),
.dataout(wire_rx_cdr_pll1_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[599:300]),
.dprioout(wire_rx_cdr_pll1_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
.freqlocked(wire_rx_cdr_pll1_freqlocked),
.inclk({rx_cruclk_in[19:10]}),
.locked(wire_rx_cdr_pll1_locked),
.locktorefclk(rx_pma_locktorefout[1]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[1]),
.rateswitch(int_hipautospdrateswitchout[1]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll1.bandwidth_type = "Auto",
rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
rx_cdr_pll1.dprio_config_mode = 6'h00,
rx_cdr_pll1.effective_data_rate = "5000 Mbps",
rx_cdr_pll1.enable_dynamic_divider = "true",
rx_cdr_pll1.fast_lock_control = "false",
rx_cdr_pll1.inclk0_input_period = 10000,
rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
rx_cdr_pll1.m = 25,
rx_cdr_pll1.n = 1,
rx_cdr_pll1.pfd_clk_select = 0,
rx_cdr_pll1.pll_type = "RX CDR",
rx_cdr_pll1.use_refclk_pin = "false",
rx_cdr_pll1.vco_post_scale = 1,
rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll2
(
.areset(rx_rxcruresetout[2]),
.clk(wire_rx_cdr_pll2_clk),
.datain(rx_pma_dataout[2]),
.dataout(wire_rx_cdr_pll2_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[899:600]),
.dprioout(wire_rx_cdr_pll2_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
.freqlocked(wire_rx_cdr_pll2_freqlocked),
.inclk({rx_cruclk_in[29:20]}),
.locked(wire_rx_cdr_pll2_locked),
.locktorefclk(rx_pma_locktorefout[2]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[2]),
.rateswitch(int_hipautospdrateswitchout[2]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll2.bandwidth_type = "Auto",
rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
rx_cdr_pll2.dprio_config_mode = 6'h00,
rx_cdr_pll2.effective_data_rate = "5000 Mbps",
rx_cdr_pll2.enable_dynamic_divider = "true",
rx_cdr_pll2.fast_lock_control = "false",
rx_cdr_pll2.inclk0_input_period = 10000,
rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
rx_cdr_pll2.m = 25,
rx_cdr_pll2.n = 1,
rx_cdr_pll2.pfd_clk_select = 0,
rx_cdr_pll2.pll_type = "RX CDR",
rx_cdr_pll2.use_refclk_pin = "false",
rx_cdr_pll2.vco_post_scale = 1,
rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll3
(
.areset(rx_rxcruresetout[3]),
.clk(wire_rx_cdr_pll3_clk),
.datain(rx_pma_dataout[3]),
.dataout(wire_rx_cdr_pll3_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[1199:900]),
.dprioout(wire_rx_cdr_pll3_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
.freqlocked(wire_rx_cdr_pll3_freqlocked),
.inclk({rx_cruclk_in[39:30]}),
.locked(wire_rx_cdr_pll3_locked),
.locktorefclk(rx_pma_locktorefout[3]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[3]),
.rateswitch(int_hipautospdrateswitchout[3]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll3.bandwidth_type = "Auto",
rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
rx_cdr_pll3.dprio_config_mode = 6'h00,
rx_cdr_pll3.effective_data_rate = "5000 Mbps",
rx_cdr_pll3.enable_dynamic_divider = "true",
rx_cdr_pll3.fast_lock_control = "false",
rx_cdr_pll3.inclk0_input_period = 10000,
rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
rx_cdr_pll3.m = 25,
rx_cdr_pll3.n = 1,
rx_cdr_pll3.pfd_clk_select = 0,
rx_cdr_pll3.pll_type = "RX CDR",
rx_cdr_pll3.use_refclk_pin = "false",
rx_cdr_pll3.vco_post_scale = 1,
rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll4
(
.areset(rx_rxcruresetout[6]),
.clk(wire_rx_cdr_pll4_clk),
.datain(rx_pma_dataout[4]),
.dataout(wire_rx_cdr_pll4_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2099:1800]),
.dprioout(wire_rx_cdr_pll4_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[4]),
.freqlocked(wire_rx_cdr_pll4_freqlocked),
.inclk({rx_cruclk_in[49:40]}),
.locked(wire_rx_cdr_pll4_locked),
.locktorefclk(rx_pma_locktorefout[4]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll4_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[6]),
.rateswitch(int_hipautospdrateswitchout[4]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll4.bandwidth_type = "Auto",
rx_cdr_pll4.channel_num = ((starting_channel_number + 4) % 4),
rx_cdr_pll4.dprio_config_mode = 6'h00,
rx_cdr_pll4.effective_data_rate = "5000 Mbps",
rx_cdr_pll4.enable_dynamic_divider = "true",
rx_cdr_pll4.fast_lock_control = "false",
rx_cdr_pll4.inclk0_input_period = 10000,
rx_cdr_pll4.input_clock_frequency = "100.0 MHz",
rx_cdr_pll4.m = 25,
rx_cdr_pll4.n = 1,
rx_cdr_pll4.pfd_clk_select = 0,
rx_cdr_pll4.pll_type = "RX CDR",
rx_cdr_pll4.use_refclk_pin = "false",
rx_cdr_pll4.vco_post_scale = 1,
rx_cdr_pll4.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll5
(
.areset(rx_rxcruresetout[7]),
.clk(wire_rx_cdr_pll5_clk),
.datain(rx_pma_dataout[5]),
.dataout(wire_rx_cdr_pll5_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2399:2100]),
.dprioout(wire_rx_cdr_pll5_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[5]),
.freqlocked(wire_rx_cdr_pll5_freqlocked),
.inclk({rx_cruclk_in[59:50]}),
.locked(wire_rx_cdr_pll5_locked),
.locktorefclk(rx_pma_locktorefout[5]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll5_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[7]),
.rateswitch(int_hipautospdrateswitchout[5]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll5.bandwidth_type = "Auto",
rx_cdr_pll5.channel_num = ((starting_channel_number + 5) % 4),
rx_cdr_pll5.dprio_config_mode = 6'h00,
rx_cdr_pll5.effective_data_rate = "5000 Mbps",
rx_cdr_pll5.enable_dynamic_divider = "true",
rx_cdr_pll5.fast_lock_control = "false",
rx_cdr_pll5.inclk0_input_period = 10000,
rx_cdr_pll5.input_clock_frequency = "100.0 MHz",
rx_cdr_pll5.m = 25,
rx_cdr_pll5.n = 1,
rx_cdr_pll5.pfd_clk_select = 0,
rx_cdr_pll5.pll_type = "RX CDR",
rx_cdr_pll5.use_refclk_pin = "false",
rx_cdr_pll5.vco_post_scale = 1,
rx_cdr_pll5.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll6
(
.areset(rx_rxcruresetout[8]),
.clk(wire_rx_cdr_pll6_clk),
.datain(rx_pma_dataout[6]),
.dataout(wire_rx_cdr_pll6_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2699:2400]),
.dprioout(wire_rx_cdr_pll6_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[6]),
.freqlocked(wire_rx_cdr_pll6_freqlocked),
.inclk({rx_cruclk_in[69:60]}),
.locked(wire_rx_cdr_pll6_locked),
.locktorefclk(rx_pma_locktorefout[6]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll6_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[8]),
.rateswitch(int_hipautospdrateswitchout[6]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll6.bandwidth_type = "Auto",
rx_cdr_pll6.channel_num = ((starting_channel_number + 6) % 4),
rx_cdr_pll6.dprio_config_mode = 6'h00,
rx_cdr_pll6.effective_data_rate = "5000 Mbps",
rx_cdr_pll6.enable_dynamic_divider = "true",
rx_cdr_pll6.fast_lock_control = "false",
rx_cdr_pll6.inclk0_input_period = 10000,
rx_cdr_pll6.input_clock_frequency = "100.0 MHz",
rx_cdr_pll6.m = 25,
rx_cdr_pll6.n = 1,
rx_cdr_pll6.pfd_clk_select = 0,
rx_cdr_pll6.pll_type = "RX CDR",
rx_cdr_pll6.use_refclk_pin = "false",
rx_cdr_pll6.vco_post_scale = 1,
rx_cdr_pll6.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll7
(
.areset(rx_rxcruresetout[9]),
.clk(wire_rx_cdr_pll7_clk),
.datain(rx_pma_dataout[7]),
.dataout(wire_rx_cdr_pll7_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2999:2700]),
.dprioout(wire_rx_cdr_pll7_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[7]),
.freqlocked(wire_rx_cdr_pll7_freqlocked),
.inclk({rx_cruclk_in[79:70]}),
.locked(wire_rx_cdr_pll7_locked),
.locktorefclk(rx_pma_locktorefout[7]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll7_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[9]),
.rateswitch(int_hipautospdrateswitchout[7]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll7.bandwidth_type = "Auto",
rx_cdr_pll7.channel_num = ((starting_channel_number + 7) % 4),
rx_cdr_pll7.dprio_config_mode = 6'h00,
rx_cdr_pll7.effective_data_rate = "5000 Mbps",
rx_cdr_pll7.enable_dynamic_divider = "true",
rx_cdr_pll7.fast_lock_control = "false",
rx_cdr_pll7.inclk0_input_period = 10000,
rx_cdr_pll7.input_clock_frequency = "100.0 MHz",
rx_cdr_pll7.m = 25,
rx_cdr_pll7.n = 1,
rx_cdr_pll7.pfd_clk_select = 0,
rx_cdr_pll7.pll_type = "RX CDR",
rx_cdr_pll7.use_refclk_pin = "false",
rx_cdr_pll7.vco_post_scale = 1,
rx_cdr_pll7.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 10000,
tx_pll0.input_clock_frequency = "100.0 MHz",
tx_pll0.logical_tx_pll_number = 0,
tx_pll0.m = 25,
tx_pll0.n = 1,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_post_scale = 1,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs0_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
.autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs0_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[0]),
.hipdataout(wire_receive_pcs0_hipdataout),
.hipdatavalid(wire_receive_pcs0_hipdatavalid),
.hipelecidle(wire_receive_pcs0_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs0_hipphydonestatus),
.hippowerdown(powerdn[1:0]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs0_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[1:0]),
.iqpphfifobyteselout(wire_receive_pcs0_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs0_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs0_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs0_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs0_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[1:0]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[1:0]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[1:0]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[1:0]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[1:0]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(wire_receive_pcs0_phfifordenableout),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(wire_receive_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs0_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(wire_receive_pcs0_signaldetect),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.auto_spd_self_switch_enable = "true",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_cid_mode_enable = "true",
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "x8",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "digital reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "true",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "true",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "central",
receive_pcs0.ph_fifo_xn_select = 2,
receive_pcs0.pipe_auto_speed_nego_enable = "true",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 249950,
receive_pcs0.protocol_hint = "pcie2",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_pipe_enable = "true",
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "int clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 32,
receive_pcs0.rxstatus_error_report_mode = 1,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs1
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs1_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
.autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs1_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[39:20]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[1]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[799:400]),
.dprioout(wire_receive_pcs1_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[1]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[1]),
.hipdataout(wire_receive_pcs1_hipdataout),
.hipdatavalid(wire_receive_pcs1_hipdatavalid),
.hipelecidle(wire_receive_pcs1_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs1_hipphydonestatus),
.hippowerdown(powerdn[3:2]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs1_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[3:2]),
.iqpphfifobyteselout(wire_receive_pcs1_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs1_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs1_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs1_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs1_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[3:2]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[3:2]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[3:2]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[3:2]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[3:2]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[1]),
.phfifordenableout(wire_receive_pcs1_phfifordenableout),
.phfiforeset(rx_phfiforeset[1]),
.phfiforesetout(wire_receive_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[1]),
.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[3:2]),
.pipepowerstate(tx_pipepowerstateout[7:4]),
.pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs1_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[1]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[1]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[1]),
.rxfound(rx_pcs_rxfound_wire[3:2]),
.signaldetect(wire_receive_pcs1_signaldetect),
.signaldetected(rx_signaldetect_wire[1]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs1.align_pattern = "0101111100",
receive_pcs1.align_pattern_length = 10,
receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs1.allow_align_polarity_inversion = "false",
receive_pcs1.allow_pipe_polarity_inversion = "true",
receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs1.auto_spd_phystatus_notify_count = 14,
receive_pcs1.auto_spd_self_switch_enable = "true",
receive_pcs1.bit_slip_enable = "false",
receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs1.byte_order_mode = "none",
receive_pcs1.byte_order_pad_pattern = "0",
receive_pcs1.byte_order_pattern = "0",
receive_pcs1.byte_order_pld_ctrl_enable = "false",
receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs1.cdrctrl_cid_mode_enable = "true",
receive_pcs1.cdrctrl_enable = "true",
receive_pcs1.cdrctrl_rxvalid_mask = "true",
receive_pcs1.channel_bonding = "x8",
receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
receive_pcs1.channel_width = 8,
receive_pcs1.clk1_mux_select = "recovered clock",
receive_pcs1.clk2_mux_select = "digital reference clock",
receive_pcs1.core_clock_0ppm = "false",
receive_pcs1.datapath_low_latency_mode = "false",
receive_pcs1.datapath_protocol = "pipe",
receive_pcs1.dec_8b_10b_compatibility_mode = "true",
receive_pcs1.dec_8b_10b_mode = "normal",
receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs1.deskew_pattern = "0",
receive_pcs1.disable_auto_idle_insertion = "false",
receive_pcs1.disable_running_disp_in_word_align = "false",
receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs1.dprio_config_mode = 6'h01,
receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
receive_pcs1.elec_idle_infer_enable = "false",
receive_pcs1.elec_idle_num_com_detect = 3,
receive_pcs1.enable_bit_reversal = "false",
receive_pcs1.enable_deep_align = "false",
receive_pcs1.enable_deep_align_byte_swap = "false",
receive_pcs1.enable_self_test_mode = "false",
receive_pcs1.enable_true_complement_match_in_word_align = "false",
receive_pcs1.force_signal_detect_dig = "true",
receive_pcs1.hip_enable = "true",
receive_pcs1.infiniband_invalid_code = 0,
receive_pcs1.insert_pad_on_underflow = "false",
receive_pcs1.logical_channel_address = (starting_channel_number + 1),
receive_pcs1.num_align_code_groups_in_ordered_set = 0,
receive_pcs1.num_align_cons_good_data = 16,
receive_pcs1.num_align_cons_pat = 4,
receive_pcs1.num_align_loss_sync_error = 17,
receive_pcs1.ph_fifo_low_latency_enable = "true",
receive_pcs1.ph_fifo_reg_mode = "true",
receive_pcs1.ph_fifo_xn_mapping0 = "none",
receive_pcs1.ph_fifo_xn_mapping1 = "none",
receive_pcs1.ph_fifo_xn_mapping2 = "central",
receive_pcs1.ph_fifo_xn_select = 2,
receive_pcs1.pipe_auto_speed_nego_enable = "true",
receive_pcs1.pipe_freq_scale_mode = "Frequency",
receive_pcs1.pma_done_count = 249950,
receive_pcs1.protocol_hint = "pcie2",
receive_pcs1.rate_match_almost_empty_threshold = 11,
receive_pcs1.rate_match_almost_full_threshold = 13,
receive_pcs1.rate_match_back_to_back = "false",
receive_pcs1.rate_match_delete_threshold = 13,
receive_pcs1.rate_match_empty_threshold = 5,
receive_pcs1.rate_match_fifo_mode = "true",
receive_pcs1.rate_match_full_threshold = 20,
receive_pcs1.rate_match_insert_threshold = 11,
receive_pcs1.rate_match_ordered_set_based = "false",
receive_pcs1.rate_match_pattern1 = "11010000111010000011",
receive_pcs1.rate_match_pattern2 = "00101111000101111100",
receive_pcs1.rate_match_pattern_size = 20,
receive_pcs1.rate_match_pipe_enable = "true",
receive_pcs1.rate_match_reset_enable = "false",
receive_pcs1.rate_match_skip_set_based = "true",
receive_pcs1.rate_match_start_threshold = 7,
receive_pcs1.rd_clk_mux_select = "int clock",
receive_pcs1.recovered_clk_mux_select = "recovered clock",
receive_pcs1.run_length = 40,
receive_pcs1.run_length_enable = "true",
receive_pcs1.rx_detect_bypass = "false",
receive_pcs1.rx_phfifo_wait_cnt = 32,
receive_pcs1.rxstatus_error_report_mode = 1,
receive_pcs1.self_test_mode = "incremental",
receive_pcs1.use_alignment_state_machine = "true",
receive_pcs1.use_deserializer_double_data_mode = "false",
receive_pcs1.use_deskew_fifo = "false",
receive_pcs1.use_double_data_mode = "false",
receive_pcs1.use_parallel_loopback = "false",
receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs2
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs2_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
.autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs2_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[59:40]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[2]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1199:800]),
.dprioout(wire_receive_pcs2_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[2]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[2]),
.hipdataout(wire_receive_pcs2_hipdataout),
.hipdatavalid(wire_receive_pcs2_hipdatavalid),
.hipelecidle(wire_receive_pcs2_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs2_hipphydonestatus),
.hippowerdown(powerdn[5:4]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs2_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[5:4]),
.iqpphfifobyteselout(wire_receive_pcs2_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs2_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs2_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs2_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs2_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[5:4]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[5:4]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[5:4]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[5:4]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[5:4]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[2]),
.phfifordenableout(wire_receive_pcs2_phfifordenableout),
.phfiforeset(rx_phfiforeset[2]),
.phfiforesetout(wire_receive_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[2]),
.phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[5:4]),
.pipepowerstate(tx_pipepowerstateout[11:8]),
.pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs2_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[2]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[2]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[2]),
.rxfound(rx_pcs_rxfound_wire[5:4]),
.signaldetect(wire_receive_pcs2_signaldetect),
.signaldetected(rx_signaldetect_wire[2]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs2.align_pattern = "0101111100",
receive_pcs2.align_pattern_length = 10,
receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs2.allow_align_polarity_inversion = "false",
receive_pcs2.allow_pipe_polarity_inversion = "true",
receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs2.auto_spd_phystatus_notify_count = 14,
receive_pcs2.auto_spd_self_switch_enable = "true",
receive_pcs2.bit_slip_enable = "false",
receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs2.byte_order_mode = "none",
receive_pcs2.byte_order_pad_pattern = "0",
receive_pcs2.byte_order_pattern = "0",
receive_pcs2.byte_order_pld_ctrl_enable = "false",
receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs2.cdrctrl_cid_mode_enable = "true",
receive_pcs2.cdrctrl_enable = "true",
receive_pcs2.cdrctrl_rxvalid_mask = "true",
receive_pcs2.channel_bonding = "x8",
receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
receive_pcs2.channel_width = 8,
receive_pcs2.clk1_mux_select = "recovered clock",
receive_pcs2.clk2_mux_select = "digital reference clock",
receive_pcs2.core_clock_0ppm = "false",
receive_pcs2.datapath_low_latency_mode = "false",
receive_pcs2.datapath_protocol = "pipe",
receive_pcs2.dec_8b_10b_compatibility_mode = "true",
receive_pcs2.dec_8b_10b_mode = "normal",
receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs2.deskew_pattern = "0",
receive_pcs2.disable_auto_idle_insertion = "false",
receive_pcs2.disable_running_disp_in_word_align = "false",
receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs2.dprio_config_mode = 6'h01,
receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
receive_pcs2.elec_idle_infer_enable = "false",
receive_pcs2.elec_idle_num_com_detect = 3,
receive_pcs2.enable_bit_reversal = "false",
receive_pcs2.enable_deep_align = "false",
receive_pcs2.enable_deep_align_byte_swap = "false",
receive_pcs2.enable_self_test_mode = "false",
receive_pcs2.enable_true_complement_match_in_word_align = "false",
receive_pcs2.force_signal_detect_dig = "true",
receive_pcs2.hip_enable = "true",
receive_pcs2.infiniband_invalid_code = 0,
receive_pcs2.insert_pad_on_underflow = "false",
receive_pcs2.logical_channel_address = (starting_channel_number + 2),
receive_pcs2.num_align_code_groups_in_ordered_set = 0,
receive_pcs2.num_align_cons_good_data = 16,
receive_pcs2.num_align_cons_pat = 4,
receive_pcs2.num_align_loss_sync_error = 17,
receive_pcs2.ph_fifo_low_latency_enable = "true",
receive_pcs2.ph_fifo_reg_mode = "true",
receive_pcs2.ph_fifo_xn_mapping0 = "none",
receive_pcs2.ph_fifo_xn_mapping1 = "none",
receive_pcs2.ph_fifo_xn_mapping2 = "central",
receive_pcs2.ph_fifo_xn_select = 2,
receive_pcs2.pipe_auto_speed_nego_enable = "true",
receive_pcs2.pipe_freq_scale_mode = "Frequency",
receive_pcs2.pma_done_count = 249950,
receive_pcs2.protocol_hint = "pcie2",
receive_pcs2.rate_match_almost_empty_threshold = 11,
receive_pcs2.rate_match_almost_full_threshold = 13,
receive_pcs2.rate_match_back_to_back = "false",
receive_pcs2.rate_match_delete_threshold = 13,
receive_pcs2.rate_match_empty_threshold = 5,
receive_pcs2.rate_match_fifo_mode = "true",
receive_pcs2.rate_match_full_threshold = 20,
receive_pcs2.rate_match_insert_threshold = 11,
receive_pcs2.rate_match_ordered_set_based = "false",
receive_pcs2.rate_match_pattern1 = "11010000111010000011",
receive_pcs2.rate_match_pattern2 = "00101111000101111100",
receive_pcs2.rate_match_pattern_size = 20,
receive_pcs2.rate_match_pipe_enable = "true",
receive_pcs2.rate_match_reset_enable = "false",
receive_pcs2.rate_match_skip_set_based = "true",
receive_pcs2.rate_match_start_threshold = 7,
receive_pcs2.rd_clk_mux_select = "int clock",
receive_pcs2.recovered_clk_mux_select = "recovered clock",
receive_pcs2.run_length = 40,
receive_pcs2.run_length_enable = "true",
receive_pcs2.rx_detect_bypass = "false",
receive_pcs2.rx_phfifo_wait_cnt = 32,
receive_pcs2.rxstatus_error_report_mode = 1,
receive_pcs2.self_test_mode = "incremental",
receive_pcs2.use_alignment_state_machine = "true",
receive_pcs2.use_deserializer_double_data_mode = "false",
receive_pcs2.use_deskew_fifo = "false",
receive_pcs2.use_double_data_mode = "false",
receive_pcs2.use_parallel_loopback = "false",
receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs3
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs3_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
.autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs3_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[79:60]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[3]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1599:1200]),
.dprioout(wire_receive_pcs3_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[3]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[3]),
.hipdataout(wire_receive_pcs3_hipdataout),
.hipdatavalid(wire_receive_pcs3_hipdatavalid),
.hipelecidle(wire_receive_pcs3_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs3_hipphydonestatus),
.hippowerdown(powerdn[7:6]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs3_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[7:6]),
.iqpphfifobyteselout(wire_receive_pcs3_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs3_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs3_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs3_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs3_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[7:6]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[7:6]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[7:6]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[7:6]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[7:6]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[3]),
.phfifordenableout(wire_receive_pcs3_phfifordenableout),
.phfiforeset(rx_phfiforeset[3]),
.phfiforesetout(wire_receive_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[3]),
.phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[7:6]),
.pipepowerstate(tx_pipepowerstateout[15:12]),
.pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs3_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[3]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[3]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[3]),
.rxfound(rx_pcs_rxfound_wire[7:6]),
.signaldetect(wire_receive_pcs3_signaldetect),
.signaldetected(rx_signaldetect_wire[3]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs3.align_pattern = "0101111100",
receive_pcs3.align_pattern_length = 10,
receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs3.allow_align_polarity_inversion = "false",
receive_pcs3.allow_pipe_polarity_inversion = "true",
receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs3.auto_spd_phystatus_notify_count = 14,
receive_pcs3.auto_spd_self_switch_enable = "true",
receive_pcs3.bit_slip_enable = "false",
receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs3.byte_order_mode = "none",
receive_pcs3.byte_order_pad_pattern = "0",
receive_pcs3.byte_order_pattern = "0",
receive_pcs3.byte_order_pld_ctrl_enable = "false",
receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs3.cdrctrl_cid_mode_enable = "true",
receive_pcs3.cdrctrl_enable = "true",
receive_pcs3.cdrctrl_rxvalid_mask = "true",
receive_pcs3.channel_bonding = "x8",
receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
receive_pcs3.channel_width = 8,
receive_pcs3.clk1_mux_select = "recovered clock",
receive_pcs3.clk2_mux_select = "digital reference clock",
receive_pcs3.core_clock_0ppm = "false",
receive_pcs3.datapath_low_latency_mode = "false",
receive_pcs3.datapath_protocol = "pipe",
receive_pcs3.dec_8b_10b_compatibility_mode = "true",
receive_pcs3.dec_8b_10b_mode = "normal",
receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs3.deskew_pattern = "0",
receive_pcs3.disable_auto_idle_insertion = "false",
receive_pcs3.disable_running_disp_in_word_align = "false",
receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs3.dprio_config_mode = 6'h01,
receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
receive_pcs3.elec_idle_infer_enable = "false",
receive_pcs3.elec_idle_num_com_detect = 3,
receive_pcs3.enable_bit_reversal = "false",
receive_pcs3.enable_deep_align = "false",
receive_pcs3.enable_deep_align_byte_swap = "false",
receive_pcs3.enable_self_test_mode = "false",
receive_pcs3.enable_true_complement_match_in_word_align = "false",
receive_pcs3.force_signal_detect_dig = "true",
receive_pcs3.hip_enable = "true",
receive_pcs3.infiniband_invalid_code = 0,
receive_pcs3.insert_pad_on_underflow = "false",
receive_pcs3.logical_channel_address = (starting_channel_number + 3),
receive_pcs3.num_align_code_groups_in_ordered_set = 0,
receive_pcs3.num_align_cons_good_data = 16,
receive_pcs3.num_align_cons_pat = 4,
receive_pcs3.num_align_loss_sync_error = 17,
receive_pcs3.ph_fifo_low_latency_enable = "true",
receive_pcs3.ph_fifo_reg_mode = "true",
receive_pcs3.ph_fifo_xn_mapping0 = "none",
receive_pcs3.ph_fifo_xn_mapping1 = "none",
receive_pcs3.ph_fifo_xn_mapping2 = "central",
receive_pcs3.ph_fifo_xn_select = 2,
receive_pcs3.pipe_auto_speed_nego_enable = "true",
receive_pcs3.pipe_freq_scale_mode = "Frequency",
receive_pcs3.pma_done_count = 249950,
receive_pcs3.protocol_hint = "pcie2",
receive_pcs3.rate_match_almost_empty_threshold = 11,
receive_pcs3.rate_match_almost_full_threshold = 13,
receive_pcs3.rate_match_back_to_back = "false",
receive_pcs3.rate_match_delete_threshold = 13,
receive_pcs3.rate_match_empty_threshold = 5,
receive_pcs3.rate_match_fifo_mode = "true",
receive_pcs3.rate_match_full_threshold = 20,
receive_pcs3.rate_match_insert_threshold = 11,
receive_pcs3.rate_match_ordered_set_based = "false",
receive_pcs3.rate_match_pattern1 = "11010000111010000011",
receive_pcs3.rate_match_pattern2 = "00101111000101111100",
receive_pcs3.rate_match_pattern_size = 20,
receive_pcs3.rate_match_pipe_enable = "true",
receive_pcs3.rate_match_reset_enable = "false",
receive_pcs3.rate_match_skip_set_based = "true",
receive_pcs3.rate_match_start_threshold = 7,
receive_pcs3.rd_clk_mux_select = "int clock",
receive_pcs3.recovered_clk_mux_select = "recovered clock",
receive_pcs3.run_length = 40,
receive_pcs3.run_length_enable = "true",
receive_pcs3.rx_detect_bypass = "false",
receive_pcs3.rx_phfifo_wait_cnt = 32,
receive_pcs3.rxstatus_error_report_mode = 1,
receive_pcs3.self_test_mode = "incremental",
receive_pcs3.use_alignment_state_machine = "true",
receive_pcs3.use_deserializer_double_data_mode = "false",
receive_pcs3.use_deskew_fifo = "false",
receive_pcs3.use_double_data_mode = "false",
receive_pcs3.use_parallel_loopback = "false",
receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs4
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs4_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs4_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[14:12]),
.autospdxnspdchg(int_rx_autospdxnspdchg[14:12]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs4_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs4_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs4_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[99:80]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[4]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[1999:1600]),
.dprioout(wire_receive_pcs4_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[4]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[4]),
.hipdataout(wire_receive_pcs4_hipdataout),
.hipdatavalid(wire_receive_pcs4_hipdatavalid),
.hipelecidle(wire_receive_pcs4_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs4_hipphydonestatus),
.hippowerdown(powerdn[9:8]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs4_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[9:8]),
.iqpphfifobyteselout(wire_receive_pcs4_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs4_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs4_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs4_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs4_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[9:8]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[9:8]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[9:8]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[9:8]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[9:8]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs4_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs4_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[4]),
.phfifordenableout(wire_receive_pcs4_phfifordenableout),
.phfiforeset(rx_phfiforeset[4]),
.phfiforesetout(wire_receive_pcs4_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[4]),
.phfifowrdisableout(wire_receive_pcs4_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[14:12]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[14:12]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[14:12]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[14:12]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[14:12]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[4]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[9:8]),
.pipepowerstate(tx_pipepowerstateout[19:16]),
.pipestatetransdoneout(wire_receive_pcs4_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[4]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(wire_receive_pcs4_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[4]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs4_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[4]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[4]),
.rxfound(rx_pcs_rxfound_wire[9:8]),
.signaldetect(wire_receive_pcs4_signaldetect),
.signaldetected(rx_signaldetect_wire[4]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs4.align_pattern = "0101111100",
receive_pcs4.align_pattern_length = 10,
receive_pcs4.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs4.allow_align_polarity_inversion = "false",
receive_pcs4.allow_pipe_polarity_inversion = "true",
receive_pcs4.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs4.auto_spd_phystatus_notify_count = 14,
receive_pcs4.auto_spd_self_switch_enable = "true",
receive_pcs4.bit_slip_enable = "false",
receive_pcs4.byte_order_double_data_mode_mask_enable = "false",
receive_pcs4.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs4.byte_order_mode = "none",
receive_pcs4.byte_order_pad_pattern = "0",
receive_pcs4.byte_order_pattern = "0",
receive_pcs4.byte_order_pld_ctrl_enable = "false",
receive_pcs4.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs4.cdrctrl_cid_mode_enable = "true",
receive_pcs4.cdrctrl_enable = "true",
receive_pcs4.cdrctrl_rxvalid_mask = "true",
receive_pcs4.channel_bonding = "x8",
receive_pcs4.channel_number = ((starting_channel_number + 4) % 4),
receive_pcs4.channel_width = 8,
receive_pcs4.clk1_mux_select = "recovered clock",
receive_pcs4.clk2_mux_select = "digital reference clock",
receive_pcs4.core_clock_0ppm = "false",
receive_pcs4.datapath_low_latency_mode = "false",
receive_pcs4.datapath_protocol = "pipe",
receive_pcs4.dec_8b_10b_compatibility_mode = "true",
receive_pcs4.dec_8b_10b_mode = "normal",
receive_pcs4.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs4.deskew_pattern = "0",
receive_pcs4.disable_auto_idle_insertion = "false",
receive_pcs4.disable_running_disp_in_word_align = "false",
receive_pcs4.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs4.dprio_config_mode = 6'h01,
receive_pcs4.elec_idle_gen1_sigdet_enable = "true",
receive_pcs4.elec_idle_infer_enable = "false",
receive_pcs4.elec_idle_num_com_detect = 3,
receive_pcs4.enable_bit_reversal = "false",
receive_pcs4.enable_deep_align = "false",
receive_pcs4.enable_deep_align_byte_swap = "false",
receive_pcs4.enable_self_test_mode = "false",
receive_pcs4.enable_true_complement_match_in_word_align = "false",
receive_pcs4.force_signal_detect_dig = "true",
receive_pcs4.hip_enable = "true",
receive_pcs4.infiniband_invalid_code = 0,
receive_pcs4.insert_pad_on_underflow = "false",
receive_pcs4.iqp_ph_fifo_xn_select = 1,
receive_pcs4.logical_channel_address = (starting_channel_number + 4),
receive_pcs4.num_align_code_groups_in_ordered_set = 0,
receive_pcs4.num_align_cons_good_data = 16,
receive_pcs4.num_align_cons_pat = 4,
receive_pcs4.num_align_loss_sync_error = 17,
receive_pcs4.ph_fifo_low_latency_enable = "true",
receive_pcs4.ph_fifo_reg_mode = "true",
receive_pcs4.ph_fifo_xn_mapping0 = "none",
receive_pcs4.ph_fifo_xn_mapping1 = "up",
receive_pcs4.ph_fifo_xn_mapping2 = "none",
receive_pcs4.ph_fifo_xn_select = 1,
receive_pcs4.pipe_auto_speed_nego_enable = "true",
receive_pcs4.pipe_freq_scale_mode = "Frequency",
receive_pcs4.pma_done_count = 249950,
receive_pcs4.protocol_hint = "pcie2",
receive_pcs4.rate_match_almost_empty_threshold = 11,
receive_pcs4.rate_match_almost_full_threshold = 13,
receive_pcs4.rate_match_back_to_back = "false",
receive_pcs4.rate_match_delete_threshold = 13,
receive_pcs4.rate_match_empty_threshold = 5,
receive_pcs4.rate_match_fifo_mode = "true",
receive_pcs4.rate_match_full_threshold = 20,
receive_pcs4.rate_match_insert_threshold = 11,
receive_pcs4.rate_match_ordered_set_based = "false",
receive_pcs4.rate_match_pattern1 = "11010000111010000011",
receive_pcs4.rate_match_pattern2 = "00101111000101111100",
receive_pcs4.rate_match_pattern_size = 20,
receive_pcs4.rate_match_pipe_enable = "true",
receive_pcs4.rate_match_reset_enable = "false",
receive_pcs4.rate_match_skip_set_based = "true",
receive_pcs4.rate_match_start_threshold = 7,
receive_pcs4.rd_clk_mux_select = "int clock",
receive_pcs4.recovered_clk_mux_select = "recovered clock",
receive_pcs4.run_length = 40,
receive_pcs4.run_length_enable = "true",
receive_pcs4.rx_detect_bypass = "false",
receive_pcs4.rx_phfifo_wait_cnt = 32,
receive_pcs4.rxstatus_error_report_mode = 1,
receive_pcs4.self_test_mode = "incremental",
receive_pcs4.use_alignment_state_machine = "true",
receive_pcs4.use_deserializer_double_data_mode = "false",
receive_pcs4.use_deskew_fifo = "false",
receive_pcs4.use_double_data_mode = "false",
receive_pcs4.use_parallel_loopback = "false",
receive_pcs4.use_rising_edge_triggered_pattern_align = "false",
receive_pcs4.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs5
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs5_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs5_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[17:15]),
.autospdxnspdchg(int_rx_autospdxnspdchg[17:15]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs5_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs5_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs5_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[119:100]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[5]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[2399:2000]),
.dprioout(wire_receive_pcs5_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[5]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[5]),
.hipdataout(wire_receive_pcs5_hipdataout),
.hipdatavalid(wire_receive_pcs5_hipdatavalid),
.hipelecidle(wire_receive_pcs5_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs5_hipphydonestatus),
.hippowerdown(powerdn[11:10]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs5_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[11:10]),
.iqpphfifobyteselout(wire_receive_pcs5_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs5_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs5_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs5_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs5_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[11:10]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[11:10]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[11:10]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[11:10]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[11:10]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs5_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs5_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[5]),
.phfifordenableout(wire_receive_pcs5_phfifordenableout),
.phfiforeset(rx_phfiforeset[5]),
.phfiforesetout(wire_receive_pcs5_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[5]),
.phfifowrdisableout(wire_receive_pcs5_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[17:15]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[17:15]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[17:15]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[17:15]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[17:15]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[5]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[11:10]),
.pipepowerstate(tx_pipepowerstateout[23:20]),
.pipestatetransdoneout(wire_receive_pcs5_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[5]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(wire_receive_pcs5_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[5]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs5_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[5]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[5]),
.rxfound(rx_pcs_rxfound_wire[11:10]),
.signaldetect(wire_receive_pcs5_signaldetect),
.signaldetected(rx_signaldetect_wire[5]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs5.align_pattern = "0101111100",
receive_pcs5.align_pattern_length = 10,
receive_pcs5.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs5.allow_align_polarity_inversion = "false",
receive_pcs5.allow_pipe_polarity_inversion = "true",
receive_pcs5.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs5.auto_spd_phystatus_notify_count = 14,
receive_pcs5.auto_spd_self_switch_enable = "true",
receive_pcs5.bit_slip_enable = "false",
receive_pcs5.byte_order_double_data_mode_mask_enable = "false",
receive_pcs5.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs5.byte_order_mode = "none",
receive_pcs5.byte_order_pad_pattern = "0",
receive_pcs5.byte_order_pattern = "0",
receive_pcs5.byte_order_pld_ctrl_enable = "false",
receive_pcs5.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs5.cdrctrl_cid_mode_enable = "true",
receive_pcs5.cdrctrl_enable = "true",
receive_pcs5.cdrctrl_rxvalid_mask = "true",
receive_pcs5.channel_bonding = "x8",
receive_pcs5.channel_number = ((starting_channel_number + 5) % 4),
receive_pcs5.channel_width = 8,
receive_pcs5.clk1_mux_select = "recovered clock",
receive_pcs5.clk2_mux_select = "digital reference clock",
receive_pcs5.core_clock_0ppm = "false",
receive_pcs5.datapath_low_latency_mode = "false",
receive_pcs5.datapath_protocol = "pipe",
receive_pcs5.dec_8b_10b_compatibility_mode = "true",
receive_pcs5.dec_8b_10b_mode = "normal",
receive_pcs5.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs5.deskew_pattern = "0",
receive_pcs5.disable_auto_idle_insertion = "false",
receive_pcs5.disable_running_disp_in_word_align = "false",
receive_pcs5.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs5.dprio_config_mode = 6'h01,
receive_pcs5.elec_idle_gen1_sigdet_enable = "true",
receive_pcs5.elec_idle_infer_enable = "false",
receive_pcs5.elec_idle_num_com_detect = 3,
receive_pcs5.enable_bit_reversal = "false",
receive_pcs5.enable_deep_align = "false",
receive_pcs5.enable_deep_align_byte_swap = "false",
receive_pcs5.enable_self_test_mode = "false",
receive_pcs5.enable_true_complement_match_in_word_align = "false",
receive_pcs5.force_signal_detect_dig = "true",
receive_pcs5.hip_enable = "true",
receive_pcs5.infiniband_invalid_code = 0,
receive_pcs5.insert_pad_on_underflow = "false",
receive_pcs5.logical_channel_address = (starting_channel_number + 5),
receive_pcs5.num_align_code_groups_in_ordered_set = 0,
receive_pcs5.num_align_cons_good_data = 16,
receive_pcs5.num_align_cons_pat = 4,
receive_pcs5.num_align_loss_sync_error = 17,
receive_pcs5.ph_fifo_low_latency_enable = "true",
receive_pcs5.ph_fifo_reg_mode = "true",
receive_pcs5.ph_fifo_xn_mapping0 = "none",
receive_pcs5.ph_fifo_xn_mapping1 = "up",
receive_pcs5.ph_fifo_xn_mapping2 = "none",
receive_pcs5.ph_fifo_xn_select = 1,
receive_pcs5.pipe_auto_speed_nego_enable = "true",
receive_pcs5.pipe_freq_scale_mode = "Frequency",
receive_pcs5.pma_done_count = 249950,
receive_pcs5.protocol_hint = "pcie2",
receive_pcs5.rate_match_almost_empty_threshold = 11,
receive_pcs5.rate_match_almost_full_threshold = 13,
receive_pcs5.rate_match_back_to_back = "false",
receive_pcs5.rate_match_delete_threshold = 13,
receive_pcs5.rate_match_empty_threshold = 5,
receive_pcs5.rate_match_fifo_mode = "true",
receive_pcs5.rate_match_full_threshold = 20,
receive_pcs5.rate_match_insert_threshold = 11,
receive_pcs5.rate_match_ordered_set_based = "false",
receive_pcs5.rate_match_pattern1 = "11010000111010000011",
receive_pcs5.rate_match_pattern2 = "00101111000101111100",
receive_pcs5.rate_match_pattern_size = 20,
receive_pcs5.rate_match_pipe_enable = "true",
receive_pcs5.rate_match_reset_enable = "false",
receive_pcs5.rate_match_skip_set_based = "true",
receive_pcs5.rate_match_start_threshold = 7,
receive_pcs5.rd_clk_mux_select = "int clock",
receive_pcs5.recovered_clk_mux_select = "recovered clock",
receive_pcs5.run_length = 40,
receive_pcs5.run_length_enable = "true",
receive_pcs5.rx_detect_bypass = "false",
receive_pcs5.rx_phfifo_wait_cnt = 32,
receive_pcs5.rxstatus_error_report_mode = 1,
receive_pcs5.self_test_mode = "incremental",
receive_pcs5.use_alignment_state_machine = "true",
receive_pcs5.use_deserializer_double_data_mode = "false",
receive_pcs5.use_deskew_fifo = "false",
receive_pcs5.use_double_data_mode = "false",
receive_pcs5.use_parallel_loopback = "false",
receive_pcs5.use_rising_edge_triggered_pattern_align = "false",
receive_pcs5.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs6
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs6_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs6_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[20:18]),
.autospdxnspdchg(int_rx_autospdxnspdchg[20:18]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs6_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs6_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs6_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[139:120]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[6]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[2799:2400]),
.dprioout(wire_receive_pcs6_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[6]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[6]),
.hipdataout(wire_receive_pcs6_hipdataout),
.hipdatavalid(wire_receive_pcs6_hipdatavalid),
.hipelecidle(wire_receive_pcs6_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs6_hipphydonestatus),
.hippowerdown(powerdn[13:12]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs6_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[13:12]),
.iqpphfifobyteselout(wire_receive_pcs6_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs6_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs6_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs6_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs6_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[13:12]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[13:12]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[13:12]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[13:12]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[13:12]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs6_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs6_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[6]),
.phfifordenableout(wire_receive_pcs6_phfifordenableout),
.phfiforeset(rx_phfiforeset[6]),
.phfiforesetout(wire_receive_pcs6_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[6]),
.phfifowrdisableout(wire_receive_pcs6_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[20:18]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[20:18]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[20:18]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[20:18]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[20:18]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[6]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[13:12]),
.pipepowerstate(tx_pipepowerstateout[27:24]),
.pipestatetransdoneout(wire_receive_pcs6_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[6]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(wire_receive_pcs6_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[6]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs6_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[6]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[6]),
.rxfound(rx_pcs_rxfound_wire[13:12]),
.signaldetect(wire_receive_pcs6_signaldetect),
.signaldetected(rx_signaldetect_wire[6]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs6.align_pattern = "0101111100",
receive_pcs6.align_pattern_length = 10,
receive_pcs6.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs6.allow_align_polarity_inversion = "false",
receive_pcs6.allow_pipe_polarity_inversion = "true",
receive_pcs6.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs6.auto_spd_phystatus_notify_count = 14,
receive_pcs6.auto_spd_self_switch_enable = "true",
receive_pcs6.bit_slip_enable = "false",
receive_pcs6.byte_order_double_data_mode_mask_enable = "false",
receive_pcs6.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs6.byte_order_mode = "none",
receive_pcs6.byte_order_pad_pattern = "0",
receive_pcs6.byte_order_pattern = "0",
receive_pcs6.byte_order_pld_ctrl_enable = "false",
receive_pcs6.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs6.cdrctrl_cid_mode_enable = "true",
receive_pcs6.cdrctrl_enable = "true",
receive_pcs6.cdrctrl_rxvalid_mask = "true",
receive_pcs6.channel_bonding = "x8",
receive_pcs6.channel_number = ((starting_channel_number + 6) % 4),
receive_pcs6.channel_width = 8,
receive_pcs6.clk1_mux_select = "recovered clock",
receive_pcs6.clk2_mux_select = "digital reference clock",
receive_pcs6.core_clock_0ppm = "false",
receive_pcs6.datapath_low_latency_mode = "false",
receive_pcs6.datapath_protocol = "pipe",
receive_pcs6.dec_8b_10b_compatibility_mode = "true",
receive_pcs6.dec_8b_10b_mode = "normal",
receive_pcs6.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs6.deskew_pattern = "0",
receive_pcs6.disable_auto_idle_insertion = "false",
receive_pcs6.disable_running_disp_in_word_align = "false",
receive_pcs6.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs6.dprio_config_mode = 6'h01,
receive_pcs6.elec_idle_gen1_sigdet_enable = "true",
receive_pcs6.elec_idle_infer_enable = "false",
receive_pcs6.elec_idle_num_com_detect = 3,
receive_pcs6.enable_bit_reversal = "false",
receive_pcs6.enable_deep_align = "false",
receive_pcs6.enable_deep_align_byte_swap = "false",
receive_pcs6.enable_self_test_mode = "false",
receive_pcs6.enable_true_complement_match_in_word_align = "false",
receive_pcs6.force_signal_detect_dig = "true",
receive_pcs6.hip_enable = "true",
receive_pcs6.infiniband_invalid_code = 0,
receive_pcs6.insert_pad_on_underflow = "false",
receive_pcs6.logical_channel_address = (starting_channel_number + 6),
receive_pcs6.num_align_code_groups_in_ordered_set = 0,
receive_pcs6.num_align_cons_good_data = 16,
receive_pcs6.num_align_cons_pat = 4,
receive_pcs6.num_align_loss_sync_error = 17,
receive_pcs6.ph_fifo_low_latency_enable = "true",
receive_pcs6.ph_fifo_reg_mode = "true",
receive_pcs6.ph_fifo_xn_mapping0 = "none",
receive_pcs6.ph_fifo_xn_mapping1 = "up",
receive_pcs6.ph_fifo_xn_mapping2 = "none",
receive_pcs6.ph_fifo_xn_select = 1,
receive_pcs6.pipe_auto_speed_nego_enable = "true",
receive_pcs6.pipe_freq_scale_mode = "Frequency",
receive_pcs6.pma_done_count = 249950,
receive_pcs6.protocol_hint = "pcie2",
receive_pcs6.rate_match_almost_empty_threshold = 11,
receive_pcs6.rate_match_almost_full_threshold = 13,
receive_pcs6.rate_match_back_to_back = "false",
receive_pcs6.rate_match_delete_threshold = 13,
receive_pcs6.rate_match_empty_threshold = 5,
receive_pcs6.rate_match_fifo_mode = "true",
receive_pcs6.rate_match_full_threshold = 20,
receive_pcs6.rate_match_insert_threshold = 11,
receive_pcs6.rate_match_ordered_set_based = "false",
receive_pcs6.rate_match_pattern1 = "11010000111010000011",
receive_pcs6.rate_match_pattern2 = "00101111000101111100",
receive_pcs6.rate_match_pattern_size = 20,
receive_pcs6.rate_match_pipe_enable = "true",
receive_pcs6.rate_match_reset_enable = "false",
receive_pcs6.rate_match_skip_set_based = "true",
receive_pcs6.rate_match_start_threshold = 7,
receive_pcs6.rd_clk_mux_select = "int clock",
receive_pcs6.recovered_clk_mux_select = "recovered clock",
receive_pcs6.run_length = 40,
receive_pcs6.run_length_enable = "true",
receive_pcs6.rx_detect_bypass = "false",
receive_pcs6.rx_phfifo_wait_cnt = 32,
receive_pcs6.rxstatus_error_report_mode = 1,
receive_pcs6.self_test_mode = "incremental",
receive_pcs6.use_alignment_state_machine = "true",
receive_pcs6.use_deserializer_double_data_mode = "false",
receive_pcs6.use_deskew_fifo = "false",
receive_pcs6.use_double_data_mode = "false",
receive_pcs6.use_parallel_loopback = "false",
receive_pcs6.use_rising_edge_triggered_pattern_align = "false",
receive_pcs6.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs7
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs7_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs7_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[23:21]),
.autospdxnspdchg(int_rx_autospdxnspdchg[23:21]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs7_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs7_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs7_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[159:140]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[7]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[3199:2800]),
.dprioout(wire_receive_pcs7_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[7]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[7]),
.hipdataout(wire_receive_pcs7_hipdataout),
.hipdatavalid(wire_receive_pcs7_hipdatavalid),
.hipelecidle(wire_receive_pcs7_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs7_hipphydonestatus),
.hippowerdown(powerdn[15:14]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs7_hipstatus),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[15:14]),
.iqpphfifobyteselout(wire_receive_pcs7_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs7_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs7_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs7_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs7_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[15:14]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[15:14]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[15:14]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[15:14]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[15:14]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs7_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs7_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[7]),
.phfifordenableout(wire_receive_pcs7_phfifordenableout),
.phfiforeset(rx_phfiforeset[7]),
.phfiforesetout(wire_receive_pcs7_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[7]),
.phfifowrdisableout(wire_receive_pcs7_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[23:21]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[23:21]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[23:21]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[23:21]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[23:21]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[7]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[15:14]),
.pipepowerstate(tx_pipepowerstateout[31:28]),
.pipestatetransdoneout(wire_receive_pcs7_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[7]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(wire_receive_pcs7_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[7]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs7_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[7]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[7]),
.rxfound(rx_pcs_rxfound_wire[15:14]),
.signaldetect(wire_receive_pcs7_signaldetect),
.signaldetected(rx_signaldetect_wire[7]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs7.align_pattern = "0101111100",
receive_pcs7.align_pattern_length = 10,
receive_pcs7.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs7.allow_align_polarity_inversion = "false",
receive_pcs7.allow_pipe_polarity_inversion = "true",
receive_pcs7.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs7.auto_spd_phystatus_notify_count = 14,
receive_pcs7.auto_spd_self_switch_enable = "true",
receive_pcs7.bit_slip_enable = "false",
receive_pcs7.byte_order_double_data_mode_mask_enable = "false",
receive_pcs7.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs7.byte_order_mode = "none",
receive_pcs7.byte_order_pad_pattern = "0",
receive_pcs7.byte_order_pattern = "0",
receive_pcs7.byte_order_pld_ctrl_enable = "false",
receive_pcs7.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs7.cdrctrl_cid_mode_enable = "true",
receive_pcs7.cdrctrl_enable = "true",
receive_pcs7.cdrctrl_rxvalid_mask = "true",
receive_pcs7.channel_bonding = "x8",
receive_pcs7.channel_number = ((starting_channel_number + 7) % 4),
receive_pcs7.channel_width = 8,
receive_pcs7.clk1_mux_select = "recovered clock",
receive_pcs7.clk2_mux_select = "digital reference clock",
receive_pcs7.core_clock_0ppm = "false",
receive_pcs7.datapath_low_latency_mode = "false",
receive_pcs7.datapath_protocol = "pipe",
receive_pcs7.dec_8b_10b_compatibility_mode = "true",
receive_pcs7.dec_8b_10b_mode = "normal",
receive_pcs7.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs7.deskew_pattern = "0",
receive_pcs7.disable_auto_idle_insertion = "false",
receive_pcs7.disable_running_disp_in_word_align = "false",
receive_pcs7.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs7.dprio_config_mode = 6'h01,
receive_pcs7.elec_idle_gen1_sigdet_enable = "true",
receive_pcs7.elec_idle_infer_enable = "false",
receive_pcs7.elec_idle_num_com_detect = 3,
receive_pcs7.enable_bit_reversal = "false",
receive_pcs7.enable_deep_align = "false",
receive_pcs7.enable_deep_align_byte_swap = "false",
receive_pcs7.enable_self_test_mode = "false",
receive_pcs7.enable_true_complement_match_in_word_align = "false",
receive_pcs7.force_signal_detect_dig = "true",
receive_pcs7.hip_enable = "true",
receive_pcs7.infiniband_invalid_code = 0,
receive_pcs7.insert_pad_on_underflow = "false",
receive_pcs7.logical_channel_address = (starting_channel_number + 7),
receive_pcs7.num_align_code_groups_in_ordered_set = 0,
receive_pcs7.num_align_cons_good_data = 16,
receive_pcs7.num_align_cons_pat = 4,
receive_pcs7.num_align_loss_sync_error = 17,
receive_pcs7.ph_fifo_low_latency_enable = "true",
receive_pcs7.ph_fifo_reg_mode = "true",
receive_pcs7.ph_fifo_xn_mapping0 = "none",
receive_pcs7.ph_fifo_xn_mapping1 = "up",
receive_pcs7.ph_fifo_xn_mapping2 = "none",
receive_pcs7.ph_fifo_xn_select = 1,
receive_pcs7.pipe_auto_speed_nego_enable = "true",
receive_pcs7.pipe_freq_scale_mode = "Frequency",
receive_pcs7.pma_done_count = 249950,
receive_pcs7.protocol_hint = "pcie2",
receive_pcs7.rate_match_almost_empty_threshold = 11,
receive_pcs7.rate_match_almost_full_threshold = 13,
receive_pcs7.rate_match_back_to_back = "false",
receive_pcs7.rate_match_delete_threshold = 13,
receive_pcs7.rate_match_empty_threshold = 5,
receive_pcs7.rate_match_fifo_mode = "true",
receive_pcs7.rate_match_full_threshold = 20,
receive_pcs7.rate_match_insert_threshold = 11,
receive_pcs7.rate_match_ordered_set_based = "false",
receive_pcs7.rate_match_pattern1 = "11010000111010000011",
receive_pcs7.rate_match_pattern2 = "00101111000101111100",
receive_pcs7.rate_match_pattern_size = 20,
receive_pcs7.rate_match_pipe_enable = "true",
receive_pcs7.rate_match_reset_enable = "false",
receive_pcs7.rate_match_skip_set_based = "true",
receive_pcs7.rate_match_start_threshold = 7,
receive_pcs7.rd_clk_mux_select = "int clock",
receive_pcs7.recovered_clk_mux_select = "recovered clock",
receive_pcs7.run_length = 40,
receive_pcs7.run_length_enable = "true",
receive_pcs7.rx_detect_bypass = "false",
receive_pcs7.rx_phfifo_wait_cnt = 32,
receive_pcs7.rxstatus_error_report_mode = 1,
receive_pcs7.self_test_mode = "incremental",
receive_pcs7.use_alignment_state_machine = "true",
receive_pcs7.use_deserializer_double_data_mode = "false",
receive_pcs7.use_deskew_fifo = "false",
receive_pcs7.use_double_data_mode = "false",
receive_pcs7.use_parallel_loopback = "false",
receive_pcs7.use_rising_edge_triggered_pattern_align = "false",
receive_pcs7.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.adaptive_equalization_mode = "none",
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "true",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.eyemon_bandwidth = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "pcie2",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis = 4,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 3,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_external_termination = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma1
(
.adaptdone(),
.analogtestbus(wire_receive_pma1_analogtestbus),
.clockout(wire_receive_pma1_clockout),
.datain(rx_datain[1]),
.dataout(wire_receive_pma1_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[7:4]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[599:300]),
.dprioout(wire_receive_pma1_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[1]),
.locktoref(rx_locktorefclk_wire[1]),
.locktorefout(wire_receive_pma1_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[1]),
.powerdn(cent_unit_rxibpowerdn[1]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
.recoverdatain(pll_ch_dataout_wire[3:2]),
.recoverdataout(wire_receive_pma1_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[1]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma1_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma1.adaptive_equalization_mode = "none",
receive_pma1.allow_serial_loopback = "false",
receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
receive_pma1.channel_type = "auto",
receive_pma1.common_mode = "0.82V",
receive_pma1.deserialization_factor = 10,
receive_pma1.dprio_config_mode = 6'h01,
receive_pma1.enable_ltd = "false",
receive_pma1.enable_ltr = "true",
receive_pma1.eq_dc_gain = 3,
receive_pma1.eqa_ctrl = 0,
receive_pma1.eqb_ctrl = 0,
receive_pma1.eqc_ctrl = 0,
receive_pma1.eqd_ctrl = 0,
receive_pma1.eqv_ctrl = 0,
receive_pma1.eyemon_bandwidth = 0,
receive_pma1.force_signal_detect = "true",
receive_pma1.logical_channel_address = (starting_channel_number + 1),
receive_pma1.low_speed_test_select = 0,
receive_pma1.offset_cancellation = 1,
receive_pma1.ppmselect = 32,
receive_pma1.protocol_hint = "pcie2",
receive_pma1.send_direct_reverse_serial_loopback = "None",
receive_pma1.signal_detect_hysteresis = 4,
receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
receive_pma1.signal_detect_loss_threshold = 3,
receive_pma1.termination = "OCT 100 Ohms",
receive_pma1.use_deser_double_data_width = "false",
receive_pma1.use_external_termination = "false",
receive_pma1.use_pma_direct = "false",
receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma2
(
.adaptdone(),
.analogtestbus(wire_receive_pma2_analogtestbus),
.clockout(wire_receive_pma2_clockout),
.datain(rx_datain[2]),
.dataout(wire_receive_pma2_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[11:8]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[899:600]),
.dprioout(wire_receive_pma2_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[2]),
.locktoref(rx_locktorefclk_wire[2]),
.locktorefout(wire_receive_pma2_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[2]),
.powerdn(cent_unit_rxibpowerdn[2]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
.recoverdatain(pll_ch_dataout_wire[5:4]),
.recoverdataout(wire_receive_pma2_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[2]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma2_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma2.adaptive_equalization_mode = "none",
receive_pma2.allow_serial_loopback = "false",
receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
receive_pma2.channel_type = "auto",
receive_pma2.common_mode = "0.82V",
receive_pma2.deserialization_factor = 10,
receive_pma2.dprio_config_mode = 6'h01,
receive_pma2.enable_ltd = "false",
receive_pma2.enable_ltr = "true",
receive_pma2.eq_dc_gain = 3,
receive_pma2.eqa_ctrl = 0,
receive_pma2.eqb_ctrl = 0,
receive_pma2.eqc_ctrl = 0,
receive_pma2.eqd_ctrl = 0,
receive_pma2.eqv_ctrl = 0,
receive_pma2.eyemon_bandwidth = 0,
receive_pma2.force_signal_detect = "true",
receive_pma2.logical_channel_address = (starting_channel_number + 2),
receive_pma2.low_speed_test_select = 0,
receive_pma2.offset_cancellation = 1,
receive_pma2.ppmselect = 32,
receive_pma2.protocol_hint = "pcie2",
receive_pma2.send_direct_reverse_serial_loopback = "None",
receive_pma2.signal_detect_hysteresis = 4,
receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
receive_pma2.signal_detect_loss_threshold = 3,
receive_pma2.termination = "OCT 100 Ohms",
receive_pma2.use_deser_double_data_width = "false",
receive_pma2.use_external_termination = "false",
receive_pma2.use_pma_direct = "false",
receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma3
(
.adaptdone(),
.analogtestbus(wire_receive_pma3_analogtestbus),
.clockout(wire_receive_pma3_clockout),
.datain(rx_datain[3]),
.dataout(wire_receive_pma3_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[15:12]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[1199:900]),
.dprioout(wire_receive_pma3_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[3]),
.locktoref(rx_locktorefclk_wire[3]),
.locktorefout(wire_receive_pma3_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[3]),
.powerdn(cent_unit_rxibpowerdn[3]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
.recoverdatain(pll_ch_dataout_wire[7:6]),
.recoverdataout(wire_receive_pma3_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[3]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma3_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma3.adaptive_equalization_mode = "none",
receive_pma3.allow_serial_loopback = "false",
receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
receive_pma3.channel_type = "auto",
receive_pma3.common_mode = "0.82V",
receive_pma3.deserialization_factor = 10,
receive_pma3.dprio_config_mode = 6'h01,
receive_pma3.enable_ltd = "false",
receive_pma3.enable_ltr = "true",
receive_pma3.eq_dc_gain = 3,
receive_pma3.eqa_ctrl = 0,
receive_pma3.eqb_ctrl = 0,
receive_pma3.eqc_ctrl = 0,
receive_pma3.eqd_ctrl = 0,
receive_pma3.eqv_ctrl = 0,
receive_pma3.eyemon_bandwidth = 0,
receive_pma3.force_signal_detect = "true",
receive_pma3.logical_channel_address = (starting_channel_number + 3),
receive_pma3.low_speed_test_select = 0,
receive_pma3.offset_cancellation = 1,
receive_pma3.ppmselect = 32,
receive_pma3.protocol_hint = "pcie2",
receive_pma3.send_direct_reverse_serial_loopback = "None",
receive_pma3.signal_detect_hysteresis = 4,
receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
receive_pma3.signal_detect_loss_threshold = 3,
receive_pma3.termination = "OCT 100 Ohms",
receive_pma3.use_deser_double_data_width = "false",
receive_pma3.use_external_termination = "false",
receive_pma3.use_pma_direct = "false",
receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma4
(
.adaptdone(),
.analogtestbus(wire_receive_pma4_analogtestbus),
.clockout(wire_receive_pma4_clockout),
.datain(rx_datain[4]),
.dataout(wire_receive_pma4_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[19:16]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2099:1800]),
.dprioout(wire_receive_pma4_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[4]),
.locktoref(rx_locktorefclk_wire[4]),
.locktorefout(wire_receive_pma4_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[4]),
.powerdn(cent_unit_rxibpowerdn[6]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[4]),
.recoverdatain(pll_ch_dataout_wire[9:8]),
.recoverdataout(wire_receive_pma4_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[6]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma4_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma4.adaptive_equalization_mode = "none",
receive_pma4.allow_serial_loopback = "false",
receive_pma4.channel_number = ((starting_channel_number + 4) % 4),
receive_pma4.channel_type = "auto",
receive_pma4.common_mode = "0.82V",
receive_pma4.deserialization_factor = 10,
receive_pma4.dprio_config_mode = 6'h01,
receive_pma4.enable_ltd = "false",
receive_pma4.enable_ltr = "true",
receive_pma4.eq_dc_gain = 3,
receive_pma4.eqa_ctrl = 0,
receive_pma4.eqb_ctrl = 0,
receive_pma4.eqc_ctrl = 0,
receive_pma4.eqd_ctrl = 0,
receive_pma4.eqv_ctrl = 0,
receive_pma4.eyemon_bandwidth = 0,
receive_pma4.force_signal_detect = "true",
receive_pma4.logical_channel_address = (starting_channel_number + 4),
receive_pma4.low_speed_test_select = 0,
receive_pma4.offset_cancellation = 1,
receive_pma4.ppmselect = 32,
receive_pma4.protocol_hint = "pcie2",
receive_pma4.send_direct_reverse_serial_loopback = "None",
receive_pma4.signal_detect_hysteresis = 4,
receive_pma4.signal_detect_hysteresis_valid_threshold = 14,
receive_pma4.signal_detect_loss_threshold = 3,
receive_pma4.termination = "OCT 100 Ohms",
receive_pma4.use_deser_double_data_width = "false",
receive_pma4.use_external_termination = "false",
receive_pma4.use_pma_direct = "false",
receive_pma4.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma5
(
.adaptdone(),
.analogtestbus(wire_receive_pma5_analogtestbus),
.clockout(wire_receive_pma5_clockout),
.datain(rx_datain[5]),
.dataout(wire_receive_pma5_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[23:20]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2399:2100]),
.dprioout(wire_receive_pma5_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[5]),
.locktoref(rx_locktorefclk_wire[5]),
.locktorefout(wire_receive_pma5_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[5]),
.powerdn(cent_unit_rxibpowerdn[7]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[5]),
.recoverdatain(pll_ch_dataout_wire[11:10]),
.recoverdataout(wire_receive_pma5_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[7]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma5_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma5.adaptive_equalization_mode = "none",
receive_pma5.allow_serial_loopback = "false",
receive_pma5.channel_number = ((starting_channel_number + 5) % 4),
receive_pma5.channel_type = "auto",
receive_pma5.common_mode = "0.82V",
receive_pma5.deserialization_factor = 10,
receive_pma5.dprio_config_mode = 6'h01,
receive_pma5.enable_ltd = "false",
receive_pma5.enable_ltr = "true",
receive_pma5.eq_dc_gain = 3,
receive_pma5.eqa_ctrl = 0,
receive_pma5.eqb_ctrl = 0,
receive_pma5.eqc_ctrl = 0,
receive_pma5.eqd_ctrl = 0,
receive_pma5.eqv_ctrl = 0,
receive_pma5.eyemon_bandwidth = 0,
receive_pma5.force_signal_detect = "true",
receive_pma5.logical_channel_address = (starting_channel_number + 5),
receive_pma5.low_speed_test_select = 0,
receive_pma5.offset_cancellation = 1,
receive_pma5.ppmselect = 32,
receive_pma5.protocol_hint = "pcie2",
receive_pma5.send_direct_reverse_serial_loopback = "None",
receive_pma5.signal_detect_hysteresis = 4,
receive_pma5.signal_detect_hysteresis_valid_threshold = 14,
receive_pma5.signal_detect_loss_threshold = 3,
receive_pma5.termination = "OCT 100 Ohms",
receive_pma5.use_deser_double_data_width = "false",
receive_pma5.use_external_termination = "false",
receive_pma5.use_pma_direct = "false",
receive_pma5.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma6
(
.adaptdone(),
.analogtestbus(wire_receive_pma6_analogtestbus),
.clockout(wire_receive_pma6_clockout),
.datain(rx_datain[6]),
.dataout(wire_receive_pma6_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[27:24]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2699:2400]),
.dprioout(wire_receive_pma6_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[6]),
.locktoref(rx_locktorefclk_wire[6]),
.locktorefout(wire_receive_pma6_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[6]),
.powerdn(cent_unit_rxibpowerdn[8]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[6]),
.recoverdatain(pll_ch_dataout_wire[13:12]),
.recoverdataout(wire_receive_pma6_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[8]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma6_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma6.adaptive_equalization_mode = "none",
receive_pma6.allow_serial_loopback = "false",
receive_pma6.channel_number = ((starting_channel_number + 6) % 4),
receive_pma6.channel_type = "auto",
receive_pma6.common_mode = "0.82V",
receive_pma6.deserialization_factor = 10,
receive_pma6.dprio_config_mode = 6'h01,
receive_pma6.enable_ltd = "false",
receive_pma6.enable_ltr = "true",
receive_pma6.eq_dc_gain = 3,
receive_pma6.eqa_ctrl = 0,
receive_pma6.eqb_ctrl = 0,
receive_pma6.eqc_ctrl = 0,
receive_pma6.eqd_ctrl = 0,
receive_pma6.eqv_ctrl = 0,
receive_pma6.eyemon_bandwidth = 0,
receive_pma6.force_signal_detect = "true",
receive_pma6.logical_channel_address = (starting_channel_number + 6),
receive_pma6.low_speed_test_select = 0,
receive_pma6.offset_cancellation = 1,
receive_pma6.ppmselect = 32,
receive_pma6.protocol_hint = "pcie2",
receive_pma6.send_direct_reverse_serial_loopback = "None",
receive_pma6.signal_detect_hysteresis = 4,
receive_pma6.signal_detect_hysteresis_valid_threshold = 14,
receive_pma6.signal_detect_loss_threshold = 3,
receive_pma6.termination = "OCT 100 Ohms",
receive_pma6.use_deser_double_data_width = "false",
receive_pma6.use_external_termination = "false",
receive_pma6.use_pma_direct = "false",
receive_pma6.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma7
(
.adaptdone(),
.analogtestbus(wire_receive_pma7_analogtestbus),
.clockout(wire_receive_pma7_clockout),
.datain(rx_datain[7]),
.dataout(wire_receive_pma7_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[31:28]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2999:2700]),
.dprioout(wire_receive_pma7_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[7]),
.locktoref(rx_locktorefclk_wire[7]),
.locktorefout(wire_receive_pma7_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[7]),
.powerdn(cent_unit_rxibpowerdn[9]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[7]),
.recoverdatain(pll_ch_dataout_wire[15:14]),
.recoverdataout(wire_receive_pma7_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[9]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma7_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma7.adaptive_equalization_mode = "none",
receive_pma7.allow_serial_loopback = "false",
receive_pma7.channel_number = ((starting_channel_number + 7) % 4),
receive_pma7.channel_type = "auto",
receive_pma7.common_mode = "0.82V",
receive_pma7.deserialization_factor = 10,
receive_pma7.dprio_config_mode = 6'h01,
receive_pma7.enable_ltd = "false",
receive_pma7.enable_ltr = "true",
receive_pma7.eq_dc_gain = 3,
receive_pma7.eqa_ctrl = 0,
receive_pma7.eqb_ctrl = 0,
receive_pma7.eqc_ctrl = 0,
receive_pma7.eqd_ctrl = 0,
receive_pma7.eqv_ctrl = 0,
receive_pma7.eyemon_bandwidth = 0,
receive_pma7.force_signal_detect = "true",
receive_pma7.logical_channel_address = (starting_channel_number + 7),
receive_pma7.low_speed_test_select = 0,
receive_pma7.offset_cancellation = 1,
receive_pma7.ppmselect = 32,
receive_pma7.protocol_hint = "pcie2",
receive_pma7.send_direct_reverse_serial_loopback = "None",
receive_pma7.signal_detect_hysteresis = 4,
receive_pma7.signal_detect_hysteresis_valid_threshold = 14,
receive_pma7.signal_detect_loss_threshold = 3,
receive_pma7.termination = "OCT 100 Ohms",
receive_pma7.use_deser_double_data_width = "false",
receive_pma7.use_external_termination = "false",
receive_pma7.use_pma_direct = "false",
receive_pma7.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(),
.coreclkout(wire_transmit_pcs0_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[0], tx_ctrlenable[0], tx_datain_wire[7:0]}),
.hipdetectrxloop(tx_detectrxloop[0]),
.hipelecidleinfersel(rx_elecidleinfersel[2:0]),
.hipforceelecidle(tx_forceelecidle[0]),
.hippowerdn(powerdn[1:0]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[0]),
.hiptxmargin(tx_pipemargin[2:0]),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(wire_transmit_pcs0_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs0_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs0_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs0_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[1:0]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[1:0]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[1:0]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[1:0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[0]),
.pipetxswing(tx_pipeswing[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "true",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "x8",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "true",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "true",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "central",
transmit_pcs0.ph_fifo_xn_select = 2,
transmit_pcs0.pipe_auto_speed_nego_enable = "true",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.pipe_voltage_swing_control = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie2",
transmit_pcs0.refclk_select = "cmu_clock_divider",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "int_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs1
(
.clkout(),
.coreclkout(wire_transmit_pcs1_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs1_dataout),
.digitalreset(tx_digitalreset_out[1]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[299:150]),
.dprioout(wire_transmit_pcs1_dprioout),
.enrevparallellpbk(tx_revparallellpbken[1]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[1], tx_ctrlenable[1], tx_datain_wire[15:8]}),
.hipdetectrxloop(tx_detectrxloop[1]),
.hipelecidleinfersel(rx_elecidleinfersel[5:3]),
.hipforceelecidle(tx_forceelecidle[1]),
.hippowerdn(powerdn[3:2]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[1]),
.hiptxmargin(tx_pipemargin[5:3]),
.invpol(tx_invpolarity[1]),
.iqpphfifobyteselout(wire_transmit_pcs1_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs1_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs1_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs1_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[3:2]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[3:2]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[3:2]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[3:2]),
.localrefclk(tx_localrefclk[1]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[1]),
.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[1]),
.pipetxswing(tx_pipeswing[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
.txdetectrx(wire_transmit_pcs1_txdetectrx),
.xgmctrl(cent_unit_txctrlout[1]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs1.allow_polarity_inversion = "false",
transmit_pcs1.auto_spd_self_switch_enable = "true",
transmit_pcs1.bitslip_enable = "false",
transmit_pcs1.channel_bonding = "x8",
transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pcs1.channel_width = 8,
transmit_pcs1.core_clock_0ppm = "false",
transmit_pcs1.datapath_low_latency_mode = "false",
transmit_pcs1.datapath_protocol = "pipe",
transmit_pcs1.disable_ph_low_latency_mode = "false",
transmit_pcs1.disparity_mode = "new",
transmit_pcs1.dprio_config_mode = 6'h01,
transmit_pcs1.elec_idle_delay = 6,
transmit_pcs1.enable_bit_reversal = "false",
transmit_pcs1.enable_idle_selection = "false",
transmit_pcs1.enable_reverse_parallel_loopback = "true",
transmit_pcs1.enable_self_test_mode = "false",
transmit_pcs1.enable_symbol_swap = "false",
transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
transmit_pcs1.enc_8b_10b_mode = "normal",
transmit_pcs1.force_echar = "false",
transmit_pcs1.force_kchar = "false",
transmit_pcs1.hip_enable = "true",
transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
transmit_pcs1.ph_fifo_reg_mode = "true",
transmit_pcs1.ph_fifo_xn_mapping0 = "none",
transmit_pcs1.ph_fifo_xn_mapping1 = "none",
transmit_pcs1.ph_fifo_xn_mapping2 = "central",
transmit_pcs1.ph_fifo_xn_select = 2,
transmit_pcs1.pipe_auto_speed_nego_enable = "true",
transmit_pcs1.pipe_freq_scale_mode = "Frequency",
transmit_pcs1.pipe_voltage_swing_control = "false",
transmit_pcs1.prbs_cid_pattern = "false",
transmit_pcs1.protocol_hint = "pcie2",
transmit_pcs1.refclk_select = "cmu_clock_divider",
transmit_pcs1.self_test_mode = "incremental",
transmit_pcs1.use_double_data_mode = "false",
transmit_pcs1.use_serializer_double_data_mode = "false",
transmit_pcs1.wr_clk_mux_select = "int_clk",
transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs2
(
.clkout(),
.coreclkout(wire_transmit_pcs2_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs2_dataout),
.digitalreset(tx_digitalreset_out[2]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[449:300]),
.dprioout(wire_transmit_pcs2_dprioout),
.enrevparallellpbk(tx_revparallellpbken[2]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs2_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[2], tx_ctrlenable[2], tx_datain_wire[23:16]}),
.hipdetectrxloop(tx_detectrxloop[2]),
.hipelecidleinfersel(rx_elecidleinfersel[8:6]),
.hipforceelecidle(tx_forceelecidle[2]),
.hippowerdn(powerdn[5:4]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[2]),
.hiptxmargin(tx_pipemargin[8:6]),
.invpol(tx_invpolarity[2]),
.iqpphfifobyteselout(wire_transmit_pcs2_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs2_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs2_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs2_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[5:4]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[5:4]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[5:4]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[5:4]),
.localrefclk(tx_localrefclk[2]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[2]),
.phfiforesetout(wire_transmit_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
.pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[2]),
.pipetxswing(tx_pipeswing[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[59:40]),
.txdetectrx(wire_transmit_pcs2_txdetectrx),
.xgmctrl(cent_unit_txctrlout[2]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[23:16]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs2.allow_polarity_inversion = "false",
transmit_pcs2.auto_spd_self_switch_enable = "true",
transmit_pcs2.bitslip_enable = "false",
transmit_pcs2.channel_bonding = "x8",
transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pcs2.channel_width = 8,
transmit_pcs2.core_clock_0ppm = "false",
transmit_pcs2.datapath_low_latency_mode = "false",
transmit_pcs2.datapath_protocol = "pipe",
transmit_pcs2.disable_ph_low_latency_mode = "false",
transmit_pcs2.disparity_mode = "new",
transmit_pcs2.dprio_config_mode = 6'h01,
transmit_pcs2.elec_idle_delay = 6,
transmit_pcs2.enable_bit_reversal = "false",
transmit_pcs2.enable_idle_selection = "false",
transmit_pcs2.enable_reverse_parallel_loopback = "true",
transmit_pcs2.enable_self_test_mode = "false",
transmit_pcs2.enable_symbol_swap = "false",
transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
transmit_pcs2.enc_8b_10b_mode = "normal",
transmit_pcs2.force_echar = "false",
transmit_pcs2.force_kchar = "false",
transmit_pcs2.hip_enable = "true",
transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
transmit_pcs2.ph_fifo_reg_mode = "true",
transmit_pcs2.ph_fifo_xn_mapping0 = "none",
transmit_pcs2.ph_fifo_xn_mapping1 = "none",
transmit_pcs2.ph_fifo_xn_mapping2 = "central",
transmit_pcs2.ph_fifo_xn_select = 2,
transmit_pcs2.pipe_auto_speed_nego_enable = "true",
transmit_pcs2.pipe_freq_scale_mode = "Frequency",
transmit_pcs2.pipe_voltage_swing_control = "false",
transmit_pcs2.prbs_cid_pattern = "false",
transmit_pcs2.protocol_hint = "pcie2",
transmit_pcs2.refclk_select = "cmu_clock_divider",
transmit_pcs2.self_test_mode = "incremental",
transmit_pcs2.use_double_data_mode = "false",
transmit_pcs2.use_serializer_double_data_mode = "false",
transmit_pcs2.wr_clk_mux_select = "int_clk",
transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs3
(
.clkout(),
.coreclkout(wire_transmit_pcs3_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs3_dataout),
.digitalreset(tx_digitalreset_out[3]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[599:450]),
.dprioout(wire_transmit_pcs3_dprioout),
.enrevparallellpbk(tx_revparallellpbken[3]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs3_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[3], tx_ctrlenable[3], tx_datain_wire[31:24]}),
.hipdetectrxloop(tx_detectrxloop[3]),
.hipelecidleinfersel(rx_elecidleinfersel[11:9]),
.hipforceelecidle(tx_forceelecidle[3]),
.hippowerdn(powerdn[7:6]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[3]),
.hiptxmargin(tx_pipemargin[11:9]),
.invpol(tx_invpolarity[3]),
.iqpphfifobyteselout(wire_transmit_pcs3_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs3_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs3_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs3_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[7:6]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[7:6]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[7:6]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[7:6]),
.localrefclk(tx_localrefclk[3]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[3]),
.phfiforesetout(wire_transmit_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
.pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[3]),
.pipetxswing(tx_pipeswing[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[79:60]),
.txdetectrx(wire_transmit_pcs3_txdetectrx),
.xgmctrl(cent_unit_txctrlout[3]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[31:24]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs3.allow_polarity_inversion = "false",
transmit_pcs3.auto_spd_self_switch_enable = "true",
transmit_pcs3.bitslip_enable = "false",
transmit_pcs3.channel_bonding = "x8",
transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pcs3.channel_width = 8,
transmit_pcs3.core_clock_0ppm = "false",
transmit_pcs3.datapath_low_latency_mode = "false",
transmit_pcs3.datapath_protocol = "pipe",
transmit_pcs3.disable_ph_low_latency_mode = "false",
transmit_pcs3.disparity_mode = "new",
transmit_pcs3.dprio_config_mode = 6'h01,
transmit_pcs3.elec_idle_delay = 6,
transmit_pcs3.enable_bit_reversal = "false",
transmit_pcs3.enable_idle_selection = "false",
transmit_pcs3.enable_reverse_parallel_loopback = "true",
transmit_pcs3.enable_self_test_mode = "false",
transmit_pcs3.enable_symbol_swap = "false",
transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
transmit_pcs3.enc_8b_10b_mode = "normal",
transmit_pcs3.force_echar = "false",
transmit_pcs3.force_kchar = "false",
transmit_pcs3.hip_enable = "true",
transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
transmit_pcs3.ph_fifo_reg_mode = "true",
transmit_pcs3.ph_fifo_xn_mapping0 = "none",
transmit_pcs3.ph_fifo_xn_mapping1 = "none",
transmit_pcs3.ph_fifo_xn_mapping2 = "central",
transmit_pcs3.ph_fifo_xn_select = 2,
transmit_pcs3.pipe_auto_speed_nego_enable = "true",
transmit_pcs3.pipe_freq_scale_mode = "Frequency",
transmit_pcs3.pipe_voltage_swing_control = "false",
transmit_pcs3.prbs_cid_pattern = "false",
transmit_pcs3.protocol_hint = "pcie2",
transmit_pcs3.refclk_select = "cmu_clock_divider",
transmit_pcs3.self_test_mode = "incremental",
transmit_pcs3.use_double_data_mode = "false",
transmit_pcs3.use_serializer_double_data_mode = "false",
transmit_pcs3.wr_clk_mux_select = "int_clk",
transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs4
(
.clkout(),
.coreclkout(wire_transmit_pcs4_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs4_dataout),
.digitalreset(tx_digitalreset_out[4]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[749:600]),
.dprioout(wire_transmit_pcs4_dprioout),
.enrevparallellpbk(tx_revparallellpbken[4]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs4_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs4_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[4], tx_ctrlenable[4], tx_datain_wire[39:32]}),
.hipdetectrxloop(tx_detectrxloop[4]),
.hipelecidleinfersel(rx_elecidleinfersel[14:12]),
.hipforceelecidle(tx_forceelecidle[4]),
.hippowerdn(powerdn[9:8]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[4]),
.hiptxmargin(tx_pipemargin[14:12]),
.invpol(tx_invpolarity[4]),
.iqpphfifobyteselout(wire_transmit_pcs4_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs4_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs4_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs4_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[9:8]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[9:8]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[9:8]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[9:8]),
.localrefclk(tx_localrefclk[4]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[4]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[4]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs4_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[4]),
.phfiforesetout(wire_transmit_pcs4_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs4_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[14:12]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[14:12]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[14:12]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[14:12]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[14:12]),
.pipeenrevparallellpbkout(wire_transmit_pcs4_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs4_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs4_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[4]),
.pipetxswing(tx_pipeswing[4]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[99:80]),
.txdetectrx(wire_transmit_pcs4_txdetectrx),
.xgmctrl(cent_unit_txctrlout[4]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[39:32]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs4.allow_polarity_inversion = "false",
transmit_pcs4.auto_spd_self_switch_enable = "true",
transmit_pcs4.bitslip_enable = "false",
transmit_pcs4.channel_bonding = "x8",
transmit_pcs4.channel_number = ((starting_channel_number + 4) % 4),
transmit_pcs4.channel_width = 8,
transmit_pcs4.core_clock_0ppm = "false",
transmit_pcs4.datapath_low_latency_mode = "false",
transmit_pcs4.datapath_protocol = "pipe",
transmit_pcs4.disable_ph_low_latency_mode = "false",
transmit_pcs4.disparity_mode = "new",
transmit_pcs4.dprio_config_mode = 6'h01,
transmit_pcs4.elec_idle_delay = 6,
transmit_pcs4.enable_bit_reversal = "false",
transmit_pcs4.enable_idle_selection = "false",
transmit_pcs4.enable_reverse_parallel_loopback = "true",
transmit_pcs4.enable_self_test_mode = "false",
transmit_pcs4.enable_symbol_swap = "false",
transmit_pcs4.enc_8b_10b_compatibility_mode = "true",
transmit_pcs4.enc_8b_10b_mode = "normal",
transmit_pcs4.force_echar = "false",
transmit_pcs4.force_kchar = "false",
transmit_pcs4.hip_enable = "true",
transmit_pcs4.iqp_ph_fifo_xn_select = 1,
transmit_pcs4.logical_channel_address = (starting_channel_number + 4),
transmit_pcs4.ph_fifo_reg_mode = "true",
transmit_pcs4.ph_fifo_xn_mapping0 = "none",
transmit_pcs4.ph_fifo_xn_mapping1 = "up",
transmit_pcs4.ph_fifo_xn_mapping2 = "none",
transmit_pcs4.ph_fifo_xn_select = 1,
transmit_pcs4.pipe_auto_speed_nego_enable = "true",
transmit_pcs4.pipe_freq_scale_mode = "Frequency",
transmit_pcs4.pipe_voltage_swing_control = "false",
transmit_pcs4.prbs_cid_pattern = "false",
transmit_pcs4.protocol_hint = "pcie2",
transmit_pcs4.refclk_select = "cmu_clock_divider",
transmit_pcs4.self_test_mode = "incremental",
transmit_pcs4.use_double_data_mode = "false",
transmit_pcs4.use_serializer_double_data_mode = "false",
transmit_pcs4.wr_clk_mux_select = "int_clk",
transmit_pcs4.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs5
(
.clkout(),
.coreclkout(wire_transmit_pcs5_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs5_dataout),
.digitalreset(tx_digitalreset_out[5]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[899:750]),
.dprioout(wire_transmit_pcs5_dprioout),
.enrevparallellpbk(tx_revparallellpbken[5]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs5_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs5_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[5], tx_ctrlenable[5], tx_datain_wire[47:40]}),
.hipdetectrxloop(tx_detectrxloop[5]),
.hipelecidleinfersel(rx_elecidleinfersel[17:15]),
.hipforceelecidle(tx_forceelecidle[5]),
.hippowerdn(powerdn[11:10]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[5]),
.hiptxmargin(tx_pipemargin[17:15]),
.invpol(tx_invpolarity[5]),
.iqpphfifobyteselout(wire_transmit_pcs5_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs5_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs5_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs5_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[11:10]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[11:10]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[11:10]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[11:10]),
.localrefclk(tx_localrefclk[5]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[5]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[5]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs5_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[5]),
.phfiforesetout(wire_transmit_pcs5_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs5_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[17:15]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[17:15]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[17:15]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[17:15]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[17:15]),
.pipeenrevparallellpbkout(wire_transmit_pcs5_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs5_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs5_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[5]),
.pipetxswing(tx_pipeswing[5]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[119:100]),
.txdetectrx(wire_transmit_pcs5_txdetectrx),
.xgmctrl(cent_unit_txctrlout[5]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[47:40]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs5.allow_polarity_inversion = "false",
transmit_pcs5.auto_spd_self_switch_enable = "true",
transmit_pcs5.bitslip_enable = "false",
transmit_pcs5.channel_bonding = "x8",
transmit_pcs5.channel_number = ((starting_channel_number + 5) % 4),
transmit_pcs5.channel_width = 8,
transmit_pcs5.core_clock_0ppm = "false",
transmit_pcs5.datapath_low_latency_mode = "false",
transmit_pcs5.datapath_protocol = "pipe",
transmit_pcs5.disable_ph_low_latency_mode = "false",
transmit_pcs5.disparity_mode = "new",
transmit_pcs5.dprio_config_mode = 6'h01,
transmit_pcs5.elec_idle_delay = 6,
transmit_pcs5.enable_bit_reversal = "false",
transmit_pcs5.enable_idle_selection = "false",
transmit_pcs5.enable_reverse_parallel_loopback = "true",
transmit_pcs5.enable_self_test_mode = "false",
transmit_pcs5.enable_symbol_swap = "false",
transmit_pcs5.enc_8b_10b_compatibility_mode = "true",
transmit_pcs5.enc_8b_10b_mode = "normal",
transmit_pcs5.force_echar = "false",
transmit_pcs5.force_kchar = "false",
transmit_pcs5.hip_enable = "true",
transmit_pcs5.logical_channel_address = (starting_channel_number + 5),
transmit_pcs5.ph_fifo_reg_mode = "true",
transmit_pcs5.ph_fifo_xn_mapping0 = "none",
transmit_pcs5.ph_fifo_xn_mapping1 = "up",
transmit_pcs5.ph_fifo_xn_mapping2 = "none",
transmit_pcs5.ph_fifo_xn_select = 1,
transmit_pcs5.pipe_auto_speed_nego_enable = "true",
transmit_pcs5.pipe_freq_scale_mode = "Frequency",
transmit_pcs5.pipe_voltage_swing_control = "false",
transmit_pcs5.prbs_cid_pattern = "false",
transmit_pcs5.protocol_hint = "pcie2",
transmit_pcs5.refclk_select = "cmu_clock_divider",
transmit_pcs5.self_test_mode = "incremental",
transmit_pcs5.use_double_data_mode = "false",
transmit_pcs5.use_serializer_double_data_mode = "false",
transmit_pcs5.wr_clk_mux_select = "int_clk",
transmit_pcs5.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs6
(
.clkout(),
.coreclkout(wire_transmit_pcs6_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs6_dataout),
.digitalreset(tx_digitalreset_out[6]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[1049:900]),
.dprioout(wire_transmit_pcs6_dprioout),
.enrevparallellpbk(tx_revparallellpbken[6]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs6_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs6_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[6], tx_ctrlenable[6], tx_datain_wire[55:48]}),
.hipdetectrxloop(tx_detectrxloop[6]),
.hipelecidleinfersel(rx_elecidleinfersel[20:18]),
.hipforceelecidle(tx_forceelecidle[6]),
.hippowerdn(powerdn[13:12]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[6]),
.hiptxmargin(tx_pipemargin[20:18]),
.invpol(tx_invpolarity[6]),
.iqpphfifobyteselout(wire_transmit_pcs6_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs6_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs6_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs6_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[13:12]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[13:12]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[13:12]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[13:12]),
.localrefclk(tx_localrefclk[6]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[6]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[6]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs6_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[6]),
.phfiforesetout(wire_transmit_pcs6_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs6_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[20:18]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[20:18]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[20:18]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[20:18]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[20:18]),
.pipeenrevparallellpbkout(wire_transmit_pcs6_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs6_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs6_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[6]),
.pipetxswing(tx_pipeswing[6]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[139:120]),
.txdetectrx(wire_transmit_pcs6_txdetectrx),
.xgmctrl(cent_unit_txctrlout[6]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[55:48]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs6.allow_polarity_inversion = "false",
transmit_pcs6.auto_spd_self_switch_enable = "true",
transmit_pcs6.bitslip_enable = "false",
transmit_pcs6.channel_bonding = "x8",
transmit_pcs6.channel_number = ((starting_channel_number + 6) % 4),
transmit_pcs6.channel_width = 8,
transmit_pcs6.core_clock_0ppm = "false",
transmit_pcs6.datapath_low_latency_mode = "false",
transmit_pcs6.datapath_protocol = "pipe",
transmit_pcs6.disable_ph_low_latency_mode = "false",
transmit_pcs6.disparity_mode = "new",
transmit_pcs6.dprio_config_mode = 6'h01,
transmit_pcs6.elec_idle_delay = 6,
transmit_pcs6.enable_bit_reversal = "false",
transmit_pcs6.enable_idle_selection = "false",
transmit_pcs6.enable_reverse_parallel_loopback = "true",
transmit_pcs6.enable_self_test_mode = "false",
transmit_pcs6.enable_symbol_swap = "false",
transmit_pcs6.enc_8b_10b_compatibility_mode = "true",
transmit_pcs6.enc_8b_10b_mode = "normal",
transmit_pcs6.force_echar = "false",
transmit_pcs6.force_kchar = "false",
transmit_pcs6.hip_enable = "true",
transmit_pcs6.logical_channel_address = (starting_channel_number + 6),
transmit_pcs6.ph_fifo_reg_mode = "true",
transmit_pcs6.ph_fifo_xn_mapping0 = "none",
transmit_pcs6.ph_fifo_xn_mapping1 = "up",
transmit_pcs6.ph_fifo_xn_mapping2 = "none",
transmit_pcs6.ph_fifo_xn_select = 1,
transmit_pcs6.pipe_auto_speed_nego_enable = "true",
transmit_pcs6.pipe_freq_scale_mode = "Frequency",
transmit_pcs6.pipe_voltage_swing_control = "false",
transmit_pcs6.prbs_cid_pattern = "false",
transmit_pcs6.protocol_hint = "pcie2",
transmit_pcs6.refclk_select = "cmu_clock_divider",
transmit_pcs6.self_test_mode = "incremental",
transmit_pcs6.use_double_data_mode = "false",
transmit_pcs6.use_serializer_double_data_mode = "false",
transmit_pcs6.wr_clk_mux_select = "int_clk",
transmit_pcs6.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs7
(
.clkout(),
.coreclkout(wire_transmit_pcs7_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs7_dataout),
.digitalreset(tx_digitalreset_out[7]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[1199:1050]),
.dprioout(wire_transmit_pcs7_dprioout),
.enrevparallellpbk(tx_revparallellpbken[7]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs7_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs7_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[7], tx_ctrlenable[7], tx_datain_wire[63:56]}),
.hipdetectrxloop(tx_detectrxloop[7]),
.hipelecidleinfersel(rx_elecidleinfersel[23:21]),
.hipforceelecidle(tx_forceelecidle[7]),
.hippowerdn(powerdn[15:14]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[7]),
.hiptxmargin(tx_pipemargin[23:21]),
.invpol(tx_invpolarity[7]),
.iqpphfifobyteselout(wire_transmit_pcs7_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs7_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs7_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs7_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[15:14]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[15:14]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[15:14]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[15:14]),
.localrefclk(tx_localrefclk[7]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[7]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[7]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs7_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[7]),
.phfiforesetout(wire_transmit_pcs7_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs7_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[23:21]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[23:21]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[23:21]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[23:21]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[23:21]),
.pipeenrevparallellpbkout(wire_transmit_pcs7_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs7_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs7_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[7]),
.pipetxswing(tx_pipeswing[7]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[159:140]),
.txdetectrx(wire_transmit_pcs7_txdetectrx),
.xgmctrl(cent_unit_txctrlout[7]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[63:56]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs7.allow_polarity_inversion = "false",
transmit_pcs7.auto_spd_self_switch_enable = "true",
transmit_pcs7.bitslip_enable = "false",
transmit_pcs7.channel_bonding = "x8",
transmit_pcs7.channel_number = ((starting_channel_number + 7) % 4),
transmit_pcs7.channel_width = 8,
transmit_pcs7.core_clock_0ppm = "false",
transmit_pcs7.datapath_low_latency_mode = "false",
transmit_pcs7.datapath_protocol = "pipe",
transmit_pcs7.disable_ph_low_latency_mode = "false",
transmit_pcs7.disparity_mode = "new",
transmit_pcs7.dprio_config_mode = 6'h01,
transmit_pcs7.elec_idle_delay = 6,
transmit_pcs7.enable_bit_reversal = "false",
transmit_pcs7.enable_idle_selection = "false",
transmit_pcs7.enable_reverse_parallel_loopback = "true",
transmit_pcs7.enable_self_test_mode = "false",
transmit_pcs7.enable_symbol_swap = "false",
transmit_pcs7.enc_8b_10b_compatibility_mode = "true",
transmit_pcs7.enc_8b_10b_mode = "normal",
transmit_pcs7.force_echar = "false",
transmit_pcs7.force_kchar = "false",
transmit_pcs7.hip_enable = "true",
transmit_pcs7.logical_channel_address = (starting_channel_number + 7),
transmit_pcs7.ph_fifo_reg_mode = "true",
transmit_pcs7.ph_fifo_xn_mapping0 = "none",
transmit_pcs7.ph_fifo_xn_mapping1 = "up",
transmit_pcs7.ph_fifo_xn_mapping2 = "none",
transmit_pcs7.ph_fifo_xn_select = 1,
transmit_pcs7.pipe_auto_speed_nego_enable = "true",
transmit_pcs7.pipe_freq_scale_mode = "Frequency",
transmit_pcs7.pipe_voltage_swing_control = "false",
transmit_pcs7.prbs_cid_pattern = "false",
transmit_pcs7.protocol_hint = "pcie2",
transmit_pcs7.refclk_select = "cmu_clock_divider",
transmit_pcs7.self_test_mode = "incremental",
transmit_pcs7.use_double_data_mode = "false",
transmit_pcs7.use_serializer_double_data_mode = "false",
transmit_pcs7.wr_clk_mux_select = "int_clk",
transmit_pcs7.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "auto",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 1,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.logical_protocol_hint_0 = "pcie2",
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin1_mapping = "x4",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.preemp_tap_1_a = 28,
transmit_pma0.preemp_tap_1_b = 22,
transmit_pma0.preemp_tap_1_c = 7,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "pcie2",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "off",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 3,
transmit_pma0.vod_selection_a = 6,
transmit_pma0.vod_selection_c = 1,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma1
(
.clockout(wire_transmit_pma1_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
.dataout(wire_transmit_pma1_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[599:300]),
.dprioout(wire_transmit_pma1_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[1]),
.powerdn(cent_unit_txobpowerdn[1]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[1]),
.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
.rxfoundout(wire_transmit_pma1_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma1.analog_power = "auto",
transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pma1.channel_type = "auto",
transmit_pma1.clkin_select = 1,
transmit_pma1.clkmux_delay = "false",
transmit_pma1.common_mode = "0.65V",
transmit_pma1.dprio_config_mode = 6'h01,
transmit_pma1.enable_reverse_serial_loopback = "false",
transmit_pma1.logical_channel_address = (starting_channel_number + 1),
transmit_pma1.logical_protocol_hint_0 = "pcie2",
transmit_pma1.low_speed_test_select = 0,
transmit_pma1.physical_clkin1_mapping = "x4",
transmit_pma1.preemp_pretap = 0,
transmit_pma1.preemp_pretap_inv = "false",
transmit_pma1.preemp_tap_1 = 0,
transmit_pma1.preemp_tap_1_a = 28,
transmit_pma1.preemp_tap_1_b = 22,
transmit_pma1.preemp_tap_1_c = 7,
transmit_pma1.preemp_tap_2 = 0,
transmit_pma1.preemp_tap_2_inv = "false",
transmit_pma1.protocol_hint = "pcie2",
transmit_pma1.rx_detect = 0,
transmit_pma1.serialization_factor = 10,
transmit_pma1.slew_rate = "off",
transmit_pma1.termination = "OCT 100 Ohms",
transmit_pma1.use_external_termination = "false",
transmit_pma1.use_pma_direct = "false",
transmit_pma1.use_ser_double_data_mode = "false",
transmit_pma1.vod_selection = 3,
transmit_pma1.vod_selection_a = 6,
transmit_pma1.vod_selection_c = 1,
transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma2
(
.clockout(wire_transmit_pma2_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
.dataout(wire_transmit_pma2_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[899:600]),
.dprioout(wire_transmit_pma2_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[2]),
.powerdn(cent_unit_txobpowerdn[2]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[2]),
.rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
.rxfoundout(wire_transmit_pma2_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma2.analog_power = "auto",
transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pma2.channel_type = "auto",
transmit_pma2.clkin_select = 1,
transmit_pma2.clkmux_delay = "false",
transmit_pma2.common_mode = "0.65V",
transmit_pma2.dprio_config_mode = 6'h01,
transmit_pma2.enable_reverse_serial_loopback = "false",
transmit_pma2.logical_channel_address = (starting_channel_number + 2),
transmit_pma2.logical_protocol_hint_0 = "pcie2",
transmit_pma2.low_speed_test_select = 0,
transmit_pma2.physical_clkin1_mapping = "x4",
transmit_pma2.preemp_pretap = 0,
transmit_pma2.preemp_pretap_inv = "false",
transmit_pma2.preemp_tap_1 = 0,
transmit_pma2.preemp_tap_1_a = 28,
transmit_pma2.preemp_tap_1_b = 22,
transmit_pma2.preemp_tap_1_c = 7,
transmit_pma2.preemp_tap_2 = 0,
transmit_pma2.preemp_tap_2_inv = "false",
transmit_pma2.protocol_hint = "pcie2",
transmit_pma2.rx_detect = 0,
transmit_pma2.serialization_factor = 10,
transmit_pma2.slew_rate = "off",
transmit_pma2.termination = "OCT 100 Ohms",
transmit_pma2.use_external_termination = "false",
transmit_pma2.use_pma_direct = "false",
transmit_pma2.use_ser_double_data_mode = "false",
transmit_pma2.vod_selection = 3,
transmit_pma2.vod_selection_a = 6,
transmit_pma2.vod_selection_c = 1,
transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma3
(
.clockout(wire_transmit_pma3_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
.dataout(wire_transmit_pma3_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[1199:900]),
.dprioout(wire_transmit_pma3_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[3]),
.powerdn(cent_unit_txobpowerdn[3]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[3]),
.rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
.rxfoundout(wire_transmit_pma3_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma3.analog_power = "auto",
transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pma3.channel_type = "auto",
transmit_pma3.clkin_select = 1,
transmit_pma3.clkmux_delay = "false",
transmit_pma3.common_mode = "0.65V",
transmit_pma3.dprio_config_mode = 6'h01,
transmit_pma3.enable_reverse_serial_loopback = "false",
transmit_pma3.logical_channel_address = (starting_channel_number + 3),
transmit_pma3.logical_protocol_hint_0 = "pcie2",
transmit_pma3.low_speed_test_select = 0,
transmit_pma3.physical_clkin1_mapping = "x4",
transmit_pma3.preemp_pretap = 0,
transmit_pma3.preemp_pretap_inv = "false",
transmit_pma3.preemp_tap_1 = 0,
transmit_pma3.preemp_tap_1_a = 28,
transmit_pma3.preemp_tap_1_b = 22,
transmit_pma3.preemp_tap_1_c = 7,
transmit_pma3.preemp_tap_2 = 0,
transmit_pma3.preemp_tap_2_inv = "false",
transmit_pma3.protocol_hint = "pcie2",
transmit_pma3.rx_detect = 0,
transmit_pma3.serialization_factor = 10,
transmit_pma3.slew_rate = "off",
transmit_pma3.termination = "OCT 100 Ohms",
transmit_pma3.use_external_termination = "false",
transmit_pma3.use_pma_direct = "false",
transmit_pma3.use_ser_double_data_mode = "false",
transmit_pma3.vod_selection = 3,
transmit_pma3.vod_selection_a = 6,
transmit_pma3.vod_selection_c = 1,
transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma4
(
.clockout(wire_transmit_pma4_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[99:80]}),
.dataout(wire_transmit_pma4_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[6]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2099:1800]),
.dprioout(wire_transmit_pma4_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[4]),
.powerdn(cent_unit_txobpowerdn[6]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[4]),
.rxdetectvalidout(wire_transmit_pma4_rxdetectvalidout),
.rxfoundout(wire_transmit_pma4_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma4.analog_power = "auto",
transmit_pma4.channel_number = ((starting_channel_number + 4) % 4),
transmit_pma4.channel_type = "auto",
transmit_pma4.clkin_select = 2,
transmit_pma4.clkmux_delay = "false",
transmit_pma4.common_mode = "0.65V",
transmit_pma4.dprio_config_mode = 6'h01,
transmit_pma4.enable_reverse_serial_loopback = "false",
transmit_pma4.logical_channel_address = (starting_channel_number + 4),
transmit_pma4.logical_protocol_hint_0 = "pcie2",
transmit_pma4.low_speed_test_select = 0,
transmit_pma4.physical_clkin2_mapping = "xn_top",
transmit_pma4.preemp_pretap = 0,
transmit_pma4.preemp_pretap_inv = "false",
transmit_pma4.preemp_tap_1 = 0,
transmit_pma4.preemp_tap_1_a = 28,
transmit_pma4.preemp_tap_1_b = 22,
transmit_pma4.preemp_tap_1_c = 7,
transmit_pma4.preemp_tap_2 = 0,
transmit_pma4.preemp_tap_2_inv = "false",
transmit_pma4.protocol_hint = "pcie2",
transmit_pma4.rx_detect = 0,
transmit_pma4.serialization_factor = 10,
transmit_pma4.slew_rate = "off",
transmit_pma4.termination = "OCT 100 Ohms",
transmit_pma4.use_external_termination = "false",
transmit_pma4.use_pma_direct = "false",
transmit_pma4.use_ser_double_data_mode = "false",
transmit_pma4.vod_selection = 3,
transmit_pma4.vod_selection_a = 6,
transmit_pma4.vod_selection_c = 1,
transmit_pma4.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma5
(
.clockout(wire_transmit_pma5_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[119:100]}),
.dataout(wire_transmit_pma5_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[7]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2399:2100]),
.dprioout(wire_transmit_pma5_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[5]),
.powerdn(cent_unit_txobpowerdn[7]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[5]),
.rxdetectvalidout(wire_transmit_pma5_rxdetectvalidout),
.rxfoundout(wire_transmit_pma5_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma5.analog_power = "auto",
transmit_pma5.channel_number = ((starting_channel_number + 5) % 4),
transmit_pma5.channel_type = "auto",
transmit_pma5.clkin_select = 2,
transmit_pma5.clkmux_delay = "false",
transmit_pma5.common_mode = "0.65V",
transmit_pma5.dprio_config_mode = 6'h01,
transmit_pma5.enable_reverse_serial_loopback = "false",
transmit_pma5.logical_channel_address = (starting_channel_number + 5),
transmit_pma5.logical_protocol_hint_0 = "pcie2",
transmit_pma5.low_speed_test_select = 0,
transmit_pma5.physical_clkin2_mapping = "xn_top",
transmit_pma5.preemp_pretap = 0,
transmit_pma5.preemp_pretap_inv = "false",
transmit_pma5.preemp_tap_1 = 0,
transmit_pma5.preemp_tap_1_a = 28,
transmit_pma5.preemp_tap_1_b = 22,
transmit_pma5.preemp_tap_1_c = 7,
transmit_pma5.preemp_tap_2 = 0,
transmit_pma5.preemp_tap_2_inv = "false",
transmit_pma5.protocol_hint = "pcie2",
transmit_pma5.rx_detect = 0,
transmit_pma5.serialization_factor = 10,
transmit_pma5.slew_rate = "off",
transmit_pma5.termination = "OCT 100 Ohms",
transmit_pma5.use_external_termination = "false",
transmit_pma5.use_pma_direct = "false",
transmit_pma5.use_ser_double_data_mode = "false",
transmit_pma5.vod_selection = 3,
transmit_pma5.vod_selection_a = 6,
transmit_pma5.vod_selection_c = 1,
transmit_pma5.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma6
(
.clockout(wire_transmit_pma6_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[139:120]}),
.dataout(wire_transmit_pma6_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[8]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2699:2400]),
.dprioout(wire_transmit_pma6_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[6]),
.powerdn(cent_unit_txobpowerdn[8]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[6]),
.rxdetectvalidout(wire_transmit_pma6_rxdetectvalidout),
.rxfoundout(wire_transmit_pma6_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[8])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma6.analog_power = "auto",
transmit_pma6.channel_number = ((starting_channel_number + 6) % 4),
transmit_pma6.channel_type = "auto",
transmit_pma6.clkin_select = 2,
transmit_pma6.clkmux_delay = "false",
transmit_pma6.common_mode = "0.65V",
transmit_pma6.dprio_config_mode = 6'h01,
transmit_pma6.enable_reverse_serial_loopback = "false",
transmit_pma6.logical_channel_address = (starting_channel_number + 6),
transmit_pma6.logical_protocol_hint_0 = "pcie2",
transmit_pma6.low_speed_test_select = 0,
transmit_pma6.physical_clkin2_mapping = "xn_top",
transmit_pma6.preemp_pretap = 0,
transmit_pma6.preemp_pretap_inv = "false",
transmit_pma6.preemp_tap_1 = 0,
transmit_pma6.preemp_tap_1_a = 28,
transmit_pma6.preemp_tap_1_b = 22,
transmit_pma6.preemp_tap_1_c = 7,
transmit_pma6.preemp_tap_2 = 0,
transmit_pma6.preemp_tap_2_inv = "false",
transmit_pma6.protocol_hint = "pcie2",
transmit_pma6.rx_detect = 0,
transmit_pma6.serialization_factor = 10,
transmit_pma6.slew_rate = "off",
transmit_pma6.termination = "OCT 100 Ohms",
transmit_pma6.use_external_termination = "false",
transmit_pma6.use_pma_direct = "false",
transmit_pma6.use_ser_double_data_mode = "false",
transmit_pma6.vod_selection = 3,
transmit_pma6.vod_selection_a = 6,
transmit_pma6.vod_selection_c = 1,
transmit_pma6.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma7
(
.clockout(wire_transmit_pma7_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[159:140]}),
.dataout(wire_transmit_pma7_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[9]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2999:2700]),
.dprioout(wire_transmit_pma7_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[7]),
.powerdn(cent_unit_txobpowerdn[9]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[7]),
.rxdetectvalidout(wire_transmit_pma7_rxdetectvalidout),
.rxfoundout(wire_transmit_pma7_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[9])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma7.analog_power = "auto",
transmit_pma7.channel_number = ((starting_channel_number + 7) % 4),
transmit_pma7.channel_type = "auto",
transmit_pma7.clkin_select = 2,
transmit_pma7.clkmux_delay = "false",
transmit_pma7.common_mode = "0.65V",
transmit_pma7.dprio_config_mode = 6'h01,
transmit_pma7.enable_reverse_serial_loopback = "false",
transmit_pma7.logical_channel_address = (starting_channel_number + 7),
transmit_pma7.logical_protocol_hint_0 = "pcie2",
transmit_pma7.low_speed_test_select = 0,
transmit_pma7.physical_clkin2_mapping = "xn_top",
transmit_pma7.preemp_pretap = 0,
transmit_pma7.preemp_pretap_inv = "false",
transmit_pma7.preemp_tap_1 = 0,
transmit_pma7.preemp_tap_1_a = 28,
transmit_pma7.preemp_tap_1_b = 22,
transmit_pma7.preemp_tap_1_c = 7,
transmit_pma7.preemp_tap_2 = 0,
transmit_pma7.preemp_tap_2_inv = "false",
transmit_pma7.protocol_hint = "pcie2",
transmit_pma7.rx_detect = 0,
transmit_pma7.serialization_factor = 10,
transmit_pma7.slew_rate = "off",
transmit_pma7.termination = "OCT 100 Ohms",
transmit_pma7.use_external_termination = "false",
transmit_pma7.use_pma_direct = "false",
transmit_pma7.use_ser_double_data_mode = "false",
transmit_pma7.vod_selection = 3,
transmit_pma7.vod_selection_a = 6,
transmit_pma7.vod_selection_c = 1,
transmit_pma7.lpm_type = "stratixiv_hssi_tx_pma";
assign
cal_blk_powerdown = 1'b0,
cent_unit_clkdivpowerdn = {wire_cent_unit1_clkdivpowerdn[0], wire_cent_unit0_clkdivpowerdn[0]},
cent_unit_cmudividerdprioout = {wire_cent_unit1_cmudividerdprioout, wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit1_cmuplldprioout, wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit1_pllpowerdn[1:0], wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit1_pllresetout[1:0], wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit1_quadresetout, wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit1_rxcrupowerdown[5:0], wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit1_rxibpowerdown[5:0], wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {rx_pcsdprioout[3199:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit1_rxpcsdprioout[1599:0], wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
cent_unit_rxpmadprioout = {wire_cent_unit1_rxpmadprioout[1799:0], wire_cent_unit0_rxpmadprioout[1799:0]},
cent_unit_tx_dprioin = {{1200{1'b0}}, tx_txdprioout[1199:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit1_txdataout[31:0], wire_cent_unit0_txdataout[31:0]},
cent_unit_txctrlout = {wire_cent_unit1_txctrlout, wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit1_txdetectrxpowerdown[5:0], wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txdprioout = {wire_cent_unit1_txpcsdprioout[599:0], wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit1_txobpowerdown[5:0], wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
cent_unit_txpmadprioout = {wire_cent_unit1_txpmadprioout[1799:0], wire_cent_unit0_txpmadprioout[1799:0]},
clk_div_clk0in = {pll0_out[7:0]},
clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div1_dprioout, {400{1'b0}}, {100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
clk_div_pclkin = {refclk_pma[0], 1'b0},
cmu_analogfastrefclkout = {wire_central_clk_div1_analogfastrefclkout, wire_central_clk_div0_analogfastrefclkout},
cmu_analogrefclkout = {wire_central_clk_div1_analogrefclkout, wire_central_clk_div0_analogrefclkout},
cmu_analogrefclkpulse = {wire_central_clk_div1_analogrefclkpulse, wire_central_clk_div0_analogrefclkpulse},
coreclkout = {coreclkout_wire[0]},
coreclkout_wire = {wire_central_clk_div1_coreclkout, wire_central_clk_div0_coreclkout},
fixedclk_div_in = {fixedclk_div5quad1c, fixedclk_div4quad1c, fixedclk_div3quad1c, fixedclk_div2quad1c, fixedclk_div1quad1c, fixedclk_div0quad1c, fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_fast = {12{1'b1}},
fixedclk_in = {{2{1'b0}}, {4{fixedclk}}, {2{1'b0}}, {4{fixedclk}}},
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[11]) & fixedclk_div_in[11]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[11])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[10]) & fixedclk_div_in[10]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[10])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[9]) & fixedclk_div_in[9]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[9])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[8]) & fixedclk_div_in[8]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[8])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[7]) & fixedclk_div_in[7]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[7])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[6]) & fixedclk_div_in[6]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[6])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
hip_tx_clkout = {{3{1'b0}}, wire_central_clk_div1_refclkout, {3{1'b0}}, wire_central_clk_div0_refclkout},
int_autospdx4configsel = {wire_cent_unit1_autospdx4configsel, wire_cent_unit0_autospdx4configsel},
int_autospdx4rateswitchout = {wire_cent_unit1_autospdx4rateswitchout, wire_cent_unit0_autospdx4rateswitchout},
int_autospdx4spdchg = {wire_cent_unit1_autospdx4spdchg, wire_cent_unit0_autospdx4spdchg},
int_hipautospdrateswitchout = {wire_receive_pcs7_autospdrateswitchout, wire_receive_pcs6_autospdrateswitchout, wire_receive_pcs5_autospdrateswitchout, wire_receive_pcs4_autospdrateswitchout, wire_receive_pcs3_autospdrateswitchout, wire_receive_pcs2_autospdrateswitchout, wire_receive_pcs1_autospdrateswitchout, wire_receive_pcs0_autospdrateswitchout},
int_hiprateswtichdone = {wire_central_clk_div1_rateswitchdone, wire_central_clk_div0_rateswitchdone},
int_phfifiox4ptrsreset = {wire_cent_unit1_phfifiox4ptrsreset, wire_cent_unit0_phfifiox4ptrsreset},
int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs7_pipeenrevparallellpbkout, wire_transmit_pcs6_pipeenrevparallellpbkout, wire_transmit_pcs5_pipeenrevparallellpbkout, wire_transmit_pcs4_pipeenrevparallellpbkout, wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
int_rateswitch = {int_rx_rateswitchout[4], int_rx_rateswitchout[0]},
int_rx_autospdspdchgout = {wire_receive_pcs7_autospdspdchgout, wire_receive_pcs6_autospdspdchgout, wire_receive_pcs5_autospdspdchgout, wire_receive_pcs4_autospdspdchgout, wire_receive_pcs3_autospdspdchgout, wire_receive_pcs2_autospdspdchgout, wire_receive_pcs1_autospdspdchgout, wire_receive_pcs0_autospdspdchgout},
int_rx_autospdxnconfigsel = {1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], 1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
int_rx_autospdxnspdchg = {1'b0, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], 1'b0, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
int_rx_coreclkout = {wire_receive_pcs7_coreclkout, wire_receive_pcs6_coreclkout, wire_receive_pcs5_coreclkout, wire_receive_pcs4_coreclkout, wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
int_rx_iqpautospdxnspgchg = {{3{{2{1'b0}}}}, int_rx_autospdspdchgout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifobyteselout = {wire_receive_pcs7_iqpphfifobyteselout, wire_receive_pcs6_iqpphfifobyteselout, wire_receive_pcs5_iqpphfifobyteselout, wire_receive_pcs4_iqpphfifobyteselout, wire_receive_pcs3_iqpphfifobyteselout, wire_receive_pcs2_iqpphfifobyteselout, wire_receive_pcs1_iqpphfifobyteselout, wire_receive_pcs0_iqpphfifobyteselout},
int_rx_iqpphfifoptrsresetout = {wire_receive_pcs7_iqpphfifoptrsresetout, wire_receive_pcs6_iqpphfifoptrsresetout, wire_receive_pcs5_iqpphfifoptrsresetout, wire_receive_pcs4_iqpphfifoptrsresetout, wire_receive_pcs3_iqpphfifoptrsresetout, wire_receive_pcs2_iqpphfifoptrsresetout, wire_receive_pcs1_iqpphfifoptrsresetout, wire_receive_pcs0_iqpphfifoptrsresetout},
int_rx_iqpphfifordenableout = {wire_receive_pcs7_iqpphfifordenableout, wire_receive_pcs6_iqpphfifordenableout, wire_receive_pcs5_iqpphfifordenableout, wire_receive_pcs4_iqpphfifordenableout, wire_receive_pcs3_iqpphfifordenableout, wire_receive_pcs2_iqpphfifordenableout, wire_receive_pcs1_iqpphfifordenableout, wire_receive_pcs0_iqpphfifordenableout},
int_rx_iqpphfifowrclkout = {wire_receive_pcs7_iqpphfifowrclkout, wire_receive_pcs6_iqpphfifowrclkout, wire_receive_pcs5_iqpphfifowrclkout, wire_receive_pcs4_iqpphfifowrclkout, wire_receive_pcs3_iqpphfifowrclkout, wire_receive_pcs2_iqpphfifowrclkout, wire_receive_pcs1_iqpphfifowrclkout, wire_receive_pcs0_iqpphfifowrclkout},
int_rx_iqpphfifowrenableout = {wire_receive_pcs7_iqpphfifowrenableout, wire_receive_pcs6_iqpphfifowrenableout, wire_receive_pcs5_iqpphfifowrenableout, wire_receive_pcs4_iqpphfifowrenableout, wire_receive_pcs3_iqpphfifowrenableout, wire_receive_pcs2_iqpphfifowrenableout, wire_receive_pcs1_iqpphfifowrenableout, wire_receive_pcs0_iqpphfifowrenableout},
int_rx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_rx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnptrsreset = {{3{{2{1'b0}}}}, int_rx_iqpphfifoptrsresetout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnwrclk = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrclkout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_rx_phfifobyteserdisable = {wire_receive_pcs7_phfifobyteserdisableout, wire_receive_pcs6_phfifobyteserdisableout, wire_receive_pcs5_phfifobyteserdisableout, wire_receive_pcs4_phfifobyteserdisableout, wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
int_rx_phfifoptrsresetout = {wire_receive_pcs7_phfifoptrsresetout, wire_receive_pcs6_phfifoptrsresetout, wire_receive_pcs5_phfifoptrsresetout, wire_receive_pcs4_phfifoptrsresetout, wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
int_rx_phfifordenableout = {wire_receive_pcs7_phfifordenableout, wire_receive_pcs6_phfifordenableout, wire_receive_pcs5_phfifordenableout, wire_receive_pcs4_phfifordenableout, wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
int_rx_phfiforesetout = {wire_receive_pcs7_phfiforesetout, wire_receive_pcs6_phfiforesetout, wire_receive_pcs5_phfiforesetout, wire_receive_pcs4_phfiforesetout, wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
int_rx_phfifowrdisableout = {wire_receive_pcs7_phfifowrdisableout, wire_receive_pcs6_phfifowrdisableout, wire_receive_pcs5_phfifowrdisableout, wire_receive_pcs4_phfifowrdisableout, wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
int_rx_phfifoxnbytesel = {1'b0, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], 1'b0, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
int_rx_phfifoxnrdenable = {1'b0, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], 1'b0, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
int_rx_phfifoxnwrclk = {1'b0, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], 1'b0, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
int_rx_phfifoxnwrenable = {1'b0, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], 1'b0, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
int_rx_rateswitchout = {wire_receive_pcs7_rateswitchout, wire_receive_pcs6_rateswitchout, wire_receive_pcs5_rateswitchout, wire_receive_pcs4_rateswitchout, wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
int_rxcoreclk = {1'b0, int_rx_coreclkout[0]},
int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs7_cdrctrlearlyeios, wire_receive_pcs6_cdrctrlearlyeios, wire_receive_pcs5_cdrctrlearlyeios, wire_receive_pcs4_cdrctrlearlyeios, wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
int_rxphfifordenable = {1'b0, int_rx_phfifordenableout[0]},
int_rxphfiforeset = {1'b0, int_rx_phfiforesetout[0]},
int_rxphfifox4byteselout = {wire_cent_unit1_rxphfifox4byteselout, wire_cent_unit0_rxphfifox4byteselout},
int_rxphfifox4rdenableout = {wire_cent_unit1_rxphfifox4rdenableout, wire_cent_unit0_rxphfifox4rdenableout},
int_rxphfifox4wrclkout = {wire_cent_unit1_rxphfifox4wrclkout, wire_cent_unit0_rxphfifox4wrclkout},
int_rxphfifox4wrenableout = {wire_cent_unit1_rxphfifox4wrenableout, wire_cent_unit0_rxphfifox4wrenableout},
int_tx_coreclkout = {wire_transmit_pcs7_coreclkout, wire_transmit_pcs6_coreclkout, wire_transmit_pcs5_coreclkout, wire_transmit_pcs4_coreclkout, wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
int_tx_iqpphfifobyteselout = {wire_transmit_pcs7_iqpphfifobyteselout, wire_transmit_pcs6_iqpphfifobyteselout, wire_transmit_pcs5_iqpphfifobyteselout, wire_transmit_pcs4_iqpphfifobyteselout, wire_transmit_pcs3_iqpphfifobyteselout, wire_transmit_pcs2_iqpphfifobyteselout, wire_transmit_pcs1_iqpphfifobyteselout, wire_transmit_pcs0_iqpphfifobyteselout},
int_tx_iqpphfifordclkout = {wire_transmit_pcs7_iqpphfifordclkout, wire_transmit_pcs6_iqpphfifordclkout, wire_transmit_pcs5_iqpphfifordclkout, wire_transmit_pcs4_iqpphfifordclkout, wire_transmit_pcs3_iqpphfifordclkout, wire_transmit_pcs2_iqpphfifordclkout, wire_transmit_pcs1_iqpphfifordclkout, wire_transmit_pcs0_iqpphfifordclkout},
int_tx_iqpphfifordenableout = {wire_transmit_pcs7_iqpphfifordenableout, wire_transmit_pcs6_iqpphfifordenableout, wire_transmit_pcs5_iqpphfifordenableout, wire_transmit_pcs4_iqpphfifordenableout, wire_transmit_pcs3_iqpphfifordenableout, wire_transmit_pcs2_iqpphfifordenableout, wire_transmit_pcs1_iqpphfifordenableout, wire_transmit_pcs0_iqpphfifordenableout},
int_tx_iqpphfifowrenableout = {wire_transmit_pcs7_iqpphfifowrenableout, wire_transmit_pcs6_iqpphfifowrenableout, wire_transmit_pcs5_iqpphfifowrenableout, wire_transmit_pcs4_iqpphfifowrenableout, wire_transmit_pcs3_iqpphfifowrenableout, wire_transmit_pcs2_iqpphfifowrenableout, wire_transmit_pcs1_iqpphfifowrenableout, wire_transmit_pcs0_iqpphfifowrenableout},
int_tx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_tx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_iqpphfifoxnrdclk = {{3{{2{1'b0}}}}, int_tx_iqpphfifordclkout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_tx_phfiforddisableout = {wire_transmit_pcs7_phfiforddisableout, wire_transmit_pcs6_phfiforddisableout, wire_transmit_pcs5_phfiforddisableout, wire_transmit_pcs4_phfiforddisableout, wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
int_tx_phfiforesetout = {wire_transmit_pcs7_phfiforesetout, wire_transmit_pcs6_phfiforesetout, wire_transmit_pcs5_phfiforesetout, wire_transmit_pcs4_phfiforesetout, wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
int_tx_phfifowrenableout = {wire_transmit_pcs7_phfifowrenableout, wire_transmit_pcs6_phfifowrenableout, wire_transmit_pcs5_phfifowrenableout, wire_transmit_pcs4_phfifowrenableout, wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
int_tx_phfifoxnbytesel = {1'b0, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], 1'b0, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
int_tx_phfifoxnrdclk = {1'b0, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], 1'b0, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
int_tx_phfifoxnrdenable = {1'b0, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], 1'b0, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
int_tx_phfifoxnwrenable = {1'b0, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], 1'b0, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
int_txcoreclk = {1'b0, int_tx_coreclkout[0]},
int_txphfiforddisable = {1'b0, int_tx_phfiforddisableout[0]},
int_txphfiforeset = {1'b0, int_tx_phfiforesetout[0]},
int_txphfifowrenable = {1'b0, int_tx_phfifowrenableout[0]},
int_txphfifox4byteselout = {wire_cent_unit1_txphfifox4byteselout, wire_cent_unit0_txphfifox4byteselout},
int_txphfifox4rdclkout = {wire_cent_unit1_txphfifox4rdclkout, wire_cent_unit0_txphfifox4rdclkout},
int_txphfifox4rdenableout = {wire_cent_unit1_txphfifox4rdenableout, wire_cent_unit0_txphfifox4rdenableout},
int_txphfifox4wrenableout = {wire_cent_unit1_txphfifox4wrenableout, wire_cent_unit0_txphfifox4wrenableout},
nonusertocmu_out = {wire_cal_blk1_nonusertocmu, wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[7:0]},
pipedatavalid_out = {wire_receive_pcs7_hipdatavalid, wire_receive_pcs6_hipdatavalid, wire_receive_pcs5_hipdatavalid, wire_receive_pcs4_hipdatavalid, wire_receive_pcs3_hipdatavalid, wire_receive_pcs2_hipdatavalid, wire_receive_pcs1_hipdatavalid, wire_receive_pcs0_hipdatavalid},
pipeelecidle = {pipeelecidle_out[7:0]},
pipeelecidle_out = {wire_receive_pcs7_hipelecidle, wire_receive_pcs6_hipelecidle, wire_receive_pcs5_hipelecidle, wire_receive_pcs4_hipelecidle, wire_receive_pcs3_hipelecidle, wire_receive_pcs2_hipelecidle, wire_receive_pcs1_hipelecidle, wire_receive_pcs0_hipelecidle},
pipephydonestatus = {wire_receive_pcs7_hipphydonestatus, wire_receive_pcs6_hipphydonestatus, wire_receive_pcs5_hipphydonestatus, wire_receive_pcs4_hipphydonestatus, wire_receive_pcs3_hipphydonestatus, wire_receive_pcs2_hipphydonestatus, wire_receive_pcs1_hipphydonestatus, wire_receive_pcs0_hipphydonestatus},
pipestatus = {wire_receive_pcs7_hipstatus, wire_receive_pcs6_hipstatus, wire_receive_pcs5_hipstatus, wire_receive_pcs4_hipstatus, wire_receive_pcs3_hipstatus, wire_receive_pcs2_hipstatus, wire_receive_pcs1_hipstatus, wire_receive_pcs0_hipstatus},
pll0_clkin = {{10{1'b0}}, {9{1'b0}}, pll_inclk_wire[0]},
pll0_dprioin = {{300{1'b0}}, cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {{300{1'b0}}, wire_tx_pll0_dprioout},
pll0_out = {{4{1'b0}}, wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll7_dataout, wire_rx_cdr_pll6_dataout, wire_rx_cdr_pll5_dataout, wire_rx_cdr_pll4_dataout, wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll7_dprioout, wire_rx_cdr_pll6_dprioout, wire_rx_cdr_pll5_dprioout, wire_rx_cdr_pll4_dprioout, wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {{600{1'b0}}, pll_ch_dprioout[2399:1200], {300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {1'b0, wire_tx_pll0_locked},
pllpowerdn_in = {{2{1'b0}}, 1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {{2{1'b0}}, 1'b0, cent_unit_pllresetout[0]},
rateswitchbaseclock = {wire_central_clk_div1_rateswitchbaseclock, wire_central_clk_div0_rateswitchbaseclock},
reconfig_fromgxb = {rx_pma_analogtestbus[33:18], wire_cent_unit1_dprioout, rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
refclk_pma = {wire_central_clk_div1_refclkout, wire_central_clk_div0_refclkout},
rx_analogreset_in = {{4{1'b0}}, {8{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
rx_analogreset_out = {wire_cent_unit1_rxanalogresetout[5:0], wire_cent_unit0_rxanalogresetout[5:0]},
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[7], {9{1'b0}}, rx_pldcruclk_in[6], {9{1'b0}}, rx_pldcruclk_in[5], {9{1'b0}}, rx_pldcruclk_in[4], {9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs7_hipdataout[8], wire_receive_pcs6_hipdataout[8], wire_receive_pcs5_hipdataout[8], wire_receive_pcs4_hipdataout[8], wire_receive_pcs3_hipdataout[8], wire_receive_pcs2_hipdataout[8], wire_receive_pcs1_hipdataout[8], wire_receive_pcs0_hipdataout[8]},
rx_dataout = {rx_out_wire[63:0]},
rx_deserclock_in = {rx_pll_clkout[31:0]},
rx_digitalreset_in = {8{int_rx_digitalreset_reg[0]}},
rx_digitalreset_out = {wire_cent_unit1_rxdigitalresetout[3:0], wire_cent_unit0_rxdigitalresetout[3:0]},
rx_enapatternalign = {8{1'b0}},
rx_freqlocked = {(rx_freqlocked_wire[7] & (~ rx_analogreset[0])), (rx_freqlocked_wire[6] & (~ rx_analogreset[0])), (rx_freqlocked_wire[5] & (~ rx_analogreset[0])), (rx_freqlocked_wire[4] & (~ rx_analogreset[0])), (rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
rx_freqlocked_wire = {wire_rx_cdr_pll7_freqlocked, wire_rx_cdr_pll6_freqlocked, wire_rx_cdr_pll5_freqlocked, wire_rx_cdr_pll4_freqlocked, wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
rx_locktodata = {8{1'b0}},
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[7]), ((~ reconfig_togxb_busy) & rx_locktodata[6]), ((~ reconfig_togxb_busy) & rx_locktodata[5]), ((~ reconfig_togxb_busy) & rx_locktodata[4]), ((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk_wire = {wire_receive_pcs7_cdrctrllocktorefclkout, wire_receive_pcs6_cdrctrllocktorefclkout, wire_receive_pcs5_cdrctrllocktorefclkout, wire_receive_pcs4_cdrctrllocktorefclkout, wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs7_hipdataout[7:0], wire_receive_pcs6_hipdataout[7:0], wire_receive_pcs5_hipdataout[7:0], wire_receive_pcs4_hipdataout[7:0], wire_receive_pcs3_hipdataout[7:0], wire_receive_pcs2_hipdataout[7:0], wire_receive_pcs1_hipdataout[7:0], wire_receive_pcs0_hipdataout[7:0]},
rx_pcs_rxfound_wire = {txdetectrxout[7], tx_rxfoundout[7], txdetectrxout[6], tx_rxfoundout[6], txdetectrxout[5], tx_rxfoundout[5], txdetectrxout[4], tx_rxfoundout[4], txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[3199:0]},
rx_pcsdprioout = {wire_receive_pcs7_dprioout, wire_receive_pcs6_dprioout, wire_receive_pcs5_dprioout, wire_receive_pcs4_dprioout, wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
rx_phfifordenable = {8{1'b1}},
rx_phfiforeset = {8{1'b0}},
rx_phfifowrdisable = {8{1'b0}},
rx_pipestatetransdoneout = {wire_receive_pcs7_pipestatetransdoneout, wire_receive_pcs6_pipestatetransdoneout, wire_receive_pcs5_pipestatetransdoneout, wire_receive_pcs4_pipestatetransdoneout, wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
rx_pldcruclk_in = {rx_cruclk[7:0]},
rx_pll_clkout = {wire_rx_cdr_pll7_clk, wire_rx_cdr_pll6_clk, wire_rx_cdr_pll5_clk, wire_rx_cdr_pll4_clk, wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
rx_pll_locked = {(rx_plllocked_wire[7] & (~ rx_analogreset[0])), (rx_plllocked_wire[6] & (~ rx_analogreset[0])), (rx_plllocked_wire[5] & (~ rx_analogreset[0])), (rx_plllocked_wire[4] & (~ rx_analogreset[0])), (rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll7_pfdrefclkout, wire_rx_cdr_pll6_pfdrefclkout, wire_rx_cdr_pll5_pfdrefclkout, wire_rx_cdr_pll4_pfdrefclkout, wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll7_locked, wire_rx_cdr_pll6_locked, wire_rx_cdr_pll5_locked, wire_rx_cdr_pll4_locked, wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {{102{1'b0}}, wire_receive_pma7_analogtestbus[5:2], wire_receive_pma6_analogtestbus[5:2], wire_receive_pma5_analogtestbus[5:2], wire_receive_pma4_analogtestbus[5:2], 1'b0, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma7_clockout, wire_receive_pma6_clockout, wire_receive_pma5_clockout, wire_receive_pma4_clockout, wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma7_dataout, wire_receive_pma6_dataout, wire_receive_pma5_dataout, wire_receive_pma4_dataout, wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma7_locktorefout, wire_receive_pma6_locktorefout, wire_receive_pma5_locktorefout, wire_receive_pma4_locktorefout, wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma7_recoverdataout[19:0], wire_receive_pma6_recoverdataout[19:0], wire_receive_pma5_recoverdataout[19:0], wire_receive_pma4_recoverdataout[19:0], wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma7_dprioout, wire_receive_pma6_dprioout, wire_receive_pma5_dprioout, wire_receive_pma4_dprioout, {2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
rx_powerdown = {8{1'b0}},
rx_powerdown_in = {{4{1'b0}}, rx_powerdown[7:0]},
rx_prbscidenable = {8{1'b0}},
rx_revparallelfdbkdata = {wire_receive_pcs7_revparallelfdbkdata, wire_receive_pcs6_revparallelfdbkdata, wire_receive_pcs5_revparallelfdbkdata, wire_receive_pcs4_revparallelfdbkdata, wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = {8{1'b0}},
rx_rxcruresetout = {wire_cent_unit1_rxcruresetout[5:0], wire_cent_unit0_rxcruresetout[5:0]},
rx_signaldetect = {rx_signaldetectout_wire[7:0]},
rx_signaldetect_wire = {wire_receive_pma7_signaldetect, wire_receive_pma6_signaldetect, wire_receive_pma5_signaldetect, wire_receive_pma4_signaldetect, wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
rx_signaldetectout_wire = {wire_receive_pcs7_signaldetect, wire_receive_pcs6_signaldetect, wire_receive_pcs5_signaldetect, wire_receive_pcs4_signaldetect, wire_receive_pcs3_signaldetect, wire_receive_pcs2_signaldetect, wire_receive_pcs1_signaldetect, wire_receive_pcs0_signaldetect},
rxphfifowrdisable = {1'b0, int_rx_phfifowrdisableout[0]},
rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
tx_analogreset_out = {wire_cent_unit1_txanalogresetout[5:0], wire_cent_unit0_txanalogresetout[5:0]},
tx_datain_wire = {tx_datain[63:0]},
tx_dataout = {wire_transmit_pma7_dataout, wire_transmit_pma6_dataout, wire_transmit_pma5_dataout, wire_transmit_pma4_dataout, wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs7_dataout, wire_transmit_pcs6_dataout, wire_transmit_pcs5_dataout, wire_transmit_pcs4_dataout, wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
tx_digitalreset_in = {8{int_tx_digitalreset_reg[0]}},
tx_digitalreset_out = {wire_cent_unit1_txdigitalresetout[3:0], wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{1200{1'b0}}, cent_unit_txdprioout[1199:0]},
tx_invpolarity = {8{1'b0}},
tx_localrefclk = {wire_transmit_pma7_clockout, wire_transmit_pma6_clockout, wire_transmit_pma5_clockout, wire_transmit_pma4_clockout, wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs7_forceelecidleout, wire_transmit_pcs6_forceelecidleout, wire_transmit_pcs5_forceelecidleout, wire_transmit_pcs4_forceelecidleout, wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = {8{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs7_pipepowerdownout, wire_transmit_pcs6_pipepowerdownout, wire_transmit_pcs5_pipepowerdownout, wire_transmit_pcs4_pipepowerdownout, wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs7_pipepowerstateout, wire_transmit_pcs6_pipepowerstateout, wire_transmit_pcs5_pipepowerstateout, wire_transmit_pcs4_pipepowerstateout, wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
tx_pipeswing = {8{1'b0}},
tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma7_dprioout, wire_transmit_pma6_dprioout, wire_transmit_pma5_dprioout, wire_transmit_pma4_dprioout, {2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
tx_revparallellpbken = {8{1'b0}},
tx_rxdetectvalidout = {wire_transmit_pma7_rxdetectvalidout, wire_transmit_pma6_rxdetectvalidout, wire_transmit_pma5_rxdetectvalidout, wire_transmit_pma4_rxdetectvalidout, wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma7_rxfoundout, wire_transmit_pma6_rxfoundout, wire_transmit_pma5_rxfoundout, wire_transmit_pma4_rxfoundout, wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
tx_txdprioout = {wire_transmit_pcs7_dprioout, wire_transmit_pcs6_dprioout, wire_transmit_pcs5_dprioout, wire_transmit_pcs4_dprioout, wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs7_txdetectrx, wire_transmit_pcs6_txdetectrx, wire_transmit_pcs5_txdetectrx, wire_transmit_pcs4_txdetectrx, wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit1_dpriodisableout, wire_cent_unit0_dpriodisableout};
endmodule //pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pcie_4243_hip_s4gx_gen2_x8_128_serdes (
cal_blk_clk,
fixedclk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_inclk,
pll_powerdown,
powerdn,
rateswitch,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_elecidleinfersel,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin,
coreclkout,
hip_tx_clkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
rateswitchbaseclock,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_signaldetect,
rx_syncstatus,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [0:0] gxb_powerdown;
input [7:0] pipe8b10binvpolarity;
input pll_inclk;
input [0:0] pll_powerdown;
input [15:0] powerdn;
input [0:0] rateswitch;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [7:0] rx_cruclk;
input [7:0] rx_datain;
input [0:0] rx_digitalreset;
input [23:0] rx_elecidleinfersel;
input [7:0] tx_ctrlenable;
input [63:0] tx_datain;
input [7:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [7:0] tx_forcedispcompliance;
input [7:0] tx_forceelecidle;
input [7:0] tx_pipedeemph;
input [23:0] tx_pipemargin;
output [0:0] coreclkout;
output [7:0] hip_tx_clkout;
output [7:0] pipedatavalid;
output [7:0] pipeelecidle;
output [7:0] pipephydonestatus;
output [23:0] pipestatus;
output [0:0] pll_locked;
output [1:0] rateswitchbaseclock;
output [33:0] reconfig_fromgxb;
output [7:0] rx_ctrldetect;
output [63:0] rx_dataout;
output [7:0] rx_freqlocked;
output [7:0] rx_patterndetect;
output [7:0] rx_pll_locked;
output [7:0] rx_signaldetect;
output [7:0] rx_syncstatus;
output [7:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [33:0] sub_wire2;
wire [23:0] sub_wire3;
wire [7:0] sub_wire4;
wire [7:0] sub_wire5;
wire [0:0] sub_wire6;
wire [63:0] sub_wire7;
wire [7:0] sub_wire8;
wire [7:0] sub_wire9;
wire [1:0] sub_wire10;
wire [7:0] sub_wire11;
wire [7:0] sub_wire12;
wire [7:0] sub_wire13;
wire [7:0] sub_wire14;
wire [0:0] sub_wire15;
wire [7:0] sub_wire16;
wire [7:0] rx_patterndetect = sub_wire0[7:0];
wire [7:0] rx_signaldetect = sub_wire1[7:0];
wire [33:0] reconfig_fromgxb = sub_wire2[33:0];
wire [23:0] pipestatus = sub_wire3[23:0];
wire [7:0] rx_pll_locked = sub_wire4[7:0];
wire [7:0] rx_syncstatus = sub_wire5[7:0];
wire [0:0] coreclkout = sub_wire6[0:0];
wire [63:0] rx_dataout = sub_wire7[63:0];
wire [7:0] hip_tx_clkout = sub_wire8[7:0];
wire [7:0] pipeelecidle = sub_wire9[7:0];
wire [1:0] rateswitchbaseclock = sub_wire10[1:0];
wire [7:0] tx_dataout = sub_wire11[7:0];
wire [7:0] rx_ctrldetect = sub_wire12[7:0];
wire [7:0] pipedatavalid = sub_wire13[7:0];
wire [7:0] pipephydonestatus = sub_wire14[7:0];
wire [0:0] pll_locked = sub_wire15[0:0];
wire [7:0] rx_freqlocked = sub_wire16[7:0];
pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.tx_forceelecidle (tx_forceelecidle),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.pll_powerdown (pll_powerdown),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.tx_pipedeemph (tx_pipedeemph),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.tx_forcedispcompliance (tx_forcedispcompliance),
.rateswitch (rateswitch),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.powerdn (powerdn),
.tx_ctrlenable (tx_ctrlenable),
.tx_pipemargin (tx_pipemargin),
.pll_inclk (pll_inclk),
.rx_elecidleinfersel (rx_elecidleinfersel),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.rx_signaldetect (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.pipestatus (sub_wire3),
.rx_pll_locked (sub_wire4),
.rx_syncstatus (sub_wire5),
.coreclkout (sub_wire6),
.rx_dataout (sub_wire7),
.hip_tx_clkout (sub_wire8),
.pipeelecidle (sub_wire9),
.rateswitchbaseclock (sub_wire10),
.tx_dataout (sub_wire11),
.rx_ctrldetect (sub_wire12),
.pipedatavalid (sub_wire13),
.pipephydonestatus (sub_wire14),
.pll_locked (sub_wire15),
.rx_freqlocked (sub_wire16))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt4gxb
clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=8;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x8;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_bonding=x8;tx_channel_width=8;tx_clkout_width=8;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;hip_enable=true;number_of_quads=2;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=34;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=0;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=0;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
defparam
pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: IP_MODE STRING "PCIE_HIP_8"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x8"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: hip_enable STRING "true"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "2"
// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "34"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "0"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "0"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: hip_tx_clkout 0 0 8 0 OUTPUT NODEFVAL "hip_tx_clkout[7..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
// Retrieval info: USED_PORT: rateswitchbaseclock 0 0 2 0 OUTPUT NODEFVAL "rateswitchbaseclock[1..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 OUTPUT NODEFVAL "reconfig_fromgxb[33..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_elecidleinfersel 0 0 24 0 INPUT NODEFVAL "rx_elecidleinfersel[23..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
// Retrieval info: USED_PORT: rx_signaldetect 0 0 8 0 OUTPUT NODEFVAL "rx_signaldetect[7..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
// Retrieval info: USED_PORT: tx_pipedeemph 0 0 8 0 INPUT NODEFVAL "tx_pipedeemph[7..0]"
// Retrieval info: USED_PORT: tx_pipemargin 0 0 24 0 INPUT NODEFVAL "tx_pipemargin[23..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_elecidleinfersel 0 0 24 0 rx_elecidleinfersel 0 0 24 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
// Retrieval info: CONNECT: @tx_pipedeemph 0 0 8 0 tx_pipedeemph 0 0 8 0
// Retrieval info: CONNECT: @tx_pipemargin 0 0 24 0 tx_pipemargin 0 0 24 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: hip_tx_clkout 0 0 8 0 @hip_tx_clkout 0 0 8 0
// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: rateswitchbaseclock 0 0 2 0 @rateswitchbaseclock 0 0 2 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 34 0 @reconfig_fromgxb 0 0 34 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
// Retrieval info: CONNECT: rx_signaldetect 0 0 8 0 @rx_signaldetect 0 0 8 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes_bb.v FALSE
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datrom.v when simulating
// the core, upd77c25_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1536),
.C_READ_DEPTH_B(1536),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1536),
.C_WRITE_DEPTH_B(1536),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module acl_fp_custom_mul_op (
clock, resetn,
mantissa_left, exponent_left, sign_left,
mantissa_right, exponent_right, sign_right,
result_mantissa,
result_exponent,
result_sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
parameter HIGH_LATENCY = 1;
input clock, resetn;
input [26:0] mantissa_left;
input [8:0] exponent_left;
input sign_left;
input [26:0] mantissa_right;
input [8:0] exponent_right;
input sign_right;
input enable;
input stall_in, valid_in;
output stall_out, valid_out;
output [27:0] result_mantissa;
output [8:0] result_exponent;
output result_sign;
wire [53:0] sub_wire0;
wire enable_mult_stage;
// The multiplier.
lpm_mult lpm_mult_component (
.clock (clock),
.datab (mantissa_right),
.clken (enable_mult_stage),
.dataa (mantissa_left),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = (HIGH_LATENCY == 1) ? 3 : 2,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 27,
lpm_mult_component.lpm_widthb = 27,
lpm_mult_component.lpm_widthp = 54;
reg [9:0] exponent_1;
reg [8:0] exponent_2;
reg [8:0] exponent_3;
reg [5:0] man_a_clear;
reg [5:0] man_b_clear;
reg exp_zeroed;
reg sign_1, sign_2, sign_3, exp_out_of_range, generate_inf, exp_left, exp_right;
reg valid_1, valid_2, valid_3, flush_mantissa, make_nan, make_nan_r;
wire stall_mult;
assign enable_mult_stage = (HIGH_CAPACITY == 1) ? (~valid_2 | ~stall_mult) : enable;
assign stall_out = valid_2 & stall_mult;
generate
if (HIGH_LATENCY == 1)
begin
reg flush_mantissa_r;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exponent_1 <= 10'dx;
exponent_2 <= 9'dx;
exponent_3 <= 9'dx;
exp_out_of_range <= 1'bx;
sign_1 <= 1'bx;
sign_2 <= 1'bx;
sign_3 <= 1'bx;
flush_mantissa_r <= 1'bx;
flush_mantissa <= 1'bx;
man_a_clear <= 6'dx;
man_b_clear <= 6'dx;
make_nan_r <= 1'bx;
make_nan <= 1'bx;
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
exp_left <= 1'bx;
exp_right <= 1'bx;
exp_zeroed <= 1'bx;
end
else if (enable_mult_stage)
begin
valid_1 <= valid_in;
valid_2 <= valid_1;
sign_1 <= sign_left ^ sign_right;
sign_2 <= sign_1;
exp_left <= exponent_left[8];
exp_right <= exponent_right[8];
exp_out_of_range <= (exponent_left[8] | exponent_right[8]);
if ((exponent_left[8] || exponent_right[8]) && (FINITE_MATH_ONLY == 0))
exponent_1 <= 10'h1ff;
else
exponent_1 <= exponent_left + exponent_right - 10'd127;
man_a_clear <= {mantissa_left[26], |mantissa_left[25:21], |mantissa_left[20:15], |mantissa_left[14:10], |mantissa_left[9:5], |mantissa_left[4:0]};
man_b_clear <= {mantissa_right[26], |mantissa_right[25:21], |mantissa_right[20:15], |mantissa_right[14:10], |mantissa_right[9:5], |mantissa_right[4:0]};
// Second cycle.
flush_mantissa_r <= 1'b0;
make_nan_r <= 1'b0;
if (exp_out_of_range && (FINITE_MATH_ONLY == 0))
begin
exponent_2 <= 9'h1ff;
if (((exp_left & (~|man_a_clear[4:0])) & (~exp_right & (~|man_b_clear))) ||
((exp_right & (~|man_b_clear[4:0])) & (~exp_left & (~|man_a_clear))) ||
((exp_left & (|man_a_clear[4:0])) || (exp_right & (|man_b_clear[4:0]))))
make_nan_r <= 1'b1;
else
flush_mantissa_r <= 1'b1;
end
else if (exponent_1[9]) // resulting exponent is less than zero.
begin
exponent_2 <= 9'd0;
flush_mantissa_r <= 1'b1;
end
else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0))// resulting exponent is above max
begin
flush_mantissa_r <= 1'b1;
exponent_2 <= 9'h1ff;
end
else
exponent_2 <= exponent_1[8:0];
// Third cycle.
exp_zeroed <= ~|exponent_2;
flush_mantissa <= flush_mantissa_r;
exponent_3 <= exponent_2;
sign_3 <= sign_2;
valid_3 <= valid_2;
make_nan <= make_nan_r;
end
end
end
else
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exponent_1 <= 10'dx;
exponent_2 <= 9'dx;
exp_out_of_range <= 1'bx;
sign_1 <= 1'bx;
sign_2 <= 1'bx;
flush_mantissa <= 1'bx;
man_a_clear <= 5'dx;
man_b_clear <= 5'dx;
make_nan <= 1'bx;
valid_1 <= 1'b0;
valid_2 <= 1'b0;
exp_left <= 1'bx;
exp_right <= 1'bx;
exp_zeroed <= 1'bx;
end
else if (enable_mult_stage)
begin
valid_1 <= valid_in;
valid_2 <= valid_1;
sign_1 <= sign_left ^ sign_right;
sign_2 <= sign_1;
exp_out_of_range <= exponent_left[8] | exponent_right[8];
exp_left <= exponent_left[8];
exp_right <= exponent_right[8];
if ((exponent_left[8] || exponent_right[8]) && (FINITE_MATH_ONLY == 0))
exponent_1 <= 10'h1ff;
else
exponent_1 <= exponent_left + exponent_right - 10'd127;
man_a_clear <= {mantissa_left[26], |mantissa_left[25:21], |mantissa_left[20:15], |mantissa_left[14:10], |mantissa_left[9:5], |mantissa_left[4:0]};
man_b_clear <= {mantissa_right[26], |mantissa_right[25:21], |mantissa_right[20:15], |mantissa_right[14:10], |mantissa_right[9:5], |mantissa_right[4:0]};
// Second cycle.
flush_mantissa <= 1'b0;
make_nan <= 1'b0;
if (exp_out_of_range && (FINITE_MATH_ONLY == 0))
begin
exponent_2 <= 9'h1ff;
if (((exp_left & (~|man_a_clear[4:0])) & (~exp_right & (~|man_b_clear))) ||
((exp_right & (~|man_b_clear[4:0])) & (~exp_left & (~|man_a_clear))) ||
((exp_left & (|man_a_clear[4:0])) || (exp_right & (|man_b_clear[4:0]))))
make_nan <= 1'b1;
else
flush_mantissa <= 1'b1;
end
else if (exponent_1[9]) // resulting exponent is less than zero.
begin
exponent_2 <= 9'd0;
flush_mantissa <= 1'b1;
end
else if ((exponent_1[8:0] >= 9'd255) && (FINITE_MATH_ONLY == 0)) // resulting exponent is above max
begin
flush_mantissa <= 1'b1;
exponent_2 <= 9'h1ff;
end
else
exponent_2 <= exponent_1[8:0];
exp_zeroed <= ~|exponent_1;
end
end
end
endgenerate
// Now collect results in registers.
reg [27:0] mult_result_int;
reg [8:0] mult_exp_int;
reg mult_sign_int;
reg mult_valid_int;
reg [4:0] mult_tail_bits;
reg exp_was_zero;
reg clear_mantissa;
reg is_nan;
wire stall_post_int;
wire enable_post_mult_stage_int;
assign enable_post_mult_stage_int = (HIGH_CAPACITY == 1) ? (~mult_valid_int | ~stall_post_int) : enable;
assign stall_mult = mult_valid_int & stall_post_int;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
mult_valid_int <= 1'b0;
mult_result_int <= 28'dx;
mult_exp_int <= 9'dx;
clear_mantissa <= 1'bx;
mult_tail_bits <= 5'dx;
exp_was_zero <= 1'bx;
is_nan <= 1'bx;
mult_sign_int <= 1'bx;
end
else if (enable_post_mult_stage_int)
begin
mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2;
is_nan <= make_nan;
clear_mantissa <= flush_mantissa | ((FLUSH_DENORMS == 1) & exp_zeroed & (~|sub_wire0[53:52]));
mult_result_int <= sub_wire0[53:26];
exp_was_zero <= exp_zeroed;
mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2;
mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2;
if (REMOVE_STICKY == 1)
mult_tail_bits <= 5'd0;
else
mult_tail_bits <= {|sub_wire0[25:20],|sub_wire0[19:15],|sub_wire0[14:10],|sub_wire0[9:5],|sub_wire0[4:0]};
end
end
end
else
begin
always@(*)
begin
mult_valid_int <= (HIGH_LATENCY == 1) ? valid_3 : valid_2;
is_nan <= make_nan;
clear_mantissa <= flush_mantissa | ((FLUSH_DENORMS == 1) & exp_zeroed & (~|sub_wire0[53:52]));
mult_result_int <= sub_wire0[53:26];
exp_was_zero <= exp_zeroed;
mult_exp_int <= (HIGH_LATENCY == 1) ? exponent_3 : exponent_2;
mult_sign_int <= (HIGH_LATENCY == 1) ? sign_3 : sign_2;
if (REMOVE_STICKY == 1)
mult_tail_bits <= 5'd0;
else
mult_tail_bits <= {|sub_wire0[25:20],|sub_wire0[19:15],|sub_wire0[14:10],|sub_wire0[9:5],|sub_wire0[4:0]};
end
end
endgenerate
// Now collect results in registers.
reg [27:0] mult_result;
reg [8:0] mult_exp;
reg mult_sign;
reg mult_valid;
wire stall_post, enable_post_mult_stage;
assign enable_post_mult_stage = (HIGH_CAPACITY == 1) ? (~mult_valid | ~stall_post) : enable;
assign stall_post_int = mult_valid & stall_post;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
mult_valid <= 1'b0;
mult_result <= 28'dx;
mult_exp <= 9'dx;
mult_sign <= 1'bx;
end
else if (enable_post_mult_stage)
begin
mult_valid <= mult_valid_int;
if (REMOVE_STICKY == 1)
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:1]};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0];
end
else
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:2], |mult_result_int[1:0] | (|mult_tail_bits)};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] | (|mult_tail_bits)};
end
if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa)
mult_exp <= 9'd1;
else
mult_exp <= mult_exp_int;
mult_sign <= mult_sign_int;
end
end
end
else
begin
always@(*)
begin
mult_valid <= mult_valid_int;
if (REMOVE_STICKY == 1)
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:1]};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & mult_result_int[27:0];
end
else
begin
if (exp_was_zero & ~is_nan &~clear_mantissa)
mult_result <= {1'b0, mult_result_int[27:2], |mult_result_int[1:0] | (|mult_tail_bits)};
else
mult_result <= is_nan ? 28'h7ffffff : {28{~clear_mantissa}} & {mult_result_int[27:1], mult_result_int[0] | (|mult_tail_bits)};
end
if (exp_was_zero & ~is_nan & mult_result_int[27] & ~clear_mantissa)
mult_exp <= 9'd1;
else
mult_exp <= mult_exp_int;
mult_sign <= mult_sign_int;
end
end
endgenerate
// Now put a staging register if we are in high-capacity mode
generate
if (HIGH_CAPACITY == 1)
begin
reg [27:0] result_mantissa_sr;
reg [8:0] result_exponent_sr;
reg result_sign_sr;
reg result_sr_valid;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_mantissa_sr <= 28'dx;
result_exponent_sr <= 9'dx;
result_sign_sr <= 1'bx;
result_sr_valid <= 1'b0;
end
else
begin
if (~stall_in)
result_sr_valid <= 1'b0;
else if (~result_sr_valid)
result_sr_valid <= mult_valid;
if (~result_sr_valid)
begin
result_mantissa_sr <= mult_result;
result_exponent_sr <= mult_exp;
result_sign_sr <= mult_sign;
end
end
end
assign result_mantissa = result_sr_valid ? result_mantissa_sr : mult_result;
assign result_exponent = result_sr_valid ? result_exponent_sr : mult_exp;
assign result_sign = result_sr_valid ? result_sign_sr : mult_sign;
assign valid_out = result_sr_valid | mult_valid;
assign stall_post = result_sr_valid;
end
else
begin
assign result_mantissa = mult_result;
assign result_exponent = mult_exp;
assign result_sign = mult_sign;
assign valid_out = mult_valid;
assign stall_post = stall_in;
end
endgenerate
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
//
// Transfer takes 2 dCLK to see data,
// sRDY recovers takes 2 dCLK + 2 sCLK
module SyncHandshake(
sCLK,
sRST,
dCLK,
sEN,
sRDY,
dPulse
);
parameter init = 1'b0;
// Source clock port signal
input sCLK ;
input sRST ;
input sEN ;
output sRDY ;
// Destination clock port signal
input dCLK ;
output dPulse ;
// Flops to hold data
reg dSyncReg1, dSyncReg2 ;
reg dLastState ;
reg sToggleReg ;
reg sSyncReg1, sSyncReg2 ;
// Output signal
assign dPulse = dSyncReg2 != dLastState ;
assign sRDY = sSyncReg2 == sToggleReg;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ! init ; // Reset hi so sRDY is low during reset
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY ! init ;
sToggleReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
// hadshake return synchronizer
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;// clock domain crossing
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
// Pulse send
if ( sEN )
begin
sToggleReg <= `BSV_ASSIGNMENT_DELAY ! sToggleReg ;
end // if ( sEN )
end
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init;
dLastState <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sToggleReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
end
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
dSyncReg1 = init ;
dSyncReg2 = init ;
dLastState = init ;
sToggleReg = init ;
sSyncReg1 = ! init ;
sSyncReg2 = ! init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // HandshakeSync
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 7; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]==0) struct_bg <= '0;
else if (cnt[30:2]==1) struct_bg <= '0;
else if (cnt[30:2]==2) struct_bg <= '0;
else if (cnt[30:2]==3) struct_bg <= '0;
else if (cnt[30:2]==4) struct_bg <= '0;
else if (cnt[30:2]==5) struct_bg <= '0;
else if (cnt[30:2]==6) struct_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0};
// verilator lint_off WIDTH
else if (cnt[30:2]==4) struct_bg <= '{default:13};
else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
// verilator lint_on WIDTH
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_bg !== 15'b0_00_0000_00000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]==0) struct_lt <= '0;
else if (cnt[30:2]==1) struct_lt <= '0;
else if (cnt[30:2]==2) struct_lt <= '0;
else if (cnt[30:2]==3) struct_lt <= '0;
else if (cnt[30:2]==4) struct_lt <= '0;
else if (cnt[30:2]==5) struct_lt <= '0;
else if (cnt[30:2]==6) struct_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0};
// verilator lint_off WIDTH
else if (cnt[30:2]==4) struct_lt <= '{default:13};
else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
// verilator lint_on WIDTH
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_lt !== 15'b0_00_0000_00000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
//
// Copyright (c) 2003 Launchbird Design Systems, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
// Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Overview:
//
// Performs finite impulse response (FIR) filtering.
// The filter's sum of products is pipelined with a register after
// every multiplier and adder. The adder network is a balanced binary
// tree to minimize latency. The sum of products has no numeric loss because the
// multipliers keep all resulting bits and each adder extends the precision by 1.
//
// Interface:
//
// Synchronization:
// clock_c : Clock input.
// reset_i : Filter delay bank synchronous reset. Does not reset sum of products pipeline registers.
//
// Inputs:
// data_i : Input data.
// k0_i : Coefficient 0 multiplied by in_i(0).
// k1_i : Coefficient 1 multiplied by in_i(k-1).
// k2_i : Coefficient 2 multiplied by in_i(k-2).
// ...
// k<order>_i : Coefficient <order> multiplied by in_i(k-<order>).
//
// Outputs:
// data_o : Output data.
//
// Built In Parameters:
//
// Filter Order = 3
// Input Precision = 8
// Coefficient Precision = 8
// Sum of Products Latency = 3
//
//
//
//
// Generated by Confluence 0.6.3 -- Launchbird Design Systems, Inc. -- www.launchbird.com
//
// Build Date : Fri Aug 22 09:45:46 CDT 2003
//
// Interface
//
// Build Name : cf_fir_3_8_8
// Clock Domains : clock_c
// Vector Input : reset_i(1)
// Vector Input : data_i(8)
// Vector Input : k0_i(8)
// Vector Input : k1_i(8)
// Vector Input : k2_i(8)
// Vector Input : k3_i(8)
// Vector Output : data_o(18)
//
//
//
module cf_fir_3_8_8 (clock_c, reset_i, data_i, k0_i, k1_i, k2_i, k3_i, data_o);
input clock_c;
input reset_i;
input [7:0] data_i;
input [7:0] k0_i;
input [7:0] k1_i;
input [7:0] k2_i;
input [7:0] k3_i;
output [17:0] data_o;
wire [17:0] n1;
cf_fir_3_8_8_1 s1 (clock_c, reset_i, k0_i, k1_i, k2_i, k3_i, data_i, n1);
assign data_o = n1;
endmodule
module cf_fir_3_8_8_1 (clock_c, i1, i2, i3, i4, i5, i6, o1);
input clock_c;
input i1;
input [7:0] i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
output [17:0] o1;
wire n1;
wire n2;
wire [17:0] s3_1;
assign n1 = 1'b1;
assign n2 = 1'b0;
cf_fir_3_8_8_2 s3 (clock_c, n1, n2, i1, i2, i3, i4, i5, i6, s3_1);
assign o1 = s3_1;
endmodule
module cf_fir_3_8_8_2 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, o1);
input clock_c;
input i1;
input i2;
input i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [7:0] i8;
output [17:0] o1;
reg [7:0] n1;
reg [7:0] n2;
reg [7:0] n3;
reg [7:0] n4;
wire n5;
wire [17:0] n6;
wire n7;
wire [17:0] n8;
wire [17:0] n9;
reg [17:0] n10;
wire [16:0] s11_1;
wire [16:0] s11_2;
wire [15:0] s12_1;
wire [15:0] s12_2;
wire [15:0] s12_3;
wire [15:0] s12_4;
always @ (posedge clock_c)
begin
if (i3 == 1'b1)
n1 <= 8'b00000000;
else if (i1 == 1'b1)
n1 <= i8;
if (i3 == 1'b1)
n2 <= 8'b00000000;
else if (i1 == 1'b1)
n2 <= n1;
if (i3 == 1'b1)
n3 <= 8'b00000000;
else if (i1 == 1'b1)
n3 <= n2;
if (i3 == 1'b1)
n4 <= 8'b00000000;
else if (i1 == 1'b1)
n4 <= n3;
if (i2 == 1'b1)
n10 <= 18'b000000000000000000;
else if (i1 == 1'b1)
n10 <= n9;
end
assign n5 = s11_1[16];
assign n6 = {n5, s11_1};
assign n7 = s11_2[16];
assign n8 = {n7, s11_2};
assign n9 = n6 + n8;
cf_fir_3_8_8_4 s11 (clock_c, i1, i2, s12_1, s12_2, s12_3, s12_4, s11_1, s11_2);
cf_fir_3_8_8_3 s12 (clock_c, i1, i2, i4, i5, i6, i7, n1, n2, n3, n4, s12_1, s12_2, s12_3, s12_4);
assign o1 = n10;
endmodule
module cf_fir_3_8_8_3 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, o1, o2, o3, o4);
input clock_c;
input i1;
input i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [7:0] i8;
input [7:0] i9;
input [7:0] i10;
output [15:0] o1;
output [15:0] o2;
output [15:0] o3;
output [15:0] o4;
wire [15:0] n1;
reg [15:0] n2;
wire [15:0] n3;
reg [15:0] n4;
wire [15:0] n5;
reg [15:0] n6;
wire [15:0] n7;
reg [15:0] n8;
assign n1 = {8'b00000000, i3} * {8'b00000000, i7};
always @ (posedge clock_c)
begin
if (i2 == 1'b1)
n2 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n2 <= n1;
if (i2 == 1'b1)
n4 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n4 <= n3;
if (i2 == 1'b1)
n6 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n6 <= n5;
if (i2 == 1'b1)
n8 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n8 <= n7;
end
assign n3 = {8'b00000000, i4} * {8'b00000000, i8};
assign n5 = {8'b00000000, i5} * {8'b00000000, i9};
assign n7 = {8'b00000000, i6} * {8'b00000000, i10};
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule
module cf_fir_3_8_8_4 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2);
input clock_c;
input i1;
input i2;
input [15:0] i3;
input [15:0] i4;
input [15:0] i5;
input [15:0] i6;
output [16:0] o1;
output [16:0] o2;
wire n1;
wire [16:0] n2;
wire n3;
wire [16:0] n4;
wire [16:0] n5;
reg [16:0] n6;
wire n7;
wire [16:0] n8;
wire n9;
wire [16:0] n10;
wire [16:0] n11;
reg [16:0] n12;
assign n1 = i3[15];
assign n2 = {n1, i3};
assign n3 = i4[15];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
if (i2 == 1'b1)
n6 <= 17'b00000000000000000;
else if (i1 == 1'b1)
n6 <= n5;
if (i2 == 1'b1)
n12 <= 17'b00000000000000000;
else if (i1 == 1'b1)
n12 <= n11;
end
assign n7 = i5[15];
assign n8 = {n7, i5};
assign n9 = i6[15];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
assign o2 = n12;
assign o1 = n6;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] a = crc[7:0];
wire [7:0] b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.a (a[7:0]),
.b (b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, a, b
);
input clk;
input [7:0] a;
input [7:0] b;
output reg [63:0] out;
and u0[7:0] (out[7:0], a[7:0], b[7:0]);
and u1[7:0] (out[15:8], a[0], b[7:0]);
and u2[7:0] (out[23:16], a[0], b[0]);
nand u3[7:0] (out[31:24], a[0], b[7:0]);
or u4[7:0] (out[39:32], a[0], b[7:0]);
nor u5[7:0] (out[47:40], a[0], b[7:0]);
xor u6[7:0] (out[55:48], a[0], b[7:0]);
xnor u7[7:0] (out[63:56], a[0], b[7:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_1_V
`define SKY130_FD_SC_HS__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/06 20:23:23
// Design Name:
// Module Name: Mealy_FSM_ROM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mealy_FSM_ROM(
input clk,
input reset,
input x,
output reg [2:0] count
);
reg [2:0] state, nextState;
reg [5:0] ROM [0:11];
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5;
// set up ROM
initial begin
$readmemb("/home/sabertazimi/gitrepo/hust-lab/verilog/lab5/Mealy_FSM_ROM/Mealy_FSM_ROM.srcs/sources_1/new/Mealy_FSM_ROM.dat", ROM, 0, 11);
end
// update state
always @(posedge clk or posedge reset) begin
if (reset) state <= s1;
else state <= nextState;
end
/*
* compute nextState and output(count) with ROM
*/
/*
* address = (state * 2 + x + (!clk & !reset)) % 12
* !clk & !reset : handle little bug
* mod 12 : handle address overflow
*
* data = {nextState, count}
*
* ROM[(state * 2 + x + (!clk & !reset)) % 12] = {nextState, count}
*/
/*
* s0 x = 0: 000010
* s0 x = 1: 001000
* s1 x = 0: 001000
* s1 x = 0: 010001
* s2 x = 0: 010001
* s2 x = 0: 011011
* s3 x = 0: 011011
* s3 x = 0: 100101
* s4 x = 0: 100101
* s4 x = 0: 101111
* s5 x = 0: 101111
* s5 x = 0: 000010
*/
always @(x or state) begin
{nextState, count} <= ROM[(state * 2 + x + (!clk & !reset)) % 12];
end
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of enumerated type methods
//
// This code exercises the various enumeration methods
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// SPDX-License-Identifier: CC0-1.0
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
// **** Pin Identifiers ****
typedef enum int
{
PINID_A0 = 32'd0, // MUST BE ZERO!
// - Standard Ports -
PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7,
PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7,
PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7,
PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7,
PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7,
PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7,
PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7,
PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7,
// PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1
PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7,
PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7,
PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7,
PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7,
PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7,
// PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0
PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7,
PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7,
PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7,
// - AUX Port (Custom) -
PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7,
// - PDI Port -
PINID_D2W_DAT, PINID_D2W_CLK,
// - Power Pins -
PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3,
PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3,
// - Maximum number of pins -
PINID_MAX
} t_pinid;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
test test_i (/*AUTOINST*/
// Inputs
.clk (clk));
// This is a compile time only test. Immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module test (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Use the enumeration size to initialize a dynamic array
t_pinid e;
int myarray1 [] = new [e.num];
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Enumeration has %d members\n", e.num);
`endif
e = e.first;
forever begin
myarray1[e] <= e.prev;
`ifdef TEST_VERBOSE
$write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]);
`endif
if (e == e.last) begin
break;
end
else begin
e = e.next;
end
end
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// LUT mapping
`ifndef _NO_LUTS
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
if (LUT == 2'b01) begin
INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
end else begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]));
end
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5 && WIDTH <= `LUT_WIDTH) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6 && WIDTH <= `LUT_WIDTH) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 5 && WIDTH > `LUT_WIDTH) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
MUXF5 mux5(.I0(f0), .I1(f1), .S(A[4]), .O(Y));
end else
if (WIDTH == 6 && WIDTH > `LUT_WIDTH) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
MUXF6 mux6(.I0(f0), .I1(f1), .S(A[5]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[ 63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
MUXF7 mux7(.I0(f0), .I1(f1), .S(A[6]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
MUXF8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y));
end else
if (WIDTH == 9) begin
wire f0, f1;
\$lut #(.LUT(LUT[255: 0]), .WIDTH(8)) lut0 (.A(A[7:0]), .Y(f0));
\$lut #(.LUT(LUT[511:256]), .WIDTH(8)) lut1 (.A(A[7:0]), .Y(f1));
MUXF9 mux9(.I0(f0), .I1(f1), .S(A[8]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif
|
// hps_design_SMP_HPS_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_SMP_HPS_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
hps_design_SMP_HPS_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for in-order coalesced memory access.
//
// Properties - Coalesced: Yes, Ordered: Yes, Hazard-Safe: Yes, Pipelined: Yes
// (see lsu_top.v for details)
//
// Description: Requests are submitted as soon as possible to memory, stalled
// requests are coalesced with neighbouring requests if they
// access the same page of memory.
// Basic coalesced read unit:
// Accept read requests on the upstream interface. Requests are sent to
// the avalon bus as soon as they are recieved. If the avalon bus is
// stalling, requests to the same global-memory word are coalesced into
// a single request to improve efficiency.
//
// The request FIFO stores the byte-address to select the appropriate word
// out of the response data as well as an extra bit to indicate if the
// request is coalesced with the previous request or if a new request was
// made. The output port looks ahead to the next pending request to
// determine whether the current response data can be thrown away or
// must be kept to service the next coalesced request.
module lsu_basic_coalesced_read
(
clk, reset, o_stall, i_valid, i_address, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Determines the max number of live requests.
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
// Constants
localparam REQUEST_FIFO_DEPTH=2*KERNEL_SIDE_MEM_LATENCY;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
/***************
* Architecture *
***************/
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire [SEGMENT_SELECT_BITS:0] rf_data_in;
wire [BYTE_SELECT_BITS-1:0] byte_addr;
wire next_new_page;
wire c_stall;
wire c_new_page;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire rf_full;
wire rf_valid;
wire [SEGMENT_SELECT_BITS:0] rf_data;
wire rf_next_valid;
wire [SEGMENT_SELECT_BITS:0] rf_next_data;
wire rf_stall_in;
wire rm_stall;
wire rm_valid;
wire rm_active;
wire [MWIDTH-1:0] rm_data;
wire rm_stall_in;
// Coalescer - Groups subsequent requests together if they are compatible and
// the avalon bus is stalled.
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
basic_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(MWIDTH/WIDTH)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !rf_full),
.o_stall(c_stall),
.o_new_page(c_new_page),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(rm_stall)
);
// Response FIFO - Buffers the requests so they can be extracted from the
// wider memory bus. Stores the segment address to extract the requested
// word from the response data, and a bit indicating if the request comes
// from a new page.
generate if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_addr;
assign segment_addr = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
assign rf_data_in = {c_new_page, segment_addr};
assign byte_addr = (rf_data[SEGMENT_SELECT_BITS-1:0] << ALIGNMENT_ABITS);
end
else
begin
assign rf_data_in = c_new_page;
assign byte_addr = {BYTE_SELECT_BITS{1'b0}};
end
endgenerate
lookahead_fifo #(
.WIDTH( SEGMENT_SELECT_BITS + 1 ),
.DEPTH( REQUEST_FIFO_DEPTH )
) request_fifo (
.clk(clk),
.reset(reset),
.i_data( rf_data_in ),
.i_valid( i_valid && !c_stall ),
.o_full(rf_full),
.i_stall(rf_stall_in),
.o_valid(rf_valid),
.o_data(rf_data),
.o_next_valid(rf_next_valid),
.o_next_data(rf_next_data)
);
// Read master - Handles pipelined read transactions through MM-Avalon.
lsu_pipelined_read #(
.AWIDTH( AWIDTH ),
.WIDTH_BYTES( MWIDTH_BYTES ),
.MWIDTH_BYTES( MWIDTH_BYTES ),
.ALIGNMENT_ABITS( BYTE_SELECT_BITS ),
.KERNEL_SIDE_MEM_LATENCY( KERNEL_SIDE_MEM_LATENCY ),
.USEOUTPUTFIFO(1),
.USEINPUTFIFO( 1 ), // Add the latency adjusting input fifos
.PIPELINE_INPUT( 1 ) // Let's add a pipline input to the input side just to help with Fmax
) read_master (
.clk(clk),
.reset(reset),
.o_stall(rm_stall),
.i_valid(c_req_valid),
.i_address({c_req_addr, {BYTE_SELECT_BITS{1'b0}}}),
.i_stall(rm_stall_in),
.o_valid(rm_valid),
.o_active(rm_active),
.o_readdata(rm_data),
.avm_address(avm_address),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
// Control logic
// Highest bit of rf_next_data indicates whether this is a new avalon request
// (new page) or was coalesced into the previous request.
assign next_new_page = rf_next_data[SEGMENT_SELECT_BITS];
assign rm_stall_in = (!next_new_page && rf_next_valid) || rf_stall_in;
assign rf_stall_in = i_stall || !rm_valid;
// Output MUX
assign o_readdata = rm_data[8*byte_addr +: WIDTH];
// External control signals
assign o_stall = c_stall || rf_full;
assign o_valid = rm_valid && rf_valid;
assign o_active=rf_valid | rm_active;
endmodule
/******************************************************************************/
// Basic coalesced write unit:
// Accept write requests on the upstream interface. The avalon spec does
// not allow a request to change while it is being stalled, so the current
// request is registered in an output register stage and not modified.
// Subsequent requests are coalesced together as long as the output register
// stage is occupied (i.e. the avalon bus is stalling).
//
// TODO: The byte enable format is not actually compliant with the
// Avalon spec. Essentially we should not enable non-adjacent words in a write
// request. This is OK for the DDR Memory Controller as it accepts our
// non-compliant format. This needs to be investigated further.
module lsu_basic_coalesced_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter USE_BYTE_EN = 0;
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
// Constants
localparam COUNTER_WIDTH=8; // Determines the max writes 'in-flight'
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// Downstream interface
input i_stall;
output o_valid;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
input [WIDTH_BYTES-1:0] i_byteenable;
/***************
* Architecture *
***************/
wire input_accepted;
wire output_acknowledged;
wire write_accepted;
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire c_new_page;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire c_stall;
reg [COUNTER_WIDTH-1:0] occ_counter;
reg [COUNTER_WIDTH-1:0] ack_counter;
reg [COUNTER_WIDTH-1:0] next_counter;
reg [COUNTER_WIDTH-1:0] or_next_counter;
wire [COUNTER_WIDTH-1:0] rf_count;
wire rf_read;
wire rf_empty;
wire rf_full;
reg [MWIDTH-1:0] wm_writedata;
reg [MWIDTH_BYTES-1:0] wm_byteenable;
reg [MWIDTH-1:0] wm_wide_wdata;
reg [MWIDTH_BYTES-1:0] wm_wide_be;
reg [MWIDTH-1:0] wm_wide_bite;
wire or_ready;
reg or_write;
reg [AWIDTH-1:0] or_address;
reg [MWIDTH-1:0] or_writedata;
reg [MWIDTH_BYTES-1:0] or_byteenable;
wire oc_full;
// Output register stage to store the next request
assign or_ready = !or_write || !avm_waitrequest;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
or_write <= 1'b0;
or_address <= {AWIDTH{1'b0}};
or_writedata <= {MWIDTH{1'b0}};
or_byteenable <= {MWIDTH_BYTES{1'b0}};
or_next_counter <= {COUNTER_WIDTH{1'b0}};
end
else
begin
if(or_ready)
begin
or_write <= c_req_valid;
or_address <= (c_req_addr << BYTE_SELECT_BITS);
or_writedata <= wm_writedata;
or_byteenable <= wm_byteenable;
or_next_counter <= next_counter;
end
end
end
assign avm_address = or_address;
assign avm_write = or_write;
assign avm_writedata = or_writedata;
assign avm_byteenable = or_byteenable;
// The address components
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
// Coalescer - Groups subsequent requests together if they are compatible
// and the output register stage is stalled
basic_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(MWIDTH/WIDTH)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !oc_full),
.o_stall(c_stall),
.o_new_page(c_new_page),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(!or_ready)
);
// Writedata MUX
generate if( SEGMENT_SELECT_BITS > 0 )
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[segment_select*SEGMENT_WIDTH +: WIDTH] = {WIDTH{1'b1}};
end
end
else
begin
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[0 +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[0 +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}} ;
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[0 +: WIDTH] = {WIDTH{1'b1}};
end
end
endgenerate
// Track the current write burst data - coalesce writes together until the
// output registers are ready for a new request.
always@(posedge clk or posedge reset)
begin
if(reset)
begin
wm_writedata <= {MWIDTH{1'b0}};
wm_byteenable <= {MWIDTH_BYTES{1'b0}};
end
else
begin
if(c_new_page)
begin
wm_writedata <= wm_wide_wdata;
wm_byteenable <= wm_wide_be;
end
else if(input_accepted)
begin
wm_writedata <= (wm_wide_wdata & wm_wide_bite) | (wm_writedata & ~wm_wide_bite);
wm_byteenable <= wm_wide_be | wm_byteenable;
end
end
end
// Write size tracker - track the number of threads represented by each pending write request
acl_ll_fifo #(
.WIDTH(COUNTER_WIDTH),
.DEPTH(KERNEL_SIDE_MEM_LATENCY+1)
) req_fifo (
.clk(clk),
.reset(reset),
.data_in( or_next_counter ),
.data_out( rf_count ),
.write( write_accepted && (!rf_empty || !avm_writeack) ),
.read( rf_read ),
.empty( rf_empty ),
.full( rf_full )
);
assign rf_read = avm_writeack && !rf_empty;
// Occupancy counter - track the number of successfully transmitted writes
// and the number of writes pending in the next request.
// occ_counter - the total occupancy (in threads) of the unit
// next_counter - the number of threads coalesced into the next transfer
// ack_counter - the number of pending threads with write completion acknowledged
assign input_accepted = i_valid && !o_stall;
assign write_accepted = avm_write && !avm_waitrequest;
assign output_acknowledged = o_valid && !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
next_counter <= {COUNTER_WIDTH{1'b0}};
end
else
begin
occ_counter <= occ_counter + input_accepted - output_acknowledged;
next_counter <= input_accepted + ((c_req_valid & or_ready) ? {COUNTER_WIDTH{1'b0}} : next_counter);
ack_counter <= ack_counter + ({COUNTER_WIDTH{avm_writeack}} & ( rf_empty ? or_next_counter : rf_count )) - output_acknowledged;
end
end
assign oc_full = (occ_counter == {COUNTER_WIDTH{1'b1}});
// Pipeline control signals
assign o_stall = oc_full || c_stall || rf_full;
assign o_valid = (ack_counter > {COUNTER_WIDTH{1'b0}});
assign o_active = (occ_counter != {COUNTER_WIDTH{1'b0}});
endmodule
/******************************************************************************/
/* RESPONSE FIFO */
// lookahead_fifo - A simple sc_fifo instantiation with an additional
// shift-register stage at the end to provide access to the next two data
// items.
module lookahead_fifo
(
clk, reset, i_data, i_valid, o_full, i_stall, o_valid, o_data,
o_next_valid, o_next_data
);
parameter WIDTH=32;
parameter DEPTH=32;
input clk;
input reset;
input [WIDTH-1:0] i_data;
input i_valid;
output o_full;
input i_stall;
output reg o_valid;
output reg [WIDTH-1:0] o_data;
output o_next_valid;
output [WIDTH-1:0] o_next_data;
wire sr_ready;
// Fifo
acl_data_fifo #(
.DATA_WIDTH(WIDTH),
.DEPTH(DEPTH),
.IMPL("ram_plus_reg")
) req_fifo (
.clock(clk),
.resetn(!reset),
.data_in( i_data ),
.data_out( o_next_data ),
.valid_in( i_valid ),
.valid_out( o_next_valid ),
.stall_in( !sr_ready ),
.stall_out( o_full )
);
// Shift-reg
assign sr_ready = !o_valid || !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
o_data <= {WIDTH{1'b0}};
o_valid <= 1'b0;
end
else
begin
o_valid <= sr_ready ? o_next_valid : o_valid;
o_data <= sr_ready ? o_next_data : o_data;
end
end
endmodule
/* BASIC COALESCING MODULE */
// basic_coalescer - Accept new inputs as long as the unit is not stalled,
// or the new request can be coalesced with the pending (stalled) request.
module basic_coalescer
(
clk, reset, i_page_addr, i_valid, o_stall, o_new_page, o_req_addr,
o_req_valid, i_stall
);
parameter PAGE_ADDR_WIDTH=32;
parameter TIMEOUT=8; // power of 2
input clk;
input reset;
input [PAGE_ADDR_WIDTH-1:0] i_page_addr;
input i_valid;
output o_stall;
output o_new_page;
output [PAGE_ADDR_WIDTH-1:0] o_req_addr;
output o_req_valid;
input i_stall;
reg [PAGE_ADDR_WIDTH-1:0] page_addr;
reg valid;
wire ready;
wire waiting;
wire match;
wire timeout;
reg [$clog2(TIMEOUT):0] timeout_counter;
assign timeout = timeout_counter[$clog2(TIMEOUT)];
// Internal signal logic
assign match = (i_page_addr == page_addr);
assign ready = !valid || !(i_stall || waiting);
assign waiting = !timeout && (!i_valid || match);
always@(posedge clk or posedge reset)
begin
if(reset)
begin
page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
valid <= 1'b0;
timeout_counter <= '0;
end
else
begin
page_addr <= ready ? i_page_addr : page_addr;
valid <= ready ? i_valid : valid;
if( i_valid )
timeout_counter <= 'd1;
else if( valid && !timeout )
timeout_counter <= timeout_counter + 'd1;
end
end
// Outputs
assign o_stall = i_valid && !match && !ready;
assign o_new_page = ready;
assign o_req_addr = page_addr;
assign o_req_valid = valid && !waiting;
endmodule
|
module test01(clk,
led_gnd1, led_gnd2, //LED grounds
led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21,
led_second_tick
);
input wire clk;
output wire led_gnd1, led_gnd2;
output wire led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21, led_second_tick;
//clk - general clock 32768
reg [14:0] clk_div; initial clk_div <= 15'd0; //?? may be not implement
always @(posedge clk) clk_div <= clk_div + 1'b1;
wire divided_clk = clk_div[3];
reg divided_clk_prev;
always @(posedge clk) divided_clk_prev <= divided_clk;
wire divided_clk_posedge = ((divided_clk_prev==1'b0)&&(divided_clk==1'b1));
assign led_gnd1 = clk_div[0];
assign led_gnd2 = ~clk_div[0];
wire [3:0] m;
wire [3:0] mm;
wire [3:0] h;
wire [3:0] hh;
wire m_en = divided_clk_posedge;
wire mm_en;
wire h_en;
wire hh_en;
wire m_cy;
wire mm_cy;
wire h_cy;
wire hh_cy;
cntr #(.max(9)) cnt_m( .en(divided_clk_posedge), .clk(clk), .out(m), .cy(m_cy) );
cntr #(.max(5)) cnt_mm( .en(m_cy), .clk(clk), .out(mm), .cy(mm_cy) );
cntr #(.max(9)) cnt_h( .en(mm_cy), .clk(clk), .out(h), .cy(h_cy), .res((hh==2)&&(h==4)) );
cntr #(.max(2)) cnt_hh( .en(h_cy), .clk(clk), .out(hh), .cy(hh_cy), .res((hh==2)&&(h==4)) );
wire [6:0] s_m;
wire [6:0] s_mm;
wire [6:0] s_h;
wire [6:0] s_hh;
bcd2seg sseg_m( .sin(m), .sout(s_m));
bcd2seg sseg_mm(.sin(mm), .sout(s_mm));
bcd2seg sseg_h( .sin(h), .sout(s_h));
bcd2seg sseg_hh(.sin(hh), .sout(s_hh));
wire a1,b1,c1,d1,e1,f1,g1;
wire a2,b2,c2,d2,e2,f2,g2;
wire a3,b3,c3,d3,e3,f3,g3;
wire a4,b4,c4,d4,e4,f4,g4;
assign {g4, f4, e4, d4, c4, b4, a4} = s_m;
assign {g3, f3, e3, d3, c3, b3, a3} = s_mm;
assign {g2, f2, e2, d2, c2, b2, a2} = s_h;
assign {g1, f1, e1, d1, c1, b1, a1} = s_hh;
//hide hour zero
wire h_show = !(hh==0);
assign led6 = (led_gnd1) ? (b1&&h_show):(b1&&h_show); // b1
assign led7 = (led_gnd1) ? (a1&&h_show):(g1&&h_show); // a1/g1
assign led8 = (led_gnd1) ? (d1&&h_show):(e1&&h_show); // d1/e1
assign led9 = (led_gnd1) ? e2:(c1&&h_show); // e2/c1
assign led10 = (led_gnd1) ? g2:b2; // g2/b2
assign led12 = (led_gnd1) ? d2:c2; // d2/c2
assign led13 = (led_gnd1) ? f2:a2; // f2/a2
assign led15 = (led_gnd1) ? a3:f3; // a3/f3
assign led16 = (led_gnd1) ? b3:g3; // b3/g3
assign led17 = (led_gnd1) ? c3:d3; // c3/d3
assign led18 = (led_gnd1) ? e4:e3; // e3/e4 !!
assign led19 = (led_gnd1) ? g4:b4; // g4/b4
assign led20 = (led_gnd1) ? d4:c4; // d4/c4
assign led21 = (led_gnd1) ? f4:a4; // f4/a4
//one second tick indicator
assign led_second_tick = led_gnd1 && clk_div[14];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V |
module io1_sub(
/*AUTOARG*/
// Outputs
sec_out, lower_out,
// Inouts
sec_io, lower_io,
// Inputs
sec_ina, lower_ina
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To instio of instio.v
input sec_ina; // To instio of instio.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout lower_io; // To/From instio of instio.v
inout sec_io; // To/From instio of instio.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From instio of instio.v
output sec_out; // From instio of instio.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
.sec_out (sec_out),
// Inouts
.lower_io (lower_io),
.sec_io (sec_io),
// Inputs
.lower_ina (lower_ina),
.sec_ina (sec_ina));
endmodule
module instio (/*AUTOARG*/
// Outputs
lower_out, sec_out,
// Inouts
lower_io, sec_io,
// Inputs
lower_ina, sec_ina
);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
wire signed [7:0] sgn_wide;
wire [7:0] unsgn_wide;
// The instantiation will Z extend, not sign extend
// verilator lint_off WIDTH
sub sub (.clk,
.sgn(sgn_wide), .unsgn(unsgn_wide),
.iss(3'sh7), .isu(3'h7),
.ius(3'sh7), .iuu(3'h7));
// verilator lint_on WIDTH
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide);
`endif
if (sgn_wide[2:0] != 3'sh7) $stop;
if (unsgn_wide[2:0] != 3'h7) $stop;
// Simulators differ here.
if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
&& sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS
if (unsgn_wide !== 8'sbzzzzz111
&& unsgn_wide!== 8'sb00000111) $stop;
cyc <= cyc + 1;
if (cyc==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input clk,
output wire signed [2:0] sgn,
output wire [2:0] unsgn,
input signed [7:0] iss,
input signed [7:0] isu,
input [7:0] ius,
input [7:0] iuu);
assign sgn = 3'sh7;
assign unsgn = 3'h7;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("in: %x %x %x %x\n", iss, isu, ius, iuu);
if (iss != 8'hff) $stop;
if (isu != 8'h07) $stop;
if (ius != 8'hff) $stop;
if (iuu != 8'h07) $stop;
`endif
end
endmodule
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address Up-Sizer
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// a_upsizer
// generic_baseblocks/*
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_a_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of converter.
// Range: 32.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_AXI_CHANNEL = 0,
// 0 = AXI AW Channel.
// 1 = AXI AR Channel.
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_FIFO_MODE = 0,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_ID_QUEUE = 0,
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3
// Log2 of number of 32bit word on MI-side.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
output wire cmd_valid,
output wire cmd_fix,
output wire cmd_modified,
output wire cmd_complete_wrap,
output wire cmd_packed_wrap,
output wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
output wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
output wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
output wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
output wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
output wire [C_S_AXI_BYTES_LOG:0] cmd_step,
output wire [8-1:0] cmd_length,
output wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire cmd_ready,
input wire cmd_id_ready,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_si_addr,
output wire [C_AXI_ID_WIDTH-1:0] cmd_si_id,
output wire [8-1:0] cmd_si_len,
output wire [3-1:0] cmd_si_size,
output wire [2-1:0] cmd_si_burst,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,
input wire [8-1:0] S_AXI_ALEN,
input wire [3-1:0] S_AXI_ASIZE,
input wire [2-1:0] S_AXI_ABURST,
input wire [2-1:0] S_AXI_ALOCK,
input wire [4-1:0] S_AXI_ACACHE,
input wire [3-1:0] S_AXI_APROT,
input wire [4-1:0] S_AXI_AREGION,
input wire [4-1:0] S_AXI_AQOS,
input wire S_AXI_AVALID,
output wire S_AXI_AREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,
output wire [8-1:0] M_AXI_ALEN,
output wire [3-1:0] M_AXI_ASIZE,
output wire [2-1:0] M_AXI_ABURST,
output wire [2-1:0] M_AXI_ALOCK,
output wire [4-1:0] M_AXI_ACACHE,
output wire [3-1:0] M_AXI_APROT,
output wire [4-1:0] M_AXI_AREGION,
output wire [4-1:0] M_AXI_AQOS,
output wire M_AXI_AVALID,
input wire M_AXI_AREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Decode the native transaction size on the SI-side interface.
localparam [3-1:0] C_S_AXI_NATIVE_SIZE = (C_S_AXI_DATA_WIDTH == 1024) ? 3'b111 :
(C_S_AXI_DATA_WIDTH == 512) ? 3'b110 :
(C_S_AXI_DATA_WIDTH == 256) ? 3'b101 :
(C_S_AXI_DATA_WIDTH == 128) ? 3'b100 :
(C_S_AXI_DATA_WIDTH == 64) ? 3'b011 :
(C_S_AXI_DATA_WIDTH == 32) ? 3'b010 :
(C_S_AXI_DATA_WIDTH == 16) ? 3'b001 :
3'b000;
// Decode the native transaction size on the MI-side interface.
localparam [3-1:0] C_M_AXI_NATIVE_SIZE = (C_M_AXI_DATA_WIDTH == 1024) ? 3'b111 :
(C_M_AXI_DATA_WIDTH == 512) ? 3'b110 :
(C_M_AXI_DATA_WIDTH == 256) ? 3'b101 :
(C_M_AXI_DATA_WIDTH == 128) ? 3'b100 :
(C_M_AXI_DATA_WIDTH == 64) ? 3'b011 :
(C_M_AXI_DATA_WIDTH == 32) ? 3'b010 :
(C_M_AXI_DATA_WIDTH == 16) ? 3'b001 :
3'b000;
// Constants used to generate maximum length on SI-side for complete wrap.
localparam [24-1:0] C_DOUBLE_LEN = 24'b0000_0000_0000_0000_1111_1111;
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
// Depth for command FIFO.
localparam integer C_FIFO_DEPTH_LOG = 5;
// Maximum address bit coverage by WRAP.
localparam integer C_BURST_BYTES_LOG = 4 + C_S_AXI_BYTES_LOG;
// Calculate unused address bits.
localparam integer C_SI_UNUSED_LOG = C_AXI_ADDR_WIDTH-C_S_AXI_BYTES_LOG;
localparam integer C_MI_UNUSED_LOG = C_AXI_ADDR_WIDTH-C_M_AXI_BYTES_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Access decoding related signals.
wire access_is_fix;
wire access_is_incr;
wire access_is_wrap;
wire access_is_modifiable;
wire access_is_unaligned;
reg [8-1:0] si_maximum_length;
wire [16-1:0] mi_word_intra_len_complete;
wire [20-1:0] mask_help_vector;
reg [C_M_AXI_BYTES_LOG-1:0] mi_word_intra_len;
reg [8-1:0] upsized_length;
wire sub_sized_wrap;
reg [C_M_AXI_BYTES_LOG-1:0] size_mask;
reg [C_BURST_BYTES_LOG-1:0] burst_mask;
// Translation related signals.
wire access_need_extra_word;
wire [8-1:0] adjusted_length;
wire [C_BURST_BYTES_LOG-1:0] wrap_addr_aligned;
// Command buffer help signals.
wire cmd_empty;
wire s_ready;
wire cmd_full;
wire allow_new_cmd;
wire cmd_push;
reg cmd_push_block;
wire s_id_ready;
// Internal Command Interface signals.
wire cmd_valid_i;
wire cmd_fix_i;
wire cmd_modified_i;
wire cmd_complete_wrap_i;
wire cmd_packed_wrap_i;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_ii;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word_ii;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word_i;
wire [C_M_AXI_BYTES_LOG:0] cmd_last_word_ii;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset_i;
reg [C_M_AXI_BYTES_LOG-1:0] cmd_mask_i;
wire [3-1:0] cmd_size_i;
wire [3-1:0] cmd_size;
reg [8-1:0] cmd_step_ii;
wire [C_S_AXI_BYTES_LOG:0] cmd_step_i;
reg [8-1:0] cmd_length_i;
// Internal SI-side signals.
wire S_AXI_AREADY_I;
// Internal MI-side signals.
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;
reg [8-1:0] M_AXI_ALEN_I;
reg [3-1:0] M_AXI_ASIZE_I;
reg [2-1:0] M_AXI_ABURST_I;
wire [2-1:0] M_AXI_ALOCK_I;
wire [4-1:0] M_AXI_ACACHE_I;
wire [3-1:0] M_AXI_APROT_I;
wire [4-1:0] M_AXI_AREGION_I;
wire [4-1:0] M_AXI_AQOS_I;
wire M_AXI_AVALID_I;
wire M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Decode the incoming transaction:
//
// Determine the burst type sucha as FIX, INCR and WRAP. Only WRAP and INCR
// transactions can be upsized to the MI-side data width.
// Detect if the transaction is modifiable and if it is of native size. Only
// native sized transaction are upsized when allowed, unless forced by
// parameter. FIX can never be upsized (packed) regardless if force is
// turned on. However the FIX data will be steered to the correct
// byte lane(s) and the transaction will be native on MI-side when
// applicable.
//
// Calculate the MI-side length for the SI-side transaction.
//
// Decode the affected address bits in the MI-side. Used to determine last
// word for a burst and if necassarily adjust the length of the upsized
// transaction. Length adjustment only occurs when the trasaction is longer
// than can fit in MI-side and there is an unalignment for the first word
// (and the last word crosses MI-word boundary and wraps).
//
// The maximum allowed SI-side length is calculated to be able to determine
// if a WRAP transaction can fit inside a single MI-side data word.
//
// Determine address bits mask for the SI-side transaction size, i.e. address
// bits that shall be removed for unalignment when managing data in W and
// R channels. For example: the two least significant bits are not used
// for data packing in a 32-bit SI-side transaction (address 1-3 will appear
// as 0 for the W and R channels, but the untouched address is still forwarded
// to the MI-side).
//
// Determine the Mask bits for the address bits that are affected by a
// sub-sized WRAP transaction (up to and including complete WRAP). The Mask
// is used to generate the correct data mapping for a sub-sized and
// complete WRAP, i.e. having a local wrap in a partial MI-side word.
//
// Detect any SI-side address unalignment when used on the MI-side.
//
/////////////////////////////////////////////////////////////////////////////
assign cmd_si_addr = S_AXI_AADDR;
assign cmd_si_id = C_SUPPORTS_ID ? S_AXI_AID : 1'b0;
assign cmd_si_len = S_AXI_ALEN;
assign cmd_si_size = S_AXI_ASIZE;
assign cmd_si_burst = S_AXI_ABURST;
// Transaction burst type.
assign access_is_fix = ( S_AXI_ABURST == C_FIX_BURST );
assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );
assign access_is_wrap = ( S_AXI_ABURST == C_WRAP_BURST );
assign cmd_fix_i = access_is_fix;
// Get if it is allowed to modify transaction.
assign access_is_modifiable = S_AXI_ACACHE[1];
// Get SI-side maximum length to fit MI-side.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b000 ? C_DOUBLE_LEN[ 8-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b001: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b001 ? C_DOUBLE_LEN[ 9-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b010: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b010 ? C_DOUBLE_LEN[10-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b011: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b011 ? C_DOUBLE_LEN[11-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b100: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b100 ? C_DOUBLE_LEN[12-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b101: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b101 ? C_DOUBLE_LEN[13-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b110: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b110 ? C_DOUBLE_LEN[14-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
3'b111: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b111 ? C_DOUBLE_LEN[15-C_M_AXI_BYTES_LOG +: 8] : 8'b0;
endcase
end
// Help vector to determine the length of thransaction in the MI-side domain.
assign mi_word_intra_len_complete = {S_AXI_ALEN, 8'b0};
// Get intra MI-side word length bits (in bytes).
always @ *
begin
if ( ~cmd_fix_i ) begin
case (S_AXI_ASIZE)
3'b000: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mi_word_intra_len_complete[8-0 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b001: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b001 ?
mi_word_intra_len_complete[8-1 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b010: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b010 ?
mi_word_intra_len_complete[8-2 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b011: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b011 ?
mi_word_intra_len_complete[8-3 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b100: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b100 ?
mi_word_intra_len_complete[8-4 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b101: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b101 ?
mi_word_intra_len_complete[8-5 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b110: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b110 ?
mi_word_intra_len_complete[8-6 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b111: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b111 ?
mi_word_intra_len_complete[8-7 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; // Illegal setting.
endcase
end else begin
mi_word_intra_len = {C_M_AXI_BYTES_LOG{1'b0}};
end
end
// Get MI-side length after upsizing.
always @ *
begin
if ( cmd_fix_i | ~cmd_modified_i ) begin
// Fix has to maintain length even if forced packing.
upsized_length = S_AXI_ALEN;
end else begin
case (S_AXI_ASIZE)
3'b000: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-0) : 8'b0;
3'b001: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b001 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-1) : 8'b0;
3'b010: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b010 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-2) : 8'b0;
3'b011: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b011 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-3) : 8'b0;
3'b100: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b100 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-4) : 8'b0;
3'b101: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b101 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-5) : 8'b0;
3'b110: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b110 ?
(S_AXI_ALEN >> C_M_AXI_BYTES_LOG-6) : 8'b0;
3'b111: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b111 ?
(S_AXI_ALEN ) : 8'b0; // Illegal setting.
endcase
end
end
// Generate address bits used for SI-side transaction size.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: size_mask = ~C_DOUBLE_LEN[8 +: C_S_AXI_BYTES_LOG];
3'b001: size_mask = ~C_DOUBLE_LEN[7 +: C_S_AXI_BYTES_LOG];
3'b010: size_mask = ~C_DOUBLE_LEN[6 +: C_S_AXI_BYTES_LOG];
3'b011: size_mask = ~C_DOUBLE_LEN[5 +: C_S_AXI_BYTES_LOG];
3'b100: size_mask = ~C_DOUBLE_LEN[4 +: C_S_AXI_BYTES_LOG];
3'b101: size_mask = ~C_DOUBLE_LEN[3 +: C_S_AXI_BYTES_LOG];
3'b110: size_mask = ~C_DOUBLE_LEN[2 +: C_S_AXI_BYTES_LOG];
3'b111: size_mask = ~C_DOUBLE_LEN[1 +: C_S_AXI_BYTES_LOG]; // Illegal setting.
endcase
end
// Help vector to determine the length of thransaction in the MI-side domain.
assign mask_help_vector = {4'b0, S_AXI_ALEN, 8'b1};
// Calculate the address bits that are affected when a complete wrap is detected.
always @ *
begin
if ( sub_sized_wrap ) begin
case (S_AXI_ASIZE)
3'b000: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-0 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b001: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-1 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b010: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-2 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b011: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-3 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b100: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-4 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b101: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-5 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b110: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-6 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};
3'b111: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-7 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; // Illegal setting.
endcase
end else begin
cmd_mask_i = {C_M_AXI_BYTES_LOG{1'b1}};
end
end
// Calculate the address bits that are affected when a complete wrap is detected.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-0 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b001: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-1 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b010: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-2 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b011: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-3 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b100: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-4 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b101: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-5 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b110: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-6 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};
3'b111: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ?
mask_help_vector[8-7 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; // Illegal setting.
endcase
end
// Propagate the SI-side size of the transaction.
assign cmd_size_i = S_AXI_ASIZE;
// Detect if there is any unalignment in regards to the MI-side.
assign access_is_unaligned = ( S_AXI_AADDR[0 +: C_M_AXI_BYTES_LOG] != {C_M_AXI_BYTES_LOG{1'b0}} );
/////////////////////////////////////////////////////////////////////////////
// Evaluate if transaction is to be translated:
// * Forcefully translate when C_PACKING_LEVEL is set to C_ALWAYS_PACK.
// * When SI-side transaction size is native, it is allowed and default
// packing is set. (Expander mode never packs).
//
/////////////////////////////////////////////////////////////////////////////
// Modify transaction forcefully or when transaction allows it
assign cmd_modified_i = ~access_is_fix &
( ( C_PACKING_LEVEL == C_ALWAYS_PACK ) |
( access_is_modifiable & ( S_AXI_ALEN != 8'b0 ) & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) );
/////////////////////////////////////////////////////////////////////////////
// Translate SI-side access to MI-side:
//
// Detemine if this is a complete WRAP. Conditions are that it must fit
// inside a single MI-side data word, it must be a WRAP access and that
// bursts are allowed. Without burst there can never be a WRAP access.
//
// Determine if this ia a packed WRAP, i.e. a WRAP that is to large to
// be a complete wrap and it is unaligned SI-side address relative to
// the native MI-side data width.
//
// The address for the First SI-side data word is adjusted to when there
// is a complete WRAP, otherwise it only the least significant bits of the
// SI-side address.
// For complete WRAP access the Offset is generated as the most significant
// bits that are left by the Mask.
// Last address is calculated with the adjusted First word address.
//
// The Adjusted MI-side burst length is calculated as the Upsized length
// plus one when the SI-side data must wrap on the MI-side (unless it is
// a complete or packed WRAP).
//
// Depending on the conditions some of the forwarded MI-side tranaction
// and Command Queue parameters has to be adjusted:
// * For unmodified transaction the parameter are left un affected.
// (M_AXI_AADDR, M_AXI_ASIZE, M_AXI_ABURST, M_AXI_ALEN and cmd_length
// are untouched)
// * For complete WRAP transactions the burst type is changed to INCR
// and the address is adjusted to the sub-size affected by the transaction
// (the sub-size can be 2 bytes up to a full MI-side data word).
// The size is set to the native MI-side transaction size. And the length
// is set to the calculated upsized length.
// * For all other modified transations the address and burst type remains
// the same. The length is adjusted to the previosly described length
// and size is set to native MI-side transaction size.
//
/////////////////////////////////////////////////////////////////////////////
// Detemine if this is a sub-sized transaction.
assign sub_sized_wrap = access_is_wrap & ( S_AXI_ALEN <= si_maximum_length );
// See if entite burst can fit inside one MI-side word.
assign cmd_complete_wrap_i = cmd_modified_i & sub_sized_wrap;
// Detect if this is a packed WRAP (multiple MI-side words).
assign cmd_packed_wrap_i = cmd_modified_i & access_is_wrap & ( S_AXI_ALEN > si_maximum_length ) &
access_is_unaligned;
// Get unalignment address bits (including aligning it inside covered area).
assign cmd_first_word_ii = S_AXI_AADDR[C_M_AXI_BYTES_LOG-1:0];
assign cmd_first_word_i = cmd_first_word_ii & cmd_mask_i & size_mask;
// Generate next word address.
assign cmd_next_word_ii = cmd_first_word_ii + cmd_step_ii[C_M_AXI_BYTES_LOG-1:0];
assign cmd_next_word_i = cmd_next_word_ii & cmd_mask_i & size_mask;
// Offset is the bits that is outside of the Mask.
assign cmd_offset_i = cmd_first_word_ii & ~cmd_mask_i;
// Select RTL or Optimized implementation.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADJUSTED_LEN
// Calculate Last word on MI-side.
assign cmd_last_word_ii = cmd_first_word_i + mi_word_intra_len;
assign cmd_last_word_i = cmd_last_word_ii[C_M_AXI_BYTES_LOG-1:0] & cmd_mask_i & size_mask;
// Detect if extra word on MI-side is needed.
assign access_need_extra_word = cmd_last_word_ii[C_M_AXI_BYTES_LOG] &
access_is_incr & cmd_modified_i;
// Calculate true length of modified transaction.
assign adjusted_length = upsized_length + access_need_extra_word;
end else begin : USE_FPGA_ADJUSTED_LEN
wire [C_M_AXI_BYTES_LOG:0] last_word_local_carry;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_sel;
wire [C_M_AXI_BYTES_LOG:0] last_word_for_mask_local_carry;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry1;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry2;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry3;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_sel;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask;
wire [C_M_AXI_BYTES_LOG-1:0] last_word_mask;
wire sel_access_need_extra_word;
wire [8:0] adjusted_length_local_carry;
wire [8-1:0] adjusted_length_sel;
assign last_word_local_carry[0] = 1'b0;
assign last_word_for_mask_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LAST_MASK
assign last_word_for_mask_sel[bit_cnt] = cmd_first_word_ii[bit_cnt] ^ mi_word_intra_len[bit_cnt];
assign last_word_mask[bit_cnt] = cmd_mask_i[bit_cnt] & size_mask[bit_cnt];
MUXCY and_inst1
(
.O (last_word_for_mask_dummy_carry1[bit_cnt]),
.CI (last_word_for_mask_local_carry[bit_cnt]),
.DI (mi_word_intra_len[bit_cnt]),
.S (last_word_for_mask_sel[bit_cnt])
);
MUXCY and_inst2
(
.O (last_word_for_mask_dummy_carry2[bit_cnt]),
.CI (last_word_for_mask_dummy_carry1[bit_cnt]),
.DI (1'b0),
.S (1'b1)
);
MUXCY and_inst3
(
.O (last_word_for_mask_dummy_carry3[bit_cnt]),
.CI (last_word_for_mask_dummy_carry2[bit_cnt]),
.DI (1'b0),
.S (1'b1)
);
MUXCY and_inst4
(
.O (last_word_for_mask_local_carry[bit_cnt+1]),
.CI (last_word_for_mask_dummy_carry3[bit_cnt]),
.DI (1'b0),
.S (1'b1)
);
XORCY xorcy_inst
(
.O(last_word_for_mask[bit_cnt]),
.CI(last_word_for_mask_local_carry[bit_cnt]),
.LI(last_word_for_mask_sel[bit_cnt])
);
generic_baseblocks_v2_1_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) last_mask_inst
(
.CIN(last_word_for_mask[bit_cnt]),
.I(last_word_mask[bit_cnt]),
.O(cmd_last_word_i[bit_cnt])
);
end // end for bit_cnt
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LAST
assign last_word_sel[bit_cnt] = cmd_first_word_ii[bit_cnt] ^ mi_word_intra_len[bit_cnt];
MUXCY and_inst
(
.O (last_word_local_carry[bit_cnt+1]),
.CI (last_word_local_carry[bit_cnt]),
.DI (mi_word_intra_len[bit_cnt]),
.S (last_word_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(cmd_last_word_ii[bit_cnt]),
.CI(last_word_local_carry[bit_cnt]),
.LI(last_word_sel[bit_cnt])
);
end // end for bit_cnt
assign sel_access_need_extra_word = access_is_incr & cmd_modified_i;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) access_need_extra_word_inst
(
.CIN(last_word_local_carry[C_M_AXI_BYTES_LOG]),
.S(sel_access_need_extra_word),
.COUT(adjusted_length_local_carry[0])
);
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : LUT_ADJUST
assign adjusted_length_sel[bit_cnt] = ( upsized_length[bit_cnt] & cmd_modified_i) |
( S_AXI_ALEN[bit_cnt] & ~cmd_modified_i);
MUXCY and_inst
(
.O (adjusted_length_local_carry[bit_cnt+1]),
.CI (adjusted_length_local_carry[bit_cnt]),
.DI (1'b0),
.S (adjusted_length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(adjusted_length[bit_cnt]),
.CI(adjusted_length_local_carry[bit_cnt]),
.LI(adjusted_length_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Generate adjusted wrap address.
assign wrap_addr_aligned = ( C_AXI_CHANNEL != 0 ) ?
( S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] ) :
( S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] + ( 2 ** C_M_AXI_BYTES_LOG ) );
// Select directly forwarded or modified transaction.
always @ *
begin
if ( cmd_modified_i ) begin
// SI to MI-side transaction translation.
if ( cmd_complete_wrap_i ) begin
// Complete wrap is turned into incr
M_AXI_AADDR_I = S_AXI_AADDR & {{C_MI_UNUSED_LOG{1'b1}}, ~cmd_mask_i};
M_AXI_ABURST_I = C_INCR_BURST;
end else begin
// Retain the currenent
if ( cmd_packed_wrap_i ) begin
M_AXI_AADDR_I = {S_AXI_AADDR[C_BURST_BYTES_LOG +: C_AXI_ADDR_WIDTH-C_BURST_BYTES_LOG],
(S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] & ~burst_mask) | (wrap_addr_aligned & burst_mask) } &
{{C_MI_UNUSED_LOG{1'b1}}, ~cmd_mask_i};
end else begin
M_AXI_AADDR_I = S_AXI_AADDR;
end
M_AXI_ABURST_I = S_AXI_ABURST;
end
M_AXI_ASIZE_I = C_M_AXI_NATIVE_SIZE;
end else begin
// SI to MI-side transaction forwarding.
M_AXI_AADDR_I = S_AXI_AADDR;
M_AXI_ASIZE_I = S_AXI_ASIZE;
M_AXI_ABURST_I = S_AXI_ABURST;
end
M_AXI_ALEN_I = adjusted_length;
cmd_length_i = adjusted_length;
end
/////////////////////////////////////////////////////////////////////////////
// Forward the command to the MI-side interface.
//
// It is determined that this is an allowed command/access when there is
// room in the command queue (and it passes any ID checks as required).
//
/////////////////////////////////////////////////////////////////////////////
// Select RTL or Optimized implementation.
generate
if ( C_FAMILY == "rtl" || ( C_SUPPORTS_ID == 0 ) ) begin : USE_RTL_AVALID
// Only allowed to forward translated command when command queue is ok with it.
assign M_AXI_AVALID_I = allow_new_cmd & S_AXI_AVALID;
end else begin : USE_FPGA_AVALID
wire sel_s_axi_avalid;
assign sel_s_axi_avalid = S_AXI_AVALID & ~ARESET;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) avalid_inst
(
.CIN(allow_new_cmd),
.S(sel_s_axi_avalid),
.COUT(M_AXI_AVALID_I)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Simple transfer of paramters that doesn't need to be adjusted.
//
// ID - Transaction still recognized with the same ID.
// LOCK - No need to change exclusive or barrier transactions.
// CACHE - No need to change the chache features. Even if the modyfiable
// bit is overridden (forcefully) there is no need to let downstream
// component beleive it is ok to modify it further.
// PROT - Security level of access is not changed when upsizing.
// REGION - Address region stays the same.
// QOS - Quality of Service remains the same.
// USER - User bits remains the same.
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_ALOCK_I = S_AXI_ALOCK;
assign M_AXI_ACACHE_I = S_AXI_ACACHE;
assign M_AXI_APROT_I = S_AXI_APROT;
assign M_AXI_AREGION_I = S_AXI_AREGION;
assign M_AXI_AQOS_I = S_AXI_AQOS;
/////////////////////////////////////////////////////////////////////////////
// Command queue to W/R channel.
//
// Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
// A flag is set if MI-side is stalling when Command is pushed to the
// Cmd FIFO. This will prevent multiple push of the same Command as well as
// keeping the MI-side Valid signal if the Allow Cmd requirement has been
// updated to disable furter Commands (I.e. it is made sure that the SI-side
// Command has been forwarded to both Cmd FIFO and MI-side).
//
// It is allowed to continue pushing new commands as long as
// * There is room in the queue
// * The ID is the same as previously queued. Since data is not reordered
// for the same ID it is ok to let them proceed.
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ID_QUEUE != 0 ) begin : gen_id_queue
generic_baseblocks_v2_1_command_fifo #
(
.C_FAMILY ("rtl"),
.C_ENABLE_S_VALID_CARRY (0),
.C_ENABLE_REGISTERED_OUTPUT (1),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH (C_AXI_ID_WIDTH)
)
id_queue
(
.ACLK (ACLK),
.ARESET (ARESET),
.EMPTY (),
.S_MESG (S_AXI_AID),
.S_VALID (cmd_push),
.S_READY (s_id_ready),
.M_MESG (cmd_id),
.M_VALID (),
.M_READY (cmd_id_ready)
);
end else begin : gen_no_id_queue
assign cmd_id = 1'b0;
assign s_id_ready = 1'b1;
end
endgenerate
// Check if it is allowed to push more commands (ID is allowed and there is room in the queue).
assign allow_new_cmd = (~cmd_full & s_id_ready) | cmd_push_block;
// Push new command when allowed and MI-side is able to receive the command.
assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;
// Block further push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_push_block <= 1'b0;
end else begin
cmd_push_block <= M_AXI_AVALID_I & ~M_AXI_AREADY_I;
end
end
// Acknowledge command when we can push it into queue (and forward it).
assign S_AXI_AREADY_I = M_AXI_AREADY_I & allow_new_cmd & ~ARESET;
assign S_AXI_AREADY = S_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Instantiate a FIFO as the queue and adjust the control signals.
//
// Decode size to step before passing it along.
//
// When there is no need for bursts the command FIFO can be greatly reduced
// becase the following is always true:
// * first = last
// * length = 0
// * nothing can be packed (i.e. no WRAP at all)
// * never any sub-size wraping => static offset (0) and mask (1)
//
/////////////////////////////////////////////////////////////////////////////
// Translate SI-side size to step for upsizer function.
always @ *
begin
case (cmd_size_i)
3'b000: cmd_step_ii = 8'b00000001;
3'b001: cmd_step_ii = 8'b00000010;
3'b010: cmd_step_ii = 8'b00000100;
3'b011: cmd_step_ii = 8'b00001000;
3'b100: cmd_step_ii = 8'b00010000;
3'b101: cmd_step_ii = 8'b00100000;
3'b110: cmd_step_ii = 8'b01000000;
3'b111: cmd_step_ii = 8'b10000000; // Illegal setting.
endcase
end
// Get only the applicable bits in step.
assign cmd_step_i = cmd_step_ii[C_S_AXI_BYTES_LOG:0];
generate
if (C_FIFO_MODE == 0) begin : GEN_CMD_QUEUE
// Instantiated queue.
generic_baseblocks_v2_1_command_fifo #
(
.C_FAMILY (C_FAMILY),
.C_ENABLE_S_VALID_CARRY (1),
.C_ENABLE_REGISTERED_OUTPUT (1),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH (1+1+1+1+C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+
C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+C_S_AXI_BYTES_LOG+1+8)
)
cmd_queue
(
.ACLK (ACLK),
.ARESET (ARESET),
.EMPTY (cmd_empty),
.S_MESG ({cmd_fix_i, cmd_modified_i, cmd_complete_wrap_i, cmd_packed_wrap_i, cmd_first_word_i, cmd_next_word_i,
cmd_last_word_i, cmd_offset_i, cmd_mask_i, cmd_step_i, cmd_length_i}),
.S_VALID (cmd_push),
.S_READY (s_ready),
.M_MESG ({cmd_fix, cmd_modified, cmd_complete_wrap, cmd_packed_wrap, cmd_first_word, cmd_next_word,
cmd_last_word, cmd_offset, cmd_mask, cmd_step, cmd_length}),
.M_VALID (cmd_valid_i),
.M_READY (cmd_ready)
);
// Queue is concidered full when not ready.
assign cmd_full = ~s_ready;
// Assign external signal.
assign cmd_valid = cmd_valid_i;
end else begin : NO_CMD_QUEUE
reg [C_FIFO_DEPTH_LOG-1:0] cmd_cnt;
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_cnt <= 0;
end else begin
if (cmd_push & ~cmd_ready) begin
cmd_cnt <= cmd_cnt + 1;
end else if (~cmd_push & cmd_ready & |cmd_cnt) begin
cmd_cnt <= cmd_cnt - 1;
end
end
end
assign cmd_full = &cmd_cnt;
assign cmd_empty = cmd_cnt == 0;
assign cmd_fix = 1'b0 ;
assign cmd_modified = 1'b0 ;
assign cmd_complete_wrap = 1'b0 ;
assign cmd_packed_wrap = 1'b0 ;
assign cmd_first_word = 0 ;
assign cmd_next_word = 0 ;
assign cmd_last_word = 0 ;
assign cmd_offset = 0 ;
assign cmd_mask = 0 ;
assign cmd_step = 0 ;
assign cmd_length = 0 ;
assign cmd_valid = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_q;
reg [8-1:0] M_AXI_ALEN_q;
reg [3-1:0] M_AXI_ASIZE_q;
reg [2-1:0] M_AXI_ABURST_q;
reg [2-1:0] M_AXI_ALOCK_q;
reg [4-1:0] M_AXI_ACACHE_q;
reg [3-1:0] M_AXI_APROT_q;
reg [4-1:0] M_AXI_AREGION_q;
reg [4-1:0] M_AXI_AQOS_q;
reg M_AXI_AVALID_q;
// Register MI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_AVALID_q <= 1'b0;
end else if ( M_AXI_AREADY_I ) begin
M_AXI_AVALID_q <= M_AXI_AVALID_I;
end
if ( M_AXI_AREADY_I ) begin
M_AXI_AADDR_q <= M_AXI_AADDR_I;
M_AXI_ALEN_q <= M_AXI_ALEN_I;
M_AXI_ASIZE_q <= M_AXI_ASIZE_I;
M_AXI_ABURST_q <= M_AXI_ABURST_I;
M_AXI_ALOCK_q <= M_AXI_ALOCK_I;
M_AXI_ACACHE_q <= M_AXI_ACACHE_I;
M_AXI_APROT_q <= M_AXI_APROT_I;
M_AXI_AREGION_q <= M_AXI_AREGION_I;
M_AXI_AQOS_q <= M_AXI_AQOS_I;
end
end
assign M_AXI_AADDR = M_AXI_AADDR_q;
assign M_AXI_ALEN = M_AXI_ALEN_q;
assign M_AXI_ASIZE = M_AXI_ASIZE_q;
assign M_AXI_ABURST = M_AXI_ABURST_q;
assign M_AXI_ALOCK = M_AXI_ALOCK_q;
assign M_AXI_ACACHE = M_AXI_ACACHE_q;
assign M_AXI_APROT = M_AXI_APROT_q;
assign M_AXI_AREGION = M_AXI_AREGION_q;
assign M_AXI_AQOS = M_AXI_AQOS_q;
assign M_AXI_AVALID = M_AXI_AVALID_q;
assign M_AXI_AREADY_I = ( M_AXI_AVALID_q & M_AXI_AREADY) | ~M_AXI_AVALID_q;
end else begin : NO_REGISTER
// Combinatorial MI-side Data.
assign M_AXI_AADDR = M_AXI_AADDR_I;
assign M_AXI_ALEN = M_AXI_ALEN_I;
assign M_AXI_ASIZE = M_AXI_ASIZE_I;
assign M_AXI_ABURST = M_AXI_ABURST_I;
assign M_AXI_ALOCK = M_AXI_ALOCK_I;
assign M_AXI_ACACHE = M_AXI_ACACHE_I;
assign M_AXI_APROT = M_AXI_APROT_I;
assign M_AXI_AREGION = M_AXI_AREGION_I;
assign M_AXI_AQOS = M_AXI_AQOS_I;
assign M_AXI_AVALID = M_AXI_AVALID_I;
assign M_AXI_AREADY_I = M_AXI_AREADY;
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : mapping
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This module maps the data received by the SircHandler (from PC) to the AluPuf.
// Issues appropriate trigger signals to start puf execution.
// Maintain state of the PUF operation - Idle or execute
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module mapping #(
parameter IN_WIDTH = 128,
parameter OUT_WIDTH = 16
)(
input wire clk,
input wire reset,
input wire trigger,
input wire [IN_WIDTH-1:0] dataIn,
output reg done,
output reg [OUT_WIDTH-1:0] dataOut,
output reg xorOut // Will use this later after output network is implemented.
);
// Input network also has to be implemented.
wire [15:0] response;
reg startPUF;
reg PUFreset;
reg [4:0] countWait;
integer ind;
reg [15:0] sum;
//FSM States
localparam IDLE = 0;
localparam COMPUTE = 1;
//State Register
reg mp_state;
reg [IN_WIDTH-1:0] buffer;
always @ (posedge clk) begin
if (reset) begin
done <= 0;
dataOut <= 0;
mp_state <= IDLE;
startPUF <= 0;
countWait <= 0;
PUFreset <=1;
end
else begin
case(mp_state)
IDLE: begin
done <= 0;
sum <= 0;
PUFreset <= 0;
countWait <=0;
startPUF <=0;
if(trigger == 1)
mp_state <= COMPUTE;
buffer <= dataIn;
end
COMPUTE: begin
startPUF <=1;
countWait <= countWait + 1;
if (countWait == 15) begin //wait for 10 clock cycles
startPUF<=0;
dataOut <= response;
done <= 1;
mp_state <= IDLE;
PUFreset <=1;
end
end
endcase
end
end
endmodule
|
// Generated by altmemphy 10.0 [Altera, IP Toolbench 1.3.0 Build 262]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int_phy (
pll_ref_clk,
global_reset_n,
soft_reset_n,
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
ctl_doing_rd,
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
oct_ctl_rs_value,
oct_ctl_rt_value,
dqs_offset_delay_ctrl,
dqs_delay_ctrl_import,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
reset_request_n,
ctl_clk,
ctl_reset_n,
ctl_wlat,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_reset_n,
dqs_delay_ctrl_export,
dll_reference_clk,
dbg_rd_data,
dbg_waitrequest,
aux_half_rate_clk,
aux_full_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqs_n);
input pll_ref_clk;
input global_reset_n;
input soft_reset_n;
input [7:0] ctl_dqs_burst;
input [7:0] ctl_wdata_valid;
input [127:0] ctl_wdata;
input [15:0] ctl_dm;
input [27:0] ctl_addr;
input [5:0] ctl_ba;
input [1:0] ctl_cas_n;
input [1:0] ctl_cke;
input [1:0] ctl_cs_n;
input [1:0] ctl_odt;
input [1:0] ctl_ras_n;
input [1:0] ctl_we_n;
input [1:0] ctl_rst_n;
input [0:0] ctl_mem_clk_disable;
input [7:0] ctl_doing_rd;
input ctl_cal_req;
input [3:0] ctl_cal_byte_lane_sel_n;
input [13:0] oct_ctl_rs_value;
input [13:0] oct_ctl_rt_value;
input [5:0] dqs_offset_delay_ctrl;
input [5:0] dqs_delay_ctrl_import;
input dbg_clk;
input dbg_reset_n;
input [12:0] dbg_addr;
input dbg_wr;
input dbg_rd;
input dbg_cs;
input [31:0] dbg_wr_data;
output reset_request_n;
output ctl_clk;
output ctl_reset_n;
output [4:0] ctl_wlat;
output [127:0] ctl_rdata;
output [1:0] ctl_rdata_valid;
output [4:0] ctl_rlat;
output ctl_cal_success;
output ctl_cal_fail;
output ctl_cal_warning;
output [13:0] mem_addr;
output [2:0] mem_ba;
output mem_cas_n;
output [0:0] mem_cke;
output [0:0] mem_cs_n;
output [3:0] mem_dm;
output [0:0] mem_odt;
output mem_ras_n;
output mem_we_n;
output mem_reset_n;
output [5:0] dqs_delay_ctrl_export;
output dll_reference_clk;
output [31:0] dbg_rd_data;
output dbg_waitrequest;
output aux_half_rate_clk;
output aux_full_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [31:0] mem_dq;
inout [3:0] mem_dqs;
inout [3:0] mem_dqs_n;
endmodule
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_buttons, input_switches, input_eth_rx, input_ps2, input_timer_stb, input_rs232_rx_stb, input_buttons_stb, input_switches_stb, input_eth_rx_stb, input_ps2_stb, input_timer_ack, input_rs232_rx_ack, input_buttons_ack, input_switches_ack, input_eth_rx_ack, input_ps2_ack, output_eth_tx, output_rs232_tx, output_leds, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
wire exception_140292293449776;
wire exception_140292292520776;
wire exception_140292291707392;
wire exception_140292291794560;
wire exception_140292291718680;
wire exception_140292290886400;
wire exception_140292291068416;
main_0 main_0_140292293449776(
.clk(clk),
.rst(rst),
.exception(exception_140292293449776),
.input_eth_in(input_eth_rx),
.input_eth_in_stb(input_eth_rx_stb),
.input_eth_in_ack(input_eth_rx_ack),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_eth_out(output_eth_tx),
.output_eth_out_stb(output_eth_tx_stb),
.output_eth_out_ack(output_eth_tx_ack));
main_1 main_1_140292292520776(
.clk(clk),
.rst(rst),
.exception(exception_140292292520776),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_140292291707392(
.clk(clk),
.rst(rst),
.exception(exception_140292291707392),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_140292291794560(
.clk(clk),
.rst(rst),
.exception(exception_140292291794560),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_4 main_4_140292291718680(
.clk(clk),
.rst(rst),
.exception(exception_140292291718680),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_140292290886400(
.clk(clk),
.rst(rst),
.exception(exception_140292290886400),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_6 main_6_140292291068416(
.clk(clk),
.rst(rst),
.exception(exception_140292291068416),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
assign exception = exception_140292293449776 || exception_140292292520776 || exception_140292291707392 || exception_140292291794560 || exception_140292291718680 || exception_140292290886400 || exception_140292291068416;
endmodule
|
//altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 2,
CFG_DATA_ID_WIDTH = 3, // number of buckets
CFG_LOCAL_ID_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_BUFFER_ADDR_WIDTH = 5,
CFG_MEM_IF_CS_WIDTH = 2,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_MAX_READ_CMD_NUM_WIDTH = 4, // expected in-flight read commands at a time
CFG_RDATA_RETURN_MODE = "PASSTHROUGH", // INORDER, PASSTHROUGH
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ERRCMD_FIFO_ADDR_WIDTH = 3,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 9,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 12,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_ERRCMD_FIFO_REG = 1 // set 1 to improve timing for errcmd_fifo
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration
cfg_type,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_burst_length,
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// command generator & TBP command load interface / cmd update interface
rdatap_free_id_valid,
rdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_read,
proc_size,
proc_localid,
// input interface data channel / buffer read interface
read_data_valid, // data sent to either dataid_manager, or input interface
read_data,
read_data_error,
read_data_localid,
// Arbiter issued reads interface
bg_do_read,
bg_to_chipsel,
bg_to_bank,
bg_to_row,
bg_to_column,
bg_dataid,
bg_localid,
bg_size,
bg_do_rmw_correct,
bg_do_rmw_partial,
// read data from memory interface
ecc_rdata,
ecc_rdatav,
ecc_sbe,
ecc_dbe,
ecc_code,
// ECC Error commands interface, to command generator
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
// ECC Error address interface, to ECC block
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// RMW fifo interface, to wdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_ECC_RDATA_COUNTER_REG = 0; // set to 1 to improve timing
localparam CFG_RMW_BIT_WIDTH = 1;
localparam CFG_RMW_PARTIAL_BIT_WIDTH = 1;
localparam CFG_PENDING_RD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_DATA_ID_WIDTH + CFG_RMW_BIT_WIDTH + CFG_RMW_PARTIAL_BIT_WIDTH;
localparam CFG_ERRCMD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_INT_SIZE_WIDTH + CFG_LOCAL_ID_WIDTH;
localparam CFG_INORDER_INFO_FIFO_WIDTH = CFG_INT_SIZE_WIDTH+CFG_LOCAL_ID_WIDTH;
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam CFG_RDATA_ERROR_WIDTH = 1;
localparam CFG_IN_ORDER_BUFFER_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RDATA_ERROR_WIDTH;
localparam CFG_MAX_READ_CMD_NUM = 2**CFG_MAX_READ_CMD_NUM_WIDTH;
localparam MIN_COL = 8;
localparam MIN_ROW = 12;
localparam MIN_BANK = 2;
localparam MIN_CS = 1;
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam CFG_IGNORE_NUM_BITS_COL = log2 (CFG_DWIDTH_RATIO);
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2 (CFG_LOCAL_ADDR_WIDTH);
integer j,k,m,n;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM-1:0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
output rdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_read;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
input [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
output read_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
output read_data_error;
output [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
input [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
input [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
input [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
// read data from memory interface
input [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
input ecc_rdatav;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
input errcmd_ready;
output errcmd_valid;
output [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
output [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
output [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// ECC Error address interface, to ECC block
output [CFG_LOCAL_ADDR_WIDTH-1:0] rdatap_rcvd_addr;
output rdatap_rcvd_cmd;
output rdatap_rcvd_corr_dropped;
// RMW fifo interface, to wdatap
output rmwfifo_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
output [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// configuration
wire [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
wire [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
reg rdatap_free_id_valid;
reg [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
reg read_data_valid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
reg read_data_error;
reg [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
wire [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
wire [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
wire [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH -1:0] int_bg_to_chipsel[CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_column [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_DATA_ID_WIDTH -1:0] int_bg_dataid;
reg [CFG_LOCAL_ID_WIDTH -1:0] int_bg_localid;
reg [CFG_INT_SIZE_WIDTH -1:0] int_bg_size;
// read data from memory interface
wire [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
wire ecc_rdatav;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// RMW fifo interface, to wdatap
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
reg rdatap_rcvd_cmd;
reg rdatap_rcvd_corr_dropped;
// -----------------------------
// signal declaration
// -----------------------------
wire[CFG_INT_SIZE_WIDTH-1:0] cfg_max_cmd_burstcount;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_row;
wire cmdload_valid;
reg [CFG_MAX_READ_CMD_NUM_WIDTH-1:0] cmd_counter;
reg cmd_counter_full;
wire cmd_counter_load;
wire free_id_get_ready;
wire free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0]free_id_dataid_vector;
wire allocated_put_ready;
wire allocated_put_valid;
wire int_free_id_valid;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_input;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_output;
wire pfifo_output_valid;
wire pfifo_input_ready;
wire rdata_burst_complete;
reg rdata_burst_complete_r;
reg rout_data_valid; // rout_data sent to dataid_manager
reg rout_cmd_valid; // rout_cmd sent to dataid_manager
reg rout_data_rmwfifo_valid; // rout_data sent to rmwfifo
reg rout_cmd_rmwfifo_valid; // rout_cmd sent to rmwfifo
wire rout_rmw_rmwpartial;
reg rout_data_error;
reg rout_sbecmd_valid;
reg rout_errnotify_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rout_data;
wire [CFG_DATA_ID_WIDTH-1:0] rout_data_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] rout_data_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] rout_data_burstcount;
wire [CFG_ECC_MULTIPLES- 1 : 0] rout_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rout_ecc_code;
reg pfifo_input_do_read;
reg pfifo_input_rmw;
reg pfifo_input_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_input_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_input_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_input_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_input_column;
reg [CFG_DATA_ID_WIDTH-1:0] pfifo_input_dataid;
reg [CFG_LOCAL_ID_WIDTH-1:0] pfifo_input_localid;
reg [CFG_INT_SIZE_WIDTH-1:0] pfifo_input_size;
reg mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM -1 : 0];
wire pfifo_rmw;
wire pfifo_rmw_partial;
wire [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel_r;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank_r;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned_r;
wire [CFG_DATA_ID_WIDTH-1:0] pfifo_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] pfifo_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] pfifo_size;
reg [CFG_LOCAL_ADDR_WIDTH-1:0] pfifo_addr;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_current_count;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdatavalid_count;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_burst_complete_count;
reg ecc_sbe_cmd_detected;
reg ecc_dbe_cmd_detected;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_LOCAL_ID_WIDTH-1:0] dataid_array_localid [CFG_DATAID_ARRAY_DEPTH-1:0];
wire inordr_id_data_complete;
reg inordr_id_data_complete_r;
wire inordr_id_valid;
wire inordr_id_list_valid;
wire inordr_read_data_valid;
reg inordr_read_data_valid_r;
wire [CFG_LOCAL_DATA_WIDTH-1:0] inordr_read_data;
wire inordr_read_data_error;
wire [CFG_DATA_ID_WIDTH-1:0] inordr_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] inordr_id_dataid_vector;
wire [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid;
reg [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid_r;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter_plus_1;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_next_data_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_id_expected_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_inordr_data_ready;
wire inordr_info_input_ready;
wire inordr_info_output_valid;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_input;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_output;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffwrite_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffwrite_data;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffread_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffread_data;
wire int_ecc_sbe;
wire int_ecc_dbe;
wire errcmd_fifo_in_cmddropped;
reg errcmd_fifo_in_cmddropped_r;
wire errcmd_fifo_in_ready;
wire errcmd_fifo_in_valid_wire;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_in_wire;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_out;
reg errcmd_fifo_in_valid;
reg [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_in;
// -----------------------------
// module definition
// -----------------------------
//
// READ DATA MAIN OUTPUT MUX
//
generate
begin : gen_rdata_output_mux
if (CFG_RDATA_RETURN_MODE == "PASSTHROUGH")
begin
always @ (*)
begin
read_data_valid = rout_data_valid;
read_data = rout_data;
read_data_error = rout_data_error;
read_data_localid = rout_data_localid;
rdatap_free_id_valid = ~cmd_counter_full;
rdatap_free_id_dataid = 0;
end
end
else
begin
always @ (*)
begin
read_data_valid = inordr_read_data_valid_r;
read_data = inordr_read_data;
read_data_error = inordr_read_data_error;
read_data_localid = inordr_id_localid_r;
rdatap_free_id_valid = ~cmd_counter_full & free_id_valid;
rdatap_free_id_dataid = free_id_dataid;
end
end
end
endgenerate
//
// RDATA_ROUTER
//
// mux to select correct burst gen output phase for read command
// assumes bg_do_read only asserted for 1 of the CFG_AFI_INTF_PHASE_NUM
genvar rdp_k;
generate
for (rdp_k = 0; rdp_k < CFG_AFI_INTF_PHASE_NUM; rdp_k = rdp_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_read [rdp_k] = bg_do_read [rdp_k];
int_bg_do_rmw_correct [rdp_k] = bg_do_rmw_correct [rdp_k];
int_bg_do_rmw_partial [rdp_k] = bg_do_rmw_partial [rdp_k];
int_bg_to_chipsel [rdp_k] = bg_to_chipsel [(((rdp_k+1)*CFG_MEM_IF_CS_WIDTH )-1):(rdp_k*CFG_MEM_IF_CS_WIDTH )];
int_bg_to_bank [rdp_k] = bg_to_bank [(((rdp_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(rdp_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [rdp_k] = bg_to_row [(((rdp_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(rdp_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_column [rdp_k] = bg_to_column [(((rdp_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(rdp_k*CFG_MEM_IF_COL_WIDTH)];
end
end
endgenerate
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
end
always @ (*)
begin
mux_pfifo_input_rmw [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_correct [0] : 0;
mux_pfifo_input_rmw_partial [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_partial [0] : 0;
mux_pfifo_input_chipsel [0] = (int_bg_do_read [0]) ? int_bg_to_chipsel [0] : 0;
mux_pfifo_input_bank [0] = (int_bg_do_read [0]) ? int_bg_to_bank [0] : 0;
mux_pfifo_input_row [0] = (int_bg_do_read [0]) ? int_bg_to_row [0] : 0;
mux_pfifo_input_column [0] = (int_bg_do_read [0]) ? int_bg_to_column [0] : 0;
end
genvar rdp_j;
generate
for (rdp_j = 1; rdp_j < CFG_AFI_INTF_PHASE_NUM; rdp_j = rdp_j + 1)
begin : gen_bg_afi_phase_mux
always @ (*)
begin
mux_pfifo_input_rmw [rdp_j] = mux_pfifo_input_rmw [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_correct [rdp_j] : 0);
mux_pfifo_input_rmw_partial [rdp_j] = mux_pfifo_input_rmw_partial [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_partial [rdp_j] : 0);
mux_pfifo_input_chipsel [rdp_j] = mux_pfifo_input_chipsel [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_chipsel [rdp_j] : 0);
mux_pfifo_input_bank [rdp_j] = mux_pfifo_input_bank [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_bank [rdp_j] : 0);
mux_pfifo_input_row [rdp_j] = mux_pfifo_input_row [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_row [rdp_j] : 0);
mux_pfifo_input_column [rdp_j] = mux_pfifo_input_column [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_column [rdp_j] : 0);
end
end
endgenerate
always @ (*)
begin
pfifo_input_do_read = |int_bg_do_read;
pfifo_input_rmw = mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_rmw_partial = mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_chipsel = mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_bank = mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_row = mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_column = mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_dataid = int_bg_dataid ;
pfifo_input_localid = int_bg_localid ;
pfifo_input_size = int_bg_size ;
end
// format for pfifo_input & pfifo_output must be same
assign pfifo_input = {pfifo_input_chipsel, pfifo_input_bank, pfifo_input_row, pfifo_input_column, pfifo_input_localid, pfifo_input_size, pfifo_input_rmw, pfifo_input_rmw_partial, pfifo_input_dataid};
assign {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column, pfifo_localid, pfifo_size, pfifo_rmw, pfifo_rmw_partial, pfifo_dataid} = pfifo_output;
// read data for this command has been fully received from memory
assign rdata_burst_complete = (pfifo_output_valid & (pfifo_size == ecc_rdata_current_count)) ? 1 : 0;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_PENDING_RD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_MAX_READ_CMD_NUM_WIDTH)
)
pending_rd_fifo
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rdata_burst_complete),
.get_valid (pfifo_output_valid),
.get_data (pfifo_output),
.put_ready (pfifo_input_ready), // no back-pressure allowed
.put_valid (pfifo_input_do_read),
.put_data (pfifo_input)
);
assign cmd_counter_load = ~proc_busy & proc_load & proc_read;
assign cmdload_valid = cmd_counter_load & proc_load_dataid;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cmd_counter <= 0;
cmd_counter_full <= 1'b0;
end
else
begin
if (cmd_counter_load & rdata_burst_complete)
begin
cmd_counter <= cmd_counter;
cmd_counter_full <= cmd_counter_full;
end
else if (cmd_counter_load)
begin
cmd_counter <= cmd_counter + 1;
if (cmd_counter == {{(CFG_MAX_READ_CMD_NUM_WIDTH - 1){1'b1}}, 1'b0}) // when cmd counter is counting up to all_ones
begin
cmd_counter_full <= 1'b1;
end
else
begin
cmd_counter_full <= 1'b0;
end
end
else if (rdata_burst_complete)
begin
cmd_counter <= cmd_counter - 1;
cmd_counter_full <= 1'b0;
end
end
end
assign rout_data = ecc_rdata;
assign rout_data_dataid = pfifo_dataid;
assign rout_data_localid = pfifo_localid;
assign rout_data_burstcount = ecc_rdata_current_count;
assign rout_rmw_rmwpartial = (pfifo_rmw | pfifo_rmw_partial);
assign rout_ecc_dbe = ecc_dbe;
assign rout_ecc_code = ecc_code;
always @ (*)
begin
//rout_data_valid = 0;
//rout_cmd_valid = 0;
rout_data_rmwfifo_valid = 0;
rout_cmd_rmwfifo_valid = 0;
rout_sbecmd_valid = 0;
rout_data_error = 0;
rout_errnotify_valid = 0;
if (~cfg_enable_ecc & ~cfg_enable_no_dm)
begin
rout_data_valid = ecc_rdatav;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
end
else
begin
rout_data_rmwfifo_valid = ecc_rdatav & rout_rmw_rmwpartial;
rout_data_valid = ecc_rdatav & ~rout_rmw_rmwpartial;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
rout_cmd_rmwfifo_valid = rout_data_rmwfifo_valid & rdata_burst_complete;
rout_data_error = int_ecc_dbe;
rout_errnotify_valid = ecc_rdatav & ( int_ecc_sbe | int_ecc_dbe );
if (cfg_enable_auto_corr)
begin
rout_sbecmd_valid = rout_cmd_valid & (ecc_sbe_cmd_detected | int_ecc_sbe);
end
end
end
// rmwfifo interface
assign rmwfifo_data_valid = rout_data_rmwfifo_valid;
assign rmwfifo_data = rout_data;
assign rmwfifo_ecc_dbe = rout_ecc_dbe;
assign rmwfifo_ecc_code = rout_ecc_code;
// ecc_sbe_cmd_detected
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else if (int_ecc_sbe)
begin
ecc_sbe_cmd_detected <= 1;
end
else if (int_ecc_dbe)
begin
ecc_dbe_cmd_detected <= 1;
end
end
end
assign int_ecc_sbe = ecc_rdatav & (|ecc_sbe);
assign int_ecc_dbe = ecc_rdatav & (|ecc_dbe);
//
// ECC_RDATA counter
//
assign ecc_rdata_current_count = (CFG_ECC_RDATA_COUNTER_REG) ? ecc_rdata_counter : ecc_rdatavalid_count;
assign ecc_rdatavalid_count = (ecc_rdatav) ? ecc_rdata_counter + 1 : ecc_rdata_counter;
assign ecc_rdata_burst_complete_count = pfifo_size;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_rdata_counter <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_rdata_counter <= ecc_rdatavalid_count - ecc_rdata_burst_complete_count;
end
else
begin
ecc_rdata_counter <= ecc_rdatavalid_count;
end
end
end
assign errcmd_fifo_in_valid_wire = rout_sbecmd_valid;
assign errcmd_fifo_in_wire = {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column_burst_aligned, cfg_max_cmd_burstcount, pfifo_localid};
assign {errcmd_chipsel, errcmd_bank, errcmd_row, errcmd_column, errcmd_size, errcmd_localid} = errcmd_fifo_out;
assign errcmd_fifo_in_cmddropped = ~errcmd_fifo_in_ready & errcmd_fifo_in_valid_wire;
assign cfg_max_cmd_burstcount = (cfg_burst_length / CFG_DWIDTH_RATIO);
// DDR3, pfifo_column_burst_aligned is burst length 8 aligned
// DDR2, pfifo_column is already burst aligned
assign pfifo_column_burst_aligned = (cfg_type == `MMR_TYPE_DDR3) ? {pfifo_column[(CFG_MEM_IF_COL_WIDTH-1):3],{3{1'b0}} } : pfifo_column;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pfifo_chipsel_r <= 0;
pfifo_bank_r <= 0;
pfifo_row_r <= 0;
pfifo_column_r <= 0;
pfifo_column_burst_aligned_r <= 0;
end
else
begin
pfifo_chipsel_r <= pfifo_chipsel ;
pfifo_bank_r <= pfifo_bank ;
pfifo_row_r <= pfifo_row ;
pfifo_column_r <= pfifo_column ;
pfifo_column_burst_aligned_r <= pfifo_column_burst_aligned;
end
end
generate
if (CFG_ERRCMD_FIFO_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
errcmd_fifo_in_valid <= 1'b0;
errcmd_fifo_in <= {CFG_ERRCMD_FIFO_WIDTH{1'b0}};
end else
begin
errcmd_fifo_in_valid <= errcmd_fifo_in_valid_wire;
errcmd_fifo_in <= errcmd_fifo_in_wire;
end
end
end else // (CFG_ERRCMD_FIFO_REG == 0)
begin
always @ (*)
begin
errcmd_fifo_in_valid = errcmd_fifo_in_valid_wire;
errcmd_fifo_in = errcmd_fifo_in_wire;
end
end
endgenerate
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_ERRCMD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH)
)
errcmd_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (errcmd_ready),
.get_valid (errcmd_valid),
.get_data (errcmd_fifo_out),
.put_ready (errcmd_fifo_in_ready),
.put_valid (errcmd_fifo_in_valid),
.put_data (errcmd_fifo_in)
);
//
// error address information for MMR's
//
// - rdatap_rcvd_addr, rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped
// - rdatap_rcvd_addr generation takes 1 cycle after an error, so need to register
// rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped to keep in sync, see SPR:362993
//
assign rdatap_rcvd_addr = pfifo_addr;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rdata_burst_complete_r <= 0;
errcmd_fifo_in_cmddropped_r <= 0;
rdatap_rcvd_cmd <= 0;
rdatap_rcvd_corr_dropped <= 0;
end
else
begin
rdata_burst_complete_r <= rdata_burst_complete;
errcmd_fifo_in_cmddropped_r <= errcmd_fifo_in_cmddropped;
rdatap_rcvd_cmd <= rdata_burst_complete;
rdatap_rcvd_corr_dropped <= errcmd_fifo_in_cmddropped;
end
end
// generate local address from chip, bank, row, column addresses
always @(*)
begin : addr_loop
pfifo_addr = 0;
// column
pfifo_addr[MIN_COL - CFG_IGNORE_NUM_BITS_COL - 1 : 0] = pfifo_column_burst_aligned_r[MIN_COL - 1 : CFG_IGNORE_NUM_BITS_COL];
for (n=MIN_COL; n<MAX_COL; n=n+1'b1) begin
if(n < cfg_col_addr_width) begin // bit of col_addr can be configured in CSR using cfg_col_addr_width
pfifo_addr[n - CFG_IGNORE_NUM_BITS_COL] = pfifo_column_burst_aligned_r[n];
end
end
// row
for (j=0; j<MIN_ROW; j=j+1'b1) begin //The purpose of using this for-loop is to get rid of "if(j < cfg_row_addr_width) begin" which causes multiplexers
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
for (j=MIN_ROW; j<MAX_ROW; j=j+1'b1) begin
if(j < cfg_row_addr_width) begin // bit of row_addr can be configured in CSR using cfg_row_addr_width
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
end
// bank
for (k=0; k<MIN_BANK; k=k+1'b1) begin //The purpose of using this for-loop is to get rid of "if(k < cfg_bank_addr_width) begin" which causes multiplexers
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
for (k=MIN_BANK; k<MAX_BANK; k=k+1'b1) begin
if(k < cfg_bank_addr_width) begin // bit of bank_addr can be configured in CSR using cfg_bank_addr_width
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
end
// cs
m = 0;
if (cfg_cs_addr_width > 1'b0) begin //if cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
for (m=0; m<MIN_CS; m=m+1'b1) begin //The purpose of using this for-loop is to get rid of "if(m < cfg_cs_addr_width) begin" which causes multiplexers
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1) begin
if(m < cfg_cs_addr_width) begin // bit of cs_addr can be configured in CSR using cfg_cs_addr_width
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
end
end
end
// pre-calculate pfifo_addr chipsel, bank, row, col bit select offsets
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cfg_addr_bitsel_chipsel <= 0;
cfg_addr_bitsel_bank <= 0;
cfg_addr_bitsel_row <= 0;
end
else
begin
//row
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_row <= cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_row <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_row <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
// bank
if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_bank <= cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_bank <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
//chipsel
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
end
end
//
// Everything below is for
// CFG_RDATA_RETURN_MODE == INORDER support
//
generate
begin : gen_rdata_return_inorder
if (CFG_RDATA_RETURN_MODE == "INORDER")
begin
//
// DATAID MANAGEMENT
//
genvar i;
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array
assign dataid_array_valid[i] = |(dataid_array_burstcount[i]);
// dataid_array
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
dataid_array_localid [i] <= 0;
end
else
begin
// update command
if (cmdload_valid & free_id_dataid_vector[i])
begin
dataid_array_burstcount[i] <= proc_size;
end
// writing data to buffer
if (rout_data_valid & (rout_data_dataid == i))
begin
dataid_array_data_ready[i] <= 1'b1;
dataid_array_localid[i] <= rout_data_localid;
end
// completed reading data from buffer
if (inordr_id_data_complete & inordr_id_dataid_vector[i])
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
end
end
end
// dataid_array output decode mux
always @ (*)
begin
if (inordr_id_valid & inordr_id_dataid_vector[i])
begin
mux_inordr_data_ready[i] = dataid_array_data_ready[i];
end
else
begin
mux_inordr_data_ready[i] = 1'b0;
end
end
end
assign inordr_read_data_valid = |mux_inordr_data_ready;
//
// FREE & ALLOCATED DATAID LIST
//
assign free_id_get_ready = cmdload_valid;
assign allocated_put_valid = free_id_get_ready & free_id_valid;
// list & fifo ready & valid assertion/de-assertion behavior may differ based on implementation, SPR:358527
assign free_id_valid = int_free_id_valid & inordr_info_input_ready;
assign inordr_id_valid = inordr_id_list_valid & inordr_info_output_valid;
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (free_id_get_ready),
.list_get_entry_valid (int_free_id_valid),
.list_get_entry_id (free_id_dataid),
.list_get_entry_id_vector (free_id_dataid_vector),
// ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (),
.list_put_entry_valid (inordr_id_data_complete),
.list_put_entry_id (inordr_id_dataid)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (inordr_id_data_complete),
.list_get_entry_valid (inordr_id_list_valid),
.list_get_entry_id (inordr_id_dataid),
.list_get_entry_id_vector (inordr_id_dataid_vector),
// allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (allocated_put_ready),
.list_put_entry_valid (allocated_put_valid),
.list_put_entry_id (free_id_dataid)
);
// format for inordr_info_input & inordr_info_output must be same
assign inordr_info_input = {proc_localid,proc_size};
assign {inordr_id_localid,inordr_id_expected_burstcount} = inordr_info_output;
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_INORDER_INFO_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_DATA_ID_WIDTH)
)
inordr_info_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (inordr_id_data_complete),
.get_valid (inordr_info_output_valid),
.get_data (inordr_info_output),
.put_ready (inordr_info_input_ready),
.put_valid (allocated_put_valid),
.put_data (inordr_info_input)
);
//
// IN-ORDER READ MANAGER
//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 0;
inordr_read_data_valid_r <= 0;
inordr_id_data_complete_r <= 0;
inordr_id_localid_r <= 0;
end
else
begin
if (inordr_id_data_complete)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 1;
end
else
begin
inordr_data_counter <= inordr_next_data_counter;
inordr_data_counter_plus_1 <= inordr_next_data_counter + 1;
end
inordr_id_localid_r <= inordr_id_localid;
// original signal used to read from buffer
// _r version used to pop the fifos
inordr_read_data_valid_r <= inordr_read_data_valid;
inordr_id_data_complete_r <= inordr_id_data_complete;
end
end
assign inordr_next_data_counter = (inordr_read_data_valid) ? (inordr_data_counter_plus_1) : inordr_data_counter;
assign inordr_id_data_complete = inordr_read_data_valid & (inordr_data_counter_plus_1 == inordr_id_expected_burstcount);
//
// BUFFER
//
assign buffwrite_offset = ecc_rdata_counter;
assign buffwrite_address = {rout_data_dataid,buffwrite_offset};
assign buffwrite_data = {rout_data_error,rout_data};
assign buffread_offset = inordr_data_counter;
assign buffread_address = {inordr_id_dataid,buffread_offset};
assign {inordr_read_data_error,inordr_read_data} = buffread_data;
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_IN_ORDER_BUFFER_DATA_WIDTH)
)
in_order_buffer_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (rout_data_valid),
.write_address (buffwrite_address),
.write_data (buffwrite_data),
// read interface
.read_valid (inordr_read_data_valid),
.read_address (buffread_address),
.read_data (buffread_data)
);
end
end
endgenerate
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
//
// assert
//
// - rdatap_free_id_valid XOR rdatap_allocated_put_ready must always be 1
// - CFG_BUFFER_ADDR_WIDTH must be >= CFG_INT_SIZE_WIDTH. must have enough location to store 1 dram command worth of data
// - put_ready goes low
// - ecc_rdatav is high, but pfifo_output_valid is low
// - buffer size must be dataid x max size per command
// - is rdata_burst_complete allowed to be high every cycle?
// - CFG_BUFFER_ADDR_WIDTH > CFG_DATA_ID_WIDTH
// - if cfg_enable_ecc is low, sbe, dbe, rdata error must all be low
// - if cfg_enable_auto_corr is low, rmw & rmw_partial must be low, errcmd_valid must never be high
// - cmd_counter_full & cmdload_valid
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ns/1ps
module bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCNFG2RD_EN = 2,
parameter nCNFG2WR = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
wtr_inhbt_config_r, was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, io_config_valid_r, io_config_strobe,
io_config, inhbt_wr_config, inhbt_rd_r, inhbt_rd_config,
inhbt_act_faw_r, idle_cnt, hi_priority, dq_busy_data,
dfi_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input dfi_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input inhbt_rd_config; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd_r; // To bank_state0 of bank_state.v
input inhbt_wr_config; // To bank_state0 of bank_state.v
input [RANK_WIDTH:0] io_config; // To bank_state0 of bank_state.v
input io_config_strobe; // To bank_state0 of bank_state.v
input io_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] wtr_inhbt_config_r; // To bank_state0 of bank_state.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.rtc (rtc),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.dfi_rddata_valid (dfi_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.io_config_strobe (io_config_strobe),
.io_config_valid_r (io_config_valid_r),
.io_config (io_config[RANK_WIDTH:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
module busy_gpr_table
(/*AUTOARG*/
// Outputs
decode_dest_reg1_busy_bits, decode_source_reg1_busy_bits,
decode_source_reg4_busy_bits, decode_source_reg2_busy_bits,
decode_source_reg3_busy_bits, decode_dest_reg2_busy_bits,
// Inputs
clk, rst, alu_valid, lsu_valid, f_decode_source_reg2,
f_decode_source_reg3, f_decode_dest_reg2, f_decode_dest_reg1,
f_decode_source_reg1, f_decode_source_reg4, alu_dest_reg1,
lsu_dest_reg, lsu_dest_reg_size, alu_dest_reg1_size, alu_dest_reg2,
alu_dest_reg2_size, f_vgpr_alu_dest_reg_addr, f_vgpr_lsu_dest_reg_addr,
f_vgpr_lsu_dest_reg_valid, f_vgpr_alu_dest_reg_valid,
f_sgpr_valu_dest_addr, f_sgpr_alu_dest_reg_addr,
f_sgpr_lsu_dest_reg_addr, f_sgpr_lsu_dest_reg_valid,
f_sgpr_alu_dest_reg_valid, f_sgpr_valu_dest_reg_valid
);
/**
* Busy bit is set when dst1 and dst2 are issued, cleared when
* register retires
***/
input clk,rst;
input alu_valid, lsu_valid;
input [`OPERAND_LENGTH_2WORD-1:0] f_decode_source_reg2, f_decode_source_reg3, f_decode_dest_reg2;
input [`OPERAND_LENGTH_4WORD-1:0] f_decode_dest_reg1, f_decode_source_reg1, f_decode_source_reg4;
input [11:0] alu_dest_reg1, lsu_dest_reg;
input [1:0] lsu_dest_reg_size;
input alu_dest_reg1_size;
wire [3:0] lsu_dest_reg_sgpr_valid, lsu_dest_reg_vgpr_valid;
wire [1:0] alu_dest_reg1_sgpr_valid, alu_dest_reg1_vgpr_valid;
input [11:0] alu_dest_reg2;
input alu_dest_reg2_size;
wire [1:0] alu_dest_reg2_sgpr_valid;
input [`VGPR_ADDR_LENGTH-1:0] f_vgpr_alu_dest_reg_addr, f_vgpr_lsu_dest_reg_addr;
input [3:0] f_vgpr_lsu_dest_reg_valid;
input f_vgpr_alu_dest_reg_valid;
input [`SGPR_ADDR_LENGTH-1:0] f_sgpr_valu_dest_addr, f_sgpr_alu_dest_reg_addr,
f_sgpr_lsu_dest_reg_addr;
input [3:0] f_sgpr_lsu_dest_reg_valid;
input [1:0] f_sgpr_alu_dest_reg_valid;
input f_sgpr_valu_dest_reg_valid;
output [3:0] decode_dest_reg1_busy_bits, decode_source_reg1_busy_bits, decode_source_reg4_busy_bits;
output [1:0] decode_source_reg2_busy_bits, decode_source_reg3_busy_bits, decode_dest_reg2_busy_bits;
wire [3:0] decode_dest_reg1_mask, decode_source_reg1_mask, decode_source_reg4_mask;
wire [1:0] decode_source_reg2_mask, decode_source_reg3_mask, decode_dest_reg2_mask;
wire [3:0] decode_dest_reg1_busy_bits_vgpr, decode_source_reg1_busy_bits_vgpr, decode_dest_reg1_busy_bits_sgpr, decode_source_reg1_busy_bits_sgpr, decode_source_reg4_busy_bits_sgpr;
wire [1:0] decode_source_reg2_busy_bits_vgpr, decode_source_reg3_busy_bits_vgpr, decode_source_reg2_busy_bits_sgpr, decode_source_reg3_busy_bits_sgpr, decode_dest_reg2_busy_bits_sgpr;
wire [`NUMBER_SGPR-1:0] sgpr_busy_bits, next_sgpr_busy_bits;
wire [`NUMBER_SGPR-1:0] alu_dest_reg1_sgpr_set_decoded, alu_dest_reg2_sgpr_set_decoded, lsu_dest_reg_sgpr_set_decoded;
wire [`NUMBER_SGPR-1:0] sgpr_alu_dest_clear_decoded, sgpr_lsu_dest_clear_decoded, sgpr_valu_dest_clear_decoded;
wire [`NUMBER_VGPR-1:0] vgpr_busy_bits, next_vgpr_busy_bits;
wire [`NUMBER_VGPR-1:0] alu_dest_reg1_vgpr_set_decoded, lsu_dest_reg_vgpr_set_decoded;
wire [`NUMBER_VGPR-1:0] vgpr_alu_dest_clear_decoded, vgpr_lsu_dest_clear_decoded;
// Decoder for the dsts value to set the busy table
// 1024 - dest1 alu - 2, dest1 lsu - 4
// 512 - dest1 alu - 1(2wide), dest1 lsu - 1(4wide), dest2 alu 1(2wide)
vgpr_busy_table_decoder #(2) alu_dst1_vgpr_set_decoder
(
.vgpr_addr(alu_dest_reg1[`VGPR_ADDR_LENGTH-1:0]),
.vgpr_valid(alu_dest_reg1_vgpr_valid),
.output_decoded(alu_dest_reg1_vgpr_set_decoded)
);
vgpr_busy_table_decoder #(4) lsu_dst1_set_decoder
(
.vgpr_addr(lsu_dest_reg[`VGPR_ADDR_LENGTH-1:0]),
.vgpr_valid(lsu_dest_reg_vgpr_valid),
.output_decoded(lsu_dest_reg_vgpr_set_decoded)
);
sgpr_busy_table_decoder #(4) lsu_dst1_sgpr_set_decoder
(
.sgpr_addr(lsu_dest_reg[`SGPR_ADDR_LENGTH-1:0]),
.sgpr_valid(lsu_dest_reg_sgpr_valid),
.output_decoded(lsu_dest_reg_sgpr_set_decoded)
);
sgpr_busy_table_decoder #(2) alu_dst1_sgpr_set_decoder
(
.sgpr_addr(alu_dest_reg1[`SGPR_ADDR_LENGTH-1:0]),
.sgpr_valid(alu_dest_reg1_sgpr_valid),
.output_decoded(alu_dest_reg1_sgpr_set_decoded)
);
sgpr_busy_table_decoder #(2) alu_dst2_sgpr_set_decoder
(
.sgpr_addr(alu_dest_reg2[`SGPR_ADDR_LENGTH-1:0]),
.sgpr_valid(alu_dest_reg2_sgpr_valid),
.output_decoded(alu_dest_reg2_sgpr_set_decoded)
);
// Decoders for the retired values to clear the busy table
// 1024 - vgpr_alu - 2, vgpr_lsu - 4
// 512 -sgpr_alu - 1(2 wide), sgpr_lsu 1(4wide)
vgpr_busy_table_decoder #(2) vgpr_alu_dst_clear_decoder
(
.vgpr_addr(f_vgpr_alu_dest_reg_addr),
.vgpr_valid({1'b0,f_vgpr_alu_dest_reg_valid}),
.output_decoded(vgpr_alu_dest_clear_decoded)
);
vgpr_busy_table_decoder #(4) vgpr_lsu_dst_clear_decoder
(
.vgpr_addr(f_vgpr_lsu_dest_reg_addr),
.vgpr_valid(f_vgpr_lsu_dest_reg_valid),
.output_decoded(vgpr_lsu_dest_clear_decoded)
);
sgpr_busy_table_decoder #(2) sgpr_alu_dst_clear_decoder
(
.sgpr_addr(f_sgpr_alu_dest_reg_addr),
.sgpr_valid(f_sgpr_alu_dest_reg_valid),
.output_decoded(sgpr_alu_dest_clear_decoded)
);
sgpr_busy_table_decoder #(2) sgpr_valu_dst_clear_decoder
(
.sgpr_addr(f_sgpr_valu_dest_addr),
.sgpr_valid({f_sgpr_valu_dest_reg_valid, f_sgpr_valu_dest_reg_valid}),
.output_decoded(sgpr_valu_dest_clear_decoded)
);
sgpr_busy_table_decoder #(4) sgpr_lsu_dst_clear_decoder
(
.sgpr_addr(f_sgpr_lsu_dest_reg_addr),
.sgpr_valid(f_sgpr_lsu_dest_reg_valid),
.output_decoded(sgpr_lsu_dest_clear_decoded)
);
// Muxes for the read ports
// 1024- 4 to dst1 and src1 2 to src2 and src3
// 1(4wide) dst1 src1 and src4, 1(2wide) dest2, src2 and src3
vgpr_busy_table_mux #(4) decode_dest_reg1_rd_port_vgpr
(
.in(vgpr_busy_bits),
.select(f_decode_dest_reg1[`VGPR_ADDR_LENGTH-1:0]),
.out(decode_dest_reg1_busy_bits_vgpr)
);
vgpr_busy_table_mux #(4) decode_source_reg1_rd_port_vgpr
(
.in(vgpr_busy_bits),
.select(f_decode_source_reg1[`VGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg1_busy_bits_vgpr)
);
vgpr_busy_table_mux #(2) decode_source_reg2_rd_port_vgpr
(
.in(vgpr_busy_bits),
.select(f_decode_source_reg2[`VGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg2_busy_bits_vgpr)
);
vgpr_busy_table_mux #(2) decode_source_reg3_rd_port_vgpr
(
.in(vgpr_busy_bits),
.select(f_decode_source_reg3[`VGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg3_busy_bits_vgpr)
);
sgpr_busy_table_mux #(4) decode_dest_reg1_rd_port_sgpr
(
.in(sgpr_busy_bits),
.select(f_decode_dest_reg1[`SGPR_ADDR_LENGTH-1:0]),
.out(decode_dest_reg1_busy_bits_sgpr)
);
sgpr_busy_table_mux #(2) decode_dest_reg2_rd_port_sgpr
(
.in(sgpr_busy_bits),
.select(f_decode_dest_reg2[`SGPR_ADDR_LENGTH-1:0]),
.out(decode_dest_reg2_busy_bits_sgpr)
);
sgpr_busy_table_mux #(4) decode_source_reg1_rd_port_sgpr
(
.in(sgpr_busy_bits),
.select(f_decode_source_reg1[`SGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg1_busy_bits_sgpr)
);
sgpr_busy_table_mux #(2) decode_source_reg2_rd_port_sgpr
(
.in(sgpr_busy_bits),
.select(f_decode_source_reg2[`SGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg2_busy_bits_sgpr)
);
sgpr_busy_table_mux #(2) decode_source_reg3_rd_port_sgpr
(
.in(sgpr_busy_bits),
.select(f_decode_source_reg3[`SGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg3_busy_bits_sgpr)
);
sgpr_busy_table_mux #(4) decode_source_reg4_rd_port_sgpr
(
.in(sgpr_busy_bits),
.select(f_decode_source_reg4[`SGPR_ADDR_LENGTH-1:0]),
.out(decode_source_reg4_busy_bits_sgpr)
);
// 1024 reg for vgpr
dff vgpr_busy_bit_reg[`NUMBER_VGPR-1:0]
(
.q(vgpr_busy_bits),
.d(next_vgpr_busy_bits),
.clk(clk),
.rst(rst)
);
// 512 reg for sgpr
dff sgpr_busy_bit_reg[`NUMBER_SGPR-1:0]
(
.q(sgpr_busy_bits),
.d(next_sgpr_busy_bits),
.clk(clk),
.rst(rst)
);
// Generate next inputs for the busy bits tables
assign next_vgpr_busy_bits
= vgpr_busy_bits &
(~vgpr_alu_dest_clear_decoded & ~vgpr_lsu_dest_clear_decoded) |
(alu_dest_reg1_vgpr_set_decoded | lsu_dest_reg_vgpr_set_decoded);
assign next_sgpr_busy_bits
= sgpr_busy_bits &
(~sgpr_valu_dest_clear_decoded & ~sgpr_alu_dest_clear_decoded & ~sgpr_lsu_dest_clear_decoded) |
( lsu_dest_reg_sgpr_set_decoded |
alu_dest_reg1_sgpr_set_decoded | alu_dest_reg2_sgpr_set_decoded );
// Generate the valid bits for write ports
assign alu_dest_reg1_vgpr_valid
= alu_valid && (alu_dest_reg1[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)?
( (alu_dest_reg1_size)? 2'b11 : 2'b01 ) :
2'b00;
assign lsu_dest_reg_vgpr_valid
= lsu_valid && (lsu_dest_reg[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)?
( (lsu_dest_reg_size[1])? 4'b1111 :
(lsu_dest_reg_size[0])? 4'b0011 : 4'b0001 ) :
4'b0000;
assign alu_dest_reg1_sgpr_valid
= alu_valid && (alu_dest_reg1[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)?
( (alu_dest_reg1_size)? 2'b11 : 2'b01 ) :
2'b00;
assign alu_dest_reg2_sgpr_valid
= alu_valid && (alu_dest_reg2[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)?
( (alu_dest_reg2_size)? 2'b11 : 2'b01 ) :
2'b00;
assign lsu_dest_reg_sgpr_valid
= lsu_valid && (lsu_dest_reg[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)?
( (lsu_dest_reg_size[1])? 4'b1111 :
(lsu_dest_reg_size[0])? 4'b0011 : 4'b0001 ) :
4'b0000;
// Select only valid values for read ports
assign decode_dest_reg1_mask = (f_decode_dest_reg1[`ISSUE_OP_4WORD_BIT])? 4'b1111 :
(f_decode_dest_reg1[`ISSUE_OP_2WORD_BIT])? 4'b0011 :
4'b0001;
assign decode_source_reg1_mask = (f_decode_source_reg1[`ISSUE_OP_4WORD_BIT])? 4'b1111 :
(f_decode_source_reg1[`ISSUE_OP_2WORD_BIT])? 4'b0011 :
4'b0001;
assign decode_source_reg4_mask = (f_decode_source_reg4[`ISSUE_OP_4WORD_BIT])? 4'b1111 :
(f_decode_source_reg4[`ISSUE_OP_2WORD_BIT])? 4'b0011 :
4'b0001;
assign decode_source_reg2_mask = (f_decode_source_reg2[`ISSUE_OP_2WORD_BIT])? 2'b11 :
2'b01;
assign decode_source_reg3_mask = (f_decode_source_reg3[`ISSUE_OP_2WORD_BIT])? 2'b11 :
2'b01;
assign decode_dest_reg2_mask = (f_decode_dest_reg2[`ISSUE_OP_2WORD_BIT])? 2'b11 :
2'b01;
assign decode_dest_reg1_busy_bits
= (f_decode_dest_reg1[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)? decode_dest_reg1_busy_bits_vgpr & decode_dest_reg1_mask :
(f_decode_dest_reg1[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)? decode_dest_reg1_busy_bits_sgpr & decode_dest_reg1_mask :
4'b0000;
assign decode_dest_reg2_busy_bits
= (f_decode_dest_reg2[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)? decode_dest_reg2_busy_bits_sgpr & decode_dest_reg2_mask:
2'b00;
assign decode_source_reg1_busy_bits
= (f_decode_source_reg1[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)? decode_source_reg1_busy_bits_vgpr & decode_source_reg1_mask :
(f_decode_source_reg1[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)? decode_source_reg1_busy_bits_sgpr & decode_source_reg1_mask:
4'b0000;
assign decode_source_reg2_busy_bits
= (f_decode_source_reg2[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)? decode_source_reg2_busy_bits_vgpr & decode_source_reg2_mask:
(f_decode_source_reg2[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)? decode_source_reg2_busy_bits_sgpr & decode_source_reg2_mask:
2'b00;
assign decode_source_reg3_busy_bits
= (f_decode_source_reg3[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)? decode_source_reg3_busy_bits_vgpr & decode_source_reg3_mask:
(f_decode_source_reg3[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)? decode_source_reg3_busy_bits_sgpr & decode_source_reg3_mask:
2'b00;
assign decode_source_reg4_busy_bits
= (f_decode_source_reg4[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)? decode_source_reg4_busy_bits_sgpr & decode_source_reg4_mask:
4'b0000;
endmodule
|
module jedi_lut (
output reg [15:0] dout,
input [13:0] address
);
// Todo: dout could be only 12 bits ?
always @(address)
begin
case (address)
14'd0 : dout <= 16'd2;
14'd1 : dout <= 16'd6;
14'd2 : dout <= 16'd10;
14'd3 : dout <= 16'd14;
14'd4 : dout <= 16'd18;
14'd5 : dout <= 16'd22;
14'd6 : dout <= 16'd26;
14'd7 : dout <= 16'd30;
14'd8 : dout <= -16'd2;
14'd9 : dout <= -16'd6;
14'd10 : dout <= -16'd10;
14'd11 : dout <= -16'd14;
14'd12 : dout <= -16'd18;
14'd13 : dout <= -16'd22;
14'd14 : dout <= -16'd26;
14'd15 : dout <= -16'd30;
14'd16 : dout <= 16'd2;
14'd17 : dout <= 16'd6;
14'd18 : dout <= 16'd10;
14'd19 : dout <= 16'd14;
14'd20 : dout <= 16'd19;
14'd21 : dout <= 16'd23;
14'd22 : dout <= 16'd27;
14'd23 : dout <= 16'd31;
14'd24 : dout <= -16'd2;
14'd25 : dout <= -16'd6;
14'd26 : dout <= -16'd10;
14'd27 : dout <= -16'd14;
14'd28 : dout <= -16'd19;
14'd29 : dout <= -16'd23;
14'd30 : dout <= -16'd27;
14'd31 : dout <= -16'd31;
14'd32 : dout <= 16'd2;
14'd33 : dout <= 16'd7;
14'd34 : dout <= 16'd11;
14'd35 : dout <= 16'd16;
14'd36 : dout <= 16'd21;
14'd37 : dout <= 16'd26;
14'd38 : dout <= 16'd30;
14'd39 : dout <= 16'd35;
14'd40 : dout <= -16'd2;
14'd41 : dout <= -16'd7;
14'd42 : dout <= -16'd11;
14'd43 : dout <= -16'd16;
14'd44 : dout <= -16'd21;
14'd45 : dout <= -16'd26;
14'd46 : dout <= -16'd30;
14'd47 : dout <= -16'd35;
14'd48 : dout <= 16'd2;
14'd49 : dout <= 16'd7;
14'd50 : dout <= 16'd13;
14'd51 : dout <= 16'd18;
14'd52 : dout <= 16'd23;
14'd53 : dout <= 16'd28;
14'd54 : dout <= 16'd34;
14'd55 : dout <= 16'd39;
14'd56 : dout <= -16'd2;
14'd57 : dout <= -16'd7;
14'd58 : dout <= -16'd13;
14'd59 : dout <= -16'd18;
14'd60 : dout <= -16'd23;
14'd61 : dout <= -16'd28;
14'd62 : dout <= -16'd34;
14'd63 : dout <= -16'd39;
14'd64 : dout <= 16'd2;
14'd65 : dout <= 16'd8;
14'd66 : dout <= 16'd14;
14'd67 : dout <= 16'd20;
14'd68 : dout <= 16'd25;
14'd69 : dout <= 16'd31;
14'd70 : dout <= 16'd37;
14'd71 : dout <= 16'd43;
14'd72 : dout <= -16'd2;
14'd73 : dout <= -16'd8;
14'd74 : dout <= -16'd14;
14'd75 : dout <= -16'd20;
14'd76 : dout <= -16'd25;
14'd77 : dout <= -16'd31;
14'd78 : dout <= -16'd37;
14'd79 : dout <= -16'd43;
14'd80 : dout <= 16'd3;
14'd81 : dout <= 16'd9;
14'd82 : dout <= 16'd15;
14'd83 : dout <= 16'd21;
14'd84 : dout <= 16'd28;
14'd85 : dout <= 16'd34;
14'd86 : dout <= 16'd40;
14'd87 : dout <= 16'd46;
14'd88 : dout <= -16'd3;
14'd89 : dout <= -16'd9;
14'd90 : dout <= -16'd15;
14'd91 : dout <= -16'd21;
14'd92 : dout <= -16'd28;
14'd93 : dout <= -16'd34;
14'd94 : dout <= -16'd40;
14'd95 : dout <= -16'd46;
14'd96 : dout <= 16'd3;
14'd97 : dout <= 16'd10;
14'd98 : dout <= 16'd17;
14'd99 : dout <= 16'd24;
14'd100 : dout <= 16'd31;
14'd101 : dout <= 16'd38;
14'd102 : dout <= 16'd45;
14'd103 : dout <= 16'd52;
14'd104 : dout <= -16'd3;
14'd105 : dout <= -16'd10;
14'd106 : dout <= -16'd17;
14'd107 : dout <= -16'd24;
14'd108 : dout <= -16'd31;
14'd109 : dout <= -16'd38;
14'd110 : dout <= -16'd45;
14'd111 : dout <= -16'd52;
14'd112 : dout <= 16'd3;
14'd113 : dout <= 16'd11;
14'd114 : dout <= 16'd19;
14'd115 : dout <= 16'd27;
14'd116 : dout <= 16'd34;
14'd117 : dout <= 16'd42;
14'd118 : dout <= 16'd50;
14'd119 : dout <= 16'd58;
14'd120 : dout <= -16'd3;
14'd121 : dout <= -16'd11;
14'd122 : dout <= -16'd19;
14'd123 : dout <= -16'd27;
14'd124 : dout <= -16'd34;
14'd125 : dout <= -16'd42;
14'd126 : dout <= -16'd50;
14'd127 : dout <= -16'd58;
14'd128 : dout <= 16'd4;
14'd129 : dout <= 16'd12;
14'd130 : dout <= 16'd21;
14'd131 : dout <= 16'd29;
14'd132 : dout <= 16'd38;
14'd133 : dout <= 16'd46;
14'd134 : dout <= 16'd55;
14'd135 : dout <= 16'd63;
14'd136 : dout <= -16'd4;
14'd137 : dout <= -16'd12;
14'd138 : dout <= -16'd21;
14'd139 : dout <= -16'd29;
14'd140 : dout <= -16'd38;
14'd141 : dout <= -16'd46;
14'd142 : dout <= -16'd55;
14'd143 : dout <= -16'd63;
14'd144 : dout <= 16'd4;
14'd145 : dout <= 16'd13;
14'd146 : dout <= 16'd23;
14'd147 : dout <= 16'd32;
14'd148 : dout <= 16'd41;
14'd149 : dout <= 16'd50;
14'd150 : dout <= 16'd60;
14'd151 : dout <= 16'd69;
14'd152 : dout <= -16'd4;
14'd153 : dout <= -16'd13;
14'd154 : dout <= -16'd23;
14'd155 : dout <= -16'd32;
14'd156 : dout <= -16'd41;
14'd157 : dout <= -16'd50;
14'd158 : dout <= -16'd60;
14'd159 : dout <= -16'd69;
14'd160 : dout <= 16'd5;
14'd161 : dout <= 16'd15;
14'd162 : dout <= 16'd25;
14'd163 : dout <= 16'd35;
14'd164 : dout <= 16'd46;
14'd165 : dout <= 16'd56;
14'd166 : dout <= 16'd66;
14'd167 : dout <= 16'd76;
14'd168 : dout <= -16'd5;
14'd169 : dout <= -16'd15;
14'd170 : dout <= -16'd25;
14'd171 : dout <= -16'd35;
14'd172 : dout <= -16'd46;
14'd173 : dout <= -16'd56;
14'd174 : dout <= -16'd66;
14'd175 : dout <= -16'd76;
14'd176 : dout <= 16'd5;
14'd177 : dout <= 16'd16;
14'd178 : dout <= 16'd28;
14'd179 : dout <= 16'd39;
14'd180 : dout <= 16'd50;
14'd181 : dout <= 16'd61;
14'd182 : dout <= 16'd73;
14'd183 : dout <= 16'd84;
14'd184 : dout <= -16'd5;
14'd185 : dout <= -16'd16;
14'd186 : dout <= -16'd28;
14'd187 : dout <= -16'd39;
14'd188 : dout <= -16'd50;
14'd189 : dout <= -16'd61;
14'd190 : dout <= -16'd73;
14'd191 : dout <= -16'd84;
14'd192 : dout <= 16'd6;
14'd193 : dout <= 16'd18;
14'd194 : dout <= 16'd31;
14'd195 : dout <= 16'd43;
14'd196 : dout <= 16'd56;
14'd197 : dout <= 16'd68;
14'd198 : dout <= 16'd81;
14'd199 : dout <= 16'd93;
14'd200 : dout <= -16'd6;
14'd201 : dout <= -16'd18;
14'd202 : dout <= -16'd31;
14'd203 : dout <= -16'd43;
14'd204 : dout <= -16'd56;
14'd205 : dout <= -16'd68;
14'd206 : dout <= -16'd81;
14'd207 : dout <= -16'd93;
14'd208 : dout <= 16'd6;
14'd209 : dout <= 16'd20;
14'd210 : dout <= 16'd34;
14'd211 : dout <= 16'd48;
14'd212 : dout <= 16'd61;
14'd213 : dout <= 16'd75;
14'd214 : dout <= 16'd89;
14'd215 : dout <= 16'd103;
14'd216 : dout <= -16'd6;
14'd217 : dout <= -16'd20;
14'd218 : dout <= -16'd34;
14'd219 : dout <= -16'd48;
14'd220 : dout <= -16'd61;
14'd221 : dout <= -16'd75;
14'd222 : dout <= -16'd89;
14'd223 : dout <= -16'd103;
14'd224 : dout <= 16'd7;
14'd225 : dout <= 16'd22;
14'd226 : dout <= 16'd37;
14'd227 : dout <= 16'd52;
14'd228 : dout <= 16'd67;
14'd229 : dout <= 16'd82;
14'd230 : dout <= 16'd97;
14'd231 : dout <= 16'd112;
14'd232 : dout <= -16'd7;
14'd233 : dout <= -16'd22;
14'd234 : dout <= -16'd37;
14'd235 : dout <= -16'd52;
14'd236 : dout <= -16'd67;
14'd237 : dout <= -16'd82;
14'd238 : dout <= -16'd97;
14'd239 : dout <= -16'd112;
14'd240 : dout <= 16'd8;
14'd241 : dout <= 16'd24;
14'd242 : dout <= 16'd41;
14'd243 : dout <= 16'd57;
14'd244 : dout <= 16'd74;
14'd245 : dout <= 16'd90;
14'd246 : dout <= 16'd107;
14'd247 : dout <= 16'd123;
14'd248 : dout <= -16'd8;
14'd249 : dout <= -16'd24;
14'd250 : dout <= -16'd41;
14'd251 : dout <= -16'd57;
14'd252 : dout <= -16'd74;
14'd253 : dout <= -16'd90;
14'd254 : dout <= -16'd107;
14'd255 : dout <= -16'd123;
14'd256 : dout <= 16'd9;
14'd257 : dout <= 16'd27;
14'd258 : dout <= 16'd45;
14'd259 : dout <= 16'd63;
14'd260 : dout <= 16'd82;
14'd261 : dout <= 16'd100;
14'd262 : dout <= 16'd118;
14'd263 : dout <= 16'd136;
14'd264 : dout <= -16'd9;
14'd265 : dout <= -16'd27;
14'd266 : dout <= -16'd45;
14'd267 : dout <= -16'd63;
14'd268 : dout <= -16'd82;
14'd269 : dout <= -16'd100;
14'd270 : dout <= -16'd118;
14'd271 : dout <= -16'd136;
14'd272 : dout <= 16'd10;
14'd273 : dout <= 16'd30;
14'd274 : dout <= 16'd50;
14'd275 : dout <= 16'd70;
14'd276 : dout <= 16'd90;
14'd277 : dout <= 16'd110;
14'd278 : dout <= 16'd130;
14'd279 : dout <= 16'd150;
14'd280 : dout <= -16'd10;
14'd281 : dout <= -16'd30;
14'd282 : dout <= -16'd50;
14'd283 : dout <= -16'd70;
14'd284 : dout <= -16'd90;
14'd285 : dout <= -16'd110;
14'd286 : dout <= -16'd130;
14'd287 : dout <= -16'd150;
14'd288 : dout <= 16'd11;
14'd289 : dout <= 16'd33;
14'd290 : dout <= 16'd55;
14'd291 : dout <= 16'd77;
14'd292 : dout <= 16'd99;
14'd293 : dout <= 16'd121;
14'd294 : dout <= 16'd143;
14'd295 : dout <= 16'd165;
14'd296 : dout <= -16'd11;
14'd297 : dout <= -16'd33;
14'd298 : dout <= -16'd55;
14'd299 : dout <= -16'd77;
14'd300 : dout <= -16'd99;
14'd301 : dout <= -16'd121;
14'd302 : dout <= -16'd143;
14'd303 : dout <= -16'd165;
14'd304 : dout <= 16'd12;
14'd305 : dout <= 16'd36;
14'd306 : dout <= 16'd60;
14'd307 : dout <= 16'd84;
14'd308 : dout <= 16'd109;
14'd309 : dout <= 16'd133;
14'd310 : dout <= 16'd157;
14'd311 : dout <= 16'd181;
14'd312 : dout <= -16'd12;
14'd313 : dout <= -16'd36;
14'd314 : dout <= -16'd60;
14'd315 : dout <= -16'd84;
14'd316 : dout <= -16'd109;
14'd317 : dout <= -16'd133;
14'd318 : dout <= -16'd157;
14'd319 : dout <= -16'd181;
14'd320 : dout <= 16'd13;
14'd321 : dout <= 16'd40;
14'd322 : dout <= 16'd66;
14'd323 : dout <= 16'd93;
14'd324 : dout <= 16'd120;
14'd325 : dout <= 16'd147;
14'd326 : dout <= 16'd173;
14'd327 : dout <= 16'd200;
14'd328 : dout <= -16'd13;
14'd329 : dout <= -16'd40;
14'd330 : dout <= -16'd66;
14'd331 : dout <= -16'd93;
14'd332 : dout <= -16'd120;
14'd333 : dout <= -16'd147;
14'd334 : dout <= -16'd173;
14'd335 : dout <= -16'd200;
14'd336 : dout <= 16'd14;
14'd337 : dout <= 16'd44;
14'd338 : dout <= 16'd73;
14'd339 : dout <= 16'd103;
14'd340 : dout <= 16'd132;
14'd341 : dout <= 16'd162;
14'd342 : dout <= 16'd191;
14'd343 : dout <= 16'd221;
14'd344 : dout <= -16'd14;
14'd345 : dout <= -16'd44;
14'd346 : dout <= -16'd73;
14'd347 : dout <= -16'd103;
14'd348 : dout <= -16'd132;
14'd349 : dout <= -16'd162;
14'd350 : dout <= -16'd191;
14'd351 : dout <= -16'd221;
14'd352 : dout <= 16'd16;
14'd353 : dout <= 16'd48;
14'd354 : dout <= 16'd81;
14'd355 : dout <= 16'd113;
14'd356 : dout <= 16'd146;
14'd357 : dout <= 16'd178;
14'd358 : dout <= 16'd211;
14'd359 : dout <= 16'd243;
14'd360 : dout <= -16'd16;
14'd361 : dout <= -16'd48;
14'd362 : dout <= -16'd81;
14'd363 : dout <= -16'd113;
14'd364 : dout <= -16'd146;
14'd365 : dout <= -16'd178;
14'd366 : dout <= -16'd211;
14'd367 : dout <= -16'd243;
14'd368 : dout <= 16'd17;
14'd369 : dout <= 16'd53;
14'd370 : dout <= 16'd89;
14'd371 : dout <= 16'd125;
14'd372 : dout <= 16'd160;
14'd373 : dout <= 16'd196;
14'd374 : dout <= 16'd232;
14'd375 : dout <= 16'd268;
14'd376 : dout <= -16'd17;
14'd377 : dout <= -16'd53;
14'd378 : dout <= -16'd89;
14'd379 : dout <= -16'd125;
14'd380 : dout <= -16'd160;
14'd381 : dout <= -16'd196;
14'd382 : dout <= -16'd232;
14'd383 : dout <= -16'd268;
14'd384 : dout <= 16'd19;
14'd385 : dout <= 16'd58;
14'd386 : dout <= 16'd98;
14'd387 : dout <= 16'd137;
14'd388 : dout <= 16'd176;
14'd389 : dout <= 16'd215;
14'd390 : dout <= 16'd255;
14'd391 : dout <= 16'd294;
14'd392 : dout <= -16'd19;
14'd393 : dout <= -16'd58;
14'd394 : dout <= -16'd98;
14'd395 : dout <= -16'd137;
14'd396 : dout <= -16'd176;
14'd397 : dout <= -16'd215;
14'd398 : dout <= -16'd255;
14'd399 : dout <= -16'd294;
14'd400 : dout <= 16'd21;
14'd401 : dout <= 16'd64;
14'd402 : dout <= 16'd108;
14'd403 : dout <= 16'd151;
14'd404 : dout <= 16'd194;
14'd405 : dout <= 16'd237;
14'd406 : dout <= 16'd281;
14'd407 : dout <= 16'd324;
14'd408 : dout <= -16'd21;
14'd409 : dout <= -16'd64;
14'd410 : dout <= -16'd108;
14'd411 : dout <= -16'd151;
14'd412 : dout <= -16'd194;
14'd413 : dout <= -16'd237;
14'd414 : dout <= -16'd281;
14'd415 : dout <= -16'd324;
14'd416 : dout <= 16'd23;
14'd417 : dout <= 16'd71;
14'd418 : dout <= 16'd118;
14'd419 : dout <= 16'd166;
14'd420 : dout <= 16'd213;
14'd421 : dout <= 16'd261;
14'd422 : dout <= 16'd308;
14'd423 : dout <= 16'd356;
14'd424 : dout <= -16'd23;
14'd425 : dout <= -16'd71;
14'd426 : dout <= -16'd118;
14'd427 : dout <= -16'd166;
14'd428 : dout <= -16'd213;
14'd429 : dout <= -16'd261;
14'd430 : dout <= -16'd308;
14'd431 : dout <= -16'd356;
14'd432 : dout <= 16'd26;
14'd433 : dout <= 16'd78;
14'd434 : dout <= 16'd130;
14'd435 : dout <= 16'd182;
14'd436 : dout <= 16'd235;
14'd437 : dout <= 16'd287;
14'd438 : dout <= 16'd339;
14'd439 : dout <= 16'd391;
14'd440 : dout <= -16'd26;
14'd441 : dout <= -16'd78;
14'd442 : dout <= -16'd130;
14'd443 : dout <= -16'd182;
14'd444 : dout <= -16'd235;
14'd445 : dout <= -16'd287;
14'd446 : dout <= -16'd339;
14'd447 : dout <= -16'd391;
14'd448 : dout <= 16'd28;
14'd449 : dout <= 16'd86;
14'd450 : dout <= 16'd143;
14'd451 : dout <= 16'd201;
14'd452 : dout <= 16'd258;
14'd453 : dout <= 16'd316;
14'd454 : dout <= 16'd373;
14'd455 : dout <= 16'd431;
14'd456 : dout <= -16'd28;
14'd457 : dout <= -16'd86;
14'd458 : dout <= -16'd143;
14'd459 : dout <= -16'd201;
14'd460 : dout <= -16'd258;
14'd461 : dout <= -16'd316;
14'd462 : dout <= -16'd373;
14'd463 : dout <= -16'd431;
14'd464 : dout <= 16'd31;
14'd465 : dout <= 16'd94;
14'd466 : dout <= 16'd158;
14'd467 : dout <= 16'd221;
14'd468 : dout <= 16'd284;
14'd469 : dout <= 16'd347;
14'd470 : dout <= 16'd411;
14'd471 : dout <= 16'd474;
14'd472 : dout <= -16'd31;
14'd473 : dout <= -16'd94;
14'd474 : dout <= -16'd158;
14'd475 : dout <= -16'd221;
14'd476 : dout <= -16'd284;
14'd477 : dout <= -16'd347;
14'd478 : dout <= -16'd411;
14'd479 : dout <= -16'd474;
14'd480 : dout <= 16'd34;
14'd481 : dout <= 16'd104;
14'd482 : dout <= 16'd174;
14'd483 : dout <= 16'd244;
14'd484 : dout <= 16'd313;
14'd485 : dout <= 16'd383;
14'd486 : dout <= 16'd453;
14'd487 : dout <= 16'd523;
14'd488 : dout <= -16'd34;
14'd489 : dout <= -16'd104;
14'd490 : dout <= -16'd174;
14'd491 : dout <= -16'd244;
14'd492 : dout <= -16'd313;
14'd493 : dout <= -16'd383;
14'd494 : dout <= -16'd453;
14'd495 : dout <= -16'd523;
14'd496 : dout <= 16'd38;
14'd497 : dout <= 16'd115;
14'd498 : dout <= 16'd191;
14'd499 : dout <= 16'd268;
14'd500 : dout <= 16'd345;
14'd501 : dout <= 16'd422;
14'd502 : dout <= 16'd498;
14'd503 : dout <= 16'd575;
14'd504 : dout <= -16'd38;
14'd505 : dout <= -16'd115;
14'd506 : dout <= -16'd191;
14'd507 : dout <= -16'd268;
14'd508 : dout <= -16'd345;
14'd509 : dout <= -16'd422;
14'd510 : dout <= -16'd498;
14'd511 : dout <= -16'd575;
14'd512 : dout <= 16'd42;
14'd513 : dout <= 16'd126;
14'd514 : dout <= 16'd210;
14'd515 : dout <= 16'd294;
14'd516 : dout <= 16'd379;
14'd517 : dout <= 16'd463;
14'd518 : dout <= 16'd547;
14'd519 : dout <= 16'd631;
14'd520 : dout <= -16'd42;
14'd521 : dout <= -16'd126;
14'd522 : dout <= -16'd210;
14'd523 : dout <= -16'd294;
14'd524 : dout <= -16'd379;
14'd525 : dout <= -16'd463;
14'd526 : dout <= -16'd547;
14'd527 : dout <= -16'd631;
14'd528 : dout <= 16'd46;
14'd529 : dout <= 16'd139;
14'd530 : dout <= 16'd231;
14'd531 : dout <= 16'd324;
14'd532 : dout <= 16'd417;
14'd533 : dout <= 16'd510;
14'd534 : dout <= 16'd602;
14'd535 : dout <= 16'd695;
14'd536 : dout <= -16'd46;
14'd537 : dout <= -16'd139;
14'd538 : dout <= -16'd231;
14'd539 : dout <= -16'd324;
14'd540 : dout <= -16'd417;
14'd541 : dout <= -16'd510;
14'd542 : dout <= -16'd602;
14'd543 : dout <= -16'd695;
14'd544 : dout <= 16'd51;
14'd545 : dout <= 16'd153;
14'd546 : dout <= 16'd255;
14'd547 : dout <= 16'd357;
14'd548 : dout <= 16'd459;
14'd549 : dout <= 16'd561;
14'd550 : dout <= 16'd663;
14'd551 : dout <= 16'd765;
14'd552 : dout <= -16'd51;
14'd553 : dout <= -16'd153;
14'd554 : dout <= -16'd255;
14'd555 : dout <= -16'd357;
14'd556 : dout <= -16'd459;
14'd557 : dout <= -16'd561;
14'd558 : dout <= -16'd663;
14'd559 : dout <= -16'd765;
14'd560 : dout <= 16'd56;
14'd561 : dout <= 16'd168;
14'd562 : dout <= 16'd280;
14'd563 : dout <= 16'd392;
14'd564 : dout <= 16'd505;
14'd565 : dout <= 16'd617;
14'd566 : dout <= 16'd729;
14'd567 : dout <= 16'd841;
14'd568 : dout <= -16'd56;
14'd569 : dout <= -16'd168;
14'd570 : dout <= -16'd280;
14'd571 : dout <= -16'd392;
14'd572 : dout <= -16'd505;
14'd573 : dout <= -16'd617;
14'd574 : dout <= -16'd729;
14'd575 : dout <= -16'd841;
14'd576 : dout <= 16'd61;
14'd577 : dout <= 16'd185;
14'd578 : dout <= 16'd308;
14'd579 : dout <= 16'd432;
14'd580 : dout <= 16'd555;
14'd581 : dout <= 16'd679;
14'd582 : dout <= 16'd802;
14'd583 : dout <= 16'd926;
14'd584 : dout <= -16'd61;
14'd585 : dout <= -16'd185;
14'd586 : dout <= -16'd308;
14'd587 : dout <= -16'd432;
14'd588 : dout <= -16'd555;
14'd589 : dout <= -16'd679;
14'd590 : dout <= -16'd802;
14'd591 : dout <= -16'd926;
14'd592 : dout <= 16'd68;
14'd593 : dout <= 16'd204;
14'd594 : dout <= 16'd340;
14'd595 : dout <= 16'd476;
14'd596 : dout <= 16'd612;
14'd597 : dout <= 16'd748;
14'd598 : dout <= 16'd884;
14'd599 : dout <= 16'd1020;
14'd600 : dout <= -16'd68;
14'd601 : dout <= -16'd204;
14'd602 : dout <= -16'd340;
14'd603 : dout <= -16'd476;
14'd604 : dout <= -16'd612;
14'd605 : dout <= -16'd748;
14'd606 : dout <= -16'd884;
14'd607 : dout <= -16'd1020;
14'd608 : dout <= 16'd74;
14'd609 : dout <= 16'd224;
14'd610 : dout <= 16'd373;
14'd611 : dout <= 16'd523;
14'd612 : dout <= 16'd672;
14'd613 : dout <= 16'd822;
14'd614 : dout <= 16'd971;
14'd615 : dout <= 16'd1121;
14'd616 : dout <= -16'd74;
14'd617 : dout <= -16'd224;
14'd618 : dout <= -16'd373;
14'd619 : dout <= -16'd523;
14'd620 : dout <= -16'd672;
14'd621 : dout <= -16'd822;
14'd622 : dout <= -16'd971;
14'd623 : dout <= -16'd1121;
14'd624 : dout <= 16'd82;
14'd625 : dout <= 16'd246;
14'd626 : dout <= 16'd411;
14'd627 : dout <= 16'd575;
14'd628 : dout <= 16'd740;
14'd629 : dout <= 16'd904;
14'd630 : dout <= 16'd1069;
14'd631 : dout <= 16'd1233;
14'd632 : dout <= -16'd82;
14'd633 : dout <= -16'd246;
14'd634 : dout <= -16'd411;
14'd635 : dout <= -16'd575;
14'd636 : dout <= -16'd740;
14'd637 : dout <= -16'd904;
14'd638 : dout <= -16'd1069;
14'd639 : dout <= -16'd1233;
14'd640 : dout <= 16'd90;
14'd641 : dout <= 16'd271;
14'd642 : dout <= 16'd452;
14'd643 : dout <= 16'd633;
14'd644 : dout <= 16'd814;
14'd645 : dout <= 16'd995;
14'd646 : dout <= 16'd1176;
14'd647 : dout <= 16'd1357;
14'd648 : dout <= -16'd90;
14'd649 : dout <= -16'd271;
14'd650 : dout <= -16'd452;
14'd651 : dout <= -16'd633;
14'd652 : dout <= -16'd814;
14'd653 : dout <= -16'd995;
14'd654 : dout <= -16'd1176;
14'd655 : dout <= -16'd1357;
14'd656 : dout <= 16'd99;
14'd657 : dout <= 16'd298;
14'd658 : dout <= 16'd497;
14'd659 : dout <= 16'd696;
14'd660 : dout <= 16'd895;
14'd661 : dout <= 16'd1094;
14'd662 : dout <= 16'd1293;
14'd663 : dout <= 16'd1492;
14'd664 : dout <= -16'd99;
14'd665 : dout <= -16'd298;
14'd666 : dout <= -16'd497;
14'd667 : dout <= -16'd696;
14'd668 : dout <= -16'd895;
14'd669 : dout <= -16'd1094;
14'd670 : dout <= -16'd1293;
14'd671 : dout <= -16'd1492;
14'd672 : dout <= 16'd109;
14'd673 : dout <= 16'd328;
14'd674 : dout <= 16'd547;
14'd675 : dout <= 16'd766;
14'd676 : dout <= 16'd985;
14'd677 : dout <= 16'd1204;
14'd678 : dout <= 16'd1423;
14'd679 : dout <= 16'd1642;
14'd680 : dout <= -16'd109;
14'd681 : dout <= -16'd328;
14'd682 : dout <= -16'd547;
14'd683 : dout <= -16'd766;
14'd684 : dout <= -16'd985;
14'd685 : dout <= -16'd1204;
14'd686 : dout <= -16'd1423;
14'd687 : dout <= -16'd1642;
14'd688 : dout <= 16'd120;
14'd689 : dout <= 16'd361;
14'd690 : dout <= 16'd601;
14'd691 : dout <= 16'd842;
14'd692 : dout <= 16'd1083;
14'd693 : dout <= 16'd1324;
14'd694 : dout <= 16'd1564;
14'd695 : dout <= 16'd1805;
14'd696 : dout <= -16'd120;
14'd697 : dout <= -16'd361;
14'd698 : dout <= -16'd601;
14'd699 : dout <= -16'd842;
14'd700 : dout <= -16'd1083;
14'd701 : dout <= -16'd1324;
14'd702 : dout <= -16'd1564;
14'd703 : dout <= -16'd1805;
14'd704 : dout <= 16'd132;
14'd705 : dout <= 16'd397;
14'd706 : dout <= 16'd662;
14'd707 : dout <= 16'd927;
14'd708 : dout <= 16'd1192;
14'd709 : dout <= 16'd1457;
14'd710 : dout <= 16'd1722;
14'd711 : dout <= 16'd1987;
14'd712 : dout <= -16'd132;
14'd713 : dout <= -16'd397;
14'd714 : dout <= -16'd662;
14'd715 : dout <= -16'd927;
14'd716 : dout <= -16'd1192;
14'd717 : dout <= -16'd1457;
14'd718 : dout <= -16'd1722;
14'd719 : dout <= -16'd1987;
14'd720 : dout <= 16'd145;
14'd721 : dout <= 16'd437;
14'd722 : dout <= 16'd728;
14'd723 : dout <= 16'd1020;
14'd724 : dout <= 16'd1311;
14'd725 : dout <= 16'd1603;
14'd726 : dout <= 16'd1894;
14'd727 : dout <= 16'd2186;
14'd728 : dout <= -16'd145;
14'd729 : dout <= -16'd437;
14'd730 : dout <= -16'd728;
14'd731 : dout <= -16'd1020;
14'd732 : dout <= -16'd1311;
14'd733 : dout <= -16'd1603;
14'd734 : dout <= -16'd1894;
14'd735 : dout <= -16'd2186;
14'd736 : dout <= 16'd160;
14'd737 : dout <= 16'd480;
14'd738 : dout <= 16'd801;
14'd739 : dout <= 16'd1121;
14'd740 : dout <= 16'd1442;
14'd741 : dout <= 16'd1762;
14'd742 : dout <= 16'd2083;
14'd743 : dout <= 16'd2403;
14'd744 : dout <= -16'd160;
14'd745 : dout <= -16'd480;
14'd746 : dout <= -16'd801;
14'd747 : dout <= -16'd1121;
14'd748 : dout <= -16'd1442;
14'd749 : dout <= -16'd1762;
14'd750 : dout <= -16'd2083;
14'd751 : dout <= -16'd2403;
14'd752 : dout <= 16'd176;
14'd753 : dout <= 16'd529;
14'd754 : dout <= 16'd881;
14'd755 : dout <= 16'd1234;
14'd756 : dout <= 16'd1587;
14'd757 : dout <= 16'd1940;
14'd758 : dout <= 16'd2292;
14'd759 : dout <= 16'd2645;
14'd760 : dout <= -16'd176;
14'd761 : dout <= -16'd529;
14'd762 : dout <= -16'd881;
14'd763 : dout <= -16'd1234;
14'd764 : dout <= -16'd1587;
14'd765 : dout <= -16'd1940;
14'd766 : dout <= -16'd2292;
14'd767 : dout <= -16'd2645;
14'd768 : dout <= 16'd194;
14'd769 : dout <= 16'd582;
14'd770 : dout <= 16'd970;
14'd771 : dout <= 16'd1358;
14'd772 : dout <= 16'd1746;
14'd773 : dout <= 16'd2134;
14'd774 : dout <= 16'd2522;
14'd775 : dout <= 16'd2910;
14'd776 : dout <= -16'd194;
14'd777 : dout <= -16'd582;
14'd778 : dout <= -16'd970;
14'd779 : dout <= -16'd1358;
14'd780 : dout <= -16'd1746;
14'd781 : dout <= -16'd2134;
14'd782 : dout <= -16'd2522;
14'd783 : dout <= -16'd2910;
default : dout <= 16'd0;
endcase
end
endmodule
|
////////////////////////////////////////////////
// Copyright (c) 2012, Andrew "bunnie" Huang
// (bunnie _aht_ bunniestudios "dote" com)
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////
/// according to Xilinx WP272, all flip flops are reset to a "known value"
/// by GSR. You're supposed to trust that. Of course, this "known value"
/// isn't very explicitly stated, searching through the xilinx manuals
/// it seems everything defaults to 0 except for stuff that's presetable.
/// anyways, this module generates a local, synchronized reset based upon
/// a global reset. The idea is to instantiate one of these near every
/// terminal reset sink, so as to avoid loading down a global reset network.
/// this should optimize utilization and speed a bit, and also allow the
/// synthesizer to get more aggressive about using larger primitives
//////////
// the input is the asychronous reset of interest
// and the clock to synchronize it to
// the output is a synchronized reset that is at least four clock cycles wide
module sync_reset (
input wire glbl_reset, // async reset
input wire clk,
output wire reset
);
wire [3:0] reschain;
FDPE fdres0( .Q(reschain[0]), .C(clk), .CE(1'b1), .D(1'b0), .PRE(glbl_reset) );
FDPE fdres1( .Q(reschain[1]), .C(clk), .CE(1'b1), .D(reschain[0]), .PRE(glbl_reset) );
FDPE fdres2( .Q(reschain[2]), .C(clk), .CE(1'b1), .D(reschain[1]), .PRE(glbl_reset) );
FDPE fdres3( .Q(reschain[3]), .C(clk), .CE(1'b1), .D(reschain[2]), .PRE(glbl_reset) );
assign reset = reschain[3];
endmodule // sync_reset
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "/home/scf-07/zhiyango/ee577b/projs/processor/syn/src/control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
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//================================================================================
//================================================================================
// ================================================
// PRM instruction
`aluwprm:
begin
case(ctrl_ppp)
`aa: // aluwprm PRM `aa
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`uu: // aluwprm PRM `uu
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//bytes8-15
result[64:127]<=64'd0;
end
`dd: // aluwprm PRM `dd
begin
//bytes0-7
result[0:63]<=64'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[0:7];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`ee: // aluwprm PRM `ee
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//byte1
result[8:15]<=8'd0;
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
//byte3
result[24:31]<=8'd0;
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
//byte5
result[40:47]<=8'd0;
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
//byte7
result[56:63]<=8'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
//byte9
result[72:79]<=8'd0;
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
//byte11
result[88:95]<=8'd0;
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
//byte13
result[104:111]<=8'd0;
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
//byte15
result[120:127]<=8'd0;
end
`oo: // aluwprm PRM `oo
begin
//byte0
result[0:7]<=8'd0;
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
//byte2
result[16:23]<=8'd0;
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
//byte4
result[32:39]<=8'd0;
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
//byte6
result[48:55]<=8'd0;
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//byte8
result[64:71]<=8'd0;
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
//byte10
result[80:87]<=8'd0;
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
//byte12
result[96:103]<=8'd0;
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
//byte14
result[112:119]<=8'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`mm: // aluwprm PRM `mm
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//bytes1-14
result[8:127]<=120'd0;
end
`ll: // aluwprm PRM `ll
begin
//bytes0-14
result[0:119]<=120'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
default: // aluwprm PRM Default
begin
result<=128'd0;
end
endcase
end
/*
* ========================================================
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*=======================================================
*========================================================
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*=========================================================
*========================================================
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*========================================================
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*=======================================================
*/
// ================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ppp)
`aa: // aluwslli SLLI `aa
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`uu: // aluwslli SLLI `uu
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:127]<=64'd0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:127]<=64'd0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:127]<=64'd0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:127]<=64'd0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:127]<=64'd0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:127]<=64'd0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:127]<=64'd0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:127]<=64'd0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:127]<=64'd0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:127]<=64'd0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:127]<=64'd0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:127]<=64'd0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:127]<=64'd0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:127]<=64'd0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:127]<=64'd0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:127]<=64'd0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:127]<=64'd0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:127]<=64'd0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:127]<=64'd0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:127]<=64'd0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
endcase
end
`dd: // aluwslli SLLI `dd
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
3'd1:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
4'd1:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
5'd1:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`ee: // aluwslli SLLI `ee
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:15]<=8'b0;
result[16:23]<=reg_A[16:23];
result[24:31]<=8'b0;
result[32:39]<=reg_A[33:39];
result[40:47]<=8'b0;
result[48:55]<=reg_A[48:55];
result[56:63]<=8'b0;
result[64:71]<=reg_A[64:71];
result[72:79]<=8'b0;
result[80:87]<=reg_A[80:87];
result[88:95]<=8'b0;
result[96:103]<=reg_A[96:103];
result[104:111]<=8'b0;
result[112:119]<=reg_A[112:119];
result[120:127]<=8'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<=8'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<=8'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<=8'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<=8'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<=8'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<=8'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<=8'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<=16'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<=16'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<=16'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<=16'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<=16'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<=16'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<=16'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<=16'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<=16'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<=16'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<=16'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<=16'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<=16'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<=16'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<=16'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<=32'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<=32'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<=32'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<=32'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<=32'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<=32'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<=32'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<=32'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<=32'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<=32'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<=32'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<=32'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<=32'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<=32'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<=32'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<=32'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<=32'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<=32'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<=32'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<=32'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<=32'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<=32'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<=32'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<=32'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<=32'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<=32'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<=32'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<=32'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<=32'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<=32'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<=32'b0;
end
endcase
end
endcase
end
`oo: // aluwslli SLLI `oo
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`mm: // aluwslli SLLI `mm
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:127]<=119'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:127]<=119'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:127]<=119'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:127]<=119'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:127]<=119'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:127]<=119'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:127]<=119'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:127]<=119'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:15]<=reg_A[0:15];
result[16:127]<=112'b0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:127]<=112'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:127]<=112'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:127]<=112'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:127]<=112'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:127]<=112'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:127]<=112'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:127]<=112'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:127]<=112'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:127]<=112'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:127]<=112'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:127]<=112'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:127]<=112'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:127]<=112'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:127]<=112'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:127]<=112'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:31]<=reg_A[0:31];
result[32:127]<=96'b0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:127]<=96'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:127]<=96'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:127]<=96'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:127]<=96'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:127]<=96'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:127]<=96'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:127]<=96'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:127]<=96'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:127]<=96'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:127]<=96'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:127]<=96'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:127]<=96'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:127]<=96'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:127]<=96'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:127]<=96'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:127]<=96'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:127]<=96'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:127]<=96'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:127]<=96'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:127]<=96'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:127]<=96'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:127]<=96'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:127]<=96'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:127]<=96'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:127]<=96'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:127]<=96'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:127]<=96'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:127]<=96'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:127]<=96'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:127]<=96'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:127]<=96'b0;
end
endcase
end
endcase
end
`ll: // aluwslli SLLI `ll
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:119]<=120'b0;
result[120:127]<=reg_A[120:127];
end
3'd1:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:111]<=112'b0;
result[112:127]<=reg_A[112:127];
end
4'd1:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:95]<=96'b0;
result[96:127]<=reg_A[96:127];
end
5'd1:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
endcase
end
// ================================================
// PRM instruction
`aluwprm:
begin
case(ctrl_ppp)
`aa: // aluwprm PRM `aa
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`uu: // aluwprm PRM `uu
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//bytes8-15
result[64:127]<=64'd0;
end
`dd: // aluwprm PRM `dd
begin
//bytes0-7
result[0:63]<=64'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[0:7];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`ee: // aluwprm PRM `ee
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//byte1
result[8:15]<=8'd0;
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
//byte3
result[24:31]<=8'd0;
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
//byte5
result[40:47]<=8'd0;
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
//byte7
result[56:63]<=8'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
//byte9
result[72:79]<=8'd0;
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
//byte11
result[88:95]<=8'd0;
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
//byte13
result[104:111]<=8'd0;
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
//byte15
result[120:127]<=8'd0;
end
`oo: // aluwprm PRM `oo
begin
//byte0
result[0:7]<=8'd0;
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
//byte2
result[16:23]<=8'd0;
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
//byte4
result[32:39]<=8'd0;
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
//byte6
result[48:55]<=8'd0;
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//byte8
result[64:71]<=8'd0;
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
//byte10
result[80:87]<=8'd0;
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
//byte12
result[96:103]<=8'd0;
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
//byte14
result[112:119]<=8'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`mm: // aluwprm PRM `mm
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//bytes1-14
result[8:127]<=120'd0;
end
`ll: // aluwprm PRM `ll
begin
//bytes0-14
result[0:119]<=120'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
default: // aluwprm PRM Default
begin
result<=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
/*
* TOP2049 Open Source programming suite
*
* Cypress M8C/M7C In System Serial Programmer
* FPGA bottomhalf implementation
*
* Copyright (c) 2010-2011 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/* The runtime ID and revision. */
`define RUNTIME_ID 16'h0007
`define RUNTIME_REV 16'h01
module m8c_issp(data, ale, write, read, osc_in, zif);
inout [7:0] data;
input ale;
input write;
input read;
input osc_in; /* 24MHz oscillator */
inout [48:1] zif;
/* Interface to the microcontroller */
wire read_oe; /* Read output-enable */
reg [7:0] address; /* Cached address value */
reg [7:0] read_data; /* Cached read data */
wire low, high; /* Constant lo/hi */
/* The M8C programmer context */
`define ISSP_VEC_SIZE 22 /* bits */
reg [1:0] issp_busy; /* Busy state. We're busy, if bits are unequal */
reg [7:0] issp_command; /* Currently loaded command */
reg [`ISSP_VEC_SIZE-1:0] issp_vector; /* Currently loaded output vector */
reg [5:0] issp_vecbit; /* Currently TXed/RXed bit */
reg [7:0] issp_count; /* General purpose counter */
reg [3:0] issp_state; /* Statemachine */
/* The M8C programmer commands */
`define ISSPCMD_NONE 0 /* No command loaded */
`define ISSPCMD_POR 1 /* Perform a power-on-reset */
`define ISSPCMD_PWROFF 2 /* Turn power off */
`define ISSPCMD_EXEC 3 /* Do an "execute" transfer */
`define IS_BUSY (issp_busy[0] != issp_busy[1])
`define SET_FINISHED issp_busy[1] <= issp_busy[0]
/* The M8C device signals */
wire sig_sdata;
wire sig_sdata_input;
wire sig_sclk;
wire sig_sclk_z;
reg dut_sdata;
reg dut_sdata_input;
reg dut_sclk;
reg dut_sclk_z;
reg dut_bitbang_disabled;
reg dut_bitbang_sdata;
reg dut_bitbang_sdata_input;
reg dut_bitbang_sclk;
reg dut_bitbang_sclk_z;
reg dut_vdd;
`define VDD_ON 1
`define VDD_OFF 0
`define ZIF_SDATA 22 /* SDATA ZIF pin */
assign low = 0;
assign high = 1;
/* The delay counter. Based on the 24MHz input clock. */
reg [15:0] delay_count;
wire osc;
IBUF osc_ibuf(.I(osc_in), .O(osc));
`define DELAY_250NS 6 - 1 /* 250 ns */
`define DELAY_1US 24 - 1 /* 1 us */
`define DELAY_1MS 24000 - 1 /* 1 ms */
`define DELAY_1P5MS 36000 - 1 /* 1.5 ms */
`define DELAY_2MS 48000 - 1 /* 2 ms */
initial begin
address <= 0;
read_data <= 0;
issp_busy <= 0;
issp_command <= 0;
issp_vector <= 0;
issp_vecbit <= 0;
issp_count <= 0;
issp_state <= 0;
dut_sdata <= 0;
dut_sdata_input <= 1;
dut_sclk <= 0;
dut_sclk_z <= 1;
dut_vdd <= `VDD_OFF;
dut_bitbang_disabled <= 0;
dut_bitbang_sdata <= 0;
dut_bitbang_sdata_input <= 1;
dut_bitbang_sclk <= 0;
dut_bitbang_sclk_z <= 1;
delay_count <= 0;
end
always @(posedge osc) begin
if (delay_count == 0 && `IS_BUSY) begin
case (issp_command)
`ISSPCMD_POR: begin
case (issp_state)
0: begin
/* Turn on power and wait vDDwait time */
dut_vdd <= `VDD_ON;
dut_bitbang_disabled <= 1;
dut_sclk_z <= 1;
dut_sclk <= 0;
dut_sdata_input <= 1;
delay_count <= `DELAY_1MS; /* TvDDwait */
issp_state <= 1;
end
1: begin
dut_sclk_z <= 0;
dut_sclk <= 0;
if (zif[`ZIF_SDATA] == 0) begin
issp_state <= 2;
issp_vecbit <= `ISSP_VEC_SIZE;
end
// delay_count <= `DELAY_250NS;
end
2: begin
if (issp_vecbit == 0) begin
issp_state <= 4;
end else begin
/* Ok, ready to send the next bit */
dut_sdata_input <= 0;
dut_sdata <= issp_vector[issp_vecbit - 1];
dut_sclk <= 1;
issp_state <= 3;
end
delay_count <= `DELAY_250NS;
end
3: begin
dut_sclk <= 0;
issp_state <= 2;
issp_vecbit <= issp_vecbit - 1;
delay_count <= `DELAY_250NS;
end
4: begin
/* We're done. */
`SET_FINISHED;
dut_bitbang_disabled <= 0;
dut_sclk <= 0;
dut_sdata_input <= 1;
issp_state <= 0;
end
endcase
end
`ISSPCMD_PWROFF: begin
dut_vdd <= `VDD_OFF;
dut_bitbang_disabled <= 0;
dut_sdata <= 0;
dut_sdata_input <= 1;
dut_sclk <= 0;
dut_sclk_z <= 1;
issp_state <= 0;
delay_count <= 0;
/* We're done. */
`SET_FINISHED;
end
`ISSPCMD_EXEC: begin
case (issp_state)
0: begin /* Init */
dut_bitbang_disabled <= 1;
dut_sdata <= 0;
dut_sdata_input <= 1;
dut_sclk_z <= 0;
dut_sclk <= 0;
issp_count <= 10;
issp_state <= 1;
end
1: begin /* Wait for SDATA=1 */
if (zif[`ZIF_SDATA]) begin
issp_state <= 5; /* goto wait-for-SDATA=0 */
end else begin
delay_count <= `DELAY_1US;
issp_count <= issp_count - 1;
issp_state <= 2;
end
end
2: begin
if (issp_count == 0) begin
/* Timeout */
issp_state <= 3; /* Send 33 CLKs */
issp_count <= 33;
end else begin
issp_state <= 1;
end
end
3: begin /* Send 33 CLKs */
dut_sclk <= 1;
issp_count <= issp_count - 1;
delay_count <= `DELAY_250NS;
issp_state <= 4;
end
4: begin
dut_sclk <= 0;
if (issp_count == 0) begin
/* Sent all */
if (zif[`ZIF_SDATA]) begin
issp_state <= 5; /* goto wait-for-SDATA=0 */
end else begin
/* goto send-50-CLKs */
issp_state <= 6;
issp_count <= 50;
end
end else begin
issp_state <= 3;
end
delay_count <= `DELAY_250NS;
end
5: begin /* Wait for SDATA=0 */
if (zif[`ZIF_SDATA] == 0) begin
issp_state <= 6;
issp_count <= 50;
end else begin
issp_state <= 5;
end
delay_count <= `DELAY_250NS;
end
6: begin /* Send 50 CLKs */
dut_sclk <= 1;
issp_count <= issp_count - 1;
delay_count <= `DELAY_250NS;
issp_state <= 7;
end
7: begin
dut_sclk <= 0;
if (issp_count == 0) begin
issp_state <= 8; /* done */
end else begin
issp_state <= 6;
end
delay_count <= `DELAY_250NS;
end
8: begin /* finish */
/* We're done. */
dut_bitbang_disabled <= 0;
issp_state <= 0;
`SET_FINISHED;
end
endcase
end
endcase
end else begin
if (delay_count) begin
delay_count <= delay_count - 1;
end
end
end
always @(posedge write) begin
case (address)
8'h10: begin
/* Bitbanging */
dut_bitbang_sdata <= data[0];
dut_bitbang_sdata_input <= data[1];
dut_bitbang_sclk <= data[2];
dut_bitbang_sclk_z <= data[3];
end
8'h11: begin
/* Load and execute command */
issp_command <= data;
issp_busy[0] <= ~issp_busy[1];
end
8'h12: begin
/* Load vector low */
issp_vector[7:0] <= data;
end
8'h13: begin
/* Load vector med */
issp_vector[15:8] <= data;
end
8'h14: begin
/* Load vector high */
issp_vector[21:16] <= data[5:0];
end
endcase
end
always @(negedge read) begin
case (address)
8'h10: begin
/* Read status */
read_data[0] <= issp_busy[0];
read_data[1] <= issp_busy[1];
read_data[2] <= issp_state[0];
read_data[3] <= issp_state[1];
read_data[4] <= issp_state[2];
read_data[5] <= zif[`ZIF_SDATA];
read_data[6] <= 0;
read_data[7] <= 0;
end
8'hFD: read_data <= `RUNTIME_ID & 16'hFF;
8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF;
8'hFF: read_data <= `RUNTIME_REV;
endcase
end
always @(negedge ale) begin
address <= data;
end
assign read_oe = !read && address[4];
assign sig_sdata = dut_bitbang_disabled ? dut_sdata : dut_bitbang_sdata;
assign sig_sdata_input = dut_bitbang_disabled ? dut_sdata_input : dut_bitbang_sdata_input;
assign sig_sclk = dut_bitbang_disabled ? dut_sclk : dut_bitbang_sclk;
assign sig_sclk_z = dut_bitbang_disabled ? dut_sclk_z : dut_bitbang_sclk_z;
bufif0(zif[1], low, low);
bufif0(zif[2], low, low);
bufif0(zif[3], low, low);
bufif0(zif[4], low, low);
bufif0(zif[5], low, low);
bufif0(zif[6], low, low);
bufif0(zif[7], low, low);
bufif0(zif[8], low, low);
bufif0(zif[9], low, low);
bufif0(zif[10], low, low);
bufif0(zif[11], low, low);
bufif0(zif[12], low, low);
bufif0(zif[13], low, low);
bufif0(zif[14], low, low);
bufif0(zif[15], low, low);
bufif0(zif[16], low, low);
bufif0(zif[17], low, low);
bufif0(zif[18], low, low);
bufif0(zif[19], low, low);
bufif0(zif[20], low, low); /* GND */
bufif0(zif[21], high, low); /* VDD */
bufif0(zif[`ZIF_SDATA], sig_sdata, sig_sdata_input); /* SDATA */
bufif0(zif[23], sig_sclk, sig_sclk_z); /* SCLK */
bufif0(zif[24], dut_vdd, low); /* VDDen */
bufif0(zif[25], low, low);
bufif0(zif[26], low, low);
bufif0(zif[27], low, low);
bufif0(zif[28], low, low);
bufif0(zif[29], low, low);
bufif0(zif[30], low, low);
bufif0(zif[31], low, low);
bufif0(zif[32], low, low);
bufif0(zif[33], low, low);
bufif0(zif[34], low, low);
bufif0(zif[35], low, low);
bufif0(zif[36], low, low);
bufif0(zif[37], low, low);
bufif0(zif[38], low, low);
bufif0(zif[39], low, low);
bufif0(zif[40], low, low);
bufif0(zif[41], low, low);
bufif0(zif[42], low, low);
bufif0(zif[43], low, low);
bufif0(zif[44], low, low);
bufif0(zif[45], low, low);
bufif0(zif[46], low, low);
bufif0(zif[47], low, low);
bufif0(zif[48], low, low);
bufif1(data[0], read_data[0], read_oe);
bufif1(data[1], read_data[1], read_oe);
bufif1(data[2], read_data[2], read_oe);
bufif1(data[3], read_data[3], read_oe);
bufif1(data[4], read_data[4], read_oe);
bufif1(data[5], read_data[5], read_oe);
bufif1(data[6], read_data[6], read_oe);
bufif1(data[7], read_data[7], read_oe);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V |
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_cmd_gen
# (parameter
// cmd_gen settings
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 4,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_DWIDTH_RATIO = 2, // 2-FR,4-HR,8-QR
CFG_CTL_QUEUE_DEPTH = 8,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary coded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_ENABLE_QUEUE = 1,
CFG_ENABLE_BURST_MERGE = 1,
CFG_CMD_GEN_OUTPUT_REG = 0,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
// tbp interface
tbp_full,
tbp_load,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_multicast,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// input interface
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_id,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
// datapath interface
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
proc_read,
proc_size,
proc_localid,
wdatap_free_id_valid, // from wdata path
wdatap_free_id_dataid, // from wdata path
rdatap_free_id_valid, // from rdata path
rdatap_free_id_dataid, // from rdata path
tbp_load_index,
data_complete,
data_rmw_complete,
// nodm and ecc signal
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
data_partial_be,
// configuration ports
cfg_enable_cmd_split,
cfg_burst_length,
cfg_addr_order,
cfg_enable_ecc,
cfg_enable_no_dm,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width
);
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
localparam INT_LOCAL_ADDR_WIDTH = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
input ctl_clk;
input ctl_reset_n;
input tbp_full;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] tbp_read;
input [CFG_CTL_TBP_NUM-1:0] tbp_write;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output cmd_gen_load;
output [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
output cmd_gen_write;
output cmd_gen_read;
output cmd_gen_multicast;
output [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
output [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
output cmd_gen_priority;
output cmd_gen_rmw_correct;
output cmd_gen_rmw_partial;
output cmd_gen_autopch;
output cmd_gen_complete;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output cmd_gen_full;
input cmd_valid;
input [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
input cmd_write;
input cmd_read;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
input cmd_multicast;
input [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
input cmd_priority;
input cmd_autoprecharge;
output proc_busy;
output proc_load;
output proc_load_dataid;
output proc_write;
output proc_read;
output [CFG_INT_SIZE_WIDTH-1:0] proc_size;
output [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
input wdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
input rdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output errcmd_ready; // high means cmd_gen accepts command
input errcmd_valid;
input [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
input [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
input data_partial_be;
input cfg_enable_cmd_split;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length; // this contains immediate BL value, max is 31
input [CFG_PORT_WIDTH_ADDR_ORDER-1:0] cfg_addr_order; // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
input cfg_enable_ecc;
input cfg_enable_no_dm;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
// === address mapping
integer n;
integer j;
integer k;
integer m;
wire [INT_LOCAL_ADDR_WIDTH-1:0] int_cmd_address;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr;
// === command splitting block
reg [CFG_MEM_IF_CS_WIDTH-1:0] split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] split_col_addr;
reg split_read;
reg split_write;
reg [CFG_INT_SIZE_WIDTH-1:0] split_size;
reg split_autopch;
reg split_multicast;
reg split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] split_localid;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg buf_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] buf_localid;
reg [CFG_LOCAL_SIZE_WIDTH:0] buf_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] buf_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg [CFG_LOCAL_SIZE_WIDTH-1:0] decrmntd_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] incrmntd_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
reg [CFG_MEM_IF_CS_WIDTH-1:0] max_chip_from_csr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
reg [2:0] unaligned_burst; // because planned max native size is 8, unaligned burst can be a max of 7
reg [3:0] native_size; // support native size up to 15, bl16 FR have native size of 8
wire require_gen;
reg deassert_ready;
reg registered;
reg generating;
// === ecc mux
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr_combi;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr_combi;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr_combi;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr_combi;
reg ecc_read_combi;
reg ecc_write_combi;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size_combi;
reg ecc_autopch_combi;
reg ecc_multicast_combi;
reg ecc_priority_combi;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid_combi;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr;
reg ecc_read;
reg ecc_write;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size;
reg ecc_autopch;
reg ecc_multicast;
reg ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid;
reg ecc_int_combi;
reg errcmd_ready_combi;
reg partial_combi;
reg correct_combi;
reg partial_opr_combi;
reg ecc_int;
reg ecc_int_r;
reg errcmd_ready;
reg partial;
reg correct;
reg partial_opr;
wire mux_busy;
wire [CFG_MEM_IF_CS_WIDTH-1:0] muxed_cs_addr;
wire [CFG_MEM_IF_BA_WIDTH-1:0] muxed_bank_addr;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] muxed_row_addr;
wire [CFG_MEM_IF_COL_WIDTH-1:0] muxed_col_addr;
wire muxed_read;
wire muxed_write;
wire [CFG_INT_SIZE_WIDTH-1:0] muxed_size;
wire muxed_autopch;
wire muxed_multicast;
wire muxed_priority;
wire [CFG_LOCAL_ID_WIDTH-1:0] muxed_localid;
wire [CFG_DATA_ID_WIDTH-1:0] muxed_dataid;
wire muxed_complete;
wire muxed_correct;
wire muxed_partial;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_0;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_1;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_2;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_3;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
reg proc_busy_sig;
reg proc_ecc_busy_sig;
reg proc_load_sig;
reg proc_load_dataid_sig;
reg proc_write_sig;
reg proc_read_sig;
reg [CFG_INT_SIZE_WIDTH-1:0] proc_size_sig;
reg [CFG_LOCAL_ID_WIDTH-1:0] proc_localid_sig;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
// === merging signals
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
reg [CFG_INT_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [CFG_INT_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last2_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last2_col_addr;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
// === queue
reg [BUFFER_WIDTH-1:0] pipe[CFG_CTL_QUEUE_DEPTH-1:0];
reg pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire write_to_queue;
wire queue_empty;
wire queue_full;
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_row_addr;
reg read [CFG_CTL_TBP_NUM-1:0];
reg write [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
wire [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire one = 1'b1;
wire zero = 1'b0;
//======================= TBP info ===========================
generate
genvar p;
for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
begin : info_per_tbp
always @ (*)
begin
if (tbp_load[p])
begin
read [p] = cmd_gen_read;
write [p] = cmd_gen_write;
chipsel[p] = cmd_gen_chipsel;
bank [p] = cmd_gen_bank;
row [p] = cmd_gen_row;
col [p] = cmd_gen_col;
end
else
begin
read [p] = tbp_read [p];
write [p] = tbp_write [p];
chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
bank [p] = tbp_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
row [p] = tbp_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
col [p] = tbp_col [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
end
end
end
for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
begin : info_per_shadow_tbp
assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
assign shadow_bank [p] = tbp_shadow_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
assign shadow_row [p] = tbp_shadow_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
end
endgenerate
//======================= Address Remapping ===========================
// Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
always @ (*)
begin
// Row width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Bank width info
if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Chipsel width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
end
assign int_cmd_address = cmd_address;
// Supported addr order
// 0 - chip-row-bank-col
// 1 - chip-bank-row-col
// 2 - row-chip-bank-col
// Derive column address from address
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
begin
if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
begin
int_col_addr[n] = int_cmd_address[n];
end
else
begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
end
// Derive row address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
always @(*)
begin : Row_addr_loop
for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
begin
row_addr_loop_1 = j + cfg_addr_bitsel_row;
int_row_addr[j] = int_cmd_address[row_addr_loop_1];
end
for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
begin
row_addr_loop_2 = j + cfg_addr_bitsel_row;
if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
begin
int_row_addr[j] = int_cmd_address[row_addr_loop_2];
end
else
begin
int_row_addr[j] = 1'b0;
end
end
end
// Derive bank address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
always @(*)
begin : Bank_addr_loop
for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
begin
bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
end
for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
begin
bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
begin
int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
end
else
begin
int_bank_addr[k] = 1'b0;
end
end
end
// Derive chipsel address from address
always @(*)
begin
m = 0;
if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
begin
for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
begin
if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
else
begin
int_cs_addr[m] = 1'b0;
end
end
end
else // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
begin
int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
end
end
//===================== end of address remapping =========================
//======================= burst splitting logic ===========================
assign cmd_gen_full = mux_busy | deassert_ready;
assign copy = ~cmd_gen_full & cmd_valid; // Copy current input command info into a register
assign require_gen = (cmd_size > native_size | unaligned_burst + cmd_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
// CSR address calculation
always @ (*)
begin
max_chip_from_csr = (2**cfg_cs_addr_width) - 1'b1;
max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
max_row_from_csr = (2**cfg_row_addr_width) - 1'b1;
max_col_from_csr = (2**cfg_col_addr_width) - 1'b1;
end
// Calculate native size for selected burstlength and controller rate
always @ (*)
begin
native_size = cfg_burst_length / CFG_DWIDTH_RATIO; // 1 for bl2 FR, 2 for bl8 HR, ...
end
always @(*)
begin
if (native_size == 1)
begin
unaligned_burst = 0;
end
else if (native_size == 2)
begin
unaligned_burst = {2'd0,int_col_addr[log2(CFG_DWIDTH_RATIO)]};
end
else if (native_size == 4)
begin
unaligned_burst = {1'd0,int_col_addr[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
end
else // native_size == 8
begin
unaligned_burst = int_col_addr[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
end
end
// Deassert local_ready signal because need to split local command into multiple memory commands
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
deassert_ready <= 0;
end
else
begin
if (copy && require_gen)
begin
deassert_ready <= 1;
end
else if ((buf_size > native_size*2) && cfg_enable_cmd_split)
begin
deassert_ready <= 1;
end
else if (generating && ~mux_busy)
begin
deassert_ready <= 0;
end
end
end
// Assert register signal so that we will pass split command into TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered <= 0;
end
else
begin
if (copy && require_gen)
begin
registered <= 1;
end
else
begin
registered <= 0;
end
end
end
// Generating signal will notify that current command in under splitting process
// Signal stays high until the last memory burst aligned command is generated
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
generating <= 0;
end
else
begin
if (registered)
begin
generating <= 1;
end
else if ((generating && buf_size > native_size*2) && cfg_enable_cmd_split)
begin
generating <= 1;
end
else if (~mux_busy)
begin
generating <= 0;
end
end
end
// Determine the correct size
always @(*)
begin
if (!generating)
begin
if ((unaligned_burst + cmd_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
begin
split_size = cmd_size;
end
else
begin
split_size = native_size - unaligned_burst;
end
end
else
begin
if (decrmntd_size > native_size - 1)
begin
split_size = native_size;
end
else
begin
split_size = decrmntd_size;
end
end
end
// MUX logic to determine where to take the command info from
always @(*)
begin
if (!generating) // not generating so take direct input from avalon if
begin
split_read = cmd_read & cmd_valid & ~registered;
split_write = cmd_write & cmd_valid & ~registered;
split_autopch = cmd_autoprecharge;
split_multicast = cmd_multicast;
split_priority = cmd_priority;
split_localid = cmd_id;
split_cs_addr = int_cs_addr;
split_bank_addr = int_bank_addr;
split_row_addr = int_row_addr;
split_col_addr = int_col_addr;
end
else // generating cmd so process buffer content
begin
split_read = buf_read_req;
split_write = buf_write_req;
split_autopch = buf_autopch_req;
split_multicast = buf_multicast;
split_priority = buf_priority;
split_localid = buf_localid;
split_cs_addr = incrmntd_cs_addr;
split_bank_addr = incrmntd_bank_addr;
split_row_addr = incrmntd_row_addr;
if (cfg_burst_length == 2)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1],1'b0};
end
else if (cfg_burst_length == 4)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2],2'b00};
end
else if (cfg_burst_length == 8)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3],3'b000};
end
else // if (cfg_burst_length == 16)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4],4'b0000};
end
end
end
// Buffered command info, to be used in split process
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
buf_priority <= 1'b0;
buf_localid <= 0;
end
else
begin
if (copy)
begin
buf_read_req <= cmd_read;
buf_write_req <= cmd_write;
buf_autopch_req <= cmd_autoprecharge;
buf_multicast <= cmd_multicast;
buf_priority <= cmd_priority;
buf_localid <= cmd_id;
end
end
end
// Keep track of command size during a split process
// will keep decreasing when a split command was sent to TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_size <= 0;
end
else
begin
if (copy)
begin
buf_size <= cmd_size + unaligned_burst;
end
else if (!registered && buf_size > native_size && ~mux_busy)
begin
buf_size <= buf_size - native_size;
end
end
end
always @(*)
begin
decrmntd_size = buf_size - native_size;
end
// Keep track of command address during a split process
// will keep increasing when a split command was sent to TBP
// also takes into account address order
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr;
buf_bank_addr <= int_bank_addr;
buf_row_addr <= int_row_addr;
buf_col_addr <= int_col_addr;
end
else if (registered || (generating && ~mux_busy))
if ((cfg_burst_length == 16 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
if (cfg_burst_length == 16)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] <= 0;
else if (cfg_burst_length == 8)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] <= 0;
else if (cfg_burst_length == 4)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] <= 0;
else // if (cfg_burst_length == 2)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] <= 0;
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
begin
buf_cs_addr <= 0;
if (buf_row_addr == max_row_from_csr)
buf_row_addr <= 0;
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
begin
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
end
else
buf_col_addr <= buf_col_addr + cfg_burst_length;
end
always @(*)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
end
//======================= end of burst splitting logic ===========================
//====================== ecc mux start ========================
// ECC process info
always @ (*)
begin
ecc_int_combi = ecc_int;
correct_combi = correct;
partial_combi = partial;
errcmd_ready_combi = errcmd_ready;
ecc_dataid_combi = ecc_dataid;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert partial after ECC write was sent to TBP
begin
partial_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (correct)
begin
errcmd_ready_combi = 1'b0;
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert correct after ECC write was sent to TBP
begin
correct_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // if there is a auto correction request
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b1;
partial_combi = 1'b0;
errcmd_ready_combi = 1'b1;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // if there is a write request in no-DM or ECC case
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b0;
partial_combi = 1'b1;
ecc_dataid_combi = wdatap_free_id_dataid;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int <= 0;
correct <= 0;
partial <= 0;
errcmd_ready <= 0;
ecc_dataid <= 0;
end
else
begin
ecc_int <= ecc_int_combi;
correct <= correct_combi;
partial <= partial_combi;
errcmd_ready <= errcmd_ready_combi;
ecc_dataid <= ecc_dataid_combi;
end
end
// Buffer for ECC command information
always @ (*)
begin
if (partial || correct)
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
else if (cfg_enable_ecc && errcmd_valid) // take in error command info
begin
ecc_cs_addr_combi = errcmd_chipsel;
ecc_bank_addr_combi = errcmd_bank;
ecc_row_addr_combi = errcmd_row;
ecc_col_addr_combi = errcmd_column;
ecc_size_combi = errcmd_size;
ecc_autopch_combi = 1'b0;
ecc_multicast_combi = 1'b0;
ecc_localid_combi = errcmd_localid;
ecc_priority_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // take in command info from split logic
begin
ecc_cs_addr_combi = split_cs_addr;
ecc_bank_addr_combi = split_bank_addr;
ecc_row_addr_combi = split_row_addr;
ecc_col_addr_combi = split_col_addr;
ecc_size_combi = split_size;
ecc_autopch_combi = split_autopch;
ecc_multicast_combi = split_multicast;
ecc_localid_combi = split_localid;
ecc_priority_combi = split_priority;
end
else
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_cs_addr <= 0;
ecc_bank_addr <= 0;
ecc_row_addr <= 0;
ecc_col_addr <= 0;
ecc_size <= 0;
ecc_autopch <= 0;
ecc_multicast <= 0;
ecc_localid <= 0;
ecc_priority <= 0;
end
else
begin
ecc_cs_addr <= ecc_cs_addr_combi;
ecc_bank_addr <= ecc_bank_addr_combi;
ecc_row_addr <= ecc_row_addr_combi;
ecc_col_addr <= ecc_col_addr_combi;
ecc_size <= ecc_size_combi;
ecc_autopch <= ecc_autopch_combi;
ecc_multicast <= ecc_multicast_combi;
ecc_localid <= ecc_localid_combi;
ecc_priority <= ecc_priority_combi;
end
end
// Logic to determine when to issue ECC read/write request
// based on partial_be info from wdata path
// if partial_be is high, it issues a read-modify-write command
// else issues normal write command
always @ (*)
begin
ecc_read_combi = ecc_read;
ecc_write_combi = ecc_write;
partial_opr_combi = partial_opr;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
partial_opr_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (data_complete[0]) // wait for data_complete from wdata path
begin
if (!data_partial_be) // if not partial_be, issues normal write
begin
ecc_write_combi = 1'b1;
end
else // else issues a RMW's read
begin
ecc_read_combi = 1'b1;
partial_opr_combi = 1'b1;
end
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
begin
ecc_write_combi = 1'b1;
end
else
begin
ecc_write_combi = 1'b0;
end
end
end
else if (correct)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
ecc_write_combi = 1'b1;
else
ecc_write_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // issues a RMW's read when there is a error correction
begin
ecc_read_combi = 1'b1;
ecc_write_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy)
begin
ecc_read_combi = 1'b0;
ecc_write_combi = 1'b0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_read <= 1'b0;
ecc_write <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_read <= ecc_read_combi;
ecc_write <= ecc_write_combi;
partial_opr <= partial_opr_combi;
end
end
// We only need to gate split_read/write in non cmd_gen registered output mode
assign mux_busy = (
queue_full |
errcmd_valid |
(
(cfg_enable_no_dm | cfg_enable_ecc) &
(
ecc_int |
(
!(CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE) &
(
(split_read & ~rdatap_free_id_valid) |
(split_write & ~wdatap_free_id_valid)
)
)
)
)
);
assign muxed_cs_addr = ecc_int ? ecc_cs_addr : split_cs_addr;
assign muxed_bank_addr = ecc_int ? ecc_bank_addr : split_bank_addr;
assign muxed_row_addr = ecc_int ? ecc_row_addr : split_row_addr;
assign muxed_col_addr = ecc_int ? ecc_col_addr : split_col_addr;
assign muxed_read = ecc_int ? (CFG_CMD_GEN_OUTPUT_REG ? (ecc_read & rdatap_free_id_valid) : ecc_read) : split_read & ~errcmd_valid; // We only need to check for free ID valid in CMD_GEN_OUTPUT_REG mode
assign muxed_write = (cfg_enable_no_dm || cfg_enable_ecc) ? ecc_write : split_write & ~errcmd_valid;
assign muxed_size = ecc_int ? ecc_size : split_size;
assign muxed_autopch = ecc_int ? ecc_autopch : split_autopch;
assign muxed_multicast = ecc_int ? ecc_multicast : split_multicast;
assign muxed_localid = ecc_int ? ecc_localid : split_localid;
assign muxed_priority = ecc_int ? ecc_priority : split_priority;
assign muxed_dataid = ecc_int ? ecc_dataid : rdatap_free_id_dataid;
assign muxed_complete = ecc_int ? 1'b1 : split_read;
assign muxed_correct = ecc_int ? correct : 1'b0;
assign muxed_partial = ecc_int ? partial_opr : 1'b0;
assign muxed_same_chipsel_addr = ecc_int_r ? ecc_same_chipsel_addr : split_same_chipsel_addr;
assign muxed_same_bank_addr = ecc_int_r ? ecc_same_bank_addr : split_same_bank_addr;
assign muxed_same_row_addr_0 = ecc_int_r ? ecc_same_row_addr_0 : split_same_row_addr_0;
assign muxed_same_row_addr_1 = ecc_int_r ? ecc_same_row_addr_1 : split_same_row_addr_1;
assign muxed_same_row_addr_2 = ecc_int_r ? ecc_same_row_addr_2 : split_same_row_addr_2;
assign muxed_same_row_addr_3 = ecc_int_r ? ecc_same_row_addr_3 : split_same_row_addr_3;
assign muxed_same_col_addr = ecc_int_r ? ecc_same_col_addr : split_same_col_addr;
assign muxed_same_read_cmd = ecc_int_r ? ecc_same_read_cmd : split_same_read_cmd;
assign muxed_same_write_cmd = ecc_int_r ? ecc_same_write_cmd : split_same_write_cmd;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int_r <= 1'b0;
end
else
begin
ecc_int_r <= ecc_int;
end
end
// Address comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (split_cs_addr == chipsel[j])
begin
split_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
split_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (split_bank_addr == bank[j])
begin
split_same_bank_addr_combi[j] = 1'b1;
end
else
begin
split_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (split_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_0_combi[j] = 1'b0;
end
if (split_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_1_combi[j] = 1'b0;
end
if (split_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_2_combi[j] = 1'b0;
end
if (split_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (split_col_addr == col[j])
begin
split_same_col_addr_combi[j] = 1'b1;
end
else
begin
split_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (split_read == read[j])
begin
split_same_read_cmd_combi[j] = 1'b1;
end
else
begin
split_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (split_write == write[j])
begin
split_same_write_cmd_combi[j] = 1'b1;
end
else
begin
split_same_write_cmd_combi[j] = 1'b0;
end
end
end
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (ecc_cs_addr == chipsel[j])
begin
ecc_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (ecc_bank_addr == bank[j])
begin
ecc_same_bank_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (ecc_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_0_combi[j] = 1'b0;
end
if (ecc_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_1_combi[j] = 1'b0;
end
if (ecc_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_2_combi[j] = 1'b0;
end
if (ecc_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (ecc_col_addr == col[j])
begin
ecc_same_col_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (ecc_read == read[j])
begin
ecc_same_read_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (ecc_write == write[j])
begin
ecc_same_write_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_write_cmd_combi[j] = 1'b0;
end
end
end
generate
if (CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE)
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
proc_write_sig <= 0;
proc_read_sig <= 0;
proc_size_sig <= 0;
proc_localid_sig <= 0;
proc_load_dataid_sig <= 0;
proc_ecc_busy_sig <= 0;
end
else
begin
if (proc_busy_sig)
begin
// Do nothing, keep old value
end
else
begin
proc_load_dataid_sig <= ~(ecc_int & (ecc_read | ecc_write));
if (ecc_int)
begin
proc_write_sig <= ecc_write & correct;
proc_read_sig <= ecc_read;
proc_size_sig <= ecc_size;
proc_localid_sig <= ecc_localid;
proc_ecc_busy_sig <= (ecc_read & ~rdatap_free_id_valid) | ((ecc_write & correct) & ~wdatap_free_id_valid);
end
else
begin
proc_write_sig <= split_write & ~errcmd_valid;
proc_read_sig <= split_read & ~errcmd_valid;
proc_size_sig <= split_size;
proc_localid_sig <= split_localid;
proc_ecc_busy_sig <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_same_chipsel_addr <= 0;
split_same_bank_addr <= 0;
split_same_row_addr_0 <= 0;
split_same_row_addr_1 <= 0;
split_same_row_addr_2 <= 0;
split_same_row_addr_3 <= 0;
split_same_col_addr <= 0;
split_same_read_cmd <= 0;
split_same_write_cmd <= 0;
ecc_same_chipsel_addr <= 0;
ecc_same_bank_addr <= 0;
ecc_same_row_addr_0 <= 0;
ecc_same_row_addr_1 <= 0;
ecc_same_row_addr_2 <= 0;
ecc_same_row_addr_3 <= 0;
ecc_same_col_addr <= 0;
ecc_same_read_cmd <= 0;
ecc_same_write_cmd <= 0;
end
else
begin
split_same_chipsel_addr <= split_same_chipsel_addr_combi;
split_same_bank_addr <= split_same_bank_addr_combi;
split_same_row_addr_0 <= split_same_row_addr_0_combi;
split_same_row_addr_1 <= split_same_row_addr_1_combi;
split_same_row_addr_2 <= split_same_row_addr_2_combi;
split_same_row_addr_3 <= split_same_row_addr_3_combi;
split_same_col_addr <= split_same_col_addr_combi;
split_same_read_cmd <= split_same_read_cmd_combi;
split_same_write_cmd <= split_same_write_cmd_combi;
ecc_same_chipsel_addr <= ecc_same_chipsel_addr_combi;
ecc_same_bank_addr <= ecc_same_bank_addr_combi;
ecc_same_row_addr_0 <= ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 <= ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 <= ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 <= ecc_same_row_addr_3_combi;
ecc_same_col_addr <= ecc_same_col_addr_combi;
ecc_same_read_cmd <= ecc_same_read_cmd_combi;
ecc_same_write_cmd <= ecc_same_write_cmd_combi;
end
end
end
else
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_ecc_busy_sig = zero;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
proc_load_dataid_sig = ~(ecc_int & (ecc_read | ecc_write));
proc_write_sig = ecc_int ? ecc_write & correct : split_write & ~errcmd_valid;
proc_read_sig = ecc_int ? ecc_read : split_read & ~errcmd_valid;
proc_size_sig = ecc_int ? ecc_size : split_size;
proc_localid_sig = ecc_int ? ecc_localid : split_localid;
end
always @ (*)
begin
split_same_chipsel_addr = split_same_chipsel_addr_combi;
split_same_bank_addr = split_same_bank_addr_combi;
split_same_row_addr_0 = split_same_row_addr_0_combi;
split_same_row_addr_1 = split_same_row_addr_1_combi;
split_same_row_addr_2 = split_same_row_addr_2_combi;
split_same_row_addr_3 = split_same_row_addr_3_combi;
split_same_col_addr = split_same_col_addr_combi;
split_same_read_cmd = split_same_read_cmd_combi;
split_same_write_cmd = split_same_write_cmd_combi;
ecc_same_chipsel_addr = ecc_same_chipsel_addr_combi;
ecc_same_bank_addr = ecc_same_bank_addr_combi;
ecc_same_row_addr_0 = ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 = ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 = ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 = ecc_same_row_addr_3_combi;
ecc_same_col_addr = ecc_same_col_addr_combi;
ecc_same_read_cmd = ecc_same_read_cmd_combi;
ecc_same_write_cmd = ecc_same_write_cmd_combi;
end
end
endgenerate
//====================== ecc mux end ========================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n)
begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last_read_req <= muxed_read;
last_write_req <= muxed_write;
last_multicast <= muxed_multicast;
last_chip_addr <= muxed_cs_addr;
last_bank_addr <= muxed_bank_addr;
last_row_addr <= muxed_row_addr;
last_col_addr <= muxed_col_addr;
last_size <= muxed_size;
end
else if (can_merge)
begin
last_size <= 2;
end
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last2_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
if (write_to_queue)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (write_to_queue) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
// do nothing
end
else if (!queue_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
// Merging logic
assign can_merge = (CFG_ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3]) )
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// mapping of buffer_input
assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
generate
if (CFG_ENABLE_QUEUE == 1)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
// TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr = muxed_same_row_addr_0 & muxed_same_row_addr_1 & muxed_same_row_addr_2 & muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
// Chipselect address
if (cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
assign queue_empty = !pipefull[0];
assign queue_full = pipefull[CFG_CTL_QUEUE_DEPTH-1] | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
assign cmd_gen_load = pipefull[0] & ((cfg_enable_no_dm | cfg_enable_ecc) | ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid)));
assign cmd_gen_read = pipe[0][BUFFER_WIDTH-1];
assign cmd_gen_write = pipe[0][BUFFER_WIDTH-2];
assign cmd_gen_multicast = pipe[0][BUFFER_WIDTH-3];
assign cmd_gen_autopch = pipe[0][BUFFER_WIDTH-4];
assign cmd_gen_priority = pipe[0][BUFFER_WIDTH-5];
assign cmd_gen_complete = pipe[0][BUFFER_WIDTH-6];
assign cmd_gen_rmw_correct = pipe[0][BUFFER_WIDTH-7];
assign cmd_gen_rmw_partial = pipe[0][BUFFER_WIDTH-8];
assign cmd_gen_dataid = cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid;
assign cmd_gen_localid = pipe[0][CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_size = pipe[0][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_chipsel = pipe[0][CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_row = pipe[0][CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_bank = pipe[0][CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_col = pipe[0][CFG_MEM_IF_COL_WIDTH - 1 : 0];
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
else
begin
wire int_queue_full;
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
reg int_register_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cmd_gen_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_cmd_gen_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_cmd_gen_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_cmd_gen_col;
reg int_cmd_gen_write;
reg int_cmd_gen_read;
reg int_cmd_gen_multicast;
reg [CFG_INT_SIZE_WIDTH-1:0] int_cmd_gen_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_cmd_gen_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid;
reg int_cmd_gen_priority;
reg int_cmd_gen_rmw_correct;
reg int_cmd_gen_rmw_partial;
reg int_cmd_gen_autopch;
reg int_cmd_gen_complete;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid_mux;
// TBP address and command comparison logic
always @ (*)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr_0 = muxed_same_row_addr_0;
int_same_row_addr_1 = muxed_same_row_addr_1;
int_same_row_addr_2 = muxed_same_row_addr_2;
int_same_row_addr_3 = muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (int_queue_full)
begin
// Chipselect address
if (int_cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
else
begin
// Chipselect address
if (muxed_cs_addr == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (muxed_bank_addr == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (muxed_row_addr == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
end
if (CFG_CMD_GEN_OUTPUT_REG)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr_r;
reg int_ecc_int;
reg int_queue_full_r;
assign int_queue_full = (tbp_full & int_register_valid) | ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid));
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_queue_full_r <= 1'b0;
end
else
begin
int_queue_full_r <= int_queue_full;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 0;
int_cmd_gen_write <= 0;
int_cmd_gen_multicast <= 0;
int_cmd_gen_autopch <= 0;
int_cmd_gen_priority <= 0;
int_cmd_gen_complete <= 0;
int_cmd_gen_rmw_correct <= 0;
int_cmd_gen_rmw_partial <= 0;
int_cmd_gen_dataid <= 0;
int_cmd_gen_localid <= 0;
int_cmd_gen_size <= 0;
int_cmd_gen_chipsel <= 0;
int_cmd_gen_row <= 0;
int_cmd_gen_bank <= 0;
int_cmd_gen_col <= 0;
int_ecc_int <= 0;
end
else
begin
if (fetch)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 1'b0;
int_cmd_gen_write <= 1'b0;
end
if (!int_queue_full)
begin
if (muxed_read || muxed_write)
begin
int_register_valid <= 1'b1;
end
int_cmd_gen_read <= muxed_read;
int_cmd_gen_write <= muxed_write;
int_cmd_gen_multicast <= muxed_multicast;
int_cmd_gen_autopch <= muxed_autopch;
int_cmd_gen_priority <= muxed_priority;
int_cmd_gen_complete <= muxed_complete;
int_cmd_gen_rmw_correct <= muxed_correct;
int_cmd_gen_rmw_partial <= muxed_partial;
int_cmd_gen_dataid <= muxed_dataid;
int_cmd_gen_localid <= muxed_localid;
int_cmd_gen_size <= muxed_size;
int_cmd_gen_chipsel <= muxed_cs_addr;
int_cmd_gen_row <= muxed_row_addr;
int_cmd_gen_bank <= muxed_bank_addr;
int_cmd_gen_col <= muxed_col_addr;
int_ecc_int <= ecc_int;
end
end
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_ecc_int ? int_cmd_gen_dataid : rdatap_free_id_dataid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_same_chipsel_addr_r <= 0;
int_same_bank_addr_r <= 0;
int_same_row_addr_0_r <= 0;
int_same_row_addr_1_r <= 0;
int_same_row_addr_2_r <= 0;
int_same_row_addr_3_r <= 0;
int_same_col_addr_r <= 0;
int_same_read_cmd_r <= 0;
int_same_write_cmd_r <= 0;
int_same_shadow_chipsel_addr_r <= 0;
int_same_shadow_bank_addr_r <= 0;
int_same_shadow_row_addr_r <= 0;
end
else
begin
if (int_queue_full & !int_queue_full_r) // positive edge detector
begin
int_same_chipsel_addr_r <= int_same_chipsel_addr;
int_same_bank_addr_r <= int_same_bank_addr;
int_same_row_addr_0_r <= int_same_row_addr_0;
int_same_row_addr_1_r <= int_same_row_addr_1;
int_same_row_addr_2_r <= int_same_row_addr_2;
int_same_row_addr_3_r <= int_same_row_addr_3;
int_same_col_addr_r <= int_same_col_addr;
int_same_read_cmd_r <= int_same_read_cmd;
int_same_write_cmd_r <= int_same_write_cmd;
end
int_same_shadow_chipsel_addr_r <= int_same_shadow_chipsel_addr;
int_same_shadow_bank_addr_r <= int_same_shadow_bank_addr;
int_same_shadow_row_addr_r <= int_same_shadow_row_addr;
end
end
always @ (*)
begin
if (!int_queue_full_r)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
end
else
begin
same_chipsel_addr = int_same_chipsel_addr_r;
same_bank_addr = int_same_bank_addr_r;
same_row_addr = int_same_row_addr_0_r & int_same_row_addr_1_r & int_same_row_addr_2_r & int_same_row_addr_3_r;
same_col_addr = int_same_col_addr_r;
same_read_cmd = int_same_read_cmd_r;
same_write_cmd = int_same_write_cmd_r;
end
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr_r;
same_shadow_bank_addr = int_same_shadow_bank_addr_r;
same_shadow_row_addr = int_same_shadow_row_addr_r;
end
end
else
begin
assign int_queue_full = tbp_full | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
always @ (*)
begin
int_register_valid = one;
int_cmd_gen_read = muxed_read;
int_cmd_gen_write = muxed_write;
int_cmd_gen_multicast = muxed_multicast;
int_cmd_gen_autopch = muxed_autopch;
int_cmd_gen_priority = muxed_priority;
int_cmd_gen_complete = muxed_complete;
int_cmd_gen_rmw_correct = muxed_correct;
int_cmd_gen_rmw_partial = muxed_partial;
int_cmd_gen_dataid = muxed_dataid;
int_cmd_gen_localid = muxed_localid;
int_cmd_gen_size = muxed_size;
int_cmd_gen_chipsel = muxed_cs_addr;
int_cmd_gen_row = muxed_row_addr;
int_cmd_gen_bank = muxed_bank_addr;
int_cmd_gen_col = muxed_col_addr;
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_cmd_gen_dataid;
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
end
assign queue_empty = 1;
assign queue_full = int_queue_full;
assign cmd_gen_load = (cmd_gen_read | cmd_gen_write) & ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid));
assign cmd_gen_read = int_cmd_gen_read;
assign cmd_gen_write = int_cmd_gen_write;
assign cmd_gen_multicast = int_cmd_gen_multicast;
assign cmd_gen_autopch = int_cmd_gen_autopch;
assign cmd_gen_priority = int_cmd_gen_priority;
assign cmd_gen_complete = int_cmd_gen_complete;
assign cmd_gen_rmw_correct = int_cmd_gen_rmw_correct;
assign cmd_gen_rmw_partial = int_cmd_gen_rmw_partial;
assign cmd_gen_dataid = (cfg_enable_no_dm || cfg_enable_ecc) ? int_cmd_gen_dataid_mux : (cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
assign cmd_gen_localid = int_cmd_gen_localid;
assign cmd_gen_size = int_cmd_gen_size;
assign cmd_gen_chipsel = int_cmd_gen_chipsel;
assign cmd_gen_row = int_cmd_gen_row;
assign cmd_gen_bank = int_cmd_gen_bank;
assign cmd_gen_col = int_cmd_gen_col;
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
endgenerate
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
assign fetch = cmd_gen_load & ~tbp_full;
// proc signals to datapath
assign proc_busy = (cfg_enable_no_dm || cfg_enable_ecc) ? (proc_busy_sig | proc_ecc_busy_sig) : tbp_full;
assign proc_load = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_sig : cmd_gen_load;
assign proc_load_dataid= (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_dataid_sig : cmd_gen_load;
assign proc_write = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_write_sig : cmd_gen_write;
assign proc_read = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_read_sig : cmd_gen_read;
assign proc_size = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_size_sig : cmd_gen_size;
assign proc_localid = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_localid_sig : cmd_gen_localid;
assign tbp_load_index = (cfg_enable_no_dm || cfg_enable_ecc) ? 1 : tbp_load;
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
pipefull[j] <= 1'b0;
pipe [j] <= 0;
end
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else if (j == last_minus_two)
begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe[CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
begin
pipefull[j] <= 1'b1;
pipe [j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0)
begin
pipefull[0] <= 1'b1;
pipe [0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else
begin
pipefull[j] <= pipefull[j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
end
end
//============================ end of queue ===============================
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module reset(
// -- raw
input core_clk,
input sample_clk,
input sd_clk,
input usb_clk,
input sys_rst,
input sys_clr,
// -- sync
output core_rst,
output sample_rst,
output sd_rst,
output sdram_rst_,
output cfg_rst,
output usb_rst
);
wire clr_rst;
assign clr_rst = sys_rst | sys_clr;
// --
// core reset sync & stretch
// --
reg [3:0] core_rst_reg;
wire [3:0] core_rst_reg_nxt;
assign core_rst = core_rst_reg[3];
assign core_rst_reg_nxt = {core_rst_reg[2:0], 1'b0};
always @(posedge core_clk or posedge clr_rst)
begin
if (clr_rst)
core_rst_reg <= `D 4'b1111;
else
core_rst_reg <= `D core_rst_reg_nxt;
end
// --
// sample reset sync & stretch
// --
reg [17:0] sample_rst_reg;
wire [17:0] sample_rst_reg_nxt;
assign sample_rst = sample_rst_reg[17];
assign sample_rst_reg_nxt = {sample_rst_reg[16:0], 1'b0};
always @(posedge sample_clk or posedge clr_rst)
begin
if (clr_rst)
sample_rst_reg <= `D 18'b111111111111111111;
else
sample_rst_reg <= `D sample_rst_reg_nxt;
end
// --
// dwrite/dread reset sync & stretch
// --
reg [3:0] sd_rst_reg;
wire [3:0] sd_rst_reg_nxt;
assign sd_rst = sd_rst_reg[3];
assign sd_rst_reg_nxt = {sd_rst_reg[2:0], 1'b0};
always @(posedge sd_clk or posedge clr_rst)
begin
if (clr_rst)
sd_rst_reg <= `D 4'b1111;
else
sd_rst_reg <= `D sd_rst_reg_nxt;
end
// --
// sdram controller reset sync & stretch
// --
reg [3:0] sdram_rst_reg = 4'b0;
wire [3:0] sdram_rst_reg_nxt;
assign sdram_rst_ = sdram_rst_reg[3];
assign sdram_rst_reg_nxt = {sdram_rst_reg[2:0], 1'b1};
always @(posedge sd_clk)
begin
sdram_rst_reg <= `D sdram_rst_reg_nxt;
end
// --
// cfg reset sync & stretch
// --
reg [3:0] cfg_rst_reg;
wire [3:0] cfg_rst_reg_nxt;
assign cfg_rst = cfg_rst_reg[3];
assign cfg_rst_reg_nxt = {cfg_rst_reg[2:0], 1'b0};
always @(posedge usb_clk or posedge sys_rst)
begin
if (sys_rst)
cfg_rst_reg <= `D 4'b1111;
else
cfg_rst_reg <= `D cfg_rst_reg_nxt;
end
// --
// usb controller reset sync & stretch
// --
reg [3:0] usb_rst_reg;
wire [3:0] usb_rst_reg_nxt;
assign usb_rst = usb_rst_reg[3];
assign usb_rst_reg_nxt = {usb_rst_reg[2:0], 1'b0};
always @(posedge usb_clk or posedge clr_rst)
begin
if (clr_rst)
usb_rst_reg <= `D 4'b1111;
else
usb_rst_reg <= `D usb_rst_reg_nxt;
end
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/counter.v:1" *)
module Counter(Reset_n_i, Clk_i, ResetSig_i, Preset_i, Enable_i, Direction_i, PresetVal_i, D_o, Overflow_o, Zero_o);
(* src = "../../verilog/counter.v:28" *)
wire [16:0] \$0\Value[16:0] ;
(* src = "../../verilog/counter.v:43" *)
wire [16:0] \$add$../../verilog/counter.v:43$4_Y ;
wire [16:0] \$procmux$22_Y ;
wire [16:0] \$procmux$24_Y ;
wire [16:0] \$procmux$27_Y ;
(* src = "../../verilog/counter.v:45" *)
wire [16:0] \$sub$../../verilog/counter.v:45$5_Y ;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/counter.v:7" *)
input Clk_i;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/counter.v:19" *)
output [15:0] D_o;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter.v:15" *)
input Direction_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter.v:13" *)
input Enable_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter.v:21" *)
output Overflow_o;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/counter.v:17" *)
input [15:0] PresetVal_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter.v:11" *)
input Preset_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter.v:9" *)
input ResetSig_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/counter.v:5" *)
input Reset_n_i;
(* src = "../../verilog/counter.v:26" *)
wire [16:0] Value;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter.v:23" *)
output Zero_o;
(* src = "../../verilog/counter.v:43" *)
\$add #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$add$../../verilog/counter.v:43$4 (
.A({ 1'b0, Value[15:0] }),
.B(1'b1),
.Y(\$add$../../verilog/counter.v:43$4_Y )
);
(* src = "../../verilog/counter.v:52" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/counter.v:52$6 (
.A(Value[15:0]),
.B(16'b0000000000000000),
.Y(Zero_o)
);
(* src = "../../verilog/counter.v:28" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(17'b00000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010001)
) \$procdff$62 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Value[16:0] ),
.Q(Value)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010001)
) \$procmux$22 (
.A(\$add$../../verilog/counter.v:43$4_Y ),
.B(\$sub$../../verilog/counter.v:45$5_Y ),
.S(Direction_i),
.Y(\$procmux$22_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010001)
) \$procmux$24 (
.A(Value),
.B(\$procmux$22_Y ),
.S(Enable_i),
.Y(\$procmux$24_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010001)
) \$procmux$27 (
.A(\$procmux$24_Y ),
.B({ 1'b0, PresetVal_i }),
.S(Preset_i),
.Y(\$procmux$27_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010001)
) \$procmux$30 (
.A(\$procmux$27_Y ),
.B(17'b00000000000000000),
.S(ResetSig_i),
.Y(\$0\Value[16:0] )
);
(* src = "../../verilog/counter.v:45" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/counter.v:45$5 (
.A({ 1'b0, Value[15:0] }),
.B(1'b1),
.Y(\$sub$../../verilog/counter.v:45$5_Y )
);
assign D_o = Value[15:0];
assign Overflow_o = Value[16];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// counters
int cnt;
int cnt_bit ;
int cnt_byte;
int cnt_int ;
int cnt_ar1d;
int cnt_ar2d;
// sizes
int siz_bit ;
int siz_byte;
int siz_int ;
int siz_ar1d;
int siz_ar2d;
// add all counters
assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d;
// finish report
always @ (posedge clk)
if (cnt == 5) begin
if (siz_bit != 1) $stop();
if (siz_byte != 8) $stop();
if (siz_int != 32) $stop();
if (siz_ar1d != 24) $stop();
if (siz_ar2d != 16) $stop();
end else if (cnt > 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
// instances with various types
mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit );
mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte);
mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int );
mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d);
mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d);
endmodule : t
module mod_typ #(
parameter type TYP = byte
)(
input logic clk,
output TYP cnt = 0,
output int siz
);
always @ (posedge clk)
cnt <= cnt + 1;
assign siz = $bits (cnt);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:01 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_sim_netlist.v
// Design : RAT_Mux4x1_10_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Mux4x1_10_0_0,Mux4x1_10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Mux4x1_10,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Mux4x1_10_0_0
(A,
B,
C,
D,
SEL,
X);
input [9:0]A;
input [9:0]B;
input [9:0]C;
input [9:0]D;
input [1:0]SEL;
output [9:0]X;
wire [9:0]A;
wire [9:0]B;
wire [9:0]C;
wire [9:0]D;
wire [1:0]SEL;
wire [9:0]X;
RAT_Mux4x1_10_0_0_Mux4x1_10 U0
(.A(A),
.B(B),
.C(C),
.D(D),
.SEL(SEL),
.X(X));
endmodule
(* ORIG_REF_NAME = "Mux4x1_10" *)
module RAT_Mux4x1_10_0_0_Mux4x1_10
(X,
D,
B,
C,
SEL,
A);
output [9:0]X;
input [9:0]D;
input [9:0]B;
input [9:0]C;
input [1:0]SEL;
input [9:0]A;
wire [9:0]A;
wire [9:0]B;
wire [9:0]C;
wire [9:0]D;
wire [1:0]SEL;
wire [9:0]X;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[0]_INST_0
(.I0(D[0]),
.I1(B[0]),
.I2(C[0]),
.I3(SEL[1]),
.I4(A[0]),
.I5(SEL[0]),
.O(X[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[1]_INST_0
(.I0(D[1]),
.I1(B[1]),
.I2(C[1]),
.I3(SEL[1]),
.I4(A[1]),
.I5(SEL[0]),
.O(X[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[2]_INST_0
(.I0(D[2]),
.I1(B[2]),
.I2(C[2]),
.I3(SEL[1]),
.I4(A[2]),
.I5(SEL[0]),
.O(X[2]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[3]_INST_0
(.I0(D[3]),
.I1(B[3]),
.I2(C[3]),
.I3(SEL[1]),
.I4(A[3]),
.I5(SEL[0]),
.O(X[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[4]_INST_0
(.I0(D[4]),
.I1(B[4]),
.I2(C[4]),
.I3(SEL[1]),
.I4(A[4]),
.I5(SEL[0]),
.O(X[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[5]_INST_0
(.I0(D[5]),
.I1(B[5]),
.I2(C[5]),
.I3(SEL[1]),
.I4(A[5]),
.I5(SEL[0]),
.O(X[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[6]_INST_0
(.I0(D[6]),
.I1(B[6]),
.I2(C[6]),
.I3(SEL[1]),
.I4(A[6]),
.I5(SEL[0]),
.O(X[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[7]_INST_0
(.I0(D[7]),
.I1(B[7]),
.I2(C[7]),
.I3(SEL[1]),
.I4(A[7]),
.I5(SEL[0]),
.O(X[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[8]_INST_0
(.I0(D[8]),
.I1(B[8]),
.I2(C[8]),
.I3(SEL[1]),
.I4(A[8]),
.I5(SEL[0]),
.O(X[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[9]_INST_0
(.I0(D[9]),
.I1(B[9]),
.I2(C[9]),
.I3(SEL[1]),
.I4(A[9]),
.I5(SEL[0]),
.O(X[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPADV2_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPADV2_BLACKBOX_V
/**
* top_power_hvc_wpadv2: A power pad with an ESD high-voltage clamp.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpadv2 (
P_PAD ,
AMUXBUS_A,
AMUXBUS_B
);
inout P_PAD ;
inout AMUXBUS_A;
inout AMUXBUS_B;
// Voltage supply signals
supply1 OGC_HVC ;
supply1 DRN_HVC ;
supply0 SRC_BDY_HVC;
supply1 P_CORE ;
supply1 VDDIO ;
supply1 VDDIO_Q ;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH ;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q ;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPADV2_BLACKBOX_V
|
module instruction_arbiter
(/*AUTOARG*/
// Outputs
simd0_alu_select, simd1_alu_select, simd2_alu_select,
simd3_alu_select, simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select, lsu_lsu_select,
salu_alu_select, lsu_wfid, alu_wfid, issued_wfid, alu_valid,
lsu_valid, issued_valid,
// Inputs
clk, rst, salu_ready_to_issue, simd_ready_to_issue,
simf_ready_to_issue, lsu_ready_to_issue, simd0_alu_ready,
simd1_alu_ready, simd2_alu_ready, simd3_alu_ready, simf0_alu_ready,
simf1_alu_ready, simf2_alu_ready, simf3_alu_ready, salu_alu_ready,
lsu_ready
);
input clk, rst;
input [`WF_PER_CU-1:0] salu_ready_to_issue, simd_ready_to_issue,
simf_ready_to_issue, lsu_ready_to_issue;
input simd0_alu_ready, simd1_alu_ready,
simd2_alu_ready, simd3_alu_ready,
simf0_alu_ready, simf1_alu_ready,
simf2_alu_ready, simf3_alu_ready,
salu_alu_ready, lsu_ready;
output simd0_alu_select, simd1_alu_select,
simd2_alu_select, simd3_alu_select,
simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select,
lsu_lsu_select, salu_alu_select;
output [`WF_ID_LENGTH-1:0] lsu_wfid, alu_wfid, issued_wfid;
output alu_valid, lsu_valid, issued_valid;
wire [`WF_PER_CU-1:0] c_issued_arry, issued_arry, inegible_wf_arry;
wire [`WF_PER_CU-1:0] f_salu_ready_to_issue, f_simd_ready_to_issue,
f_simf_ready_to_issue, f_lsu_ready_to_issue;
wire f_simd0_alu_ready, f_simd1_alu_ready,
f_simd2_alu_ready, f_simd3_alu_ready,
f_simf0_alu_ready, f_simf1_alu_ready,
f_simf2_alu_ready, f_simf3_alu_ready,
f_salu_alu_ready, f_lsu_ready;
wire c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select;
wire c_issued_valid;
wire [`WF_ID_LENGTH-1:0] c_issued_wfid;
decoder_6b_40b_en c_issued_decoder
(.addr_in(c_issued_wfid),
.en(c_issued_valid),
.out(c_issued_arry)
);
decoder_6b_40b_en issued_decoder
(.addr_in(issued_wfid),
.en(issued_valid),
.out(issued_arry)
);
// Hack: make sure the wf that are being chosen right now and the one
// that was chosen last cycle are not issued.
assign inegible_wf_arry = c_issued_arry | issued_arry;
dff input_flops[(40*4 + 10)-1:0]
(.d({salu_ready_to_issue & ~inegible_wf_arry, simd_ready_to_issue & ~inegible_wf_arry,
simf_ready_to_issue & ~inegible_wf_arry, lsu_ready_to_issue & ~inegible_wf_arry,
simd0_alu_ready & ~simd0_alu_select & ~c_simd0_alu_select,
simd1_alu_ready & ~simd1_alu_select & ~c_simd1_alu_select ,
simd2_alu_ready & ~simd2_alu_select & ~c_simd2_alu_select,
simd3_alu_ready & ~simd3_alu_select & ~c_simd3_alu_select,
simf0_alu_ready & ~simf0_alu_select & ~c_simf0_alu_select,
simf1_alu_ready & ~simf1_alu_select & ~c_simf1_alu_select,
simf2_alu_ready & ~simf2_alu_select & ~c_simf2_alu_select,
simf3_alu_ready & ~simf3_alu_select & ~c_simf3_alu_select,
salu_alu_ready & ~salu_alu_select & ~c_salu_alu_select,
lsu_ready & ~lsu_lsu_select & ~c_lsu_lsu_select}),
.q({f_salu_ready_to_issue, f_simd_ready_to_issue,
f_simf_ready_to_issue, f_lsu_ready_to_issue,
f_simd0_alu_ready, f_simd1_alu_ready,
f_simd2_alu_ready, f_simd3_alu_ready,
f_simf0_alu_ready, f_simf1_alu_ready,
f_simf2_alu_ready, f_simf3_alu_ready,
f_salu_alu_ready, f_lsu_ready}),
.clk(clk),
.rst(rst));
dff output_flops[(6*1 + 11)-1:0]
(.d({c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select,
c_issued_wfid,
c_issued_valid}),
.q({simd0_alu_select, simd1_alu_select,
simd2_alu_select, simd3_alu_select,
simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select,
lsu_lsu_select, salu_alu_select,
issued_wfid,
issued_valid}),
.clk(clk),
.rst(rst));
wire lsu_wf_valid, salu_wf_valid, simd_wf_valid, simf_wf_valid;
wire [`WF_ID_LENGTH-1:0] lsu_wf_chosen, salu_wf_choosen, simd_wf_choosen, simf_wf_choosen;
arbiter lsu_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_lsu_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(lsu_wf_valid),
.choosen_wf_id(lsu_wf_chosen)
);
arbiter salu_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_salu_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(salu_wf_valid),
.choosen_wf_id(salu_wf_choosen)
);
arbiter simd_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_simd_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(simd_wf_valid),
.choosen_wf_id(simd_wf_choosen)
);
arbiter simf_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_simf_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(simf_wf_valid),
.choosen_wf_id(simf_wf_choosen)
);
alu_issue_logic alu_issue_logic
(/*AUTOINST*/
// Outputs
.c_issued_valid (c_issued_valid),
.c_simd0_alu_select (c_simd0_alu_select),
.c_simd1_alu_select (c_simd1_alu_select),
.c_simd2_alu_select (c_simd2_alu_select),
.c_simd3_alu_select (c_simd3_alu_select),
.c_simf0_alu_select (c_simf0_alu_select),
.c_simf1_alu_select (c_simf1_alu_select),
.c_simf2_alu_select (c_simf2_alu_select),
.c_simf3_alu_select (c_simf3_alu_select),
.c_lsu_lsu_select (c_lsu_lsu_select),
.c_salu_alu_select (c_salu_alu_select),
.c_issued_wfid (c_issued_wfid[`WF_ID_LENGTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.f_lsu_ready (f_lsu_ready),
.f_salu_alu_ready (f_salu_alu_ready),
.f_simf3_alu_ready (f_simf3_alu_ready),
.f_simf2_alu_ready (f_simf2_alu_ready),
.f_simf1_alu_ready (f_simf1_alu_ready),
.f_simf0_alu_ready (f_simf0_alu_ready),
.f_simd3_alu_ready (f_simd3_alu_ready),
.f_simd2_alu_ready (f_simd2_alu_ready),
.f_simd1_alu_ready (f_simd1_alu_ready),
.f_simd0_alu_ready (f_simd0_alu_ready),
.lsu_wf_valid (lsu_wf_valid),
.simd_wf_valid (simd_wf_valid),
.simf_wf_valid (simf_wf_valid),
.salu_wf_valid (salu_wf_valid),
.lsu_wf_chosen (lsu_wf_chosen[`WF_ID_LENGTH-1:0]),
.simd_wf_choosen (simd_wf_choosen[`WF_ID_LENGTH-1:0]),
.simf_wf_choosen (simf_wf_choosen[`WF_ID_LENGTH-1:0]),
.salu_wf_choosen (salu_wf_choosen[`WF_ID_LENGTH-1:0]));
assign alu_wfid = issued_wfid;
assign lsu_wfid = issued_wfid;
assign alu_valid = simd0_alu_select | simd1_alu_select | simd2_alu_select |
simd3_alu_select | simf0_alu_select | simf1_alu_select |
simf2_alu_select | simf3_alu_select | salu_alu_select;
assign lsu_valid = lsu_lsu_select;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_PP_SYMBOL_V
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
/*
-- ============================================================================
-- FILE NAME : ex_reg.v
-- DESCRIPTION : EXXe[WpCvCWX^
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module ex_reg (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** ALUÌoÍ **********/
input wire [`WordDataBus] alu_out, // ZÊ
input wire alu_of, // I[ot[
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
input wire int_detect, // èÝo
/********** ID/EXpCvCWX^ **********/
input wire [`WordAddrBus] id_pc, // vOJE^
input wire id_en, // pCvCf[^ÌLø
input wire id_br_flag, // ªòtO
input wire [`MemOpBus] id_mem_op, // Iy[V
input wire [`WordDataBus] id_mem_wr_data, // «Ýf[^
input wire [`CtrlOpBus] id_ctrl_op, // §äWX^Iy[V
input wire [`RegAddrBus] id_dst_addr, // ÄpWX^«ÝAhX
input wire id_gpr_we_, // ÄpWX^«ÝLø
input wire [`IsaExpBus] id_exp_code, // áOR[h
/********** EX/MEMpCvCWX^ **********/
output reg [`WordAddrBus] ex_pc, // vOJE^
output reg ex_en, // pCvCf[^ÌLø
output reg ex_br_flag, // ªòtO
output reg [`MemOpBus] ex_mem_op, // Iy[V
output reg [`WordDataBus] ex_mem_wr_data, // «Ýf[^
output reg [`CtrlOpBus] ex_ctrl_op, // §äWX^Iy[V
output reg [`RegAddrBus] ex_dst_addr, // ÄpWX^«ÝAhX
output reg ex_gpr_we_, // ÄpWX^«ÝLø
output reg [`IsaExpBus] ex_exp_code, // áOR[h
output reg [`WordDataBus] ex_out // Ê
);
/********** pCvCWX^ **********/
always @(posedge clk or `RESET_EDGE reset) begin
/* ñ¯úZbg */
if (reset == `RESET_ENABLE) begin
ex_pc <= #1 `WORD_ADDR_W'h0;
ex_en <= #1 `DISABLE;
ex_br_flag <= #1 `DISABLE;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_NO_EXP;
ex_out <= #1 `WORD_DATA_W'h0;
end else begin
/* pCvCWX^ÌXV */
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // tbV
ex_pc <= #1 `WORD_ADDR_W'h0;
ex_en <= #1 `DISABLE;
ex_br_flag <= #1 `DISABLE;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_NO_EXP;
ex_out <= #1 `WORD_DATA_W'h0;
end else if (int_detect == `ENABLE) begin // èÝÌo
ex_pc <= #1 id_pc;
ex_en <= #1 id_en;
ex_br_flag <= #1 id_br_flag;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_EXT_INT;
ex_out <= #1 `WORD_DATA_W'h0;
end else if (alu_of == `ENABLE) begin // ZpI[ot[
ex_pc <= #1 id_pc;
ex_en <= #1 id_en;
ex_br_flag <= #1 id_br_flag;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_OVERFLOW;
ex_out <= #1 `WORD_DATA_W'h0;
end else begin // Ìf[^
ex_pc <= #1 id_pc;
ex_en <= #1 id_en;
ex_br_flag <= #1 id_br_flag;
ex_mem_op <= #1 id_mem_op;
ex_mem_wr_data <= #1 id_mem_wr_data;
ex_ctrl_op <= #1 id_ctrl_op;
ex_dst_addr <= #1 id_dst_addr;
ex_gpr_we_ <= #1 id_gpr_we_;
ex_exp_code <= #1 id_exp_code;
ex_out <= #1 alu_out;
end
end
end
end
endmodule
|
// Automatically generated: write_netlist -wrapapp -verilog -module reconflogic-wrapextadc.v
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [15:0] AdcValue_s;
wire [15:0] PeriodCounterPreset_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [1:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPeriodCounterPresetEnable_s;
wire ParamThresholdEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 4 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(2),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
ExtADC ExtADC_0 (
.AdcDone_i(AdcConvComplete_i),
.AdcStart_o(AdcDoConvert_o),
.AdcValue_i(AdcValue_s),
.SensorReady_i(Inputs_i[0]),
.SensorPower_o(Outputs_o[0]),
.SensorStart_o(Outputs_o[1]),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PeriodCounterPreset_i(PeriodCounterPreset_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s)
);
assign AdcValue_s = { 6'b000000, AdcValue_i };
assign I2C_DataIn_o = 8'b00000000;
assign I2C_F100_400_n_o = 1'b0;
assign I2C_FIFOReadNext_o = 1'b0;
assign I2C_FIFOWrite_o = 1'b0;
assign I2C_ReadCount_o = 4'b0000;
assign I2C_ReceiveSend_n_o = 1'b0;
assign I2C_StartProcess_o = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_DataIn_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SPI_ReadNext_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign SPI_Write_o = 1'b0;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPreset_s),
.Enable_i(ParamPeriodCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPeriodCounterPresetEnable_s = TODO: implement;
/* Address $03 */
assign ParamThresholdEnable_s = TODO: implement;
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
// CPU reset button
input wire CPU_RESET_n,
// buttons
input wire [3:0] BUTTON,
input wire [3:0] SW,
// LEDs
output wire [6:0] HEX0_D,
output wire HEX0_DP,
output wire [6:0] HEX1_D,
output wire HEX1_DP,
output wire [3:0] LED,
output wire [3:0] LED_BRACKET,
output wire LED_RJ45_L,
output wire LED_RJ45_R,
// Temperature control
//inout wire TEMP_CLK,
//inout wire TEMP_DATA,
//input wire TEMP_INT_n,
//input wire TEMP_OVERT_n,
output wire FAN_CTRL,
// 50 MHz clock inputs
input wire OSC_50_B3B,
input wire OSC_50_B3D,
input wire OSC_50_B4A,
input wire OSC_50_B4D,
input wire OSC_50_B7A,
input wire OSC_50_B7D,
input wire OSC_50_B8A,
input wire OSC_50_B8D,
// PCIe interface
//input wire PCIE_PERST_n,
//input wire PCIE_REFCLK_p,
//input wire [7:0] PCIE_RX_p,
//output wire [7:0] PCIE_TX_p,
//input wire PCIE_WAKE_n,
//inout wire PCIE_SMBCLK,
//inout wire PCIE_SMBDAT,
// Si570
inout wire CLOCK_SCL,
inout wire CLOCK_SDA,
// 10G Ethernet
input wire SFPA_LOS,
input wire SFPA_TXFAULT,
input wire SFPA_MOD0_PRESNT_n,
inout wire SFPA_MOD1_SCL,
inout wire SFPA_MOD2_SDA,
output wire SFPA_TXDISABLE,
output wire [1:0] SPFA_RATESEL,
input wire SFPA_RX_p,
output wire SFPA_TX_p,
input wire SFPB_LOS,
input wire SFPB_TXFAULT,
input wire SFPB_MOD0_PRESNT_n,
inout wire SFPB_MOD1_SCL,
inout wire SFPB_MOD2_SDA,
output wire SFPB_TXDISABLE,
output wire [1:0] SPFB_RATESEL,
input wire SFPB_RX_p,
output wire SFPB_TX_p,
input wire SFPC_LOS,
input wire SFPC_TXFAULT,
input wire SFPC_MOD0_PRESNT_n,
inout wire SFPC_MOD1_SCL,
inout wire SFPC_MOD2_SDA,
output wire SFPC_TXDISABLE,
output wire [1:0] SPFC_RATESEL,
input wire SFPC_RX_p,
output wire SFPC_TX_p,
input wire SFPD_LOS,
input wire SFPD_TXFAULT,
input wire SFPD_MOD0_PRESNT_n,
inout wire SFPD_MOD1_SCL,
inout wire SFPD_MOD2_SDA,
output wire SFPD_TXDISABLE,
output wire [1:0] SPFD_RATESEL,
input wire SFPD_RX_p,
output wire SFPD_TX_p,
input wire SFP_REFCLK_P
);
// Clock and reset
wire clk_50mhz = OSC_50_B3B;
wire rst_50mhz;
sync_reset #(
.N(4)
)
sync_reset_50mhz_inst (
.clk(clk_50mhz),
.rst(~CPU_RESET_n),
.out(rst_50mhz)
);
wire clk_156mhz;
wire rst_156mhz;
wire phy_pll_locked;
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz),
.rst(rst_50mhz | ~phy_pll_locked),
.out(rst_156mhz)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
wire [3:0] led_int;
wire [3:0] led_bkt_int;
wire [6:0] led_hex0_d_int;
wire led_hex0_dp_int;
wire [6:0] led_hex1_d_int;
wire led_hex1_dp_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(156250)
)
debounce_switch_inst (
.clk(clk_156mhz),
.rst(rst_156mhz),
.in({BUTTON,
SW}),
.out({btn_int,
sw_int})
);
assign LED = ~led_int;
assign LED_BRACKET = ~led_bkt_int;
assign HEX0_D = ~led_hex0_d_int;
assign HEX0_DP = ~led_hex0_dp_int;
assign HEX1_D = ~led_hex1_d_int;
assign HEX1_DP = ~led_hex1_dp_int;
assign FAN_CTRL = 1;
// Si570 oscillator I2C init
wire si570_scl_i;
wire si570_scl_o;
wire si570_scl_t;
wire si570_sda_i;
wire si570_sda_o;
wire si570_sda_t;
assign si570_sda_i = CLOCK_SDA;
assign CLOCK_SDA = si570_sda_t ? 1'bz : si570_sda_o;
assign si570_scl_i = CLOCK_SCL;
assign CLOCK_SCL = si570_scl_t ? 1'bz : si570_scl_o;
wire [6:0] si570_i2c_cmd_address;
wire si570_i2c_cmd_start;
wire si570_i2c_cmd_read;
wire si570_i2c_cmd_write;
wire si570_i2c_cmd_write_multiple;
wire si570_i2c_cmd_stop;
wire si570_i2c_cmd_valid;
wire si570_i2c_cmd_ready;
wire [7:0] si570_i2c_data;
wire si570_i2c_data_valid;
wire si570_i2c_data_ready;
wire si570_i2c_data_last;
si570_i2c_init
si570_i2c_init_inst (
.clk(clk_50mhz),
.rst(rst_50mhz),
.cmd_address(si570_i2c_cmd_address),
.cmd_start(si570_i2c_cmd_start),
.cmd_read(si570_i2c_cmd_read),
.cmd_write(si570_i2c_cmd_write),
.cmd_write_multiple(si570_i2c_cmd_write_multiple),
.cmd_stop(si570_i2c_cmd_stop),
.cmd_valid(si570_i2c_cmd_valid),
.cmd_ready(si570_i2c_cmd_ready),
.data_out(si570_i2c_data),
.data_out_valid(si570_i2c_data_valid),
.data_out_ready(si570_i2c_data_ready),
.data_out_last(si570_i2c_data_last),
.busy(),
.start(1)
);
i2c_master
si570_i2c_master_inst (
.clk(clk_50mhz),
.rst(rst_50mhz),
.cmd_address(si570_i2c_cmd_address),
.cmd_start(si570_i2c_cmd_start),
.cmd_read(si570_i2c_cmd_read),
.cmd_write(si570_i2c_cmd_write),
.cmd_write_multiple(si570_i2c_cmd_write_multiple),
.cmd_stop(si570_i2c_cmd_stop),
.cmd_valid(si570_i2c_cmd_valid),
.cmd_ready(si570_i2c_cmd_ready),
.data_in(si570_i2c_data),
.data_in_valid(si570_i2c_data_valid),
.data_in_ready(si570_i2c_data_ready),
.data_in_last(si570_i2c_data_last),
.data_out(),
.data_out_valid(),
.data_out_ready(1),
.data_out_last(),
.scl_i(si570_scl_i),
.scl_o(si570_scl_o),
.scl_t(si570_scl_t),
.sda_i(si570_sda_i),
.sda_o(si570_sda_o),
.sda_t(si570_sda_t),
.busy(),
.bus_control(),
.bus_active(),
.missed_ack(),
.prescale(312),
.stop_on_idle(1)
);
// 10G Ethernet PHY
wire [71:0] sfp_a_tx_dc;
wire [71:0] sfp_a_rx_dc;
wire [71:0] sfp_b_tx_dc;
wire [71:0] sfp_b_rx_dc;
wire [71:0] sfp_c_tx_dc;
wire [71:0] sfp_c_rx_dc;
wire [71:0] sfp_d_tx_dc;
wire [71:0] sfp_d_rx_dc;
wire [367:0] phy_reconfig_from_xcvr;
wire [559:0] phy_reconfig_to_xcvr;
assign SFPA_MOD1_SCL = 1'bz;
assign SFPA_MOD2_SDA = 1'bz;
assign SFPA_TXDISABLE = 1'b0;
assign SPFA_RATESEL = 2'b00;
assign SFPB_MOD1_SCL = 1'bz;
assign SFPB_MOD2_SDA = 1'bz;
assign SFPB_TXDISABLE = 1'b0;
assign SPFB_RATESEL = 2'b00;
assign SFPC_MOD1_SCL = 1'bz;
assign SFPC_MOD2_SDA = 1'bz;
assign SFPC_TXDISABLE = 1'b0;
assign SPFC_RATESEL = 2'b00;
assign SFPD_MOD1_SCL = 1'bz;
assign SFPD_MOD2_SDA = 1'bz;
assign SFPD_TXDISABLE = 1'b0;
assign SPFD_RATESEL = 2'b00;
phy
phy_inst (
.pll_ref_clk(SFP_REFCLK_P),
.pll_locked(phy_pll_locked),
.tx_serial_data_0(SFPA_TX_p),
.rx_serial_data_0(SFPA_RX_p),
.tx_serial_data_1(SFPB_TX_p),
.rx_serial_data_1(SFPB_RX_p),
.tx_serial_data_2(SFPC_TX_p),
.rx_serial_data_2(SFPC_RX_p),
.tx_serial_data_3(SFPD_TX_p),
.rx_serial_data_3(SFPD_RX_p),
.xgmii_tx_dc_0(sfp_a_tx_dc),
.xgmii_rx_dc_0(sfp_a_rx_dc),
.xgmii_tx_dc_1(sfp_b_tx_dc),
.xgmii_rx_dc_1(sfp_b_rx_dc),
.xgmii_tx_dc_2(sfp_c_tx_dc),
.xgmii_rx_dc_2(sfp_c_rx_dc),
.xgmii_tx_dc_3(sfp_d_tx_dc),
.xgmii_rx_dc_3(sfp_d_rx_dc),
.xgmii_rx_clk(clk_156mhz),
.xgmii_tx_clk(clk_156mhz),
.tx_ready(~rst_156mhz),
.rx_ready(),
.rx_data_ready(),
.phy_mgmt_clk(clk_50mhz),
.phy_mgmt_clk_reset(rst_50mhz),
.phy_mgmt_address(9'd0),
.phy_mgmt_read(1'b0),
.phy_mgmt_readdata(),
.phy_mgmt_waitrequest(),
.phy_mgmt_write(1'b0),
.phy_mgmt_writedata(32'd0),
.reconfig_from_xcvr(phy_reconfig_from_xcvr),
.reconfig_to_xcvr(phy_reconfig_to_xcvr)
);
phy_reconfig
phy_reconfig_inst (
.reconfig_busy(),
.mgmt_clk_clk(clk_50mhz),
.mgmt_rst_reset(rst_50mhz),
.reconfig_mgmt_address(7'd0),
.reconfig_mgmt_read(1'b0),
.reconfig_mgmt_readdata(),
.reconfig_mgmt_waitrequest(),
.reconfig_mgmt_write(1'b0),
.reconfig_mgmt_writedata(32'd0),
.reconfig_to_xcvr(phy_reconfig_to_xcvr),
.reconfig_from_xcvr(phy_reconfig_from_xcvr)
);
// Convert XGMII interfaces
wire [63:0] sfp_a_txd_int;
wire [7:0] sfp_a_txc_int;
wire [63:0] sfp_a_rxd_int;
wire [7:0] sfp_a_rxc_int;
wire [63:0] sfp_b_txd_int;
wire [7:0] sfp_b_txc_int;
wire [63:0] sfp_b_rxd_int;
wire [7:0] sfp_b_rxc_int;
wire [63:0] sfp_c_txd_int;
wire [7:0] sfp_c_txc_int;
wire [63:0] sfp_c_rxd_int;
wire [7:0] sfp_c_rxc_int;
wire [63:0] sfp_d_txd_int;
wire [7:0] sfp_d_txc_int;
wire [63:0] sfp_d_rxd_int;
wire [7:0] sfp_d_rxc_int;
xgmii_interleave
xgmii_interleave_inst_a (
.input_xgmii_d(sfp_a_txd_int),
.input_xgmii_c(sfp_a_txc_int),
.output_xgmii_dc(sfp_a_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_a (
.input_xgmii_dc(sfp_a_rx_dc),
.output_xgmii_d(sfp_a_rxd_int),
.output_xgmii_c(sfp_a_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_b (
.input_xgmii_d(sfp_b_txd_int),
.input_xgmii_c(sfp_b_txc_int),
.output_xgmii_dc(sfp_b_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_b (
.input_xgmii_dc(sfp_b_rx_dc),
.output_xgmii_d(sfp_b_rxd_int),
.output_xgmii_c(sfp_b_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_c (
.input_xgmii_d(sfp_c_txd_int),
.input_xgmii_c(sfp_c_txc_int),
.output_xgmii_dc(sfp_c_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_c (
.input_xgmii_dc(sfp_c_rx_dc),
.output_xgmii_d(sfp_c_rxd_int),
.output_xgmii_c(sfp_c_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_d (
.input_xgmii_d(sfp_d_txd_int),
.input_xgmii_c(sfp_d_txc_int),
.output_xgmii_dc(sfp_d_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_d (
.input_xgmii_dc(sfp_d_rx_dc),
.output_xgmii_d(sfp_d_rxd_int),
.output_xgmii_c(sfp_d_rxc_int)
);
// Core logic
fpga_core
core_inst (
/*
* Clock: 156.25MHz
* Synchronous reset
*/
.clk(clk_156mhz),
.rst(rst_156mhz),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led(led_int),
.led_bkt(led_bkt_int),
.led_hex0_d(led_hex0_d_int),
.led_hex0_dp(led_hex0_dp_int),
.led_hex1_d(led_hex1_d_int),
.led_hex1_dp(led_hex1_dp_int),
/*
* 10G Ethernet
*/
.sfp_a_txd(sfp_a_txd_int),
.sfp_a_txc(sfp_a_txc_int),
.sfp_a_rxd(sfp_a_rxd_int),
.sfp_a_rxc(sfp_a_rxc_int),
.sfp_b_txd(sfp_b_txd_int),
.sfp_b_txc(sfp_b_txc_int),
.sfp_b_rxd(sfp_b_rxd_int),
.sfp_b_rxc(sfp_b_rxc_int),
.sfp_c_txd(sfp_c_txd_int),
.sfp_c_txc(sfp_c_txc_int),
.sfp_c_rxd(sfp_c_rxd_int),
.sfp_c_rxc(sfp_c_rxc_int),
.sfp_d_txd(sfp_d_txd_int),
.sfp_d_txc(sfp_d_txc_int),
.sfp_d_rxd(sfp_d_rxd_int),
.sfp_d_rxc(sfp_d_rxc_int)
);
endmodule
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 36K-bit Configurable Synchronous Block RAM
// /___/ /\ Filename : RAMB36E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 02/28/2013 - intial from FIFO
// 03/09/2013 - update from various initial CR - collisions
// 03/19/2013 - 707443 - RDADDRECC not hooked up
// 03/22/2013 - sync5 yaml update, port ordering
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - revert NO_CHANGE fix
// 04/04/2013 - 709962 - typo CASDOUTPA/PB vs CASDOUTAP/BP
// 04/23/2013 - PR683925 - add invertible pin support.
// 04/26/2013 - 714182 - RDADDRECC bits shifted by 1.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAMB36E2 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_ORDER_B = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter integer DOA_REG = 1,
parameter integer DOB_REG = 1,
parameter ENADDRENA = "FALSE",
parameter ENADDRENB = "FALSE",
parameter EN_ECC_PIPE = "FALSE",
parameter EN_ECC_READ = "FALSE",
parameter EN_ECC_WRITE = "FALSE",
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [35:0] INIT_A = 36'h000000000,
parameter [35:0] INIT_B = 36'h000000000,
parameter INIT_FILE = "NONE",
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0,
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0,
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0,
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0,
parameter RDADDRCHANGEA = "FALSE",
parameter RDADDRCHANGEB = "FALSE",
parameter integer READ_WIDTH_A = 0,
parameter integer READ_WIDTH_B = 0,
parameter RSTREG_PRIORITY_A = "RSTREG",
parameter RSTREG_PRIORITY_B = "RSTREG",
parameter SIM_COLLISION_CHECK = "ALL",
parameter SLEEP_ASYNC = "FALSE",
parameter [35:0] SRVAL_A = 36'h000000000,
parameter [35:0] SRVAL_B = 36'h000000000,
parameter WRITE_MODE_A = "NO_CHANGE",
parameter WRITE_MODE_B = "NO_CHANGE",
parameter integer WRITE_WIDTH_A = 0,
parameter integer WRITE_WIDTH_B = 0
)(
output [31:0] CASDOUTA,
output [31:0] CASDOUTB,
output [3:0] CASDOUTPA,
output [3:0] CASDOUTPB,
output CASOUTDBITERR,
output CASOUTSBITERR,
output DBITERR,
output [31:0] DOUTADOUT,
output [31:0] DOUTBDOUT,
output [3:0] DOUTPADOUTP,
output [3:0] DOUTPBDOUTP,
output [7:0] ECCPARITY,
output [8:0] RDADDRECC,
output SBITERR,
input [14:0] ADDRARDADDR,
input [14:0] ADDRBWRADDR,
input ADDRENA,
input ADDRENB,
input CASDIMUXA,
input CASDIMUXB,
input [31:0] CASDINA,
input [31:0] CASDINB,
input [3:0] CASDINPA,
input [3:0] CASDINPB,
input CASDOMUXA,
input CASDOMUXB,
input CASDOMUXEN_A,
input CASDOMUXEN_B,
input CASINDBITERR,
input CASINSBITERR,
input CASOREGIMUXA,
input CASOREGIMUXB,
input CASOREGIMUXEN_A,
input CASOREGIMUXEN_B,
input CLKARDCLK,
input CLKBWRCLK,
input [31:0] DINADIN,
input [31:0] DINBDIN,
input [3:0] DINPADINP,
input [3:0] DINPBDINP,
input ECCPIPECE,
input ENARDEN,
input ENBWREN,
input INJECTDBITERR,
input INJECTSBITERR,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input SLEEP,
input [3:0] WEA,
input [7:0] WEBWE
);
// define constants
localparam MODULE_NAME = "RAMB36E2";
// Parameter encodings and registers
localparam CASCADE_ORDER_A_FIRST = 1;
localparam CASCADE_ORDER_A_LAST = 2;
localparam CASCADE_ORDER_A_MIDDLE = 3;
localparam CASCADE_ORDER_A_NONE = 0;
localparam CASCADE_ORDER_B_FIRST = 1;
localparam CASCADE_ORDER_B_LAST = 2;
localparam CASCADE_ORDER_B_MIDDLE = 3;
localparam CASCADE_ORDER_B_NONE = 0;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam DOA_REG_0 = 1;
localparam DOA_REG_1 = 0;
localparam DOB_REG_0 = 1;
localparam DOB_REG_1 = 0;
localparam ENADDRENA_FALSE = 0;
localparam ENADDRENA_TRUE = 1;
localparam ENADDRENB_FALSE = 0;
localparam ENADDRENB_TRUE = 1;
localparam EN_ECC_PIPE_FALSE = 0;
localparam EN_ECC_PIPE_TRUE = 1;
localparam EN_ECC_READ_FALSE = 0;
localparam EN_ECC_READ_TRUE = 1;
localparam EN_ECC_WRITE_FALSE = 0;
localparam EN_ECC_WRITE_TRUE = 1;
localparam RDADDRCHANGEA_FALSE = 0;
localparam RDADDRCHANGEA_TRUE = 1;
localparam RDADDRCHANGEB_FALSE = 0;
localparam RDADDRCHANGEB_TRUE = 1;
localparam READ_WIDTH_A_0 = 1;
localparam READ_WIDTH_A_1 = 1;
localparam READ_WIDTH_A_18 = 16;
localparam READ_WIDTH_A_2 = 2;
localparam READ_WIDTH_A_36 = 32;
localparam READ_WIDTH_A_4 = 4;
localparam READ_WIDTH_A_72 = 64;
localparam READ_WIDTH_A_9 = 8;
localparam READ_WIDTH_B_0 = 1;
localparam READ_WIDTH_B_1 = 1;
localparam READ_WIDTH_B_18 = 16;
localparam READ_WIDTH_B_2 = 2;
localparam READ_WIDTH_B_36 = 32;
localparam READ_WIDTH_B_4 = 4;
localparam READ_WIDTH_B_9 = 8;
localparam RSTREG_PRIORITY_A_REGCE = 1;
localparam RSTREG_PRIORITY_A_RSTREG = 0;
localparam RSTREG_PRIORITY_B_REGCE = 1;
localparam RSTREG_PRIORITY_B_RSTREG = 0;
localparam SIM_COLLISION_CHECK_ALL = 0;
localparam SIM_COLLISION_CHECK_GENERATE_X_ONLY = 1;
localparam SIM_COLLISION_CHECK_NONE = 2;
localparam SIM_COLLISION_CHECK_WARNING_ONLY = 3;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRITE_MODE_A_NO_CHANGE = 0;
localparam WRITE_MODE_A_READ_FIRST = 1;
localparam WRITE_MODE_A_WRITE_FIRST = 2;
localparam WRITE_MODE_B_NO_CHANGE = 0;
localparam WRITE_MODE_B_READ_FIRST = 1;
localparam WRITE_MODE_B_WRITE_FIRST = 2;
localparam WRITE_WIDTH_A_0 = 1;
localparam WRITE_WIDTH_A_1 = 1;
localparam WRITE_WIDTH_A_18 = 16;
localparam WRITE_WIDTH_A_2 = 2;
localparam WRITE_WIDTH_A_36 = 32;
localparam WRITE_WIDTH_A_4 = 4;
localparam WRITE_WIDTH_A_9 = 8;
localparam WRITE_WIDTH_B_0 = 1;
localparam WRITE_WIDTH_B_1 = 1;
localparam WRITE_WIDTH_B_18 = 16;
localparam WRITE_WIDTH_B_2 = 2;
localparam WRITE_WIDTH_B_36 = 32;
localparam WRITE_WIDTH_B_4 = 4;
localparam WRITE_WIDTH_B_72 = 64;
localparam WRITE_WIDTH_B_9 = 8;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "RAMB36E2_dr.v"
`else
localparam [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A;
localparam [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [0:0] DOA_REG_REG = DOA_REG;
localparam [0:0] DOB_REG_REG = DOB_REG;
localparam [40:1] ENADDRENA_REG = ENADDRENA;
localparam [40:1] ENADDRENB_REG = ENADDRENB;
localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE;
localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ;
localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE;
localparam [255:0] INITP_00_REG = INITP_00;
localparam [255:0] INITP_01_REG = INITP_01;
localparam [255:0] INITP_02_REG = INITP_02;
localparam [255:0] INITP_03_REG = INITP_03;
localparam [255:0] INITP_04_REG = INITP_04;
localparam [255:0] INITP_05_REG = INITP_05;
localparam [255:0] INITP_06_REG = INITP_06;
localparam [255:0] INITP_07_REG = INITP_07;
localparam [255:0] INITP_08_REG = INITP_08;
localparam [255:0] INITP_09_REG = INITP_09;
localparam [255:0] INITP_0A_REG = INITP_0A;
localparam [255:0] INITP_0B_REG = INITP_0B;
localparam [255:0] INITP_0C_REG = INITP_0C;
localparam [255:0] INITP_0D_REG = INITP_0D;
localparam [255:0] INITP_0E_REG = INITP_0E;
localparam [255:0] INITP_0F_REG = INITP_0F;
localparam [255:0] INIT_00_REG = INIT_00;
localparam [255:0] INIT_01_REG = INIT_01;
localparam [255:0] INIT_02_REG = INIT_02;
localparam [255:0] INIT_03_REG = INIT_03;
localparam [255:0] INIT_04_REG = INIT_04;
localparam [255:0] INIT_05_REG = INIT_05;
localparam [255:0] INIT_06_REG = INIT_06;
localparam [255:0] INIT_07_REG = INIT_07;
localparam [255:0] INIT_08_REG = INIT_08;
localparam [255:0] INIT_09_REG = INIT_09;
localparam [255:0] INIT_0A_REG = INIT_0A;
localparam [255:0] INIT_0B_REG = INIT_0B;
localparam [255:0] INIT_0C_REG = INIT_0C;
localparam [255:0] INIT_0D_REG = INIT_0D;
localparam [255:0] INIT_0E_REG = INIT_0E;
localparam [255:0] INIT_0F_REG = INIT_0F;
localparam [255:0] INIT_10_REG = INIT_10;
localparam [255:0] INIT_11_REG = INIT_11;
localparam [255:0] INIT_12_REG = INIT_12;
localparam [255:0] INIT_13_REG = INIT_13;
localparam [255:0] INIT_14_REG = INIT_14;
localparam [255:0] INIT_15_REG = INIT_15;
localparam [255:0] INIT_16_REG = INIT_16;
localparam [255:0] INIT_17_REG = INIT_17;
localparam [255:0] INIT_18_REG = INIT_18;
localparam [255:0] INIT_19_REG = INIT_19;
localparam [255:0] INIT_1A_REG = INIT_1A;
localparam [255:0] INIT_1B_REG = INIT_1B;
localparam [255:0] INIT_1C_REG = INIT_1C;
localparam [255:0] INIT_1D_REG = INIT_1D;
localparam [255:0] INIT_1E_REG = INIT_1E;
localparam [255:0] INIT_1F_REG = INIT_1F;
localparam [255:0] INIT_20_REG = INIT_20;
localparam [255:0] INIT_21_REG = INIT_21;
localparam [255:0] INIT_22_REG = INIT_22;
localparam [255:0] INIT_23_REG = INIT_23;
localparam [255:0] INIT_24_REG = INIT_24;
localparam [255:0] INIT_25_REG = INIT_25;
localparam [255:0] INIT_26_REG = INIT_26;
localparam [255:0] INIT_27_REG = INIT_27;
localparam [255:0] INIT_28_REG = INIT_28;
localparam [255:0] INIT_29_REG = INIT_29;
localparam [255:0] INIT_2A_REG = INIT_2A;
localparam [255:0] INIT_2B_REG = INIT_2B;
localparam [255:0] INIT_2C_REG = INIT_2C;
localparam [255:0] INIT_2D_REG = INIT_2D;
localparam [255:0] INIT_2E_REG = INIT_2E;
localparam [255:0] INIT_2F_REG = INIT_2F;
localparam [255:0] INIT_30_REG = INIT_30;
localparam [255:0] INIT_31_REG = INIT_31;
localparam [255:0] INIT_32_REG = INIT_32;
localparam [255:0] INIT_33_REG = INIT_33;
localparam [255:0] INIT_34_REG = INIT_34;
localparam [255:0] INIT_35_REG = INIT_35;
localparam [255:0] INIT_36_REG = INIT_36;
localparam [255:0] INIT_37_REG = INIT_37;
localparam [255:0] INIT_38_REG = INIT_38;
localparam [255:0] INIT_39_REG = INIT_39;
localparam [255:0] INIT_3A_REG = INIT_3A;
localparam [255:0] INIT_3B_REG = INIT_3B;
localparam [255:0] INIT_3C_REG = INIT_3C;
localparam [255:0] INIT_3D_REG = INIT_3D;
localparam [255:0] INIT_3E_REG = INIT_3E;
localparam [255:0] INIT_3F_REG = INIT_3F;
localparam [255:0] INIT_40_REG = INIT_40;
localparam [255:0] INIT_41_REG = INIT_41;
localparam [255:0] INIT_42_REG = INIT_42;
localparam [255:0] INIT_43_REG = INIT_43;
localparam [255:0] INIT_44_REG = INIT_44;
localparam [255:0] INIT_45_REG = INIT_45;
localparam [255:0] INIT_46_REG = INIT_46;
localparam [255:0] INIT_47_REG = INIT_47;
localparam [255:0] INIT_48_REG = INIT_48;
localparam [255:0] INIT_49_REG = INIT_49;
localparam [255:0] INIT_4A_REG = INIT_4A;
localparam [255:0] INIT_4B_REG = INIT_4B;
localparam [255:0] INIT_4C_REG = INIT_4C;
localparam [255:0] INIT_4D_REG = INIT_4D;
localparam [255:0] INIT_4E_REG = INIT_4E;
localparam [255:0] INIT_4F_REG = INIT_4F;
localparam [255:0] INIT_50_REG = INIT_50;
localparam [255:0] INIT_51_REG = INIT_51;
localparam [255:0] INIT_52_REG = INIT_52;
localparam [255:0] INIT_53_REG = INIT_53;
localparam [255:0] INIT_54_REG = INIT_54;
localparam [255:0] INIT_55_REG = INIT_55;
localparam [255:0] INIT_56_REG = INIT_56;
localparam [255:0] INIT_57_REG = INIT_57;
localparam [255:0] INIT_58_REG = INIT_58;
localparam [255:0] INIT_59_REG = INIT_59;
localparam [255:0] INIT_5A_REG = INIT_5A;
localparam [255:0] INIT_5B_REG = INIT_5B;
localparam [255:0] INIT_5C_REG = INIT_5C;
localparam [255:0] INIT_5D_REG = INIT_5D;
localparam [255:0] INIT_5E_REG = INIT_5E;
localparam [255:0] INIT_5F_REG = INIT_5F;
localparam [255:0] INIT_60_REG = INIT_60;
localparam [255:0] INIT_61_REG = INIT_61;
localparam [255:0] INIT_62_REG = INIT_62;
localparam [255:0] INIT_63_REG = INIT_63;
localparam [255:0] INIT_64_REG = INIT_64;
localparam [255:0] INIT_65_REG = INIT_65;
localparam [255:0] INIT_66_REG = INIT_66;
localparam [255:0] INIT_67_REG = INIT_67;
localparam [255:0] INIT_68_REG = INIT_68;
localparam [255:0] INIT_69_REG = INIT_69;
localparam [255:0] INIT_6A_REG = INIT_6A;
localparam [255:0] INIT_6B_REG = INIT_6B;
localparam [255:0] INIT_6C_REG = INIT_6C;
localparam [255:0] INIT_6D_REG = INIT_6D;
localparam [255:0] INIT_6E_REG = INIT_6E;
localparam [255:0] INIT_6F_REG = INIT_6F;
localparam [255:0] INIT_70_REG = INIT_70;
localparam [255:0] INIT_71_REG = INIT_71;
localparam [255:0] INIT_72_REG = INIT_72;
localparam [255:0] INIT_73_REG = INIT_73;
localparam [255:0] INIT_74_REG = INIT_74;
localparam [255:0] INIT_75_REG = INIT_75;
localparam [255:0] INIT_76_REG = INIT_76;
localparam [255:0] INIT_77_REG = INIT_77;
localparam [255:0] INIT_78_REG = INIT_78;
localparam [255:0] INIT_79_REG = INIT_79;
localparam [255:0] INIT_7A_REG = INIT_7A;
localparam [255:0] INIT_7B_REG = INIT_7B;
localparam [255:0] INIT_7C_REG = INIT_7C;
localparam [255:0] INIT_7D_REG = INIT_7D;
localparam [255:0] INIT_7E_REG = INIT_7E;
localparam [255:0] INIT_7F_REG = INIT_7F;
localparam [35:0] INIT_A_REG = INIT_A;
localparam [35:0] INIT_B_REG = INIT_B;
localparam INIT_FILE_REG = INIT_FILE;
localparam [0:0] IS_CLKARDCLK_INVERTED_REG = IS_CLKARDCLK_INVERTED;
localparam [0:0] IS_CLKBWRCLK_INVERTED_REG = IS_CLKBWRCLK_INVERTED;
localparam [0:0] IS_ENARDEN_INVERTED_REG = IS_ENARDEN_INVERTED;
localparam [0:0] IS_ENBWREN_INVERTED_REG = IS_ENBWREN_INVERTED;
localparam [0:0] IS_RSTRAMARSTRAM_INVERTED_REG = IS_RSTRAMARSTRAM_INVERTED;
localparam [0:0] IS_RSTRAMB_INVERTED_REG = IS_RSTRAMB_INVERTED;
localparam [0:0] IS_RSTREGARSTREG_INVERTED_REG = IS_RSTREGARSTREG_INVERTED;
localparam [0:0] IS_RSTREGB_INVERTED_REG = IS_RSTREGB_INVERTED;
localparam [40:1] RDADDRCHANGEA_REG = RDADDRCHANGEA;
localparam [40:1] RDADDRCHANGEB_REG = RDADDRCHANGEB;
localparam [6:0] READ_WIDTH_A_REG = READ_WIDTH_A;
localparam [5:0] READ_WIDTH_B_REG = READ_WIDTH_B;
localparam [48:1] RSTREG_PRIORITY_A_REG = RSTREG_PRIORITY_A;
localparam [48:1] RSTREG_PRIORITY_B_REG = RSTREG_PRIORITY_B;
localparam [120:1] SIM_COLLISION_CHECK_REG = SIM_COLLISION_CHECK;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [35:0] SRVAL_A_REG = SRVAL_A;
localparam [35:0] SRVAL_B_REG = SRVAL_B;
localparam [88:1] WRITE_MODE_A_REG = WRITE_MODE_A;
localparam [88:1] WRITE_MODE_B_REG = WRITE_MODE_B;
localparam [5:0] WRITE_WIDTH_A_REG = WRITE_WIDTH_A;
localparam [6:0] WRITE_WIDTH_B_REG = WRITE_WIDTH_B;
`endif
wire [1:0] CASCADE_ORDER_A_BIN;
wire [1:0] CASCADE_ORDER_B_BIN;
wire CLOCK_DOMAINS_BIN;
wire DOA_REG_BIN;
wire DOB_REG_BIN;
wire ENADDRENA_BIN;
wire ENADDRENB_BIN;
wire EN_ECC_PIPE_BIN;
wire EN_ECC_READ_BIN;
wire EN_ECC_WRITE_BIN;
wire [255:0] INITP_BIN [0:15];
wire [255:0] INIT_BIN [0:127];
wire [35:0] INIT_A_BIN;
wire [35:0] INIT_B_BIN;
wire IS_CLKARDCLK_INVERTED_BIN;
wire IS_CLKBWRCLK_INVERTED_BIN;
wire IS_ENARDEN_INVERTED_BIN;
wire IS_ENBWREN_INVERTED_BIN;
wire IS_RSTRAMARSTRAM_INVERTED_BIN;
wire IS_RSTRAMB_INVERTED_BIN;
wire IS_RSTREGARSTREG_INVERTED_BIN;
wire IS_RSTREGB_INVERTED_BIN;
wire RDADDRCHANGEA_BIN;
wire RDADDRCHANGEB_BIN;
wire [6:0] READ_WIDTH_A_BIN;
wire [6:0] READ_WIDTH_B_BIN;
wire RSTREG_PRIORITY_A_BIN;
wire RSTREG_PRIORITY_B_BIN;
wire [1:0] SIM_COLLISION_CHECK_BIN;
wire SLEEP_ASYNC_BIN;
wire [35:0] SRVAL_A_BIN;
wire [35:0] SRVAL_B_BIN;
wire [1:0] WRITE_MODE_A_BIN;
wire [1:0] WRITE_MODE_B_BIN;
wire [6:0] WRITE_WIDTH_A_BIN;
wire [6:0] WRITE_WIDTH_B_BIN;
reg INIT_MEM = 0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR || INIT_MEM;
wire CASOUTDBITERR_out;
wire CASOUTSBITERR_out;
reg DBITERR_out;
reg SBITERR_out;
wire [31:0] CASDOUTA_out;
wire [31:0] CASDOUTB_out;
reg [31:0] DOUTADOUT_out;
reg [31:0] DOUTBDOUT_out;
wire [3:0] CASDOUTPA_out;
wire [3:0] CASDOUTPB_out;
reg [3:0] DOUTPADOUTP_out;
reg [3:0] DOUTPBDOUTP_out;
wire [7:0] ECCPARITY_out;
wire [8:0] RDADDRECC_out;
wire ADDRENA_in;
wire ADDRENB_in;
wire CASDIMUXA_in;
wire CASDIMUXB_in;
wire CASDOMUXA_in;
wire CASDOMUXB_in;
wire CASDOMUXEN_A_in;
wire CASDOMUXEN_B_in;
wire CASINDBITERR_in;
wire CASINSBITERR_in;
wire CASOREGIMUXA_in;
wire CASOREGIMUXB_in;
wire CASOREGIMUXEN_A_in;
wire CASOREGIMUXEN_B_in;
wire CLKARDCLK_in;
wire CLKBWRCLK_in;
wire ECCPIPECE_in;
wire ENARDEN_in;
wire ENBWREN_in;
wire INJECTDBITERR_in;
wire INJECTSBITERR_in;
wire REGCEAREGCE_in;
wire REGCEB_in;
wire RSTRAMARSTRAM_in;
wire RSTRAMB_in;
wire RSTREGARSTREG_in;
wire RSTREGB_in;
wire SLEEP_in;
reg [14:0] ADDRARDADDR_in;
reg [14:0] ADDRBWRADDR_in;
wire [31:0] CASDINA_in;
wire [31:0] CASDINB_in;
reg [31:0] DINADIN_in;
reg [31:0] DINBDIN_in;
wire [3:0] CASDINPA_in;
wire [3:0] CASDINPB_in;
reg [3:0] DINPADINP_in;
reg [3:0] DINPBDINP_in;
wire [3:0] WEA_in;
wire [7:0] WEBWE_in;
`ifdef XIL_TIMING
wire ADDRENA_delay;
wire ADDRENB_delay;
wire CASDIMUXA_delay;
wire CASDIMUXB_delay;
wire CASDOMUXA_delay;
wire CASDOMUXB_delay;
wire CASDOMUXEN_A_delay;
wire CASDOMUXEN_B_delay;
wire CASINDBITERR_delay;
wire CASINSBITERR_delay;
wire CASOREGIMUXA_delay;
wire CASOREGIMUXB_delay;
wire CASOREGIMUXEN_A_delay;
wire CASOREGIMUXEN_B_delay;
wire CLKARDCLK_delay;
wire CLKBWRCLK_delay;
wire ECCPIPECE_delay;
wire ENARDEN_delay;
wire ENBWREN_delay;
wire INJECTDBITERR_delay;
wire INJECTSBITERR_delay;
wire REGCEAREGCE_delay;
wire REGCEB_delay;
wire RSTRAMARSTRAM_delay;
wire RSTRAMB_delay;
wire RSTREGARSTREG_delay;
wire RSTREGB_delay;
wire SLEEP_delay;
wire [14:0] ADDRARDADDR_delay;
wire [14:0] ADDRBWRADDR_delay;
wire [31:0] CASDINA_delay;
wire [31:0] CASDINB_delay;
wire [31:0] DINADIN_delay;
wire [31:0] DINBDIN_delay;
wire [3:0] CASDINPA_delay;
wire [3:0] CASDINPB_delay;
wire [3:0] DINPADINP_delay;
wire [3:0] DINPBDINP_delay;
wire [3:0] WEA_delay;
wire [7:0] WEBWE_delay;
`endif
assign CASDOUTA = CASDOUTA_out;
assign CASDOUTB = CASDOUTB_out;
assign CASDOUTPA = CASDOUTPA_out;
assign CASDOUTPB = CASDOUTPB_out;
assign CASOUTDBITERR = CASOUTDBITERR_out;
assign CASOUTSBITERR = CASOUTSBITERR_out;
assign DBITERR = DBITERR_out;
assign DOUTADOUT = DOUTADOUT_out;
assign DOUTBDOUT = DOUTBDOUT_out;
assign DOUTPADOUTP = DOUTPADOUTP_out;
assign DOUTPBDOUTP = DOUTPBDOUTP_out;
assign ECCPARITY = ECCPARITY_out;
assign RDADDRECC = RDADDRECC_out;
assign SBITERR = SBITERR_out;
`ifdef XIL_TIMING
always @ (*) ADDRARDADDR_in = ADDRARDADDR_delay;
always @ (*) ADDRBWRADDR_in = ADDRBWRADDR_delay;
assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA_delay; // rv 1
assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB_delay; // rv 1
assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA_delay; // rv 0
assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB_delay; // rv 0
assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA_delay[0]; // rv 0
assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA_delay[10]; // rv 0
assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA_delay[11]; // rv 0
assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA_delay[12]; // rv 0
assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA_delay[13]; // rv 0
assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA_delay[14]; // rv 0
assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA_delay[15]; // rv 0
assign CASDINA_in[16] = (CASDINA[16] !== 1'bz) && CASDINA_delay[16]; // rv 0
assign CASDINA_in[17] = (CASDINA[17] !== 1'bz) && CASDINA_delay[17]; // rv 0
assign CASDINA_in[18] = (CASDINA[18] !== 1'bz) && CASDINA_delay[18]; // rv 0
assign CASDINA_in[19] = (CASDINA[19] !== 1'bz) && CASDINA_delay[19]; // rv 0
assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA_delay[1]; // rv 0
assign CASDINA_in[20] = (CASDINA[20] !== 1'bz) && CASDINA_delay[20]; // rv 0
assign CASDINA_in[21] = (CASDINA[21] !== 1'bz) && CASDINA_delay[21]; // rv 0
assign CASDINA_in[22] = (CASDINA[22] !== 1'bz) && CASDINA_delay[22]; // rv 0
assign CASDINA_in[23] = (CASDINA[23] !== 1'bz) && CASDINA_delay[23]; // rv 0
assign CASDINA_in[24] = (CASDINA[24] !== 1'bz) && CASDINA_delay[24]; // rv 0
assign CASDINA_in[25] = (CASDINA[25] !== 1'bz) && CASDINA_delay[25]; // rv 0
assign CASDINA_in[26] = (CASDINA[26] !== 1'bz) && CASDINA_delay[26]; // rv 0
assign CASDINA_in[27] = (CASDINA[27] !== 1'bz) && CASDINA_delay[27]; // rv 0
assign CASDINA_in[28] = (CASDINA[28] !== 1'bz) && CASDINA_delay[28]; // rv 0
assign CASDINA_in[29] = (CASDINA[29] !== 1'bz) && CASDINA_delay[29]; // rv 0
assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA_delay[2]; // rv 0
assign CASDINA_in[30] = (CASDINA[30] !== 1'bz) && CASDINA_delay[30]; // rv 0
assign CASDINA_in[31] = (CASDINA[31] !== 1'bz) && CASDINA_delay[31]; // rv 0
assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA_delay[3]; // rv 0
assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA_delay[4]; // rv 0
assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA_delay[5]; // rv 0
assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA_delay[6]; // rv 0
assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA_delay[7]; // rv 0
assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA_delay[8]; // rv 0
assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA_delay[9]; // rv 0
assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB_delay[0]; // rv 0
assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB_delay[10]; // rv 0
assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB_delay[11]; // rv 0
assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB_delay[12]; // rv 0
assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB_delay[13]; // rv 0
assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB_delay[14]; // rv 0
assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB_delay[15]; // rv 0
assign CASDINB_in[16] = (CASDINB[16] !== 1'bz) && CASDINB_delay[16]; // rv 0
assign CASDINB_in[17] = (CASDINB[17] !== 1'bz) && CASDINB_delay[17]; // rv 0
assign CASDINB_in[18] = (CASDINB[18] !== 1'bz) && CASDINB_delay[18]; // rv 0
assign CASDINB_in[19] = (CASDINB[19] !== 1'bz) && CASDINB_delay[19]; // rv 0
assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB_delay[1]; // rv 0
assign CASDINB_in[20] = (CASDINB[20] !== 1'bz) && CASDINB_delay[20]; // rv 0
assign CASDINB_in[21] = (CASDINB[21] !== 1'bz) && CASDINB_delay[21]; // rv 0
assign CASDINB_in[22] = (CASDINB[22] !== 1'bz) && CASDINB_delay[22]; // rv 0
assign CASDINB_in[23] = (CASDINB[23] !== 1'bz) && CASDINB_delay[23]; // rv 0
assign CASDINB_in[24] = (CASDINB[24] !== 1'bz) && CASDINB_delay[24]; // rv 0
assign CASDINB_in[25] = (CASDINB[25] !== 1'bz) && CASDINB_delay[25]; // rv 0
assign CASDINB_in[26] = (CASDINB[26] !== 1'bz) && CASDINB_delay[26]; // rv 0
assign CASDINB_in[27] = (CASDINB[27] !== 1'bz) && CASDINB_delay[27]; // rv 0
assign CASDINB_in[28] = (CASDINB[28] !== 1'bz) && CASDINB_delay[28]; // rv 0
assign CASDINB_in[29] = (CASDINB[29] !== 1'bz) && CASDINB_delay[29]; // rv 0
assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB_delay[2]; // rv 0
assign CASDINB_in[30] = (CASDINB[30] !== 1'bz) && CASDINB_delay[30]; // rv 0
assign CASDINB_in[31] = (CASDINB[31] !== 1'bz) && CASDINB_delay[31]; // rv 0
assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB_delay[3]; // rv 0
assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB_delay[4]; // rv 0
assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB_delay[5]; // rv 0
assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB_delay[6]; // rv 0
assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB_delay[7]; // rv 0
assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB_delay[8]; // rv 0
assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB_delay[9]; // rv 0
assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA_delay[0]; // rv 0
assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA_delay[1]; // rv 0
assign CASDINPA_in[2] = (CASDINPA[2] !== 1'bz) && CASDINPA_delay[2]; // rv 0
assign CASDINPA_in[3] = (CASDINPA[3] !== 1'bz) && CASDINPA_delay[3]; // rv 0
assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB_delay[0]; // rv 0
assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB_delay[1]; // rv 0
assign CASDINPB_in[2] = (CASDINPB[2] !== 1'bz) && CASDINPB_delay[2]; // rv 0
assign CASDINPB_in[3] = (CASDINPB[3] !== 1'bz) && CASDINPB_delay[3]; // rv 0
assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA_delay; // rv 0
assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB_delay; // rv 0
assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A_delay; // rv 1
assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B_delay; // rv 1
assign CASINDBITERR_in = (CASINDBITERR !== 1'bz) && CASINDBITERR_delay; // rv 0
assign CASINSBITERR_in = (CASINSBITERR !== 1'bz) && CASINSBITERR_delay; // rv 0
assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA_delay; // rv 0
assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB_delay; // rv 0
assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A_delay; // rv 1
assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B_delay; // rv 1
assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0
assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0
always @ (*) DINADIN_in = DINADIN_delay;
always @ (*) DINBDIN_in = DINBDIN_delay;
always @ (*) DINPADINP_in = DINPADINP_delay;
always @ (*) DINPBDINP_in = DINPBDINP_delay;
assign ECCPIPECE_in = (ECCPIPECE === 1'bz) || ECCPIPECE_delay; // rv 1
assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN_delay ^ IS_ENARDEN_INVERTED_BIN); // rv 0
assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN_delay ^ IS_ENBWREN_INVERTED_BIN); // rv 0
assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR_delay; // rv 0
assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR_delay; // rv 0
assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE_delay; // rv 1
assign REGCEB_in = (REGCEB === 1'bz) || REGCEB_delay; // rv 1
assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0
assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB_delay ^ IS_RSTRAMB_INVERTED_BIN); // rv 0
assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0
assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB_delay ^ IS_RSTREGB_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
assign WEA_in[0] = (WEA[0] === 1'bz) || WEA_delay[0]; // rv 1
assign WEA_in[1] = (WEA[1] === 1'bz) || WEA_delay[1]; // rv 1
assign WEA_in[2] = (WEA[2] === 1'bz) || WEA_delay[2]; // rv 1
assign WEA_in[3] = (WEA[3] === 1'bz) || WEA_delay[3]; // rv 1
assign WEBWE_in = WEBWE_delay;
`else
always @ (*) ADDRARDADDR_in = ADDRARDADDR;
always @ (*) ADDRBWRADDR_in = ADDRBWRADDR;
assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA; // rv 1
assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB; // rv 1
assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA; // rv 0
assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB; // rv 0
assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA[0]; // rv 0
assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA[10]; // rv 0
assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA[11]; // rv 0
assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA[12]; // rv 0
assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA[13]; // rv 0
assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA[14]; // rv 0
assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA[15]; // rv 0
assign CASDINA_in[16] = (CASDINA[16] !== 1'bz) && CASDINA[16]; // rv 0
assign CASDINA_in[17] = (CASDINA[17] !== 1'bz) && CASDINA[17]; // rv 0
assign CASDINA_in[18] = (CASDINA[18] !== 1'bz) && CASDINA[18]; // rv 0
assign CASDINA_in[19] = (CASDINA[19] !== 1'bz) && CASDINA[19]; // rv 0
assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA[1]; // rv 0
assign CASDINA_in[20] = (CASDINA[20] !== 1'bz) && CASDINA[20]; // rv 0
assign CASDINA_in[21] = (CASDINA[21] !== 1'bz) && CASDINA[21]; // rv 0
assign CASDINA_in[22] = (CASDINA[22] !== 1'bz) && CASDINA[22]; // rv 0
assign CASDINA_in[23] = (CASDINA[23] !== 1'bz) && CASDINA[23]; // rv 0
assign CASDINA_in[24] = (CASDINA[24] !== 1'bz) && CASDINA[24]; // rv 0
assign CASDINA_in[25] = (CASDINA[25] !== 1'bz) && CASDINA[25]; // rv 0
assign CASDINA_in[26] = (CASDINA[26] !== 1'bz) && CASDINA[26]; // rv 0
assign CASDINA_in[27] = (CASDINA[27] !== 1'bz) && CASDINA[27]; // rv 0
assign CASDINA_in[28] = (CASDINA[28] !== 1'bz) && CASDINA[28]; // rv 0
assign CASDINA_in[29] = (CASDINA[29] !== 1'bz) && CASDINA[29]; // rv 0
assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA[2]; // rv 0
assign CASDINA_in[30] = (CASDINA[30] !== 1'bz) && CASDINA[30]; // rv 0
assign CASDINA_in[31] = (CASDINA[31] !== 1'bz) && CASDINA[31]; // rv 0
assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA[3]; // rv 0
assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA[4]; // rv 0
assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA[5]; // rv 0
assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA[6]; // rv 0
assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA[7]; // rv 0
assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA[8]; // rv 0
assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA[9]; // rv 0
assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB[0]; // rv 0
assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB[10]; // rv 0
assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB[11]; // rv 0
assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB[12]; // rv 0
assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB[13]; // rv 0
assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB[14]; // rv 0
assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB[15]; // rv 0
assign CASDINB_in[16] = (CASDINB[16] !== 1'bz) && CASDINB[16]; // rv 0
assign CASDINB_in[17] = (CASDINB[17] !== 1'bz) && CASDINB[17]; // rv 0
assign CASDINB_in[18] = (CASDINB[18] !== 1'bz) && CASDINB[18]; // rv 0
assign CASDINB_in[19] = (CASDINB[19] !== 1'bz) && CASDINB[19]; // rv 0
assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB[1]; // rv 0
assign CASDINB_in[20] = (CASDINB[20] !== 1'bz) && CASDINB[20]; // rv 0
assign CASDINB_in[21] = (CASDINB[21] !== 1'bz) && CASDINB[21]; // rv 0
assign CASDINB_in[22] = (CASDINB[22] !== 1'bz) && CASDINB[22]; // rv 0
assign CASDINB_in[23] = (CASDINB[23] !== 1'bz) && CASDINB[23]; // rv 0
assign CASDINB_in[24] = (CASDINB[24] !== 1'bz) && CASDINB[24]; // rv 0
assign CASDINB_in[25] = (CASDINB[25] !== 1'bz) && CASDINB[25]; // rv 0
assign CASDINB_in[26] = (CASDINB[26] !== 1'bz) && CASDINB[26]; // rv 0
assign CASDINB_in[27] = (CASDINB[27] !== 1'bz) && CASDINB[27]; // rv 0
assign CASDINB_in[28] = (CASDINB[28] !== 1'bz) && CASDINB[28]; // rv 0
assign CASDINB_in[29] = (CASDINB[29] !== 1'bz) && CASDINB[29]; // rv 0
assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB[2]; // rv 0
assign CASDINB_in[30] = (CASDINB[30] !== 1'bz) && CASDINB[30]; // rv 0
assign CASDINB_in[31] = (CASDINB[31] !== 1'bz) && CASDINB[31]; // rv 0
assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB[3]; // rv 0
assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB[4]; // rv 0
assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB[5]; // rv 0
assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB[6]; // rv 0
assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB[7]; // rv 0
assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB[8]; // rv 0
assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB[9]; // rv 0
assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA[0]; // rv 0
assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA[1]; // rv 0
assign CASDINPA_in[2] = (CASDINPA[2] !== 1'bz) && CASDINPA[2]; // rv 0
assign CASDINPA_in[3] = (CASDINPA[3] !== 1'bz) && CASDINPA[3]; // rv 0
assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB[0]; // rv 0
assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB[1]; // rv 0
assign CASDINPB_in[2] = (CASDINPB[2] !== 1'bz) && CASDINPB[2]; // rv 0
assign CASDINPB_in[3] = (CASDINPB[3] !== 1'bz) && CASDINPB[3]; // rv 0
assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA; // rv 0
assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB; // rv 0
assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A; // rv 1
assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B; // rv 1
assign CASINDBITERR_in = (CASINDBITERR !== 1'bz) && CASINDBITERR; // rv 0
assign CASINSBITERR_in = (CASINSBITERR !== 1'bz) && CASINSBITERR; // rv 0
assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA; // rv 0
assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB; // rv 0
assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A; // rv 1
assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B; // rv 1
assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0
assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0
// always @ (CLKARDCLK) begin
// if ((CLKARDCLK === 1'bz) || // rv 0
// (CLKARDCLK === IS_CLKARDCLK_INVERTED_BIN)) CLKARDCLK_in = 1'b0;
// else CLKARDCLK_in = 1'b1;
// end
// always @ (CLKBWRCLK) begin
// if ((CLKBWRCLK === 1'bz) || // rv 0
// (CLKBWRCLK === IS_CLKBWRCLK_INVERTED_BIN)) CLKBWRCLK_in = 1'b0;
// else CLKBWRCLK_in = 1'b1;
// end
always @ (*) DINADIN_in = DINADIN;
always @ (*) DINBDIN_in = DINBDIN;
always @ (*) DINPADINP_in = DINPADINP;
always @ (*) DINPBDINP_in = DINPBDINP;
assign ECCPIPECE_in = (ECCPIPECE === 1'bz) || ECCPIPECE; // rv 1
assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN ^ IS_ENARDEN_INVERTED_BIN); // rv 0
assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN ^ IS_ENBWREN_INVERTED_BIN); // rv 0
assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR; // rv 0
assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR; // rv 0
assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE; // rv 1
assign REGCEB_in = (REGCEB === 1'bz) || REGCEB; // rv 1
assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0
assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB ^ IS_RSTRAMB_INVERTED_BIN); // rv 0
assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0
assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB ^ IS_RSTREGB_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
assign WEA_in[0] = (WEA[0] === 1'bz) || WEA[0]; // rv 1
assign WEA_in[1] = (WEA[1] === 1'bz) || WEA[1]; // rv 1
assign WEA_in[2] = (WEA[2] === 1'bz) || WEA[2]; // rv 1
assign WEA_in[3] = (WEA[3] === 1'bz) || WEA[3]; // rv 1
assign WEBWE_in = WEBWE;
`endif
// internal variables, signals, busses
localparam integer ADDR_WIDTH = 15;
localparam integer INIT_WIDTH = 72;
localparam integer D_WIDTH = 64;
localparam integer DP_WIDTH = 8;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_size = 32768;
localparam mem_depth = mem_size;
localparam memp_depth = mem_size/8;
localparam mem_pad = 64;
localparam memp_pad = 8;
localparam encode = 1'b1;
localparam decode = 1'b0;
//localparam tmp_mem_width = (READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : READ_WIDTH_B;
localparam tmp_mem_width = (READ_WIDTH_A >= READ_WIDTH_B) ? ((READ_WIDTH_A == 0) ? 1 : READ_WIDTH_A) :
READ_WIDTH_B;
localparam tmp_memp_width = (tmp_mem_width < 9) ? 0 :
(tmp_mem_width < 18) ? 1 :
(tmp_mem_width < 36) ? 2 :
(tmp_mem_width < 72) ? 4 : 8;
localparam tmp_mem_depth = mem_size/(tmp_mem_width-tmp_memp_width);
reg [tmp_mem_width-1:0] tmp_mem_tmp = 0;
integer t_coll_min = 50;
integer t_coll_max = 500 - 99;
reg [255:0] INITP_TMP;
reg [255:0] INIT_TMP;
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer raw=0;
integer wb=0;
integer rb=0;
integer rbb=0;
integer rbw=0;
integer wa=0;
integer rd_loops_a = 1;
integer wr_loops_a = 1;
integer rd_loops_b = 1;
integer rd_loops_f = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
wire WREN_ecc;
wire SLEEP_A_int;
wire SLEEP_B_int;
reg [1:0] SLEEP_A_reg = 2'b0;
reg [1:0] SLEEP_B_reg = 2'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
wire ADDRENA_int;
wire ADDRENB_int;
wire RSTREG_B_int;
wire REGCE_B_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
reg CASDOMUXB_reg = 1'b0;
reg CASOREGIMUXB_reg = 1'b0;
wire CASDOMUXB_int;
wire INJECTDBITERR_int;
wire INJECTSBITERR_int;
reg [6:0] error_bit = 7'b0;
reg [DP_WIDTH-1:0] eccparity_reg = 8'h00;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire [INIT_WIDTH/2-1:0] INIT_B_int;
wire [INIT_WIDTH/2-1:0] SRVAL_B_int;
wire mem_wr_en_a;
reg mem_wr_en_a_wf = 1'b0;
reg [D_WIDTH/2-1:0] mem_we_a;
reg [DP_WIDTH/2-1:0] memp_we_a;
wire [D_WIDTH/2-1:0] mem_rm_doutb;
wire [DP_WIDTH/2-1:0] memp_rm_doutb;
wire [D_WIDTH-1:0] mem_rm_a;
wire [D_WIDTH-1:0] mem_rm_b;
wire [D_WIDTH-1:0] mem_wm_a;
wire [D_WIDTH-1:0] mem_wm_b;
reg wr_data_matches = 0;
reg wr_a_data_matches_rd_b_data = 0;
reg wr_b_data_matches_rd_a_data = 0;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
reg [D_WIDTH-1:0] mem_we_b;
reg [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_en_a;
wire mem_rst_a;
reg mem_is_rst_a = 1'b0;
reg first_read = 1'b0;
wire mem_rd_en_b;
wire mem_rst_b;
reg mem_is_rst_b = 1'b0;
reg mem [0 : mem_depth+mem_pad-1];
reg [D_WIDTH/2-1 : 0] mem_wr_a;
reg wr_a_event = 1'b0;
reg wr_a_wf_event = 1'b0;
reg [D_WIDTH-1 : 0] ram_rd_a;
reg [D_WIDTH-1 : 0] mem_rd_a_wf;
reg [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg wr_b_wf_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
reg [D_WIDTH-1 : 0] mem_a_reg_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
reg [D_WIDTH-1 : 0] mem_a_pipe;
reg [D_WIDTH/2-1 : 0] mem_b_reg;
reg [D_WIDTH/2-1 : 0] mem_b_reg_mux;
reg [D_WIDTH/2-1 : 0] mem_b_lat;
reg memp [0 : memp_depth+memp_pad-1];
reg [DP_WIDTH-1 : 0] memp_wr_a;
reg [DP_WIDTH-1 : 0] ramp_rd_a;
reg [DP_WIDTH-1 : 0] memp_rd_a_wf;
reg [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
reg [DP_WIDTH-1 : 0] memp_a_reg_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
reg [DP_WIDTH-1 : 0] memp_a_out;
reg [DP_WIDTH-1 : 0] memp_a_pipe;
reg [DP_WIDTH/2-1 : 0] memp_b_reg;
reg [DP_WIDTH/2-1 : 0] memp_b_reg_mux;
reg [DP_WIDTH/2-1 : 0] memp_b_lat;
reg [DP_WIDTH/2-1 : 0] memp_b_out;
wire dbit_int;
wire sbit_int;
reg dbit_lat = 0;
reg sbit_lat = 0;
reg dbit_pipe = 0;
reg sbit_pipe = 0;
reg dbit_reg = 0;
reg sbit_reg = 0;
wire [8:0] r_a_ecc_ecc;
reg [8:0] r_a_ecc_lat = 9'b0;
reg [8:0] r_a_ecc_pipe = 9'b0;
reg [8:0] r_a_ecc_reg = 9'b0;
reg dbit_ecc;
reg sbit_ecc;
wire [ADDR_WIDTH-1:0] rd_addr_a_mask;
wire [ADDR_WIDTH-1:0] rd_addr_b_mask;
wire [ADDR_WIDTH-1:0] wr_addr_a_mask;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_a_last = 0;
reg [ADDR_WIDTH-1:0] rd_addr_a_last = 0;
reg rd_addr_a_valid = 0;
reg rd_addr_a_nochange = 0;
reg [63:0] rd_addr_a_count = 0;
reg [63:0] rd_addr_a_nocount = 0;
reg [ADDR_WIDTH-1:0] rd_addr_b = 0;
reg [ADDR_WIDTH-1:0] wr_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b_last = 0;
reg [ADDR_WIDTH-1:0] rd_addr_b_last = 0;
reg rd_addr_b_valid = 0;
reg rd_addr_b_nochange = 0;
reg [63:0] rd_addr_b_count = 0;
reg [63:0] rd_addr_b_nocount = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
reg wr_a_rd_b_addr_coll = 1'b0;
reg wr_addr_coll = 1'b0;
reg wr_b_rd_a_addr_coll = 1'b0;
reg [7:0] synd_wr;
reg [7:0] synd_rd;
reg [7:0] synd_ecc;
wire sdp_mode;
wire sdp_mode_wr;
wire sdp_mode_rd;
// clk period for collision window variables
integer t_max_a=3000, t_max_b=3000;
integer clk_period_a=10000, clk_period_b=10000;
reg clk_a_slowest = 1'b0; //victor drc
reg [63:0] total_clks_a=1, total_clks_b=1;
reg clka_toggled=1'b0, clkb_toggled=1'b0;
reg clka_done=1'b0, clkb_done=1'b0;
reg clka_timeout=0, clkb_timeout=0;
reg clka_changed = 1'b0;
reg clkb_changed = 1'b0;
wire clks_done;
reg en_clk_sync = 1'b0;
// define tasks, functions
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
task read_init_file;
reg [tmp_mem_width-1:0] tmp_mem [0:tmp_mem_depth-1];
integer w,d;
begin
$readmemh (INIT_FILE_REG, tmp_mem);
for (d=0;d<tmp_mem_depth;d=d+1) begin
tmp_mem_tmp = tmp_mem[d];
for (w=0;w<tmp_mem_width-tmp_memp_width;w=w+1) begin
mem[d*(tmp_mem_width-tmp_memp_width)+w] = tmp_mem[d][w];
end
if (tmp_memp_width > 0) begin
for (w=0;w<tmp_memp_width;w=w+1) begin
memp[d*tmp_memp_width+w] = tmp_mem[d][tmp_mem_width-tmp_memp_width+w];
end
end
end
end
endtask
reg cas_a_warning = 1'b0;
reg cas_b_warning = 1'b0;
task is_cas_a_connected;
integer i;
begin
cas_a_warning = 1'b0;
if (CASDIMUXA === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDIMUXA signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
for (i=0;i<=31;i=i+1) begin
if (CASDINA[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDINA[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=3;i=i+1) begin
if (CASDINPA[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDINPA[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CASDOMUXA === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUXA signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASDOMUXEN_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUXEN_A signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASINDBITERR === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASINDBITERR signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASINSBITERR === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASINSBITERR signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUXA === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUXA signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUXEN_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUXEN_A signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
end
endtask // is_cas_a_connected
task is_cas_b_connected;
integer i;
begin
cas_b_warning = 1'b0;
if (CASDIMUXB === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDIMUXB signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
for (i=0;i<=31;i=i+1) begin
if (CASDINB[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDINB[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=3;i=i+1) begin
if (CASDINPB[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDINPB[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CASDOMUXB === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUXB signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASDOMUXEN_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUXEN_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASINDBITERR === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASINDBITERR signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASINSBITERR === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASINSBITERR signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUXB === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUXB signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUXEN_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUXEN_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
end
endtask // is_cas_b_connected
assign mem_rst_a = RSTRAMARSTRAM_in;
assign mem_rst_b = sdp_mode ? RSTRAMARSTRAM_in : RSTRAMB_in;
assign INJECTDBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTDBITERR_in;
assign INJECTSBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTSBITERR_in || INJECTDBITERR_in;
wire [35:0] bit_err_pat;
assign bit_err_pat = INJECTDBITERR_int ? 36'h400000004 : INJECTSBITERR_int ? 36'h000000004 : 36'h0;
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDIMUXA_in)
mem_wr_a = {32'h0, CASDINA_in};
else
mem_wr_a = {32'h0, DINADIN_in};
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDIMUXA_in)
memp_wr_a = {4'h0, CASDINPA_in};
else
memp_wr_a = {4'h0, DINPADINP_in};
end
always @ (*) begin
if (INJECTDBITERR_int || INJECTSBITERR_int) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
mem_wr_b = {CASDINB_in, CASDINA_in} ^ {bit_err_pat, 28'h0};
else
mem_wr_b = {DINBDIN_in, DINADIN_in} ^ {bit_err_pat, 28'h0};
end
else if (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
mem_wr_b = {CASDINB_in, CASDINA_in};
else
mem_wr_b = {DINBDIN_in, DINADIN_in};
end
else begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
mem_wr_b = {32'h0, CASDINB_in};
else
mem_wr_b = {32'b0, DINBDIN_in};
end
end
always @ (*) begin
if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) begin
memp_wr_b = synd_wr;
end
else if (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
memp_wr_b = {CASDINPB_in, CASDINPA_in};
else
memp_wr_b = {DINPBDINP_in, DINPADINP_in};
end
else begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
memp_wr_b = {32'h0, CASDINPB_in};
else
memp_wr_b = {32'b0, DINPBDINP_in};
end
end
assign mem_wr_en_a = ~sdp_mode && ENARDEN_in && |WEA_in;
assign mem_rd_en_a = (WRITE_MODE_A_BIN == WRITE_MODE_A_NO_CHANGE) ?
ENARDEN_in && (~mem_wr_en_a || mem_rst_a) : ENARDEN_in;
assign mem_wr_en_b = ENBWREN_in && (sdp_mode ? |WEBWE_in : |WEBWE_in[DP_WIDTH/2-1:0]);
assign mem_rd_en_b = (WRITE_MODE_B_BIN == WRITE_MODE_B_NO_CHANGE) ?
~sdp_mode && ENBWREN_in && (~mem_wr_en_b || mem_rst_b) :
~sdp_mode && ENBWREN_in;
//victor DRC
reg sleep_is_asserted;
reg sleep_is_deasserted;
reg ENARDEN_p1;
reg ENBWREN_p1;
reg SLEEPA_p1;
reg SLEEPA_p2;
reg SLEEPB_p1;
reg SLEEPB_p2;
always @(SLEEP_in) begin
sleep_is_asserted <= 1'b0;
sleep_is_deasserted <= 1'b0;
if (SLEEP_in == 1'b1)
sleep_is_asserted <= 1'b1;
else if (SLEEP_in == 1'b0)
sleep_is_deasserted <= 1'b1;
end
//victor drc #5
always @(posedge CLKARDCLK_in) begin
if (SLEEP_ASYNC_REG == "FALSE") begin
if (sleep_is_asserted && ENARDEN_in)
$display("Error: [Unisim %s-23] DRC : When SLEEP_ASYNC = FALSE, ENA must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge CLKBWRCLK_in) begin
if (SLEEP_ASYNC_REG == "FALSE") begin
if (sleep_is_asserted && ENBWREN_in)
$display("Error: [Unisim %s-23] DRC : When SLEEP_ASYNC = FALSE, ENB must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge CLKARDCLK_in) begin
if (glblGSR)
ENARDEN_p1 <= 1'b0;
else
ENARDEN_p1 <= ENARDEN_in;
end
always @(posedge CLKBWRCLK_in) begin
if (glblGSR)
ENBWREN_p1 <= 1'b0;
else
ENBWREN_p1 <= ENBWREN_in;
end
always @(posedge CLKARDCLK_in or posedge CLKBWRCLK_in) begin
if (SLEEP_ASYNC_REG == "TRUE") begin
if (clk_a_slowest) begin
if (sleep_is_asserted && ENARDEN_p1)
$display("Error: [Unisim %s-23] DRC : When SLEEP_ASYNC = TRUE, ENA must be LOW at least one clock cycle (slowest clock) before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end else begin
if (sleep_is_asserted && ENBWREN_p1)
$display("Error: [Unisim %s-23] DRC : When SLEEP_ASYNC = TRUE, ENB must be LOW at least one clock cycle (slowest clock) before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
end
//victor drc #6
always @(posedge CLKARDCLK_in) begin
if (glblGSR) begin
SLEEPA_p1 <= 1'b0;
SLEEPA_p2 <= 1'b0;
end
else begin
SLEEPA_p1 <= SLEEP_in;
SLEEPA_p2 <= SLEEPA_p1;
end
end
always @(posedge CLKBWRCLK_in) begin
if (glblGSR) begin
SLEEPB_p1 <= 1'b0;
SLEEPB_p2 <= 1'b0;
end
else begin
SLEEPB_p1 <= SLEEP_in;
SLEEPB_p2 <= SLEEPB_p1;
end
end
always @(ENARDEN_in) begin
if (ENARDEN_in && SLEEPA_p2)
$display("Error: [Unisim %s-23] DRC : ENA can be asserted at least 2 cycles CLKARDCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME);
end
always @(ENBWREN_in) begin
if (ENBWREN_in && SLEEPB_p2)
$display("Error: [Unisim %s-23] DRC : ENB can be asserted at least 2 cycles CLKBWRCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME);
end
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE :
CASCADE_ORDER_A_NONE;
assign CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE :
CASCADE_ORDER_B_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign DOA_REG_BIN =
(DOA_REG_REG == 1) ? DOA_REG_1 :
(DOA_REG_REG == 0) ? DOA_REG_0 :
DOA_REG_1;
assign DOB_REG_BIN =
(DOB_REG_REG == 1) ? DOB_REG_1 :
(DOB_REG_REG == 0) ? DOB_REG_0 :
DOB_REG_1;
assign ENADDRENA_BIN =
(ENADDRENA_REG == "FALSE") ? ENADDRENA_FALSE :
(ENADDRENA_REG == "TRUE") ? ENADDRENA_TRUE :
ENADDRENA_FALSE;
assign ENADDRENB_BIN =
(ENADDRENB_REG == "FALSE") ? ENADDRENB_FALSE :
(ENADDRENB_REG == "TRUE") ? ENADDRENB_TRUE :
ENADDRENB_FALSE;
assign EN_ECC_PIPE_BIN =
(EN_ECC_PIPE_REG == "FALSE") ? EN_ECC_PIPE_FALSE :
(EN_ECC_PIPE_REG == "TRUE") ? EN_ECC_PIPE_TRUE :
EN_ECC_PIPE_FALSE;
assign EN_ECC_READ_BIN =
(EN_ECC_READ_REG == "FALSE") ? EN_ECC_READ_FALSE :
(EN_ECC_READ_REG == "TRUE") ? EN_ECC_READ_TRUE :
EN_ECC_READ_FALSE;
assign EN_ECC_WRITE_BIN =
(EN_ECC_WRITE_REG == "FALSE") ? EN_ECC_WRITE_FALSE :
(EN_ECC_WRITE_REG == "TRUE") ? EN_ECC_WRITE_TRUE :
EN_ECC_WRITE_FALSE;
assign INITP_BIN['h00] = INITP_00_REG;
assign INITP_BIN['h01] = INITP_01_REG;
assign INITP_BIN['h02] = INITP_02_REG;
assign INITP_BIN['h03] = INITP_03_REG;
assign INITP_BIN['h04] = INITP_04_REG;
assign INITP_BIN['h05] = INITP_05_REG;
assign INITP_BIN['h06] = INITP_06_REG;
assign INITP_BIN['h07] = INITP_07_REG;
assign INITP_BIN['h08] = INITP_08_REG;
assign INITP_BIN['h09] = INITP_09_REG;
assign INITP_BIN['h0A] = INITP_0A_REG;
assign INITP_BIN['h0B] = INITP_0B_REG;
assign INITP_BIN['h0C] = INITP_0C_REG;
assign INITP_BIN['h0D] = INITP_0D_REG;
assign INITP_BIN['h0E] = INITP_0E_REG;
assign INITP_BIN['h0F] = INITP_0F_REG;
assign INIT_BIN['h00] = INIT_00_REG;
assign INIT_BIN['h01] = INIT_01_REG;
assign INIT_BIN['h02] = INIT_02_REG;
assign INIT_BIN['h03] = INIT_03_REG;
assign INIT_BIN['h04] = INIT_04_REG;
assign INIT_BIN['h05] = INIT_05_REG;
assign INIT_BIN['h06] = INIT_06_REG;
assign INIT_BIN['h07] = INIT_07_REG;
assign INIT_BIN['h08] = INIT_08_REG;
assign INIT_BIN['h09] = INIT_09_REG;
assign INIT_BIN['h0A] = INIT_0A_REG;
assign INIT_BIN['h0B] = INIT_0B_REG;
assign INIT_BIN['h0C] = INIT_0C_REG;
assign INIT_BIN['h0D] = INIT_0D_REG;
assign INIT_BIN['h0E] = INIT_0E_REG;
assign INIT_BIN['h0F] = INIT_0F_REG;
assign INIT_BIN['h10] = INIT_10_REG;
assign INIT_BIN['h11] = INIT_11_REG;
assign INIT_BIN['h12] = INIT_12_REG;
assign INIT_BIN['h13] = INIT_13_REG;
assign INIT_BIN['h14] = INIT_14_REG;
assign INIT_BIN['h15] = INIT_15_REG;
assign INIT_BIN['h16] = INIT_16_REG;
assign INIT_BIN['h17] = INIT_17_REG;
assign INIT_BIN['h18] = INIT_18_REG;
assign INIT_BIN['h19] = INIT_19_REG;
assign INIT_BIN['h1A] = INIT_1A_REG;
assign INIT_BIN['h1B] = INIT_1B_REG;
assign INIT_BIN['h1C] = INIT_1C_REG;
assign INIT_BIN['h1D] = INIT_1D_REG;
assign INIT_BIN['h1E] = INIT_1E_REG;
assign INIT_BIN['h1F] = INIT_1F_REG;
assign INIT_BIN['h20] = INIT_20_REG;
assign INIT_BIN['h21] = INIT_21_REG;
assign INIT_BIN['h22] = INIT_22_REG;
assign INIT_BIN['h23] = INIT_23_REG;
assign INIT_BIN['h24] = INIT_24_REG;
assign INIT_BIN['h25] = INIT_25_REG;
assign INIT_BIN['h26] = INIT_26_REG;
assign INIT_BIN['h27] = INIT_27_REG;
assign INIT_BIN['h28] = INIT_28_REG;
assign INIT_BIN['h29] = INIT_29_REG;
assign INIT_BIN['h2A] = INIT_2A_REG;
assign INIT_BIN['h2B] = INIT_2B_REG;
assign INIT_BIN['h2C] = INIT_2C_REG;
assign INIT_BIN['h2D] = INIT_2D_REG;
assign INIT_BIN['h2E] = INIT_2E_REG;
assign INIT_BIN['h2F] = INIT_2F_REG;
assign INIT_BIN['h30] = INIT_30_REG;
assign INIT_BIN['h31] = INIT_31_REG;
assign INIT_BIN['h32] = INIT_32_REG;
assign INIT_BIN['h33] = INIT_33_REG;
assign INIT_BIN['h34] = INIT_34_REG;
assign INIT_BIN['h35] = INIT_35_REG;
assign INIT_BIN['h36] = INIT_36_REG;
assign INIT_BIN['h37] = INIT_37_REG;
assign INIT_BIN['h38] = INIT_38_REG;
assign INIT_BIN['h39] = INIT_39_REG;
assign INIT_BIN['h3A] = INIT_3A_REG;
assign INIT_BIN['h3B] = INIT_3B_REG;
assign INIT_BIN['h3C] = INIT_3C_REG;
assign INIT_BIN['h3D] = INIT_3D_REG;
assign INIT_BIN['h3E] = INIT_3E_REG;
assign INIT_BIN['h3F] = INIT_3F_REG;
assign INIT_BIN['h40] = INIT_40_REG;
assign INIT_BIN['h41] = INIT_41_REG;
assign INIT_BIN['h42] = INIT_42_REG;
assign INIT_BIN['h43] = INIT_43_REG;
assign INIT_BIN['h44] = INIT_44_REG;
assign INIT_BIN['h45] = INIT_45_REG;
assign INIT_BIN['h46] = INIT_46_REG;
assign INIT_BIN['h47] = INIT_47_REG;
assign INIT_BIN['h48] = INIT_48_REG;
assign INIT_BIN['h49] = INIT_49_REG;
assign INIT_BIN['h4A] = INIT_4A_REG;
assign INIT_BIN['h4B] = INIT_4B_REG;
assign INIT_BIN['h4C] = INIT_4C_REG;
assign INIT_BIN['h4D] = INIT_4D_REG;
assign INIT_BIN['h4E] = INIT_4E_REG;
assign INIT_BIN['h4F] = INIT_4F_REG;
assign INIT_BIN['h50] = INIT_50_REG;
assign INIT_BIN['h51] = INIT_51_REG;
assign INIT_BIN['h52] = INIT_52_REG;
assign INIT_BIN['h53] = INIT_53_REG;
assign INIT_BIN['h54] = INIT_54_REG;
assign INIT_BIN['h55] = INIT_55_REG;
assign INIT_BIN['h56] = INIT_56_REG;
assign INIT_BIN['h57] = INIT_57_REG;
assign INIT_BIN['h58] = INIT_58_REG;
assign INIT_BIN['h59] = INIT_59_REG;
assign INIT_BIN['h5A] = INIT_5A_REG;
assign INIT_BIN['h5B] = INIT_5B_REG;
assign INIT_BIN['h5C] = INIT_5C_REG;
assign INIT_BIN['h5D] = INIT_5D_REG;
assign INIT_BIN['h5E] = INIT_5E_REG;
assign INIT_BIN['h5F] = INIT_5F_REG;
assign INIT_BIN['h60] = INIT_60_REG;
assign INIT_BIN['h61] = INIT_61_REG;
assign INIT_BIN['h62] = INIT_62_REG;
assign INIT_BIN['h63] = INIT_63_REG;
assign INIT_BIN['h64] = INIT_64_REG;
assign INIT_BIN['h65] = INIT_65_REG;
assign INIT_BIN['h66] = INIT_66_REG;
assign INIT_BIN['h67] = INIT_67_REG;
assign INIT_BIN['h68] = INIT_68_REG;
assign INIT_BIN['h69] = INIT_69_REG;
assign INIT_BIN['h6A] = INIT_6A_REG;
assign INIT_BIN['h6B] = INIT_6B_REG;
assign INIT_BIN['h6C] = INIT_6C_REG;
assign INIT_BIN['h6D] = INIT_6D_REG;
assign INIT_BIN['h6E] = INIT_6E_REG;
assign INIT_BIN['h6F] = INIT_6F_REG;
assign INIT_BIN['h70] = INIT_70_REG;
assign INIT_BIN['h71] = INIT_71_REG;
assign INIT_BIN['h72] = INIT_72_REG;
assign INIT_BIN['h73] = INIT_73_REG;
assign INIT_BIN['h74] = INIT_74_REG;
assign INIT_BIN['h75] = INIT_75_REG;
assign INIT_BIN['h76] = INIT_76_REG;
assign INIT_BIN['h77] = INIT_77_REG;
assign INIT_BIN['h78] = INIT_78_REG;
assign INIT_BIN['h79] = INIT_79_REG;
assign INIT_BIN['h7A] = INIT_7A_REG;
assign INIT_BIN['h7B] = INIT_7B_REG;
assign INIT_BIN['h7C] = INIT_7C_REG;
assign INIT_BIN['h7D] = INIT_7D_REG;
assign INIT_BIN['h7E] = INIT_7E_REG;
assign INIT_BIN['h7F] = INIT_7F_REG;
assign INIT_A_BIN = INIT_A_REG;
assign INIT_B_BIN = INIT_B_REG;
// assign INIT_FILE_BIN =
// (INIT_FILE_REG == "NONE") ? INIT_FILE_NONE :
// INIT_FILE_NONE;
assign IS_CLKARDCLK_INVERTED_BIN = IS_CLKARDCLK_INVERTED_REG;
assign IS_CLKBWRCLK_INVERTED_BIN = IS_CLKBWRCLK_INVERTED_REG;
assign IS_ENARDEN_INVERTED_BIN = IS_ENARDEN_INVERTED_REG;
assign IS_ENBWREN_INVERTED_BIN = IS_ENBWREN_INVERTED_REG;
assign IS_RSTRAMARSTRAM_INVERTED_BIN = IS_RSTRAMARSTRAM_INVERTED_REG;
assign IS_RSTRAMB_INVERTED_BIN = IS_RSTRAMB_INVERTED_REG;
assign IS_RSTREGARSTREG_INVERTED_BIN = IS_RSTREGARSTREG_INVERTED_REG;
assign IS_RSTREGB_INVERTED_BIN = IS_RSTREGB_INVERTED_REG;
assign RDADDRCHANGEA_BIN =
(RDADDRCHANGEA_REG == "FALSE") ? RDADDRCHANGEA_FALSE :
(RDADDRCHANGEA_REG == "TRUE") ? RDADDRCHANGEA_TRUE :
RDADDRCHANGEA_FALSE;
assign RDADDRCHANGEB_BIN =
(RDADDRCHANGEB_REG == "FALSE") ? RDADDRCHANGEB_FALSE :
(RDADDRCHANGEB_REG == "TRUE") ? RDADDRCHANGEB_TRUE :
RDADDRCHANGEB_FALSE;
assign READ_WIDTH_A_BIN =
(READ_WIDTH_A_REG == 0) ? READ_WIDTH_A_0 :
(READ_WIDTH_A_REG == 1) ? READ_WIDTH_A_1 :
(READ_WIDTH_A_REG == 2) ? READ_WIDTH_A_2 :
(READ_WIDTH_A_REG == 4) ? READ_WIDTH_A_4 :
(READ_WIDTH_A_REG == 9) ? READ_WIDTH_A_9 :
(READ_WIDTH_A_REG == 18) ? READ_WIDTH_A_18 :
(READ_WIDTH_A_REG == 36) ? READ_WIDTH_A_36 :
(READ_WIDTH_A_REG == 72) ? READ_WIDTH_A_72 :
READ_WIDTH_A_0;
assign READ_WIDTH_B_BIN =
(READ_WIDTH_B_REG == 0) ? READ_WIDTH_B_0 :
(READ_WIDTH_B_REG == 1) ? READ_WIDTH_B_1 :
(READ_WIDTH_B_REG == 2) ? READ_WIDTH_B_2 :
(READ_WIDTH_B_REG == 4) ? READ_WIDTH_B_4 :
(READ_WIDTH_B_REG == 9) ? READ_WIDTH_B_9 :
(READ_WIDTH_B_REG == 18) ? READ_WIDTH_B_18 :
(READ_WIDTH_B_REG == 36) ? READ_WIDTH_B_36 :
READ_WIDTH_B_0;
assign RSTREG_PRIORITY_A_BIN =
(RSTREG_PRIORITY_A_REG == "RSTREG") ? RSTREG_PRIORITY_A_RSTREG :
(RSTREG_PRIORITY_A_REG == "REGCE") ? RSTREG_PRIORITY_A_REGCE :
RSTREG_PRIORITY_A_RSTREG;
assign RSTREG_PRIORITY_B_BIN =
(RSTREG_PRIORITY_B_REG == "RSTREG") ? RSTREG_PRIORITY_B_RSTREG :
(RSTREG_PRIORITY_B_REG == "REGCE") ? RSTREG_PRIORITY_B_REGCE :
RSTREG_PRIORITY_B_RSTREG;
assign SIM_COLLISION_CHECK_BIN =
(SIM_COLLISION_CHECK_REG == "ALL") ? SIM_COLLISION_CHECK_ALL :
(SIM_COLLISION_CHECK_REG == "GENERATE_X_ONLY") ? SIM_COLLISION_CHECK_GENERATE_X_ONLY :
(SIM_COLLISION_CHECK_REG == "NONE") ? SIM_COLLISION_CHECK_NONE :
(SIM_COLLISION_CHECK_REG == "WARNING_ONLY") ? SIM_COLLISION_CHECK_WARNING_ONLY :
SIM_COLLISION_CHECK_ALL;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_A_BIN = SRVAL_A_REG;
assign SRVAL_B_BIN = SRVAL_B_REG;
assign WRITE_MODE_A_BIN =
(WRITE_MODE_A_REG == "NO_CHANGE") ? WRITE_MODE_A_NO_CHANGE :
(WRITE_MODE_A_REG == "READ_FIRST") ? WRITE_MODE_A_READ_FIRST :
(WRITE_MODE_A_REG == "WRITE_FIRST") ? WRITE_MODE_A_WRITE_FIRST :
WRITE_MODE_A_NO_CHANGE;
assign WRITE_MODE_B_BIN =
(WRITE_MODE_B_REG == "NO_CHANGE") ? WRITE_MODE_B_NO_CHANGE :
(WRITE_MODE_B_REG == "READ_FIRST") ? WRITE_MODE_B_READ_FIRST :
(WRITE_MODE_B_REG == "WRITE_FIRST") ? WRITE_MODE_B_WRITE_FIRST :
WRITE_MODE_B_NO_CHANGE;
assign WRITE_WIDTH_A_BIN =
(WRITE_WIDTH_A_REG == 0) ? WRITE_WIDTH_A_0 :
(WRITE_WIDTH_A_REG == 1) ? WRITE_WIDTH_A_1 :
(WRITE_WIDTH_A_REG == 2) ? WRITE_WIDTH_A_2 :
(WRITE_WIDTH_A_REG == 4) ? WRITE_WIDTH_A_4 :
(WRITE_WIDTH_A_REG == 9) ? WRITE_WIDTH_A_9 :
(WRITE_WIDTH_A_REG == 18) ? WRITE_WIDTH_A_18 :
(WRITE_WIDTH_A_REG == 36) ? WRITE_WIDTH_A_36 :
WRITE_WIDTH_A_0;
assign WRITE_WIDTH_B_BIN =
(WRITE_WIDTH_B_REG == 0) ? WRITE_WIDTH_B_0 :
(WRITE_WIDTH_B_REG == 1) ? WRITE_WIDTH_B_1 :
(WRITE_WIDTH_B_REG == 2) ? WRITE_WIDTH_B_2 :
(WRITE_WIDTH_B_REG == 4) ? WRITE_WIDTH_B_4 :
(WRITE_WIDTH_B_REG == 9) ? WRITE_WIDTH_B_9 :
(WRITE_WIDTH_B_REG == 18) ? WRITE_WIDTH_B_18 :
(WRITE_WIDTH_B_REG == 36) ? WRITE_WIDTH_B_36 :
(WRITE_WIDTH_B_REG == 72) ? WRITE_WIDTH_B_72 :
WRITE_WIDTH_B_0;
initial begin
#1;
trig_attr = 1'b1;
#100;
trig_attr = 1'b0;
end
always @ (posedge trig_attr) begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_A_REG != "NONE") &&
(CASCADE_ORDER_A_REG != "FIRST") &&
(CASCADE_ORDER_A_REG != "LAST") &&
(CASCADE_ORDER_A_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-101] CASCADE_ORDER_A attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_B_REG != "NONE") &&
(CASCADE_ORDER_B_REG != "FIRST") &&
(CASCADE_ORDER_B_REG != "LAST") &&
(CASCADE_ORDER_B_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-102] CASCADE_ORDER_B attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON"))) begin
$display("Error: [Unisim %s-103] CLOCK_DOMAINS attribute is set to %s. Legal values for this attribute are INDEPENDENT or COMMON. Instance: %m", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DOA_REG_REG != 1) &&
(DOA_REG_REG != 0))) begin
$display("Error: [Unisim %s-104] DOA_REG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DOA_REG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DOB_REG_REG != 1) &&
(DOB_REG_REG != 0))) begin
$display("Error: [Unisim %s-105] DOB_REG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DOB_REG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENADDRENA_REG != "FALSE") &&
(ENADDRENA_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] ENADDRENA attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENADDRENA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENADDRENB_REG != "FALSE") &&
(ENADDRENB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] ENADDRENB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENADDRENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_PIPE_REG != "FALSE") &&
(EN_ECC_PIPE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] EN_ECC_PIPE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_PIPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_READ_REG != "FALSE") &&
(EN_ECC_READ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] EN_ECC_READ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_READ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WRITE_REG != "FALSE") &&
(EN_ECC_WRITE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] EN_ECC_WRITE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WRITE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RDADDRCHANGEA_REG != "FALSE") &&
(RDADDRCHANGEA_REG != "TRUE"))) begin
$display("Error: [Unisim %s-266] RDADDRCHANGEA attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RDADDRCHANGEA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RDADDRCHANGEB_REG != "FALSE") &&
(RDADDRCHANGEB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-267] RDADDRCHANGEB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RDADDRCHANGEB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_WIDTH_A_REG != 0) &&
(READ_WIDTH_A_REG != 1) &&
(READ_WIDTH_A_REG != 2) &&
(READ_WIDTH_A_REG != 4) &&
(READ_WIDTH_A_REG != 9) &&
(READ_WIDTH_A_REG != 18) &&
(READ_WIDTH_A_REG != 36) &&
(READ_WIDTH_A_REG != 72))) begin
$display("Error: [Unisim %s-268] READ_WIDTH_A attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, READ_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_WIDTH_B_REG != 0) &&
(READ_WIDTH_B_REG != 1) &&
(READ_WIDTH_B_REG != 2) &&
(READ_WIDTH_B_REG != 4) &&
(READ_WIDTH_B_REG != 9) &&
(READ_WIDTH_B_REG != 18) &&
(READ_WIDTH_B_REG != 36))) begin
$display("Error: [Unisim %s-269] READ_WIDTH_B attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36. Instance: %m", MODULE_NAME, READ_WIDTH_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RSTREG_PRIORITY_A_REG != "RSTREG") &&
(RSTREG_PRIORITY_A_REG != "REGCE"))) begin
$display("Error: [Unisim %s-270] RSTREG_PRIORITY_A attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RSTREG_PRIORITY_B_REG != "RSTREG") &&
(RSTREG_PRIORITY_B_REG != "REGCE"))) begin
$display("Error: [Unisim %s-271] RSTREG_PRIORITY_B attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_COLLISION_CHECK_REG != "ALL") &&
(SIM_COLLISION_CHECK_REG != "GENERATE_X_ONLY") &&
(SIM_COLLISION_CHECK_REG != "NONE") &&
(SIM_COLLISION_CHECK_REG != "WARNING_ONLY"))) begin
$display("Error: [Unisim %s-272] SIM_COLLISION_CHECK attribute is set to %s. Legal values for this attribute are ALL, GENERATE_X_ONLY, NONE or WARNING_ONLY. Instance: %m", MODULE_NAME, SIM_COLLISION_CHECK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE"))) begin
$display("Error: [Unisim %s-273] SLEEP_ASYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_MODE_A_REG != "NO_CHANGE") &&
(WRITE_MODE_A_REG != "READ_FIRST") &&
(WRITE_MODE_A_REG != "WRITE_FIRST"))) begin
$display("Error: [Unisim %s-276] WRITE_MODE_A attribute is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST. Instance: %m", MODULE_NAME, WRITE_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_MODE_B_REG != "NO_CHANGE") &&
(WRITE_MODE_B_REG != "READ_FIRST") &&
(WRITE_MODE_B_REG != "WRITE_FIRST"))) begin
$display("Error: [Unisim %s-277] WRITE_MODE_B attribute is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST. Instance: %m", MODULE_NAME, WRITE_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_WIDTH_A_REG != 0) &&
(WRITE_WIDTH_A_REG != 1) &&
(WRITE_WIDTH_A_REG != 2) &&
(WRITE_WIDTH_A_REG != 4) &&
(WRITE_WIDTH_A_REG != 9) &&
(WRITE_WIDTH_A_REG != 18) &&
(WRITE_WIDTH_A_REG != 36))) begin
$display("Error: [Unisim %s-278] WRITE_WIDTH_A attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36. Instance: %m", MODULE_NAME, WRITE_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_WIDTH_B_REG != 0) &&
(WRITE_WIDTH_B_REG != 1) &&
(WRITE_WIDTH_B_REG != 2) &&
(WRITE_WIDTH_B_REG != 4) &&
(WRITE_WIDTH_B_REG != 9) &&
(WRITE_WIDTH_B_REG != 18) &&
(WRITE_WIDTH_B_REG != 36) &&
(WRITE_WIDTH_B_REG != 72))) begin
$display("Error: [Unisim %s-279] WRITE_WIDTH_B attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, WRITE_WIDTH_B_REG);
attr_err = 1'b1;
end
if ((CASCADE_ORDER_A_REG == "LAST") ||
(CASCADE_ORDER_A_REG == "MIDDLE")) begin
is_cas_a_connected;
if (cas_a_warning) $display("Warning: [Unisim %s-126] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if ((CASCADE_ORDER_B_REG == "LAST") ||
(CASCADE_ORDER_B_REG == "MIDDLE")) begin
is_cas_b_connected;
if (cas_b_warning) $display("Warning: [Unisim %s-127] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (attr_err == 1'b1) #100 $finish;
end
initial begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign rd_addr_a_mask =
(READ_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(READ_WIDTH_A_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign rd_addr_b_mask =
(READ_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(READ_WIDTH_B_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_a_mask =
(WRITE_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_A_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_b_mask =
(WRITE_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_B_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_A_BIN) rd_loops_a <= READ_WIDTH_A_BIN;
always @(READ_WIDTH_B_BIN) rd_loops_b <= READ_WIDTH_B_BIN;
always @(*) begin
if (READ_WIDTH_A_BIN > READ_WIDTH_B_BIN) rd_loops_f <= READ_WIDTH_A_BIN;
else rd_loops_f <= READ_WIDTH_B_BIN;
end
always @(WRITE_WIDTH_A_BIN) wr_loops_a <= WRITE_WIDTH_A_BIN;
always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN;
// determine clk period for collision window.
assign clks_done = clka_done && clkb_done;
always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin
clka_timeout = 0;
clka_done = 0;
if (glblGSR) @(negedge glblGSR);
@(posedge CLKARDCLK_in);
@(posedge CLKARDCLK_in);
@(posedge CLKARDCLK_in);
clka_timeout <= #6000 1;
@(posedge CLKARDCLK_in or posedge clka_timeout);
if (~clka_timeout) begin
t_max_a = $time/1.0;
@ (negedge CLKARDCLK_in) t_max_a = $time/1.0 - t_max_a;
end else begin
t_max_a = 2000;
end
clka_done = 1;
end
always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin
@(posedge CLKARDCLK_in)
@(posedge CLKARDCLK_in)
@(posedge CLKARDCLK_in)
@(posedge CLKARDCLK_in)
clk_period_a = $time/1.0;
@(posedge CLKARDCLK_in)
clk_period_a = $time/1.0 - clk_period_a;
clka_toggled = 1'b1;
end
always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin
@(posedge CLKBWRCLK_in)
@(posedge CLKBWRCLK_in)
@(posedge CLKBWRCLK_in)
@(posedge CLKBWRCLK_in)
clk_period_b = $time/1.0;
@(posedge CLKBWRCLK_in)
clk_period_b = $time/1.0 - clk_period_b;
clkb_toggled = 1'b1;
end
//victor drc
always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin
if (clk_period_a <= clk_period_b)
clk_a_slowest <= 1'b0;
else
clk_a_slowest <= 1'b1;
end
always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin
clkb_timeout = 0;
clkb_done = 0;
if (glblGSR) @(negedge glblGSR);
@(posedge CLKBWRCLK_in);
@(posedge CLKBWRCLK_in);
@(posedge CLKBWRCLK_in);
clkb_timeout <= #6000 1;
@(posedge CLKBWRCLK_in or posedge clkb_timeout);
if (~clkb_timeout) begin
t_max_b = $time;
@ (negedge CLKBWRCLK_in) t_max_b = $time - t_max_b;
end else begin
t_max_b = 2000;
end
clkb_done = 1;
end
always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin
@(posedge clks_done);
if (((t_max_a > 50) && (t_max_a <= 1500)) &&
((t_max_b == 0) || (t_max_a <= t_max_b))) t_coll_max = 2 * t_max_a - 99;
if (((t_max_b > 50) && (t_max_b <= 1500)) &&
((t_max_a == 0) || (t_max_b < t_max_a))) t_coll_max = 2 * t_max_b - 99;
if ((t_max_a <= 50) && (t_max_b <= 50)) t_coll_max = 500 -99;
if ((t_max_a > 1500) && (t_max_b > 1500)) t_coll_max = 3000 -99;
end
always @ (posedge CLKARDCLK_in) begin
if (glblGSR) begin
SLEEP_A_reg <= 2'b0;
end
else begin
SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in};
end
end
always @ (posedge CLKBWRCLK_in) begin
if (glblGSR) begin
SLEEP_B_reg <= 2'b0;
end
else begin
SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in};
end
end
assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in;
assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in;
assign sdp_mode_wr = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? 1'b1 : 1'b0;
assign sdp_mode_rd = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ? 1'b1 : 1'b0;
assign sdp_mode = sdp_mode_rd || sdp_mode_wr;
assign REGCE_A_int = REGCEAREGCE_in;
assign REGCE_B_int = REGCEB_in;
assign RSTREG_A_int = (RSTREG_PRIORITY_A_BIN == RSTREG_PRIORITY_A_RSTREG) ?
RSTREGARSTREG_in : (RSTREGARSTREG_in && REGCEAREGCE_in);
assign RSTREG_B_int = (RSTREG_PRIORITY_B_BIN == RSTREG_PRIORITY_B_RSTREG) ?
RSTREGB_in : (RSTREGB_in && REGCEB_in);
assign ADDRENA_int = (ENADDRENA_BIN == ENADDRENA_TRUE) ? ADDRENA_in : 1'b1;
assign ADDRENB_int = (ENADDRENB_BIN == ENADDRENB_TRUE) ? ADDRENB_in : 1'b1;
assign WREN_ecc = ECCPIPECE_in && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && first_read;
assign ECCPARITY_out = eccparity_reg;
assign RDADDRECC_out = (DOA_REG_BIN == DOA_REG_1) ? r_a_ecc_reg : r_a_ecc_ecc;
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin
SBITERR_out = CASINSBITERR_in;
DBITERR_out = CASINDBITERR_in;
end
else if (DOA_REG_BIN == DOA_REG_1) begin
SBITERR_out = sbit_reg;
DBITERR_out = dbit_reg;
end
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin
SBITERR_out = sbit_pipe;
DBITERR_out = dbit_pipe;
end
else begin
SBITERR_out = sbit_lat;
DBITERR_out = dbit_lat;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin
DOUTADOUT_out = CASDINA_in;
DOUTPADOUTP_out = CASDINPA_in;
end
else if (DOA_REG_BIN == DOA_REG_1) begin
DOUTADOUT_out = mem_a_reg ^ mem_rm_douta;
DOUTPADOUTP_out = memp_a_reg ^ memp_rm_douta;
end
else if (mem_wr_en_a_wf) begin
DOUTADOUT_out = mem_rd_a_wf ^ mem_rm_douta;
DOUTPADOUTP_out = memp_rd_a_wf ^ memp_rm_douta;
end
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin
DOUTADOUT_out = mem_a_pipe ^ mem_rm_douta;
DOUTPADOUTP_out = memp_a_pipe ^ memp_rm_douta;
end
else begin
DOUTADOUT_out = mem_a_lat ^ mem_rm_douta;
DOUTPADOUTP_out = memp_a_lat ^ memp_rm_douta;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDOMUXB_int) begin
DOUTBDOUT_out = CASDINB_in;
DOUTPBDOUTP_out = CASDINPB_in;
end
else if (sdp_mode_rd) begin
if (DOA_REG_BIN == DOA_REG_1) begin
DOUTBDOUT_out = mem_a_reg[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_a_reg[7:4] ^ memp_rm_douta[7:4];
end
else if (mem_wr_en_a_wf) begin
DOUTBDOUT_out = mem_rd_a_wf[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_rd_a_wf[7:4] ^ memp_rm_douta[7:4];
end
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin
DOUTBDOUT_out = mem_a_pipe[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_a_pipe[7:4] ^ memp_rm_douta[7:4];
end
else begin
DOUTBDOUT_out = mem_a_lat[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_a_lat[7:4] ^ memp_rm_douta[7:4];
end
end
else begin
if (DOB_REG_BIN == DOB_REG_1) begin
DOUTBDOUT_out = mem_b_reg ^ mem_rm_doutb;
DOUTPBDOUTP_out = memp_b_reg ^ memp_rm_doutb;
end
else if (mem_wr_en_b_wf) begin
DOUTBDOUT_out = mem_rd_b_wf ^ mem_rm_doutb;
DOUTPBDOUTP_out = memp_rd_b_wf ^ memp_rm_doutb;
end
else begin
DOUTBDOUT_out = mem_b_lat ^ mem_rm_doutb;
DOUTPBDOUTP_out = memp_b_lat ^ memp_rm_doutb;
end
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) dbit_ecc = CASINDBITERR_in;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) dbit_ecc = dbit_pipe;
else dbit_ecc = dbit_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) sbit_ecc = CASINSBITERR_in;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) sbit_ecc = sbit_pipe;
else sbit_ecc = sbit_lat;
end
assign r_a_ecc_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? r_a_ecc_pipe : r_a_ecc_lat;
assign INIT_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{INIT_A_BIN[8]}}, {8{INIT_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{INIT_A_BIN[17:16]}}, {4{INIT_A_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{INIT_A_BIN[35:32]}}, {2{INIT_A_BIN[31:0]}}} :
{INIT_B_BIN[35:32],INIT_A_BIN[35:32],INIT_B_BIN[31:0],INIT_A_BIN[31:0]};
assign INIT_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{INIT_B_BIN[8]}}, {4{INIT_B_BIN[7:0]}}} :
(READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{INIT_B_BIN[17:16]}}, {2{INIT_B_BIN[15:0]}}} :
INIT_B_BIN;
assign SRVAL_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{SRVAL_A_BIN[8]}}, {8{SRVAL_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{SRVAL_A_BIN[17:16]}}, {4{SRVAL_A_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{SRVAL_A_BIN[35:32]}}, {2{SRVAL_A_BIN[31:0]}}} :
{SRVAL_B_BIN[35:32],SRVAL_A_BIN[35:32],SRVAL_B_BIN[31:0],SRVAL_A_BIN[31:0]};
assign SRVAL_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{SRVAL_B_BIN[8]}}, {4{SRVAL_B_BIN[7:0]}}} :
(READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{SRVAL_B_BIN[17:16]}}, {2{SRVAL_B_BIN[15:0]}}} :
SRVAL_B_BIN;
// cascade out
assign CASDOUTA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
DOUTADOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
DOUTPADOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASDOUTB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ?
DOUTBDOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ?
DOUTPBDOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASOUTDBITERR_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
DBITERR_out : 1'b0;
assign CASOUTSBITERR_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
SBITERR_out : 1'b0;
// start model internals
// cascade control
always @ (posedge CLKARDCLK_in) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in;
end
always @ (posedge CLKARDCLK_in) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in;
end
assign CASDOMUXB_int = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ?
CASDOMUXA_reg : CASDOMUXB_reg;
always @ (posedge CLKBWRCLK_in) begin
if (glblGSR || sdp_mode) CASDOMUXB_reg <= 1'b0;
else if (CASDOMUXEN_B_in == 1'b1) CASDOMUXB_reg <= CASDOMUXB_in;
end
always @ (posedge CLKBWRCLK_in) begin
if (glblGSR || sdp_mode) CASOREGIMUXB_reg <= 1'b0;
else if (CASOREGIMUXEN_B_in == 1'b1) CASOREGIMUXB_reg <= CASOREGIMUXB_in;
end
// collison detection
reg coll_win_wr_clk_a_min = 1'b0;
reg coll_win_wr_clk_b_min = 1'b0;
reg coll_win_rd_clk_a_min = 1'b0;
reg coll_win_rd_clk_b_min = 1'b0;
reg coll_win_wr_clk_a_max = 1'b0;
reg coll_win_wr_clk_b_max = 1'b0;
reg coll_win_rd_clk_a_max = 1'b0;
reg coll_win_rd_clk_b_max = 1'b0;
reg wr_b_wr_a_coll = 1'b0;
reg wr_b_rd_a_coll = 1'b0;
reg rd_b_wr_a_coll = 1'b0;
reg wr_a_wr_b_coll = 1'b0;
reg wr_a_rd_b_coll = 1'b0;
reg rd_a_wr_b_coll = 1'b0;
wire coll_wr_sim;
wire coll_wr_b_wr_a;
wire coll_wr_b_rd_a_sim;
wire coll_wr_b_rd_a;
//wire coll_rd_b_wr_a_sim;
wire coll_rd_b_wr_a;
wire coll_wr_a_wr_b;
wire coll_wr_a_rd_b_sim;
wire coll_wr_a_rd_b;
//wire coll_rd_a_wr_b_sim;
wire coll_rd_a_wr_b;
assign coll_wr_sim = wr_addr_coll && coll_win_wr_clk_a_min && coll_win_wr_clk_b_min;
assign coll_wr_b_wr_a = wr_addr_coll && coll_win_wr_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_b_rd_a_sim = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && coll_win_rd_clk_a_min;
//assign coll_rd_a_wr_b_sim = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && coll_win_wr_clk_b_min;
assign coll_wr_a_rd_b_sim = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && coll_win_rd_clk_b_min;
//assign coll_rd_b_wr_a_sim = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && coll_win_wr_clk_a_min;
assign coll_wr_b_rd_a = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && ~coll_win_rd_clk_a_min && coll_win_rd_clk_a_max;
assign coll_rd_b_wr_a = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_a_wr_b = wr_addr_coll && coll_win_wr_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
assign coll_wr_a_rd_b = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && ~coll_win_rd_clk_b_min && coll_win_rd_clk_b_max;
assign coll_rd_a_wr_b = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
always @(posedge CLKARDCLK_in) begin
if (mem_wr_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) & ~sdp_mode) begin
if (coll_win_wr_clk_a_max) begin
coll_win_wr_clk_a_max = 1'b0;
if (clks_done) clka_changed = 1'b1;
end else if (clks_done) begin
clka_changed = 1'b0;
coll_win_wr_clk_a_min <= #1 1'b1;
coll_win_wr_clk_a_max <= #99 1'b1;
coll_win_wr_clk_a_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_a_max <= #(t_coll_max) 1'b0;
end
end
end
always @(posedge coll_wr_sim) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-1] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-2] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_wr_b) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-3] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b_last);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-4] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b_last);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-5] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) and a READ on port B (%h) occured.\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-6] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b) begin
if (~wr_a_data_matches_rd_b_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-7] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b_last);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-8] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b_last);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge CLKBWRCLK_in) begin
if (mem_wr_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if (coll_win_wr_clk_b_max) begin
coll_win_wr_clk_b_max = 1'b0;
if (clks_done) clkb_changed = 1'b1;
end else if (clks_done) begin
clkb_changed = 1'b0;
coll_win_wr_clk_b_min <= #1 1'b1;
coll_win_wr_clk_b_max <= #99 1'b1;
coll_win_wr_clk_b_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_b_max <= #(t_coll_max) 1'b0;
end
end
end
always @(posedge coll_wr_b_wr_a) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-9] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a_last);
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-10] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a_last);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-11] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) and READ on port A (%h) occured.\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-12] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a) begin
if (~wr_b_data_matches_rd_a_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-13] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a_last);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-14] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a_last);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge CLKARDCLK_in) begin
if (mem_rd_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if (coll_win_rd_clk_a_max) begin
coll_win_rd_clk_a_max = 1'b0;
if (clks_done) clka_changed = 1'b1;
end else if (clks_done) begin
clka_changed = 1'b0;
coll_win_rd_clk_a_min <= #1 1'b1;
coll_win_rd_clk_a_max <= #99 1'b1;
coll_win_rd_clk_a_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_a_max <= #(t_coll_max) 1'b0;
end
end
end
//always @(posedge coll_rd_a_wr_b_sim) begin
// if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
// if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
// $display("Error: [Unisim %s-15] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
// rd_a_wr_b_coll <= #10 1'b1;
// rd_a_wr_b_coll <= #100 1'b0;
// end
// else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
// $display("Error: [Unisim %s-16] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
// if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
// rd_a_wr_b_coll <= #10 1'b1;
// rd_a_wr_b_coll <= #100 1'b0;
// end
// end
//end
always @(posedge coll_rd_a_wr_b) begin
if (~wr_b_data_matches_rd_a_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-17] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b_last);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-18] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b_last);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge CLKBWRCLK_in) begin
if (mem_rd_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) && ~sdp_mode) begin
if (coll_win_rd_clk_b_max) begin
coll_win_rd_clk_b_max = 1'b0;
if (clks_done) clkb_changed = 1'b1;
end else if (clks_done) begin
clkb_changed = 1'b0;
coll_win_rd_clk_b_min <= #1 1'b1;
coll_win_rd_clk_b_max <= #99 1'b1;
coll_win_rd_clk_b_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_b_max <= #(t_coll_max) 1'b0;
end
end
end
always @(posedge coll_rd_b_wr_a) begin
if (~wr_a_data_matches_rd_b_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-21] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a_last);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-22] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a_last);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
// output register
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) mem_a_reg_mux = {CASDINB_in, CASDINA_in};
else if (mem_wr_en_a_wf) mem_a_reg_mux = mem_rd_a_wf;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) mem_a_reg_mux = mem_a_pipe;
else mem_a_reg_mux = mem_a_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) memp_a_reg_mux = {CASDINPB_in, CASDINPA_in};
else if (mem_wr_en_a_wf) memp_a_reg_mux = memp_rd_a_wf;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) memp_a_reg_mux = memp_a_pipe;
else memp_a_reg_mux = memp_a_lat;
end
always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= #100 INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= #100 mem_a_reg_mux;
memp_a_reg <= #100 memp_a_reg_mux;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) &&
CASOREGIMUXB_reg) mem_b_reg_mux = CASDINB_in;
else if (mem_wr_en_b_wf) mem_b_reg_mux = mem_rd_b_wf;
else mem_b_reg_mux = mem_b_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) &&
CASOREGIMUXB_reg) memp_b_reg_mux = CASDINPB_in;
else if (mem_wr_en_b_wf) memp_b_reg_mux = memp_rd_b_wf;
else memp_b_reg_mux = memp_b_lat;
end
always @ (posedge CLKBWRCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM || sdp_mode) begin
{memp_b_reg, mem_b_reg} <= #100 INIT_B_int;
end
else if (RSTREG_B_int) begin
{memp_b_reg, mem_b_reg} <= #100 SRVAL_B_int;
end
else if (REGCE_B_int) begin
mem_b_reg <= #100 mem_b_reg_mux;
memp_b_reg <= #100 memp_b_reg_mux;
end
end
// bit err reg
always @ (posedge CLKARDCLK_in or glblGSR) begin
if (glblGSR || mem_rst_a) begin
dbit_reg <= 1'b0;
sbit_reg <= 1'b0;
r_a_ecc_reg <= 9'h0;
end
else if (REGCE_A_int) begin
dbit_reg <= dbit_ecc;
sbit_reg <= sbit_ecc;
r_a_ecc_reg <= r_a_ecc_ecc;
end
end
// ecc pipe register
always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_pipe, mem_a_pipe} <= #100 INIT_A_int;
dbit_pipe <= #100 1'b0;
sbit_pipe <= #100 1'b0;
r_a_ecc_pipe <= #100 9'b0;
end
else if (WREN_ecc) begin
mem_a_pipe <= #100 mem_a_lat;
memp_a_pipe <= #100 memp_a_lat;
dbit_pipe <= #100 dbit_lat;
sbit_pipe <= #100 sbit_lat;
r_a_ecc_pipe <= #100 r_a_ecc_lat;
end
end
// read engine
always @ (posedge CLKARDCLK_in) begin
if ((WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) && ~sdp_mode && mem_rd_en_a && ~glblGSR) begin
mem_wr_en_a_wf <= mem_wr_en_a && ~mem_rst_a;
end
end
always @ (posedge CLKBWRCLK_in) begin
if ((WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) && mem_rd_en_b && ~glblGSR) begin
mem_wr_en_b_wf <= mem_wr_en_b && ~mem_rst_b;
end
end
always @ (wr_a_wf_event or INIT_MEM) begin
if (coll_wr_sim || coll_wr_b_wr_a || coll_wr_a_wr_b) begin
for (raw=0;raw<rd_loops_f;raw=raw+1) begin
mem_rd_a_wf[raw] <= 1'bx;
end
if (rd_loops_f >= 8) begin
for (raw=0;raw<rd_loops_f/8;raw=raw+1) begin
memp_rd_a_wf[raw] <= 1'bx;
end
end
end else if (~(coll_rd_a_wr_b || coll_wr_b_rd_a || coll_wr_b_rd_a_sim)) begin
for (raw=0;raw<rd_loops_f;raw=raw+1) begin
mem_rd_a_wf[raw] <= mem [rd_addr_a+raw];
end
if (rd_loops_f >= 8) begin
for (raw=0;raw<rd_loops_f/8;raw=raw+1) begin
memp_rd_a_wf[raw] <= memp [(rd_addr_a/8)+raw];
end
end
end
end
// always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_a_event or wr_b_event or posedge coll_win_rd_clk_b_min or INIT_MEM) begin
// always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_a_event or wr_b_event or posedge wr_b_wr_a_coll or INIT_MEM) begin
always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_a_event or wr_b_event or INIT_MEM) begin
if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin
for (raa=0;raa<rd_loops_a;raa=raa+1) begin
ram_rd_a[raa] = mem [rd_addr_a+raa];
end
if (rd_loops_a >= 8) begin
for (raa=0;raa<rd_loops_a/8;raa=raa+1) begin
ramp_rd_a[raa] = memp [(rd_addr_a/8)+raa];
end
end
end
end
always @(posedge CLKARDCLK_in or posedge INIT_MEM or posedge glblGSR or posedge wr_b_rd_a_coll or posedge rd_a_wr_b_coll or posedge wr_a_wr_b_coll or posedge wr_b_wr_a_coll) begin
if (glblGSR || INIT_MEM) begin
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 INIT_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 INIT_A_int >> (D_WIDTH+ra);
end
end
first_read <= 1'b0;
end
else if (SLEEP_A_int && mem_rd_en_a) begin
$display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 1'bx;
end
end
end
else if (mem_rst_a && mem_rd_en_a) begin
if (~mem_is_rst_a) begin
mem_is_rst_a <= 1'b1;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 SRVAL_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 SRVAL_A_int >> (D_WIDTH+ra);
end
end
end
end
else if (rd_a_wr_b_coll || wr_b_rd_a_coll || wr_a_wr_b_coll || wr_b_wr_a_coll) begin
if (~wr_b_data_matches_rd_a_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 1'bx;
end
end
end
end
else if (mem_rd_en_a) begin
mem_is_rst_a <= 1'b0;
if ((EN_ECC_READ_BIN == EN_ECC_READ_TRUE) && sbit_int) begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) begin
// if (coll_wr_b_rd_a_sim && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) begin
{memp_a_lat, mem_a_lat} <= #100 fn_cor_bit(synd_ecc[6:0], mem_rd_b_rf, memp_rd_b_rf);
end
else begin
{memp_a_lat, mem_a_lat} <= #100 fn_cor_bit(synd_ecc[6:0], ram_rd_a, ramp_rd_a);
end
end
else begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) begin
// if (coll_wr_b_rd_a_sim && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) begin
mem_a_lat <= #100 mem_rd_b_rf;
memp_a_lat <= #100 memp_rd_b_rf;
end
else begin
mem_a_lat <= #100 ram_rd_a;
memp_a_lat <= #100 ramp_rd_a;
end
end
first_read <= 1'b1;
end
end
always @ (wr_b_wf_event) begin
if (coll_wr_sim || coll_wr_b_wr_a || coll_wr_a_wr_b) begin
for (rbw=0;rbw<rd_loops_f;rbw=rbw+1) begin
mem_rd_b_wf[rbw] <= 1'bx;
end
if (rd_loops_f >= 8) begin
for (rbw=0;rbw<rd_loops_f/8;rbw=rbw+1) begin
memp_rd_b_wf[rbw] <= 1'bx;
end
end
end else if (~(coll_rd_b_wr_a || coll_wr_a_rd_b || coll_wr_a_rd_b_sim)) begin
for (rbw=0;rbw<rd_loops_f;rbw=rbw+1) begin
mem_rd_b_wf[rbw] <= mem [rd_addr_b+rbw];
if (rbw<rd_loops_f/8) begin
memp_rd_b_wf[rbw] <= memp [(rd_addr_b/8)+rbw];
end
end
end
end
always @ (rd_addr_b or mem_rd_en_b or mem_rst_b or wr_b_event or wr_a_event or INIT_MEM) begin
if ((mem_rd_en_b || INIT_MEM) && ~mem_rst_b) begin
for (rbb=0;rbb<rd_loops_b;rbb=rbb+1) begin
mem_rd_b[rbb] <= mem [rd_addr_b+rbb];
if (rbb<rd_loops_b/8) begin
memp_rd_b[rbb] <= memp [(rd_addr_b/8)+rbb];
end
end
end
end
always @(posedge CLKBWRCLK_in or posedge INIT_MEM or posedge glblGSR or posedge wr_a_rd_b_coll or posedge rd_b_wr_a_coll or posedge wr_a_wr_b_coll or posedge wr_b_wr_a_coll) begin
if (glblGSR || INIT_MEM) begin
mem_is_rst_b <= 1'b0;
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= #100 INIT_B_int >> rb;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= #100 INIT_B_int >> (D_WIDTH/2+rb);
end
end
end
else if (SLEEP_B_int && mem_rd_en_b && ~sdp_mode) begin
$display("Error: [Unisim %s-24] DRC : READ on port B attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
mem_is_rst_b <= 1'b0;
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= #100 1'bx;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= #100 1'bx;
end
end
end
else if (mem_rst_b && mem_rd_en_b && ~sdp_mode) begin
if (~mem_is_rst_b) begin
mem_is_rst_b <= 1'b1;
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= #100 SRVAL_B_int >> rb;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= #100 SRVAL_B_int >> (D_WIDTH/2+rb);
end
end
end
end
else if (rd_b_wr_a_coll || wr_a_rd_b_coll || wr_a_wr_b_coll || wr_b_wr_a_coll) begin
mem_is_rst_b <= 1'b0;
if (~wr_a_data_matches_rd_b_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= #100 1'bx;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= #100 1'bx;
end
end
end
end
else if (mem_rd_en_b && ~sdp_mode) begin
mem_is_rst_b <= 1'b0;
mem_b_lat <= #100 mem_rd_b[D_WIDTH/2-1:0];
memp_b_lat <= #100 memp_rd_b[DP_WIDTH/2-1:0];
end
end
// write engine
always @ (posedge CLKARDCLK_in or posedge wr_a_wr_b_coll) begin
if (wr_a_wr_b_coll && ~glblGSR) begin
if (~wr_data_matches) begin
for (wa=0;wa<wr_loops_a;wa=wa+1) begin
if (mem_we_a[wa]) mem [wr_addr_a+wa] <= {mem_width{1'bx}};
if (wa<wr_loops_a/8) begin
if (memp_we_a[wa]) memp [(wr_addr_a/8)+wa] <= {memp_width{1'bx}};
end
end
end
end
else if (mem_wr_en_a && ~glblGSR && ~sdp_mode) begin
if (SLEEP_A_int) begin
$display("Error: [Unisim %s-25] DRC : WRITE on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
end
else begin
for (wa=0;wa<wr_loops_a;wa=wa+1) begin
if (mem_we_a[wa]) begin
mem [wr_addr_a+wa] <= mem_wr_a[wa];
end
end
if (wr_loops_a >= 8) begin
for (wa=0;wa<wr_loops_a/8;wa=wa+1) begin
if (memp_we_a[wa]) begin
memp [(wr_addr_a/8)+wa] <= memp_wr_a[wa];
end
end
end
wr_a_event <= ~wr_a_event;
if (WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) wr_a_wf_event <= ~wr_a_wf_event;
end
end
end
always @ (posedge CLKBWRCLK_in or posedge INIT_MEM or posedge wr_b_wr_a_coll) begin
if (INIT_MEM == 1'b1) begin
// initialize memory
if (INIT_FILE_REG != "NONE") begin
if (READ_WIDTH_A != READ_WIDTH_A_REG) begin
$display("Error: [Unisim %s-27] DRC : READ_WIDTH_A (%d) has been changed (%d) through write_attr function. In order to initialize memory via INIT_FILE (%s), the READ_WIDTH must be set by a static parameter. Instance: %m.", MODULE_NAME, READ_WIDTH_A, READ_WIDTH_A_REG, INIT_FILE_REG);
end else if (READ_WIDTH_B != READ_WIDTH_B_REG) begin
$display("Error: [Unisim %s-28] DRC : READ_WIDTH_B (%d) has been changed (%d) through write_attr function. In order to initialize memory via INIT_FILE (%s), the READ_WIDTH must be set by a static parameter. Instance: %m.", MODULE_NAME, READ_WIDTH_B, READ_WIDTH_B_REG, INIT_FILE_REG);
end else begin
read_init_file;
end
end else begin
for (j=0;j<128;j=j+1) begin
INIT_TMP = INIT_BIN[j];
for (i=0;i<256;i=i+1) begin
mem [j*256+i] <= INIT_TMP[i];
end
end
// initialize memory p
for (j=0;j<16;j=j+1) begin
INITP_TMP = INITP_BIN[j];
for (i=0;i<256;i=i+1) begin
memp [j*256+i] <= INITP_TMP[i];
end
end
end
end
else if (wr_b_wr_a_coll && ~glblGSR) begin
if (~wr_data_matches) begin
for (wb=0;wb<wr_loops_b;wb=wb+1) begin
if (mem_we_b[wb]) mem [wr_addr_b+wb] <= {mem_width{1'bx}};
if (wb<wr_loops_b/8) begin
if (memp_we_b[wb]) memp [(wr_addr_b/8)+wb] <= {memp_width{1'bx}};
end
end
end
end
else if (mem_wr_en_b && ~glblGSR) begin
if (SLEEP_B_int) begin
$display("Error: [Unisim %s-26] DRC : WRITE on port B attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
end
else begin
// for (wb=0;wb<max_rd_loops;wb=wb+1) begin
for (wb=0;wb<rd_loops_f;wb=wb+1) begin
mem_rd_b_rf[wb] <= mem [rd_addr_b+wb];
// if (wb<max_rd_loops/8) begin
if (wb<rd_loops_f/8) begin
memp_rd_b_rf[wb] <= memp [rd_addr_b/8+wb];
end
end
for (wb=0;wb<wr_loops_b;wb=wb+1) begin
if (mem_we_b[wb]) begin
mem [wr_addr_b+wb] <= mem_wr_b[wb];
end
end
if (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) begin
for (wb=0;wb<wr_loops_b/8;wb=wb+1) begin
if (memp_we_b[wb]) begin
memp [(wr_addr_b/8)+wb] <= memp_wr_b[wb];
end
end
end
wr_b_event <= ~wr_b_event;
if (WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) wr_b_wf_event <= ~wr_b_wf_event;
end
end
end
assign mem_rm_douta = sdp_mode_rd ? {D_WIDTH{1'b0}} : {D_WIDTH{1'bx}}<<rd_loops_a;
assign memp_rm_douta = sdp_mode_rd ? {DP_WIDTH{1'b0}} : {DP_WIDTH{1'bx}}<<rd_loops_a/8;
assign mem_rm_doutb = sdp_mode_rd ? {D_WIDTH/2{1'b0}} : {D_WIDTH{1'bx}}<<rd_loops_b;
assign memp_rm_doutb = sdp_mode_rd ? {DP_WIDTH/2{1'b0}} : {DP_WIDTH/2{1'bx}}<<rd_loops_b/8;
always @(ADDRARDADDR_in or ADDRENA_int) begin
if (ADDRENA_int == 1'b1) begin
rd_addr_a = ADDRARDADDR_in & rd_addr_a_mask;
wr_addr_a = ADDRARDADDR_in & wr_addr_a_mask;
end
end
always @(posedge CLKARDCLK_in or glblGSR) begin
if (mem_wr_en_a) begin
wr_addr_a_last <= wr_addr_a;
end
if (mem_rd_en_a) begin
rd_addr_a_last <= rd_addr_a;
end
if (glblGSR || mem_wr_en_a || mem_wr_en_b) begin
rd_addr_a_valid <= 1'b0;
end else if (mem_rd_en_a) begin
rd_addr_a_valid <= 1'b1;
end
end
always @(posedge CLKARDCLK_in or glblGSR) begin
if (glblGSR || (RDADDRCHANGEA_BIN == RDADDRCHANGEA_FALSE)) begin
if (rd_addr_a_count != 0) begin
total_clks_a = $time/clk_period_a;
$display("Info: [Unisim %s-27] Power : RDADDRCHANGEA(%s) : (%d) READs were skipped out of (%d) total READs (%.2f %%) on port A. BRAM READ duty cycle (%.2f %%) in (%d) CLKA periods at time %.2f ns. Instance: %m.", MODULE_NAME, RDADDRCHANGEA, rd_addr_a_nocount, rd_addr_a_count, (rd_addr_a_nocount*100.0)/(rd_addr_a_count*1.0), (rd_addr_a_count*100.0)/(total_clks_a*1.0), total_clks_a, $time/1000.0);
end
rd_addr_a_nochange <= 1'b0;
rd_addr_a_count <= 0;
rd_addr_a_nocount <= 0;
end else if (mem_rd_en_a) begin
rd_addr_a_count <= rd_addr_a_count + 1;
if ((rd_addr_a_last === rd_addr_a) && rd_addr_a_valid) begin
rd_addr_a_nochange <= 1'b1;
rd_addr_a_nocount <= rd_addr_a_nocount + 1;
end else begin
rd_addr_a_nochange <= 1'b0;
rd_addr_a_nocount <= rd_addr_a_nocount;
end
end else if (mem_wr_en_a || mem_wr_en_b) begin
rd_addr_a_nochange <= 1'b0;
rd_addr_a_count <= rd_addr_a_count;
rd_addr_a_nocount <= rd_addr_a_nocount;
end
end
always @(ADDRBWRADDR_in or ADDRARDADDR_in or ADDRENB_int or sdp_mode) begin
if (ADDRENB_int == 1'b1) begin
if (sdp_mode == 1'b1) begin
rd_addr_b = ADDRARDADDR_in & rd_addr_a_mask;
end else begin
rd_addr_b = ADDRBWRADDR_in & rd_addr_b_mask;
end
wr_addr_b = ADDRBWRADDR_in & wr_addr_b_mask;
end
end
always @(posedge CLKBWRCLK_in or glblGSR) begin
if (mem_wr_en_b) begin
wr_addr_b_last <= wr_addr_b;
end
if (mem_rd_en_b) begin
rd_addr_b_last <= rd_addr_b;
end
if (glblGSR || mem_wr_en_a || mem_wr_en_b) begin
rd_addr_b_valid <= 1'b0;
end else if (mem_rd_en_b) begin
rd_addr_b_valid <= 1'b1;
end
end
always @(posedge CLKBWRCLK_in or glblGSR) begin
if (glblGSR || (RDADDRCHANGEB_BIN == RDADDRCHANGEB_FALSE)) begin
if (rd_addr_b_count != 0) begin
total_clks_b = $time/clk_period_b;
$display("Info: [Unisim %s-28] Power : RDADDRCHANGEB(%s) : (%d) READs were skipped out of (%d) total READs (%.2f %%) on port B. BRAM READ duty cycle (%.2f %%) in (%d) CLKB periods at time %.2f ns. Instance: %m.", MODULE_NAME, RDADDRCHANGEB, rd_addr_b_nocount, rd_addr_b_count, (rd_addr_b_nocount*100.0)/(rd_addr_b_count*1.0), (rd_addr_b_count*100.0)/(total_clks_b*1.0), total_clks_b, $time/1000.0);
end
rd_addr_b_nochange <= 1'b0;
rd_addr_b_count <= 0;
rd_addr_b_nocount <= 0;
end else if (mem_rd_en_b) begin
rd_addr_b_count <= rd_addr_b_count + 1;
if ((rd_addr_b_last === rd_addr_b) && rd_addr_b_valid) begin
rd_addr_b_nochange <= 1'b1;
rd_addr_b_nocount <= rd_addr_b_nocount + 1;
end else begin
rd_addr_b_nochange <= 1'b0;
rd_addr_b_nocount <= rd_addr_b_nocount;
end
end else if (mem_wr_en_a || mem_wr_en_b) begin
rd_addr_b_nochange <= 1'b0;
rd_addr_b_count <= rd_addr_b_count;
rd_addr_b_nocount <= rd_addr_b_nocount;
end
end
assign mem_rm_a = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_a);
assign mem_rm_b = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_b);
assign mem_wm_a = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a);
assign mem_wm_b = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b);
always @(*) begin
if (~sdp_mode && mem_wr_en_a && mem_rd_en_b && ~mem_wr_en_b && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if ((wr_addr_a_last & rd_addr_b_mask) == (rd_addr_b_last & wr_addr_a_mask)) wr_a_rd_b_addr_coll = 1'b1;
else wr_a_rd_b_addr_coll = 1'b0;
end
else wr_a_rd_b_addr_coll = 1'b0;
end
always @(*) begin
if (~sdp_mode && mem_wr_en_b && mem_wr_en_a && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if ((wr_addr_a_last & wr_addr_b_mask) == (wr_addr_b_last & wr_addr_a_mask)) wr_addr_coll = 1'b1;
else wr_addr_coll = 1'b0;
end
else wr_addr_coll = 1'b0;
end
always @(*) begin
if (mem_wr_en_b && mem_rd_en_a && ~mem_wr_en_a && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if ((wr_addr_b_last & rd_addr_a_mask) == (rd_addr_a_last & wr_addr_b_mask)) wr_b_rd_a_addr_coll = 1'b1;
else wr_b_rd_a_addr_coll = 1'b0;
end
else wr_b_rd_a_addr_coll = 1'b0;
end
always @ (WEA_in or glblGSR) begin
mem_we_a = {{8{WEA_in[3]}},{8{WEA_in[2]}},{8{WEA_in[1]}},{8{WEA_in[0]}}};
if (WRITE_WIDTH_A_BIN > WRITE_WIDTH_A_4) memp_we_a = WEA_in;
else memp_we_a = 4'b0;
end
always @ (WEBWE_in or glblGSR) begin
mem_we_b = {{8{WEBWE_in[7]}},{8{WEBWE_in[6]}},{8{WEBWE_in[5]}},{8{WEBWE_in[4]}},
{8{WEBWE_in[3]}},{8{WEBWE_in[2]}},{8{WEBWE_in[1]}},{8{WEBWE_in[0]}}};
if (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) memp_we_b = WEBWE_in;
else memp_we_b = 8'b0;
end
// eccparity is flopped
always @ (*) begin
if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) synd_wr = 8'b0;
else begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
synd_wr = fn_ecc(encode, {CASDINB_in, CASDINA_in}, {CASDINPB_in, CASDINPA_in});
else
synd_wr = fn_ecc(encode, {DINBDIN_in, DINADIN_in}, {DINPBDINP_in, DINPADINP_in});
end
end
always @ (*) begin
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin
if (coll_wr_b_rd_a_sim && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST))
synd_rd = fn_ecc(decode, mem_rd_b_rf, memp_rd_b_rf);
else
synd_rd = fn_ecc(decode, ram_rd_a, ramp_rd_a);
end
else synd_rd = 8'b0;
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST))
synd_ecc = synd_rd ^ memp_rd_b_rf;
else
synd_ecc = synd_rd ^ ramp_rd_a;
end
else
synd_ecc = 8'b0;
//CR-1055052
if(synd_ecc[7] && synd_ecc[6:0] >71) begin
$display("Error: [Unisim %s-23] DRC : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code. @%0t Instance: %m", $time, MODULE_NAME);
$finish;
end
end
assign sbit_int = (|synd_ecc && synd_ecc[7]);
assign dbit_int = (|synd_ecc && ~synd_ecc[7]);
always @(posedge CLKARDCLK_in) begin
if (mem_rd_en_a && mem_rst_a) begin
sbit_lat <= 1'b0;
dbit_lat <= 1'b0;
error_bit <= 7'b0;
r_a_ecc_lat <= 9'b0;
end
else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin
sbit_lat <= sbit_int;
dbit_lat <= dbit_int;
error_bit <= synd_ecc[6:0];
r_a_ecc_lat <= rd_addr_a[ADDR_WIDTH-1:ADDR_WIDTH-9];
end
end
// assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ?
// fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) :
// {memp_rd_a, mem_rd_a};
always @ (posedge CLKBWRCLK_in or glblGSR) begin
if(glblGSR || (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE))
eccparity_reg <= 8'h00;
else if (ENBWREN_in)
eccparity_reg <= synd_wr;
end
`ifdef XIL_TIMING
reg notifier;
wire clkardclk_en_n;
wire clkardclk_en_p;
wire clkbwrclk_en_n;
wire clkbwrclk_en_p;
assign clkardclk_en_n = IS_CLKARDCLK_INVERTED_BIN;
assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED_BIN;
assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED_BIN;
assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED_BIN;
`endif
specify
(CASDINA *> CASDOUTA) = (0:0:0, 0:0:0);
(CASDINA *> DOUTADOUT) = (0:0:0, 0:0:0);
(CASDINB *> CASDOUTB) = (0:0:0, 0:0:0);
(CASDINB *> DOUTBDOUT) = (0:0:0, 0:0:0);
(CASDINPA *> CASDOUTPA) = (0:0:0, 0:0:0);
(CASDINPA *> DOUTPADOUTP) = (0:0:0, 0:0:0);
(CASDINPB *> CASDOUTPB) = (0:0:0, 0:0:0);
(CASDINPB *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
(CASINDBITERR => CASOUTDBITERR) = (0:0:0, 0:0:0);
(CASINDBITERR => DBITERR) = (0:0:0, 0:0:0);
(CASINSBITERR => CASOUTSBITERR) = (0:0:0, 0:0:0);
(CASINSBITERR => SBITERR) = (0:0:0, 0:0:0);
(CLKARDCLK *> CASDOUTA) = (100:100:100, 100:100:100);
(CLKARDCLK *> CASDOUTB) = (100:100:100, 100:100:100);
(CLKARDCLK *> CASDOUTPA) = (100:100:100, 100:100:100);
(CLKARDCLK *> CASDOUTPB) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOUTADOUT) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOUTBDOUT) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOUTPADOUTP) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOUTPBDOUTP) = (100:100:100, 100:100:100);
(CLKARDCLK *> RDADDRECC) = (100:100:100, 100:100:100);
(CLKARDCLK => CASOUTDBITERR) = (100:100:100, 100:100:100);
(CLKARDCLK => CASOUTSBITERR) = (100:100:100, 100:100:100);
(CLKARDCLK => DBITERR) = (100:100:100, 100:100:100);
(CLKARDCLK => SBITERR) = (100:100:100, 100:100:100);
(CLKBWRCLK *> CASDOUTB) = (100:100:100, 100:100:100);
(CLKBWRCLK *> CASDOUTPB) = (100:100:100, 100:100:100);
(CLKBWRCLK *> DOUTBDOUT) = (100:100:100, 100:100:100);
(CLKBWRCLK *> DOUTPBDOUTP) = (100:100:100, 100:100:100);
(CLKBWRCLK *> ECCPARITY) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKARDCLK, 0:0:0, notifier);
$period (negedge CLKBWRCLK, 0:0:0, notifier);
$period (posedge CLKARDCLK, 0:0:0, notifier);
$period (posedge CLKBWRCLK, 0:0:0, notifier);
$setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEB_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEB_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEB_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEB_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEBWE_delay);
$width (negedge CLKARDCLK, 0:0:0, 0, notifier);
$width (negedge CLKBWRCLK, 0:0:0, 0, notifier);
$width (posedge CLKARDCLK, 0:0:0, 0, notifier);
$width (posedge CLKBWRCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
module antiDroopIIR (
input clk,
input trig,
input signed [12:0] din,
input signed [6:0] tapWeight,
input accClr_en,
//input oflowClr,
(* shreg_extract = "no" *) output reg oflowDetect = 1'd0,
//output reg signed [12:0] dout = 13'sd0);
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15).
//`define ADDPIPEREG
reg signed [12:0] din_del = 13'sd0;
`ifdef ADDPIPEREG reg signed [12:0] din_del_b = 13'sd0;
`endif
reg signed [47:0] tap = 48'sd0;
reg signed [19:0] multreg = 20'sd0;
(* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0;
wire trig_edge = trig_a & ~trig_b;
//reg trig_edge = 1'b0;
//(* shreg_extract = "no", keep = "yes" *) reg signed [6:0] tapWeight_a = 7'sd0;
(* shreg_extract = "no" *) reg signed [6:0] tapWeight_a = 7'sd0;
(* shreg_extract = "no" *) reg signed [6:0] tapWeight_b = 7'sd0;
//(* shreg_extract = "no" *) reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0;
//(* shreg_extract = "no" *) reg signed [6:0] tapWeight_c = 7'sd0;// tapWeight_d = 'sd0;
always @(posedge clk) begin
//trig_edge <= trig_a & ~trig_b;
tapWeight_a <= tapWeight;
tapWeight_b <= tapWeight_a;
//tapWeight_c <= tapWeight_b;
//tapWeight_d <= tapWeight_c;
trig_a <= trig;
trig_b <= trig_a;
din_del <= din;
`ifdef ADDPIPEREG
din_del_b <= din_del;
multreg <= din_del*tapWeight_b;
//dout <= din_del_b + tap[IIR_scale+12:IIR_scale];
`else
multreg <= din*tapWeight_b;
dout <= {din_del, 3'b000} + tap[IIR_scale+12:IIR_scale-3];
//dout <= din_del + tap[IIR_scale+12:IIR_scale];
`endif
if (trig_edge && accClr_en) tap <= 48'd0;
else tap <= multreg + tap;
//tap <= din*tapWeight + tap;
//if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
//else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if (^ tap[IIR_scale+13:IIR_scale+12]) oflowDetect <= 1'b1;
//else oflowDetect <= oflowDetect;
oflowDetect <= (^tap[IIR_scale+13:IIR_scale+12]) ? 1'b1 : 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_1_V
`define SKY130_FD_SC_HS__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_1_V
|
/*
* cla_adder_4bit.v - 4 bit carry lookahead adder
*/
`include "cla_full_adder.v"
`ifndef _cla_adder_4bit
`define _cla_adder_4bit
module cla_adder_4bit(
input wire [3:0] a,
input wire [3:0] b,
input wire c_in,
output wire [3:0] s,
output wire c_out);
wire [4:0] c;
wire [3:0] g, p;
assign c[0] = c_in;
assign c_out = c[4];
cla_full_adder add0(.a(a[0]), .b(b[0]), .c(c[0]),
.g(g[0]), .p(p[0]), .s(s[0]));
assign c[1] = g[0] | (p[0] & c[0]);
cla_full_adder add1(.a(a[1]), .b(b[1]), .c(c[1]),
.g(g[1]), .p(p[1]), .s(s[1]));
/*assign c[2] = g[1] | (p[1] & c[1]);*/
assign c[2] = g[1] | (p[1] & (g[0] | (p[0] & c[0])));
cla_full_adder add2(.a(a[2]), .b(b[2]), .c(c[2]),
.g(g[2]), .p(p[2]), .s(s[2]));
/*assign c[3] = g[2] | (p[2] & c[2]);*/
assign c[3] = g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0])))));
cla_full_adder add3(.a(a[3]), .b(b[3]), .c(c[3]),
.g(g[3]), .p(p[3]), .s(s[3]));
/*assign c[4] = g[3] | (p[3] & c[3]);*/
assign c[4] = g[3] | (p[3] &
(g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0])))))));
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: init_mem_pattern_ctr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/24 00:08:32 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel has a small FSM to control the operation of
// memc_traffic_gen module.It first fill up the memory with a selected
// DATA pattern and then starts the memory testing state.
//Reference:
//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
// and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6"
// The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
// 1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during
// memory testing phase.
// 1.3 1-4-2012 Fixed end address logic if defined END_ADDRESS == 0x0FFFFFFF.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_init_mem_pattern_ctr #
(
parameter SIMULATION = "FALSE",
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6", // VIRTEX6, SPARTAN6
parameter MEM_TYPE = "DDR3",//DDR3,DDR2, QDR2PLUS,
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
// "R_W_INSTR_MODE" - Random Read/Write commands will be generated.
parameter MEM_BURST_LEN = 8, // VIRTEX 6 Option.
parameter nCK_PER_CLK = 4,
parameter BL_WIDTH = 10,
parameter NUM_DQ_PINS = 4, // Total number of memory dq pins in the design.
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_ALL" option generates all available
// commands pattern.
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00000fff,
parameter ADDR_WIDTH = 30,
parameter DWIDTH = 32,
parameter CMD_SEED_VALUE = 32'h12345678,
parameter DATA_SEED_VALUE = 32'hca345675,
parameter DATA_MODE = 4'b0010,
parameter PORT_MODE = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE"
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory
// signals. It overwrites the TST_MEM_INSTR_MODE setting.
// Traffic Generator will onlywrite to one single location and no
// read transactions will be generated.
)
(
input clk_i,
input rst_i,
input single_write_button,
input single_read_button,
input slow_write_read_button,
input single_operation, // tie this signal to '1' if want to do single operation
input memc_cmd_en_i,
input memc_wr_en_i,
input vio_modify_enable, // 0: default to ADDR as DATA PATTERN. No runtime change in data mode.
// 1: enable exteral VIO to control the data_mode pattern
input [3:0] vio_instr_mode_value, // "0000" = Fixed
// "0001" = bram; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0111" = Single Step
// and address mode pattern during runtime.
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [1:0] vio_bl_mode_value,
input vio_data_mask_gen,
input [2:0] vio_fixed_instr_value,
input [BL_WIDTH - 1:0] vio_fixed_bl_value, // valid range is: from 1 to 64.
input memc_init_done_i,
input cmp_error,
output reg run_traffic_o,
// runtime parameter
output [31:0] start_addr_o, // define the start of address
output [31:0] end_addr_o,
output [31:0] cmd_seed_o, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
output [31:0] data_seed_o,
output reg load_seed_o, //
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
output reg [2:0] addr_mode_o, // "00" = bram; takes the address from bram output
// "001" = fixed address from the fixed_addr input
// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "011" = sequential
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
output reg [3:0] instr_mode_o, // "0000" = Fixed
// "0001" = bram; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0111" = Single Step
// "1111" = Debug Read Only, bypass memory initialization
output reg [1:0] bl_mode_o, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
output reg [3:0] data_mode_o, // "00" = bram;
// "01" = fixed data from the fixed_data input
// "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR
// "11" = sequential using the addrs as the starting data pattern
output reg mode_load_o,
// fixed pattern inputs interface
output reg [BL_WIDTH-1:0] fixed_bl_o, // range from 1 to 64
output reg [2:0] fixed_instr_o, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
output reg mem_pattern_init_done_o
);
//FSM State Defination
parameter IDLE = 8'b00000001,
INIT_MEM_WRITE = 8'b00000010,
INIT_MEM_READ = 8'b00000100,
TEST_MEM = 8'b00001000,
SINGLE_STEP_WRITE = 8'b00010000, //0x10
SINGLE_STEP_READ = 8'b00100000, //0x20
CMP_ERROR = 8'b01000000,
SINGLE_CMD_WAIT = 8'b10000000;
localparam BRAM_ADDR = 3'b000;
localparam FIXED_ADDR = 3'b001;
localparam PRBS_ADDR = 3'b010;
localparam SEQUENTIAL_ADDR = 3'b011;
localparam BRAM_INSTR_MODE = 4'b0000;
localparam FIXED_INSTR_MODE = 4'b0001;
localparam R_W_INSTR_MODE = 4'b0010;
localparam RP_WP_INSTR_MODE = 4'b0011;
localparam R_RP_W_WP_INSTR_MODE = 4'b0100;
localparam R_RP_W_WP_REF_INSTR_MODE = 4'b0101;
localparam BRAM_BL_MODE = 2'b00;
localparam FIXED_BL_MODE = 2'b01;
localparam PRBS_BL_MODE = 2'b10;
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
// type fixed instruction
localparam RD_INSTR = 3'b001;
localparam RDP_INSTR = 3'b011;
localparam WR_INSTR = 3'b000;
localparam WRP_INSTR = 3'b010;
localparam REFRESH_INSTR = 3'b100;
localparam NOP_WR_INSTR = 3'b101;
//(* FSM_ENCODING="USER" *) reg [6:0] STATE = current_state;
reg [7:0] current_state;
reg [7:0] next_state;
reg memc_init_done_reg;
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
reg upper_end_matched;
reg [31:0] end_boundary_addr;
reg memc_cmd_en_r;
reg lower_end_matched;
reg end_addr_reached;
reg run_traffic;
reg bram_mode_enable;
reg [31:0] current_address;
reg [BL_WIDTH-1:0] fix_bl_value;
reg [3:0] data_mode_sel;
reg [1:0] bl_mode_sel;
reg [2:0] addr_mode;
reg [10:0] INC_COUNTS;
wire [3:0] test_mem_instr_mode;
reg pre_instr_switch;
reg switch_instr;
reg memc_wr_en_r;
reg mode_load_d1,mode_load_d2,mode_load_pulse;
reg mode_load_d3,mode_load_d4,mode_load_d5;
always @ (posedge clk_i) begin
mode_load_d1 <= #TCQ mode_load_o;
mode_load_d2 <= #TCQ mode_load_d1;
mode_load_d3 <= #TCQ mode_load_d2;
mode_load_d4 <= #TCQ mode_load_d3;
mode_load_d5 <= #TCQ mode_load_d4;
end
always @ (posedge clk_i)
mode_load_pulse <= #TCQ mode_load_d4 & ~mode_load_d5;
always @ (TST_MEM_INSTR_MODE, EYE_TEST)
if ((TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || TST_MEM_INSTR_MODE == "R_W_INSTR_MODE" ||
TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" || TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" ||
TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" || TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE" )
&& (EYE_TEST == "TRUE"))
begin: Warning_Message1
$display("Invalid Parameter setting! When EYE_TEST is set to TRUE, only WRITE commands can be generated.");
$stop;
end
else
begin: NoWarning_Message1
end
always @ (TST_MEM_INSTR_MODE)
if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "SPARTAN6")
begin
$display("Error ! Not supported test instruction mode in Spartan 6");
$stop;
end
else
begin
// dummy
end
always @ (vio_fixed_bl_value,vio_data_mode_value)
if (vio_fixed_bl_value[6:0] > 7'd64 && FAMILY == "SPARTAN6")
begin
$display("Error ! Maximum User Burst Length is 64");
$display("Change a smaller burst size");
$stop;
end
else if ((vio_data_mode_value == 4'h6 || vio_data_mode_value == 4'h5) && FAMILY == "VIRTEX6")
begin
$display("Data DQ bus Walking 1's test.");
$display("A single DQ bit is set to 1 and walk through entire DQ bus to test ");
$display("if each DQ bit can be set to 0 or 1 ");
if (NUM_DQ_PINS == 8)begin
$display("Warning ! Fixed Burst Length in this mode is forced to 64");
$display("to ensure '1' always appear on DQ0 of each beginning User Burst");
end
else begin
$display("Warning ! Fixed Burst Length in this mode is forced to equal to NUM_DQ_PINS");
$display("to ensure '1' always appear on DQ0 of each beginning User Burst");
end
end
else
begin// dummy
end
always @ (data_mode_o)
if (data_mode_o == 4'h7 && FAMILY == "SPARTAN6")
begin
$display("Error ! Hammer PRBS is not support in MCB-like interface");
$display("Set value to 4'h8 for Psuedo PRBS");
$stop;
end
else
begin
// dummy
end
//always @ (vio_data_mode_value,TST_MEM_INSTR_MODE)
//if (TST_MEM_INSTR_MODE != "FIXED_INSTR_R_MODE" &&
// vio_data_mode_value == 4'b1000)
//begin
//$display("Error ! The selected PRBS data pattern has to run together with FIXED_INSTR_R_MODE");
//$display("Set the TST_MEM_INSTR_MODE = FIXED_INSTR_R_MODE and addr_mode to sequential mode");
//$stop;
//end
assign test_mem_instr_mode = (vio_instr_mode_value[3:2] == 2'b11) ? 4'b1111:
(vio_instr_mode_value[3:2] == 2'b10) ? 4'b1011:
(TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE") ? 4'b0000:
(TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" ||
TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") ? 4'b0001:
(TST_MEM_INSTR_MODE == "R_W_INSTR_MODE") ? 4'b0010:
(TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0011:
(TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0100:
(TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0101:
4'b0010;
always @ (posedge clk_i)
begin
if (data_mode_o == 4)
begin
fix_bl_value[4:0] <= 5'd8;//Simple_Data_MODE;
fix_bl_value[BL_WIDTH-1:5] <= 'b0;
end
else if (data_mode_o == 5 || data_mode_o == 6 )
if (MEM_TYPE == "RLD3" && vio_modify_enable)
fix_bl_value <= vio_fixed_bl_value;
else
if (NUM_DQ_PINS == 8)
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
else
fix_bl_value <= NUM_DQ_PINS;//Waling 1's or 0's;
else if (data_mode_o == 8)
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
else if (vio_modify_enable == 1'b1)
if (vio_fixed_bl_value == 0) // not valid value;
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
else begin
fix_bl_value <= vio_fixed_bl_value;
end
else
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
end
generate
if (FAMILY == "SPARTAN6" )
begin : INC_COUNTS_S
always @ (posedge clk_i)
INC_COUNTS <= (DWIDTH/8);
end
else // VIRTEX 6
begin : INC_COUNTS_V
always @ (posedge clk_i)
if (MEM_TYPE == "QDR2PLUS")
INC_COUNTS <= 1;// Each address is associated with 4 words in QDR2.
else
INC_COUNTS <= MEM_BURST_LEN;
end
endgenerate
// In V6, each write command in MEM_BLEN = 8, TG writes 8 words of DQ width data to the accessed location.
// For MEM_BLEN = 4, TG writes 4 words of DQ width data to the accessed location.
reg Cout_b;
always @ (posedge clk_i)
begin
if (rst_i)
current_address <= BEGIN_ADDRESS;
else if (memc_wr_en_r && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE"))
|| (memc_wr_en_r && (current_state == IDLE && PORT_MODE == "RD_MODE")) )
// ** current_address stops incrementing when reaching the beginning of last END_ADDRESS write burst.
{Cout_b,current_address} <= current_address + INC_COUNTS;
else
current_address <= current_address;
end
always @ (posedge clk_i)
begin
if (rst_i)
AC3_G_E3 <= 1'b0;
else if (current_address[29:24] >= end_boundary_addr[29:24])
AC3_G_E3 <= 1'b1;
else
AC3_G_E3 <= AC3_G_E3;
if (rst_i)
AC2_G_E2 <= 1'b0;
else if (current_address[23:16] >= end_boundary_addr[23:16])
AC2_G_E2 <= AC3_G_E3;
else
AC2_G_E2 <= AC2_G_E2;
if (rst_i)
AC1_G_E1 <= 1'b0;
else if (current_address[15:8] >= end_boundary_addr[15:8] )
AC1_G_E1 <= AC2_G_E2 & AC3_G_E3;
else
AC1_G_E1 <= AC1_G_E1;
end
always @(posedge clk_i)
begin
if (rst_i)
upper_end_matched <= 1'b0;
else if (memc_cmd_en_i)
upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1;
else
upper_end_matched <= upper_end_matched;
end
//synthesis translate_off
always @ (fix_bl_value)
if(fix_bl_value * MEM_BURST_LEN > END_ADDRESS)
begin
$display("Error ! User Burst Size goes beyond END Address");
$display("decrease vio_fixed_bl_value or increase END Address range");
$stop;
end
else
begin
// dummy
end
always @ (vio_data_mode_value, vio_data_mask_gen)
if(vio_data_mode_value != 4'b0010 && vio_data_mask_gen)
begin
$display("Error ! Data Mask Generation only supported in Data Mode = Address as Data");
$stop;
end
else
begin
// dummy
end
//synthesis translate_on
reg COuta;
always @(posedge clk_i)
begin
// **end_boundary_addr defination is the beginning address of the last write burst of END_ADDRESS
{COuta,end_boundary_addr} <= (END_ADDRESS[31:0] - {{32-BL_WIDTH{1'b0}} ,fix_bl_value } +1) ;
end
always @(posedge clk_i)
begin
if ((current_address[7:4] >= END_ADDRESS[7:4]) && MEM_TYPE == "QDR2PLUS")
lower_end_matched <= 1'b1;
else if ((current_address[7:0] >= end_boundary_addr[7:0]) && MEM_TYPE != "QDR2PLUS")
lower_end_matched <= 1'b1;
else
lower_end_matched <= 1'b0;
end
always @(posedge clk_i)
begin
if (rst_i)
pre_instr_switch <= 1'b0;
else if (current_address[7:0] >= end_boundary_addr[7:0] ) // V6 send a seed address to memc_flow_ctr
pre_instr_switch <= 1'b1;
end
always @(posedge clk_i)
begin
//if (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6" && MEM_TYPE == "QDR2PLUS")
// end_addr_reached <= 1'b1;
if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) ||
(upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) ||
(upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") ||
(upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6"))
end_addr_reached <= 1'b1;
else
end_addr_reached <= 1'b0;
end
always @(posedge clk_i)
begin
if ((upper_end_matched && pre_instr_switch && FAMILY == "VIRTEX6"))
switch_instr <= 1'b1;
else
switch_instr <= 1'b0;
end
always @ (posedge clk_i)
begin
memc_wr_en_r <= memc_wr_en_i;
memc_init_done_reg <= memc_init_done_i;
end
always @ (posedge clk_i)
run_traffic_o <= run_traffic;
always @ (posedge clk_i)
begin
if (rst_i)
current_state <= 5'b00001;
else
current_state <= next_state;
end
assign start_addr_o = BEGIN_ADDRESS;//BEGIN_ADDRESS;
assign end_addr_o = END_ADDRESS;
assign cmd_seed_o = CMD_SEED_VALUE;
assign data_seed_o = DATA_SEED_VALUE;
//
always @ (posedge clk_i)
begin
if (rst_i)
mem_pattern_init_done_o <= 1'b0;
else if (current_address >= end_boundary_addr )
mem_pattern_init_done_o <= 1'b1;
end
reg [3:0] syn1_vio_data_mode_value;
reg [2:0] syn1_vio_addr_mode_value;
always @ (posedge clk_i)
begin
if (rst_i) begin
syn1_vio_data_mode_value <= 4'b0011;
syn1_vio_addr_mode_value <= 3'b011;
end
else if (vio_modify_enable == 1'b1) begin
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE;
end
else if (vio_modify_enable == 1'b1) begin
data_mode_sel <= syn1_vio_data_mode_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i )
bl_mode_sel <= FIXED_BL_MODE;
else if (test_mem_instr_mode[3])
bl_mode_sel <= 2'b11;
else if (vio_modify_enable == 1'b1) begin
bl_mode_sel <= vio_bl_mode_value;
end
end
always @ (posedge clk_i)
begin
// whenever vio_instr_mode_value[3] == 1'b1, TG expects reading back phy calibration data pattern
// which is: 0xFF, 0x00, 0xAA,0x55, 0x55, 0xAA, 0x99 and 0x66.
if (vio_modify_enable)
if (vio_instr_mode_value == 4'h7)
data_mode_o <= 4'h1; // fixed data input
else
data_mode_o <= (test_mem_instr_mode[3]) ? 4'b1000: data_mode_sel;
else
data_mode_o <= DATA_MODE;
addr_mode_o <= (test_mem_instr_mode[3]) ? 3'b000: addr_mode ;
// assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero
// user wants to have bram interface.
if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1)
bram_mode_enable <= 1'b1;
else
bram_mode_enable <= 1'b0;
end
reg single_write_r1,single_write_r2,single_read_r1,single_read_r2;
reg single_instr_run_trarric;
reg slow_write_read_button_r1,slow_write_read_button_r2;
reg toggle_start_stop_write_read;
wire int_single_wr,int_single_rd;
reg [8:0] write_read_counter;
always @ (posedge clk_i)
begin
if (rst_i) begin
write_read_counter <= 'b0;
slow_write_read_button_r1 <= 1'b0;
slow_write_read_button_r2 <= 1'b0;
toggle_start_stop_write_read <= 1'b0;
end
else begin
write_read_counter <= write_read_counter + 1;
slow_write_read_button_r1 <= slow_write_read_button;
slow_write_read_button_r2 <= slow_write_read_button_r1;
if (~slow_write_read_button_r2 && slow_write_read_button_r1)
toggle_start_stop_write_read <= ~toggle_start_stop_write_read;
end
end
assign int_single_wr = write_read_counter[8];
assign int_single_rd = ~write_read_counter[8];
always @ (posedge clk_i)
begin
if (rst_i)
begin
single_write_r1 <= 1'b0;
single_write_r2 <= 1'b0;
single_read_r1 <= 1'b0;
single_read_r2 <= 1'b0;
end
else begin
single_write_r1 <= single_write_button | (int_single_wr & toggle_start_stop_write_read);
single_write_r2 <= single_write_r1 ;
single_read_r1 <= single_read_button | (int_single_rd & toggle_start_stop_write_read);
single_read_r2 <= single_read_r1 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i)
single_instr_run_trarric <= 1'b0;
else if ((single_write_r1 && ~single_write_r2) || (single_read_r1 && ~single_read_r2))
single_instr_run_trarric <= 1'b1;
else if (mode_load_o)
single_instr_run_trarric <= 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i)
run_traffic <= 1'b0;
else if ((current_state == SINGLE_CMD_WAIT ) || (current_state == SINGLE_STEP_WRITE ) || (current_state == SINGLE_STEP_READ ))
run_traffic <= single_instr_run_trarric;
else if ((current_state == SINGLE_CMD_WAIT ) )
run_traffic <= 1'b0;
else if ( (current_state != IDLE))
run_traffic <= 1'b1;
else
run_traffic <= 1'b0;
end
always @ (*)
begin
load_seed_o = 1'b0;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
addr_mode = 'b0;
else
addr_mode = SEQUENTIAL_ADDR;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = 'b0;
else
instr_mode_o = FIXED_INSTR_MODE;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
bl_mode_o = 'b0;
else
bl_mode_o = FIXED_BL_MODE;
if (vio_modify_enable)
if (vio_instr_mode_value == 7)
fixed_bl_o = 10'd1;
else if (data_mode_o[2:0] == 3'b111)
if (FAMILY == "VIRTEX6")
fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256.
else
fixed_bl_o = 10'd64;
else
if (FAMILY == "VIRTEX6")
fixed_bl_o = vio_fixed_bl_value;
// PRBS mode
else if (data_mode_o[3:0] == 4'b1000 && FAMILY == "SPARTAN6")
fixed_bl_o = 10'd64; //
else
fixed_bl_o = fix_bl_value;
else
fixed_bl_o = fix_bl_value;
// fixed_bl_o = 10'd64;
// fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256.
mode_load_o = 1'b0;
// run_traffic = 1'b0;
next_state = IDLE;
if (PORT_MODE == "RD_MODE")
fixed_instr_o = RD_INSTR;
else //if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")
fixed_instr_o = WR_INSTR;
case(current_state)
IDLE:
begin
if(memc_init_done_reg ) //rdp_rdy_i comes from read_data path
begin
if (vio_instr_mode_value == 4'h7 && single_write_r1 && ~single_write_r2)
begin
next_state = SINGLE_STEP_WRITE;
mode_load_o = 1'b1;
// run_traffic = 1'b1;
load_seed_o = 1'b1;
end
else if (vio_instr_mode_value == 4'h7 && single_read_r1 && ~single_read_r2)
begin
next_state = SINGLE_STEP_READ;
mode_load_o = 1'b1;
// run_traffic = 1'b1;
load_seed_o = 1'b1;
end
else if ((PORT_MODE == "WR_MODE" || (PORT_MODE == "BI_MODE" && test_mem_instr_mode[3:2] != 2'b11)) &&
vio_instr_mode_value != 4'h7 ) // normal test mode
begin
next_state = INIT_MEM_WRITE;
mode_load_o = 1'b1;
// run_traffic = 1'b0;
load_seed_o = 1'b1;
end
else if ((PORT_MODE == "RD_MODE" && end_addr_reached || (test_mem_instr_mode == 4'b1111)) &&
vio_instr_mode_value != 4'h7 )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
// run_traffic = 1'b1;
load_seed_o = 1'b1;
end
else
begin
next_state = IDLE;
// run_traffic = 1'b0;
load_seed_o = 1'b0;
end
end
else
begin
next_state = IDLE;
// run_traffic = 1'b0;
load_seed_o = 1'b0;
end
end
SINGLE_CMD_WAIT: begin
if (single_operation&& single_read_r1 && ~single_read_r2)
next_state = SINGLE_STEP_READ;
else
next_state = SINGLE_CMD_WAIT;
fixed_instr_o = RD_INSTR;
addr_mode = FIXED_ADDR;
bl_mode_o = FIXED_BL_MODE;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
end
SINGLE_STEP_WRITE: begin
// run_traffic = single_instr_run_trarric;
if (memc_cmd_en_i)
next_state = IDLE;
else
next_state = SINGLE_STEP_WRITE;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
addr_mode = FIXED_ADDR;
bl_mode_o = FIXED_BL_MODE;
fixed_instr_o = WR_INSTR;
end
SINGLE_STEP_READ: begin //0x20
// run_traffic = single_instr_run_trarric;
if (single_operation)
next_state = SINGLE_CMD_WAIT;
else if (memc_cmd_en_i)
next_state = IDLE;
else
next_state = SINGLE_STEP_READ;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
// run_traffic = 1'b1;
addr_mode = FIXED_ADDR;
bl_mode_o = FIXED_BL_MODE;
fixed_instr_o = RD_INSTR;
end
INIT_MEM_WRITE: begin
if (end_addr_reached && EYE_TEST == "FALSE" )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
// run_traffic = 1'b1;
end
else
begin
next_state = INIT_MEM_WRITE;
// run_traffic = 1'b1;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
if (EYE_TEST == "TRUE")
addr_mode = FIXED_ADDR;
else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
addr_mode = 'b0;
else
addr_mode = SEQUENTIAL_ADDR;
if (switch_instr && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE")
fixed_instr_o = RD_INSTR;
else
fixed_instr_o = WR_INSTR;
end
end
INIT_MEM_READ: begin
if (end_addr_reached )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
end
else
begin
next_state = INIT_MEM_READ;
// run_traffic = 1'b0;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
end
end
TEST_MEM: begin
if (single_operation)
next_state = SINGLE_CMD_WAIT;
else if (cmp_error)
next_state = TEST_MEM;//CMP_ERROR;
else
next_state = TEST_MEM;
// run_traffic = 1'b1;
if (vio_modify_enable)
fixed_instr_o = vio_fixed_instr_value;
else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
fixed_instr_o = WR_INSTR;
else if (PORT_MODE == "BI_MODE" && ( TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" ||
TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE"))
fixed_instr_o = RD_INSTR;
else if (PORT_MODE == "RD_MODE")
fixed_instr_o = RD_INSTR;
else //if( PORT_MODE == "WR_MODE")
fixed_instr_o = WR_INSTR;
if ((data_mode_o == 3'b111) && FAMILY == "VIRTEX6")
fixed_bl_o = 10'd256;
else if ((FAMILY == "SPARTAN6"))
fixed_bl_o = 10'd64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o = fix_bl_value;
if (data_mode_o == 3'b111)
bl_mode_o = FIXED_BL_MODE;
else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
bl_mode_o = FIXED_BL_MODE;
else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110)
// simplify the downstream logic, data_mode is forced to FIXED_BL_MODE
// if data_mode is set to Walking 1's or Walking 0's.
bl_mode_o = FIXED_BL_MODE;
else
bl_mode_o = bl_mode_sel ;
/* if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
addr_mode = SEQUENTIAL_ADDR;
else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110)
// simplify the downstream logic, addr_mode is forced to SEQUENTIAL
// if data_mode is set to Walking 1's or Walking 0's.
// This ensure the starting burst address always in in the beginning
// of burst_length address for the number of DQ pins.And to ensure the
// DQ0 always asserts at the beginning of each user burst.
addr_mode = SEQUENTIAL_ADDR;
else if (bl_mode_o == PRBS_BL_MODE)
addr_mode = PRBS_ADDR;
else
addr_mode = 3'b010;*/
addr_mode = vio_addr_mode_value;
if (vio_modify_enable )
instr_mode_o = vio_instr_mode_value;
else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "VIRTEX6")
instr_mode_o = FIXED_INSTR_MODE;
else if(PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE != "FIXED_INSTR_R_EYE_MODE")
if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = BRAM_INSTR_MODE;
else
instr_mode_o = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
else //if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin
instr_mode_o = FIXED_INSTR_MODE;
end
CMP_ERROR:
begin
next_state = CMP_ERROR;
bl_mode_o = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE;
fixed_instr_o = RD_INSTR;
addr_mode = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR;
if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = BRAM_INSTR_MODE;//
else
instr_mode_o = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
// run_traffic = 1'b1; // ?? keep it running or stop if error happened
end
default:
begin
next_state = IDLE;
//run_traffic = 1'b0;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLXTN_FUNCTIONAL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlxtn (
Q ,
D ,
GATE_N
);
// Module ports
output Q ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
not not0 (GATE , GATE_N );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//sata_command_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
`define RESET_TIMEOUT 32'h00000002
module sata_command_layer (
input rst, //reset
input linkup,
input clk,
input data_in_clk,
input data_in_clk_valid,
input data_out_clk,
input data_out_clk_valid,
//User Interface
output command_layer_ready,
output reg sata_busy,
input send_sync_escape,
input [15:0] user_features,
//XXX: New Stb
// input write_data_stb,
// input read_data_stb,
output hard_drive_error,
input execute_command_stb,
input command_layer_reset,
output reg pio_data_ready,
input [7:0] hard_drive_command,
input [15:0] sector_count,
input [47:0] sector_address,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output user_din_empty,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
//Transfer Layer Interface
input transport_layer_ready,
output reg sync_escape,
output t_send_command_stb,
output reg t_send_control_stb,
output t_send_data_stb,
input t_dma_activate_stb,
input t_d2h_reg_stb,
input t_pio_setup_stb,
input t_d2h_data_stb,
input t_dma_setup_stb,
input t_set_device_bits_stb,
input t_remote_abort,
input t_xmit_error,
input t_read_crc_error,
//PIO
input t_pio_response,
input t_pio_direction,
input [15:0] t_pio_transfer_count,
input [7:0] t_pio_e_status,
//Host to Device Register Values
output [7:0] h2d_command,
output reg [15:0] h2d_features,
output [7:0] h2d_control,
output [3:0] h2d_port_mult,
output [7:0] h2d_device,
output [47:0] h2d_lba,
output [15:0] h2d_sector_count,
//Device to Host Register Values
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
output d2h_error_bbk, //Bad Block
output d2h_error_unc, //Uncorrectable Error
output d2h_error_mc, //Removable Media Error
output d2h_error_idnf, //request sector's ID Field could not be found
output d2h_error_mcr, //Removable Media Error
output d2h_error_abrt, //Abort (from invalid command, drive not ready, write fault)
output d2h_error_tk0nf, //Track 0 not found
output d2h_error_amnf, //Data Address Mark is not found after finding correct ID
output d2h_status_bsy, //Set to 1 when drive has access to command block, no other bits are valid when 1
// Set after reset
// Set after soft reset (srst)
// Set immediately after host writes to command register
output d2h_status_drdy, //Drive is ready to accept command
output d2h_status_dwf, //Drive Write Fault
output d2h_status_dsc, //Drive Seek Complete
output d2h_status_drq, //Data Request, Drive is ready to send data to the host
output d2h_status_corr, //Correctable Data bit (an error that was encountered but was corrected)
output d2h_status_idx, //once per disc revolution this bit is set to one then back to zero
output d2h_status_err, //error bit, if this bit is high check the error flags
//command layer data interface
input t_if_strobe,
output [31:0] t_if_data,
output t_if_ready,
input t_if_activate,
output [23:0] t_if_size,
input t_of_strobe,
input [31:0] t_of_data,
output [1:0] t_of_ready,
input [1:0] t_of_activate,
output [23:0] t_of_size,
//Debug
output [3:0] cl_c_state,
output [3:0] cl_w_state
);
//Parameters
parameter IDLE = 4'h0;
parameter PIO_WAIT_FOR_DATA = 4'h1;
parameter PIO_WRITE_DATA = 4'h2;
parameter WAIT_FOR_DMA_ACT = 4'h1;
parameter WAIT_FOR_WRITE_DATA = 4'h2;
parameter SEND_DATA = 4'h3;
//Registers/Wires
reg [3:0] cntrl_state;
reg srst;
reg [7:0] status;
wire idle;
reg cntrl_send_data_stb;
reg send_command_stb;
wire dev_busy;
wire dev_data_req;
//Write State Machine
reg [3:0] write_state;
reg dma_send_data_stb;
reg dma_act_detected_en;
reg enable_tl_data_ready;
//Ping Pong FIFOs
wire [1:0] if_write_ready;
wire [1:0] if_write_activate;
wire [23:0] if_write_size;
wire if_write_strobe;
wire [31:0] if_write_data;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire if_reset;
wire [31:0] of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_read_size;
wire of_write_strobe;
wire out_fifo_starved;
wire of_read_ready;
wire [31:0] of_read_data;
wire of_read_activate;
wire [23:0] of_write_size;
wire of_read_strobe;
wire of_reset;
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_in (
.reset (if_reset ), //XXX: Veify that new PPFIFO doesn't need an external reset
//write side
//XXX: This can be different clocks
.write_clock (data_in_clk ),
.write_data (if_write_data ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_size ),
.write_strobe (if_write_strobe ),
//.starved (if_starved ),
.starved (user_din_empty ),
//read side
//XXX: This can be different clocks
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data ),
.inactive ( )
);
//Output FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_out (
.reset (of_reset ),
//.reset (0),
//write side
//XXX: This can be different clocks
.write_clock (clk ),
.write_data (of_write_data ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
//.starved (out_fifo_starved ),
.starved ( ),
//read side
//XXX: This can be different clocks
.read_clock (data_out_clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data ),
.inactive ( )
);
//Asynchronous Logic
//Attach output of Input FIFO to TL
assign t_if_ready = if_read_ready && enable_tl_data_ready;
assign t_if_size = if_read_size;
assign t_if_data = if_read_data;
assign if_read_activate = t_if_activate;
assign if_read_strobe = t_if_strobe;
//Attach input of output FIFO to TL
assign t_of_ready = of_write_ready;
//assign t_of_size = of_write_size;
assign t_of_size = 24'h00800;
assign of_write_data = t_of_data;
assign of_write_activate = t_of_activate;
assign of_write_strobe = t_of_strobe;
assign of_reset = (rst && data_out_clk_valid);
assign if_reset = (rst && data_in_clk_valid);
assign if_write_data = user_din;
assign if_write_strobe = user_din_stb;
assign user_din_ready = if_write_ready;
assign if_write_activate = user_din_activate;
assign user_din_size = if_write_size;
assign user_dout = of_read_data;
assign user_dout_ready = of_read_ready;
assign of_read_activate = user_dout_activate;
assign user_dout_size = of_read_size;
assign of_read_strobe = user_dout_stb;
assign d2h_status_bsy = d2h_status[7];
assign d2h_status_drdy = d2h_status[6];
assign d2h_status_dwf = d2h_status[5];
assign d2h_status_dsc = d2h_status[4];
assign d2h_status_drq = d2h_status[3];
assign d2h_status_corr = d2h_status[2];
assign d2h_status_idx = d2h_status[1];
assign d2h_status_err = d2h_status[0];
assign d2h_error_bbk = d2h_error[7];
assign d2h_error_unc = d2h_error[6];
assign d2h_error_mc = d2h_error[5];
assign d2h_error_idnf = d2h_error[4];
assign d2h_error_mcr = d2h_error[3];
assign d2h_error_abrt = d2h_error[2];
assign d2h_error_tk0nf = d2h_error[1];
assign d2h_error_amnf = d2h_error[0];
//Strobes
//assign t_send_command_stb = read_data_stb || write_data_stb || execute_command_stb;
assign t_send_command_stb = execute_command_stb;
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
//IDLE
assign idle = (cntrl_state == IDLE) &&
(write_state == IDLE) &&
transport_layer_ready;
assign command_layer_ready = idle;
assign h2d_command = hard_drive_command;
assign h2d_sector_count = sector_count;
assign h2d_lba = sector_address;
//XXX: The individual bits should be controlled directly
assign h2d_control = {5'h00, srst, 2'b00};
//XXX: This should be controlled from a higher level
assign h2d_port_mult = 4'h0;
//XXX: This should be controlled from a higher level
assign h2d_device = `D2H_REG_DEVICE;
assign dev_busy = status[`STATUS_BUSY_BIT];
assign dev_data_req = status[`STATUS_DRQ_BIT];
assign hard_drive_error = status[`STATUS_ERR_BIT];
assign cl_c_state = cntrl_state;
assign cl_w_state = write_state;
//Synchronous Logic
//Control State Machine
always @ (posedge clk) begin
if (rst || (!linkup)) begin
cntrl_state <= IDLE;
h2d_features <= `D2H_REG_FEATURES;
srst <= 0;
//Strobes
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
status <= 0;
sata_busy <= 0;
sync_escape <= 0;
end
else begin
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
//Reset Count
if (t_d2h_reg_stb) begin
//Receiving a register strobe from the device
sata_busy <= 0;
h2d_features <= `D2H_REG_FEATURES;
end
/*
if (t_send_command_stb || t_send_control_stb) begin
sata_busy <= 1;
end
*/
if (execute_command_stb) begin
h2d_features <= user_features;
sata_busy <= 1;
end
case (cntrl_state)
IDLE: begin
//Soft Reset will break out of any flow
if (command_layer_reset && !srst) begin
srst <= 1;
t_send_control_stb <= 1;
end
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//User Initiated commands
if (!command_layer_reset && srst) begin
srst <= 0;
t_send_control_stb <= 1;
end
end
//Device Initiated Transfers
if(t_pio_setup_stb) begin
if (t_pio_direction) begin
//Read from device
cntrl_state <= PIO_WAIT_FOR_DATA;
end
else begin
//Write to device
cntrl_state <= PIO_WRITE_DATA;
end
end
if (t_set_device_bits_stb) begin
status <= d2h_status;
//status register was updated
end
if (t_d2h_reg_stb) begin
status <= d2h_status;
end
end
PIO_WAIT_FOR_DATA: begin
if (t_d2h_data_stb) begin
//the next peice of data is related to the PIO
pio_data_ready <= 1;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
PIO_WRITE_DATA: begin
if (if_read_activate) begin
cntrl_send_data_stb <= 0;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
default: begin
cntrl_state <= IDLE;
end
endcase
if (send_sync_escape) begin
cntrl_state <= IDLE;
sync_escape <= 1;
sata_busy <= 0;
end
end
end
//Write State Machine
always @ (posedge clk) begin
if (rst || !linkup) begin
write_state <= IDLE;
dma_send_data_stb <= 0;
enable_tl_data_ready <= 0;
dma_act_detected_en <= 0;
end
else begin
dma_send_data_stb <= 0;
if (t_dma_activate_stb) begin
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
dma_act_detected_en <= 1;
end
case (write_state)
IDLE: begin
enable_tl_data_ready <= 0;
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//if (write_data_stb) begin
if (dma_act_detected_en) begin
//send a request to write data
write_state <= WAIT_FOR_DMA_ACT;
end
end
end
WAIT_FOR_DMA_ACT: begin
if (dma_act_detected_en) begin
dma_act_detected_en <= 0;
enable_tl_data_ready <= 1;
write_state <= WAIT_FOR_WRITE_DATA;
end
end
WAIT_FOR_WRITE_DATA: begin
if (if_read_activate) begin
enable_tl_data_ready <= 0;
write_state <= SEND_DATA;
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
//Send the Data FIS
dma_send_data_stb <= 1;
dma_act_detected_en <= 0;
write_state <= IDLE;
end
end
default: begin
write_state <= IDLE;
end
endcase
//if (command_layer_reset || !reset_timeout) begin
if (command_layer_reset) begin
//Break out of the normal flow and return to IDLE
write_state <= IDLE;
end
if (t_d2h_reg_stb) begin
//Whenever I read a register transfer from the device I need to go back to IDLE
write_state <= IDLE;
end
if (send_sync_escape) begin
write_state <= IDLE;
end
end
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests the magic $signed system function.
*/
module main;
reg [3:0] a;
initial begin
a = 4'd12;
// The expression should not change the bit pattern in any way
if ($signed(a) !== 4'b1100) begin
$display("FAILED -- $signed(%b) === %b", a, $signed(a));
$finish;
end
if ($signed(a) == 4) begin
$display("FAILED -- $signed(%b) == 4", a);
$finish;
end
// The >= should do a signed comparison here.
if ($signed(a) >= 0) begin
$display("FAILED -- $signed(%b) > 0", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spd module
*/
`include "spdu.v"
`include "demux2to4.v"
`include "selector.v"
module spd (d0, d1, d2, d3, pm0, pm1, pm2, pm3, out, clk, reset);
// outputs
output out;
// inputs
input d0, d1, d2, d3;
input [3:0] pm0, pm1, pm2, pm3;
input clk, reset;
// wires
wire out;
wire selectord0, selectord1;
wire spdu0out0, spdu0out1, spdu0out2, spdu0out3;
wire spdu1out0, spdu1out1, spdu1out2, spdu1out3;
wire spdu2out0, spdu2out1, spdu2out2, spdu2out3;
wire spdu3out0, spdu3out1, spdu3out2, spdu3out3;
wire spdu4out0, spdu4out1, spdu4out2, spdu4out3;
wire spdu5out0, spdu5out1, spdu5out2, spdu5out3;
wire spdu6out0, spdu6out1, spdu6out2, spdu6out3;
wire spdu7out0, spdu7out1, spdu7out2, spdu7out3;
wire spdu8out0, spdu8out1, spdu8out2, spdu8out3;
wire spdu9out0, spdu9out1, spdu9out2, spdu9out3;
wire spdu10out0, spdu10out1, spdu10out2, spdu10out3;
wire spdu11out0, spdu11out1, spdu11out2, spdu11out3;
wire spdu12out0, spdu12out1, spdu12out2, spdu12out3;
wire spdu13out0, spdu13out1, spdu13out2, spdu13out3;
wire spdu14out0, spdu14out1, spdu14out2, spdu14out3;
spdu spdu0(1'b0,
1'b0,
1'b1,
1'b1, d0, d1, d2, d3,
spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, clk, reset);
spdu spdu1(spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, d0, d1, d2, d3,
spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, clk, reset);
spdu spdu2(spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, d0, d1, d2, d3,
spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, clk, reset);
spdu spdu3(spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, d0, d1, d2, d3,
spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, clk, reset);
spdu spdu4(spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, d0, d1, d2, d3,
spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, clk, reset);
spdu spdu5(spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, d0, d1, d2, d3,
spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, clk, reset);
spdu spdu6(spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, d0, d1, d2, d3,
spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, clk, reset);
spdu spdu7(spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, d0, d1, d2, d3,
spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, clk, reset);
spdu spdu8(spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, d0, d1, d2, d3,
spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, clk, reset);
spdu spdu9(spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, d0, d1, d2, d3,
spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, clk, reset);
spdu spdu10(spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, d0, d1, d2, d3,
spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, clk, reset);
spdu spdu11(spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, d0, d1, d2, d3,
spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, clk, reset);
spdu spdu12(spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, d0, d1, d2, d3,
spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, clk, reset);
spdu spdu13(spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, d0, d1, d2, d3,
spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, clk, reset);
spdu spdu14(spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, d0, d1, d2, d3,
spdu14out0,
spdu14out1,
spdu14out2,
spdu14out3, clk, reset);
selector selector1 (pm0, pm1, pm2, pm3, selectord0, selectord1);
demux demux1 (spdu14out0, spdu14out1, spdu14out2, spdu14out3,
selectord0, selectord1, out);
endmodule
|
module peripherals (
input clk,
input nrst,
output reg[31:0] data_out,
input wire[31:0] data_in,
input wire[5:0] addr,
input cs,
input oe,
input[3:0] wstrb,
// PORTA
inout[7:0] porta,
// PORTB
inout[7:0] portb,
// SDCARD
input sdcard_sck,
input sdcard_mosi,
output sdcard_miso,
// UART related
input rxd,
output wire txd,
// TIMER0
output timer0_comp_irq
);
wire [7:0] porta_pinx;
reg [7:0] porta_portx;
reg [7:0] porta_ddrx;
wire [7:0] portb_pinx;
reg [7:0] portb_portx;
reg [7:0] portb_ddrx;
reg [10:0] ser_out = ~0;
reg [8:0] ser_in = ~0;
reg [15:0] ser_tx_cnt = 0;
reg [15:0] ser_rx_cnt = 0;
reg [7:0] ser_rx_data;
reg [15:0] ser_brr;
reg ser_rxc;
reg ser_fe;
reg ser_dor;
reg rxd_s;
assign txd = ser_out[0];
reg ocie0, ocf0;
reg [23:0] tcnt0, ocr0;
assign timer0_comp_irq = ocie0 && ocf0;
tri_buf tri_buf_porta_inst[7:0](.out(porta_portx), .in(porta_pinx),
.en(porta_ddrx), .pin(porta));
tri_buf tri_buf_portb_inst[7:0](
.out ({portb_portx[7:3],
{sdcard_mosi, sdcard_sck},
portb_portx[0]}),
.in (portb_pinx),
.en ({portb_ddrx[7:4], 1'b0, portb_ddrx[2:0]}),
.pin (portb));
assign sdcard_miso = portb_pinx[3];
always @(posedge clk)
if (~nrst) begin
porta_portx <= 8'h00;
porta_ddrx <= 8'h00;
portb_portx <= 8'h00;
portb_ddrx <= 8'h00;
ser_out <= ~0;
ser_in <= ~0;
ser_tx_cnt <= 0;
ser_rx_cnt <= 0;
ser_brr <= 0;
ser_rx_data <= 8'h00;
ser_rxc <= 1'b0;
ser_fe <= 1'b0;
ser_dor <= 1'b0;
rxd_s <= 1'b1;
ocie0 <= 1'b0;
ocf0 <= 1'b0;
tcnt0 <= 0;
ocr0 <= 0;
end else begin
if (ser_tx_cnt == 0) begin
ser_out <= {1'b1,ser_out[10:1]};
ser_tx_cnt <= ser_brr;
end else
ser_tx_cnt <= ser_tx_cnt - 1;
if (ser_rx_cnt == 0) begin
ser_rx_cnt <= ser_brr;
if (!ser_in[0]) begin
ser_rx_data <= ser_in[8:1];
ser_fe <= ~rxd_s;
ser_dor <= ser_rxc;
ser_rxc <= 1'b1;
ser_in <= ~0;
end else
ser_in <= { rxd_s, ser_in[8:1] };
end else if (&ser_in && rxd_s) // if (ser_rx_cnt == 0)
ser_rx_cnt <= ser_brr >> 1;
else
ser_rx_cnt <= ser_rx_cnt - 1;
rxd_s <= rxd;
if(cs && oe && addr == 6'h08) begin
/* UDR0 is read, clear RXC0, FE0, and DOR0 */
ser_rxc <= 1'b0;
ser_fe <= 1'b0;
ser_dor <= 1'b0;
end
if (tcnt0 == ocr0) begin
tcnt0 <= 0;
ocf0 <= 1'b1;
end else
tcnt0 <= tcnt0 + 1;
if(cs && wstrb[0])
case(addr)
6'h00: porta_portx <= data_in[7:0];
6'h02: porta_ddrx <= data_in[7:0];
6'h04: portb_portx <= data_in[7:0];
6'h06: portb_ddrx <= data_in[7:0];
6'h08: ser_out <= {1'b1, data_in[7:0], 1'b0, 1'b1};
6'h0a: ser_brr[7:0] <= data_in[7:0];
6'h0c: tcnt0[7:0] <= data_in[7:0];
6'h0d: ocr0[7:0] <= data_in[7:0];
6'h0e: if (data_in[0]) ocf0 <= 1'b0;
6'h0f: ocie0 <= data_in[0];
endcase; // case (addr)
if(cs && wstrb[1])
case(addr)
6'h0a: ser_brr[15:8] <= data_in[15:8];
6'h0c: tcnt0[15:8] <= data_in[15:8];
6'h0d: ocr0[15:8] <= data_in[15:8];
endcase; // case (addr)
if(cs && wstrb[2])
case(addr)
6'h0c: tcnt0[23:16] <= data_in[23:16];
6'h0d: ocr0[23:16] <= data_in[23:16];
endcase; // case (addr)
end // else: !if(~nrst)
always @(*) begin
data_out = 32'h00000000;
if (nrst && cs && oe)
case(addr)
6'h00: data_out[7:0] = porta_portx;
6'h01: data_out[7:0] = porta_pinx;
6'h02: data_out[7:0] = porta_ddrx;
6'h04: data_out[7:0] = portb_portx;
6'h05: data_out[7:0] = portb_pinx;
6'h06: data_out[7:0] = portb_ddrx;
6'h08: data_out[7:0] = ser_rx_data;
6'h09: data_out[7:0] = {ser_rxc, &ser_out, &ser_out, ser_fe, ser_dor, 3'b000};
6'h0a: data_out[15:0] = ser_brr;
6'h0c: data_out[23:0] = tcnt0;
6'h0d: data_out[23:0] = ocr0;
6'h0e: data_out[0] = ocf0;
6'h0f: data_out[0] = ocie0;
endcase // case (addr)
end
endmodule // peripherals
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input wr_clk;
input [AW:0] wr_rd_gray_pointer;//synced from read domain
input wr_write;
//###########
//# OUTPUTS
//###########
output wr_fifo_full;
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
//#########
//# REGS
//#########
reg [AW:0] wr_gray_pointer;
reg [AW:0] wr_binary_pointer;
reg wr_fifo_full;
//##########
//# WIRES
//##########
wire wr_fifo_full_next;
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
begin
wr_binary_pointer[AW:0] <= {(AW+1){1'b0}};
wr_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(wr_write)
begin
wr_binary_pointer[AW:0] <= wr_binary_next[AW:0];
wr_gray_pointer[AW:0] <= wr_gray_next[AW:0];
end
//Write Address
assign wr_addr[AW-1:0] = wr_binary_pointer[AW-1:0];
//Updating binary pointer
assign wr_binary_next[AW:0] = wr_binary_pointer[AW:0] +
{{(AW){1'b0}},wr_write};
//Gray Pointer Conversion (for more reliable synchronization)!
assign wr_gray_next[AW:0] = {1'b0,wr_binary_next[AW:1]} ^
wr_binary_next[AW:0];
//FIFO full indication
assign wr_fifo_full_next =
(wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
else
wr_fifo_full <=wr_fifo_full_next;
endmodule // fifo_full_block
|
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is the sprites part of denise
// It supports all OCS sprite modes.
//
// 12-06-2005 -started coding
// -first finished version
// 21-06-2005 -changed sprite priority logic and nsprite output
// 02-10-2005 -sprites are now attached if odd,even or both sprites SPRXCTL bit 7 is set
// 17-10-2005 -sprites were displayed one pixel too early, fixed.
// ----------
// JB:
// 2008-07-14 - swapped shifta and shiftb in serialized output (fix for Zool2: copper writes to SPRxDATx registers)
// 2009-01-26 - cleanup
// - added sprena signal
// 2009-05-24 - clean-up & renaming
// 2010-06-17 - improved OCS sprite attach mode
module sprites
(
input clk, // bus clock
input reset, // reset
input [8:1] reg_address_in, // register address input
input [8:0] hpos, // horizontal beam counter
input [15:0] data_in, // bus data in
input sprena, // sprite enable signal
output [7:0] nsprite, // sprite data valid signals
output reg [3:0] sprdata // sprite data out
);
//register names and adresses
parameter SPRPOSCTLBASE = 9'h140; //sprite data, position and control register base address
//local signals
wire selspr0; // select sprite 0
wire selspr1; // select sprite 1
wire selspr2; // select sprite 2
wire selspr3; // select sprite 3
wire selspr4; // select sprite 4
wire selspr5; // select sprite 5
wire selspr6; // select sprite 6
wire selspr7; // select sprite 7
wire [1:0] sprdat0; // data sprite 0
wire [1:0] sprdat1; // data sprite 1
wire [1:0] sprdat2; // data sprite 2
wire [1:0] sprdat3; // data sprite 3
wire [1:0] sprdat4; // data sprite 4
wire [1:0] sprdat5; // data sprite 5
wire [1:0] sprdat6; // data sprite 6
wire [1:0] sprdat7; // data sprite 7
wire attach0; // attach sprite 0,1
wire attach1; // attach sprite 0,1
wire attach2; // attach sprite 2,3
wire attach3; // attach sprite 2,3
wire attach4; // attach sprite 4,5
wire attach5; // attach sprite 4,5
wire attach6; // attach sprite 6,7
wire attach7; // attach sprite 6,7
//--------------------------------------------------------------------------------------
// sprite register address decoder
wire selsprx;
assign selsprx = SPRPOSCTLBASE[8:6]==reg_address_in[8:6] ? 1'b1 : 1'b0; // base address
assign selspr0 = selsprx && reg_address_in[5:3]==3'd0 ? 1'b1 : 1'b0;
assign selspr1 = selsprx && reg_address_in[5:3]==3'd1 ? 1'b1 : 1'b0;
assign selspr2 = selsprx && reg_address_in[5:3]==3'd2 ? 1'b1 : 1'b0;
assign selspr3 = selsprx && reg_address_in[5:3]==3'd3 ? 1'b1 : 1'b0;
assign selspr4 = selsprx && reg_address_in[5:3]==3'd4 ? 1'b1 : 1'b0;
assign selspr5 = selsprx && reg_address_in[5:3]==3'd5 ? 1'b1 : 1'b0;
assign selspr6 = selsprx && reg_address_in[5:3]==3'd6 ? 1'b1 : 1'b0;
assign selspr7 = selsprx && reg_address_in[5:3]==3'd7 ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------
// instantiate sprite 0
sprshift sps0
(
.clk(clk),
.reset(reset),
.aen(selspr0),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat0),
.attach(attach0)
);
// instantiate sprite 1
sprshift sps1
(
.clk(clk),
.reset(reset),
.aen(selspr1),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat1),
.attach(attach1)
);
// instantiate sprite 2
sprshift sps2
(
.clk(clk),
.reset(reset),
.aen(selspr2),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat2),
.attach(attach2)
);
// instantiate sprite 3
sprshift sps3
(
.clk(clk),
.reset(reset),
.aen(selspr3),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat3),
.attach(attach3)
);
// instantiate sprite 4
sprshift sps4
(
.clk(clk),
.reset(reset),
.aen(selspr4),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat4),
.attach(attach4)
);
// instantiate sprite 5
sprshift sps5
(
.clk(clk),
.reset(reset),
.aen(selspr5),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat5),
.attach(attach5)
);
// instantiate sprite 6
sprshift sps6
(
.clk(clk),
.reset(reset),
.aen(selspr6),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat6),
.attach(attach6)
);
// instantiate sprite 7
sprshift sps7
(
.clk(clk),
.reset(reset),
.aen(selspr7),
.address(reg_address_in[2:1]),
.hpos(hpos),
.data_in(data_in),
.sprdata(sprdat7),
.attach(attach7)
);
//--------------------------------------------------------------------------------------
// generate sprite data valid signals
assign nsprite[0] = (sprena && sprdat0[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[1] = (sprena && sprdat1[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[2] = (sprena && sprdat2[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[3] = (sprena && sprdat3[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[4] = (sprena && sprdat4[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[5] = (sprena && sprdat5[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[6] = (sprena && sprdat6[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
assign nsprite[7] = (sprena && sprdat7[1:0]!=2'b00) ? 1'b1 : 1'b0;//if any non-zero bit -> valid video data
//--------------------------------------------------------------------------------------
// sprite video priority logic and color decoder
always @(attach0 or attach1 or attach2 or attach3 or
attach4 or attach5 or attach6 or attach7 or
sprdat0 or sprdat1 or sprdat2 or sprdat3 or
sprdat4 or sprdat5 or sprdat6 or sprdat7 or
nsprite)
begin
if (nsprite[1:0]!=2'b00) // sprites 0,1 non transparant ?
begin
if (attach1) // sprites are attached -> 15 colors + transparant
sprdata[3:0] = {sprdat1[1:0],sprdat0[1:0]};
else if (nsprite[0]) // output lowered number sprite
sprdata[3:0] = {2'b00,sprdat0[1:0]};
else // output higher numbered sprite
sprdata[3:0] = {2'b00,sprdat1[1:0]};
end
else if (nsprite[3:2]!=2'b00) // sprites 2,3 non transparant ?
begin
if (attach3) // sprites are attached -> 15 colors + transparant
sprdata[3:0] = {sprdat3[1:0],sprdat2[1:0]};
else if (nsprite[2]) // output lowered number sprite
sprdata[3:0] = {2'b01,sprdat2[1:0]};
else // output higher numbered sprite
sprdata[3:0] = {2'b01,sprdat3[1:0]};
end
else if (nsprite[5:4]!=2'b00) // sprites 4,5 non transparant ?
begin
if (attach5) // sprites are attached -> 15 colors + transparant
sprdata[3:0] = {sprdat5[1:0],sprdat4[1:0]};
else if (nsprite[4]) // output lowered number sprite
sprdata[3:0] = {2'b10,sprdat4[1:0]};
else // output higher numbered sprite
sprdata[3:0] = {2'b10,sprdat5[1:0]};
end
else if (nsprite[7:6]!=2'b00) // sprites 6,7 non transparant ?
begin
if (attach7) // sprites are attached -> 15 colors + transparant
sprdata[3:0] = {sprdat7[1:0],sprdat6[1:0]};
else if (nsprite[6]) // output lowered number sprite
sprdata[3:0] = {2'b11,sprdat6[1:0]};
else // output higher numbered sprite
sprdata[3:0] = {2'b11,sprdat7[1:0]};
end
else // all sprites transparant
begin
sprdata[3:0] = 4'b0000;
end
end
//--------------------------------------------------------------------------------------
endmodule
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
// this is the sprite parallel to serial converter
// clk is 7.09379 MHz (low resolution pixel clock)
// the sprdata assign circuitry is constructed differently from the hardware
// as described in the amiga hardware reference manual
// this is to make sure that the horizontal start position of a sprite
// aligns with the bitplane/playfield start position
module sprshift
(
input clk, // bus clock
input reset, // reset
input aen, // address enable
input [1:0] address, // register address input
input [8:0] hpos, // horizontal beam counter
input [15:0] data_in, // bus data in
output [1:0] sprdata, // serialized sprite data out
output reg attach // sprite is attached
);
// register names and adresses
parameter POS = 2'b00;
parameter CTL = 2'b01;
parameter DATA = 2'b10;
parameter DATB = 2'b11;
// local signals
reg [15:0] datla; // data register A
reg [15:0] datlb; // data register B
reg [15:0] shifta; // shift register A
reg [15:0] shiftb; // shift register B
reg [8:0] hstart; // horizontal start value
reg armed; // sprite "armed" signal
reg load; // load shift register signal
reg load_del;
//--------------------------------------------------------------------------------------
// generate armed signal
always @(posedge clk)
if (reset) // reset disables sprite
armed <= 0;
else if (aen && address==CTL) // writing CTL register disables sprite
armed <= 0;
else if (aen && address==DATA) // writing data register A arms sprite
armed <= 1;
//--------------------------------------------------------------------------------------
// generate load signal
always @(posedge clk)
load <= armed && hpos[8:0]==hstart[8:0] ? 1'b1 : 1'b0;
always @(posedge clk)
load_del <= load;
//--------------------------------------------------------------------------------------
// POS register
always @(posedge clk)
if (aen && address==POS)
hstart[8:1] <= data_in[7:0];
// CTL register
always @(posedge clk)
if (aen && address==CTL)
{attach,hstart[0]} <= {data_in[7],data_in[0]};
// data register A
always @(posedge clk)
if (aen && address==DATA)
datla[15:0] <= data_in[15:0];
// data register B
always @(posedge clk)
if (aen && address==DATB)
datlb[15:0] <= data_in[15:0];
//--------------------------------------------------------------------------------------
// sprite shift register
always @(posedge clk)
if (load_del) // load new data into shift register
begin
shifta[15:0] <= datla[15:0];
shiftb[15:0] <= datlb[15:0];
end
else // shift out data
begin
shifta[15:0] <= {shifta[14:0],1'b0};
shiftb[15:0] <= {shiftb[14:0],1'b0};
end
// assign serialized output data
assign sprdata[1:0] = {shiftb[15],shifta[15]};
//--------------------------------------------------------------------------------------
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPM_Toggle_PHY_B_Reset for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPM_Toggle_PHY_B_Reset
// Module Name: NPM_Toggle_PHY_B_Reset
// File Name: NPM_Toggle_PHY_B_Reset.v
//
// Version: v1.0.0
//
// Description: NFC Phy reset FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPM_Toggle_PHY_B_Reset
(
iSystemClock ,
iReset ,
oReady ,
oLastStep ,
iStart ,
oPI_BUFF_Reset ,
oPI_BUFF_RE ,
oPI_BUFF_WE ,
oPO_DQStrobe ,
oDQSOutEnable
);
input iSystemClock ;
input iReset ;
output oReady ;
output oLastStep ;
input iStart ;
output oPI_BUFF_Reset ;
output oPI_BUFF_RE ;
output oPI_BUFF_WE ;
output [7:0] oPO_DQStrobe ;
output oDQSOutEnable ;
// FSM Parameters/Wires/Regs
parameter PBR_FSM_BIT = 4;
parameter PBR_RESET = 4'b0001;
parameter PBR_READY = 4'b0010;
parameter PBR_RFRST = 4'b0100; // reset first
parameter PBR_RLOOP = 4'b1000; // reset loop
reg [PBR_FSM_BIT-1:0] rPBR_cur_state ;
reg [PBR_FSM_BIT-1:0] rPBR_nxt_state ;
// Internal Wires/Regs
reg rReady ;
reg [3:0] rTimer ;
wire wJOBDone ;
reg rPI_BUFF_Reset ;
reg rPI_BUFF_RE ;
reg rPI_BUFF_WE ;
reg [7:0] rPO_DQStrobe ;
reg rDQSOutEnable ;
// Control Signals
// Flow Control
assign wJOBDone = (4'b1010 == rTimer[3:0]);
// 1 + '10' = 11 cycles
// there is DQS delay by OSEDESE module,
// combination of {buffer reset, clock cycle, real DQS's cycle} will be less than design
// FSM
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rPBR_cur_state <= PBR_RESET;
end else begin
rPBR_cur_state <= rPBR_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (rPBR_cur_state)
PBR_RESET: begin
rPBR_nxt_state <= PBR_READY;
end
PBR_READY: begin
rPBR_nxt_state <= (iStart)? PBR_RFRST:PBR_READY;
end
PBR_RFRST: begin
rPBR_nxt_state <= PBR_RLOOP;
end
PBR_RLOOP: begin
rPBR_nxt_state <= (wJOBDone)? ((iStart)? PBR_RFRST:PBR_READY):PBR_RLOOP;
end
default:
rPBR_nxt_state <= PBR_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rReady <= 0;
rTimer[3:0] <= 0;
rPI_BUFF_Reset <= 0;
rPI_BUFF_RE <= 0;
rPI_BUFF_WE <= 0;
rPO_DQStrobe[7:0] <= 0;
rDQSOutEnable <= 0;
end else begin
case (rPBR_nxt_state)
PBR_RESET: begin
rReady <= 0;
rTimer[3:0] <= 0;
rPI_BUFF_Reset <= 0;
rPI_BUFF_RE <= 0;
rPI_BUFF_WE <= 0;
rPO_DQStrobe[7:0] <= 0;
rDQSOutEnable <= 0;
end
PBR_READY: begin
rReady <= 1;
rTimer[3:0] <= 0;
rPI_BUFF_Reset <= 0;
rPI_BUFF_RE <= 0;
rPI_BUFF_WE <= 0;
rPO_DQStrobe[7:0] <= 0;
rDQSOutEnable <= 0;
end
PBR_RFRST: begin
rReady <= 0;
rTimer[3:0] <= 4'b0000;
rPI_BUFF_Reset <= 1'b1;
rPI_BUFF_RE <= 1'b0;
rPI_BUFF_WE <= 1'b0;
rPO_DQStrobe[7:0] <= 8'b0101_0101;
rDQSOutEnable <= 1'b1;
end
PBR_RLOOP: begin
rReady <= 0;
rTimer[3:0] <= rTimer[3:0] + 1'b1;
rPI_BUFF_Reset <= 1'b1;
rPI_BUFF_RE <= 1'b0;
rPI_BUFF_WE <= 1'b0;
rPO_DQStrobe[7:0] <= 8'b0101_0101;
rDQSOutEnable <= 1'b1;
end
endcase
end
end
// Output
assign oReady = rReady | wJOBDone ;
assign oLastStep = wJOBDone ;
assign oPI_BUFF_Reset = rPI_BUFF_Reset ;
assign oPI_BUFF_RE = rPI_BUFF_RE ;
assign oPI_BUFF_WE = rPI_BUFF_WE ;
assign oPO_DQStrobe = rPO_DQStrobe ;
assign oDQSOutEnable = rDQSOutEnable ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S18_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYGATE4S18_FUNCTIONAL_V
/**
* dlygate4s18: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s18 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S18_FUNCTIONAL_V |
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 42: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 42: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 42: 0] entry_0;
reg [ 42: 0] entry_1;
wire full;
reg rd_address;
reg [ 42: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 23: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 23: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 8: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 23: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 42: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 3: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 14: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
wasca_external_sdram_controller_input_efifo_module the_wasca_external_sdram_controller_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[23],f_addr[9]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 11600;
else if (refresh_counter == 0)
refresh_counter <= 18095;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {4{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 2;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 8;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[23],active_addr[9]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[22 : 10]} == {f_addr[22 : 10]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[8 : 0] } : { {4{1'b0}},active_addr[8 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 4'b0000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 2;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[22 : 10];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 3;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 2;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 8;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// applications related to the deployment of airbags, or any
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v1_8_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$_MUX8_ (
A,
B,
C,
D,
E,
F,
G,
H,
S,
T,
U,
Y
);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
mux8x0 _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.C (C),
.D (D),
.E (E),
.F (F),
.G (G),
.H (H),
.S0(S),
.S1(T),
.S2(U),
.Q (Y)
);
endmodule
module \$_MUX4_ (
A,
B,
C,
D,
S,
T,
U,
Y
);
input A, B, C, D, S, T, U;
output Y;
mux4x0 _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.C (C),
.D (D),
.S0(S),
.S1(T),
.Q (Y)
);
endmodule
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:31:21 AM
// Design Name:
// Module Name: multiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multiplier
# (parameter W = 32/*,level=5*/) (//level=log2(W)
input wire clk,
input wire [W-1:0] Data_A_i,
input wire [W-1:0] Data_B_i,
output wire [2*W-1:0] Data_S_o
);
//reg [W-1:0] aint,bint;
reg [2*W-1:0] pdt_int;/*[level-1:0];*/
//integer i;
assign Data_S_o=pdt_int;//[level-1];
always@(posedge clk)
begin
//aint<=Data_A_i;
//bint<=Data_B_i;
pdt_int<= Data_A_i*Data_B_i;
//for (i=1;i<level;i=i+1)
//pdt_int[i]<=pdt_int[i-1];
end
endmodule
//module multiplier #(parameter W=32)(
// input wire clk,
// input wire [W-1:0] Data_A_i,
// input wire [W-1:0] Data_B_i,
// output reg [2*W-1:0] Data_S_o
// );
// //reg [W-1:0] a_in, b_in;
// //wire [2*W-1:0] multi_reg;
// reg [2*W-1:0] pipe1, pipe2, pipe3, pipe4, pipe5;
// //assign multi_reg = a_in * b_in;
// always @(posedge clk) begin
// //a_in <= Data_A_i; b_in <= Data_B_i;
// pipe1 <= Data_A_i*Data_B_i;
// pipe2 <= pipe1;
// pipe3 <= pipe2;
// pipe4 <= pipe3;
// pipe5 <= pipe4;
// Data_S_o <= pipe5;
// end
// endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
//
// There are two modes:
// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
// (resp. high) edge/peak is detected, with hysteresis
// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
// is detected.
// That way you can detect two consecutive edges/peaks at the same level (L/H)
//
// Output:
// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
// - ssp_clk: cross_lo
`include "lp20khz_1MSa_iir_filter.v"
`include "lf_edge_detect.v"
module lo_edge_detect(
input pck0, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, input ssp_dout, output ssp_clk,
input cross_lo,
output dbg,
input lf_field,
input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
);
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
// No logic, straight through.
assign pwr_oe1 = 1'b0; // not used in LF mode
assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
// when modulating, add another 33 Ohms and 10k Ohms in parallel:
assign pwr_oe2 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1'b0;
// filter the ADC values
wire data_rdy;
wire [7:0] adc_filtered;
assign adc_clk = pck0;
lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
// detect edges
wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
wire [7:0] max, min;
wire edge_state, edge_toggle;
lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
max, min,
high_threshold, highz_threshold, lowz_threshold, low_threshold,
edge_state, edge_toggle);
assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Matt Myers.
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package config_pkg;
typedef struct packed {
int UPPER0;
struct packed {
int USE_QUAD0;
int USE_QUAD1;
int USE_QUAD2;
} mac;
int UPPER2;
} config_struct;
function automatic config_struct static_config(int selector);
config_struct return_config;
return_config = '0;
return_config.UPPER0 = 10;
return_config.UPPER2 = 20;
return_config.mac.USE_QUAD0 = 4;
return_config.mac.USE_QUAD2 = 6;
case (selector)
1: return_config.mac.USE_QUAD1 = 5;
endcase
return return_config;
endfunction
endpackage : config_pkg
module t;
import config_pkg::*;
localparam config_struct MY_CONFIG = static_config(1);
struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I ();
endmodule : t
module struct_submodule
import config_pkg::*;
#(parameter config_struct MY_CONFIG = '0);
initial begin
`checkd(MY_CONFIG.UPPER0, 10);
`checkd(MY_CONFIG.mac.USE_QUAD0, 4);
`checkd(MY_CONFIG.mac.USE_QUAD1, 5);
`checkd(MY_CONFIG.mac.USE_QUAD2, 6);
`checkd(MY_CONFIG.UPPER2, 20);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : struct_submodule
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: cntmux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cntmux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire0;
wire [3:0] sub_wire3 = data1x[3:0];
wire [3:0] result = sub_wire0[3:0];
wire [3:0] sub_wire1 = data0x[3:0];
wire [7:0] sub_wire2 = {sub_wire3, sub_wire1};
wire sub_wire4 = sel;
wire sub_wire5 = sub_wire4;
lpm_mux LPM_MUX_component (
.data (sub_wire2),
.sel (sub_wire5),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 4,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
/*************************************************************************************
*pwmfre = 50000000Hz/pwm frequency
*dutyratio = pwmfre * percent
*Example : 100Hz 50% dutyratio pwm output
pwmfre = 50000000Hz/100Hz
dutyratio = pwmfre * 50%
**************************************************************************************/
module pwm_out(rst_n, clk, enable, pha, phb, pwmfre, dutyratio);
input rst_n;
input clk;
input enable;
input[31:0] pwmfre;
input[31:0] dutyratio;
output pha;
output phb;
reg pwm_reg;
reg [31:0] count_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
end
else if (enable)
begin
if (count_reg < pwmfre) begin
count_reg <= count_reg + 1;
end
else begin
count_reg <= 0;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pwm_reg <= 1'h0;
end
else if (enable)
begin
if (count_reg < dutyratio) begin
pwm_reg <= 1'h1;
end
else begin
pwm_reg <= 1'h0;
end
end
end
assign pha = pwm_reg;
assign phb = ~pwm_reg;
endmodule |
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CPolynomials.
Require Import Morphisms.
Require Import CRings.
(**
* Polynomials: Nth Coefficient
%\begin{convention}% Let [R] be a ring and write [RX] for the ring of
polynomials over [R].
%\end{convention}%
** Definitions
*)
Section NthCoeff_def.
Variable R : CRing.
(* begin hide *)
Notation RX := (cpoly_cring R).
(* end hide *)
(**
The [n]-th coefficient of a polynomial. The default value is
[Zero:CR] e.g. if the [n] is higher than the length. For the
polynomial $a_0 +a_1 X +a_2 X^2 + \cdots + a_n X^n$ #a0 +a1 X +a2 X^2
+ ... + an X^n#, the [Zero]-th coefficient is $a_0$#a0#, the first
is $a_1$#a1# etcetera. *)
Fixpoint nth_coeff (n : nat) (p : RX) {struct p} : R :=
match p with
| cpoly_zero => [0]
| cpoly_linear c q =>
match n with
| O => c
| S m => nth_coeff m q
end
end.
Lemma nth_coeff_strext : forall n p p', nth_coeff n p [#] nth_coeff n p' -> p [#] p'.
Proof.
do 3 intro.
generalize n.
clear n.
pattern p, p' in |- *.
apply Ccpoly_double_sym_ind.
unfold Csymmetric in |- *.
intros.
apply ap_symmetric_unfolded.
apply X with n.
apply ap_symmetric_unfolded.
assumption.
intro p0.
pattern p0 in |- *.
apply Ccpoly_induc.
simpl in |- *.
intros.
elim (ap_irreflexive_unfolded _ _ X).
do 4 intro.
elim n.
simpl in |- *.
auto.
intros.
cut (c [#] [0] or p1 [#] [0]).
intro; apply _linear_ap_zero.
auto.
right.
apply X with n0.
astepr ([0]:R). auto.
intros.
induction n as [| n Hrecn].
simpl in X0.
cut (c [#] d or p0 [#] q).
auto.
auto.
cut (c [#] d or p0 [#] q).
auto.
right.
apply X with n.
exact X0.
Qed.
Lemma nth_coeff_wd : forall n p p', p [=] p' -> nth_coeff n p [=] nth_coeff n p'.
Proof.
intros.
generalize (fun_strext_imp_wd _ _ (nth_coeff n)); intro.
unfold fun_wd in H0.
apply H0.
unfold fun_strext in |- *.
intros.
apply nth_coeff_strext with n.
assumption.
assumption.
Qed.
Global Instance: forall n, Proper (@st_eq _ ==> @st_eq _) (nth_coeff n).
Proof. intros n ??. apply (nth_coeff_wd n). Qed.
Definition nth_coeff_fun n := Build_CSetoid_fun _ _ _ (nth_coeff_strext n).
(**
%\begin{shortcoming}%
We would like to use [nth_coeff_fun n] all the time.
However, Coq's coercion mechanism doesn't support this properly:
the term
[(nth_coeff_fun n p)] won't get parsed, and has to be written as
[((nth_coeff_fun n) p)] instead.
So, in the names of lemmas, we write [(nth_coeff n p)],
which always (e.g. in proofs) can be converted
to [((nth_coeff_fun n) p)].
%\end{shortcoming}%
*)
Definition nonConst p : CProp := {n : nat | 0 < n | nth_coeff n p [#] [0]}.
(**
The following is probably NOT needed. These functions are
NOT extensional, that is, they are not CSetoid functions.
*)
Fixpoint nth_coeff_ok (n : nat) (p : RX) {struct p} : bool :=
match n, p with
| O, cpoly_zero => false
| O, cpoly_linear c q => true
| S m, cpoly_zero => false
| S m, cpoly_linear c q => nth_coeff_ok m q
end.
(* The in_coeff predicate*)
Fixpoint in_coeff (c : R) (p : RX) {struct p} : Prop :=
match p with
| cpoly_zero => False
| cpoly_linear d q => c [=] d \/ in_coeff c q
end.
(**
The [cpoly_zero] case should be [c [=] [0]] in order to be extensional.
*)
Lemma nth_coeff_S : forall m p c,
in_coeff (nth_coeff m p) p -> in_coeff (nth_coeff (S m) (c[+X*]p)) (c[+X*]p).
Proof.
simpl in |- *; auto.
Qed.
End NthCoeff_def.
Implicit Arguments nth_coeff [R].
Implicit Arguments nth_coeff_fun [R].
Hint Resolve nth_coeff_wd: algebra_c.
Section NthCoeff_props.
(**
** Properties of [nth_coeff] *)
Variable R : CRing.
(* begin hide *)
Notation RX := (cpoly_cring R).
(* end hide *)
Lemma nth_coeff_zero : forall n, nth_coeff n ([0]:RX) [=] [0].
Proof.
intros.
simpl in |- *.
algebra.
Qed.
Lemma coeff_O_lin : forall p (c : R), nth_coeff 0 (c[+X*]p) [=] c.
Proof.
intros.
simpl in |- *.
algebra.
Qed.
Lemma coeff_Sm_lin : forall p (c : R) m, nth_coeff (S m) (c[+X*]p) [=] nth_coeff m p.
Proof.
intros.
simpl in |- *.
algebra.
Qed.
Lemma coeff_O_c_ : forall c : R, nth_coeff 0 (_C_ c) [=] c.
Proof.
intros.
simpl in |- *.
algebra.
Qed.
Lemma coeff_O_x_mult : forall p : RX, nth_coeff 0 (_X_[*]p) [=] [0].
Proof.
intros.
astepl (nth_coeff 0 ([0][+]_X_[*]p)).
astepl (nth_coeff 0 (_C_ [0][+]_X_[*]p)).
astepl (nth_coeff 0 ([0][+X*]p)).
simpl in |- *.
algebra.
Qed.
Lemma coeff_Sm_x_mult : forall (p : RX) m, nth_coeff (S m) (_X_[*]p) [=] nth_coeff m p.
Proof.
intros.
astepl (nth_coeff (S m) ([0][+]_X_[*]p)).
astepl (nth_coeff (S m) (_C_ [0][+]_X_[*]p)).
astepl (nth_coeff (S m) ([0][+X*]p)).
simpl in |- *.
algebra.
Qed.
Lemma coeff_Sm_mult_x_ : forall (p : RX) m, nth_coeff (S m) (p[*]_X_) [=] nth_coeff m p.
Proof.
intros.
astepl (nth_coeff (S m) (_X_[*]p)).
apply coeff_Sm_x_mult.
Qed.
Hint Resolve nth_coeff_zero coeff_O_lin coeff_Sm_lin coeff_O_c_
coeff_O_x_mult coeff_Sm_x_mult coeff_Sm_mult_x_: algebra.
Lemma nth_coeff_ap_zero_imp : forall (p : RX) n, nth_coeff n p [#] [0] -> p [#] [0].
Proof.
intros.
cut (nth_coeff n p [#] nth_coeff n [0]).
intro H0.
apply (nth_coeff_strext _ _ _ _ H0).
algebra.
Qed.
Lemma nth_coeff_plus : forall (p q : RX) n,
nth_coeff n (p[+]q) [=] nth_coeff n p[+]nth_coeff n q.
Proof.
do 2 intro.
pattern p, q in |- *.
apply poly_double_comp_ind.
intros.
astepl (nth_coeff n (p1[+]q1)).
astepr (nth_coeff n p1[+]nth_coeff n q1).
apply H1.
intros.
simpl in |- *.
algebra.
intros.
elim n.
simpl in |- *.
algebra.
intros.
astepl (nth_coeff n0 (p0[+]q0)).
generalize (H n0); intro.
astepl (nth_coeff n0 p0[+]nth_coeff n0 q0).
algebra.
Qed.
Lemma nth_coeff_inv : forall (p : RX) n, nth_coeff n [--]p [=] [--] (nth_coeff n p).
Proof.
intro.
pattern p in |- *.
apply cpoly_induc.
intros.
simpl in |- *.
algebra.
intros.
elim n.
simpl in |- *.
algebra.
intros. simpl in |- *.
apply H.
Qed.
Hint Resolve nth_coeff_inv: algebra.
Lemma nth_coeff_c_mult_p : forall (p : RX) c n, nth_coeff n (_C_ c[*]p) [=] c[*]nth_coeff n p.
Proof.
do 2 intro.
pattern p in |- *.
apply cpoly_induc.
intros.
astepl (nth_coeff n ([0]:RX)).
astepr (c[*][0]).
astepl ([0]:R).
algebra.
intros.
elim n.
simpl in |- *.
algebra.
intros.
astepl (nth_coeff (S n0) (c[*]c0[+X*]_C_ c[*]p0)).
astepl (nth_coeff n0 (_C_ c[*]p0)).
astepl (c[*]nth_coeff n0 p0).
algebra.
Qed.
Lemma nth_coeff_p_mult_c_ : forall (p : RX) c n, nth_coeff n (p[*]_C_ c) [=] nth_coeff n p[*]c.
Proof.
intros.
astepl (nth_coeff n (_C_ c[*]p)).
astepr (c[*]nth_coeff n p).
apply nth_coeff_c_mult_p.
Qed.
Hint Resolve nth_coeff_c_mult_p nth_coeff_p_mult_c_ nth_coeff_plus: algebra.
Lemma nth_coeff_complicated : forall a b (p : RX) n,
nth_coeff (S n) ((_C_ a[*]_X_[+]_C_ b) [*]p) [=] a[*]nth_coeff n p[+]b[*]nth_coeff (S n) p.
Proof.
intros.
astepl (nth_coeff (S n) (_C_ a[*]_X_[*]p[+]_C_ b[*]p)).
astepl (nth_coeff (S n) (_C_ a[*]_X_[*]p) [+]nth_coeff (S n) (_C_ b[*]p)).
astepl (nth_coeff (S n) (_C_ a[*] (_X_[*]p)) [+]b[*]nth_coeff (S n) p).
astepl (a[*]nth_coeff (S n) (_X_[*]p) [+]b[*]nth_coeff (S n) p).
algebra.
Qed.
Lemma all_nth_coeff_eq_imp : forall p p' : RX,
(forall i, nth_coeff i p [=] nth_coeff i p') -> p [=] p'.
Proof.
intro. induction p as [| s p Hrecp]; intros;
[ induction p' as [| s p' Hrecp'] | induction p' as [| s0 p' Hrecp'] ]; intros.
algebra.
simpl in |- *. simpl in H. simpl in Hrecp'. split.
apply eq_symmetric_unfolded. apply (H 0). apply Hrecp'.
intros. apply (H (S i)).
simpl in |- *. simpl in H. simpl in Hrecp. split.
apply (H 0).
change ([0] [=] (p:RX)) in |- *. apply eq_symmetric_unfolded. simpl in |- *. apply Hrecp.
intros. apply (H (S i)).
simpl in |- *. simpl in H. split.
apply (H 0).
change ((p:RX) [=] (p':RX)) in |- *. apply Hrecp. intros. apply (H (S i)).
Qed.
Lemma poly_at_zero : forall p : RX, p ! [0] [=] nth_coeff 0 p.
Proof.
intros. induction p as [| s p Hrecp]; intros.
simpl in |- *. algebra.
simpl in |- *. Step_final (s[+][0]).
Qed.
Lemma nth_coeff_inv' : forall (p : RX) i,
nth_coeff i (cpoly_inv _ p) [=] [--] (nth_coeff i p).
Proof.
intros. change (nth_coeff i [--] (p:RX) [=] [--] (nth_coeff i p)) in |- *. algebra.
Qed.
Lemma nth_coeff_minus : forall (p q : RX) i,
nth_coeff i (p[-]q) [=] nth_coeff i p[-]nth_coeff i q.
Proof.
intros.
astepl (nth_coeff i (p[+][--]q)).
astepl (nth_coeff i p[+]nth_coeff i [--]q).
Step_final (nth_coeff i p[+][--] (nth_coeff i q)).
Qed.
Hint Resolve nth_coeff_minus: algebra.
Lemma nth_coeff_sum0 : forall (p_ : nat -> RX) k n,
nth_coeff k (Sum0 n p_) [=] Sum0 n (fun i => nth_coeff k (p_ i)).
Proof.
intros. induction n as [| n Hrecn]; intros.
simpl in |- *. algebra.
change (nth_coeff k (Sum0 n p_[+]p_ n) [=]
Sum0 n (fun i : nat => nth_coeff k (p_ i)) [+]nth_coeff k (p_ n)) in |- *.
Step_final (nth_coeff k (Sum0 n p_) [+]nth_coeff k (p_ n)).
Qed.
Lemma nth_coeff_sum : forall (p_ : nat -> RX) k m n,
nth_coeff k (Sum m n p_) [=] Sum m n (fun i => nth_coeff k (p_ i)).
Proof.
unfold Sum in |- *. unfold Sum1 in |- *. intros.
astepl (nth_coeff k (Sum0 (S n) p_) [-]nth_coeff k (Sum0 m p_)).
apply cg_minus_wd; apply nth_coeff_sum0.
Qed.
Lemma nth_coeff_nexp_eq : forall i, nth_coeff i (_X_[^]i) [=] ([1]:R).
Proof.
intros. induction i as [| i Hreci]; intros.
simpl in |- *. algebra.
change (nth_coeff (S i) (_X_[^]i[*]_X_) [=] ([1]:R)) in |- *.
Step_final (nth_coeff i (_X_[^]i):R).
Qed.
Lemma nth_coeff_nexp_neq : forall i j, i <> j -> nth_coeff i (_X_[^]j) [=] ([0]:R).
Proof.
intro; induction i as [| i Hreci]; intros;
[ induction j as [| j Hrecj] | induction j as [| j Hrecj] ]; intros.
elim (H (refl_equal _)).
Step_final (nth_coeff 0 (_X_[*]_X_[^]j):R).
simpl in |- *. algebra.
change (nth_coeff (S i) (_X_[^]j[*]_X_) [=] ([0]:R)) in |- *.
astepl (nth_coeff i (_X_[^]j):R).
apply Hreci. auto.
Qed.
Lemma nth_coeff_mult : forall (p q : RX) n,
nth_coeff n (p[*]q) [=] Sum 0 n (fun i => nth_coeff i p[*]nth_coeff (n - i) q).
Proof.
intro; induction p as [| s p Hrecp]. intros.
stepl (nth_coeff n ([0]:RX)).
simpl in |- *. apply eq_symmetric_unfolded.
apply Sum_zero. auto with arith. intros. algebra.
apply nth_coeff_wd.
change ([0][=][0][*]q).
algebra.
intros.
apply eq_transitive_unfolded with (nth_coeff n (_C_ s[*]q[+]_X_[*] ((p:RX) [*]q))).
apply nth_coeff_wd.
change ((s[+X*]p) [*]q [=] _C_ s[*]q[+]_X_[*] ((p:RX) [*]q)) in |- *.
astepl ((_C_ s[+]_X_[*]p) [*]q).
Step_final (_C_ s[*]q[+]_X_[*]p[*]q).
astepl (nth_coeff n (_C_ s[*]q) [+]nth_coeff n (_X_[*] ((p:RX) [*]q))).
astepl (s[*]nth_coeff n q[+]nth_coeff n (_X_[*] ((p:RX) [*]q))).
induction n as [| n Hrecn]; intros.
astepl (s[*]nth_coeff 0 q[+][0]).
astepl (s[*]nth_coeff 0 q).
astepl (nth_coeff 0 (cpoly_linear _ s p) [*]nth_coeff 0 q).
pattern 0 at 2 in |- *. replace 0 with (0 - 0).
apply eq_symmetric_unfolded.
apply Sum_one with (f := fun i : nat => nth_coeff i (cpoly_linear _ s p) [*]nth_coeff (0 - i) q).
auto.
astepl (s[*]nth_coeff (S n) q[+]nth_coeff n ((p:RX) [*]q)).
apply eq_transitive_unfolded with (nth_coeff 0 (cpoly_linear _ s p) [*]nth_coeff (S n - 0) q[+]
Sum 1 (S n) (fun i : nat => nth_coeff i (cpoly_linear _ s p) [*]nth_coeff (S n - i) q)).
apply bin_op_wd_unfolded. algebra.
astepl (Sum 0 n (fun i : nat => nth_coeff i p[*]nth_coeff (n - i) q)).
apply Sum_shift. intros. simpl in |- *. algebra.
apply eq_symmetric_unfolded.
apply Sum_first with (f := fun i : nat => nth_coeff i (cpoly_linear _ s p) [*]nth_coeff (S n - i) q).
Qed.
End NthCoeff_props.
Hint Resolve nth_coeff_wd: algebra_c.
Hint Resolve nth_coeff_complicated poly_at_zero nth_coeff_inv: algebra.
Hint Resolve nth_coeff_inv' nth_coeff_c_mult_p nth_coeff_mult: algebra.
Hint Resolve nth_coeff_zero nth_coeff_plus nth_coeff_minus: algebra.
Hint Resolve nth_coeff_nexp_eq nth_coeff_nexp_neq: algebra.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A21O_PP_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_PP_SYMBOL_V
|
module spi_slave_tb
#(parameter transactions = 1000,
parameter init_value = 8'h42);
reg clk = 1'b1;
reg rst = 1'b1;
always #5 clk = ~clk;
initial #100 rst = 1'b0;
wire [7:0] gpio;
vlog_tb_utils vtu();
spi_bfm #(.sclk_period (50))
bfm
(.sclk_o (sclk),
.mosi_o (mosi),
.miso_i (1'b0),
.cs_n_o (cs_n));
spi_slave
#(.INIT_VALUE (init_value))
dut
(.clk (clk),
.rst (rst),
.sclk_i (sclk),
.mosi_i (mosi),
.miso_o (),
.cs_n_i (cs_n),
.gpio_o (gpio));
integer idx;
integer seed = 1;
reg [7:0] value = init_value;
initial begin
$display("Running %0d transactions", transactions);
@(negedge rst);
$display("Reset released");
@(clk);
for (idx=0 ; idx<transactions ; idx=idx+1 ) begin
bfm.send(value, 1'b0);
if (gpio != value) begin
$display("Error in transaction %0d. Expected %02x. Got %02x", idx, value, gpio);
$finish;
end
value = $dist_uniform(seed, 0, 255);
end
$display("Test passed!");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////////////////
// TimeCounter for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: TimeCounter
// Module Name: TimeCounter
// File Name: TimeCounter.v
//
// Version: v1.0.0
//
// Description: Time counter
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module TimeCounter
#
(
parameter TimerWidth = 32 ,
parameter DefaultPeriod = 100000000
)
(
iClock ,
iReset ,
iEnabled ,
iPeriodSetting ,
iSettingValid ,
iProbe ,
oCountValue
);
input iClock ;
input iReset ;
input iEnabled ;
input [TimerWidth - 1:0] iPeriodSetting ;
input iSettingValid ;
input iProbe ;
output [TimerWidth - 1:0] oCountValue ;
reg [TimerWidth - 1:0] rPeriod ;
reg [TimerWidth - 1:0] rSampledCount ;
reg [TimerWidth - 1:0] rCounter ;
reg [TimerWidth - 1:0] rTimeCount ;
always @ (posedge iClock)
if (iReset | !iEnabled | rTimeCount == rPeriod)
rCounter <= {(TimerWidth){1'b0}};
else
if (iEnabled & iProbe)
rCounter <= rCounter + 1'b1;
always @ (posedge iClock)
if (iReset | !iEnabled | rTimeCount == rPeriod)
rTimeCount <= {(TimerWidth){1'b0}};
else
if (iEnabled)
rTimeCount <= rTimeCount + 1'b1;
always @ (posedge iClock)
if (iReset)
rSampledCount <= {(TimerWidth){1'b0}};
else
if (rTimeCount == rPeriod)
rSampledCount <= rCounter;
always @ (posedge iClock)
if (iReset)
rPeriod <= DefaultPeriod;
else
if (iSettingValid)
rPeriod <= iPeriodSetting;
assign oCountValue = rSampledCount;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__ebufn (
VPWR,
VGND,
Z ,
A ,
TE_B
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE_B;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_FUNCTIONAL_V |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_timer_ms (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h3E7;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or |(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = ^(vect);
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_BEHAVIORAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:10:35 12/16/2015
// Design Name: uart2_tx
// Module Name: H:/Firmware/font5_base_new/font5_base/font5-firmware/uart2_tb.v
// Project Name: font5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart2_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart2_tb;
// Inputs
reg reset;
reg clk;
reg ld_tx_data;
reg [7:0] tx_data;
reg tx_enable;
// Outputs
wire tx_out;
wire tx_empty;
// Instantiate the Unit Under Test (UUT)
uart2_tx uut (
.reset(reset),
.clk(clk),
.ld_tx_data(ld_tx_data),
.tx_data(tx_data),
.tx_enable(tx_enable),
.tx_out(tx_out),
.tx_empty(tx_empty)
);
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
ld_tx_data = 0;
tx_data = 0;
tx_enable = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.12.beta1 (build 32746, 2013-12-02)
//
// On Wed Mar 5 21:17:23 CST 2014
//
//
// Ports:
// Name I/O size props
// read O 16
// CLK I 1 clock
// RST_N I 1 reset
// write_x I 16 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSOP1(CLK,
RST_N,
write_x,
read);
input CLK;
input RST_N;
// action method write
input [15 : 0] write_x;
// value method read
output [15 : 0] read;
// signals for module outputs
wire [15 : 0] read;
// register taps_0
reg [15 : 0] taps_0;
wire [15 : 0] taps_0$D_IN;
wire taps_0$EN;
// register taps_1
reg [15 : 0] taps_1;
wire [15 : 0] taps_1$D_IN;
wire taps_1$EN;
// register taps_2
reg [15 : 0] taps_2;
wire [15 : 0] taps_2$D_IN;
wire taps_2$EN;
// register taps_3
reg [15 : 0] taps_3;
wire [15 : 0] taps_3$D_IN;
wire taps_3$EN;
// register y
reg [31 : 0] y;
wire [31 : 0] y$D_IN;
wire y$EN;
// remaining internal signals
wire [31 : 0] SEXT_taps_0_BITS_25_TO_0_CONCAT_0_PLUS_SEXT_ta_ETC___d14,
SEXT_taps_0__q3,
SEXT_taps_1__q4,
SEXT_taps_2__q5,
SEXT_taps_3__q6,
SEXT_y_BITS_31_TO_8__q2;
wire [23 : 0] y_BITS_31_TO_8__q1;
// value method read
assign read = SEXT_y_BITS_31_TO_8__q2[15:0] ;
// register taps_0
assign taps_0$D_IN = write_x ;
assign taps_0$EN = 1'd1 ;
// register taps_1
assign taps_1$D_IN = taps_0 ;
assign taps_1$EN = 1'd1 ;
// register taps_2
assign taps_2$D_IN = taps_1 ;
assign taps_2$EN = 1'd1 ;
// register taps_3
assign taps_3$D_IN = taps_2 ;
assign taps_3$EN = 1'd1 ;
// register y
assign y$D_IN =
SEXT_taps_0_BITS_25_TO_0_CONCAT_0_PLUS_SEXT_ta_ETC___d14 +
{ SEXT_taps_3__q6[25:0], 6'd0 } ;
assign y$EN = 1'd1 ;
// remaining internal signals
assign SEXT_taps_0_BITS_25_TO_0_CONCAT_0_PLUS_SEXT_ta_ETC___d14 =
{ SEXT_taps_0__q3[25:0], 6'd0 } +
{ SEXT_taps_1__q4[25:0], 6'd0 } +
{ SEXT_taps_2__q5[25:0], 6'd0 } ;
assign SEXT_taps_0__q3 = { {16{taps_0[15]}}, taps_0 } ;
assign SEXT_taps_1__q4 = { {16{taps_1[15]}}, taps_1 } ;
assign SEXT_taps_2__q5 = { {16{taps_2[15]}}, taps_2 } ;
assign SEXT_taps_3__q6 = { {16{taps_3[15]}}, taps_3 } ;
assign SEXT_y_BITS_31_TO_8__q2 =
{ {8{y_BITS_31_TO_8__q1[23]}}, y_BITS_31_TO_8__q1 } ;
assign y_BITS_31_TO_8__q1 = y[31:8] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
taps_0 <= `BSV_ASSIGNMENT_DELAY 16'd0;
taps_1 <= `BSV_ASSIGNMENT_DELAY 16'd0;
taps_2 <= `BSV_ASSIGNMENT_DELAY 16'd0;
taps_3 <= `BSV_ASSIGNMENT_DELAY 16'd0;
y <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (taps_0$EN) taps_0 <= `BSV_ASSIGNMENT_DELAY taps_0$D_IN;
if (taps_1$EN) taps_1 <= `BSV_ASSIGNMENT_DELAY taps_1$D_IN;
if (taps_2$EN) taps_2 <= `BSV_ASSIGNMENT_DELAY taps_2$D_IN;
if (taps_3$EN) taps_3 <= `BSV_ASSIGNMENT_DELAY taps_3$D_IN;
if (y$EN) y <= `BSV_ASSIGNMENT_DELAY y$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
taps_0 = 16'hAAAA;
taps_1 = 16'hAAAA;
taps_2 = 16'hAAAA;
taps_3 = 16'hAAAA;
y = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkSOP1
|